Boot log: qemu_arm64-virt-gicv3
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
- Errors: 0
1 10:10:28.217233 lava-dispatcher, installed at version: 2023.01
2 10:10:28.217471 start: 0 validate
3 10:10:28.217595 Start time: 2023-06-10 10:10:28.217587+00:00 (UTC)
4 10:10:28.218788 Validating that http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig/gcc-10/kernel/Image exists
5 10:10:28.560218 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz exists
6 10:10:28.731191 cmd: ['docker', 'pull', 'kernelci/qemu']
7 10:10:28.731447 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 10:10:28.892732 >> Using default tag: latest
9 10:10:30.126218 >> latest: Pulling from kernelci/qemu
10 10:10:30.158381 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
11 10:10:30.158634 >> Status: Image is up to date for kernelci/qemu:latest
12 10:10:30.191635 >> docker.io/kernelci/qemu:latest
13 10:10:30.195458 Returned 0 in 1 seconds
14 10:10:30.332250 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 10:10:30.332546 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 10:10:32.027863 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 10:10:32.028163 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 10:10:33.132670 Returned 0 in 2 seconds
19 10:10:33.233839 validate duration: 5.02
21 10:10:33.234263 start: 1 deployimages (timeout 00:03:00) [common]
22 10:10:33.234395 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 10:10:33.234775 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst
24 10:10:33.234969 makedir: /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin
25 10:10:33.235122 makedir: /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/tests
26 10:10:33.235274 makedir: /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/results
27 10:10:33.235424 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-add-keys
28 10:10:33.235621 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-add-sources
29 10:10:33.235797 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-background-process-start
30 10:10:33.235976 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-background-process-stop
31 10:10:33.236147 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-common-functions
32 10:10:33.236314 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-echo-ipv4
33 10:10:33.236487 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-install-packages
34 10:10:33.236663 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-installed-packages
35 10:10:33.236827 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-os-build
36 10:10:33.237000 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-probe-channel
37 10:10:33.237176 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-probe-ip
38 10:10:33.237353 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-target-ip
39 10:10:33.237529 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-target-mac
40 10:10:33.237717 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-target-storage
41 10:10:33.237898 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-test-case
42 10:10:33.238074 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-test-event
43 10:10:33.238246 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-test-feedback
44 10:10:33.238417 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-test-raise
45 10:10:33.238592 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-test-reference
46 10:10:33.238766 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-test-runner
47 10:10:33.238936 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-test-set
48 10:10:33.239115 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-test-shell
49 10:10:33.239294 Updating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-install-packages (oe)
50 10:10:33.239534 Updating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/bin/lava-installed-packages (oe)
51 10:10:33.239717 Creating /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/environment
52 10:10:33.239871 LAVA metadata
53 10:10:33.239971 - LAVA_JOB_ID=592458
54 10:10:33.240065 - LAVA_DISPATCHER_IP=172.27.0.2
55 10:10:33.240228 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 10:10:33.240329 skipped lava-vland-overlay
57 10:10:33.240447 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 10:10:33.240565 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 10:10:33.240659 skipped lava-multinode-overlay
60 10:10:33.240768 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 10:10:33.240886 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 10:10:33.241007 Loading test definitions
63 10:10:33.241146 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 10:10:33.241256 Using /lava-592458 at stage 0
65 10:10:33.241734 uuid=592458_1.1.3.1 testdef=None
66 10:10:33.241865 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 10:10:33.241985 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 10:10:33.242676 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 10:10:33.243030 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 10:10:33.243861 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 10:10:33.244201 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 10:10:33.244984 runner path: /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/0/tests/0_timesync-off test_uuid 592458_1.1.3.1
75 10:10:33.245191 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 10:10:33.245536 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 10:10:33.245637 Using /lava-592458 at stage 0
79 10:10:33.245792 Fetching tests from https://github.com/kernelci/test-definitions.git
80 10:10:33.245907 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/0/tests/1_kselftest-arm64_qemu'
81 10:10:36.050206 Running '/usr/bin/git checkout kernelci.org
82 10:10:36.126719 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 10:10:36.127864 uuid=592458_1.1.3.5 testdef=None
84 10:10:36.128107 end: 1.1.3.5 git-repo-action (duration 00:00:03) [common]
86 10:10:36.128592 start: 1.1.3.6 test-overlay (timeout 00:02:57) [common]
87 10:10:36.130193 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 10:10:36.130678 start: 1.1.3.7 test-install-overlay (timeout 00:02:57) [common]
90 10:10:36.132847 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 10:10:36.133363 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:57) [common]
93 10:10:36.135454 runner path: /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/0/tests/1_kselftest-arm64_qemu test_uuid 592458_1.1.3.5
94 10:10:36.135634 BOARD='qemu_arm64-virt-gicv3'
95 10:10:36.135761 BRANCH='cip'
96 10:10:36.135879 SKIPFILE='/dev/null'
97 10:10:36.135996 SKIP_INSTALL='True'
98 10:10:36.136112 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig/gcc-10/kselftest.tar.xz'
99 10:10:36.136234 TST_CASENAME=''
100 10:10:36.136349 TST_CMDFILES='arm64'
101 10:10:36.136621 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 10:10:36.137077 Creating lava-test-runner.conf files
104 10:10:36.137206 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/592458/lava-overlay-pl_imlst/lava-592458/0 for stage 0
105 10:10:36.137384 - 0_timesync-off
106 10:10:36.137524 - 1_kselftest-arm64_qemu
107 10:10:36.137713 end: 1.1.3 test-definition (duration 00:00:03) [common]
108 10:10:36.137881 start: 1.1.4 compress-overlay (timeout 00:02:57) [common]
109 10:10:44.900496 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 10:10:44.900690 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:48) [common]
111 10:10:44.900783 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 10:10:44.900895 end: 1.1 lava-overlay (duration 00:00:12) [common]
113 10:10:44.900985 start: 1.2 apply-overlay-guest (timeout 00:02:48) [common]
114 10:10:44.901063 Overlay: /var/lib/lava/dispatcher/tmp/592458/compress-overlay-dpvag_7e/overlay-1.1.4.tar.gz
115 10:10:59.933736 end: 1.2 apply-overlay-guest (duration 00:00:15) [common]
117 10:10:59.934491 start: 1.3 deploy-device-env (timeout 00:02:33) [common]
118 10:10:59.934661 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 10:10:59.934828 start: 1.4 download-retry (timeout 00:02:33) [common]
120 10:10:59.934999 start: 1.4.1 http-download (timeout 00:02:33) [common]
121 10:10:59.935288 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig/gcc-10/kernel/Image
122 10:10:59.935424 saving as /var/lib/lava/dispatcher/tmp/592458/deployimages-om5uhj3c/kernel/Image
123 10:10:59.935546 total size: 37358080 (35MB)
124 10:10:59.935663 No compression specified
125 10:11:00.275953 progress 0% (0MB)
126 10:11:01.289097 progress 5% (1MB)
127 10:11:01.478133 progress 10% (3MB)
128 10:11:01.642753 progress 15% (5MB)
129 10:11:01.816183 progress 20% (7MB)
130 10:11:02.157653 progress 25% (8MB)
131 10:11:02.323746 progress 30% (10MB)
132 10:11:02.494677 progress 35% (12MB)
133 10:11:02.665619 progress 40% (14MB)
134 10:11:02.836398 progress 45% (16MB)
135 10:11:03.006961 progress 50% (17MB)
136 10:11:03.178566 progress 55% (19MB)
137 10:11:03.348835 progress 60% (21MB)
138 10:11:03.519141 progress 65% (23MB)
139 10:11:03.689234 progress 70% (24MB)
140 10:11:03.859424 progress 75% (26MB)
141 10:11:04.029262 progress 80% (28MB)
142 10:11:04.201183 progress 85% (30MB)
143 10:11:04.441770 progress 90% (32MB)
144 10:11:04.610684 progress 95% (33MB)
145 10:11:04.705940 progress 100% (35MB)
146 10:11:04.706210 35MB downloaded in 4.77s (7.47MB/s)
147 10:11:04.706532 end: 1.4.1 http-download (duration 00:00:05) [common]
149 10:11:04.707090 end: 1.4 download-retry (duration 00:00:05) [common]
150 10:11:04.707285 start: 1.5 download-retry (timeout 00:02:29) [common]
151 10:11:04.707473 start: 1.5.1 http-download (timeout 00:02:29) [common]
152 10:11:04.707732 Not decompressing ramdisk as can be used compressed.
153 10:11:04.707923 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz
154 10:11:04.708067 saving as /var/lib/lava/dispatcher/tmp/592458/deployimages-om5uhj3c/ramdisk/rootfs.cpio.gz
155 10:11:04.708219 total size: 88976554 (84MB)
156 10:11:04.708365 No compression specified
157 10:11:04.879093 progress 0% (0MB)
158 10:11:05.230916 progress 5% (4MB)
159 10:11:05.742756 progress 10% (8MB)
160 10:11:06.405782 progress 15% (12MB)
161 10:11:06.914136 progress 20% (17MB)
162 10:11:07.421319 progress 25% (21MB)
163 10:11:07.926253 progress 30% (25MB)
164 10:11:08.431613 progress 35% (29MB)
165 10:11:08.787411 progress 40% (33MB)
166 10:11:09.300971 progress 45% (38MB)
167 10:11:09.805909 progress 50% (42MB)
168 10:11:10.309400 progress 55% (46MB)
169 10:11:10.800752 progress 60% (50MB)
170 10:11:11.164536 progress 65% (55MB)
171 10:11:11.668838 progress 70% (59MB)
172 10:11:12.171765 progress 75% (63MB)
173 10:11:12.673639 progress 80% (67MB)
174 10:11:13.164352 progress 85% (72MB)
175 10:11:13.533219 progress 90% (76MB)
176 10:11:14.037259 progress 95% (80MB)
177 10:11:14.535151 progress 100% (84MB)
178 10:11:14.535562 84MB downloaded in 9.83s (8.63MB/s)
179 10:11:14.535870 end: 1.5.1 http-download (duration 00:00:10) [common]
181 10:11:14.536422 end: 1.5 download-retry (duration 00:00:10) [common]
182 10:11:14.536608 end: 1 deployimages (duration 00:00:41) [common]
183 10:11:14.536804 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 10:11:14.536991 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 10:11:14.537177 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 10:11:14.537582 Extending command line for qcow2 test overlay
187 10:11:14.538258 Pulling docker image
188 10:11:14.538438 cmd: ['docker', 'pull', 'kernelci/qemu']
189 10:11:14.538598 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 10:11:14.702745 >> Using default tag: latest
191 10:11:15.822737 >> latest: Pulling from kernelci/qemu
192 10:11:15.854720 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
193 10:11:15.854976 >> Status: Image is up to date for kernelci/qemu:latest
194 10:11:15.888012 >> docker.io/kernelci/qemu:latest
195 10:11:15.891124 Returned 0 in 1 seconds
196 10:11:16.027788 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-592458-2.1.1-sta8tig9s0 --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/592458/deployimages-om5uhj3c/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/592458/deployimages-om5uhj3c/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/592458/apply-overlay-guest-gawj13tq/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 10:11:16.147721 started a shell command
198 10:11:16.148404 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 10:11:16.148640 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 10:11:16.148852 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 10:11:16.149053 Setting prompt string to ['Linux version [0-9]']
202 10:11:16.149218 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 10:11:20.205317 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 10:11:20.205846 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j19309-arm64-gcc-10-defconfig-t8srs) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 10 09:57:04 UTC 2023
205 10:11:20.205967 [ 0.000000] random: crng init done
206 10:11:20.206081 [ 0.000000] Machine model: linux,dummy-virt
207 10:11:20.206178 [ 0.000000] efi: UEFI not found.
208 10:11:20.206520 start: 2.2.1 login-action (timeout 00:04:54) [common]
209 10:11:20.206647 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
210 10:11:20.206799 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
211 10:11:20.206921 Using line separator: #'\n'#
212 10:11:20.207014 No login prompt set.
213 10:11:20.207113 Parsing kernel messages
214 10:11:20.207203 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
215 10:11:20.207380 [login-action] Waiting for messages, (timeout 00:04:54)
216 10:11:20.208355 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
217 10:11:20.208465 [ 0.000000] printk: bootconsole [pl11] enabled
218 10:11:20.209768 [ 0.000000] NUMA: No NUMA configuration found
219 10:11:20.210322 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 10:11:20.210879 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf2a00-0x7fdf4fff]
221 10:11:20.213089 [ 0.000000] Zone ranges:
222 10:11:20.213932 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 10:11:20.214053 [ 0.000000] DMA32 empty
224 10:11:20.214172 [ 0.000000] Normal empty
225 10:11:20.214265 [ 0.000000] Movable zone start for each node
226 10:11:20.214374 [ 0.000000] Early memory node ranges
227 10:11:20.214478 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 10:11:20.214807 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 10:11:20.230110 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 10:11:20.231220 [ 0.000000] psci: probing for conduit method from DT.
231 10:11:20.231476 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 10:11:20.231628 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 10:11:20.231817 [ 0.000000] psci: Trusted OS migration not required
234 10:11:20.231974 [ 0.000000] psci: SMC Calling Convention v1.0
235 10:11:20.234323 [ 0.000000] percpu: Embedded 20 pages/cpu s44840 r8192 d28888 u81920
236 10:11:20.234745 [ 0.000000] pcpu-alloc: s44840 r8192 d28888 u81920 alloc=20*4096
237 10:11:20.235070 [ 0.000000] pcpu-alloc: [0] 0
238 10:11:20.236587 [ 0.000000] Detected PIPT I-cache on CPU0
239 10:11:20.241980 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 10:11:20.242423 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 10:11:20.242802 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 10:11:20.243024 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 10:11:20.243172 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 10:11:20.243332 [ 0.000000] CPU features: detected: Spectre-v4
245 10:11:20.247006 [ 0.000000] alternatives: applying boot alternatives
246 10:11:20.249915 [ 0.000000] Fallback order for Node 0: 0
247 10:11:20.250314 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 10:11:20.250421 [ 0.000000] Policy zone: DMA
249 10:11:20.250746 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 10:11:20.253280 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 10:11:20.255752 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 10:11:20.256131 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 10:11:20.256470 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 10:11:20.265956 <6>[ 0.000000] Memory: 870672K/1048576K available (16192K kernel code, 3714K rwdata, 8860K rodata, 7552K init, 609K bss, 145136K reserved, 32768K cma-reserved)
255 10:11:20.271968 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 10:11:20.278785 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 10:11:20.279011 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 10:11:20.279130 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 10:11:20.279223 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 10:11:20.279313 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 10:11:20.279637 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 10:11:20.279746 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 10:11:20.280630 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 10:11:20.287435 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 10:11:20.287902 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 10:11:20.289291 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 10:11:20.289431 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 10:11:20.290267 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 10:11:20.294375 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 10:11:20.295308 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @42830000 (indirect, esz 8, psz 64K, shr 1)
271 10:11:20.295687 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @42840000 (flat, esz 8, psz 64K, shr 1)
272 10:11:20.296423 <6>[ 0.000000] GICv3: using LPI property table @0x0000000042850000
273 10:11:20.296925 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000042860000
274 10:11:20.298327 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 10:11:20.306374 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 10:11:20.306929 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 10:11:20.307611 <6>[ 0.000078] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 10:11:20.324801 <6>[ 0.014750] Console: colour dummy device 80x25
279 10:11:20.328843 <6>[ 0.020811] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 10:11:20.329079 <6>[ 0.021709] pid_max: default: 32768 minimum: 301
281 10:11:20.330382 <6>[ 0.023158] LSM: Security Framework initializing
282 10:11:20.335852 <6>[ 0.028278] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 10:11:20.336017 <6>[ 0.028610] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 10:11:20.371162 <4>[ 0.063789] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 10:11:20.377296 <6>[ 0.069808] cblist_init_generic: Setting adjustable number of callback queues.
286 10:11:20.377514 <6>[ 0.070145] cblist_init_generic: Setting shift to 0 and lim to 1.
287 10:11:20.378162 <6>[ 0.070706] cblist_init_generic: Setting shift to 0 and lim to 1.
288 10:11:20.379881 <6>[ 0.072389] rcu: Hierarchical SRCU implementation.
289 10:11:20.380129 <6>[ 0.072647] rcu: Max phase no-delay instances is 1000.
290 10:11:20.385003 <6>[ 0.077453] Platform MSI: its@8080000 domain created
291 10:11:20.385591 <6>[ 0.078117] PCI/MSI: /intc@8000000/its@8080000 domain created
292 10:11:20.386064 <6>[ 0.078763] fsl-mc MSI: its@8080000 domain created
293 10:11:20.389575 <6>[ 0.082132] EFI services will not be available.
294 10:11:20.390270 <6>[ 0.083011] smp: Bringing up secondary CPUs ...
295 10:11:20.390614 <6>[ 0.083243] smp: Brought up 1 node, 1 CPU
296 10:11:20.390737 <6>[ 0.083398] SMP: Total of 1 processors activated.
297 10:11:20.391079 <6>[ 0.083755] CPU features: detected: Branch Target Identification
298 10:11:20.391426 <6>[ 0.083979] CPU features: detected: 32-bit EL0 Support
299 10:11:20.391542 <6>[ 0.084155] CPU features: detected: 32-bit EL1 Support
300 10:11:20.391648 <6>[ 0.084321] CPU features: detected: ARMv8.4 Translation Table Level
301 10:11:20.391984 <6>[ 0.084516] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 10:11:20.392571 <6>[ 0.084794] CPU features: detected: Common not Private translations
303 10:11:20.392694 <6>[ 0.085366] CPU features: detected: CRC32 instructions
304 10:11:20.392798 <6>[ 0.085537] CPU features: detected: E0PD
305 10:11:20.393141 <6>[ 0.085707] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 10:11:20.393270 <6>[ 0.085891] CPU features: detected: RCpc load-acquire (LDAPR)
307 10:11:20.393379 <6>[ 0.086054] CPU features: detected: LSE atomic instructions
308 10:11:20.393483 <6>[ 0.086203] CPU features: detected: Privileged Access Never
309 10:11:20.393872 <6>[ 0.086364] CPU features: detected: RAS Extension Support
310 10:11:20.394059 <6>[ 0.086525] CPU features: detected: Random Number Generator
311 10:11:20.394326 <6>[ 0.086676] CPU features: detected: Speculation barrier (SB)
312 10:11:20.394524 <6>[ 0.086858] CPU features: detected: Stage-2 Force Write-Back
313 10:11:20.394823 <6>[ 0.087033] CPU features: detected: TLB range maintenance instructions
314 10:11:20.395019 <6>[ 0.087267] CPU features: detected: Scalable Matrix Extension
315 10:11:20.395176 <6>[ 0.087422] CPU features: detected: FA64
316 10:11:20.395322 <6>[ 0.087529] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 10:11:20.395502 <6>[ 0.087689] CPU features: detected: Scalable Vector Extension
318 10:11:20.407257 <6>[ 0.097171] SVE: maximum available vector length 256 bytes per vector
319 10:11:20.407736 <6>[ 0.100244] SVE: default vector length 64 bytes per vector
320 10:11:20.409861 <6>[ 0.102198] SME: minimum available vector length 16 bytes per vector
321 10:11:20.409989 <6>[ 0.102423] SME: maximum available vector length 256 bytes per vector
322 10:11:20.410097 <6>[ 0.102623] SME: default vector length 32 bytes per vector
323 10:11:20.410295 <6>[ 0.103053] CPU: All CPU(s) started at EL1
324 10:11:20.410658 <6>[ 0.103416] alternatives: applying system-wide alternatives
325 10:11:20.463841 <6>[ 0.156272] devtmpfs: initialized
326 10:11:20.484943 <6>[ 0.177149] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 10:11:20.485395 <6>[ 0.178041] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 10:11:20.491619 <6>[ 0.184095] pinctrl core: initialized pinctrl subsystem
329 10:11:20.503299 <6>[ 0.195890] DMI not present or invalid.
330 10:11:20.513108 <6>[ 0.205714] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 10:11:20.525464 <6>[ 0.217643] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 10:11:20.525921 <6>[ 0.218490] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 10:11:20.526555 <6>[ 0.219010] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 10:11:20.527028 <6>[ 0.219570] audit: initializing netlink subsys (disabled)
335 10:11:20.533678 <5>[ 0.226104] audit: type=2000 audit(0.184:1): state=initialized audit_enabled=0 res=1
336 10:11:20.535420 <6>[ 0.227830] thermal_sys: Registered thermal governor 'step_wise'
337 10:11:20.536064 <6>[ 0.227905] thermal_sys: Registered thermal governor 'power_allocator'
338 10:11:20.536169 <6>[ 0.228545] cpuidle: using governor menu
339 10:11:20.537837 <6>[ 0.230349] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
340 10:11:20.538316 <6>[ 0.231004] ASID allocator initialised with 65536 entries
341 10:11:20.544453 <6>[ 0.237220] Serial: AMBA PL011 UART driver
342 10:11:20.594223 <6>[ 0.286533] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
343 10:11:20.595753 <6>[ 0.288358] printk: console [ttyAMA0] enabled
344 10:11:20.596254 <6>[ 0.288358] printk: console [ttyAMA0] enabled
345 10:11:20.596475 <6>[ 0.288924] printk: bootconsole [pl11] disabled
346 10:11:20.596650 <6>[ 0.288924] printk: bootconsole [pl11] disabled
347 10:11:20.607317 <6>[ 0.300011] KASLR enabled
348 10:11:20.638490 <6>[ 0.330924] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
349 10:11:20.638710 <6>[ 0.331156] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
350 10:11:20.638826 <6>[ 0.331369] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
351 10:11:20.639174 <6>[ 0.331666] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
352 10:11:20.639277 <6>[ 0.331847] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
353 10:11:20.639385 <6>[ 0.332024] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
354 10:11:20.639494 <6>[ 0.332217] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
355 10:11:20.639821 <6>[ 0.332417] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
356 10:11:20.651100 <6>[ 0.343834] ACPI: Interpreter disabled.
357 10:11:20.659588 <6>[ 0.352293] iommu: Default domain type: Translated
358 10:11:20.659992 <6>[ 0.352475] iommu: DMA domain TLB invalidation policy: strict mode
359 10:11:20.661470 <5>[ 0.354197] SCSI subsystem initialized
360 10:11:20.662336 <7>[ 0.355094] libata version 3.00 loaded.
361 10:11:20.663975 <6>[ 0.356491] usbcore: registered new interface driver usbfs
362 10:11:20.664407 <6>[ 0.356911] usbcore: registered new interface driver hub
363 10:11:20.664850 <6>[ 0.357351] usbcore: registered new device driver usb
364 10:11:20.667899 <6>[ 0.360416] pps_core: LinuxPPS API ver. 1 registered
365 10:11:20.668081 <6>[ 0.360588] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
366 10:11:20.668240 <6>[ 0.361014] PTP clock support registered
367 10:11:20.668848 <6>[ 0.361641] EDAC MC: Ver: 3.0.0
368 10:11:20.674334 <6>[ 0.367089] FPGA manager framework
369 10:11:20.675351 <6>[ 0.367899] Advanced Linux Sound Architecture Driver Initialized.
370 10:11:20.684608 <6>[ 0.377373] vgaarb: loaded
371 10:11:20.688547 <6>[ 0.381280] clocksource: Switched to clocksource arch_sys_counter
372 10:11:20.689959 <5>[ 0.382489] VFS: Disk quotas dquot_6.6.0
373 10:11:20.690081 <6>[ 0.382784] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
374 10:11:20.691387 <6>[ 0.384169] pnp: PnP ACPI: disabled
375 10:11:20.711534 <6>[ 0.404161] NET: Registered PF_INET protocol family
376 10:11:20.713792 <6>[ 0.406340] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
377 10:11:20.718719 <6>[ 0.411144] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
378 10:11:20.718976 <6>[ 0.411473] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
379 10:11:20.719222 <6>[ 0.411753] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
380 10:11:20.719709 <6>[ 0.412167] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
381 10:11:20.720203 <6>[ 0.412719] TCP: Hash tables configured (established 8192 bind 8192)
382 10:11:20.721418 <6>[ 0.413991] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
383 10:11:20.721863 <6>[ 0.414373] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
384 10:11:20.723057 <6>[ 0.415539] NET: Registered PF_UNIX/PF_LOCAL protocol family
385 10:11:20.725805 <6>[ 0.418296] RPC: Registered named UNIX socket transport module.
386 10:11:20.726008 <6>[ 0.418533] RPC: Registered udp transport module.
387 10:11:20.726174 <6>[ 0.418700] RPC: Registered tcp transport module.
388 10:11:20.726323 <6>[ 0.418829] RPC: Registered tcp NFSv4.1 backchannel transport module.
389 10:11:20.726470 <6>[ 0.419100] PCI: CLS 0 bytes, default 64
390 10:11:20.730341 <6>[ 0.423121] Unpacking initramfs...
391 10:11:20.740968 <6>[ 0.433437] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
392 10:11:20.741508 <6>[ 0.434270] kvm [1]: HYP mode not available
393 10:11:20.746694 <5>[ 0.439444] Initialise system trusted keyrings
394 10:11:20.752820 <6>[ 0.445499] workingset: timestamp_bits=42 max_order=18 bucket_order=0
395 10:11:20.792662 <6>[ 0.485316] squashfs: version 4.0 (2009/01/31) Phillip Lougher
396 10:11:20.798272 <5>[ 0.490977] NFS: Registering the id_resolver key type
397 10:11:20.798727 <5>[ 0.491475] Key type id_resolver registered
398 10:11:20.799090 <5>[ 0.491652] Key type id_legacy registered
399 10:11:20.799692 <6>[ 0.492193] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
400 10:11:20.799817 <6>[ 0.492432] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
401 10:11:20.804735 <6>[ 0.497471] 9p: Installing v9fs 9p2000 file system support
402 10:11:20.870057 <5>[ 0.562734] Key type asymmetric registered
403 10:11:20.870517 <5>[ 0.562960] Asymmetric key parser 'x509' registered
404 10:11:20.870878 <6>[ 0.563494] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
405 10:11:20.871221 <6>[ 0.563912] io scheduler mq-deadline registered
406 10:11:20.871555 <6>[ 0.564118] io scheduler kyber registered
407 10:11:20.936956 <6>[ 0.629508] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
408 10:11:20.947761 <6>[ 0.640238] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
409 10:11:20.953054 <6>[ 0.645369] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
410 10:11:20.953599 <6>[ 0.646168] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
411 10:11:20.953840 <6>[ 0.646476] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
412 10:11:20.954655 <4>[ 0.647196] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
413 10:11:20.955735 <6>[ 0.647896] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
414 10:11:20.961406 <6>[ 0.653958] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
415 10:11:20.961899 <6>[ 0.654409] pci_bus 0000:00: root bus resource [bus 00-ff]
416 10:11:20.962124 <6>[ 0.654689] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
417 10:11:20.962321 <6>[ 0.654952] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
418 10:11:20.962495 <6>[ 0.655152] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
419 10:11:20.964237 <6>[ 0.656720] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
420 10:11:20.971607 <6>[ 0.664291] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
421 10:11:20.972359 <6>[ 0.664719] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
422 10:11:20.972537 <6>[ 0.664936] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
423 10:11:20.976764 <6>[ 0.669117] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
424 10:11:20.976941 <6>[ 0.669400] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
425 10:11:20.977391 <6>[ 0.670037] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
426 10:11:20.977608 <6>[ 0.670215] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
427 10:11:20.977818 <6>[ 0.670377] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
428 10:11:20.977951 <6>[ 0.670545] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
429 10:11:20.984948 <6>[ 0.677414] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
430 10:11:20.985282 <6>[ 0.677899] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
431 10:11:20.985808 <6>[ 0.678256] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
432 10:11:20.986007 <6>[ 0.678512] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
433 10:11:20.986188 <6>[ 0.678781] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
434 10:11:20.986369 <6>[ 0.679023] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
435 10:11:20.986555 <6>[ 0.679243] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
436 10:11:21.001592 <6>[ 0.694305] EINJ: ACPI disabled.
437 10:11:21.090578 <6>[ 0.782940] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
438 10:11:21.097431 <6>[ 0.789938] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
439 10:11:21.129895 <6>[ 0.822319] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
440 10:11:21.145157 <6>[ 0.837884] SuperH (H)SCI(F) driver initialized
441 10:11:21.146580 <6>[ 0.839317] msm_serial: driver initialized
442 10:11:21.155325 <4>[ 0.848023] cacheinfo: Unable to detect cache hierarchy for CPU 0
443 10:11:21.193307 <6>[ 0.885903] loop: module loaded
444 10:11:21.194633 <6>[ 0.887146] virtio_blk virtio1: 1/0/0 default/read/poll queues
445 10:11:21.212168 <5>[ 0.904785] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
446 10:11:21.251718 <6>[ 0.944039] megasas: 07.719.03.00-rc1
447 10:11:21.266329 <5>[ 0.958683] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
448 10:11:21.267870 <6>[ 0.960342] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
449 10:11:21.272659 <6>[ 0.965121] Intel/Sharp Extended Query Table at 0x0031
450 10:11:21.273381 <6>[ 0.965947] Using buffer write method
451 10:11:21.273850 <7>[ 0.966398] erase region 0: offset=0x0,size=0x40000,blocks=256
452 10:11:21.274346 <5>[ 0.966762] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
453 10:11:21.275016 <6>[ 0.967478] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
454 10:11:21.275145 <6>[ 0.967826] Intel/Sharp Extended Query Table at 0x0031
455 10:11:21.275737 <6>[ 0.968534] Using buffer write method
456 10:11:21.276236 <7>[ 0.968680] erase region 0: offset=0x0,size=0x40000,blocks=256
457 10:11:21.276399 <5>[ 0.968907] Concatenating MTD devices:
458 10:11:21.280351 <5>[ 0.973141] (0): \"0.flash\"
459 10:11:21.280832 <5>[ 0.973228] (1): \"0.flash\"
460 10:11:21.280980 <5>[ 0.973328] into device \"0.flash\"
461 10:11:26.045422 <6>[ 5.737950] Freeing initrd memory: 86888K
462 10:11:26.158192 <6>[ 5.850833] tun: Universal TUN/TAP device driver, 1.6
463 10:11:26.167739 <6>[ 5.860454] thunder_xcv, ver 1.0
464 10:11:26.168260 <6>[ 5.860670] thunder_bgx, ver 1.0
465 10:11:26.168431 <6>[ 5.860908] nicpf, ver 1.0
466 10:11:26.171878 <6>[ 5.864431] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
467 10:11:26.172071 <6>[ 5.864660] hns3: Copyright (c) 2017 Huawei Corporation.
468 10:11:26.172498 <6>[ 5.865134] hclge is initializing
469 10:11:26.172726 <6>[ 5.865386] e1000: Intel(R) PRO/1000 Network Driver
470 10:11:26.172943 <6>[ 5.865545] e1000: Copyright (c) 1999-2006 Intel Corporation.
471 10:11:26.173179 <6>[ 5.865880] e1000e: Intel(R) PRO/1000 Network Driver
472 10:11:26.173361 <6>[ 5.866034] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
473 10:11:26.173733 <6>[ 5.866398] igb: Intel(R) Gigabit Ethernet Network Driver
474 10:11:26.173864 <6>[ 5.866550] igb: Copyright (c) 2007-2014 Intel Corporation.
475 10:11:26.174205 <6>[ 5.866902] igbvf: Intel(R) Gigabit Virtual Function Network Driver
476 10:11:26.174441 <6>[ 5.867114] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
477 10:11:26.175612 <6>[ 5.868168] sky2: driver version 1.30
478 10:11:26.178645 <6>[ 5.871183] VFIO - User Level meta-driver version: 0.3
479 10:11:26.187947 <6>[ 5.880437] usbcore: registered new interface driver usb-storage
480 10:11:26.197265 <6>[ 5.889756] rtc-pl031 9010000.pl031: registered as rtc0
481 10:11:26.198341 <6>[ 5.890517] rtc-pl031 9010000.pl031: setting system clock to 2023-06-10T10:11:26 UTC (1686391886)
482 10:11:26.199937 <6>[ 5.892678] i2c_dev: i2c /dev entries driver
483 10:11:26.216899 <6>[ 5.909585] sdhci: Secure Digital Host Controller Interface driver
484 10:11:26.217378 <6>[ 5.909721] sdhci: Copyright(c) Pierre Ossman
485 10:11:26.219164 <6>[ 5.911717] Synopsys Designware Multimedia Card Interface Driver
486 10:11:26.221897 <6>[ 5.914373] sdhci-pltfm: SDHCI platform and OF driver helper
487 10:11:26.227116 <6>[ 5.919556] ledtrig-cpu: registered to indicate activity on CPUs
488 10:11:26.233331 <6>[ 5.925689] usbcore: registered new interface driver usbhid
489 10:11:26.233594 <6>[ 5.925911] usbhid: USB HID core driver
490 10:11:26.250784 <6>[ 5.943237] NET: Registered PF_PACKET protocol family
491 10:11:26.251835 <6>[ 5.944345] 9pnet: Installing 9P2000 support
492 10:11:26.252065 <5>[ 5.944725] Key type dns_resolver registered
493 10:11:26.253545 <6>[ 5.946086] registered taskstats version 1
494 10:11:26.253832 <5>[ 5.946479] Loading compiled-in X.509 certificates
495 10:11:26.275241 <6>[ 5.967707] input: gpio-keys as /devices/platform/gpio-keys/input/input0
496 10:11:26.282445 <6>[ 5.974921] ALSA device list:
497 10:11:26.282638 <6>[ 5.975110] No soundcards found.
498 10:11:26.285309 <6>[ 5.977820] uart-pl011 9000000.pl011: no DMA platform data
499 10:11:26.339205 <6>[ 6.031871] Freeing unused kernel memory: 7552K
500 10:11:26.340080 <6>[ 6.032845] Run /init as init process
501 10:11:26.340433 <7>[ 6.032977] with arguments:
502 10:11:26.340541 <7>[ 6.033223] /init
503 10:11:26.340646 <7>[ 6.033317] verbose
504 10:11:26.340752 <7>[ 6.033436] with environment:
505 10:11:26.340860 <7>[ 6.033586] HOME=/
506 10:11:26.340963 <7>[ 6.033715] TERM=linux
507 10:11:26.475412 <30>[ 6.167356] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
508 10:11:26.476263 <31>[ 6.168776] systemd[1]: No virtualization found in DMI
509 10:11:26.477471 <31>[ 6.169981] systemd[1]: UML virtualization not found in /proc/cpuinfo.
510 10:11:26.477676 <31>[ 6.170290] systemd[1]: No virtualization found in CPUID
511 10:11:26.478144 <31>[ 6.170581] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
512 10:11:26.479134 <31>[ 6.171669] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
513 10:11:26.479349 <31>[ 6.172075] systemd[1]: Found VM virtualization qemu
514 10:11:26.479826 <30>[ 6.172334] systemd[1]: Detected virtualization qemu.
515 10:11:26.479991 <30>[ 6.172653] systemd[1]: Detected architecture arm64.
516 10:11:26.480472 <31>[ 6.172953] systemd[1]: Detected initialized system, this is not the first boot.
517 10:11:26.484529
518 10:11:26.484889 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
519 10:11:26.484995
520 10:11:26.486722 <30>[ 6.179265] systemd[1]: Set hostname to <debian-bullseye-arm64>.
521 10:11:26.505788 <31>[ 6.198207] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
522 10:11:26.506894 <31>[ 6.199346] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
523 10:11:26.507355 <31>[ 6.199852] systemd[1]: Successfully brought loopback interface up
524 10:11:26.511919 <31>[ 6.204410] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
525 10:11:26.523690 <31>[ 6.216205] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
526 10:11:26.523881 <31>[ 6.216528] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
527 10:11:26.563658 <31>[ 6.256024] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
528 10:11:26.565169 <31>[ 6.257655] systemd[1]: Controller 'cpu' supported: yes
529 10:11:26.565366 <31>[ 6.257892] systemd[1]: Controller 'cpuacct' supported: no
530 10:11:26.565562 <31>[ 6.258078] systemd[1]: Controller 'cpuset' supported: yes
531 10:11:26.565751 <31>[ 6.258274] systemd[1]: Controller 'io' supported: yes
532 10:11:26.565943 <31>[ 6.258461] systemd[1]: Controller 'blkio' supported: no
533 10:11:26.566104 <31>[ 6.258671] systemd[1]: Controller 'memory' supported: yes
534 10:11:26.566287 <31>[ 6.258825] systemd[1]: Controller 'devices' supported: no
535 10:11:26.566443 <31>[ 6.258986] systemd[1]: Controller 'pids' supported: yes
536 10:11:26.566618 <31>[ 6.259194] systemd[1]: Controller 'bpf-firewall' supported: yes
537 10:11:26.566767 <31>[ 6.259414] systemd[1]: Controller 'bpf-devices' supported: yes
538 10:11:26.568138 <31>[ 6.260566] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
539 10:11:26.568715 <31>[ 6.261213] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
540 10:11:26.569168 <31>[ 6.261824] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
541 10:11:26.577042 <31>[ 6.269482] systemd[1]: Enabling (yes) showing of status (commandline).
542 10:11:26.584420 <31>[ 6.276875] systemd[1]: Successfully forked off '(sd-executor)' as PID 94.
543 10:11:26.594062 <31>[ 6.286466] systemd[94]: Successfully forked off '(direxec)' as PID 95.
544 10:11:26.595838 <31>[ 6.288384] systemd[94]: Successfully forked off '(direxec)' as PID 96.
545 10:11:26.598077 <31>[ 6.290513] systemd[94]: Successfully forked off '(direxec)' as PID 97.
546 10:11:26.599873 <31>[ 6.292441] systemd[94]: Successfully forked off '(direxec)' as PID 98.
547 10:11:26.618339 <31>[ 6.310946] systemd[94]: Successfully forked off '(direxec)' as PID 99.
548 10:11:26.774285 <31>[ 6.466638] systemd-bless-boot-generator[95]: Skipping generator, not an EFI boot.
549 10:11:26.779380 <31>[ 6.471749] systemd-fstab-generator[96]: Parsing /etc/fstab...
550 10:11:26.781066 <31>[ 6.473527] systemd-getty-generator[97]: Automatically adding serial getty for /dev/ttyAMA0.
551 10:11:26.782603 <31>[ 6.475016] systemd-getty-generator[97]: SELinux enabled state cached to: disabled
552 10:11:26.792349 <31>[ 6.484788] systemd-fstab-generator[96]: Found entry what=/dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76 where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
553 10:11:26.796349 <31>[ 6.488810] systemd[94]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
554 10:11:26.799748 <31>[ 6.492005] systemd-fstab-generator[96]: Checking was requested for /dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76, but fsck.ext4 does not exist.
555 10:11:26.806074 <31>[ 6.498602] systemd-fstab-generator[96]: SELinux enabled state cached to: disabled
556 10:11:26.811159 <31>[ 6.503717] systemd[94]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
557 10:11:26.811546 <31>[ 6.504210] systemd[94]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
558 10:11:26.811960 <31>[ 6.504556] systemd[94]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
559 10:11:26.812496 <31>[ 6.504902] systemd[94]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
560 10:11:26.815341 <31>[ 6.507896] systemd[1]: (sd-executor) succeeded.
561 10:11:26.817256 <31>[ 6.509828] systemd[1]: Looking for unit files in (higher priority first):
562 10:11:26.817386 <31>[ 6.510080] systemd[1]: /etc/systemd/system.control
563 10:11:26.817733 <31>[ 6.510272] systemd[1]: /run/systemd/system.control
564 10:11:26.817842 <31>[ 6.510500] systemd[1]: /run/systemd/transient
565 10:11:26.817949 <31>[ 6.510663] systemd[1]: /run/systemd/generator.early
566 10:11:26.818161 <31>[ 6.510828] systemd[1]: /etc/systemd/system
567 10:11:26.818284 <31>[ 6.510986] systemd[1]: /etc/systemd/system.attached
568 10:11:26.818623 <31>[ 6.511160] systemd[1]: /run/systemd/system
569 10:11:26.818731 <31>[ 6.511313] systemd[1]: /run/systemd/system.attached
570 10:11:26.818842 <31>[ 6.511472] systemd[1]: /run/systemd/generator
571 10:11:26.818950 <31>[ 6.511639] systemd[1]: /usr/local/lib/systemd/system
572 10:11:26.819286 <31>[ 6.511845] systemd[1]: /lib/systemd/system
573 10:11:26.819385 <31>[ 6.512018] systemd[1]: /usr/lib/systemd/system
574 10:11:26.819489 <31>[ 6.512176] systemd[1]: /run/systemd/generator.late
575 10:11:26.854440 <31>[ 6.547062] systemd[1]: Modification times have changed, need to update cache.
576 10:11:26.856034 <31>[ 6.548552] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
577 10:11:26.857817 <31>[ 6.550152] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
578 10:11:26.858434 <31>[ 6.550913] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
579 10:11:26.859188 <31>[ 6.551728] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
580 10:11:26.860210 <31>[ 6.552549] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
581 10:11:26.860581 <31>[ 6.552927] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
582 10:11:26.861169 <31>[ 6.553602] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
583 10:11:26.861500 <31>[ 6.553976] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
584 10:11:26.861889 <31>[ 6.554304] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
585 10:11:26.862004 <31>[ 6.554665] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
586 10:11:26.862380 <31>[ 6.555039] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
587 10:11:26.863196 <31>[ 6.555780] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
588 10:11:26.863772 <31>[ 6.556133] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
589 10:11:26.863996 <31>[ 6.556442] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
590 10:11:26.864913 <31>[ 6.557287] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
591 10:11:26.865147 <31>[ 6.557634] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
592 10:11:26.865672 <31>[ 6.557950] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
593 10:11:26.865873 <31>[ 6.558338] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
594 10:11:26.866103 <31>[ 6.558673] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
595 10:11:26.866918 <31>[ 6.559321] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
596 10:11:26.867260 <31>[ 6.559675] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp.service
597 10:11:26.867980 <31>[ 6.560337] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
598 10:11:26.868205 <31>[ 6.560723] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup-pre.target
599 10:11:26.868948 <31>[ 6.561401] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
600 10:11:26.869129 <31>[ 6.561766] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
601 10:11:26.869570 <31>[ 6.562144] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
602 10:11:26.870062 <31>[ 6.562499] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.service
603 10:11:26.870774 <31>[ 6.563212] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
604 10:11:26.871499 <31>[ 6.563838] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
605 10:11:26.871675 <31>[ 6.564264] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
606 10:11:26.872150 <31>[ 6.564602] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
607 10:11:26.873038 <31>[ 6.565401] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
608 10:11:26.873219 <31>[ 6.565749] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
609 10:11:26.873682 <31>[ 6.566095] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
610 10:11:26.874178 <31>[ 6.566467] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
611 10:11:26.874358 <31>[ 6.566840] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
612 10:11:26.874801 <31>[ 6.567214] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-device.target
613 10:11:26.875020 <31>[ 6.567591] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-parse-etc.service
614 10:11:26.875574 <31>[ 6.567954] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
615 10:11:26.875825 <31>[ 6.568287] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
616 10:11:26.876045 <31>[ 6.568580] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
617 10:11:26.876291 <31>[ 6.568889] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
618 10:11:26.876823 <31>[ 6.569339] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
619 10:11:26.877077 <31>[ 6.569643] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
620 10:11:26.877588 <31>[ 6.569934] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
621 10:11:26.878165 <31>[ 6.570514] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
622 10:11:26.878389 <31>[ 6.570868] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
623 10:11:26.878887 <31>[ 6.571479] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel2.target → multi-user.target
624 10:11:26.879969 <31>[ 6.571807] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
625 10:11:26.880171 <31>[ 6.572147] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend.target
626 10:11:26.880382 <31>[ 6.572401] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
627 10:11:26.881003 <31>[ 6.572667] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysusers.service
628 10:11:26.881206 <31>[ 6.573501] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
629 10:11:26.881378 <31>[ 6.573819] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
630 10:11:26.881799 <31>[ 6.574154] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
631 10:11:26.881987 <31>[ 6.574485] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
632 10:11:26.882750 <31>[ 6.575158] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
633 10:11:26.883236 <31>[ 6.575555] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
634 10:11:26.883430 <31>[ 6.575956] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
635 10:11:26.884253 <31>[ 6.576615] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
636 10:11:26.884779 <31>[ 6.577193] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
637 10:11:26.885366 <31>[ 6.577668] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-lookup.target
638 10:11:26.885601 <31>[ 6.578019] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/umount.target
639 10:11:26.885861 <31>[ 6.578418] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
640 10:11:26.886398 <31>[ 6.578806] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-tracing.mount
641 10:11:26.886619 <31>[ 6.579147] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.socket
642 10:11:26.887154 <31>[ 6.579516] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
643 10:11:26.887372 <31>[ 6.579858] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
644 10:11:26.887907 <31>[ 6.580205] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
645 10:11:26.888127 <31>[ 6.580530] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-online.target
646 10:11:26.888310 <31>[ 6.580882] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
647 10:11:26.889231 <31>[ 6.581487] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hybrid-sleep.service
648 10:11:26.889453 <31>[ 6.581904] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
649 10:11:26.889984 <31>[ 6.582244] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
650 10:11:26.890232 <31>[ 6.582877] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
651 10:11:26.890783 <31>[ 6.583210] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
652 10:11:26.890998 <31>[ 6.583531] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
653 10:11:26.891862 <31>[ 6.584066] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
654 10:11:26.892088 <31>[ 6.584470] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
655 10:11:26.892641 <31>[ 6.584835] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
656 10:11:26.893271 <31>[ 6.585583] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
657 10:11:26.893856 <31>[ 6.586147] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
658 10:11:26.894452 <31>[ 6.586843] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.locale1.service → systemd-localed.service
659 10:11:26.894687 <31>[ 6.587215] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
660 10:11:26.894872 <31>[ 6.587510] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
661 10:11:26.895082 <31>[ 6.587762] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
662 10:11:26.895446 <31>[ 6.588039] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
663 10:11:26.895675 <31>[ 6.588268] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
664 10:11:26.895866 <31>[ 6.588528] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
665 10:11:26.896397 <31>[ 6.588801] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsck-root.service
666 10:11:26.897067 <31>[ 6.589312] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-quotacheck.service
667 10:11:26.897264 <31>[ 6.589646] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
668 10:11:26.897492 <31>[ 6.589972] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
669 10:11:26.897732 <31>[ 6.590284] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
670 10:11:26.898261 <31>[ 6.590659] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
671 10:11:26.898484 <31>[ 6.590937] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
672 10:11:26.898658 <31>[ 6.591222] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
673 10:11:26.899157 <31>[ 6.591679] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-varlink@.socket
674 10:11:26.899411 <31>[ 6.592013] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
675 10:11:26.899600 <31>[ 6.592287] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
676 10:11:26.900344 <31>[ 6.592947] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.hostname1.service → systemd-hostnamed.service
677 10:11:26.900896 <31>[ 6.593512] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
678 10:11:26.901497 <31>[ 6.593858] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
679 10:11:26.901738 <31>[ 6.594133] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
680 10:11:26.901908 <31>[ 6.594375] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user-runtime-dir@.service
681 10:11:26.902094 <31>[ 6.594643] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kmod-static-nodes.service
682 10:11:26.902301 <31>[ 6.594897] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-logind.service
683 10:11:26.902843 <31>[ 6.595162] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
684 10:11:26.903047 <31>[ 6.595424] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-bless-boot.service
685 10:11:26.903232 <31>[ 6.595731] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
686 10:11:26.903435 <31>[ 6.596028] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
687 10:11:26.903985 <31>[ 6.596361] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-pre.target
688 10:11:26.904191 <31>[ 6.596643] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
689 10:11:26.904373 <31>[ 6.596871] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
690 10:11:26.905276 <31>[ 6.597667] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
691 10:11:26.905544 <31>[ 6.598099] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
692 10:11:26.906156 <31>[ 6.598503] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
693 10:11:26.906709 <31>[ 6.598991] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.service
694 10:11:26.906948 <31>[ 6.599447] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-cleanup.service
695 10:11:26.907190 <31>[ 6.599732] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/basic.target
696 10:11:26.907380 <31>[ 6.599983] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
697 10:11:26.907901 <31>[ 6.600310] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
698 10:11:26.908114 <31>[ 6.600630] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
699 10:11:26.908658 <31>[ 6.600914] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-kernel.socket
700 10:11:26.908855 <31>[ 6.601362] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
701 10:11:26.909095 <31>[ 6.601696] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
702 10:11:26.909669 <31>[ 6.602035] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/serial-getty@.service
703 10:11:26.909899 <31>[ 6.602328] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
704 10:11:26.910124 <31>[ 6.602623] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
705 10:11:26.910304 <31>[ 6.602894] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sockets.target
706 10:11:26.910775 <31>[ 6.603371] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks.service → /dev/null
707 10:11:26.911334 <31>[ 6.603731] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
708 10:11:26.911822 <31>[ 6.604397] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
709 10:11:26.912061 <31>[ 6.604705] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
710 10:11:26.912564 <31>[ 6.604984] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate.service
711 10:11:26.913218 <31>[ 6.605483] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
712 10:11:26.913416 <31>[ 6.605770] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
713 10:11:26.913619 <31>[ 6.606000] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
714 10:11:26.913852 <31>[ 6.606282] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
715 10:11:26.914041 <31>[ 6.606531] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sound.target
716 10:11:26.914272 <31>[ 6.606745] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
717 10:11:26.914505 <31>[ 6.606995] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
718 10:11:26.914739 <31>[ 6.607270] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
719 10:11:26.915528 <31>[ 6.607709] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
720 10:11:26.915790 <31>[ 6.608205] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
721 10:11:26.915962 <31>[ 6.608475] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
722 10:11:26.916145 <31>[ 6.608727] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
723 10:11:26.916664 <31>[ 6.609219] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
724 10:11:26.916902 <31>[ 6.609531] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/boot-complete.target
725 10:11:26.917149 <31>[ 6.609789] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
726 10:11:26.917678 <31>[ 6.610062] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
727 10:11:27.352958 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
728 10:11:27.357390 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
729 10:11:27.360759 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
730 10:11:27.363681 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
731 10:11:27.367326 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
732 10:11:27.368930 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
733 10:11:27.371106 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
734 10:11:27.372138 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
735 10:11:27.373071 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
736 10:11:27.373838 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
737 10:11:27.374600 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
738 10:11:27.378313 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
739 10:11:27.382332 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
740 10:11:27.385309 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
741 10:11:27.387525 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
742 10:11:27.390273 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
743 10:11:27.393033 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
744 10:11:27.394994 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
745 10:11:27.422214 Mounting [0;1;39mHuge Pages File System[0m...
746 10:11:27.457591 Mounting [0;1;39mPOSIX Message Queue File System[0m...
747 10:11:27.497815 Mounting [0;1;39mKernel Debug File System[0m...
748 10:11:27.531324 Starting [0;1;39mLoad Kernel Module configfs[0m...
749 10:11:27.577983 Starting [0;1;39mLoad Kernel Module drm[0m...
750 10:11:27.634313 Starting [0;1;39mJournal Service[0m...
751 10:11:27.666177 Starting [0;1;39mLoad Kernel Modules[0m...
752 10:11:27.709904 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
753 10:11:27.762085 Starting [0;1;39mColdplug All udev Devices[0m...
754 10:11:27.861131 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
755 10:11:27.863522 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
756 10:11:27.874853 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
757 10:11:27.930411 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
758 10:11:27.989244 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
759 10:11:28.011473 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
760 10:11:28.086027 Mounting [0;1;39mKernel Configuration File System[0m...
761 10:11:28.225807 Starting [0;1;39mApply Kernel Variables[0m...
762 10:11:28.278695 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
763 10:11:28.314899 <47>[ 8.007475] systemd-journald[105]: SELinux enabled state cached to: disabled
764 10:11:28.316266 <47>[ 8.008741] systemd-journald[105]: Auditing in kernel turned off.
765 10:11:28.355866 <47>[ 8.048486] systemd-journald[105]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
766 10:11:28.418196 <47>[ 8.110758] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
767 10:11:28.434217 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
768 10:11:28.434821 <47>[ 8.127372] systemd-journald[105]: Fixed min_use=3.8M max_use=19.4M max_size=2.4M min_size=512.0K keep_free=9.7M n_max_files=100
769 10:11:28.441597 See 'systemctl status systemd-remount-fs.service' for details.
770 10:11:28.445016 <47>[ 8.137447] systemd-journald[105]: Reserving 333 entries in field hash table.
771 10:11:28.478328 <47>[ 8.170940] systemd-journald[105]: Reserving 4437 entries in data hash table.
772 10:11:28.480460 <47>[ 8.172916] systemd-journald[105]: Vacuuming...
773 10:11:28.483095 Starting [0;1;39mLoad/Save Random Seed[0m...
774 10:11:28.497583 <47>[ 8.189877] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
775 10:11:28.497844 <47>[ 8.190550] systemd-journald[105]: Flushing /dev/kmsg...
776 10:11:28.554047 Starting [0;1;39mCreate System Users[0m...
777 10:11:28.593268 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
778 10:11:28.697596 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
779 10:11:28.881183 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
780 10:11:28.926767 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
781 10:11:29.067751 <47>[ 8.760117] systemd-journald[105]: systemd-journald running as PID 105 for the system.
782 10:11:29.082208 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
783 10:11:29.092849 <47>[ 8.785403] systemd-journald[105]: Sent READY=1 notification.
784 10:11:29.093474 <47>[ 8.785976] systemd-journald[105]: Sent WATCHDOG=1 notification.
785 10:11:29.132044 <47>[ 8.824435] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
786 10:11:29.142182 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
787 10:11:29.172881 <47>[ 8.865246] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
788 10:11:29.184899 <47>[ 8.877318] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
789 10:11:29.201379 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
790 10:11:29.204839 <47>[ 8.897323] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
791 10:11:29.209900 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
792 10:11:29.218325 <47>[ 8.910697] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
793 10:11:29.223380 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
794 10:11:29.239748 <47>[ 8.932051] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
795 10:11:29.250956 <47>[ 8.943339] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
796 10:11:29.283843 <47>[ 8.975473] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
797 10:11:29.298505 <47>[ 8.991098] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
798 10:11:29.300425 <47>[ 8.992892] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
799 10:11:29.308986 <47>[ 9.001701] systemd-journald[105]: n/a: New incoming connection.
800 10:11:29.309753 <47>[ 9.002277] systemd-journald[105]: varlink-20: varlink: setting state idle-server
801 10:11:29.326636 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
802 10:11:29.337429 <47>[ 9.029800] systemd-journald[105]: varlink-20: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
803 10:11:29.339216 <47>[ 9.031768] systemd-journald[105]: varlink-20: varlink: changing state idle-server → processing-method
804 10:11:29.339597 <46>[ 9.032185] systemd-journald[105]: Received client request to flush runtime journal.
805 10:11:29.340218 <47>[ 9.032673] systemd-journald[105]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
806 10:11:29.353061 <47>[ 9.045771] systemd-journald[105]: Vacuuming...
807 10:11:29.353758 <47>[ 9.046208] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
808 10:11:29.354965 <47>[ 9.047501] systemd-journald[105]: varlink-20: Sending message: {\"parameters\":{}}
809 10:11:29.355369 <47>[ 9.047797] systemd-journald[105]: varlink-20: varlink: changing state processing-method → processed-method
810 10:11:29.355755 <47>[ 9.048224] systemd-journald[105]: varlink-20: varlink: changing state processed-method → idle-server
811 10:11:29.381631 <47>[ 9.073888] systemd-journald[105]: varlink-20: varlink: changing state idle-server → pending-disconnect
812 10:11:29.381961 <47>[ 9.074258] systemd-journald[105]: varlink-20: varlink: changing state pending-disconnect → processing-disconnect
813 10:11:29.382185 <47>[ 9.074636] systemd-journald[105]: varlink-20: varlink: changing state processing-disconnect → disconnected
814 10:11:29.383985 <47>[ 9.076464] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
815 10:11:29.387833 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
816 10:11:29.392082 <47>[ 9.084443] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
817 10:11:29.415647 <47>[ 9.107937] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
818 10:11:29.430536 <47>[ 9.123136] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
819 10:11:29.449074 <47>[ 9.141426] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
820 10:11:29.458210 Starting [0;1;39mCreate Volatile Files and Directories[0m...
821 10:11:29.480807 <47>[ 9.173375] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
822 10:11:29.897095 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
823 10:11:29.974934 Starting [0;1;39mNetwork Service[0m...
824 10:11:30.008199 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
825 10:11:30.035226 <47>[ 9.727526] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
826 10:11:30.098132 Starting [0;1;39mNetwork Time Synchronization[0m...
827 10:11:30.147392 <47>[ 9.839980] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
828 10:11:30.166213 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
829 10:11:30.174783 <47>[ 9.867176] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
830 10:11:30.596592 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
831 10:11:31.624314 <47>[ 11.316407] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3328 of 4437 items, 2555904 file size, 768 bytes per hash table item), suggesting rotation.
832 10:11:31.641084 <47>[ 11.333450] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
833 10:11:31.641332 <47>[ 11.334047] systemd-journald[105]: Rotating...
834 10:11:31.642597 <47>[ 11.335023] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
835 10:11:31.644067 <47>[ 11.336512] systemd-journald[105]: Reserving 333 entries in field hash table.
836 10:11:31.661389 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
837 10:11:31.714679 <47>[ 11.407232] systemd-journald[105]: Reserving 4437 entries in data hash table.
838 10:11:31.730630 <47>[ 11.423267] systemd-journald[105]: Vacuuming...
839 10:11:31.753354 <47>[ 11.445708] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
840 10:11:31.779009 Starting [0;1;39mNetwork Name Resolution[0m...
841 10:11:31.811147 <47>[ 11.503450] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
842 10:11:32.118587 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
843 10:11:32.122814 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
844 10:11:32.138221 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
845 10:11:32.209038 <47>[ 11.901344] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
846 10:11:33.480996 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
847 10:11:33.492860 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
848 10:11:33.514176 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
849 10:11:33.529827 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
850 10:11:33.543303 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
851 10:11:33.547697 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
852 10:11:33.577747 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
853 10:11:33.578507 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
854 10:11:33.579163 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
855 10:11:33.674627 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
856 10:11:33.693580 <47>[ 13.386114] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
857 10:11:33.854081 <47>[ 13.546321] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
858 10:11:33.854965 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
859 10:11:34.034460 Starting [0;1;39mUser Login Management[0m...
860 10:11:34.078774 <47>[ 13.771371] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
861 10:11:34.239927 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
862 10:11:34.242132 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
863 10:11:34.245269 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
864 10:11:34.326005 Starting [0;1;39mPermit User Sessions[0m...
865 10:11:34.331403 <47>[ 14.023769] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
866 10:11:34.585141 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
867 10:11:34.653391 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
868 10:11:34.864349 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
869 10:11:35.289404 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
870 10:11:37.406268 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
871 10:11:37.483367 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
872 10:11:37.506045 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
873 10:11:37.519497 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
874 10:11:37.533045 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
875 10:11:37.593787 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
876 10:11:37.605312 <47>[ 17.297649] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
877 10:11:37.843411 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
878 10:11:37.901838 <47>[ 17.594217] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
879 10:11:37.902743 <47>[ 17.595238] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
880 10:11:38.016515
881 10:11:38.017039 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
882 10:11:38.017155
883 10:11:38.017252 debian-bullseye-arm64 login: root (automatic login)
884 10:11:38.017627
885 10:11:38.219601 <6>[ 17.912150] virtio_net virtio0 enp0s1: renamed from eth0
886 10:11:38.350751 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 10 09:57:04 UTC 2023 aarch64
887 10:11:38.351745
888 10:11:38.352126 The programs included with the Debian GNU/Linux system are free software;
889 10:11:38.352237 the exact distribution terms for each program are described in the
890 10:11:38.352331 individual files in /usr/share/doc/*/copyright.
891 10:11:38.352423
892 10:11:38.352522 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
893 10:11:38.360545 permitted by applicable law.
894 10:11:39.132177 <47>[ 18.824503] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3329 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
895 10:11:39.148872 <47>[ 18.841227] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
896 10:11:39.149133 <47>[ 18.841657] systemd-journald[105]: Rotating...
897 10:11:39.150760 <47>[ 18.843457] systemd-journald[105]: Reserving 333 entries in field hash table.
898 10:11:39.194670 <47>[ 18.887076] systemd-journald[105]: Reserving 4437 entries in data hash table.
899 10:11:39.206037 <47>[ 18.898716] systemd-journald[105]: Vacuuming...
900 10:11:39.207482 <47>[ 18.900001] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
901 10:11:39.226831 <47>[ 18.919427] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
902 10:11:39.454296 <47>[ 19.146832] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
903 10:11:40.736757 <47>[ 20.429283] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
904 10:11:41.885278 Matched prompt #10: / #
906 10:11:41.885697 Setting prompt string to ['/ #']
907 10:11:41.885833 end: 2.2.1 login-action (duration 00:00:22) [common]
909 10:11:41.886113 end: 2.2 auto-login-action (duration 00:00:26) [common]
910 10:11:41.886227 start: 2.3 expect-shell-connection (timeout 00:04:33) [common]
911 10:11:41.886320 Setting prompt string to ['/ #']
912 10:11:41.886402 Forcing a shell prompt, looking for ['/ #']
914 10:11:41.936715 / #
915 10:11:41.936902 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
916 10:11:41.937007 Waiting using forced prompt support (timeout 00:02:30)
917 10:11:41.939108
918 10:11:41.946423 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
919 10:11:41.946558 start: 2.4 export-device-env (timeout 00:04:33) [common]
920 10:11:41.946678 end: 2.4 export-device-env (duration 00:00:00) [common]
921 10:11:41.946782 end: 2 boot-image-retry (duration 00:00:27) [common]
922 10:11:41.946889 start: 3 lava-test-retry (timeout 00:08:51) [common]
923 10:11:41.946993 start: 3.1 lava-test-shell (timeout 00:08:51) [common]
924 10:11:41.947085 Using namespace: common
926 10:11:42.047833 / # #
927 10:11:42.048080 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
928 10:11:42.048798 #
930 10:11:42.158611 / # mkdir /lava-592458
931 10:11:42.159574 mkdir /lava-592458
933 10:11:42.283039 / # mount /dev/disk/by-uuid/18cd3e18-c601-4525-9ef4-19f1a271b997 -t ext2 /lava-592458
934 10:11:42.284020 mount /dev/disk/by-uuid/18cd3e18-c601-4525-9ef4-19f1a271b997 -t ext2 /lava-592458
935 10:11:42.327072 <4>[ 22.019229] ext2 filesystem being mounted at /lava-592458 supports timestamps until 2038 (0x7fffffff)
937 10:11:42.469248 / # ls -la /lava-592458/bin/lava-test-runner
938 10:11:42.470160 ls -la /lava-592458/bin/lava-test-runner
939 10:11:42.523141 -rwxr-xr-x 1 root root 1039 Jun 10 10:10 /lava-592458/bin/lava-test-runner
940 10:11:42.536072 Using /lava-592458
942 10:11:42.637179 / # export SHELL=/bin/sh
943 10:11:42.638050 export SHELL=/bin/sh
945 10:11:42.747449 / # . /lava-592458/environment
946 10:11:42.748352 . /lava-592458/environment
948 10:11:42.860492 / # /lava-592458/bin/lava-test-runner /lava-592458/0
949 10:11:42.860781 Test shell timeout: 10s (minimum of the action and connection timeout)
950 10:11:42.861535 /lava-592458/bin/lava-test-runner /lava-592458/0
951 10:11:43.012522 + export TESTRUN_ID=0_timesync-off
952 10:11:43.012760 + cd /lava-592458/0/tests/0_timesync-off
953 10:11:43.014729 + cat uuid
954 10:11:43.022646 + UUID=592458_1.1.3.1
955 10:11:43.022812 + set +x
956 10:11:43.023078 <LAVA_SIGNAL_STARTRUN 0_timesync-off 592458_1.1.3.1>
957 10:11:43.023397 Received signal: <STARTRUN> 0_timesync-off 592458_1.1.3.1
958 10:11:43.023493 Starting test lava.0_timesync-off (592458_1.1.3.1)
959 10:11:43.023589 Skipping test definition patterns.
960 10:11:43.023702 + systemctl stop systemd-timesyncd
961 10:11:43.296995 + set +x
962 10:11:43.297231 <LAVA_SIGNAL_ENDRUN 0_timesync-off 592458_1.1.3.1>
963 10:11:43.297522 Received signal: <ENDRUN> 0_timesync-off 592458_1.1.3.1
964 10:11:43.297662 Ending use of test pattern.
965 10:11:43.297759 Ending test lava.0_timesync-off (592458_1.1.3.1), duration 0.27
967 10:11:43.347136 + export TESTRUN_ID=1_kselftest-arm64_qemu
968 10:11:43.347751 + cd /lava-592458/0/tests/1_kselftest-arm64_qemu
969 10:11:43.350210 + cat uuid
970 10:11:43.359148 + UUID=592458_1.1.3.5
971 10:11:43.359446 + set +x
972 10:11:43.359650 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 592458_1.1.3.5>
973 10:11:43.359864 + cd ./automated/linux/kselftest/
974 10:11:43.360188 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 592458_1.1.3.5
975 10:11:43.360317 Starting test lava.1_kselftest-arm64_qemu (592458_1.1.3.5)
976 10:11:43.360491 Skipping test definition patterns.
977 10:11:43.365813 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip -e -p /opt/kselftests/mainline/ -n 1 -i 1
978 10:11:43.475033 INFO: install_deps skipped
979 10:11:43.513956 --2023-06-10 10:11:43-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-45-gce658d9231044/arm64/defconfig/gcc-10/kselftest.tar.xz
980 10:11:43.674234 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
981 10:11:43.863141 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
982 10:11:44.048777 HTTP request sent, awaiting response... 200 OK
983 10:11:44.052163 Length: 2701176 (2.6M) [application/octet-stream]
984 10:11:44.053686 Saving to: 'kselftest.tar.xz'
985 10:11:44.055282
986 10:11:45.286038 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 160KB/s kselftest.tar.xz 8%[> ] 219.84K 343KB/s kselftest.tar.xz 34%[=====> ] 898.59K 926KB/s kselftest.tar.xz 84%[===============> ] 2.17M 1.85MB/s kselftest.tar.xz 100%[===================>] 2.58M 2.17MB/s in 1.2s
987 10:11:45.286253
988 10:11:45.291621 2023-06-10 10:11:45 (2.17 MB/s) - 'kselftest.tar.xz' saved [2701176/2701176]
989 10:11:45.291726
990 10:11:48.705081 skiplist:
991 10:11:48.705575 ========================================
992 10:11:48.706127 ========================================
993 10:11:48.768865 arm64:tags_test
994 10:11:48.769112 arm64:run_tags_test.sh
995 10:11:48.769203 arm64:fake_sigreturn_bad_magic
996 10:11:48.769492 arm64:fake_sigreturn_bad_size
997 10:11:48.769595 arm64:fake_sigreturn_bad_size_for_magic0
998 10:11:48.769713 arm64:fake_sigreturn_duplicated_fpsimd
999 10:11:48.769795 arm64:fake_sigreturn_misaligned_sp
1000 10:11:48.769875 arm64:fake_sigreturn_missing_fpsimd
1001 10:11:48.769951 arm64:fake_sigreturn_sme_change_vl
1002 10:11:48.770028 arm64:fake_sigreturn_sve_change_vl
1003 10:11:48.770109 arm64:mangle_pstate_invalid_compat_toggle
1004 10:11:48.770186 arm64:mangle_pstate_invalid_daif_bits
1005 10:11:48.770511 arm64:mangle_pstate_invalid_mode_el1h
1006 10:11:48.770622 arm64:mangle_pstate_invalid_mode_el1t
1007 10:11:48.770709 arm64:mangle_pstate_invalid_mode_el2h
1008 10:11:48.770790 arm64:mangle_pstate_invalid_mode_el2t
1009 10:11:48.770873 arm64:mangle_pstate_invalid_mode_el3h
1010 10:11:48.771309 arm64:mangle_pstate_invalid_mode_el3t
1011 10:11:48.771558 arm64:sme_trap_no_sm
1012 10:11:48.771756 arm64:sme_trap_non_streaming
1013 10:11:48.771933 arm64:sme_trap_za
1014 10:11:48.772088 arm64:sme_vl
1015 10:11:48.772212 arm64:ssve_regs
1016 10:11:48.772331 arm64:sve_regs
1017 10:11:48.772448 arm64:sve_vl
1018 10:11:48.772565 arm64:za_no_regs
1019 10:11:48.772681 arm64:za_regs
1020 10:11:48.772796 arm64:pac
1021 10:11:48.772914 arm64:fp-stress
1022 10:11:48.773030 arm64:sve-ptrace
1023 10:11:48.773146 arm64:sve-probe-vls
1024 10:11:48.773263 arm64:vec-syscfg
1025 10:11:48.773392 arm64:za-fork
1026 10:11:48.773512 arm64:za-ptrace
1027 10:11:48.773629 arm64:check_buffer_fill
1028 10:11:48.773841 arm64:check_child_memory
1029 10:11:48.773985 arm64:check_gcr_el1_cswitch
1030 10:11:48.774104 arm64:check_ksm_options
1031 10:11:48.774220 arm64:check_mmap_options
1032 10:11:48.774335 arm64:check_prctl
1033 10:11:48.774451 arm64:check_tags_inclusion
1034 10:11:48.774568 arm64:check_user_mem
1035 10:11:48.774683 arm64:btitest
1036 10:11:48.774798 arm64:nobtitest
1037 10:11:48.774914 arm64:hwcap
1038 10:11:48.775029 arm64:ptrace
1039 10:11:48.775143 arm64:syscall-abi
1040 10:11:48.775259 arm64:tpidr2
1041 10:11:48.788230 ============== Tests to run ===============
1042 10:11:48.793601 arm64:tags_test
1043 10:11:48.793958 arm64:run_tags_test.sh
1044 10:11:48.794174 arm64:fake_sigreturn_bad_magic
1045 10:11:48.794362 arm64:fake_sigreturn_bad_size
1046 10:11:48.794605 arm64:fake_sigreturn_bad_size_for_magic0
1047 10:11:48.794965 arm64:fake_sigreturn_duplicated_fpsimd
1048 10:11:48.795068 arm64:fake_sigreturn_misaligned_sp
1049 10:11:48.795152 arm64:fake_sigreturn_missing_fpsimd
1050 10:11:48.795230 arm64:fake_sigreturn_sme_change_vl
1051 10:11:48.795309 arm64:fake_sigreturn_sve_change_vl
1052 10:11:48.795384 arm64:mangle_pstate_invalid_compat_toggle
1053 10:11:48.795476 arm64:mangle_pstate_invalid_daif_bits
1054 10:11:48.795782 arm64:mangle_pstate_invalid_mode_el1h
1055 10:11:48.795883 arm64:mangle_pstate_invalid_mode_el1t
1056 10:11:48.795963 arm64:mangle_pstate_invalid_mode_el2h
1057 10:11:48.796048 arm64:mangle_pstate_invalid_mode_el2t
1058 10:11:48.796125 arm64:mangle_pstate_invalid_mode_el3h
1059 10:11:48.796201 arm64:mangle_pstate_invalid_mode_el3t
1060 10:11:48.796277 arm64:sme_trap_no_sm
1061 10:11:48.796353 arm64:sme_trap_non_streaming
1062 10:11:48.796429 arm64:sme_trap_za
1063 10:11:48.796505 arm64:sme_vl
1064 10:11:48.796580 arm64:ssve_regs
1065 10:11:48.796656 arm64:sve_regs
1066 10:11:48.796731 arm64:sve_vl
1067 10:11:48.796807 arm64:za_no_regs
1068 10:11:48.796902 arm64:za_regs
1069 10:11:48.796981 arm64:pac
1070 10:11:48.797058 arm64:fp-stress
1071 10:11:48.797137 arm64:sve-ptrace
1072 10:11:48.797213 arm64:sve-probe-vls
1073 10:11:48.797288 arm64:vec-syscfg
1074 10:11:48.797362 arm64:za-fork
1075 10:11:48.797437 arm64:za-ptrace
1076 10:11:48.797512 arm64:check_buffer_fill
1077 10:11:48.797588 arm64:check_child_memory
1078 10:11:48.797673 arm64:check_gcr_el1_cswitch
1079 10:11:48.797750 arm64:check_ksm_options
1080 10:11:48.797825 arm64:check_mmap_options
1081 10:11:48.797900 arm64:check_prctl
1082 10:11:48.797975 arm64:check_tags_inclusion
1083 10:11:48.798050 arm64:check_user_mem
1084 10:11:48.798160 arm64:btitest
1085 10:11:48.798246 arm64:nobtitest
1086 10:11:48.798323 arm64:hwcap
1087 10:11:48.798398 arm64:ptrace
1088 10:11:48.798474 arm64:syscall-abi
1089 10:11:48.798567 arm64:tpidr2
1090 10:11:48.799753 ===========End Tests to run ===============
1091 10:11:50.143464 <12>[ 29.836132] kselftest: Running tests in arm64
1092 10:11:50.180824 TAP version 13
1093 10:11:50.202476 1..48
1094 10:11:50.261283 # selftests: arm64: tags_test
1095 10:11:50.334679 ok 1 selftests: arm64: tags_test
1096 10:11:50.412406 # selftests: arm64: run_tags_test.sh
1097 10:11:50.477662 # --------------------
1098 10:11:50.477892 # running tags test
1099 10:11:50.477975 # --------------------
1100 10:11:50.478052 # [PASS]
1101 10:11:50.485771 ok 2 selftests: arm64: run_tags_test.sh
1102 10:11:50.551921 # selftests: arm64: fake_sigreturn_bad_magic
1103 10:11:50.615662 # Registered handlers for all signals.
1104 10:11:50.615912 # Detected MINSTKSIGSZ:10000
1105 10:11:50.616219 # Testcase initialized.
1106 10:11:50.616305 # uc context validated.
1107 10:11:50.616387 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1108 10:11:50.616466 # Handled SIG_COPYCTX
1109 10:11:50.619198 # Available space:3536
1110 10:11:50.619320 # Using badly built context - ERR: BAD MAGIC !
1111 10:11:50.619789 # SIG_OK -- SP:0xFFFFFF953810 si_addr@:0xffffff953810 si_code:2 token@:0xffffff9525b0 offset:-4704
1112 10:11:50.619958 # ==>> completed. PASS(1)
1113 10:11:50.620138 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1114 10:11:50.620646 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFF9525B0
1115 10:11:50.630364 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1116 10:11:50.710551 # selftests: arm64: fake_sigreturn_bad_size
1117 10:11:50.797947 # Registered handlers for all signals.
1118 10:11:50.798384 # Detected MINSTKSIGSZ:10000
1119 10:11:50.798483 # Testcase initialized.
1120 10:11:50.798564 # uc context validated.
1121 10:11:50.798640 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1122 10:11:50.798716 # Handled SIG_COPYCTX
1123 10:11:50.798805 # Available space:3536
1124 10:11:50.799512 # uc context validated.
1125 10:11:50.799837 # Using badly built context - ERR: Bad size for esr_context
1126 10:11:50.799961 # SIG_OK -- SP:0xFFFFD2421050 si_addr@:0xffffd2421050 si_code:2 token@:0xffffd241fdf0 offset:-4704
1127 10:11:50.800053 # ==>> completed. PASS(1)
1128 10:11:50.800386 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1129 10:11:50.800496 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD241FDF0
1130 10:11:50.809730 ok 4 selftests: arm64: fake_sigreturn_bad_size
1131 10:11:50.873940 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1132 10:11:50.929211 # Registered handlers for all signals.
1133 10:11:50.929457 # Detected MINSTKSIGSZ:10000
1134 10:11:50.929795 # Testcase initialized.
1135 10:11:50.929904 # uc context validated.
1136 10:11:50.929995 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1137 10:11:50.930086 # Handled SIG_COPYCTX
1138 10:11:50.930174 # Available space:3536
1139 10:11:50.930261 # Using badly built context - ERR: Bad size for terminator
1140 10:11:50.930346 # SIG_OK -- SP:0xFFFFC902DC80 si_addr@:0xffffc902dc80 si_code:2 token@:0xffffc902ca20 offset:-4704
1141 10:11:50.930637 # ==>> completed. PASS(1)
1142 10:11:50.930740 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1143 10:11:50.930833 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC902CA20
1144 10:11:50.938184 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1145 10:11:51.005968 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1146 10:11:51.097973 # Registered handlers for all signals.
1147 10:11:51.098445 # Detected MINSTKSIGSZ:10000
1148 10:11:51.098578 # Testcase initialized.
1149 10:11:51.098723 # uc context validated.
1150 10:11:51.098828 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1151 10:11:51.098947 # Handled SIG_COPYCTX
1152 10:11:51.099050 # Available space:3536
1153 10:11:51.099145 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1154 10:11:51.099259 # SIG_OK -- SP:0xFFFFFC63D7C0 si_addr@:0xfffffc63d7c0 si_code:2 token@:0xfffffc63c560 offset:-4704
1155 10:11:51.099396 # ==>> completed. PASS(1)
1156 10:11:51.100243 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1157 10:11:51.100637 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFC63C560
1158 10:11:51.110053 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1159 10:11:51.171212 # selftests: arm64: fake_sigreturn_misaligned_sp
1160 10:11:51.256001 # Registered handlers for all signals.
1161 10:11:51.256240 # Detected MINSTKSIGSZ:10000
1162 10:11:51.256338 # Testcase initialized.
1163 10:11:51.256420 # uc context validated.
1164 10:11:51.256524 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1165 10:11:51.256669 # Handled SIG_COPYCTX
1166 10:11:51.260576 # SIG_OK -- SP:0xFFFFDA1864E3 si_addr@:0xffffda1864e3 si_code:2 token@:0xffffda1864e3 offset:0
1167 10:11:51.260918 # ==>> completed. PASS(1)
1168 10:11:51.261026 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1169 10:11:51.261442 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDA1864E3
1170 10:11:51.270543 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1171 10:11:51.327865 # selftests: arm64: fake_sigreturn_missing_fpsimd
1172 10:11:51.389919 # Registered handlers for all signals.
1173 10:11:51.390160 # Detected MINSTKSIGSZ:10000
1174 10:11:51.390253 # Testcase initialized.
1175 10:11:51.390342 # uc context validated.
1176 10:11:51.390430 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1177 10:11:51.390736 # Handled SIG_COPYCTX
1178 10:11:51.390847 # Mangling template header. Spare space:4096
1179 10:11:51.390940 # Using badly built context - ERR: Missing FPSIMD
1180 10:11:51.393138 # SIG_OK -- SP:0xFFFFD2CB2D60 si_addr@:0xffffd2cb2d60 si_code:2 token@:0xffffd2cb1b00 offset:-4704
1181 10:11:51.393261 # ==>> completed. PASS(1)
1182 10:11:51.393550 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1183 10:11:51.393672 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD2CB1B00
1184 10:11:51.405309 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1185 10:11:51.482131 # selftests: arm64: fake_sigreturn_sme_change_vl
1186 10:11:51.572201 # Registered handlers for all signals.
1187 10:11:51.572805 # Detected MINSTKSIGSZ:10000
1188 10:11:51.572983 # Required Features: [ SME ] supported
1189 10:11:51.573150 # Incompatible Features: [] absent
1190 10:11:51.573314 # Testcase initialized.
1191 10:11:51.573456 # uc context validated.
1192 10:11:51.576608 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1193 10:11:51.576810 # Handled SIG_COPYCTX
1194 10:11:51.576973 # Attempting to change VL from 16 to 256
1195 10:11:51.577731 # SIG_OK -- SP:0xFFFFE34B6280 si_addr@:0xffffe34b6280 si_code:2 token@:0xffffe34b5020 offset:-4704
1196 10:11:51.578191 # ==>> completed. PASS(1)
1197 10:11:51.578351 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1198 10:11:51.578479 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE34B5020
1199 10:11:51.588542 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1200 10:11:51.666679 # selftests: arm64: fake_sigreturn_sve_change_vl
1201 10:11:51.730003 # Registered handlers for all signals.
1202 10:11:51.730665 # Detected MINSTKSIGSZ:10000
1203 10:11:51.730780 # Required Features: [ SVE ] supported
1204 10:11:51.730886 # Incompatible Features: [] absent
1205 10:11:51.730984 # Testcase initialized.
1206 10:11:51.731082 # uc context validated.
1207 10:11:51.731193 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1208 10:11:51.731270 # Handled SIG_COPYCTX
1209 10:11:51.731346 # Attempting to change VL from 16 to 256
1210 10:11:51.734666 # SIG_OK -- SP:0xFFFFCB5F2840 si_addr@:0xffffcb5f2840 si_code:2 token@:0xffffcb5f15e0 offset:-4704
1211 10:11:51.734791 # ==>> completed. PASS(1)
1212 10:11:51.734892 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1213 10:11:51.735560 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCB5F15E0
1214 10:11:51.745160 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1215 10:11:51.829729 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1216 10:11:51.910054 # Registered handlers for all signals.
1217 10:11:51.910510 # Detected MINSTKSIGSZ:10000
1218 10:11:51.910621 # Testcase initialized.
1219 10:11:51.910719 # uc context validated.
1220 10:11:51.910792 # Handled SIG_TRIG
1221 10:11:51.911018 # SIG_OK -- SP:0xFFFFF1B2AC00 si_addr@:0xfffff1b2ac00 si_code:2 token@:(nil) offset:-281474736761856
1222 10:11:51.911103 # ==>> completed. PASS(1)
1223 10:11:51.911168 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1224 10:11:51.922379 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1225 10:11:51.974773 # selftests: arm64: mangle_pstate_invalid_daif_bits
1226 10:11:52.036322 # Registered handlers for all signals.
1227 10:11:52.036849 # Detected MINSTKSIGSZ:10000
1228 10:11:52.036959 # Testcase initialized.
1229 10:11:52.037052 # uc context validated.
1230 10:11:52.037143 # Handled SIG_TRIG
1231 10:11:52.037415 # SIG_OK -- SP:0xFFFFC4992A90 si_addr@:0xffffc4992a90 si_code:2 token@:(nil) offset:-281473980115600
1232 10:11:52.037523 # ==>> completed. PASS(1)
1233 10:11:52.037614 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1234 10:11:52.045235 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1235 10:11:52.103032 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1236 10:11:52.181993 # Registered handlers for all signals.
1237 10:11:52.182224 # Detected MINSTKSIGSZ:10000
1238 10:11:52.182323 # Testcase initialized.
1239 10:11:52.182622 # uc context validated.
1240 10:11:52.182728 # Handled SIG_TRIG
1241 10:11:52.182816 # SIG_OK -- SP:0xFFFFE50DF140 si_addr@:0xffffe50df140 si_code:2 token@:(nil) offset:-281474524639552
1242 10:11:52.182900 # ==>> completed. PASS(1)
1243 10:11:52.183003 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1244 10:11:52.194154 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1245 10:11:52.249702 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1246 10:11:52.302001 # Registered handlers for all signals.
1247 10:11:52.302463 # Detected MINSTKSIGSZ:10000
1248 10:11:52.302571 # Testcase initialized.
1249 10:11:52.302662 # uc context validated.
1250 10:11:52.302749 # Handled SIG_TRIG
1251 10:11:52.302835 # SIG_OK -- SP:0xFFFFE34B0F40 si_addr@:0xffffe34b0f40 si_code:2 token@:(nil) offset:-281474495090496
1252 10:11:52.302941 # ==>> completed. PASS(1)
1253 10:11:52.303030 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1254 10:11:52.311225 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1255 10:11:52.359004 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1256 10:11:52.409713 # Registered handlers for all signals.
1257 10:11:52.409962 # Detected MINSTKSIGSZ:10000
1258 10:11:52.410056 # Testcase initialized.
1259 10:11:52.410362 # uc context validated.
1260 10:11:52.410467 # Handled SIG_TRIG
1261 10:11:52.410558 # SIG_OK -- SP:0xFFFFE88A2FE0 si_addr@:0xffffe88a2fe0 si_code:2 token@:(nil) offset:-281474583113696
1262 10:11:52.410648 # ==>> completed. PASS(1)
1263 10:11:52.410737 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1264 10:11:52.418435 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1265 10:11:52.466423 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1266 10:11:52.516794 # Registered handlers for all signals.
1267 10:11:52.517164 # Detected MINSTKSIGSZ:10000
1268 10:11:52.517357 # Testcase initialized.
1269 10:11:52.517722 # uc context validated.
1270 10:11:52.517858 # Handled SIG_TRIG
1271 10:11:52.517981 # SIG_OK -- SP:0xFFFFFA24BFF0 si_addr@:0xfffffa24bff0 si_code:2 token@:(nil) offset:-281474878455792
1272 10:11:52.518100 # ==>> completed. PASS(1)
1273 10:11:52.518214 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1274 10:11:52.525482 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1275 10:11:52.574624 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1276 10:11:52.624568 # Registered handlers for all signals.
1277 10:11:52.624818 # Detected MINSTKSIGSZ:10000
1278 10:11:52.625133 # Testcase initialized.
1279 10:11:52.625245 # uc context validated.
1280 10:11:52.625336 # Handled SIG_TRIG
1281 10:11:52.625423 # SIG_OK -- SP:0xFFFFC1935210 si_addr@:0xffffc1935210 si_code:2 token@:(nil) offset:-281473929400848
1282 10:11:52.625511 # ==>> completed. PASS(1)
1283 10:11:52.625597 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1284 10:11:52.633419 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1285 10:11:52.682524 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1286 10:11:52.734087 # Registered handlers for all signals.
1287 10:11:52.734337 # Detected MINSTKSIGSZ:10000
1288 10:11:52.734438 # Testcase initialized.
1289 10:11:52.734735 # uc context validated.
1290 10:11:52.734831 # Handled SIG_TRIG
1291 10:11:52.736724 # SIG_OK -- SP:0xFFFFD3FD7520 si_addr@:0xffffd3fd7520 si_code:2 token@:(nil) offset:-281474238346528
1292 10:11:52.737047 # ==>> completed. PASS(1)
1293 10:11:52.737144 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1294 10:11:52.744187 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1295 10:11:52.791640 # selftests: arm64: sme_trap_no_sm
1296 10:11:52.911711 # Registered handlers for all signals.
1297 10:11:52.912139 # Detected MINSTKSIGSZ:10000
1298 10:11:52.912246 # Required Features: [ SME ] supported
1299 10:11:52.912341 # Incompatible Features: [] absent
1300 10:11:52.912431 # Testcase initialized.
1301 10:11:52.914634 # SIG_OK -- SP:0xFFFFFBF9A330 si_addr@:0xaaaab73e2514 si_code:1 token@:(nil) offset:-187650195465492
1302 10:11:52.914937 # ==>> completed. PASS(1)
1303 10:11:52.915056 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1304 10:11:52.929238 ok 19 selftests: arm64: sme_trap_no_sm
1305 10:11:53.026101 # selftests: arm64: sme_trap_non_streaming
1306 10:11:53.146642 # Registered handlers for all signals.
1307 10:11:53.146882 # Detected MINSTKSIGSZ:10000
1308 10:11:53.146991 # Required Features: [] NOT supported
1309 10:11:53.147123 # Incompatible Features: [] supported
1310 10:11:53.147258 # ==>> completed. SKIP.
1311 10:11:53.152810 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1312 10:11:53.172231 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1313 10:11:53.224263 # selftests: arm64: sme_trap_za
1314 10:11:53.277989 # Registered handlers for all signals.
1315 10:11:53.278225 # Detected MINSTKSIGSZ:10000
1316 10:11:53.278561 # Testcase initialized.
1317 10:11:53.278772 # SIG_OK -- SP:0xFFFFFCB8B2F0 si_addr@:0xaaaacf632510 si_code:1 token@:(nil) offset:-187650600543504
1318 10:11:53.278955 # ==>> completed. PASS(1)
1319 10:11:53.279124 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1320 10:11:53.285427 ok 21 selftests: arm64: sme_trap_za
1321 10:11:53.335249 # selftests: arm64: sme_vl
1322 10:11:53.388282 # Registered handlers for all signals.
1323 10:11:53.388618 # Detected MINSTKSIGSZ:10000
1324 10:11:53.389049 # Required Features: [ SME ] supported
1325 10:11:53.389232 # Incompatible Features: [] absent
1326 10:11:53.389364 # Testcase initialized.
1327 10:11:53.389481 # uc context validated.
1328 10:11:53.389597 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1329 10:11:53.389732 # Handled SIG_COPYCTX
1330 10:11:53.389848 # got expected VL 32
1331 10:11:53.389963 # ==>> completed. PASS(1)
1332 10:11:53.390078 # # SME VL :: Check that we get the right SME VL reported
1333 10:11:53.398787 ok 22 selftests: arm64: sme_vl
1334 10:11:53.480994 # selftests: arm64: ssve_regs
1335 10:11:53.732610 # Registered handlers for all signals.
1336 10:11:53.732868 # Detected MINSTKSIGSZ:10000
1337 10:11:53.732965 # Required Features: [ SME FA64 ] supported
1338 10:11:53.733053 # Incompatible Features: [] absent
1339 10:11:53.733140 # Testcase initialized.
1340 10:11:53.733224 # Testing VL 256
1341 10:11:53.733525 # Validating EXTRA...
1342 10:11:53.735130 # uc context validated.
1343 10:11:53.735636 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1344 10:11:53.735741 # Handled SIG_COPYCTX
1345 10:11:53.735844 # Got expected size 8752 and VL 256
1346 10:11:53.735932 # Testing VL 128
1347 10:11:53.736221 # Validating EXTRA...
1348 10:11:53.736320 # uc context validated.
1349 10:11:53.736422 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1350 10:11:53.736511 # Handled SIG_COPYCTX
1351 10:11:53.736592 # Got expected size 4384 and VL 128
1352 10:11:53.736695 # Testing VL 64
1353 10:11:53.736780 # uc context validated.
1354 10:11:53.736864 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1355 10:11:53.736947 # Handled SIG_COPYCTX
1356 10:11:53.745261 # Got expected size 2208 and VL 64
1357 10:11:53.745514 # Testing VL 32
1358 10:11:53.745631 # uc context validated.
1359 10:11:53.745984 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1360 10:11:53.746088 # Handled SIG_COPYCTX
1361 10:11:53.746180 # Got expected size 1120 and VL 32
1362 10:11:53.746270 # Testing VL 16
1363 10:11:53.746372 # uc context validated.
1364 10:11:53.746448 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1365 10:11:53.746525 # Handled SIG_COPYCTX
1366 10:11:53.746595 # Got expected size 576 and VL 16
1367 10:11:53.746677 # ==>> completed. PASS(1)
1368 10:11:53.746747 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1369 10:11:53.746820 ok 23 selftests: arm64: ssve_regs
1370 10:11:53.824311 # selftests: arm64: sve_regs
1371 10:11:54.317744 # Registered handlers for all signals.
1372 10:11:54.318201 # Detected MINSTKSIGSZ:10000
1373 10:11:54.318314 # Required Features: [ SVE ] supported
1374 10:11:54.320280 # Incompatible Features: [] absent
1375 10:11:54.320622 # Testcase initialized.
1376 10:11:54.320730 # Testing VL 256
1377 10:11:54.320834 # Validating EXTRA...
1378 10:11:54.320933 # uc context validated.
1379 10:11:54.321041 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1380 10:11:54.321133 # Handled SIG_COPYCTX
1381 10:11:54.321222 # Got expected size 8752 and VL 256
1382 10:11:54.321300 # Testing VL 240
1383 10:11:54.321396 # Validating EXTRA...
1384 10:11:54.321470 # uc context validated.
1385 10:11:54.321544 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1386 10:11:54.321637 # Handled SIG_COPYCTX
1387 10:11:54.321719 # Got expected size 8208 and VL 240
1388 10:11:54.321793 # Testing VL 224
1389 10:11:54.321866 # Validating EXTRA...
1390 10:11:54.321957 # uc context validated.
1391 10:11:54.322027 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1392 10:11:54.322101 # Handled SIG_COPYCTX
1393 10:11:54.330044 # Got expected size 7664 and VL 224
1394 10:11:54.330235 # Testing VL 208
1395 10:11:54.330553 # Validating EXTRA...
1396 10:11:54.330653 # uc context validated.
1397 10:11:54.330767 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1398 10:11:54.330854 # Handled SIG_COPYCTX
1399 10:11:54.330937 # Got expected size 7120 and VL 208
1400 10:11:54.331013 # Testing VL 192
1401 10:11:54.331081 # Validating EXTRA...
1402 10:11:54.331162 # uc context validated.
1403 10:11:54.331231 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1404 10:11:54.331314 # Handled SIG_COPYCTX
1405 10:11:54.331409 # Got expected size 6576 and VL 192
1406 10:11:54.331522 # Testing VL 176
1407 10:11:54.331665 # Validating EXTRA...
1408 10:11:54.331766 # uc context validated.
1409 10:11:54.331869 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1410 10:11:54.332163 # Handled SIG_COPYCTX
1411 10:11:54.332260 # Got expected size 6032 and VL 176
1412 10:11:54.332573 # Testing VL 160
1413 10:11:54.332670 # Validating EXTRA...
1414 10:11:54.332747 # uc context validated.
1415 10:11:54.332823 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1416 10:11:54.332899 # Handled SIG_COPYCTX
1417 10:11:54.332975 # Got expected size 5488 and VL 160
1418 10:11:54.333065 # Testing VL 144
1419 10:11:54.333138 # Validating EXTRA...
1420 10:11:54.333874 # uc context validated.
1421 10:11:54.333964 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1422 10:11:54.334033 # Handled SIG_COPYCTX
1423 10:11:54.334093 # Got expected size 4944 and VL 144
1424 10:11:54.334152 # Testing VL 128
1425 10:11:54.334210 # Validating EXTRA...
1426 10:11:54.334268 # uc context validated.
1427 10:11:54.334326 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1428 10:11:54.334384 # Handled SIG_COPYCTX
1429 10:11:54.334447 # Got expected size 4384 and VL 128
1430 10:11:54.334505 # Testing VL 112
1431 10:11:54.334563 # Validating EXTRA...
1432 10:11:54.334620 # uc context validated.
1433 10:11:54.334678 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1434 10:11:54.334737 # Handled SIG_COPYCTX
1435 10:11:54.334794 # Got expected size 3840 and VL 112
1436 10:11:54.334853 # Testing VL 96
1437 10:11:54.335111 # uc context validated.
1438 10:11:54.335222 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1439 10:11:54.338811 # Handled SIG_COPYCTX
1440 10:11:54.339013 # Got expected size 3296 and VL 96
1441 10:11:54.339316 # Testing VL 80
1442 10:11:54.339431 # uc context validated.
1443 10:11:54.339540 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1444 10:11:54.339654 # Handled SIG_COPYCTX
1445 10:11:54.339754 # Got expected size 2752 and VL 80
1446 10:11:54.339841 # Testing VL 64
1447 10:11:54.339922 # uc context validated.
1448 10:11:54.340021 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1449 10:11:54.340109 # Handled SIG_COPYCTX
1450 10:11:54.340193 # Got expected size 2208 and VL 64
1451 10:11:54.340270 # Testing VL 48
1452 10:11:54.340331 # uc context validated.
1453 10:11:54.340403 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1454 10:11:54.340494 # Handled SIG_COPYCTX
1455 10:11:54.340563 # Got expected size 1664 and VL 48
1456 10:11:54.340634 # Testing VL 32
1457 10:11:54.340696 # uc context validated.
1458 10:11:54.340770 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1459 10:11:54.340832 # Handled SIG_COPYCTX
1460 10:11:54.340891 # Got expected size 1120 and VL 32
1461 10:11:54.340964 # Testing VL 16
1462 10:11:54.341060 # uc context validated.
1463 10:11:54.341142 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1464 10:11:54.341222 # Handled SIG_COPYCTX
1465 10:11:54.341301 # Got expected size 576 and VL 16
1466 10:11:54.341382 # ==>> completed. PASS(1)
1467 10:11:54.341463 # # SVE registers :: Check that we get the right SVE registers reported
1468 10:11:54.341562 ok 24 selftests: arm64: sve_regs
1469 10:11:54.392934 # selftests: arm64: sve_vl
1470 10:11:54.465524 # Registered handlers for all signals.
1471 10:11:54.465815 # Detected MINSTKSIGSZ:10000
1472 10:11:54.466006 # Required Features: [ SVE ] supported
1473 10:11:54.466179 # Incompatible Features: [] absent
1474 10:11:54.466332 # Testcase initialized.
1475 10:11:54.466454 # uc context validated.
1476 10:11:54.466566 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1477 10:11:54.466680 # Handled SIG_COPYCTX
1478 10:11:54.466791 # got expected VL 64
1479 10:11:54.466902 # ==>> completed. PASS(1)
1480 10:11:54.467013 # # SVE VL :: Check that we get the right SVE VL reported
1481 10:11:54.474120 ok 25 selftests: arm64: sve_vl
1482 10:11:54.525530 # selftests: arm64: za_no_regs
1483 10:11:54.591700 # Registered handlers for all signals.
1484 10:11:54.592037 # Detected MINSTKSIGSZ:10000
1485 10:11:54.592479 # Required Features: [ SME ] supported
1486 10:11:54.592685 # Incompatible Features: [] absent
1487 10:11:54.592860 # Testcase initialized.
1488 10:11:54.593026 # Testing VL 256
1489 10:11:54.593193 # uc context validated.
1490 10:11:54.593356 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1491 10:11:54.593522 # Handled SIG_COPYCTX
1492 10:11:54.593700 # Got expected size 16 and VL 256
1493 10:11:54.593870 # Testing VL 128
1494 10:11:54.594406 # uc context validated.
1495 10:11:54.595477 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1496 10:11:54.595716 # Handled SIG_COPYCTX
1497 10:11:54.595947 # Got expected size 16 and VL 128
1498 10:11:54.596169 # Testing VL 64
1499 10:11:54.596382 # uc context validated.
1500 10:11:54.596569 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1501 10:11:54.596739 # Handled SIG_COPYCTX
1502 10:11:54.596884 # Got expected size 16 and VL 64
1503 10:11:54.597025 # Testing VL 32
1504 10:11:54.597165 # uc context validated.
1505 10:11:54.597344 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1506 10:11:54.597483 # Handled SIG_COPYCTX
1507 10:11:54.597623 # Got expected size 16 and VL 32
1508 10:11:54.597778 # Testing VL 16
1509 10:11:54.597919 # uc context validated.
1510 10:11:54.598058 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1511 10:11:54.598198 # Handled SIG_COPYCTX
1512 10:11:54.598337 # Got expected size 16 and VL 16
1513 10:11:54.598477 # ==>> completed. PASS(1)
1514 10:11:54.603999 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1515 10:11:54.604500 ok 26 selftests: arm64: za_no_regs
1516 10:11:54.661862 # selftests: arm64: za_regs
1517 10:11:54.855411 # Registered handlers for all signals.
1518 10:11:54.855652 # Detected MINSTKSIGSZ:10000
1519 10:11:54.855747 # Required Features: [ SME ] supported
1520 10:11:54.855837 # Incompatible Features: [] absent
1521 10:11:54.856238 # Testcase initialized.
1522 10:11:54.856393 # Testing VL 256
1523 10:11:54.856481 # Validating EXTRA...
1524 10:11:54.856567 # uc context validated.
1525 10:11:54.856658 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1526 10:11:54.856761 # Handled SIG_COPYCTX
1527 10:11:54.856864 # Got expected size 65552 and VL 256
1528 10:11:54.856967 # Testing VL 128
1529 10:11:54.857061 # Validating EXTRA...
1530 10:11:54.857366 # uc context validated.
1531 10:11:54.857719 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1532 10:11:54.857823 # Handled SIG_COPYCTX
1533 10:11:54.857910 # Got expected size 16400 and VL 128
1534 10:11:54.857994 # Testing VL 64
1535 10:11:54.858077 # Validating EXTRA...
1536 10:11:54.858164 # uc context validated.
1537 10:11:54.858248 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1538 10:11:54.858332 # Handled SIG_COPYCTX
1539 10:11:54.858415 # Got expected size 4112 and VL 64
1540 10:11:54.858499 # Testing VL 32
1541 10:11:54.858580 # uc context validated.
1542 10:11:54.858661 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1543 10:11:54.858744 # Handled SIG_COPYCTX
1544 10:11:54.858826 # Got expected size 1040 and VL 32
1545 10:11:54.858911 # Testing VL 16
1546 10:11:54.859016 # uc context validated.
1547 10:11:54.859102 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1548 10:11:54.859186 # Handled SIG_COPYCTX
1549 10:11:54.859270 # Got expected size 272 and VL 16
1550 10:11:54.859359 # ==>> completed. PASS(1)
1551 10:11:54.859444 # # ZA register :: Check that we get the right ZA registers reported
1552 10:11:54.872282 ok 27 selftests: arm64: za_regs
1553 10:11:54.941507 # selftests: arm64: pac
1554 10:11:55.262968 # TAP version 13
1555 10:11:55.263216 # 1..7
1556 10:11:55.263528 # # Starting 7 tests from 1 test cases.
1557 10:11:55.263634 # # RUN global.corrupt_pac ...
1558 10:11:55.263727 # # OK global.corrupt_pac
1559 10:11:55.263808 # ok 1 global.corrupt_pac
1560 10:11:55.263893 # # RUN global.pac_instructions_not_nop ...
1561 10:11:55.263994 # # OK global.pac_instructions_not_nop
1562 10:11:55.264081 # ok 2 global.pac_instructions_not_nop
1563 10:11:55.264162 # # RUN global.pac_instructions_not_nop_generic ...
1564 10:11:55.264260 # # OK global.pac_instructions_not_nop_generic
1565 10:11:55.264343 # ok 3 global.pac_instructions_not_nop_generic
1566 10:11:55.264636 # # RUN global.single_thread_different_keys ...
1567 10:11:55.264753 # # OK global.single_thread_different_keys
1568 10:11:55.264853 # ok 4 global.single_thread_different_keys
1569 10:11:55.264953 # # RUN global.exec_changed_keys ...
1570 10:11:55.265059 # # OK global.exec_changed_keys
1571 10:11:55.265168 # ok 5 global.exec_changed_keys
1572 10:11:55.265481 # # RUN global.context_switch_keep_keys ...
1573 10:11:55.265582 # # OK global.context_switch_keep_keys
1574 10:11:55.265717 # ok 6 global.context_switch_keep_keys
1575 10:11:55.265825 # # RUN global.context_switch_keep_keys_generic ...
1576 10:11:55.276427 # # OK global.context_switch_keep_keys_generic
1577 10:11:55.276913 # ok 7 global.context_switch_keep_keys_generic
1578 10:11:55.277026 # # PASSED: 7 / 7 tests passed.
1579 10:11:55.277117 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1580 10:11:55.277208 ok 28 selftests: arm64: pac
1581 10:11:55.343302 # selftests: arm64: fp-stress
1582 10:12:14.547310 # TAP version 13
1583 10:12:14.547615 # 1..27
1584 10:12:14.547819 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1585 10:12:14.547968 # # Will run for 10s
1586 10:12:14.548087 # # Started FPSIMD-0-0
1587 10:12:14.548200 # # Started SVE-VL-256-0
1588 10:12:14.548312 # # Started SVE-VL-240-0
1589 10:12:14.548423 # # Started SVE-VL-224-0
1590 10:12:14.548534 # # Started SVE-VL-208-0
1591 10:12:14.548653 # # Started SVE-VL-192-0
1592 10:12:14.548788 # # Started SVE-VL-176-0
1593 10:12:14.548903 # # Started SVE-VL-160-0
1594 10:12:14.551088 # # Started SVE-VL-144-0
1595 10:12:14.551465 # # Started SVE-VL-128-0
1596 10:12:14.551644 # # Started SVE-VL-112-0
1597 10:12:14.551800 # # Started SVE-VL-96-0
1598 10:12:14.551919 # # Started SVE-VL-80-0
1599 10:12:14.552041 # # Started SVE-VL-64-0
1600 10:12:14.552152 # # Started SVE-VL-48-0
1601 10:12:14.552261 # # Started SVE-VL-32-0
1602 10:12:14.552369 # # Started SVE-VL-16-0
1603 10:12:14.552506 # # Started SSVE-VL-256-0
1604 10:12:14.552621 # # Started ZA-VL-256-0
1605 10:12:14.552732 # # Started SSVE-VL-128-0
1606 10:12:14.552843 # # Started ZA-VL-128-0
1607 10:12:14.552953 # # Started SSVE-VL-64-0
1608 10:12:14.553062 # # Started ZA-VL-64-0
1609 10:12:14.555694 # # SVE-VL-256-0: Vector length: 2048 bits
1610 10:12:14.555896 # # SVE-VL-256-0: PID: 908
1611 10:12:14.556267 # # FPSIMD-0-0: Vector length: 128 bits
1612 10:12:14.556399 # # FPSIMD-0-0: PID: 907
1613 10:12:14.556518 # # SVE-VL-224-0: Vector length: 1792 bits
1614 10:12:14.559534 # # SVE-VL-224-0: PID: 910
1615 10:12:14.560023 # # SVE-VL-208-0: Vector length: 1664 bits
1616 10:12:14.560177 # # SVE-VL-208-0: PID: 911
1617 10:12:14.560295 # # SVE-VL-128-0: Vector length: 1024 bits
1618 10:12:14.560408 # # SVE-VL-128-0: PID: 916
1619 10:12:14.561221 # # SVE-VL-240-0: Vector length: 1920 bits
1620 10:12:14.561333 # # SVE-VL-240-0: PID: 909
1621 10:12:14.561440 # # SVE-VL-112-0: Vector length: 896 bits
1622 10:12:14.561531 # # SVE-VL-112-0: PID: 917
1623 10:12:14.561630 # # Started SSVE-VL-32-0
1624 10:12:14.561943 # # SVE-VL-160-0: Vector length: 1280 bits
1625 10:12:14.562043 # # SVE-VL-160-0: PID: 914
1626 10:12:14.562130 # # SVE-VL-96-0: Vector length: 768 bits
1627 10:12:14.562211 # # SVE-VL-96-0: PID: 918
1628 10:12:14.562308 # # SVE-VL-144-0: Vector length: 1152 bits
1629 10:12:14.562392 # # SVE-VL-144-0: PID: 915
1630 10:12:14.562489 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1631 10:12:14.562573 # # SVE-VL-192-0: Vector length: 1536 bits
1632 10:12:14.562668 # # SVE-VL-192-0: PID: 912
1633 10:12:14.562969 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1634 10:12:14.563066 # # SSVE-VL-256-0: PID: 924
1635 10:12:14.563149 # # SVE-VL-48-0: Vector length: 384 bits
1636 10:12:14.563247 # # SVE-VL-48-0: PID: 921
1637 10:12:14.563332 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1638 10:12:14.563427 # # SSVE-VL-64-0: PID: 928
1639 10:12:14.563524 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1640 10:12:14.563849 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1641 10:12:14.563952 # # ZA-VL-64-0: PID: 929
1642 10:12:14.564047 # # SVE-VL-176-0: Vector length: 1408 bits
1643 10:12:14.580654 # # SVE-VL-176-0: PID: 913
1644 10:12:14.581093 # # SVE-VL-64-0: Vector length: 512 bits
1645 10:12:14.581196 # # SVE-VL-64-0: PID: 920
1646 10:12:14.581286 # # SVE-VL-16-0: Vector length: 128 bits
1647 10:12:14.581388 # # SVE-VL-16-0: PID: 923
1648 10:12:14.581476 # # SVE-VL-80-0: Vector length: 640 bits
1649 10:12:14.581561 # # SVE-VL-80-0: PID: 919
1650 10:12:14.581668 # # ZA-VL-256-0: PID: 925
1651 10:12:14.581755 # # Started ZA-VL-32-0
1652 10:12:14.581854 # # ZA-VL-128-0: PID: 927
1653 10:12:14.581955 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1654 10:12:14.582040 # # SSVE-VL-128-0: PID: 926
1655 10:12:14.582135 # # SVE-VL-32-0: Vector length: 256 bits
1656 10:12:14.582232 # # SVE-VL-32-0: PID: 922
1657 10:12:14.582329 # # Started SSVE-VL-16-0
1658 10:12:14.582624 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1659 10:12:14.582725 # # SSVE-VL-32-0: PID: 930
1660 10:12:14.582825 # # Started ZA-VL-16-0
1661 10:12:14.582927 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1662 10:12:14.583023 # # ZA-VL-32-0: PID: 931
1663 10:12:14.583316 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1664 10:12:14.583417 # # SSVE-VL-16-0: PID: 932
1665 10:12:14.583517 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1666 10:12:14.583617 # # ZA-VL-16-0: PID: 933
1667 10:12:14.583701 # # Finishing up...
1668 10:12:14.584054 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=3384, signals=9
1669 10:12:14.597864 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=5759, signals=9
1670 10:12:14.598448 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=4860, signals=9
1671 10:12:14.598631 # ok 1 FPSIMD-0-0
1672 10:12:14.598837 # ok 2 SVE-VL-256-0
1673 10:12:14.599019 # ok 3 SVE-VL-240-0
1674 10:12:14.599181 # ok 4 SVE-VL-224-0
1675 10:12:14.599328 # ok 5 SVE-VL-208-0
1676 10:12:14.599513 # ok 6 SVE-VL-192-0
1677 10:12:14.599663 # ok 7 SVE-VL-176-0
1678 10:12:14.599835 # ok 8 SVE-VL-160-0
1679 10:12:14.599978 # ok 9 SVE-VL-144-0
1680 10:12:14.600122 # ok 10 SVE-VL-128-0
1681 10:12:14.600245 # ok 11 SVE-VL-112-0
1682 10:12:14.600357 # ok 12 SVE-VL-96-0
1683 10:12:14.600469 # ok 13 SVE-VL-80-0
1684 10:12:14.600581 # ok 14 SVE-VL-64-0
1685 10:12:14.600692 # ok 15 SVE-VL-48-0
1686 10:12:14.600804 # ok 16 SVE-VL-32-0
1687 10:12:14.600916 # ok 17 SVE-VL-16-0
1688 10:12:14.601026 # ok 18 SSVE-VL-256-0
1689 10:12:14.601137 # ok 19 ZA-VL-256-0
1690 10:12:14.601248 # ok 20 SSVE-VL-128-0
1691 10:12:14.601359 # ok 21 ZA-VL-128-0
1692 10:12:14.601471 # ok 22 SSVE-VL-64-0
1693 10:12:14.601581 # ok 23 ZA-VL-64-0
1694 10:12:14.601787 # ok 24 SSVE-VL-32-0
1695 10:12:14.601985 # ok 25 ZA-VL-32-0
1696 10:12:14.602167 # ok 26 SSVE-VL-16-0
1697 10:12:14.602346 # ok 27 ZA-VL-16-0
1698 10:12:14.602567 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=5676, signals=10
1699 10:12:14.602710 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=1116, signals=7
1700 10:12:14.635417 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=1355, signals=10
1701 10:12:14.635867 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=6690, signals=10
1702 10:12:14.635978 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=662, signals=10
1703 10:12:14.636078 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=3166, signals=9
1704 10:12:14.701503 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=3319, signals=9
1705 10:12:14.701951 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=7547, signals=10
1706 10:12:14.702051 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=13424, signals=10
1707 10:12:14.702138 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=937, signals=7
1708 10:12:14.702236 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=2940, signals=9
1709 10:12:14.702320 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=9100, signals=10
1710 10:12:14.702420 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=7717, signals=7
1711 10:12:14.702705 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=8331, signals=10
1712 10:12:14.702843 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=4191, signals=9
1713 10:12:14.703128 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=4839, signals=9
1714 10:12:14.703413 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=2873, signals=9
1715 10:12:14.703515 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=4388, signals=10
1716 10:12:14.703615 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=9236, signals=10
1717 10:12:14.703896 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=257, signals=10
1718 10:12:14.703996 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=5916, signals=10
1719 10:12:14.708473 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=3122, signals=9
1720 10:12:14.708876 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=3255, signals=9
1721 10:12:14.709043 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2904, signals=10
1722 10:12:14.709195 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1723 10:12:14.709318 ok 29 selftests: arm64: fp-stress
1724 10:12:14.837815 # selftests: arm64: sve-ptrace
1725 10:12:14.959504 # TAP version 13
1726 10:12:14.959804 # 1..4104
1727 10:12:14.960264 # # Parent is 950, child is 951
1728 10:12:14.960437 # ok 1 SVE FPSIMD set via SVE: 0
1729 10:12:14.960611 # ok 2 SVE get_fpsimd() gave same state
1730 10:12:14.960809 # ok 3 SVE SVE_PT_VL_INHERIT set
1731 10:12:14.960981 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1732 10:12:14.961154 # ok 5 Set SVE VL 16
1733 10:12:14.961337 # ok 6 Set and get SVE data for VL 16
1734 10:12:14.961485 # ok 7 Set and get FPSIMD data for SVE VL 16
1735 10:12:14.961684 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1736 10:12:14.961824 # ok 9 Set SVE VL 32
1737 10:12:14.961953 # ok 10 Set and get SVE data for VL 32
1738 10:12:14.962078 # ok 11 Set and get FPSIMD data for SVE VL 32
1739 10:12:14.962205 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1740 10:12:14.962341 # ok 13 Set SVE VL 48
1741 10:12:14.962478 # ok 14 Set and get SVE data for VL 48
1742 10:12:14.962626 # ok 15 Set and get FPSIMD data for SVE VL 48
1743 10:12:14.962763 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1744 10:12:14.962920 # ok 17 Set SVE VL 64
1745 10:12:14.963047 # ok 18 Set and get SVE data for VL 64
1746 10:12:14.963173 # ok 19 Set and get FPSIMD data for SVE VL 64
1747 10:12:14.963370 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1748 10:12:14.963543 # ok 21 Set SVE VL 80
1749 10:12:14.963714 # ok 22 Set and get SVE data for VL 80
1750 10:12:14.963874 # ok 23 Set and get FPSIMD data for SVE VL 80
1751 10:12:14.964030 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1752 10:12:14.964174 # ok 25 Set SVE VL 96
1753 10:12:14.964347 # ok 26 Set and get SVE data for VL 96
1754 10:12:14.964482 # ok 27 Set and get FPSIMD data for SVE VL 96
1755 10:12:14.964597 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1756 10:12:14.964712 # ok 29 Set SVE VL 112
1757 10:12:14.964824 # ok 30 Set and get SVE data for VL 112
1758 10:12:14.964936 # ok 31 Set and get FPSIMD data for SVE VL 112
1759 10:12:14.965046 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1760 10:12:14.965157 # ok 33 Set SVE VL 128
1761 10:12:14.965267 # ok 34 Set and get SVE data for VL 128
1762 10:12:14.965376 # ok 35 Set and get FPSIMD data for SVE VL 128
1763 10:12:14.965487 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1764 10:12:14.965598 # ok 37 Set SVE VL 144
1765 10:12:14.965730 # ok 38 Set and get SVE data for VL 144
1766 10:12:14.965842 # ok 39 Set and get FPSIMD data for SVE VL 144
1767 10:12:14.965952 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1768 10:12:14.966091 # ok 41 Set SVE VL 160
1769 10:12:14.966210 # ok 42 Set and get SVE data for VL 160
1770 10:12:14.966323 # ok 43 Set and get FPSIMD data for SVE VL 160
1771 10:12:14.966434 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1772 10:12:14.966548 # ok 45 Set SVE VL 176
1773 10:12:14.966658 # ok 46 Set and get SVE data for VL 176
1774 10:12:14.966768 # ok 47 Set and get FPSIMD data for SVE VL 176
1775 10:12:14.966878 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1776 10:12:14.967199 # ok 49 Set SVE VL 192
1777 10:12:14.967325 # ok 50 Set and get SVE data for VL 192
1778 10:12:14.969052 # ok 51 Set and get FPSIMD data for SVE VL 192
1779 10:12:14.969506 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1780 10:12:14.969706 # ok 53 Set SVE VL 208
1781 10:12:14.969877 # ok 54 Set and get SVE data for VL 208
1782 10:12:14.970048 # ok 55 Set and get FPSIMD data for SVE VL 208
1783 10:12:14.970251 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1784 10:12:14.970496 # ok 57 Set SVE VL 224
1785 10:12:14.970719 # ok 58 Set and get SVE data for VL 224
1786 10:12:14.970929 # ok 59 Set and get FPSIMD data for SVE VL 224
1787 10:12:14.971141 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1788 10:12:14.971367 # ok 61 Set SVE VL 240
1789 10:12:14.971592 # ok 62 Set and get SVE data for VL 240
1790 10:12:14.971787 # ok 63 Set and get FPSIMD data for SVE VL 240
1791 10:12:14.971948 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1792 10:12:14.972097 # ok 65 Set SVE VL 256
1793 10:12:14.972248 # ok 66 Set and get SVE data for VL 256
1794 10:12:14.972406 # ok 67 Set and get FPSIMD data for SVE VL 256
1795 10:12:14.972527 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1796 10:12:14.972640 # ok 69 Set SVE VL 272
1797 10:12:14.972748 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1798 10:12:14.972857 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1799 10:12:14.972966 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1800 10:12:14.973075 # ok 73 Set SVE VL 288
1801 10:12:14.973182 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1802 10:12:14.973289 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1803 10:12:14.973397 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1804 10:12:14.973509 # ok 77 Set SVE VL 304
1805 10:12:14.973617 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1806 10:12:14.973838 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1807 10:12:14.974030 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1808 10:12:14.974212 # ok 81 Set SVE VL 320
1809 10:12:14.974365 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1810 10:12:14.974504 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1811 10:12:14.976871 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1812 10:12:14.977080 # ok 85 Set SVE VL 336
1813 10:12:14.977484 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1814 10:12:14.977593 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1815 10:12:14.977688 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1816 10:12:14.977778 # ok 89 Set SVE VL 352
1817 10:12:14.977862 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1818 10:12:14.977948 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1819 10:12:14.978046 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1820 10:12:14.978131 # ok 93 Set SVE VL 368
1821 10:12:14.978212 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1822 10:12:14.978293 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1823 10:12:14.978390 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1824 10:12:14.978474 # ok 97 Set SVE VL 384
1825 10:12:14.978570 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1826 10:12:14.978656 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1827 10:12:14.978753 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1828 10:12:14.978836 # ok 101 Set SVE VL 400
1829 10:12:14.979665 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1830 10:12:14.979961 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1831 10:12:14.980053 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1832 10:12:14.980138 # ok 105 Set SVE VL 416
1833 10:12:14.980234 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1834 10:12:14.980316 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1835 10:12:14.987004 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1836 10:12:14.987133 # ok 109 Set SVE VL 432
1837 10:12:14.987425 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1838 10:12:14.987531 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1839 10:12:14.987616 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1840 10:12:14.987703 # ok 113 Set SVE VL 448
1841 10:12:14.987799 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1842 10:12:14.987884 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1843 10:12:14.987965 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1844 10:12:14.988061 # ok 117 Set SVE VL 464
1845 10:12:14.988145 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1846 10:12:14.988238 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1847 10:12:14.988663 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1848 10:12:14.989126 # ok 121 Set SVE VL 480
1849 10:12:14.989326 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1850 10:12:14.989524 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1851 10:12:14.989725 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1852 10:12:14.989908 # ok 125 Set SVE VL 496
1853 10:12:14.990147 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1854 10:12:14.990340 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1855 10:12:14.990518 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1856 10:12:14.990698 # ok 129 Set SVE VL 512
1857 10:12:14.990843 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1858 10:12:14.990980 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1859 10:12:14.991131 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1860 10:12:14.991282 # ok 133 Set SVE VL 528
1861 10:12:14.991431 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1862 10:12:14.991617 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1863 10:12:14.991795 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1864 10:12:14.991952 # ok 137 Set SVE VL 544
1865 10:12:14.992075 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1866 10:12:14.992212 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1867 10:12:14.992331 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1868 10:12:14.992443 # ok 141 Set SVE VL 560
1869 10:12:14.992554 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1870 10:12:14.992669 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1871 10:12:14.992781 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1872 10:12:14.992892 # ok 145 Set SVE VL 576
1873 10:12:14.993001 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1874 10:12:14.993111 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1875 10:12:14.993223 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1876 10:12:14.993334 # ok 149 Set SVE VL 592
1877 10:12:14.993476 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1878 10:12:14.993593 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1879 10:12:14.993795 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1880 10:12:14.993987 # ok 153 Set SVE VL 608
1881 10:12:14.994166 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1882 10:12:14.994344 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1883 10:12:14.994521 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1884 10:12:15.000148 # ok 157 Set SVE VL 624
1885 10:12:15.000529 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1886 10:12:15.000716 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1887 10:12:15.000917 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1888 10:12:15.001059 # ok 161 Set SVE VL 640
1889 10:12:15.001185 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1890 10:12:15.001330 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1891 10:12:15.001460 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1892 10:12:15.001585 # ok 165 Set SVE VL 656
1893 10:12:15.001719 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1894 10:12:15.001870 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1895 10:12:15.001998 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1896 10:12:15.002123 # ok 169 Set SVE VL 672
1897 10:12:15.002245 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1898 10:12:15.002368 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1899 10:12:15.002521 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1900 10:12:15.002651 # ok 173 Set SVE VL 688
1901 10:12:15.002777 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1902 10:12:15.002902 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1903 10:12:15.003026 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1904 10:12:15.003164 # ok 177 Set SVE VL 704
1905 10:12:15.003290 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1906 10:12:15.003426 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1907 10:12:15.003581 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1908 10:12:15.003766 # ok 181 Set SVE VL 720
1909 10:12:15.003927 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1910 10:12:15.004086 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1911 10:12:15.004242 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1912 10:12:15.004380 # ok 185 Set SVE VL 736
1913 10:12:15.004495 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1914 10:12:15.004607 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1915 10:12:15.004716 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1916 10:12:15.004824 # ok 189 Set SVE VL 752
1917 10:12:15.004933 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1918 10:12:15.005041 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1919 10:12:15.005150 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1920 10:12:15.005258 # ok 193 Set SVE VL 768
1921 10:12:15.005365 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1922 10:12:15.005498 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1923 10:12:15.005613 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1924 10:12:15.005831 # ok 197 Set SVE VL 784
1925 10:12:15.006019 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1926 10:12:15.006197 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1927 10:12:15.010671 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1928 10:12:15.010876 # ok 201 Set SVE VL 800
1929 10:12:15.011200 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1930 10:12:15.011427 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1931 10:12:15.011605 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1932 10:12:15.011764 # ok 205 Set SVE VL 816
1933 10:12:15.011922 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1934 10:12:15.012080 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1935 10:12:15.012273 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1936 10:12:15.012407 # ok 209 Set SVE VL 832
1937 10:12:15.012524 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1938 10:12:15.012675 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1939 10:12:15.012832 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1940 10:12:15.013012 # ok 213 Set SVE VL 848
1941 10:12:15.013173 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1942 10:12:15.013332 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1943 10:12:15.013516 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1944 10:12:15.013688 # ok 217 Set SVE VL 864
1945 10:12:15.013888 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1946 10:12:15.014058 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1947 10:12:15.014264 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1948 10:12:15.014440 # ok 221 Set SVE VL 880
1949 10:12:15.014621 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1950 10:12:15.014788 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1951 10:12:15.014924 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1952 10:12:15.015084 # ok 225 Set SVE VL 896
1953 10:12:15.015238 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1954 10:12:15.015396 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1955 10:12:15.015549 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1956 10:12:15.015704 # ok 229 Set SVE VL 912
1957 10:12:15.015858 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1958 10:12:15.016004 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1959 10:12:15.016155 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1960 10:12:15.016286 # ok 233 Set SVE VL 928
1961 10:12:15.016406 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1962 10:12:15.016520 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1963 10:12:15.016635 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1964 10:12:15.016776 # ok 237 Set SVE VL 944
1965 10:12:15.016894 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1966 10:12:15.017007 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1967 10:12:15.017122 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1968 10:12:15.017235 # ok 241 Set SVE VL 960
1969 10:12:15.017346 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1970 10:12:15.017457 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1971 10:12:15.017567 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1972 10:12:15.017734 # ok 245 Set SVE VL 976
1973 10:12:15.017935 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1974 10:12:15.018359 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1975 10:12:15.018554 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1976 10:12:15.018742 # ok 249 Set SVE VL 992
1977 10:12:15.018922 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1978 10:12:15.019102 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1979 10:12:15.019263 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1980 10:12:15.019404 # ok 253 Set SVE VL 1008
1981 10:12:15.019544 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1982 10:12:15.019688 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1983 10:12:15.019829 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1984 10:12:15.019970 # ok 257 Set SVE VL 1024
1985 10:12:15.024193 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1986 10:12:15.024395 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1987 10:12:15.024777 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1988 10:12:15.024978 # ok 261 Set SVE VL 1040
1989 10:12:15.025217 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1990 10:12:15.025377 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1991 10:12:15.025537 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1992 10:12:15.025746 # ok 265 Set SVE VL 1056
1993 10:12:15.025996 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1994 10:12:15.026191 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1995 10:12:15.026410 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1996 10:12:15.026593 # ok 269 Set SVE VL 1072
1997 10:12:15.026743 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
1998 10:12:15.026930 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
1999 10:12:15.027127 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2000 10:12:15.027295 # ok 273 Set SVE VL 1088
2001 10:12:15.027464 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2002 10:12:15.027658 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2003 10:12:15.027873 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2004 10:12:15.028040 # ok 277 Set SVE VL 1104
2005 10:12:15.028159 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2006 10:12:15.028317 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2007 10:12:15.028447 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2008 10:12:15.028560 # ok 281 Set SVE VL 1120
2009 10:12:15.028702 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2010 10:12:15.028822 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2011 10:12:15.028938 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2012 10:12:15.029051 # ok 285 Set SVE VL 1136
2013 10:12:15.029162 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2014 10:12:15.029274 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2015 10:12:15.029386 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2016 10:12:15.029497 # ok 289 Set SVE VL 1152
2017 10:12:15.029611 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2018 10:12:15.029826 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2019 10:12:15.036572 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2020 10:12:15.038884 # ok 293 Set SVE VL 1168
2021 10:12:15.039087 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2022 10:12:15.039340 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2023 10:12:15.039526 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2024 10:12:15.039715 # ok 297 Set SVE VL 1184
2025 10:12:15.039874 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2026 10:12:15.040067 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2027 10:12:15.040221 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2028 10:12:15.040352 # ok 301 Set SVE VL 1200
2029 10:12:15.040470 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2030 10:12:15.040586 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2031 10:12:15.040718 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2032 10:12:15.040890 # ok 305 Set SVE VL 1216
2033 10:12:15.041031 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2034 10:12:15.041150 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2035 10:12:15.041266 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2036 10:12:15.041405 # ok 309 Set SVE VL 1232
2037 10:12:15.043223 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2038 10:12:15.043603 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2039 10:12:15.043755 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2040 10:12:15.043904 # ok 313 Set SVE VL 1248
2041 10:12:15.044065 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2042 10:12:15.044195 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2043 10:12:15.044316 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2044 10:12:15.044432 # ok 317 Set SVE VL 1264
2045 10:12:15.044571 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2046 10:12:15.044703 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2047 10:12:15.044924 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2048 10:12:15.045097 # ok 321 Set SVE VL 1280
2049 10:12:15.045297 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2050 10:12:15.045539 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2051 10:12:15.045737 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2052 10:12:15.045914 # ok 325 Set SVE VL 1296
2053 10:12:15.046097 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2054 10:12:15.046261 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2055 10:12:15.046458 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2056 10:12:15.046626 # ok 329 Set SVE VL 1312
2057 10:12:15.046785 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2058 10:12:15.046945 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2059 10:12:15.047102 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2060 10:12:15.047247 # ok 333 Set SVE VL 1328
2061 10:12:15.047391 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2062 10:12:15.047585 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2063 10:12:15.047772 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2064 10:12:15.047944 # ok 337 Set SVE VL 1344
2065 10:12:15.048100 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2066 10:12:15.048257 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2067 10:12:15.048452 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2068 10:12:15.048631 # ok 341 Set SVE VL 1360
2069 10:12:15.048808 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2070 10:12:15.048979 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2071 10:12:15.049152 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2072 10:12:15.049327 # ok 345 Set SVE VL 1376
2073 10:12:15.049501 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2074 10:12:15.049690 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2075 10:12:15.049862 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2076 10:12:15.050031 # ok 349 Set SVE VL 1392
2077 10:12:15.050243 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2078 10:12:15.050431 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2079 10:12:15.050614 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2080 10:12:15.050789 # ok 353 Set SVE VL 1408
2081 10:12:15.050963 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2082 10:12:15.056804 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2083 10:12:15.057001 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2084 10:12:15.057355 # ok 357 Set SVE VL 1424
2085 10:12:15.057533 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2086 10:12:15.057704 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2087 10:12:15.057895 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2088 10:12:15.058103 # ok 361 Set SVE VL 1440
2089 10:12:15.058339 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2090 10:12:15.058506 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2091 10:12:15.058715 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2092 10:12:15.058887 # ok 365 Set SVE VL 1456
2093 10:12:15.059048 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2094 10:12:15.059209 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2095 10:12:15.059369 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2096 10:12:15.059529 # ok 369 Set SVE VL 1472
2097 10:12:15.059682 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2098 10:12:15.059832 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2099 10:12:15.060028 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2100 10:12:15.060205 # ok 373 Set SVE VL 1488
2101 10:12:15.060356 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2102 10:12:15.060473 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2103 10:12:15.060585 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2104 10:12:15.060698 # ok 377 Set SVE VL 1504
2105 10:12:15.060808 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2106 10:12:15.060919 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2107 10:12:15.061030 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2108 10:12:15.061140 # ok 381 Set SVE VL 1520
2109 10:12:15.061249 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2110 10:12:15.061359 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2111 10:12:15.061469 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2112 10:12:15.061580 # ok 385 Set SVE VL 1536
2113 10:12:15.061767 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2114 10:12:15.061998 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2115 10:12:15.062186 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2116 10:12:15.062367 # ok 389 Set SVE VL 1552
2117 10:12:15.062507 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2118 10:12:15.064906 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2119 10:12:15.065359 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2120 10:12:15.065550 # ok 393 Set SVE VL 1568
2121 10:12:15.065730 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2122 10:12:15.065934 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2123 10:12:15.066091 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2124 10:12:15.066241 # ok 397 Set SVE VL 1584
2125 10:12:15.066431 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2126 10:12:15.066604 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2127 10:12:15.066810 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2128 10:12:15.067017 # ok 401 Set SVE VL 1600
2129 10:12:15.067240 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2130 10:12:15.067422 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2131 10:12:15.067596 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2132 10:12:15.067769 # ok 405 Set SVE VL 1616
2133 10:12:15.067959 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2134 10:12:15.068122 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2135 10:12:15.068315 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2136 10:12:15.068460 # ok 409 Set SVE VL 1632
2137 10:12:15.068599 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2138 10:12:15.068785 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2139 10:12:15.068919 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2140 10:12:15.069059 # ok 413 Set SVE VL 1648
2141 10:12:15.069196 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2142 10:12:15.069334 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2143 10:12:15.069473 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2144 10:12:15.069611 # ok 417 Set SVE VL 1664
2145 10:12:15.069761 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2146 10:12:15.069900 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2147 10:12:15.070039 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2148 10:12:15.070181 # ok 421 Set SVE VL 1680
2149 10:12:15.070318 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2150 10:12:15.070457 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2151 10:12:15.070596 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2152 10:12:15.070734 # ok 425 Set SVE VL 1696
2153 10:12:15.070870 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2154 10:12:15.071008 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2155 10:12:15.071150 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2156 10:12:15.071287 # ok 429 Set SVE VL 1712
2157 10:12:15.071425 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2158 10:12:15.071562 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2159 10:12:15.072777 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2160 10:12:15.073167 # ok 433 Set SVE VL 1728
2161 10:12:15.073418 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2162 10:12:15.073544 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2163 10:12:15.073687 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2164 10:12:15.073859 # ok 437 Set SVE VL 1744
2165 10:12:15.073963 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2166 10:12:15.074068 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2167 10:12:15.074198 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2168 10:12:15.074344 # ok 441 Set SVE VL 1760
2169 10:12:15.074491 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2170 10:12:15.074669 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2171 10:12:15.074802 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2172 10:12:15.074936 # ok 445 Set SVE VL 1776
2173 10:12:15.075064 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2174 10:12:15.075200 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2175 10:12:15.075355 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2176 10:12:15.075493 # ok 449 Set SVE VL 1792
2177 10:12:15.075634 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2178 10:12:15.075788 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2179 10:12:15.075948 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2180 10:12:15.076077 # ok 453 Set SVE VL 1808
2181 10:12:15.076208 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2182 10:12:15.076346 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2183 10:12:15.076452 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2184 10:12:15.076539 # ok 457 Set SVE VL 1824
2185 10:12:15.076623 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2186 10:12:15.076706 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2187 10:12:15.076774 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2188 10:12:15.076831 # ok 461 Set SVE VL 1840
2189 10:12:15.076888 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2190 10:12:15.076944 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2191 10:12:15.077015 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2192 10:12:15.077077 # ok 465 Set SVE VL 1856
2193 10:12:15.077134 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2194 10:12:15.077192 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2195 10:12:15.080581 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2196 10:12:15.080909 # ok 469 Set SVE VL 1872
2197 10:12:15.081098 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2198 10:12:15.081274 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2199 10:12:15.081455 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2200 10:12:15.081605 # ok 473 Set SVE VL 1888
2201 10:12:15.081749 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2202 10:12:15.081866 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2203 10:12:15.081979 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2204 10:12:15.082090 # ok 477 Set SVE VL 1904
2205 10:12:15.082224 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2206 10:12:15.082340 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2207 10:12:15.088666 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2208 10:12:15.088976 # ok 481 Set SVE VL 1920
2209 10:12:15.089079 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2210 10:12:15.089176 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2211 10:12:15.089257 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2212 10:12:15.089347 # ok 485 Set SVE VL 1936
2213 10:12:15.089426 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2214 10:12:15.089515 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2215 10:12:15.089594 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2216 10:12:15.089693 # ok 489 Set SVE VL 1952
2217 10:12:15.089774 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2218 10:12:15.089864 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2219 10:12:15.089942 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2220 10:12:15.090031 # ok 493 Set SVE VL 1968
2221 10:12:15.090113 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2222 10:12:15.090206 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2223 10:12:15.090298 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2224 10:12:15.090401 # ok 497 Set SVE VL 1984
2225 10:12:15.090495 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2226 10:12:15.090590 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2227 10:12:15.090680 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2228 10:12:15.090774 # ok 501 Set SVE VL 2000
2229 10:12:15.090851 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2230 10:12:15.090940 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2231 10:12:15.091030 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2232 10:12:15.091120 # ok 505 Set SVE VL 2016
2233 10:12:15.091408 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2234 10:12:15.091508 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2235 10:12:15.091601 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2236 10:12:15.091679 # ok 509 Set SVE VL 2032
2237 10:12:15.091772 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2238 10:12:15.091862 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2239 10:12:15.091939 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2240 10:12:15.092027 # ok 513 Set SVE VL 2048
2241 10:12:15.092116 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2242 10:12:15.092205 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2243 10:12:15.092577 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2244 10:12:15.092857 # ok 517 Set SVE VL 2064
2245 10:12:15.092942 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2246 10:12:15.093049 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2247 10:12:15.093137 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2248 10:12:15.093404 # ok 521 Set SVE VL 2080
2249 10:12:15.093488 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2250 10:12:15.093609 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2251 10:12:15.093703 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2252 10:12:15.093785 # ok 525 Set SVE VL 2096
2253 10:12:15.093881 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2254 10:12:15.093959 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2255 10:12:15.094050 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2256 10:12:15.094130 # ok 529 Set SVE VL 2112
2257 10:12:15.094206 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2258 10:12:15.094266 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2259 10:12:15.094525 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2260 10:12:15.094607 # ok 533 Set SVE VL 2128
2261 10:12:15.094713 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2262 10:12:15.094800 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2263 10:12:15.094897 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2264 10:12:15.094993 # ok 537 Set SVE VL 2144
2265 10:12:15.095072 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2266 10:12:15.095163 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2267 10:12:15.095252 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2268 10:12:15.095340 # ok 541 Set SVE VL 2160
2269 10:12:15.095431 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2270 10:12:15.095515 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2271 10:12:15.095775 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2272 10:12:15.095858 # ok 545 Set SVE VL 2176
2273 10:12:15.095937 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2274 10:12:15.096017 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2275 10:12:15.096261 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2276 10:12:15.096348 # ok 549 Set SVE VL 2192
2277 10:12:15.100606 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2278 10:12:15.100956 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2279 10:12:15.101115 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2280 10:12:15.101263 # ok 553 Set SVE VL 2208
2281 10:12:15.101672 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2282 10:12:15.101832 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2283 10:12:15.101979 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2284 10:12:15.102154 # ok 557 Set SVE VL 2224
2285 10:12:15.102328 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2286 10:12:15.102482 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2287 10:12:15.102673 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2288 10:12:15.102838 # ok 561 Set SVE VL 2240
2289 10:12:15.102996 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2290 10:12:15.103163 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2291 10:12:15.103354 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2292 10:12:15.103511 # ok 565 Set SVE VL 2256
2293 10:12:15.103658 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2294 10:12:15.103817 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2295 10:12:15.103972 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2296 10:12:15.104114 # ok 569 Set SVE VL 2272
2297 10:12:15.104282 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2298 10:12:15.104446 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2299 10:12:15.104605 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2300 10:12:15.104733 # ok 573 Set SVE VL 2288
2301 10:12:15.104846 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2302 10:12:15.104958 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2303 10:12:15.105070 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2304 10:12:15.105182 # ok 577 Set SVE VL 2304
2305 10:12:15.105294 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2306 10:12:15.105406 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2307 10:12:15.105518 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2308 10:12:15.105630 # ok 581 Set SVE VL 2320
2309 10:12:15.105860 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2310 10:12:15.106083 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2311 10:12:15.107680 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2312 10:12:15.108042 # ok 585 Set SVE VL 2336
2313 10:12:15.108142 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2314 10:12:15.108222 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2315 10:12:15.108312 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2316 10:12:15.108389 # ok 589 Set SVE VL 2352
2317 10:12:15.108464 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2318 10:12:15.108748 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2319 10:12:15.108847 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2320 10:12:15.108925 # ok 593 Set SVE VL 2368
2321 10:12:15.109015 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2322 10:12:15.109110 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2323 10:12:15.109202 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2324 10:12:15.109293 # ok 597 Set SVE VL 2384
2325 10:12:15.109384 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2326 10:12:15.109477 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2327 10:12:15.109573 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2328 10:12:15.109670 # ok 601 Set SVE VL 2400
2329 10:12:15.109760 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2330 10:12:15.110047 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2331 10:12:15.110159 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2332 10:12:15.110239 # ok 605 Set SVE VL 2416
2333 10:12:15.110329 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2334 10:12:15.110408 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2335 10:12:15.110500 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2336 10:12:15.110592 # ok 609 Set SVE VL 2432
2337 10:12:15.110684 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2338 10:12:15.110799 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2339 10:12:15.110892 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2340 10:12:15.110984 # ok 613 Set SVE VL 2448
2341 10:12:15.111076 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2342 10:12:15.111168 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2343 10:12:15.111442 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2344 10:12:15.111525 # ok 617 Set SVE VL 2464
2345 10:12:15.111615 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2346 10:12:15.111888 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2347 10:12:15.111971 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2348 10:12:15.112048 # ok 621 Set SVE VL 2480
2349 10:12:15.112138 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2350 10:12:15.112217 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2351 10:12:15.112307 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2352 10:12:15.112397 # ok 625 Set SVE VL 2496
2353 10:12:15.112490 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2354 10:12:15.112778 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2355 10:12:15.112876 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2356 10:12:15.112968 # ok 629 Set SVE VL 2512
2357 10:12:15.113059 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2358 10:12:15.113150 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2359 10:12:15.113240 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2360 10:12:15.113317 # ok 633 Set SVE VL 2528
2361 10:12:15.113409 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2362 10:12:15.113498 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2363 10:12:15.113587 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2364 10:12:15.113685 # ok 637 Set SVE VL 2544
2365 10:12:15.113775 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2366 10:12:15.114061 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2367 10:12:15.114160 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2368 10:12:15.114254 # ok 641 Set SVE VL 2560
2369 10:12:15.114344 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2370 10:12:15.114433 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2371 10:12:15.114522 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2372 10:12:15.114611 # ok 645 Set SVE VL 2576
2373 10:12:15.114895 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2374 10:12:15.114994 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2375 10:12:15.115085 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2376 10:12:15.115163 # ok 649 Set SVE VL 2592
2377 10:12:15.115252 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2378 10:12:15.115341 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2379 10:12:15.115626 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2380 10:12:15.115724 # ok 653 Set SVE VL 2608
2381 10:12:15.115802 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2382 10:12:15.115891 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2383 10:12:15.115969 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2384 10:12:15.116061 # ok 657 Set SVE VL 2624
2385 10:12:15.116152 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2386 10:12:15.116230 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2387 10:12:15.116318 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2388 10:12:15.116396 # ok 661 Set SVE VL 2640
2389 10:12:15.116483 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2390 10:12:15.116573 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2391 10:12:15.116868 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2392 10:12:15.116966 # ok 665 Set SVE VL 2656
2393 10:12:15.117059 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2394 10:12:15.127300 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2395 10:12:15.127597 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2396 10:12:15.127697 # ok 669 Set SVE VL 2672
2397 10:12:15.127788 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2398 10:12:15.127866 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2399 10:12:15.127954 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2400 10:12:15.128032 # ok 673 Set SVE VL 2688
2401 10:12:15.128106 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2402 10:12:15.128194 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2403 10:12:15.128271 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2404 10:12:15.128359 # ok 677 Set SVE VL 2704
2405 10:12:15.128666 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2406 10:12:15.128868 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2407 10:12:15.129018 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2408 10:12:15.129177 # ok 681 Set SVE VL 2720
2409 10:12:15.129328 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2410 10:12:15.129500 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2411 10:12:15.129644 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2412 10:12:15.129826 # ok 685 Set SVE VL 2736
2413 10:12:15.129987 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2414 10:12:15.130172 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2415 10:12:15.130301 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2416 10:12:15.130444 # ok 689 Set SVE VL 2752
2417 10:12:15.130599 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2418 10:12:15.130726 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2419 10:12:15.130875 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2420 10:12:15.131047 # ok 693 Set SVE VL 2768
2421 10:12:15.131233 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2422 10:12:15.131422 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2423 10:12:15.131612 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2424 10:12:15.131774 # ok 697 Set SVE VL 2784
2425 10:12:15.131931 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2426 10:12:15.132087 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2427 10:12:15.132291 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2428 10:12:15.132490 # ok 701 Set SVE VL 2800
2429 10:12:15.132675 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2430 10:12:15.132839 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2431 10:12:15.132964 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2432 10:12:15.133070 # ok 705 Set SVE VL 2816
2433 10:12:15.133177 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2434 10:12:15.133287 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2435 10:12:15.133410 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2436 10:12:15.133508 # ok 709 Set SVE VL 2832
2437 10:12:15.133594 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2438 10:12:15.133701 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2439 10:12:15.133825 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2440 10:12:15.133953 # ok 713 Set SVE VL 2848
2441 10:12:15.134073 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2442 10:12:15.134200 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2443 10:12:15.134308 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2444 10:12:15.134451 # ok 717 Set SVE VL 2864
2445 10:12:15.134572 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2446 10:12:15.134684 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2447 10:12:15.134801 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2448 10:12:15.134881 # ok 721 Set SVE VL 2880
2449 10:12:15.135159 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2450 10:12:15.135240 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2451 10:12:15.135303 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2452 10:12:15.135363 # ok 725 Set SVE VL 2896
2453 10:12:15.135433 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2454 10:12:15.135497 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2455 10:12:15.135589 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2456 10:12:15.135684 # ok 729 Set SVE VL 2912
2457 10:12:15.135761 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2458 10:12:15.135844 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2459 10:12:15.135940 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2460 10:12:15.136005 # ok 733 Set SVE VL 2928
2461 10:12:15.136064 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2462 10:12:15.136138 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2463 10:12:15.136222 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2464 10:12:15.136327 # ok 737 Set SVE VL 2944
2465 10:12:15.136408 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2466 10:12:15.136489 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2467 10:12:15.136556 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2468 10:12:15.136628 # ok 741 Set SVE VL 2960
2469 10:12:15.136689 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2470 10:12:15.136746 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2471 10:12:15.136809 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2472 10:12:15.136866 # ok 745 Set SVE VL 2976
2473 10:12:15.136923 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2474 10:12:15.136983 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2475 10:12:15.137056 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2476 10:12:15.137118 # ok 749 Set SVE VL 2992
2477 10:12:15.137176 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2478 10:12:15.137235 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2479 10:12:15.137314 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2480 10:12:15.137398 # ok 753 Set SVE VL 3008
2481 10:12:15.137460 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2482 10:12:15.137533 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2483 10:12:15.137596 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2484 10:12:15.137670 # ok 757 Set SVE VL 3024
2485 10:12:15.137773 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2486 10:12:15.137883 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2487 10:12:15.137978 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2488 10:12:15.138071 # ok 761 Set SVE VL 3040
2489 10:12:15.138163 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2490 10:12:15.138267 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2491 10:12:15.138364 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2492 10:12:15.138456 # ok 765 Set SVE VL 3056
2493 10:12:15.138736 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2494 10:12:15.138823 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2495 10:12:15.138901 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2496 10:12:15.138973 # ok 769 Set SVE VL 3072
2497 10:12:15.139053 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2498 10:12:15.139157 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2499 10:12:15.139251 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2500 10:12:15.139323 # ok 773 Set SVE VL 3088
2501 10:12:15.139400 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2502 10:12:15.139492 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2503 10:12:15.139561 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2504 10:12:15.139630 # ok 777 Set SVE VL 3104
2505 10:12:15.139697 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2506 10:12:15.139802 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2507 10:12:15.139868 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2508 10:12:15.139928 # ok 781 Set SVE VL 3120
2509 10:12:15.139997 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2510 10:12:15.140081 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2511 10:12:15.140174 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2512 10:12:15.140268 # ok 785 Set SVE VL 3136
2513 10:12:15.140576 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2514 10:12:15.140821 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2515 10:12:15.140996 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2516 10:12:15.141148 # ok 789 Set SVE VL 3152
2517 10:12:15.141328 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2518 10:12:15.141485 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2519 10:12:15.141621 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2520 10:12:15.141803 # ok 793 Set SVE VL 3168
2521 10:12:15.141960 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2522 10:12:15.142118 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2523 10:12:15.142259 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2524 10:12:15.142381 # ok 797 Set SVE VL 3184
2525 10:12:15.142500 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2526 10:12:15.142617 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2527 10:12:15.142778 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2528 10:12:15.142878 # ok 801 Set SVE VL 3200
2529 10:12:15.142987 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2530 10:12:15.143070 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2531 10:12:15.143145 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2532 10:12:15.143241 # ok 805 Set SVE VL 3216
2533 10:12:15.143351 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2534 10:12:15.143440 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2535 10:12:15.143532 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2536 10:12:15.143641 # ok 809 Set SVE VL 3232
2537 10:12:15.143727 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2538 10:12:15.143819 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2539 10:12:15.143892 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2540 10:12:15.143957 # ok 813 Set SVE VL 3248
2541 10:12:15.144016 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2542 10:12:15.144077 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2543 10:12:15.144135 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2544 10:12:15.144192 # ok 817 Set SVE VL 3264
2545 10:12:15.144250 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2546 10:12:15.144313 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2547 10:12:15.144386 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2548 10:12:15.144449 # ok 821 Set SVE VL 3280
2549 10:12:15.144507 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2550 10:12:15.144573 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2551 10:12:15.144645 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2552 10:12:15.144710 # ok 825 Set SVE VL 3296
2553 10:12:15.144769 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2554 10:12:15.144839 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2555 10:12:15.144914 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2556 10:12:15.144993 # ok 829 Set SVE VL 3312
2557 10:12:15.145268 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2558 10:12:15.145377 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2559 10:12:15.145471 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2560 10:12:15.145580 # ok 833 Set SVE VL 3328
2561 10:12:15.145689 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2562 10:12:15.145774 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2563 10:12:15.145873 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2564 10:12:15.145971 # ok 837 Set SVE VL 3344
2565 10:12:15.146089 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2566 10:12:15.146166 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2567 10:12:15.146248 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2568 10:12:15.146318 # ok 841 Set SVE VL 3360
2569 10:12:15.146433 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2570 10:12:15.146550 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2571 10:12:15.146666 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2572 10:12:15.146767 # ok 845 Set SVE VL 3376
2573 10:12:15.146865 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2574 10:12:15.146944 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2575 10:12:15.147039 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2576 10:12:15.147145 # ok 849 Set SVE VL 3392
2577 10:12:15.147229 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2578 10:12:15.147312 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2579 10:12:15.147540 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2580 10:12:15.147629 # ok 853 Set SVE VL 3408
2581 10:12:15.147704 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2582 10:12:15.152390 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2583 10:12:15.152582 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2584 10:12:15.152762 # ok 857 Set SVE VL 3424
2585 10:12:15.152922 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2586 10:12:15.153107 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2587 10:12:15.153256 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2588 10:12:15.153414 # ok 861 Set SVE VL 3440
2589 10:12:15.153581 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2590 10:12:15.153762 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2591 10:12:15.153908 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2592 10:12:15.154033 # ok 865 Set SVE VL 3456
2593 10:12:15.154184 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2594 10:12:15.154317 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2595 10:12:15.154429 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2596 10:12:15.154555 # ok 869 Set SVE VL 3472
2597 10:12:15.154662 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2598 10:12:15.154787 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2599 10:12:15.154930 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2600 10:12:15.155061 # ok 873 Set SVE VL 3488
2601 10:12:15.155182 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2602 10:12:15.155301 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2603 10:12:15.155434 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2604 10:12:15.155587 # ok 877 Set SVE VL 3504
2605 10:12:15.155749 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2606 10:12:15.155936 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2607 10:12:15.156098 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2608 10:12:15.156261 # ok 881 Set SVE VL 3520
2609 10:12:15.156417 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2610 10:12:15.156575 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2611 10:12:15.156726 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2612 10:12:15.156891 # ok 885 Set SVE VL 3536
2613 10:12:15.157050 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2614 10:12:15.157218 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2615 10:12:15.157344 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2616 10:12:15.157445 # ok 889 Set SVE VL 3552
2617 10:12:15.157552 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2618 10:12:15.157675 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2619 10:12:15.157777 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2620 10:12:15.157877 # ok 893 Set SVE VL 3568
2621 10:12:15.157982 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2622 10:12:15.158090 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2623 10:12:15.158202 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2624 10:12:15.158286 # ok 897 Set SVE VL 3584
2625 10:12:15.158364 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2626 10:12:15.158619 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2627 10:12:15.158725 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2628 10:12:15.158812 # ok 901 Set SVE VL 3600
2629 10:12:15.158888 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2630 10:12:15.158954 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2631 10:12:15.159023 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2632 10:12:15.159091 # ok 905 Set SVE VL 3616
2633 10:12:15.159167 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2634 10:12:15.159248 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2635 10:12:15.159327 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2636 10:12:15.159400 # ok 909 Set SVE VL 3632
2637 10:12:15.159478 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2638 10:12:15.159566 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2639 10:12:15.159633 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2640 10:12:15.159696 # ok 913 Set SVE VL 3648
2641 10:12:15.159773 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2642 10:12:15.159846 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2643 10:12:15.159915 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2644 10:12:15.159977 # ok 917 Set SVE VL 3664
2645 10:12:15.160038 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2646 10:12:15.160115 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2647 10:12:15.160181 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2648 10:12:15.160245 # ok 921 Set SVE VL 3680
2649 10:12:15.160306 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2650 10:12:15.160372 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2651 10:12:15.160445 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2652 10:12:15.160522 # ok 925 Set SVE VL 3696
2653 10:12:15.160600 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2654 10:12:15.160858 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2655 10:12:15.160926 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2656 10:12:15.160998 # ok 929 Set SVE VL 3712
2657 10:12:15.161075 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2658 10:12:15.161332 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2659 10:12:15.161414 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2660 10:12:15.161486 # ok 933 Set SVE VL 3728
2661 10:12:15.161746 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2662 10:12:15.161819 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2663 10:12:15.161911 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2664 10:12:15.161995 # ok 937 Set SVE VL 3744
2665 10:12:15.162084 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2666 10:12:15.162419 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2667 10:12:15.162514 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2668 10:12:15.162591 # ok 941 Set SVE VL 3760
2669 10:12:15.162681 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2670 10:12:15.162758 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2671 10:12:15.162831 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2672 10:12:15.162906 # ok 945 Set SVE VL 3776
2673 10:12:15.163167 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2674 10:12:15.163258 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2675 10:12:15.163335 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2676 10:12:15.163447 # ok 949 Set SVE VL 3792
2677 10:12:15.163546 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2678 10:12:15.163642 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2679 10:12:15.163744 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2680 10:12:15.164012 # ok 953 Set SVE VL 3808
2681 10:12:15.164094 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2682 10:12:15.164171 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2683 10:12:15.164251 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2684 10:12:15.164345 # ok 957 Set SVE VL 3824
2685 10:12:15.164618 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2686 10:12:15.164714 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2687 10:12:15.164804 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2688 10:12:15.165064 # ok 961 Set SVE VL 3840
2689 10:12:15.165141 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2690 10:12:15.165216 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2691 10:12:15.165288 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2692 10:12:15.165371 # ok 965 Set SVE VL 3856
2693 10:12:15.165669 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2694 10:12:15.165784 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2695 10:12:15.165867 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2696 10:12:15.165952 # ok 969 Set SVE VL 3872
2697 10:12:15.166041 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2698 10:12:15.166120 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2699 10:12:15.166209 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2700 10:12:15.166300 # ok 973 Set SVE VL 3888
2701 10:12:15.166579 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2702 10:12:15.166675 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2703 10:12:15.166768 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2704 10:12:15.166847 # ok 977 Set SVE VL 3904
2705 10:12:15.166937 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2706 10:12:15.167027 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2707 10:12:15.167118 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2708 10:12:15.167208 # ok 981 Set SVE VL 3920
2709 10:12:15.167497 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2710 10:12:15.167600 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2711 10:12:15.167704 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2712 10:12:15.167806 # ok 985 Set SVE VL 3936
2713 10:12:15.167894 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2714 10:12:15.167993 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2715 10:12:15.168087 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2716 10:12:15.168340 # ok 989 Set SVE VL 3952
2717 10:12:15.168415 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2718 10:12:15.168661 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2719 10:12:15.168736 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2720 10:12:15.168808 # ok 993 Set SVE VL 3968
2721 10:12:15.169069 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2722 10:12:15.169156 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2723 10:12:15.169229 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2724 10:12:15.169300 # ok 997 Set SVE VL 3984
2725 10:12:15.169540 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2726 10:12:15.169603 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2727 10:12:15.169859 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2728 10:12:15.169927 # ok 1001 Set SVE VL 4000
2729 10:12:15.169986 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2730 10:12:15.170055 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2731 10:12:15.170300 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2732 10:12:15.170365 # ok 1005 Set SVE VL 4016
2733 10:12:15.170435 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2734 10:12:15.170506 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2735 10:12:15.170779 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2736 10:12:15.170844 # ok 1009 Set SVE VL 4032
2737 10:12:15.170914 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2738 10:12:15.170984 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2739 10:12:15.171233 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2740 10:12:15.171308 # ok 1013 Set SVE VL 4048
2741 10:12:15.171379 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2742 10:12:15.171628 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2743 10:12:15.171703 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2744 10:12:15.171775 # ok 1017 Set SVE VL 4064
2745 10:12:15.172043 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2746 10:12:15.172119 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2747 10:12:15.172364 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2748 10:12:15.172428 # ok 1021 Set SVE VL 4080
2749 10:12:15.172673 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2750 10:12:15.172747 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2751 10:12:15.172992 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2752 10:12:15.173057 # ok 1025 Set SVE VL 4096
2753 10:12:15.173127 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2754 10:12:15.173197 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2755 10:12:15.173443 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2756 10:12:15.173507 # ok 1029 Set SVE VL 4112
2757 10:12:15.173576 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2758 10:12:15.173829 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2759 10:12:15.173904 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2760 10:12:15.173974 # ok 1033 Set SVE VL 4128
2761 10:12:15.174218 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2762 10:12:15.174283 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2763 10:12:15.174353 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2764 10:12:15.174598 # ok 1037 Set SVE VL 4144
2765 10:12:15.174663 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2766 10:12:15.174751 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2767 10:12:15.174997 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2768 10:12:15.180086 # ok 1041 Set SVE VL 4160
2769 10:12:15.180237 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2770 10:12:15.180331 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2771 10:12:15.180421 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2772 10:12:15.180702 # ok 1045 Set SVE VL 4176
2773 10:12:15.180828 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2774 10:12:15.180942 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2775 10:12:15.181242 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2776 10:12:15.181340 # ok 1049 Set SVE VL 4192
2777 10:12:15.181445 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2778 10:12:15.181536 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2779 10:12:15.181640 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2780 10:12:15.181740 # ok 1053 Set SVE VL 4208
2781 10:12:15.181845 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2782 10:12:15.181941 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2783 10:12:15.182044 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2784 10:12:15.182158 # ok 1057 Set SVE VL 4224
2785 10:12:15.182264 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2786 10:12:15.182370 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2787 10:12:15.182477 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2788 10:12:15.182584 # ok 1061 Set SVE VL 4240
2789 10:12:15.182688 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2790 10:12:15.182801 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2791 10:12:15.183097 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2792 10:12:15.183194 # ok 1065 Set SVE VL 4256
2793 10:12:15.183298 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2794 10:12:15.183391 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2795 10:12:15.183495 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2796 10:12:15.183600 # ok 1069 Set SVE VL 4272
2797 10:12:15.183697 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2798 10:12:15.183790 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2799 10:12:15.184081 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2800 10:12:15.184176 # ok 1073 Set SVE VL 4288
2801 10:12:15.184262 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2802 10:12:15.184342 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2803 10:12:15.184614 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2804 10:12:15.184695 # ok 1077 Set SVE VL 4304
2805 10:12:15.184783 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2806 10:12:15.185048 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2807 10:12:15.185135 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2808 10:12:15.185212 # ok 1081 Set SVE VL 4320
2809 10:12:15.185288 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2810 10:12:15.185527 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2811 10:12:15.185603 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2812 10:12:15.185685 # ok 1085 Set SVE VL 4336
2813 10:12:15.185800 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2814 10:12:15.186101 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2815 10:12:15.186186 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2816 10:12:15.186263 # ok 1089 Set SVE VL 4352
2817 10:12:15.186343 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2818 10:12:15.186434 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2819 10:12:15.186705 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2820 10:12:15.186793 # ok 1093 Set SVE VL 4368
2821 10:12:15.186855 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2822 10:12:15.186926 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2823 10:12:15.187175 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2824 10:12:15.187270 # ok 1097 Set SVE VL 4384
2825 10:12:15.187365 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2826 10:12:15.187459 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2827 10:12:15.187544 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2828 10:12:15.187629 # ok 1101 Set SVE VL 4400
2829 10:12:15.187714 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2830 10:12:15.187836 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2831 10:12:15.187944 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2832 10:12:15.188194 # ok 1105 Set SVE VL 4416
2833 10:12:15.188260 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2834 10:12:15.188528 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2835 10:12:15.188621 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2836 10:12:15.188686 # ok 1109 Set SVE VL 4432
2837 10:12:15.188926 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2838 10:12:15.188990 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2839 10:12:15.189061 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2840 10:12:15.189150 # ok 1113 Set SVE VL 4448
2841 10:12:15.189398 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2842 10:12:15.189463 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2843 10:12:15.189532 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2844 10:12:15.189777 # ok 1117 Set SVE VL 4464
2845 10:12:15.189843 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2846 10:12:15.190091 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2847 10:12:15.190162 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2848 10:12:15.190222 # ok 1121 Set SVE VL 4480
2849 10:12:15.190291 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2850 10:12:15.190537 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2851 10:12:15.190600 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2852 10:12:15.190673 # ok 1125 Set SVE VL 4496
2853 10:12:15.190756 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2854 10:12:15.191007 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2855 10:12:15.191086 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2856 10:12:15.191346 # ok 1129 Set SVE VL 4512
2857 10:12:15.191414 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2858 10:12:15.191484 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2859 10:12:15.191730 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2860 10:12:15.191804 # ok 1133 Set SVE VL 4528
2861 10:12:15.191882 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2862 10:12:15.192144 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2863 10:12:15.192423 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2864 10:12:15.192502 # ok 1137 Set SVE VL 4544
2865 10:12:15.192581 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2866 10:12:15.192658 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2867 10:12:15.192923 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2868 10:12:15.192992 # ok 1141 Set SVE VL 4560
2869 10:12:15.193063 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2870 10:12:15.193310 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2871 10:12:15.193725 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2872 10:12:15.193806 # ok 1145 Set SVE VL 4576
2873 10:12:15.194283 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2874 10:12:15.194360 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2875 10:12:15.194605 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2876 10:12:15.194677 # ok 1149 Set SVE VL 4592
2877 10:12:15.194749 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2878 10:12:15.195001 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2879 10:12:15.195076 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2880 10:12:15.195153 # ok 1153 Set SVE VL 4608
2881 10:12:15.195399 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2882 10:12:15.195473 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2883 10:12:15.195717 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2884 10:12:15.195781 # ok 1157 Set SVE VL 4624
2885 10:12:15.196030 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2886 10:12:15.196123 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2887 10:12:15.196386 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2888 10:12:15.196452 # ok 1161 Set SVE VL 4640
2889 10:12:15.196915 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2890 10:12:15.196999 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2891 10:12:15.197240 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2892 10:12:15.197506 # ok 1165 Set SVE VL 4656
2893 10:12:15.197594 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2894 10:12:15.197673 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2895 10:12:15.197914 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2896 10:12:15.198167 # ok 1169 Set SVE VL 4672
2897 10:12:15.198257 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2898 10:12:15.198347 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2899 10:12:15.198458 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2900 10:12:15.198542 # ok 1173 Set SVE VL 4688
2901 10:12:15.198630 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2902 10:12:15.198727 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2903 10:12:15.198819 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2904 10:12:15.198900 # ok 1177 Set SVE VL 4704
2905 10:12:15.198998 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2906 10:12:15.199089 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2907 10:12:15.199183 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2908 10:12:15.199461 # ok 1181 Set SVE VL 4720
2909 10:12:15.199544 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2910 10:12:15.199633 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2911 10:12:15.199720 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2912 10:12:15.199808 # ok 1185 Set SVE VL 4736
2913 10:12:15.200097 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2914 10:12:15.200189 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2915 10:12:15.200273 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2916 10:12:15.200356 # ok 1189 Set SVE VL 4752
2917 10:12:15.200435 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2918 10:12:15.200671 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2919 10:12:15.200770 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2920 10:12:15.200851 # ok 1193 Set SVE VL 4768
2921 10:12:15.200932 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2922 10:12:15.201242 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2923 10:12:15.201337 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2924 10:12:15.201419 # ok 1197 Set SVE VL 4784
2925 10:12:15.201505 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2926 10:12:15.203862 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2927 10:12:15.204008 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2928 10:12:15.204089 # ok 1201 Set SVE VL 4800
2929 10:12:15.204168 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2930 10:12:15.204248 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2931 10:12:15.204319 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2932 10:12:15.204380 # ok 1205 Set SVE VL 4816
2933 10:12:15.204439 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2934 10:12:15.204506 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2935 10:12:15.204587 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2936 10:12:15.204651 # ok 1209 Set SVE VL 4832
2937 10:12:15.204711 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2938 10:12:15.204787 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2939 10:12:15.204868 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2940 10:12:15.204946 # ok 1213 Set SVE VL 4848
2941 10:12:15.205025 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2942 10:12:15.205106 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2943 10:12:15.205181 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2944 10:12:15.205256 # ok 1217 Set SVE VL 4864
2945 10:12:15.205330 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2946 10:12:15.205605 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2947 10:12:15.205702 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2948 10:12:15.205779 # ok 1221 Set SVE VL 4880
2949 10:12:15.205854 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2950 10:12:15.205930 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2951 10:12:15.213562 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2952 10:12:15.213779 # ok 1225 Set SVE VL 4896
2953 10:12:15.213889 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2954 10:12:15.213986 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2955 10:12:15.214062 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2956 10:12:15.214140 # ok 1229 Set SVE VL 4912
2957 10:12:15.214206 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2958 10:12:15.214280 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2959 10:12:15.214540 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2960 10:12:15.214639 # ok 1233 Set SVE VL 4928
2961 10:12:15.214743 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2962 10:12:15.214833 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2963 10:12:15.214944 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2964 10:12:15.215039 # ok 1237 Set SVE VL 4944
2965 10:12:15.215142 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2966 10:12:15.215233 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2967 10:12:15.215336 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2968 10:12:15.215407 # ok 1241 Set SVE VL 4960
2969 10:12:15.215480 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2970 10:12:15.216545 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2971 10:12:15.216639 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2972 10:12:15.216710 # ok 1245 Set SVE VL 4976
2973 10:12:15.216772 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2974 10:12:15.216833 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2975 10:12:15.216893 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2976 10:12:15.216953 # ok 1249 Set SVE VL 4992
2977 10:12:15.217013 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2978 10:12:15.217072 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2979 10:12:15.217735 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2980 10:12:15.218037 # ok 1253 Set SVE VL 5008
2981 10:12:15.218136 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2982 10:12:15.218229 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2983 10:12:15.218309 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2984 10:12:15.218398 # ok 1257 Set SVE VL 5024
2985 10:12:15.218476 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2986 10:12:15.218742 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2987 10:12:15.218818 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2988 10:12:15.218890 # ok 1261 Set SVE VL 5040
2989 10:12:15.218984 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2990 10:12:15.219056 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2991 10:12:15.219145 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2992 10:12:15.219231 # ok 1265 Set SVE VL 5056
2993 10:12:15.219498 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2994 10:12:15.219581 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2995 10:12:15.219672 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2996 10:12:15.219752 # ok 1269 Set SVE VL 5072
2997 10:12:15.219832 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
2998 10:12:15.219921 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
2999 10:12:15.220184 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3000 10:12:15.220264 # ok 1273 Set SVE VL 5088
3001 10:12:15.220342 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3002 10:12:15.220416 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3003 10:12:15.221012 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3004 10:12:15.221257 # ok 1277 Set SVE VL 5104
3005 10:12:15.221322 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3006 10:12:15.221571 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3007 10:12:15.221655 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3008 10:12:15.221733 # ok 1281 Set SVE VL 5120
3009 10:12:15.221815 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3010 10:12:15.221906 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3011 10:12:15.222184 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3012 10:12:15.222275 # ok 1285 Set SVE VL 5136
3013 10:12:15.222374 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3014 10:12:15.222469 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3015 10:12:15.222574 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3016 10:12:15.222646 # ok 1289 Set SVE VL 5152
3017 10:12:15.222742 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3018 10:12:15.223004 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3019 10:12:15.223090 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3020 10:12:15.223162 # ok 1293 Set SVE VL 5168
3021 10:12:15.223250 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3022 10:12:15.223334 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3023 10:12:15.223616 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3024 10:12:15.223721 # ok 1297 Set SVE VL 5184
3025 10:12:15.223828 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3026 10:12:15.223921 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3027 10:12:15.224024 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3028 10:12:15.224127 # ok 1301 Set SVE VL 5200
3029 10:12:15.224226 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3030 10:12:15.224524 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3031 10:12:15.224762 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3032 10:12:15.224846 # ok 1305 Set SVE VL 5216
3033 10:12:15.224925 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3034 10:12:15.225181 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3035 10:12:15.225252 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3036 10:12:15.225327 # ok 1309 Set SVE VL 5232
3037 10:12:15.225401 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3038 10:12:15.225661 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3039 10:12:15.225740 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3040 10:12:15.225815 # ok 1313 Set SVE VL 5248
3041 10:12:15.225889 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3042 10:12:15.225977 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3043 10:12:15.226229 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3044 10:12:15.226303 # ok 1317 Set SVE VL 5264
3045 10:12:15.226410 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3046 10:12:15.226675 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3047 10:12:15.226759 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3048 10:12:15.226831 # ok 1321 Set SVE VL 5280
3049 10:12:15.227097 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3050 10:12:15.227168 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3051 10:12:15.227452 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3052 10:12:15.227547 # ok 1325 Set SVE VL 5296
3053 10:12:15.227656 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3054 10:12:15.227750 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3055 10:12:15.227817 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3056 10:12:15.227890 # ok 1329 Set SVE VL 5312
3057 10:12:15.227955 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3058 10:12:15.228216 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3059 10:12:15.228304 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3060 10:12:15.228412 # ok 1333 Set SVE VL 5328
3061 10:12:15.228483 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3062 10:12:15.228746 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3063 10:12:15.228867 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3064 10:12:15.228971 # ok 1337 Set SVE VL 5344
3065 10:12:15.229078 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3066 10:12:15.229368 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3067 10:12:15.229475 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3068 10:12:15.229578 # ok 1341 Set SVE VL 5360
3069 10:12:15.229875 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3070 10:12:15.232498 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3071 10:12:15.232581 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3072 10:12:15.232646 # ok 1345 Set SVE VL 5376
3073 10:12:15.232706 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3074 10:12:15.232766 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3075 10:12:15.232826 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3076 10:12:15.232885 # ok 1349 Set SVE VL 5392
3077 10:12:15.232946 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3078 10:12:15.233009 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3079 10:12:15.233070 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3080 10:12:15.233139 # ok 1353 Set SVE VL 5408
3081 10:12:15.233218 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3082 10:12:15.233299 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3083 10:12:15.233391 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3084 10:12:15.233494 # ok 1357 Set SVE VL 5424
3085 10:12:15.233590 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3086 10:12:15.233705 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3087 10:12:15.233801 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3088 10:12:15.233916 # ok 1361 Set SVE VL 5440
3089 10:12:15.234012 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3090 10:12:15.234099 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3091 10:12:15.234174 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3092 10:12:15.234259 # ok 1365 Set SVE VL 5456
3093 10:12:15.234355 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3094 10:12:15.234448 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3095 10:12:15.234523 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3096 10:12:15.234600 # ok 1369 Set SVE VL 5472
3097 10:12:15.234674 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3098 10:12:15.234763 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3099 10:12:15.234863 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3100 10:12:15.234949 # ok 1373 Set SVE VL 5488
3101 10:12:15.235026 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3102 10:12:15.235301 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3103 10:12:15.235409 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3104 10:12:15.235499 # ok 1377 Set SVE VL 5504
3105 10:12:15.235567 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3106 10:12:15.235629 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3107 10:12:15.235691 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3108 10:12:15.235753 # ok 1381 Set SVE VL 5520
3109 10:12:15.235812 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3110 10:12:15.235874 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3111 10:12:15.235934 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3112 10:12:15.236004 # ok 1385 Set SVE VL 5536
3113 10:12:15.236079 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3114 10:12:15.236157 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3115 10:12:15.236229 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3116 10:12:15.236289 # ok 1389 Set SVE VL 5552
3117 10:12:15.236374 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3118 10:12:15.236441 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3119 10:12:15.236500 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3120 10:12:15.236558 # ok 1393 Set SVE VL 5568
3121 10:12:15.236615 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3122 10:12:15.236673 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3123 10:12:15.236730 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3124 10:12:15.236788 # ok 1397 Set SVE VL 5584
3125 10:12:15.236861 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3126 10:12:15.236924 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3127 10:12:15.236982 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3128 10:12:15.237041 # ok 1401 Set SVE VL 5600
3129 10:12:15.237099 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3130 10:12:15.237157 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3131 10:12:15.237215 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3132 10:12:15.237273 # ok 1405 Set SVE VL 5616
3133 10:12:15.237332 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3134 10:12:15.260420 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3135 10:12:15.260524 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3136 10:12:15.262725 # ok 1409 Set SVE VL 5632
3137 10:12:15.263013 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3138 10:12:15.263107 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3139 10:12:15.263197 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3140 10:12:15.263290 # ok 1413 Set SVE VL 5648
3141 10:12:15.263402 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3142 10:12:15.263492 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3143 10:12:15.263606 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3144 10:12:15.263698 # ok 1417 Set SVE VL 5664
3145 10:12:15.263803 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3146 10:12:15.263889 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3147 10:12:15.263979 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3148 10:12:15.264080 # ok 1421 Set SVE VL 5680
3149 10:12:15.264174 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3150 10:12:15.264458 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3151 10:12:15.265193 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3152 10:12:15.265480 # ok 1425 Set SVE VL 5696
3153 10:12:15.265575 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3154 10:12:15.265684 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3155 10:12:15.265792 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3156 10:12:15.265881 # ok 1429 Set SVE VL 5712
3157 10:12:15.265951 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3158 10:12:15.266041 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3159 10:12:15.266141 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3160 10:12:15.266226 # ok 1433 Set SVE VL 5728
3161 10:12:15.266322 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3162 10:12:15.266420 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3163 10:12:15.266501 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3164 10:12:15.266581 # ok 1437 Set SVE VL 5744
3165 10:12:15.266669 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3166 10:12:15.266781 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3167 10:12:15.266876 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3168 10:12:15.266969 # ok 1441 Set SVE VL 5760
3169 10:12:15.267051 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3170 10:12:15.267167 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3171 10:12:15.267341 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3172 10:12:15.267526 # ok 1445 Set SVE VL 5776
3173 10:12:15.267708 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3174 10:12:15.267828 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3175 10:12:15.267980 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3176 10:12:15.268132 # ok 1449 Set SVE VL 5792
3177 10:12:15.268266 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3178 10:12:15.268421 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3179 10:12:15.268519 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3180 10:12:15.268606 # ok 1453 Set SVE VL 5808
3181 10:12:15.269037 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3182 10:12:15.269325 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3183 10:12:15.269412 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3184 10:12:15.269499 # ok 1457 Set SVE VL 5824
3185 10:12:15.269577 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3186 10:12:15.269682 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3187 10:12:15.269809 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3188 10:12:15.269907 # ok 1461 Set SVE VL 5840
3189 10:12:15.269998 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3190 10:12:15.270085 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3191 10:12:15.270336 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3192 10:12:15.270422 # ok 1465 Set SVE VL 5856
3193 10:12:15.270519 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3194 10:12:15.270605 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3195 10:12:15.270719 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3196 10:12:15.270797 # ok 1469 Set SVE VL 5872
3197 10:12:15.270906 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3198 10:12:15.271026 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3199 10:12:15.271133 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3200 10:12:15.271211 # ok 1473 Set SVE VL 5888
3201 10:12:15.271303 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3202 10:12:15.271397 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3203 10:12:15.271532 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3204 10:12:15.271825 # ok 1477 Set SVE VL 5904
3205 10:12:15.271911 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3206 10:12:15.272003 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3207 10:12:15.272097 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3208 10:12:15.272179 # ok 1481 Set SVE VL 5920
3209 10:12:15.272270 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3210 10:12:15.272376 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3211 10:12:15.273171 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3212 10:12:15.273444 # ok 1485 Set SVE VL 5936
3213 10:12:15.273537 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3214 10:12:15.273667 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3215 10:12:15.273748 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3216 10:12:15.273862 # ok 1489 Set SVE VL 5952
3217 10:12:15.273963 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3218 10:12:15.274077 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3219 10:12:15.274183 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3220 10:12:15.274255 # ok 1493 Set SVE VL 5968
3221 10:12:15.274343 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3222 10:12:15.274433 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3223 10:12:15.274715 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3224 10:12:15.274801 # ok 1497 Set SVE VL 5984
3225 10:12:15.274882 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3226 10:12:15.274998 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3227 10:12:15.275073 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3228 10:12:15.275162 # ok 1501 Set SVE VL 6000
3229 10:12:15.275247 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3230 10:12:15.275340 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3231 10:12:15.275614 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3232 10:12:15.275691 # ok 1505 Set SVE VL 6016
3233 10:12:15.275797 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3234 10:12:15.275884 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3235 10:12:15.276162 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3236 10:12:15.276267 # ok 1509 Set SVE VL 6032
3237 10:12:15.276364 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3238 10:12:15.276447 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3239 10:12:15.276919 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3240 10:12:15.277237 # ok 1513 Set SVE VL 6048
3241 10:12:15.277419 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3242 10:12:15.277603 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3243 10:12:15.277775 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3244 10:12:15.277931 # ok 1517 Set SVE VL 6064
3245 10:12:15.278107 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3246 10:12:15.278272 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3247 10:12:15.278436 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3248 10:12:15.278598 # ok 1521 Set SVE VL 6080
3249 10:12:15.278750 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3250 10:12:15.278937 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3251 10:12:15.279098 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3252 10:12:15.279204 # ok 1525 Set SVE VL 6096
3253 10:12:15.279309 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3254 10:12:15.279411 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3255 10:12:15.279519 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3256 10:12:15.279624 # ok 1529 Set SVE VL 6112
3257 10:12:15.279755 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3258 10:12:15.279871 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3259 10:12:15.279986 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3260 10:12:15.280088 # ok 1533 Set SVE VL 6128
3261 10:12:15.280205 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3262 10:12:15.280317 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3263 10:12:15.280429 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3264 10:12:15.280521 # ok 1537 Set SVE VL 6144
3265 10:12:15.280626 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3266 10:12:15.280716 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3267 10:12:15.280802 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3268 10:12:15.280896 # ok 1541 Set SVE VL 6160
3269 10:12:15.281001 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3270 10:12:15.281131 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3271 10:12:15.281241 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3272 10:12:15.281363 # ok 1545 Set SVE VL 6176
3273 10:12:15.281469 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3274 10:12:15.281599 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3275 10:12:15.281758 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3276 10:12:15.281907 # ok 1549 Set SVE VL 6192
3277 10:12:15.282071 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3278 10:12:15.282204 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3279 10:12:15.282298 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3280 10:12:15.282394 # ok 1553 Set SVE VL 6208
3281 10:12:15.282504 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3282 10:12:15.282584 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3283 10:12:15.282849 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3284 10:12:15.282949 # ok 1557 Set SVE VL 6224
3285 10:12:15.283042 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3286 10:12:15.283121 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3287 10:12:15.283207 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3288 10:12:15.283296 # ok 1561 Set SVE VL 6240
3289 10:12:15.283393 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3290 10:12:15.283520 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3291 10:12:15.283619 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3292 10:12:15.283717 # ok 1565 Set SVE VL 6256
3293 10:12:15.283790 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3294 10:12:15.283898 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3295 10:12:15.283994 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3296 10:12:15.284078 # ok 1569 Set SVE VL 6272
3297 10:12:15.284193 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3298 10:12:15.284293 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3299 10:12:15.284398 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3300 10:12:15.284468 # ok 1573 Set SVE VL 6288
3301 10:12:15.284542 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3302 10:12:15.284811 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3303 10:12:15.284912 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3304 10:12:15.285008 # ok 1577 Set SVE VL 6304
3305 10:12:15.285092 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3306 10:12:15.285190 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3307 10:12:15.285281 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3308 10:12:15.285372 # ok 1581 Set SVE VL 6320
3309 10:12:15.285463 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3310 10:12:15.285553 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3311 10:12:15.285839 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3312 10:12:15.285939 # ok 1585 Set SVE VL 6336
3313 10:12:15.286032 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3314 10:12:15.286110 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3315 10:12:15.286205 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3316 10:12:15.286285 # ok 1589 Set SVE VL 6352
3317 10:12:15.288043 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3318 10:12:15.288144 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3319 10:12:15.288246 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3320 10:12:15.288329 # ok 1593 Set SVE VL 6368
3321 10:12:15.288420 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3322 10:12:15.288708 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3323 10:12:15.289002 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3324 10:12:15.289093 # ok 1597 Set SVE VL 6384
3325 10:12:15.289201 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3326 10:12:15.289346 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3327 10:12:15.289475 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3328 10:12:15.289713 # ok 1601 Set SVE VL 6400
3329 10:12:15.289883 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3330 10:12:15.290033 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3331 10:12:15.290211 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3332 10:12:15.290342 # ok 1605 Set SVE VL 6416
3333 10:12:15.290463 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3334 10:12:15.290582 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3335 10:12:15.290716 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3336 10:12:15.290841 # ok 1609 Set SVE VL 6432
3337 10:12:15.290960 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3338 10:12:15.291076 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3339 10:12:15.291207 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3340 10:12:15.291376 # ok 1613 Set SVE VL 6448
3341 10:12:15.291502 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3342 10:12:15.291626 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3343 10:12:15.291748 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3344 10:12:15.291863 # ok 1617 Set SVE VL 6464
3345 10:12:15.291978 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3346 10:12:15.292127 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3347 10:12:15.292239 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3348 10:12:15.292355 # ok 1621 Set SVE VL 6480
3349 10:12:15.292464 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3350 10:12:15.292565 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3351 10:12:15.292677 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3352 10:12:15.292783 # ok 1625 Set SVE VL 6496
3353 10:12:15.292900 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3354 10:12:15.293016 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3355 10:12:15.293131 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3356 10:12:15.293246 # ok 1629 Set SVE VL 6512
3357 10:12:15.293362 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3358 10:12:15.293471 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3359 10:12:15.293605 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3360 10:12:15.293809 # ok 1633 Set SVE VL 6528
3361 10:12:15.293955 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3362 10:12:15.294080 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3363 10:12:15.294172 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3364 10:12:15.294266 # ok 1637 Set SVE VL 6544
3365 10:12:15.294359 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3366 10:12:15.294654 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3367 10:12:15.294740 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3368 10:12:15.294814 # ok 1641 Set SVE VL 6560
3369 10:12:15.294889 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3370 10:12:15.294952 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3371 10:12:15.295012 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3372 10:12:15.295072 # ok 1645 Set SVE VL 6576
3373 10:12:15.295131 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3374 10:12:15.295203 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3375 10:12:15.295265 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3376 10:12:15.295325 # ok 1649 Set SVE VL 6592
3377 10:12:15.295384 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3378 10:12:15.295443 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3379 10:12:15.295513 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3380 10:12:15.295575 # ok 1653 Set SVE VL 6608
3381 10:12:15.295634 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3382 10:12:15.295714 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3383 10:12:15.295803 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3384 10:12:15.295885 # ok 1657 Set SVE VL 6624
3385 10:12:15.296148 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3386 10:12:15.296225 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3387 10:12:15.296310 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3388 10:12:15.296383 # ok 1661 Set SVE VL 6640
3389 10:12:15.296648 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3390 10:12:15.296934 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3391 10:12:15.297247 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3392 10:12:15.297348 # ok 1665 Set SVE VL 6656
3393 10:12:15.297441 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3394 10:12:15.297532 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3395 10:12:15.297818 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3396 10:12:15.297930 # ok 1669 Set SVE VL 6672
3397 10:12:15.298023 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3398 10:12:15.298324 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3399 10:12:15.298424 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3400 10:12:15.298519 # ok 1673 Set SVE VL 6688
3401 10:12:15.298597 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3402 10:12:15.298686 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3403 10:12:15.298775 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3404 10:12:15.298865 # ok 1677 Set SVE VL 6704
3405 10:12:15.298954 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3406 10:12:15.299240 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3407 10:12:15.299351 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3408 10:12:15.299433 # ok 1681 Set SVE VL 6720
3409 10:12:15.299524 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3410 10:12:15.299616 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3411 10:12:15.299708 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3412 10:12:15.299799 # ok 1685 Set SVE VL 6736
3413 10:12:15.300094 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3414 10:12:15.300192 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3415 10:12:15.300287 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3416 10:12:15.300366 # ok 1689 Set SVE VL 6752
3417 10:12:15.300455 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3418 10:12:15.300740 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3419 10:12:15.300863 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3420 10:12:15.300956 # ok 1693 Set SVE VL 6768
3421 10:12:15.301038 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3422 10:12:15.301204 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3423 10:12:15.301290 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3424 10:12:15.301367 # ok 1697 Set SVE VL 6784
3425 10:12:15.301457 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3426 10:12:15.301535 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3427 10:12:15.301624 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3428 10:12:15.301710 # ok 1701 Set SVE VL 6800
3429 10:12:15.301802 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3430 10:12:15.301884 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3431 10:12:15.301977 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3432 10:12:15.302068 # ok 1705 Set SVE VL 6816
3433 10:12:15.302160 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3434 10:12:15.302250 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3435 10:12:15.302345 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3436 10:12:15.302622 # ok 1709 Set SVE VL 6832
3437 10:12:15.302723 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3438 10:12:15.302817 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3439 10:12:15.302897 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3440 10:12:15.302975 # ok 1713 Set SVE VL 6848
3441 10:12:15.303066 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3442 10:12:15.303159 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3443 10:12:15.303239 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3444 10:12:15.303330 # ok 1717 Set SVE VL 6864
3445 10:12:15.303410 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3446 10:12:15.303696 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3447 10:12:15.303794 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3448 10:12:15.303873 # ok 1721 Set SVE VL 6880
3449 10:12:15.303965 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3450 10:12:15.304046 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3451 10:12:15.304144 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3452 10:12:15.304222 # ok 1725 Set SVE VL 6896
3453 10:12:15.304311 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3454 10:12:15.304401 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3455 10:12:15.304687 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3456 10:12:15.304787 # ok 1729 Set SVE VL 6912
3457 10:12:15.304881 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3458 10:12:15.304973 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3459 10:12:15.305067 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3460 10:12:15.305146 # ok 1733 Set SVE VL 6928
3461 10:12:15.305235 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3462 10:12:15.305427 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3463 10:12:15.305529 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3464 10:12:15.305624 # ok 1737 Set SVE VL 6944
3465 10:12:15.305726 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3466 10:12:15.305820 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3467 10:12:15.305914 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3468 10:12:15.306005 # ok 1741 Set SVE VL 6960
3469 10:12:15.306095 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3470 10:12:15.306382 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3471 10:12:15.306483 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3472 10:12:15.306575 # ok 1745 Set SVE VL 6976
3473 10:12:15.306655 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3474 10:12:15.306749 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3475 10:12:15.306828 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3476 10:12:15.306917 # ok 1749 Set SVE VL 6992
3477 10:12:15.306995 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3478 10:12:15.307085 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3479 10:12:15.307376 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3480 10:12:15.307474 # ok 1753 Set SVE VL 7008
3481 10:12:15.307553 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3482 10:12:15.307642 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3483 10:12:15.307732 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3484 10:12:15.307810 # ok 1757 Set SVE VL 7024
3485 10:12:15.307899 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3486 10:12:15.307989 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3487 10:12:15.308080 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3488 10:12:15.308169 # ok 1761 Set SVE VL 7040
3489 10:12:15.308454 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3490 10:12:15.308554 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3491 10:12:15.308645 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3492 10:12:15.308726 # ok 1765 Set SVE VL 7056
3493 10:12:15.308817 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3494 10:12:15.309090 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3495 10:12:15.309174 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3496 10:12:15.309266 # ok 1769 Set SVE VL 7072
3497 10:12:15.309356 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3498 10:12:15.309446 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3499 10:12:15.309536 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3500 10:12:15.311021 # ok 1773 Set SVE VL 7088
3501 10:12:15.311119 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3502 10:12:15.311212 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3503 10:12:15.311291 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3504 10:12:15.311380 # ok 1777 Set SVE VL 7104
3505 10:12:15.311471 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3506 10:12:15.311560 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3507 10:12:15.311847 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3508 10:12:15.311946 # ok 1781 Set SVE VL 7120
3509 10:12:15.312026 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3510 10:12:15.312119 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3511 10:12:15.312199 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3512 10:12:15.312278 # ok 1785 Set SVE VL 7136
3513 10:12:15.312369 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3514 10:12:15.312448 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3515 10:12:15.312809 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3516 10:12:15.313091 # ok 1789 Set SVE VL 7152
3517 10:12:15.313189 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3518 10:12:15.313283 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3519 10:12:15.313373 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3520 10:12:15.313669 # ok 1793 Set SVE VL 7168
3521 10:12:15.313755 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3522 10:12:15.313832 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3523 10:12:15.313922 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3524 10:12:15.313994 # ok 1797 Set SVE VL 7184
3525 10:12:15.314082 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3526 10:12:15.314157 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3527 10:12:15.314259 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3528 10:12:15.314556 # ok 1801 Set SVE VL 7200
3529 10:12:15.314649 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3530 10:12:15.314725 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3531 10:12:15.314794 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3532 10:12:15.314876 # ok 1805 Set SVE VL 7216
3533 10:12:15.314960 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3534 10:12:15.315033 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3535 10:12:15.315217 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3536 10:12:15.315299 # ok 1809 Set SVE VL 7232
3537 10:12:15.315374 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3538 10:12:15.315624 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3539 10:12:15.315699 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3540 10:12:15.315771 # ok 1813 Set SVE VL 7248
3541 10:12:15.316017 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3542 10:12:15.316266 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3543 10:12:15.316332 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3544 10:12:15.316407 # ok 1817 Set SVE VL 7264
3545 10:12:15.316652 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3546 10:12:15.316733 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3547 10:12:15.316980 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3548 10:12:15.317045 # ok 1821 Set SVE VL 7280
3549 10:12:15.317116 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3550 10:12:15.317368 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3551 10:12:15.317433 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3552 10:12:15.317504 # ok 1825 Set SVE VL 7296
3553 10:12:15.317576 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3554 10:12:15.317656 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3555 10:12:15.317905 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3556 10:12:15.317980 # ok 1829 Set SVE VL 7312
3557 10:12:15.318052 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3558 10:12:15.318297 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3559 10:12:15.318545 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3560 10:12:15.318611 # ok 1833 Set SVE VL 7328
3561 10:12:15.318682 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3562 10:12:15.318754 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3563 10:12:15.319006 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3564 10:12:15.319072 # ok 1837 Set SVE VL 7344
3565 10:12:15.319143 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3566 10:12:15.319389 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3567 10:12:15.319632 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3568 10:12:15.319697 # ok 1841 Set SVE VL 7360
3569 10:12:15.319768 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3570 10:12:15.319830 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3571 10:12:15.320073 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3572 10:12:15.320138 # ok 1845 Set SVE VL 7376
3573 10:12:15.320208 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3574 10:12:15.320462 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3575 10:12:15.320705 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3576 10:12:15.320770 # ok 1849 Set SVE VL 7392
3577 10:12:15.320842 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3578 10:12:15.320915 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3579 10:12:15.321177 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3580 10:12:15.321255 # ok 1853 Set SVE VL 7408
3581 10:12:15.321329 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3582 10:12:15.321577 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3583 10:12:15.321660 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3584 10:12:15.321733 # ok 1857 Set SVE VL 7424
3585 10:12:15.321804 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3586 10:12:15.322049 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3587 10:12:15.322123 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3588 10:12:15.322199 # ok 1861 Set SVE VL 7440
3589 10:12:15.322496 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3590 10:12:15.322592 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3591 10:12:15.322684 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3592 10:12:15.322782 # ok 1865 Set SVE VL 7456
3593 10:12:15.322862 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3594 10:12:15.323147 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3595 10:12:15.323285 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3596 10:12:15.323424 # ok 1869 Set SVE VL 7472
3597 10:12:15.323543 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3598 10:12:15.323663 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3599 10:12:15.323821 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3600 10:12:15.323953 # ok 1873 Set SVE VL 7488
3601 10:12:15.324086 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3602 10:12:15.324203 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3603 10:12:15.324319 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3604 10:12:15.324450 # ok 1877 Set SVE VL 7504
3605 10:12:15.324610 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3606 10:12:15.324747 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3607 10:12:15.324885 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3608 10:12:15.325015 # ok 1881 Set SVE VL 7520
3609 10:12:15.325158 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3610 10:12:15.325293 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3611 10:12:15.325395 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3612 10:12:15.325487 # ok 1885 Set SVE VL 7536
3613 10:12:15.325597 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3614 10:12:15.325708 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3615 10:12:15.325801 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3616 10:12:15.325895 # ok 1889 Set SVE VL 7552
3617 10:12:15.326002 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3618 10:12:15.326096 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3619 10:12:15.326192 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3620 10:12:15.326287 # ok 1893 Set SVE VL 7568
3621 10:12:15.326420 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3622 10:12:15.326542 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3623 10:12:15.326688 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3624 10:12:15.326868 # ok 1897 Set SVE VL 7584
3625 10:12:15.327027 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3626 10:12:15.327159 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3627 10:12:15.327298 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3628 10:12:15.327423 # ok 1901 Set SVE VL 7600
3629 10:12:15.327544 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3630 10:12:15.327657 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3631 10:12:15.327793 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3632 10:12:15.327935 # ok 1905 Set SVE VL 7616
3633 10:12:15.328056 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3634 10:12:15.328170 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3635 10:12:15.328275 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3636 10:12:15.328390 # ok 1909 Set SVE VL 7632
3637 10:12:15.328717 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3638 10:12:15.328845 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3639 10:12:15.328963 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3640 10:12:15.329079 # ok 1913 Set SVE VL 7648
3641 10:12:15.329189 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3642 10:12:15.329278 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3643 10:12:15.329382 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3644 10:12:15.329471 # ok 1917 Set SVE VL 7664
3645 10:12:15.329550 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3646 10:12:15.329631 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3647 10:12:15.329720 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3648 10:12:15.329813 # ok 1921 Set SVE VL 7680
3649 10:12:15.329890 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3650 10:12:15.329980 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3651 10:12:15.330060 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3652 10:12:15.330137 # ok 1925 Set SVE VL 7696
3653 10:12:15.330214 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3654 10:12:15.330293 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3655 10:12:15.330374 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3656 10:12:15.330471 # ok 1929 Set SVE VL 7712
3657 10:12:15.330560 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3658 10:12:15.330663 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3659 10:12:15.330759 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3660 10:12:15.330846 # ok 1933 Set SVE VL 7728
3661 10:12:15.330951 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3662 10:12:15.331036 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3663 10:12:15.331118 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3664 10:12:15.331203 # ok 1937 Set SVE VL 7744
3665 10:12:15.331288 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3666 10:12:15.331390 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3667 10:12:15.331479 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3668 10:12:15.331562 # ok 1941 Set SVE VL 7760
3669 10:12:15.331645 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3670 10:12:15.331745 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3671 10:12:15.331834 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3672 10:12:15.331922 # ok 1945 Set SVE VL 7776
3673 10:12:15.332026 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3674 10:12:15.332118 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3675 10:12:15.332219 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3676 10:12:15.332305 # ok 1949 Set SVE VL 7792
3677 10:12:15.332398 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3678 10:12:15.332484 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3679 10:12:15.332585 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3680 10:12:15.332875 # ok 1953 Set SVE VL 7808
3681 10:12:15.332958 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3682 10:12:15.333034 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3683 10:12:15.334472 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3684 10:12:15.334571 # ok 1957 Set SVE VL 7824
3685 10:12:15.334670 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3686 10:12:15.334745 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3687 10:12:15.334849 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3688 10:12:15.334943 # ok 1961 Set SVE VL 7840
3689 10:12:15.335040 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3690 10:12:15.335140 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3691 10:12:15.335252 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3692 10:12:15.335357 # ok 1965 Set SVE VL 7856
3693 10:12:15.335631 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3694 10:12:15.335734 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3695 10:12:15.335831 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3696 10:12:15.335896 # ok 1969 Set SVE VL 7872
3697 10:12:15.335954 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3698 10:12:15.336024 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3699 10:12:15.336275 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3700 10:12:15.336356 # ok 1973 Set SVE VL 7888
3701 10:12:15.336440 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3702 10:12:15.336524 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3703 10:12:15.336902 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3704 10:12:15.337187 # ok 1977 Set SVE VL 7904
3705 10:12:15.337288 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3706 10:12:15.337397 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3707 10:12:15.337483 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3708 10:12:15.337572 # ok 1981 Set SVE VL 7920
3709 10:12:15.337657 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3710 10:12:15.337753 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3711 10:12:15.337847 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3712 10:12:15.337941 # ok 1985 Set SVE VL 7936
3713 10:12:15.338036 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3714 10:12:15.338133 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3715 10:12:15.338403 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3716 10:12:15.338471 # ok 1989 Set SVE VL 7952
3717 10:12:15.338542 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3718 10:12:15.338805 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3719 10:12:15.338890 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3720 10:12:15.338970 # ok 1993 Set SVE VL 7968
3721 10:12:15.339037 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3722 10:12:15.339121 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3723 10:12:15.339385 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3724 10:12:15.339456 # ok 1997 Set SVE VL 7984
3725 10:12:15.339528 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3726 10:12:15.339606 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3727 10:12:15.339857 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3728 10:12:15.339925 # ok 2001 Set SVE VL 8000
3729 10:12:15.339996 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3730 10:12:15.340072 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3731 10:12:15.340340 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3732 10:12:15.340431 # ok 2005 Set SVE VL 8016
3733 10:12:15.340510 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3734 10:12:15.340778 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3735 10:12:15.340873 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3736 10:12:15.340965 # ok 2009 Set SVE VL 8032
3737 10:12:15.341044 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3738 10:12:15.341134 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3739 10:12:15.341396 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3740 10:12:15.341479 # ok 2013 Set SVE VL 8048
3741 10:12:15.341555 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3742 10:12:15.341654 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3743 10:12:15.341935 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3744 10:12:15.342033 # ok 2017 Set SVE VL 8064
3745 10:12:15.342108 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3746 10:12:15.342192 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3747 10:12:15.342269 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3748 10:12:15.342336 # ok 2021 Set SVE VL 8080
3749 10:12:15.342413 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3750 10:12:15.342484 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3751 10:12:15.342571 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3752 10:12:15.342648 # ok 2025 Set SVE VL 8096
3753 10:12:15.342950 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3754 10:12:15.343049 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3755 10:12:15.343142 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3756 10:12:15.343219 # ok 2029 Set SVE VL 8112
3757 10:12:15.343307 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3758 10:12:15.343399 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3759 10:12:15.343476 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3760 10:12:15.343594 # ok 2033 Set SVE VL 8128
3761 10:12:15.343687 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3762 10:12:15.343779 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3763 10:12:15.344068 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3764 10:12:15.344164 # ok 2037 Set SVE VL 8144
3765 10:12:15.344258 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3766 10:12:15.344338 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3767 10:12:15.344421 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3768 10:12:15.344515 # ok 2041 Set SVE VL 8160
3769 10:12:15.344798 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3770 10:12:15.344881 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3771 10:12:15.344969 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3772 10:12:15.345049 # ok 2045 Set SVE VL 8176
3773 10:12:15.345147 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3774 10:12:15.345246 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3775 10:12:15.345340 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3776 10:12:15.345608 # ok 2049 Set SVE VL 8192
3777 10:12:15.345699 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3778 10:12:15.345786 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3779 10:12:15.345882 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3780 10:12:15.345973 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3781 10:12:15.346060 # ok 2054 Streaming SVE get_fpsimd() gave same state
3782 10:12:15.346150 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3783 10:12:15.346407 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3784 10:12:15.346492 # ok 2057 Set Streaming SVE VL 16
3785 10:12:15.346608 # ok 2058 Set and get Streaming SVE data for VL 16
3786 10:12:15.346709 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3787 10:12:15.346800 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3788 10:12:15.347074 # ok 2061 Set Streaming SVE VL 32
3789 10:12:15.347157 # ok 2062 Set and get Streaming SVE data for VL 32
3790 10:12:15.347246 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3791 10:12:15.347335 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3792 10:12:15.347431 # ok 2065 Set Streaming SVE VL 48
3793 10:12:15.347526 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3794 10:12:15.347622 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3795 10:12:15.347728 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3796 10:12:15.347820 # ok 2069 Set Streaming SVE VL 64
3797 10:12:15.347909 # ok 2070 Set and get Streaming SVE data for VL 64
3798 10:12:15.348149 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3799 10:12:15.348254 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3800 10:12:15.348351 # ok 2073 Set Streaming SVE VL 80
3801 10:12:15.348634 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3802 10:12:15.348745 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3803 10:12:15.349006 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3804 10:12:15.349097 # ok 2077 Set Streaming SVE VL 96
3805 10:12:15.349358 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3806 10:12:15.349439 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3807 10:12:15.349514 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3808 10:12:15.349590 # ok 2081 Set Streaming SVE VL 112
3809 10:12:15.349874 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3810 10:12:15.349970 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3811 10:12:15.350225 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3812 10:12:15.350295 # ok 2085 Set Streaming SVE VL 128
3813 10:12:15.350369 # ok 2086 Set and get Streaming SVE data for VL 128
3814 10:12:15.350460 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3815 10:12:15.350728 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3816 10:12:15.350801 # ok 2089 Set Streaming SVE VL 144
3817 10:12:15.350872 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3818 10:12:15.351120 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3819 10:12:15.351195 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3820 10:12:15.351265 # ok 2093 Set Streaming SVE VL 160
3821 10:12:15.351519 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3822 10:12:15.351598 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3823 10:12:15.351850 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3824 10:12:15.351929 # ok 2097 Set Streaming SVE VL 176
3825 10:12:15.352018 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3826 10:12:15.352111 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3827 10:12:15.352373 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3828 10:12:15.352453 # ok 2101 Set Streaming SVE VL 192
3829 10:12:15.352720 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3830 10:12:15.352809 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3831 10:12:15.353066 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3832 10:12:15.353133 # ok 2105 Set Streaming SVE VL 208
3833 10:12:15.353203 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3834 10:12:15.353449 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3835 10:12:15.353524 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3836 10:12:15.353799 # ok 2109 Set Streaming SVE VL 224
3837 10:12:15.353880 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3838 10:12:15.353962 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3839 10:12:15.354239 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3840 10:12:15.354320 # ok 2113 Set Streaming SVE VL 240
3841 10:12:15.354405 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3842 10:12:15.354496 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3843 10:12:15.354607 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3844 10:12:15.354885 # ok 2117 Set Streaming SVE VL 256
3845 10:12:15.354974 # ok 2118 Set and get Streaming SVE data for VL 256
3846 10:12:15.355063 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3847 10:12:15.355147 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3848 10:12:15.355234 # ok 2121 Set Streaming SVE VL 272
3849 10:12:15.355504 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3850 10:12:15.355599 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3851 10:12:15.355685 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3852 10:12:15.355924 # ok 2125 Set Streaming SVE VL 288
3853 10:12:15.357895 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3854 10:12:15.358202 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3855 10:12:15.358300 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3856 10:12:15.358396 # ok 2129 Set Streaming SVE VL 304
3857 10:12:15.358501 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3858 10:12:15.358604 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3859 10:12:15.358863 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3860 10:12:15.358944 # ok 2133 Set Streaming SVE VL 320
3861 10:12:15.359040 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3862 10:12:15.359133 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3863 10:12:15.359356 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3864 10:12:15.359457 # ok 2137 Set Streaming SVE VL 336
3865 10:12:15.359542 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3866 10:12:15.359798 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3867 10:12:15.359881 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3868 10:12:15.359955 # ok 2141 Set Streaming SVE VL 352
3869 10:12:15.360227 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3870 10:12:15.360307 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3871 10:12:15.360391 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3872 10:12:15.360755 # ok 2145 Set Streaming SVE VL 368
3873 10:12:15.361026 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3874 10:12:15.361118 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3875 10:12:15.361195 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3876 10:12:15.361448 # ok 2149 Set Streaming SVE VL 384
3877 10:12:15.361516 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3878 10:12:15.361768 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3879 10:12:15.361848 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3880 10:12:15.361923 # ok 2153 Set Streaming SVE VL 400
3881 10:12:15.362173 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3882 10:12:15.362429 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3883 10:12:15.362507 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3884 10:12:15.362611 # ok 2157 Set Streaming SVE VL 416
3885 10:12:15.362700 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3886 10:12:15.363022 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3887 10:12:15.363113 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3888 10:12:15.363221 # ok 2161 Set Streaming SVE VL 432
3889 10:12:15.363340 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3890 10:12:15.363437 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3891 10:12:15.363704 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3892 10:12:15.363800 # ok 2165 Set Streaming SVE VL 448
3893 10:12:15.363905 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3894 10:12:15.363984 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3895 10:12:15.364242 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3896 10:12:15.364326 # ok 2169 Set Streaming SVE VL 464
3897 10:12:15.364414 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3898 10:12:15.364673 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3899 10:12:15.364763 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3900 10:12:15.364848 # ok 2173 Set Streaming SVE VL 480
3901 10:12:15.364934 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3902 10:12:15.365206 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3903 10:12:15.365302 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3904 10:12:15.365390 # ok 2177 Set Streaming SVE VL 496
3905 10:12:15.365484 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3906 10:12:15.365800 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3907 10:12:15.365897 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3908 10:12:15.365990 # ok 2181 Set Streaming SVE VL 512
3909 10:12:15.366071 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3910 10:12:15.366167 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3911 10:12:15.366263 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3912 10:12:15.366519 # ok 2185 Set Streaming SVE VL 528
3913 10:12:15.366765 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3914 10:12:15.366834 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3915 10:12:15.366907 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3916 10:12:15.366982 # ok 2189 Set Streaming SVE VL 544
3917 10:12:15.367242 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3918 10:12:15.367320 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3919 10:12:15.367573 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3920 10:12:15.367641 # ok 2193 Set Streaming SVE VL 560
3921 10:12:15.367721 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3922 10:12:15.367983 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3923 10:12:15.368066 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3924 10:12:15.368150 # ok 2197 Set Streaming SVE VL 576
3925 10:12:15.368428 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3926 10:12:15.368507 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3927 10:12:15.368734 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3928 10:12:15.368836 # ok 2201 Set Streaming SVE VL 592
3929 10:12:15.368916 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3930 10:12:15.369166 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3931 10:12:15.369242 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3932 10:12:15.369493 # ok 2205 Set Streaming SVE VL 608
3933 10:12:15.369559 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3934 10:12:15.369809 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3935 10:12:15.370068 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3936 10:12:15.370152 # ok 2209 Set Streaming SVE VL 624
3937 10:12:15.370228 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3938 10:12:15.370316 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3939 10:12:15.370406 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3940 10:12:15.370669 # ok 2213 Set Streaming SVE VL 640
3941 10:12:15.370754 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3942 10:12:15.370846 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3943 10:12:15.371139 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3944 10:12:15.371224 # ok 2217 Set Streaming SVE VL 656
3945 10:12:15.371322 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3946 10:12:15.371699 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3947 10:12:15.371771 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3948 10:12:15.371832 # ok 2221 Set Streaming SVE VL 672
3949 10:12:15.372069 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3950 10:12:15.372134 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3951 10:12:15.372203 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3952 10:12:15.372275 # ok 2225 Set Streaming SVE VL 688
3953 10:12:15.372521 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3954 10:12:15.372763 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3955 10:12:15.373053 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3956 10:12:15.373120 # ok 2229 Set Streaming SVE VL 704
3957 10:12:15.373180 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3958 10:12:15.373417 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3959 10:12:15.373671 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3960 10:12:15.373740 # ok 2233 Set Streaming SVE VL 720
3961 10:12:15.373804 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3962 10:12:15.373877 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3963 10:12:15.373951 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3964 10:12:15.374034 # ok 2237 Set Streaming SVE VL 736
3965 10:12:15.374286 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3966 10:12:15.374366 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3967 10:12:15.374789 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3968 10:12:15.374859 # ok 2241 Set Streaming SVE VL 752
3969 10:12:15.374920 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3970 10:12:15.374996 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3971 10:12:15.375060 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3972 10:12:15.375310 # ok 2245 Set Streaming SVE VL 768
3973 10:12:15.376902 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3974 10:12:15.376971 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3975 10:12:15.377035 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3976 10:12:15.377099 # ok 2249 Set Streaming SVE VL 784
3977 10:12:15.377161 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3978 10:12:15.377223 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3979 10:12:15.377287 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3980 10:12:15.377352 # ok 2253 Set Streaming SVE VL 800
3981 10:12:15.377413 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3982 10:12:15.377475 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3983 10:12:15.377534 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3984 10:12:15.377592 # ok 2257 Set Streaming SVE VL 816
3985 10:12:15.377662 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3986 10:12:15.377725 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3987 10:12:15.377969 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3988 10:12:15.378039 # ok 2261 Set Streaming SVE VL 832
3989 10:12:15.378102 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3990 10:12:15.378162 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3991 10:12:15.378225 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3992 10:12:15.378287 # ok 2265 Set Streaming SVE VL 848
3993 10:12:15.378347 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3994 10:12:15.378422 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3995 10:12:15.378487 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3996 10:12:15.378549 # ok 2269 Set Streaming SVE VL 864
3997 10:12:15.378626 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
3998 10:12:15.378690 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
3999 10:12:15.378751 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4000 10:12:15.378827 # ok 2273 Set Streaming SVE VL 880
4001 10:12:15.378901 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4002 10:12:15.379155 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4003 10:12:15.379235 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4004 10:12:15.379309 # ok 2277 Set Streaming SVE VL 896
4005 10:12:15.379559 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4006 10:12:15.382314 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4007 10:12:15.382419 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4008 10:12:15.382673 # ok 2281 Set Streaming SVE VL 912
4009 10:12:15.382741 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4010 10:12:15.382814 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4011 10:12:15.383068 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4012 10:12:15.383146 # ok 2285 Set Streaming SVE VL 928
4013 10:12:15.383393 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4014 10:12:15.383488 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4015 10:12:15.383749 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4016 10:12:15.383826 # ok 2289 Set Streaming SVE VL 944
4017 10:12:15.384076 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4018 10:12:15.384155 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4019 10:12:15.384582 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4020 10:12:15.384651 # ok 2293 Set Streaming SVE VL 960
4021 10:12:15.385205 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4022 10:12:15.385500 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4023 10:12:15.385572 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4024 10:12:15.385651 # ok 2297 Set Streaming SVE VL 976
4025 10:12:15.385907 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4026 10:12:15.385986 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4027 10:12:15.386252 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4028 10:12:15.386349 # ok 2301 Set Streaming SVE VL 992
4029 10:12:15.386438 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4030 10:12:15.386778 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4031 10:12:15.386896 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4032 10:12:15.386993 # ok 2305 Set Streaming SVE VL 1008
4033 10:12:15.387074 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4034 10:12:15.387169 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4035 10:12:15.387448 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4036 10:12:15.387533 # ok 2309 Set Streaming SVE VL 1024
4037 10:12:15.387619 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4038 10:12:15.387876 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4039 10:12:15.388001 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4040 10:12:15.388114 # ok 2313 Set Streaming SVE VL 1040
4041 10:12:15.388225 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4042 10:12:15.388335 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4043 10:12:15.388635 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4044 10:12:15.388750 # ok 2317 Set Streaming SVE VL 1056
4045 10:12:15.389052 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4046 10:12:15.389152 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4047 10:12:15.389268 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4048 10:12:15.389381 # ok 2321 Set Streaming SVE VL 1072
4049 10:12:15.389491 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4050 10:12:15.389792 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4051 10:12:15.389908 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4052 10:12:15.390021 # ok 2325 Set Streaming SVE VL 1088
4053 10:12:15.390131 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4054 10:12:15.390433 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4055 10:12:15.390533 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4056 10:12:15.390644 # ok 2329 Set Streaming SVE VL 1104
4057 10:12:15.390755 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4058 10:12:15.390866 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4059 10:12:15.391167 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4060 10:12:15.391266 # ok 2333 Set Streaming SVE VL 1120
4061 10:12:15.391380 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4062 10:12:15.391491 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4063 10:12:15.391799 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4064 10:12:15.391899 # ok 2337 Set Streaming SVE VL 1136
4065 10:12:15.392008 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4066 10:12:15.392309 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4067 10:12:15.392408 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4068 10:12:15.392519 # ok 2341 Set Streaming SVE VL 1152
4069 10:12:15.392630 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4070 10:12:15.392930 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4071 10:12:15.393044 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4072 10:12:15.393155 # ok 2345 Set Streaming SVE VL 1168
4073 10:12:15.393268 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4074 10:12:15.393570 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4075 10:12:15.393692 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4076 10:12:15.393805 # ok 2349 Set Streaming SVE VL 1184
4077 10:12:15.394097 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4078 10:12:15.394171 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4079 10:12:15.394441 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4080 10:12:15.394512 # ok 2353 Set Streaming SVE VL 1200
4081 10:12:15.394602 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4082 10:12:15.394876 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4083 10:12:15.394961 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4084 10:12:15.395047 # ok 2357 Set Streaming SVE VL 1216
4085 10:12:15.395309 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4086 10:12:15.395393 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4087 10:12:15.395663 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4088 10:12:15.395749 # ok 2361 Set Streaming SVE VL 1232
4089 10:12:15.396013 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4090 10:12:15.396084 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4091 10:12:15.396175 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4092 10:12:15.396440 # ok 2365 Set Streaming SVE VL 1248
4093 10:12:15.396511 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4094 10:12:15.396777 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4095 10:12:15.396861 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4096 10:12:15.397124 # ok 2369 Set Streaming SVE VL 1264
4097 10:12:15.397209 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4098 10:12:15.397484 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4099 10:12:15.397570 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4100 10:12:15.397662 # ok 2373 Set Streaming SVE VL 1280
4101 10:12:15.397947 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4102 10:12:15.398032 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4103 10:12:15.398312 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4104 10:12:15.398384 # ok 2377 Set Streaming SVE VL 1296
4105 10:12:15.398484 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4106 10:12:15.398745 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4107 10:12:15.398830 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4108 10:12:15.399094 # ok 2381 Set Streaming SVE VL 1312
4109 10:12:15.399178 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4110 10:12:15.399444 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4111 10:12:15.399530 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4112 10:12:15.399616 # ok 2385 Set Streaming SVE VL 1328
4113 10:12:15.399880 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4114 10:12:15.400141 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4115 10:12:15.400226 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4116 10:12:15.400312 # ok 2389 Set Streaming SVE VL 1344
4117 10:12:15.400593 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4118 10:12:15.400713 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4119 10:12:15.401005 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4120 10:12:15.401096 # ok 2393 Set Streaming SVE VL 1360
4121 10:12:15.401178 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4122 10:12:15.401266 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4123 10:12:15.401374 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4124 10:12:15.401694 # ok 2397 Set Streaming SVE VL 1376
4125 10:12:15.401795 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4126 10:12:15.401899 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4127 10:12:15.401987 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4128 10:12:15.402078 # ok 2401 Set Streaming SVE VL 1392
4129 10:12:15.402146 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4130 10:12:15.402425 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4131 10:12:15.402526 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4132 10:12:15.402689 # ok 2405 Set Streaming SVE VL 1408
4133 10:12:15.402794 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4134 10:12:15.402904 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4135 10:12:15.403005 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4136 10:12:15.403075 # ok 2409 Set Streaming SVE VL 1424
4137 10:12:15.403161 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4138 10:12:15.403285 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4139 10:12:15.403429 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4140 10:12:15.403572 # ok 2413 Set Streaming SVE VL 1440
4141 10:12:15.403697 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4142 10:12:15.403801 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4143 10:12:15.404144 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4144 10:12:15.404246 # ok 2417 Set Streaming SVE VL 1456
4145 10:12:15.404345 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4146 10:12:15.404439 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4147 10:12:15.404710 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4148 10:12:15.404982 # ok 2421 Set Streaming SVE VL 1472
4149 10:12:15.405068 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4150 10:12:15.405159 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4151 10:12:15.405431 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4152 10:12:15.405514 # ok 2425 Set Streaming SVE VL 1488
4153 10:12:15.405626 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4154 10:12:15.405743 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4155 10:12:15.405838 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4156 10:12:15.407794 # ok 2429 Set Streaming SVE VL 1504
4157 10:12:15.407927 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4158 10:12:15.408047 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4159 10:12:15.408180 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4160 10:12:15.408326 # ok 2433 Set Streaming SVE VL 1520
4161 10:12:15.408453 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4162 10:12:15.408822 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4163 10:12:15.409107 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4164 10:12:15.409204 # ok 2437 Set Streaming SVE VL 1536
4165 10:12:15.409296 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4166 10:12:15.409399 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4167 10:12:15.409693 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4168 10:12:15.409783 # ok 2441 Set Streaming SVE VL 1552
4169 10:12:15.409878 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4170 10:12:15.409949 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4171 10:12:15.410039 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4172 10:12:15.410143 # ok 2445 Set Streaming SVE VL 1568
4173 10:12:15.410241 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4174 10:12:15.410520 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4175 10:12:15.410625 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4176 10:12:15.410740 # ok 2449 Set Streaming SVE VL 1584
4177 10:12:15.410836 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4178 10:12:15.411122 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4179 10:12:15.411227 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4180 10:12:15.411325 # ok 2453 Set Streaming SVE VL 1600
4181 10:12:15.411421 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4182 10:12:15.411516 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4183 10:12:15.411822 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4184 10:12:15.411927 # ok 2457 Set Streaming SVE VL 1616
4185 10:12:15.412023 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4186 10:12:15.412117 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4187 10:12:15.412407 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4188 10:12:15.412506 # ok 2461 Set Streaming SVE VL 1632
4189 10:12:15.412599 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4190 10:12:15.412866 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4191 10:12:15.412950 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4192 10:12:15.413042 # ok 2465 Set Streaming SVE VL 1648
4193 10:12:15.413134 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4194 10:12:15.413227 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4195 10:12:15.413519 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4196 10:12:15.413618 # ok 2469 Set Streaming SVE VL 1664
4197 10:12:15.413721 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4198 10:12:15.413816 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4199 10:12:15.413907 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4200 10:12:15.413997 # ok 2473 Set Streaming SVE VL 1680
4201 10:12:15.414293 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4202 10:12:15.414392 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4203 10:12:15.414488 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4204 10:12:15.414567 # ok 2477 Set Streaming SVE VL 1696
4205 10:12:15.414656 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4206 10:12:15.414746 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4207 10:12:15.414837 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4208 10:12:15.414927 # ok 2481 Set Streaming SVE VL 1712
4209 10:12:15.415023 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4210 10:12:15.415312 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4211 10:12:15.415426 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4212 10:12:15.415707 # ok 2485 Set Streaming SVE VL 1728
4213 10:12:15.415805 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4214 10:12:15.415899 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4215 10:12:15.415993 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4216 10:12:15.416086 # ok 2489 Set Streaming SVE VL 1744
4217 10:12:15.416178 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4218 10:12:15.416271 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4219 10:12:15.416556 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4220 10:12:15.416668 # ok 2493 Set Streaming SVE VL 1760
4221 10:12:15.416947 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4222 10:12:15.417030 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4223 10:12:15.417184 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4224 10:12:15.417285 # ok 2497 Set Streaming SVE VL 1776
4225 10:12:15.417380 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4226 10:12:15.417471 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4227 10:12:15.417757 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4228 10:12:15.417896 # ok 2501 Set Streaming SVE VL 1792
4229 10:12:15.417996 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4230 10:12:15.418270 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4231 10:12:15.418381 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4232 10:12:15.418486 # ok 2505 Set Streaming SVE VL 1808
4233 10:12:15.418572 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4234 10:12:15.418847 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4235 10:12:15.418942 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4236 10:12:15.419041 # ok 2509 Set Streaming SVE VL 1824
4237 10:12:15.419115 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4238 10:12:15.419200 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4239 10:12:15.419478 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4240 10:12:15.419581 # ok 2513 Set Streaming SVE VL 1840
4241 10:12:15.419661 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4242 10:12:15.419952 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4243 10:12:15.420050 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4244 10:12:15.420141 # ok 2517 Set Streaming SVE VL 1856
4245 10:12:15.420222 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4246 10:12:15.420314 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4247 10:12:15.420589 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4248 10:12:15.420693 # ok 2521 Set Streaming SVE VL 1872
4249 10:12:15.420796 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4250 10:12:15.420883 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4251 10:12:15.421150 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4252 10:12:15.421238 # ok 2525 Set Streaming SVE VL 1888
4253 10:12:15.421317 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4254 10:12:15.421597 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4255 10:12:15.421715 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4256 10:12:15.421811 # ok 2529 Set Streaming SVE VL 1904
4257 10:12:15.421896 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4258 10:12:15.421989 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4259 10:12:15.422284 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4260 10:12:15.422374 # ok 2533 Set Streaming SVE VL 1920
4261 10:12:15.422452 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4262 10:12:15.422548 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4263 10:12:15.422827 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4264 10:12:15.422908 # ok 2537 Set Streaming SVE VL 1936
4265 10:12:15.423006 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4266 10:12:15.423103 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4267 10:12:15.423453 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4268 10:12:15.423547 # ok 2541 Set Streaming SVE VL 1952
4269 10:12:15.423824 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4270 10:12:15.423913 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4271 10:12:15.423985 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4272 10:12:15.424059 # ok 2545 Set Streaming SVE VL 1968
4273 10:12:15.424141 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4274 10:12:15.424250 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4275 10:12:15.424344 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4276 10:12:15.424623 # ok 2549 Set Streaming SVE VL 1984
4277 10:12:15.424720 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4278 10:12:15.424983 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4279 10:12:15.425066 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4280 10:12:15.425152 # ok 2553 Set Streaming SVE VL 2000
4281 10:12:15.425417 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4282 10:12:15.425529 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4283 10:12:15.425839 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4284 10:12:15.425951 # ok 2557 Set Streaming SVE VL 2016
4285 10:12:15.426069 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4286 10:12:15.426153 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4287 10:12:15.426243 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4288 10:12:15.426321 # ok 2561 Set Streaming SVE VL 2032
4289 10:12:15.426413 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4290 10:12:15.426509 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4291 10:12:15.426798 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4292 10:12:15.426886 # ok 2565 Set Streaming SVE VL 2048
4293 10:12:15.426966 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4294 10:12:15.427061 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4295 10:12:15.427340 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4296 10:12:15.427444 # ok 2569 Set Streaming SVE VL 2064
4297 10:12:15.427562 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4298 10:12:15.427662 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4299 10:12:15.427953 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4300 10:12:15.428058 # ok 2573 Set Streaming SVE VL 2080
4301 10:12:15.428153 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4302 10:12:15.428247 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4303 10:12:15.428537 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4304 10:12:15.428635 # ok 2577 Set Streaming SVE VL 2096
4305 10:12:15.428729 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4306 10:12:15.430205 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4307 10:12:15.430499 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4308 10:12:15.430592 # ok 2581 Set Streaming SVE VL 2112
4309 10:12:15.430715 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4310 10:12:15.430819 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4311 10:12:15.430918 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4312 10:12:15.431014 # ok 2585 Set Streaming SVE VL 2128
4313 10:12:15.431111 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4314 10:12:15.431205 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4315 10:12:15.431499 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4316 10:12:15.431597 # ok 2589 Set Streaming SVE VL 2144
4317 10:12:15.431695 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4318 10:12:15.431985 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4319 10:12:15.432076 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4320 10:12:15.432163 # ok 2593 Set Streaming SVE VL 2160
4321 10:12:15.432241 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4322 10:12:15.432521 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4323 10:12:15.432810 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4324 10:12:15.432926 # ok 2597 Set Streaming SVE VL 2176
4325 10:12:15.433022 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4326 10:12:15.433323 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4327 10:12:15.433421 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4328 10:12:15.433515 # ok 2601 Set Streaming SVE VL 2192
4329 10:12:15.433598 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4330 10:12:15.433706 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4331 10:12:15.433998 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4332 10:12:15.434084 # ok 2605 Set Streaming SVE VL 2208
4333 10:12:15.434177 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4334 10:12:15.434442 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4335 10:12:15.434540 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4336 10:12:15.434633 # ok 2609 Set Streaming SVE VL 2224
4337 10:12:15.434728 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4338 10:12:15.434820 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4339 10:12:15.435112 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4340 10:12:15.435211 # ok 2613 Set Streaming SVE VL 2240
4341 10:12:15.435306 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4342 10:12:15.435398 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4343 10:12:15.435688 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4344 10:12:15.435813 # ok 2617 Set Streaming SVE VL 2256
4345 10:12:15.435917 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4346 10:12:15.436000 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4347 10:12:15.436091 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4348 10:12:15.436169 # ok 2621 Set Streaming SVE VL 2272
4349 10:12:15.436258 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4350 10:12:15.436355 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4351 10:12:15.436667 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4352 10:12:15.436799 # ok 2625 Set Streaming SVE VL 2288
4353 10:12:15.436928 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4354 10:12:15.437021 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4355 10:12:15.437115 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4356 10:12:15.437211 # ok 2629 Set Streaming SVE VL 2304
4357 10:12:15.437334 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4358 10:12:15.437439 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4359 10:12:15.437561 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4360 10:12:15.437791 # ok 2633 Set Streaming SVE VL 2320
4361 10:12:15.437916 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4362 10:12:15.438032 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4363 10:12:15.438335 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4364 10:12:15.438429 # ok 2637 Set Streaming SVE VL 2336
4365 10:12:15.438526 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4366 10:12:15.438606 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4367 10:12:15.438699 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4368 10:12:15.438796 # ok 2641 Set Streaming SVE VL 2352
4369 10:12:15.438901 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4370 10:12:15.439181 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4371 10:12:15.439269 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4372 10:12:15.439350 # ok 2645 Set Streaming SVE VL 2368
4373 10:12:15.439442 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4374 10:12:15.439723 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4375 10:12:15.439821 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4376 10:12:15.439903 # ok 2649 Set Streaming SVE VL 2384
4377 10:12:15.439995 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4378 10:12:15.440090 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4379 10:12:15.440378 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4380 10:12:15.440480 # ok 2653 Set Streaming SVE VL 2400
4381 10:12:15.440607 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4382 10:12:15.440895 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4383 10:12:15.440991 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4384 10:12:15.441069 # ok 2657 Set Streaming SVE VL 2416
4385 10:12:15.441338 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4386 10:12:15.441438 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4387 10:12:15.441529 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4388 10:12:15.441607 # ok 2661 Set Streaming SVE VL 2432
4389 10:12:15.441898 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4390 10:12:15.442007 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4391 10:12:15.442109 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4392 10:12:15.442204 # ok 2665 Set Streaming SVE VL 2448
4393 10:12:15.442303 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4394 10:12:15.442592 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4395 10:12:15.442706 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4396 10:12:15.442793 # ok 2669 Set Streaming SVE VL 2464
4397 10:12:15.442885 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4398 10:12:15.443181 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4399 10:12:15.443288 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4400 10:12:15.443390 # ok 2673 Set Streaming SVE VL 2480
4401 10:12:15.443482 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4402 10:12:15.443756 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4403 10:12:15.443857 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4404 10:12:15.443961 # ok 2677 Set Streaming SVE VL 2496
4405 10:12:15.444049 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4406 10:12:15.444331 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4407 10:12:15.444452 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4408 10:12:15.444548 # ok 2681 Set Streaming SVE VL 2512
4409 10:12:15.444663 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4410 10:12:15.444957 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4411 10:12:15.445051 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4412 10:12:15.445138 # ok 2685 Set Streaming SVE VL 2528
4413 10:12:15.445223 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4414 10:12:15.445501 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4415 10:12:15.445599 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4416 10:12:15.445705 # ok 2689 Set Streaming SVE VL 2544
4417 10:12:15.445791 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4418 10:12:15.446063 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4419 10:12:15.446173 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4420 10:12:15.446286 # ok 2693 Set Streaming SVE VL 2560
4421 10:12:15.446591 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4422 10:12:15.446686 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4423 10:12:15.446807 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4424 10:12:15.446902 # ok 2697 Set Streaming SVE VL 2576
4425 10:12:15.446998 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4426 10:12:15.447279 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4427 10:12:15.447375 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4428 10:12:15.447458 # ok 2701 Set Streaming SVE VL 2592
4429 10:12:15.447585 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4430 10:12:15.447703 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4431 10:12:15.447792 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4432 10:12:15.447881 # ok 2705 Set Streaming SVE VL 2608
4433 10:12:15.447986 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4434 10:12:15.448188 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4435 10:12:15.448303 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4436 10:12:15.448449 # ok 2709 Set Streaming SVE VL 2624
4437 10:12:15.448736 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4438 10:12:15.448850 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4439 10:12:15.449128 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4440 10:12:15.449213 # ok 2713 Set Streaming SVE VL 2640
4441 10:12:15.449305 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4442 10:12:15.449407 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4443 10:12:15.449679 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4444 10:12:15.449777 # ok 2717 Set Streaming SVE VL 2656
4445 10:12:15.449869 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4446 10:12:15.450166 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4447 10:12:15.450277 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4448 10:12:15.450360 # ok 2721 Set Streaming SVE VL 2672
4449 10:12:15.450452 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4450 10:12:15.450546 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4451 10:12:15.450827 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4452 10:12:15.450913 # ok 2725 Set Streaming SVE VL 2688
4453 10:12:15.451003 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4454 10:12:15.451093 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4455 10:12:15.452518 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4456 10:12:15.452635 # ok 2729 Set Streaming SVE VL 2704
4457 10:12:15.452940 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4458 10:12:15.453062 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4459 10:12:15.453350 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4460 10:12:15.453453 # ok 2733 Set Streaming SVE VL 2720
4461 10:12:15.453562 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4462 10:12:15.453743 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4463 10:12:15.453863 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4464 10:12:15.453986 # ok 2737 Set Streaming SVE VL 2736
4465 10:12:15.454103 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4466 10:12:15.454214 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4467 10:12:15.454321 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4468 10:12:15.454522 # ok 2741 Set Streaming SVE VL 2752
4469 10:12:15.454630 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4470 10:12:15.454735 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4471 10:12:15.454853 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4472 10:12:15.454950 # ok 2745 Set Streaming SVE VL 2768
4473 10:12:15.455073 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4474 10:12:15.455357 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4475 10:12:15.455471 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4476 10:12:15.455587 # ok 2749 Set Streaming SVE VL 2784
4477 10:12:15.455705 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4478 10:12:15.455999 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4479 10:12:15.456087 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4480 10:12:15.456187 # ok 2753 Set Streaming SVE VL 2800
4481 10:12:15.456288 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4482 10:12:15.456366 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4483 10:12:15.456650 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4484 10:12:15.456758 # ok 2757 Set Streaming SVE VL 2816
4485 10:12:15.456837 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4486 10:12:15.457122 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4487 10:12:15.457218 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4488 10:12:15.457319 # ok 2761 Set Streaming SVE VL 2832
4489 10:12:15.457415 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4490 10:12:15.457521 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4491 10:12:15.457810 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4492 10:12:15.457907 # ok 2765 Set Streaming SVE VL 2848
4493 10:12:15.458029 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4494 10:12:15.458134 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4495 10:12:15.458263 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4496 10:12:15.458389 # ok 2769 Set Streaming SVE VL 2864
4497 10:12:15.458735 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4498 10:12:15.458835 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4499 10:12:15.458931 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4500 10:12:15.459014 # ok 2773 Set Streaming SVE VL 2880
4501 10:12:15.459106 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4502 10:12:15.459394 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4503 10:12:15.459500 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4504 10:12:15.459595 # ok 2777 Set Streaming SVE VL 2896
4505 10:12:15.459676 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4506 10:12:15.459767 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4507 10:12:15.459861 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4508 10:12:15.459952 # ok 2781 Set Streaming SVE VL 2912
4509 10:12:15.460243 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4510 10:12:15.460343 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4511 10:12:15.460437 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4512 10:12:15.460530 # ok 2785 Set Streaming SVE VL 2928
4513 10:12:15.460812 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4514 10:12:15.460910 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4515 10:12:15.461003 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4516 10:12:15.461097 # ok 2789 Set Streaming SVE VL 2944
4517 10:12:15.461387 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4518 10:12:15.461486 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4519 10:12:15.461581 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4520 10:12:15.461669 # ok 2793 Set Streaming SVE VL 2960
4521 10:12:15.461761 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4522 10:12:15.462057 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4523 10:12:15.462170 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4524 10:12:15.462251 # ok 2797 Set Streaming SVE VL 2976
4525 10:12:15.462341 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4526 10:12:15.462628 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4527 10:12:15.462735 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4528 10:12:15.462816 # ok 2801 Set Streaming SVE VL 2992
4529 10:12:15.462903 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4530 10:12:15.463196 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4531 10:12:15.463292 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4532 10:12:15.463391 # ok 2805 Set Streaming SVE VL 3008
4533 10:12:15.463488 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4534 10:12:15.463773 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4535 10:12:15.463863 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4536 10:12:15.463943 # ok 2809 Set Streaming SVE VL 3024
4537 10:12:15.464042 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4538 10:12:15.464330 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4539 10:12:15.464440 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4540 10:12:15.464567 # ok 2813 Set Streaming SVE VL 3040
4541 10:12:15.464866 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4542 10:12:15.464980 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4543 10:12:15.465270 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4544 10:12:15.465363 # ok 2817 Set Streaming SVE VL 3056
4545 10:12:15.465466 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4546 10:12:15.465548 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4547 10:12:15.465654 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4548 10:12:15.465776 # ok 2821 Set Streaming SVE VL 3072
4549 10:12:15.465887 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4550 10:12:15.466176 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4551 10:12:15.466285 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4552 10:12:15.466384 # ok 2825 Set Streaming SVE VL 3088
4553 10:12:15.466665 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4554 10:12:15.466750 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4555 10:12:15.466868 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4556 10:12:15.466983 # ok 2829 Set Streaming SVE VL 3104
4557 10:12:15.467091 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4558 10:12:15.467199 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4559 10:12:15.467508 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4560 10:12:15.467607 # ok 2833 Set Streaming SVE VL 3120
4561 10:12:15.467720 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4562 10:12:15.467824 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4563 10:12:15.467907 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4564 10:12:15.467988 # ok 2837 Set Streaming SVE VL 3136
4565 10:12:15.468266 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4566 10:12:15.468374 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4567 10:12:15.468488 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4568 10:12:15.468569 # ok 2841 Set Streaming SVE VL 3152
4569 10:12:15.468845 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4570 10:12:15.468937 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4571 10:12:15.469038 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4572 10:12:15.469139 # ok 2845 Set Streaming SVE VL 3168
4573 10:12:15.469331 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4574 10:12:15.469451 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4575 10:12:15.469576 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4576 10:12:15.469705 # ok 2849 Set Streaming SVE VL 3184
4577 10:12:15.469812 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4578 10:12:15.469903 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4579 10:12:15.470182 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4580 10:12:15.470287 # ok 2853 Set Streaming SVE VL 3200
4581 10:12:15.470369 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4582 10:12:15.470478 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4583 10:12:15.470782 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4584 10:12:15.470883 # ok 2857 Set Streaming SVE VL 3216
4585 10:12:15.470989 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4586 10:12:15.471090 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4587 10:12:15.471185 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4588 10:12:15.471279 # ok 2861 Set Streaming SVE VL 3232
4589 10:12:15.471558 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4590 10:12:15.471643 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4591 10:12:15.471726 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4592 10:12:15.471983 # ok 2865 Set Streaming SVE VL 3248
4593 10:12:15.472060 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4594 10:12:15.472308 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4595 10:12:15.472384 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4596 10:12:15.472457 # ok 2869 Set Streaming SVE VL 3264
4597 10:12:15.472883 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4598 10:12:15.472963 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4599 10:12:15.473212 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4600 10:12:15.473280 # ok 2873 Set Streaming SVE VL 3280
4601 10:12:15.473351 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4602 10:12:15.473601 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4603 10:12:15.473869 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4604 10:12:15.473937 # ok 2877 Set Streaming SVE VL 3296
4605 10:12:15.491906 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4606 10:12:15.492360 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4607 10:12:15.492453 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4608 10:12:15.492538 # ok 2881 Set Streaming SVE VL 3312
4609 10:12:15.492633 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4610 10:12:15.494505 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4611 10:12:15.494840 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4612 10:12:15.494943 # ok 2885 Set Streaming SVE VL 3328
4613 10:12:15.495035 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4614 10:12:15.495142 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4615 10:12:15.495235 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4616 10:12:15.495361 # ok 2889 Set Streaming SVE VL 3344
4617 10:12:15.495506 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4618 10:12:15.495615 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4619 10:12:15.495904 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4620 10:12:15.496001 # ok 2893 Set Streaming SVE VL 3360
4621 10:12:15.496091 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4622 10:12:15.496197 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4623 10:12:15.496304 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4624 10:12:15.496408 # ok 2897 Set Streaming SVE VL 3376
4625 10:12:15.496523 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4626 10:12:15.501523 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4627 10:12:15.501846 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4628 10:12:15.501945 # ok 2901 Set Streaming SVE VL 3392
4629 10:12:15.502052 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4630 10:12:15.502144 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4631 10:12:15.502436 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4632 10:12:15.502532 # ok 2905 Set Streaming SVE VL 3408
4633 10:12:15.502637 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4634 10:12:15.502743 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4635 10:12:15.502847 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4636 10:12:15.502939 # ok 2909 Set Streaming SVE VL 3424
4637 10:12:15.503044 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4638 10:12:15.503147 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4639 10:12:15.503444 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4640 10:12:15.503558 # ok 2913 Set Streaming SVE VL 3440
4641 10:12:15.503665 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4642 10:12:15.503771 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4643 10:12:15.504065 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4644 10:12:15.504161 # ok 2917 Set Streaming SVE VL 3456
4645 10:12:15.504266 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4646 10:12:15.504372 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4647 10:12:15.509617 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4648 10:12:15.509947 # ok 2921 Set Streaming SVE VL 3472
4649 10:12:15.510049 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4650 10:12:15.510161 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4651 10:12:15.510256 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4652 10:12:15.510365 # ok 2925 Set Streaming SVE VL 3488
4653 10:12:15.510501 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4654 10:12:15.510802 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4655 10:12:15.510916 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4656 10:12:15.511025 # ok 2929 Set Streaming SVE VL 3504
4657 10:12:15.511135 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4658 10:12:15.511245 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4659 10:12:15.511550 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4660 10:12:15.511632 # ok 2933 Set Streaming SVE VL 3520
4661 10:12:15.511707 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4662 10:12:15.511954 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4663 10:12:15.512203 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4664 10:12:15.512269 # ok 2937 Set Streaming SVE VL 3536
4665 10:12:15.512339 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4666 10:12:15.512598 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4667 10:12:15.518245 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4668 10:12:15.518508 # ok 2941 Set Streaming SVE VL 3552
4669 10:12:15.518584 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4670 10:12:15.518829 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4671 10:12:15.518903 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4672 10:12:15.518974 # ok 2945 Set Streaming SVE VL 3568
4673 10:12:15.519219 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4674 10:12:15.519284 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4675 10:12:15.519555 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4676 10:12:15.519636 # ok 2949 Set Streaming SVE VL 3584
4677 10:12:15.519711 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4678 10:12:15.519792 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4679 10:12:15.520059 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4680 10:12:15.520139 # ok 2953 Set Streaming SVE VL 3600
4681 10:12:15.520384 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4682 10:12:15.520471 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4683 10:12:15.521004 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4684 10:12:15.521251 # ok 2957 Set Streaming SVE VL 3616
4685 10:12:15.521315 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4686 10:12:15.521386 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4687 10:12:15.521631 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4688 10:12:15.521702 # ok 2961 Set Streaming SVE VL 3632
4689 10:12:15.521949 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4690 10:12:15.522197 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4691 10:12:15.522261 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4692 10:12:15.522332 # ok 2965 Set Streaming SVE VL 3648
4693 10:12:15.522577 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4694 10:12:15.522825 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4695 10:12:15.522889 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4696 10:12:15.522959 # ok 2969 Set Streaming SVE VL 3664
4697 10:12:15.523204 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4698 10:12:15.523278 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4699 10:12:15.523552 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4700 10:12:15.523644 # ok 2973 Set Streaming SVE VL 3680
4701 10:12:15.523905 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4702 10:12:15.523986 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4703 10:12:15.524238 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4704 10:12:15.524304 # ok 2977 Set Streaming SVE VL 3696
4705 10:12:15.524378 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4706 10:12:15.524639 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4707 10:12:15.527081 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4708 10:12:15.527365 # ok 2981 Set Streaming SVE VL 3712
4709 10:12:15.527474 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4710 10:12:15.527591 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4711 10:12:15.527886 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4712 10:12:15.527986 # ok 2985 Set Streaming SVE VL 3728
4713 10:12:15.528086 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4714 10:12:15.528373 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4715 10:12:15.528483 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4716 10:12:15.528581 # ok 2989 Set Streaming SVE VL 3744
4717 10:12:15.528678 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4718 10:12:15.528942 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4719 10:12:15.529048 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4720 10:12:15.529298 # ok 2993 Set Streaming SVE VL 3760
4721 10:12:15.529374 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4722 10:12:15.529620 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4723 10:12:15.529735 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4724 10:12:15.534651 # ok 2997 Set Streaming SVE VL 3776
4725 10:12:15.534933 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4726 10:12:15.535054 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4727 10:12:15.535186 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4728 10:12:15.535273 # ok 3001 Set Streaming SVE VL 3792
4729 10:12:15.535398 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4730 10:12:15.535688 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4731 10:12:15.535801 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4732 10:12:15.535883 # ok 3005 Set Streaming SVE VL 3808
4733 10:12:15.535975 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4734 10:12:15.536063 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4735 10:12:15.536319 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4736 10:12:15.536405 # ok 3009 Set Streaming SVE VL 3824
4737 10:12:15.536508 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4738 10:12:15.542566 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4739 10:12:15.542844 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4740 10:12:15.542924 # ok 3013 Set Streaming SVE VL 3840
4741 10:12:15.543016 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4742 10:12:15.543087 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4743 10:12:15.543356 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4744 10:12:15.543431 # ok 3017 Set Streaming SVE VL 3856
4745 10:12:15.543829 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4746 10:12:15.543938 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4747 10:12:15.544025 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4748 10:12:15.544312 # ok 3021 Set Streaming SVE VL 3872
4749 10:12:15.544414 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4750 10:12:15.544503 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4751 10:12:15.544591 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4752 10:12:15.544696 # ok 3025 Set Streaming SVE VL 3888
4753 10:12:15.545421 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4754 10:12:15.546334 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4755 10:12:15.546631 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4756 10:12:15.546724 # ok 3029 Set Streaming SVE VL 3904
4757 10:12:15.546827 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4758 10:12:15.546929 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4759 10:12:15.547227 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4760 10:12:15.547333 # ok 3033 Set Streaming SVE VL 3920
4761 10:12:15.547429 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4762 10:12:15.547522 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4763 10:12:15.547806 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4764 10:12:15.547917 # ok 3037 Set Streaming SVE VL 3936
4765 10:12:15.548184 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4766 10:12:15.548474 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4767 10:12:15.548743 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4768 10:12:15.548812 # ok 3041 Set Streaming SVE VL 3952
4769 10:12:15.557715 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4770 10:12:15.557992 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4771 10:12:15.558083 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4772 10:12:15.558202 # ok 3045 Set Streaming SVE VL 3968
4773 10:12:15.558297 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4774 10:12:15.558400 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4775 10:12:15.558503 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4776 10:12:15.558619 # ok 3049 Set Streaming SVE VL 3984
4777 10:12:15.558740 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4778 10:12:15.558840 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4779 10:12:15.559126 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4780 10:12:15.559237 # ok 3053 Set Streaming SVE VL 4000
4781 10:12:15.559351 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4782 10:12:15.559469 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4783 10:12:15.559770 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4784 10:12:15.559870 # ok 3057 Set Streaming SVE VL 4016
4785 10:12:15.559963 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4786 10:12:15.560204 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4787 10:12:15.560312 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4788 10:12:15.560588 # ok 3061 Set Streaming SVE VL 4032
4789 10:12:15.560666 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4790 10:12:15.563099 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4791 10:12:15.563424 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4792 10:12:15.563552 # ok 3065 Set Streaming SVE VL 4048
4793 10:12:15.563654 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4794 10:12:15.563764 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4795 10:12:15.563856 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4796 10:12:15.563964 # ok 3069 Set Streaming SVE VL 4064
4797 10:12:15.564061 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4798 10:12:15.564159 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4799 10:12:15.564293 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4800 10:12:15.564578 # ok 3073 Set Streaming SVE VL 4080
4801 10:12:15.564657 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4802 10:12:15.567849 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4803 10:12:15.567957 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4804 10:12:15.568072 # ok 3077 Set Streaming SVE VL 4096
4805 10:12:15.568170 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4806 10:12:15.568458 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4807 10:12:15.568578 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4808 10:12:15.568698 # ok 3081 Set Streaming SVE VL 4112
4809 10:12:15.568809 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4810 10:12:15.568925 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4811 10:12:15.569217 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4812 10:12:15.574081 # ok 3085 Set Streaming SVE VL 4128
4813 10:12:15.574353 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4814 10:12:15.574446 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4815 10:12:15.574550 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4816 10:12:15.574662 # ok 3089 Set Streaming SVE VL 4144
4817 10:12:15.574768 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4818 10:12:15.575079 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4819 10:12:15.575184 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4820 10:12:15.575266 # ok 3093 Set Streaming SVE VL 4160
4821 10:12:15.575379 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4822 10:12:15.575493 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4823 10:12:15.575621 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4824 10:12:15.575898 # ok 3097 Set Streaming SVE VL 4176
4825 10:12:15.575986 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4826 10:12:15.576064 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4827 10:12:15.576316 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4828 10:12:15.576386 # ok 3101 Set Streaming SVE VL 4192
4829 10:12:15.576504 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4830 10:12:15.581666 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4831 10:12:15.581948 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4832 10:12:15.582040 # ok 3105 Set Streaming SVE VL 4208
4833 10:12:15.582155 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4834 10:12:15.582279 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4835 10:12:15.582398 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4836 10:12:15.582498 # ok 3109 Set Streaming SVE VL 4224
4837 10:12:15.582590 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4838 10:12:15.582872 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4839 10:12:15.582970 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4840 10:12:15.583057 # ok 3113 Set Streaming SVE VL 4240
4841 10:12:15.583135 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4842 10:12:15.583222 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4843 10:12:15.583510 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4844 10:12:15.583630 # ok 3117 Set Streaming SVE VL 4256
4845 10:12:15.583750 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4846 10:12:15.584041 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4847 10:12:15.584133 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4848 10:12:15.584226 # ok 3121 Set Streaming SVE VL 4272
4849 10:12:15.584316 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4850 10:12:15.584437 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4851 10:12:15.589482 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4852 10:12:15.589760 # ok 3125 Set Streaming SVE VL 4288
4853 10:12:15.589853 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4854 10:12:15.589963 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4855 10:12:15.590066 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4856 10:12:15.590154 # ok 3129 Set Streaming SVE VL 4304
4857 10:12:15.590423 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4858 10:12:15.590514 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4859 10:12:15.590612 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4860 10:12:15.590707 # ok 3133 Set Streaming SVE VL 4320
4861 10:12:15.590803 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4862 10:12:15.591110 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4863 10:12:15.591210 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4864 10:12:15.591306 # ok 3137 Set Streaming SVE VL 4336
4865 10:12:15.591387 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4866 10:12:15.591478 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4867 10:12:15.591767 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4868 10:12:15.591854 # ok 3141 Set Streaming SVE VL 4352
4869 10:12:15.591945 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4870 10:12:15.592035 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4871 10:12:15.592333 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4872 10:12:15.592447 # ok 3145 Set Streaming SVE VL 4368
4873 10:12:15.592547 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4874 10:12:15.601634 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4875 10:12:15.602005 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4876 10:12:15.602101 # ok 3149 Set Streaming SVE VL 4384
4877 10:12:15.602204 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4878 10:12:15.602325 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4879 10:12:15.602433 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4880 10:12:15.602542 # ok 3153 Set Streaming SVE VL 4400
4881 10:12:15.602656 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4882 10:12:15.602740 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4883 10:12:15.602864 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4884 10:12:15.602997 # ok 3157 Set Streaming SVE VL 4416
4885 10:12:15.603095 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4886 10:12:15.603229 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4887 10:12:15.603361 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4888 10:12:15.603464 # ok 3161 Set Streaming SVE VL 4432
4889 10:12:15.603751 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4890 10:12:15.603858 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4891 10:12:15.603980 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4892 10:12:15.604066 # ok 3165 Set Streaming SVE VL 4448
4893 10:12:15.604155 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4894 10:12:15.604231 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4895 10:12:15.604331 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4896 10:12:15.604448 # ok 3169 Set Streaming SVE VL 4464
4897 10:12:15.604734 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4898 10:12:15.621674 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4899 10:12:15.622040 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4900 10:12:15.622177 # ok 3173 Set Streaming SVE VL 4480
4901 10:12:15.622276 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4902 10:12:15.622371 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4903 10:12:15.622453 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4904 10:12:15.623136 # ok 3177 Set Streaming SVE VL 4496
4905 10:12:15.623242 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4906 10:12:15.623349 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4907 10:12:15.623460 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4908 10:12:15.623545 # ok 3181 Set Streaming SVE VL 4512
4909 10:12:15.623670 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4910 10:12:15.623877 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4911 10:12:15.624101 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4912 10:12:15.624269 # ok 3185 Set Streaming SVE VL 4528
4913 10:12:15.624433 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4914 10:12:15.624600 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4915 10:12:15.636486 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4916 10:12:15.636651 # ok 3189 Set Streaming SVE VL 4544
4917 10:12:15.637418 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4918 10:12:15.637768 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4919 10:12:15.637981 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4920 10:12:15.638157 # ok 3193 Set Streaming SVE VL 4560
4921 10:12:15.638336 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4922 10:12:15.638507 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4923 10:12:15.638693 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4924 10:12:15.638920 # ok 3197 Set Streaming SVE VL 4576
4925 10:12:15.639081 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4926 10:12:15.639236 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4927 10:12:15.639430 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4928 10:12:15.639656 # ok 3201 Set Streaming SVE VL 4592
4929 10:12:15.639825 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4930 10:12:15.639994 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4931 10:12:15.640150 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4932 10:12:15.640297 # ok 3205 Set Streaming SVE VL 4608
4933 10:12:15.640439 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4934 10:12:15.640640 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4935 10:12:15.640774 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4936 10:12:15.640903 # ok 3209 Set Streaming SVE VL 4624
4937 10:12:15.641018 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4938 10:12:15.641132 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4939 10:12:15.641246 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4940 10:12:15.641359 # ok 3213 Set Streaming SVE VL 4640
4941 10:12:15.648076 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4942 10:12:15.648470 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4943 10:12:15.648653 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4944 10:12:15.648862 # ok 3217 Set Streaming SVE VL 4656
4945 10:12:15.649003 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4946 10:12:15.654178 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4947 10:12:15.654568 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4948 10:12:15.654761 # ok 3221 Set Streaming SVE VL 4672
4949 10:12:15.654935 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4950 10:12:15.655115 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4951 10:12:15.655258 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4952 10:12:15.655439 # ok 3225 Set Streaming SVE VL 4688
4953 10:12:15.655616 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4954 10:12:15.655829 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4955 10:12:15.655986 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4956 10:12:15.656131 # ok 3229 Set Streaming SVE VL 4704
4957 10:12:15.656293 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4958 10:12:15.656452 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4959 10:12:15.656629 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4960 10:12:15.656774 # ok 3233 Set Streaming SVE VL 4720
4961 10:12:15.656890 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4962 10:12:15.657005 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4963 10:12:15.657118 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4964 10:12:15.657255 # ok 3237 Set Streaming SVE VL 4736
4965 10:12:15.659953 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4966 10:12:15.660258 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4967 10:12:15.660360 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4968 10:12:15.660440 # ok 3241 Set Streaming SVE VL 4752
4969 10:12:15.660535 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4970 10:12:15.660614 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4971 10:12:15.660900 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4972 10:12:15.660999 # ok 3245 Set Streaming SVE VL 4768
4973 10:12:15.661080 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4974 10:12:15.668475 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4975 10:12:15.668784 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4976 10:12:15.669948 # ok 3249 Set Streaming SVE VL 4784
4977 10:12:15.670243 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4978 10:12:15.670354 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4979 10:12:15.670449 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4980 10:12:15.670541 # ok 3253 Set Streaming SVE VL 4800
4981 10:12:15.670633 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4982 10:12:15.670937 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4983 10:12:15.671123 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4984 10:12:15.671251 # ok 3257 Set Streaming SVE VL 4816
4985 10:12:15.671451 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4986 10:12:15.671613 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4987 10:12:15.671818 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4988 10:12:15.672014 # ok 3261 Set Streaming SVE VL 4832
4989 10:12:15.672157 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4990 10:12:15.672278 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4991 10:12:15.672417 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4992 10:12:15.672553 # ok 3265 Set Streaming SVE VL 4848
4993 10:12:15.672723 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4994 10:12:15.672896 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4995 10:12:15.673032 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4996 10:12:15.677788 # ok 3269 Set Streaming SVE VL 4864
4997 10:12:15.678138 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
4998 10:12:15.678323 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
4999 10:12:15.678549 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5000 10:12:15.678726 # ok 3273 Set Streaming SVE VL 4880
5001 10:12:15.678881 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5002 10:12:15.679067 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5003 10:12:15.679221 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5004 10:12:15.679381 # ok 3277 Set Streaming SVE VL 4896
5005 10:12:15.679581 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5006 10:12:15.679780 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5007 10:12:15.679936 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5008 10:12:15.680083 # ok 3281 Set Streaming SVE VL 4912
5009 10:12:15.680217 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5010 10:12:15.680332 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5011 10:12:15.680472 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5012 10:12:15.680600 # ok 3285 Set Streaming SVE VL 4928
5013 10:12:15.680717 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5014 10:12:15.680832 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5015 10:12:15.680947 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5016 10:12:15.681081 # ok 3289 Set Streaming SVE VL 4944
5017 10:12:15.685789 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5018 10:12:15.686201 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5019 10:12:15.686373 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5020 10:12:15.686549 # ok 3293 Set Streaming SVE VL 4960
5021 10:12:15.686730 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5022 10:12:15.686874 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5023 10:12:15.687049 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5024 10:12:15.687186 # ok 3297 Set Streaming SVE VL 4976
5025 10:12:15.687341 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5026 10:12:15.687541 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5027 10:12:15.687705 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5028 10:12:15.687830 # ok 3301 Set Streaming SVE VL 4992
5029 10:12:15.687948 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5030 10:12:15.688064 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5031 10:12:15.688203 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5032 10:12:15.688332 # ok 3305 Set Streaming SVE VL 5008
5033 10:12:15.688504 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5034 10:12:15.688654 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5035 10:12:15.688831 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5036 10:12:15.688970 # ok 3309 Set Streaming SVE VL 5024
5037 10:12:15.689112 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5038 10:12:15.694142 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5039 10:12:15.694465 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5040 10:12:15.694630 # ok 3313 Set Streaming SVE VL 5040
5041 10:12:15.694820 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5042 10:12:15.695000 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5043 10:12:15.695130 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5044 10:12:15.695281 # ok 3317 Set Streaming SVE VL 5056
5045 10:12:15.695474 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5046 10:12:15.695672 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5047 10:12:15.695868 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5048 10:12:15.696006 # ok 3321 Set Streaming SVE VL 5072
5049 10:12:15.696129 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5050 10:12:15.696279 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5051 10:12:15.696405 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5052 10:12:15.696521 # ok 3325 Set Streaming SVE VL 5088
5053 10:12:15.696634 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5054 10:12:15.697508 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5055 10:12:15.697900 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5056 10:12:15.698056 # ok 3329 Set Streaming SVE VL 5104
5057 10:12:15.698205 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5058 10:12:15.698380 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5059 10:12:15.698517 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5060 10:12:15.698658 # ok 3333 Set Streaming SVE VL 5120
5061 10:12:15.698830 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5062 10:12:15.698965 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5063 10:12:15.699106 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5064 10:12:15.699279 # ok 3337 Set Streaming SVE VL 5136
5065 10:12:15.699461 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5066 10:12:15.699646 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5067 10:12:15.699847 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5068 10:12:15.700020 # ok 3341 Set Streaming SVE VL 5152
5069 10:12:15.700183 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5070 10:12:15.700378 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5071 10:12:15.700542 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5072 10:12:15.700704 # ok 3345 Set Streaming SVE VL 5168
5073 10:12:15.700870 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5074 10:12:15.701061 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5075 10:12:15.701224 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5076 10:12:15.701390 # ok 3349 Set Streaming SVE VL 5184
5077 10:12:15.704128 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5078 10:12:15.704424 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5079 10:12:15.704521 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5080 10:12:15.704622 # ok 3353 Set Streaming SVE VL 5200
5081 10:12:15.709704 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5082 10:12:15.709985 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5083 10:12:15.710077 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5084 10:12:15.710330 # ok 3357 Set Streaming SVE VL 5216
5085 10:12:15.710412 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5086 10:12:15.710666 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5087 10:12:15.710922 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5088 10:12:15.710991 # ok 3361 Set Streaming SVE VL 5232
5089 10:12:15.711244 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5090 10:12:15.711547 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5091 10:12:15.711760 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5092 10:12:15.711908 # ok 3365 Set Streaming SVE VL 5248
5093 10:12:15.712073 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5094 10:12:15.712230 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5095 10:12:15.712388 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5096 10:12:15.712516 # ok 3369 Set Streaming SVE VL 5264
5097 10:12:15.712676 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5098 10:12:15.716668 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5099 10:12:15.717984 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5100 10:12:15.718153 # ok 3373 Set Streaming SVE VL 5280
5101 10:12:15.718327 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5102 10:12:15.718681 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5103 10:12:15.718823 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5104 10:12:15.718978 # ok 3377 Set Streaming SVE VL 5296
5105 10:12:15.719112 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5106 10:12:15.719263 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5107 10:12:15.719480 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5108 10:12:15.719668 # ok 3381 Set Streaming SVE VL 5312
5109 10:12:15.719812 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5110 10:12:15.719950 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5111 10:12:15.720314 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5112 10:12:15.720470 # ok 3385 Set Streaming SVE VL 5328
5113 10:12:15.720656 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5114 10:12:15.720817 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5115 10:12:15.725413 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5116 10:12:15.725850 # ok 3389 Set Streaming SVE VL 5344
5117 10:12:15.726087 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5118 10:12:15.726334 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5119 10:12:15.726555 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5120 10:12:15.726738 # ok 3393 Set Streaming SVE VL 5360
5121 10:12:15.726937 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5122 10:12:15.727103 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5123 10:12:15.727267 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5124 10:12:15.727424 # ok 3397 Set Streaming SVE VL 5376
5125 10:12:15.727553 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5126 10:12:15.727669 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5127 10:12:15.727809 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5128 10:12:15.727928 # ok 3401 Set Streaming SVE VL 5392
5129 10:12:15.728041 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5130 10:12:15.728152 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5131 10:12:15.728264 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5132 10:12:15.728377 # ok 3405 Set Streaming SVE VL 5408
5133 10:12:15.728512 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5134 10:12:15.728632 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5135 10:12:15.728746 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5136 10:12:15.728881 # ok 3409 Set Streaming SVE VL 5424
5137 10:12:15.729001 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5138 10:12:15.735084 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5139 10:12:15.735394 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5140 10:12:15.735499 # ok 3413 Set Streaming SVE VL 5440
5141 10:12:15.735605 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5142 10:12:15.735709 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5143 10:12:15.735811 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5144 10:12:15.736092 # ok 3417 Set Streaming SVE VL 5456
5145 10:12:15.736194 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5146 10:12:15.736481 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5147 10:12:15.736584 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5148 10:12:15.736665 # ok 3421 Set Streaming SVE VL 5472
5149 10:12:15.736757 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5150 10:12:15.736836 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5151 10:12:15.740684 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5152 10:12:15.740841 # ok 3425 Set Streaming SVE VL 5488
5153 10:12:15.742099 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5154 10:12:15.742535 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5155 10:12:15.742715 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5156 10:12:15.742878 # ok 3429 Set Streaming SVE VL 5504
5157 10:12:15.743044 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5158 10:12:15.743185 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5159 10:12:15.743313 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5160 10:12:15.743489 # ok 3433 Set Streaming SVE VL 5520
5161 10:12:15.743645 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5162 10:12:15.743771 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5163 10:12:15.743890 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5164 10:12:15.744081 # ok 3437 Set Streaming SVE VL 5536
5165 10:12:15.744222 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5166 10:12:15.744349 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5167 10:12:15.744497 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5168 10:12:15.744628 # ok 3441 Set Streaming SVE VL 5552
5169 10:12:15.744771 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5170 10:12:15.744893 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5171 10:12:15.753779 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5172 10:12:15.753946 # ok 3445 Set Streaming SVE VL 5568
5173 10:12:15.754220 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5174 10:12:15.754308 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5175 10:12:15.754408 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5176 10:12:15.754493 # ok 3449 Set Streaming SVE VL 5584
5177 10:12:15.754587 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5178 10:12:15.754824 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5179 10:12:15.754915 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5180 10:12:15.755001 # ok 3453 Set Streaming SVE VL 5600
5181 10:12:15.755250 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5182 10:12:15.755322 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5183 10:12:15.755433 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5184 10:12:15.755524 # ok 3457 Set Streaming SVE VL 5616
5185 10:12:15.755824 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5186 10:12:15.755925 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5187 10:12:15.756032 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5188 10:12:15.756133 # ok 3461 Set Streaming SVE VL 5632
5189 10:12:15.756220 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5190 10:12:15.756318 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5191 10:12:15.756428 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5192 10:12:15.756724 # ok 3465 Set Streaming SVE VL 5648
5193 10:12:15.765745 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5194 10:12:15.766044 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5195 10:12:15.766156 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5196 10:12:15.766245 # ok 3469 Set Streaming SVE VL 5664
5197 10:12:15.766345 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5198 10:12:15.766634 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5199 10:12:15.766932 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5200 10:12:15.767060 # ok 3473 Set Streaming SVE VL 5680
5201 10:12:15.767207 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5202 10:12:15.767358 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5203 10:12:15.768329 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5204 10:12:15.768471 # ok 3477 Set Streaming SVE VL 5696
5205 10:12:15.768624 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5206 10:12:15.768753 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5207 10:12:15.777688 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5208 10:12:15.777890 # ok 3481 Set Streaming SVE VL 5712
5209 10:12:15.778294 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5210 10:12:15.778475 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5211 10:12:15.778643 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5212 10:12:15.778841 # ok 3485 Set Streaming SVE VL 5728
5213 10:12:15.779013 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5214 10:12:15.779180 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5215 10:12:15.779346 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5216 10:12:15.779551 # ok 3489 Set Streaming SVE VL 5744
5217 10:12:15.779720 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5218 10:12:15.779883 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5219 10:12:15.780077 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5220 10:12:15.780242 # ok 3493 Set Streaming SVE VL 5760
5221 10:12:15.780404 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5222 10:12:15.780564 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5223 10:12:15.780718 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5224 10:12:15.780901 # ok 3497 Set Streaming SVE VL 5776
5225 10:12:15.781062 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5226 10:12:15.781224 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5227 10:12:15.781382 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5228 10:12:15.789732 # ok 3501 Set Streaming SVE VL 5792
5229 10:12:15.790161 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5230 10:12:15.790313 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5231 10:12:15.790442 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5232 10:12:15.790590 # ok 3505 Set Streaming SVE VL 5808
5233 10:12:15.790718 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5234 10:12:15.790845 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5235 10:12:15.791091 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5236 10:12:15.791277 # ok 3509 Set Streaming SVE VL 5824
5237 10:12:15.791448 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5238 10:12:15.791593 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5239 10:12:15.791732 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5240 10:12:15.791909 # ok 3513 Set Streaming SVE VL 5840
5241 10:12:15.792082 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5242 10:12:15.792261 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5243 10:12:15.792388 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5244 10:12:15.792559 # ok 3517 Set Streaming SVE VL 5856
5245 10:12:15.792701 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5246 10:12:15.792878 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5247 10:12:15.793014 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5248 10:12:15.793155 # ok 3521 Set Streaming SVE VL 5872
5249 10:12:15.793295 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5250 10:12:15.793435 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5251 10:12:15.793574 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5252 10:12:15.801724 # ok 3525 Set Streaming SVE VL 5888
5253 10:12:15.802147 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5254 10:12:15.802332 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5255 10:12:15.802484 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5256 10:12:15.802647 # ok 3529 Set Streaming SVE VL 5904
5257 10:12:15.802786 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5258 10:12:15.802928 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5259 10:12:15.803073 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5260 10:12:15.803255 # ok 3533 Set Streaming SVE VL 5920
5261 10:12:15.803442 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5262 10:12:15.803610 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5263 10:12:15.803743 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5264 10:12:15.803897 # ok 3537 Set Streaming SVE VL 5936
5265 10:12:15.804025 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5266 10:12:15.804151 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5267 10:12:15.804272 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5268 10:12:15.804392 # ok 3541 Set Streaming SVE VL 5952
5269 10:12:15.804540 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5270 10:12:15.804669 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5271 10:12:15.804789 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5272 10:12:15.804904 # ok 3545 Set Streaming SVE VL 5968
5273 10:12:15.805038 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5274 10:12:15.811070 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5275 10:12:15.811781 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5276 10:12:15.812020 # ok 3549 Set Streaming SVE VL 5984
5277 10:12:15.812183 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5278 10:12:15.812567 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5279 10:12:15.812782 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5280 10:12:15.813004 # ok 3553 Set Streaming SVE VL 6000
5281 10:12:15.813176 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5282 10:12:15.813333 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5283 10:12:15.813484 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5284 10:12:15.813825 # ok 3557 Set Streaming SVE VL 6016
5285 10:12:15.813969 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5286 10:12:15.814131 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5287 10:12:15.814312 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5288 10:12:15.814472 # ok 3561 Set Streaming SVE VL 6032
5289 10:12:15.814646 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5290 10:12:15.814807 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5291 10:12:15.814978 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5292 10:12:15.815157 # ok 3565 Set Streaming SVE VL 6048
5293 10:12:15.815351 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5294 10:12:15.815510 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5295 10:12:15.815632 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5296 10:12:15.815787 # ok 3569 Set Streaming SVE VL 6064
5297 10:12:15.815926 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5298 10:12:15.816083 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5299 10:12:15.816263 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5300 10:12:15.816409 # ok 3573 Set Streaming SVE VL 6080
5301 10:12:15.816530 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5302 10:12:15.816645 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5303 10:12:15.816775 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5304 10:12:15.816914 # ok 3577 Set Streaming SVE VL 6096
5305 10:12:15.817033 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5306 10:12:15.817147 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5307 10:12:15.821463 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5308 10:12:15.822094 # ok 3581 Set Streaming SVE VL 6112
5309 10:12:15.822216 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5310 10:12:15.822319 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5311 10:12:15.822646 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5312 10:12:15.822749 # ok 3585 Set Streaming SVE VL 6128
5313 10:12:15.822835 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5314 10:12:15.822941 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5315 10:12:15.823402 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5316 10:12:15.823741 # ok 3589 Set Streaming SVE VL 6144
5317 10:12:15.823925 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5318 10:12:15.824313 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5319 10:12:15.824414 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5320 10:12:15.824494 # ok 3593 Set Streaming SVE VL 6160
5321 10:12:15.824571 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5322 10:12:15.824655 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5323 10:12:15.824746 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5324 10:12:15.824824 # ok 3597 Set Streaming SVE VL 6176
5325 10:12:15.824899 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5326 10:12:15.829499 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5327 10:12:15.830303 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5328 10:12:15.830480 # ok 3601 Set Streaming SVE VL 6192
5329 10:12:15.830670 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5330 10:12:15.830830 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5331 10:12:15.830996 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5332 10:12:15.831128 # ok 3605 Set Streaming SVE VL 6208
5333 10:12:15.831249 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5334 10:12:15.831431 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5335 10:12:15.831584 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5336 10:12:15.831759 # ok 3609 Set Streaming SVE VL 6224
5337 10:12:15.831884 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5338 10:12:15.832033 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5339 10:12:15.832155 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5340 10:12:15.832291 # ok 3613 Set Streaming SVE VL 6240
5341 10:12:15.832441 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5342 10:12:15.832585 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5343 10:12:15.832712 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5344 10:12:15.832844 # ok 3617 Set Streaming SVE VL 6256
5345 10:12:15.837386 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5346 10:12:15.837973 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5347 10:12:15.838234 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5348 10:12:15.838305 # ok 3621 Set Streaming SVE VL 6272
5349 10:12:15.838380 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5350 10:12:15.838681 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5351 10:12:15.838839 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5352 10:12:15.839017 # ok 3625 Set Streaming SVE VL 6288
5353 10:12:15.854972 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5354 10:12:15.855412 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5355 10:12:15.855578 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5356 10:12:15.855769 # ok 3629 Set Streaming SVE VL 6304
5357 10:12:15.855989 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5358 10:12:15.856177 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5359 10:12:15.856355 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5360 10:12:15.856516 # ok 3633 Set Streaming SVE VL 6320
5361 10:12:15.856709 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5362 10:12:15.856860 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5363 10:12:15.856985 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5364 10:12:15.857102 # ok 3637 Set Streaming SVE VL 6336
5365 10:12:15.857218 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5366 10:12:15.857356 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5367 10:12:15.857477 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5368 10:12:15.861572 # ok 3641 Set Streaming SVE VL 6352
5369 10:12:15.861776 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5370 10:12:15.861976 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5371 10:12:15.862161 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5372 10:12:15.862326 # ok 3645 Set Streaming SVE VL 6368
5373 10:12:15.862495 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5374 10:12:15.862706 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5375 10:12:15.862880 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5376 10:12:15.863040 # ok 3649 Set Streaming SVE VL 6384
5377 10:12:15.863172 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5378 10:12:15.863289 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5379 10:12:15.863479 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5380 10:12:15.863621 # ok 3653 Set Streaming SVE VL 6400
5381 10:12:15.863741 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5382 10:12:15.863856 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5383 10:12:15.863971 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5384 10:12:15.864085 # ok 3657 Set Streaming SVE VL 6416
5385 10:12:15.864227 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5386 10:12:15.864350 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5387 10:12:15.864468 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5388 10:12:15.864583 # ok 3661 Set Streaming SVE VL 6432
5389 10:12:15.864697 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5390 10:12:15.864834 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5391 10:12:15.864955 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5392 10:12:15.865073 # ok 3665 Set Streaming SVE VL 6448
5393 10:12:15.865189 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5394 10:12:15.867014 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5395 10:12:15.867192 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5396 10:12:15.867349 # ok 3669 Set Streaming SVE VL 6464
5397 10:12:15.867500 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5398 10:12:15.867840 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5399 10:12:15.867987 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5400 10:12:15.868108 # ok 3673 Set Streaming SVE VL 6480
5401 10:12:15.868248 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5402 10:12:15.868369 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5403 10:12:15.868508 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5404 10:12:15.868628 # ok 3677 Set Streaming SVE VL 6496
5405 10:12:15.868767 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5406 10:12:15.877291 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5407 10:12:15.877637 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5408 10:12:15.877774 # ok 3681 Set Streaming SVE VL 6512
5409 10:12:15.877916 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5410 10:12:15.878101 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5411 10:12:15.878241 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5412 10:12:15.878391 # ok 3685 Set Streaming SVE VL 6528
5413 10:12:15.878548 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5414 10:12:15.878702 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5415 10:12:15.878863 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5416 10:12:15.878990 # ok 3689 Set Streaming SVE VL 6544
5417 10:12:15.879127 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5418 10:12:15.879247 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5419 10:12:15.879448 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5420 10:12:15.879606 # ok 3693 Set Streaming SVE VL 6560
5421 10:12:15.879783 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5422 10:12:15.879951 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5423 10:12:15.880107 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5424 10:12:15.880300 # ok 3697 Set Streaming SVE VL 6576
5425 10:12:15.880443 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5426 10:12:15.880617 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5427 10:12:15.880762 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5428 10:12:15.880908 # ok 3701 Set Streaming SVE VL 6592
5429 10:12:15.883969 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5430 10:12:15.884307 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5431 10:12:15.884408 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5432 10:12:15.884503 # ok 3705 Set Streaming SVE VL 6608
5433 10:12:15.884790 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5434 10:12:15.884888 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5435 10:12:15.893517 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5436 10:12:15.893630 # ok 3709 Set Streaming SVE VL 6624
5437 10:12:15.893912 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5438 10:12:15.893996 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5439 10:12:15.894087 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5440 10:12:15.894181 # ok 3713 Set Streaming SVE VL 6640
5441 10:12:15.894471 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5442 10:12:15.894582 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5443 10:12:15.894858 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5444 10:12:15.894941 # ok 3717 Set Streaming SVE VL 6656
5445 10:12:15.895031 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5446 10:12:15.895123 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5447 10:12:15.895445 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5448 10:12:15.895677 # ok 3721 Set Streaming SVE VL 6672
5449 10:12:15.895850 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5450 10:12:15.895996 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5451 10:12:15.896170 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5452 10:12:15.896309 # ok 3725 Set Streaming SVE VL 6688
5453 10:12:15.896449 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5454 10:12:15.896621 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5455 10:12:15.896789 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5456 10:12:15.896961 # ok 3729 Set Streaming SVE VL 6704
5457 10:12:15.897135 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5458 10:12:15.905903 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5459 10:12:15.906279 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5460 10:12:15.906473 # ok 3733 Set Streaming SVE VL 6720
5461 10:12:15.906660 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5462 10:12:15.906891 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5463 10:12:15.907069 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5464 10:12:15.907227 # ok 3737 Set Streaming SVE VL 6736
5465 10:12:15.907386 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5466 10:12:15.907539 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5467 10:12:15.907729 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5468 10:12:15.907917 # ok 3741 Set Streaming SVE VL 6752
5469 10:12:15.908114 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5470 10:12:15.908283 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5471 10:12:15.908471 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5472 10:12:15.908680 # ok 3745 Set Streaming SVE VL 6768
5473 10:12:15.908855 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5474 10:12:15.908978 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5475 10:12:15.909094 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5476 10:12:15.909206 # ok 3749 Set Streaming SVE VL 6784
5477 10:12:15.909354 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5478 10:12:15.909488 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5479 10:12:15.909601 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5480 10:12:15.909789 # ok 3753 Set Streaming SVE VL 6800
5481 10:12:15.909981 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5482 10:12:15.916724 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5483 10:12:15.916931 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5484 10:12:15.917100 # ok 3757 Set Streaming SVE VL 6816
5485 10:12:15.917264 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5486 10:12:15.922151 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5487 10:12:15.922323 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5488 10:12:15.922538 # ok 3761 Set Streaming SVE VL 6832
5489 10:12:15.922718 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5490 10:12:15.922908 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5491 10:12:15.923095 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5492 10:12:15.923232 # ok 3765 Set Streaming SVE VL 6848
5493 10:12:15.923359 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5494 10:12:15.923581 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5495 10:12:15.923744 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5496 10:12:15.923907 # ok 3769 Set Streaming SVE VL 6864
5497 10:12:15.924042 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5498 10:12:15.924197 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5499 10:12:15.924312 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5500 10:12:15.924401 # ok 3773 Set Streaming SVE VL 6880
5501 10:12:15.924489 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5502 10:12:15.924782 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5503 10:12:15.929191 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5504 10:12:15.929463 # ok 3777 Set Streaming SVE VL 6896
5505 10:12:15.929541 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5506 10:12:15.929633 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5507 10:12:15.929725 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5508 10:12:15.929812 # ok 3781 Set Streaming SVE VL 6912
5509 10:12:15.930074 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5510 10:12:15.930158 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5511 10:12:15.930419 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5512 10:12:15.930489 # ok 3785 Set Streaming SVE VL 6928
5513 10:12:15.930577 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5514 10:12:15.930677 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5515 10:12:15.930938 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5516 10:12:15.931189 # ok 3789 Set Streaming SVE VL 6944
5517 10:12:15.931258 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5518 10:12:15.931331 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5519 10:12:15.931446 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5520 10:12:15.931736 # ok 3793 Set Streaming SVE VL 6960
5521 10:12:15.931820 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5522 10:12:15.931895 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5523 10:12:15.931961 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5524 10:12:15.932033 # ok 3797 Set Streaming SVE VL 6976
5525 10:12:15.932282 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5526 10:12:15.932529 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5527 10:12:15.932607 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5528 10:12:15.932675 # ok 3801 Set Streaming SVE VL 6992
5529 10:12:15.932782 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5530 10:12:15.937151 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5531 10:12:15.937592 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5532 10:12:15.937675 # ok 3805 Set Streaming SVE VL 7008
5533 10:12:15.937954 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5534 10:12:15.938232 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5535 10:12:15.938532 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5536 10:12:15.938620 # ok 3809 Set Streaming SVE VL 7024
5537 10:12:15.938709 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5538 10:12:15.938785 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5539 10:12:15.939056 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5540 10:12:15.939157 # ok 3813 Set Streaming SVE VL 7040
5541 10:12:15.939443 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5542 10:12:15.939553 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5543 10:12:15.939658 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5544 10:12:15.939782 # ok 3817 Set Streaming SVE VL 7056
5545 10:12:15.940055 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5546 10:12:15.940144 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5547 10:12:15.940222 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5548 10:12:15.940472 # ok 3821 Set Streaming SVE VL 7072
5549 10:12:15.940551 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5550 10:12:15.940803 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5551 10:12:15.940891 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5552 10:12:15.945196 # ok 3825 Set Streaming SVE VL 7088
5553 10:12:15.945354 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5554 10:12:15.945506 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5555 10:12:15.945665 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5556 10:12:15.945797 # ok 3829 Set Streaming SVE VL 7104
5557 10:12:15.945944 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5558 10:12:15.946096 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5559 10:12:15.946224 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5560 10:12:15.946347 # ok 3833 Set Streaming SVE VL 7120
5561 10:12:15.946496 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5562 10:12:15.946626 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5563 10:12:15.946777 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5564 10:12:15.946906 # ok 3837 Set Streaming SVE VL 7136
5565 10:12:15.947048 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5566 10:12:15.947176 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5567 10:12:15.947321 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5568 10:12:15.947538 # ok 3841 Set Streaming SVE VL 7152
5569 10:12:15.947733 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5570 10:12:15.947897 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5571 10:12:15.948029 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5572 10:12:15.948158 # ok 3845 Set Streaming SVE VL 7168
5573 10:12:15.948305 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5574 10:12:15.948435 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5575 10:12:15.948561 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5576 10:12:15.948693 # ok 3849 Set Streaming SVE VL 7184
5577 10:12:15.948905 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5578 10:12:15.949050 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5579 10:12:15.949168 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5580 10:12:15.953286 # ok 3853 Set Streaming SVE VL 7200
5581 10:12:15.953666 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5582 10:12:15.953832 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5583 10:12:15.953989 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5584 10:12:15.954115 # ok 3857 Set Streaming SVE VL 7216
5585 10:12:15.954257 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5586 10:12:15.954384 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5587 10:12:15.954528 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5588 10:12:15.954656 # ok 3861 Set Streaming SVE VL 7232
5589 10:12:15.954797 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5590 10:12:15.954925 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5591 10:12:15.955071 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5592 10:12:15.955199 # ok 3865 Set Streaming SVE VL 7248
5593 10:12:15.955367 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5594 10:12:15.955597 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5595 10:12:15.955770 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5596 10:12:15.955970 # ok 3869 Set Streaming SVE VL 7264
5597 10:12:15.956140 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5598 10:12:15.956270 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5599 10:12:15.956417 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5600 10:12:15.956543 # ok 3873 Set Streaming SVE VL 7280
5601 10:12:15.956697 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5602 10:12:15.956901 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5603 10:12:15.959570 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5604 10:12:15.960020 # ok 3877 Set Streaming SVE VL 7296
5605 10:12:15.960219 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5606 10:12:15.960408 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5607 10:12:15.960568 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5608 10:12:15.960723 # ok 3881 Set Streaming SVE VL 7312
5609 10:12:15.960903 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5610 10:12:15.961062 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5611 10:12:15.961225 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5612 10:12:15.961406 # ok 3885 Set Streaming SVE VL 7328
5613 10:12:15.961564 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5614 10:12:15.961732 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5615 10:12:15.961914 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5616 10:12:15.962073 # ok 3889 Set Streaming SVE VL 7344
5617 10:12:15.962229 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5618 10:12:15.962382 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5619 10:12:15.962562 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5620 10:12:15.962721 # ok 3893 Set Streaming SVE VL 7360
5621 10:12:15.962875 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5622 10:12:15.963028 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5623 10:12:15.963209 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5624 10:12:15.963378 # ok 3897 Set Streaming SVE VL 7376
5625 10:12:15.963533 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5626 10:12:15.963685 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5627 10:12:15.963839 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5628 10:12:15.963992 # ok 3901 Set Streaming SVE VL 7392
5629 10:12:15.964175 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5630 10:12:15.964333 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5631 10:12:15.964488 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5632 10:12:15.964641 # ok 3905 Set Streaming SVE VL 7408
5633 10:12:15.964793 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5634 10:12:15.964947 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5635 10:12:15.965126 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5636 10:12:15.965284 # ok 3909 Set Streaming SVE VL 7424
5637 10:12:15.965437 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5638 10:12:15.973287 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5639 10:12:15.973826 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5640 10:12:15.973994 # ok 3913 Set Streaming SVE VL 7440
5641 10:12:15.974128 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5642 10:12:15.974255 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5643 10:12:15.974431 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5644 10:12:15.974609 # ok 3917 Set Streaming SVE VL 7456
5645 10:12:15.974764 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5646 10:12:15.974917 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5647 10:12:15.975138 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5648 10:12:15.975323 # ok 3921 Set Streaming SVE VL 7472
5649 10:12:15.975518 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5650 10:12:15.975689 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5651 10:12:15.975871 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5652 10:12:15.976015 # ok 3925 Set Streaming SVE VL 7488
5653 10:12:15.976164 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5654 10:12:15.976313 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5655 10:12:15.976460 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5656 10:12:15.976610 # ok 3929 Set Streaming SVE VL 7504
5657 10:12:15.976790 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5658 10:12:15.981428 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5659 10:12:15.981943 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5660 10:12:15.982150 # ok 3933 Set Streaming SVE VL 7520
5661 10:12:15.982322 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5662 10:12:15.982540 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5663 10:12:15.982731 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5664 10:12:15.982916 # ok 3937 Set Streaming SVE VL 7536
5665 10:12:15.983101 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5666 10:12:15.983321 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5667 10:12:15.983509 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5668 10:12:15.983692 # ok 3941 Set Streaming SVE VL 7552
5669 10:12:15.983874 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5670 10:12:15.984052 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5671 10:12:15.984199 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5672 10:12:15.984377 # ok 3945 Set Streaming SVE VL 7568
5673 10:12:15.984516 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5674 10:12:15.984651 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5675 10:12:15.984788 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5676 10:12:15.984923 # ok 3949 Set Streaming SVE VL 7584
5677 10:12:15.985057 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5678 10:12:15.985217 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5679 10:12:15.985357 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5680 10:12:15.985493 # ok 3953 Set Streaming SVE VL 7600
5681 10:12:15.989300 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5682 10:12:15.989829 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5683 10:12:15.990036 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5684 10:12:15.990203 # ok 3957 Set Streaming SVE VL 7616
5685 10:12:15.990392 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5686 10:12:15.990558 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5687 10:12:15.990719 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5688 10:12:15.990877 # ok 3961 Set Streaming SVE VL 7632
5689 10:12:15.991064 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5690 10:12:15.991229 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5691 10:12:15.991393 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5692 10:12:15.991554 # ok 3965 Set Streaming SVE VL 7648
5693 10:12:15.991742 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5694 10:12:15.991905 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5695 10:12:15.992066 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5696 10:12:15.992225 # ok 3969 Set Streaming SVE VL 7664
5697 10:12:15.992414 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5698 10:12:15.992578 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5699 10:12:15.992738 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5700 10:12:15.992897 # ok 3973 Set Streaming SVE VL 7680
5701 10:12:15.993054 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5702 10:12:15.993245 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5703 10:12:15.993413 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5704 10:12:15.997188 # ok 3977 Set Streaming SVE VL 7696
5705 10:12:15.997611 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5706 10:12:15.997842 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5707 10:12:15.998038 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5708 10:12:15.998205 # ok 3981 Set Streaming SVE VL 7712
5709 10:12:15.998351 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5710 10:12:15.998525 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5711 10:12:15.998687 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5712 10:12:15.998852 # ok 3985 Set Streaming SVE VL 7728
5713 10:12:15.999028 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5714 10:12:15.999181 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5715 10:12:15.999336 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5716 10:12:15.999491 # ok 3989 Set Streaming SVE VL 7744
5717 10:12:15.999679 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5718 10:12:15.999851 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5719 10:12:16.000032 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5720 10:12:16.000218 # ok 3993 Set Streaming SVE VL 7760
5721 10:12:16.000396 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5722 10:12:16.000572 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5723 10:12:16.000779 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5724 10:12:16.000958 # ok 3997 Set Streaming SVE VL 7776
5725 10:12:16.001123 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5726 10:12:16.001320 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5727 10:12:16.005336 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5728 10:12:16.005829 # ok 4001 Set Streaming SVE VL 7792
5729 10:12:16.005999 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5730 10:12:16.006150 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5731 10:12:16.006329 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5732 10:12:16.006485 # ok 4005 Set Streaming SVE VL 7808
5733 10:12:16.006659 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5734 10:12:16.006811 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5735 10:12:16.006988 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5736 10:12:16.007140 # ok 4009 Set Streaming SVE VL 7824
5737 10:12:16.007309 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5738 10:12:16.007487 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5739 10:12:16.007642 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5740 10:12:16.007789 # ok 4013 Set Streaming SVE VL 7840
5741 10:12:16.007961 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5742 10:12:16.008110 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5743 10:12:16.008283 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5744 10:12:16.008433 # ok 4017 Set Streaming SVE VL 7856
5745 10:12:16.008604 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5746 10:12:16.008754 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5747 10:12:16.008923 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5748 10:12:16.009072 # ok 4021 Set Streaming SVE VL 7872
5749 10:12:16.013545 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5750 10:12:16.013868 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5751 10:12:16.014025 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5752 10:12:16.014209 # ok 4025 Set Streaming SVE VL 7888
5753 10:12:16.014364 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5754 10:12:16.014515 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5755 10:12:16.014666 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5756 10:12:16.014815 # ok 4029 Set Streaming SVE VL 7904
5757 10:12:16.014995 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5758 10:12:16.015148 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5759 10:12:16.015298 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5760 10:12:16.015456 # ok 4033 Set Streaming SVE VL 7920
5761 10:12:16.015605 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5762 10:12:16.015785 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5763 10:12:16.015940 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5764 10:12:16.016089 # ok 4037 Set Streaming SVE VL 7936
5765 10:12:16.016242 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5766 10:12:16.016391 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5767 10:12:16.016570 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5768 10:12:16.016725 # ok 4041 Set Streaming SVE VL 7952
5769 10:12:16.016875 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5770 10:12:16.017024 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5771 10:12:16.017173 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5772 10:12:16.017353 # ok 4045 Set Streaming SVE VL 7968
5773 10:12:16.017510 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5774 10:12:16.020900 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5775 10:12:16.021546 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5776 10:12:16.021668 # ok 4049 Set Streaming SVE VL 7984
5777 10:12:16.021765 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5778 10:12:16.021844 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5779 10:12:16.021942 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5780 10:12:16.022034 # ok 4053 Set Streaming SVE VL 8000
5781 10:12:16.022124 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5782 10:12:16.022610 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5783 10:12:16.022707 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5784 10:12:16.022786 # ok 4057 Set Streaming SVE VL 8016
5785 10:12:16.022877 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5786 10:12:16.022954 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5787 10:12:16.023043 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5788 10:12:16.023132 # ok 4061 Set Streaming SVE VL 8032
5789 10:12:16.023221 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5790 10:12:16.023497 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5791 10:12:16.023592 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5792 10:12:16.023684 # ok 4065 Set Streaming SVE VL 8048
5793 10:12:16.023969 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5794 10:12:16.024077 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5795 10:12:16.024351 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5796 10:12:16.024433 # ok 4069 Set Streaming SVE VL 8064
5797 10:12:16.024522 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5798 10:12:16.024611 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5799 10:12:16.024940 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5800 10:12:16.026875 # ok 4073 Set Streaming SVE VL 8080
5801 10:12:16.027261 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5802 10:12:16.027995 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5803 10:12:16.028183 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5804 10:12:16.028321 # ok 4077 Set Streaming SVE VL 8096
5805 10:12:16.028469 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5806 10:12:16.028596 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5807 10:12:16.028739 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5808 10:12:16.028889 # ok 4081 Set Streaming SVE VL 8112
5809 10:12:16.031776 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5810 10:12:16.032203 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5811 10:12:16.032339 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5812 10:12:16.032461 # ok 4085 Set Streaming SVE VL 8128
5813 10:12:16.032572 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5814 10:12:16.032670 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5815 10:12:16.032784 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5816 10:12:16.032877 # ok 4089 Set Streaming SVE VL 8144
5817 10:12:16.033580 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5818 10:12:16.033836 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5819 10:12:16.034091 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5820 10:12:16.034174 # ok 4093 Set Streaming SVE VL 8160
5821 10:12:16.034426 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5822 10:12:16.034853 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5823 10:12:16.035101 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5824 10:12:16.035167 # ok 4097 Set Streaming SVE VL 8176
5825 10:12:16.035449 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5826 10:12:16.035629 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5827 10:12:16.035982 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5828 10:12:16.036096 # ok 4101 Set Streaming SVE VL 8192
5829 10:12:16.036193 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5830 10:12:16.036470 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5831 10:12:16.036735 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5832 10:12:16.041354 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5833 10:12:16.041691 ok 30 selftests: arm64: sve-ptrace
5834 10:12:16.041764 # selftests: arm64: sve-probe-vls
5835 10:12:16.041828 # TAP version 13
5836 10:12:16.041889 # 1..2
5837 10:12:16.041950 # ok 1 Enumerated 16 vector lengths
5838 10:12:16.042024 # ok 2 All vector lengths valid
5839 10:12:16.042087 # # 16
5840 10:12:16.042148 # # 32
5841 10:12:16.042210 # # 48
5842 10:12:16.042274 # # 64
5843 10:12:16.042335 # # 80
5844 10:12:16.042396 # # 96
5845 10:12:16.042455 # # 112
5846 10:12:16.042530 # # 128
5847 10:12:16.042595 # # 144
5848 10:12:16.042661 # # 160
5849 10:12:16.042718 # # 176
5850 10:12:16.042777 # # 192
5851 10:12:16.042835 # # 208
5852 10:12:16.042893 # # 224
5853 10:12:16.042953 # # 240
5854 10:12:16.043010 # # 256
5855 10:12:16.043070 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5856 10:12:16.043144 ok 31 selftests: arm64: sve-probe-vls
5857 10:12:16.101595 # selftests: arm64: vec-syscfg
5858 10:12:16.827390 # TAP version 13
5859 10:12:16.827915 # 1..20
5860 10:12:16.828099 # ok 1 SVE default vector length 64
5861 10:12:16.828295 # ok 2 SVE minimum vector length 16
5862 10:12:16.828477 # ok 3 SVE maximum vector length 256
5863 10:12:16.828676 # ok 4 SVE current VL is 64
5864 10:12:16.828868 # ok 5 SVE set VL 64 and have VL 64
5865 10:12:16.829082 # ok 6 SVE prctl() set min/max
5866 10:12:16.829255 # ok 7 SVE vector length used default
5867 10:12:16.829425 # ok 8 SVE vector length was inherited
5868 10:12:16.829556 # ok 9 SVE vector length set on exec
5869 10:12:16.829703 # ok 10 SVE prctl() set all VLs, 0 errors
5870 10:12:16.829906 # ok 11 SME default vector length 32
5871 10:12:16.830101 # ok 12 SME minimum vector length 16
5872 10:12:16.830294 # ok 13 SME maximum vector length 256
5873 10:12:16.830464 # ok 14 SME current VL is 32
5874 10:12:16.830647 # ok 15 SME set VL 32 and have VL 32
5875 10:12:16.830841 # ok 16 SME prctl() set min/max
5876 10:12:16.831015 # ok 17 SME vector length used default
5877 10:12:16.831183 # ok 18 SME vector length was inherited
5878 10:12:16.831349 # ok 19 SME vector length set on exec
5879 10:12:16.831520 # ok 20 SME prctl() set all VLs, 0 errors
5880 10:12:16.831688 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5881 10:12:16.839355 ok 32 selftests: arm64: vec-syscfg
5882 10:12:16.918013 # selftests: arm64: za-fork
5883 10:12:17.104278 # TAP version 13
5884 10:12:17.104779 # 1..1
5885 10:12:17.104937 # # PID: 1014
5886 10:12:17.105087 # ok 1 fork_test
5887 10:12:17.105238 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5888 10:12:17.128398 ok 33 selftests: arm64: za-fork
5889 10:12:17.307472 # selftests: arm64: za-ptrace
5890 10:12:17.481011 # TAP version 13
5891 10:12:17.481192 # 1..1536
5892 10:12:17.481388 # # Parent is 1032, child is 1033
5893 10:12:17.481804 # ok 1 Set VL 16
5894 10:12:17.481964 # ok 2 Disabled ZA for VL 16
5895 10:12:17.482089 # ok 3 Data match for VL 16
5896 10:12:17.482208 # ok 4 Set VL 32
5897 10:12:17.482325 # ok 5 Disabled ZA for VL 32
5898 10:12:17.482440 # ok 6 Data match for VL 32
5899 10:12:17.482556 # ok 7 Set VL 48
5900 10:12:17.482671 # ok 8 # SKIP Disabled ZA for VL 48
5901 10:12:17.484417 # ok 9 # SKIP Get and set data for VL 48
5902 10:12:17.484863 # ok 10 Set VL 64
5903 10:12:17.485070 # ok 11 Disabled ZA for VL 64
5904 10:12:17.485263 # ok 12 Data match for VL 64
5905 10:12:17.485450 # ok 13 Set VL 80
5906 10:12:17.485632 # ok 14 # SKIP Disabled ZA for VL 80
5907 10:12:17.485851 # ok 15 # SKIP Get and set data for VL 80
5908 10:12:17.486000 # ok 16 Set VL 96
5909 10:12:17.486202 # ok 17 # SKIP Disabled ZA for VL 96
5910 10:12:17.486389 # ok 18 # SKIP Get and set data for VL 96
5911 10:12:17.486560 # ok 19 Set VL 112
5912 10:12:17.486723 # ok 20 # SKIP Disabled ZA for VL 112
5913 10:12:17.486879 # ok 21 # SKIP Get and set data for VL 112
5914 10:12:17.487053 # ok 22 Set VL 128
5915 10:12:17.487255 # ok 23 Disabled ZA for VL 128
5916 10:12:17.487441 # ok 24 Data match for VL 128
5917 10:12:17.487659 # ok 25 Set VL 144
5918 10:12:17.487866 # ok 26 # SKIP Disabled ZA for VL 144
5919 10:12:17.488105 # ok 27 # SKIP Get and set data for VL 144
5920 10:12:17.488302 # ok 28 Set VL 160
5921 10:12:17.488507 # ok 29 # SKIP Disabled ZA for VL 160
5922 10:12:17.488701 # ok 30 # SKIP Get and set data for VL 160
5923 10:12:17.488896 # ok 31 Set VL 176
5924 10:12:17.489062 # ok 32 # SKIP Disabled ZA for VL 176
5925 10:12:17.489194 # ok 33 # SKIP Get and set data for VL 176
5926 10:12:17.489361 # ok 34 Set VL 192
5927 10:12:17.489508 # ok 35 # SKIP Disabled ZA for VL 192
5928 10:12:17.489623 # ok 36 # SKIP Get and set data for VL 192
5929 10:12:17.489836 # ok 37 Set VL 208
5930 10:12:17.490023 # ok 38 # SKIP Disabled ZA for VL 208
5931 10:12:17.490186 # ok 39 # SKIP Get and set data for VL 208
5932 10:12:17.490327 # ok 40 Set VL 224
5933 10:12:17.490471 # ok 41 # SKIP Disabled ZA for VL 224
5934 10:12:17.490610 # ok 42 # SKIP Get and set data for VL 224
5935 10:12:17.490748 # ok 43 Set VL 240
5936 10:12:17.490885 # ok 44 # SKIP Disabled ZA for VL 240
5937 10:12:17.491025 # ok 45 # SKIP Get and set data for VL 240
5938 10:12:17.491163 # ok 46 Set VL 256
5939 10:12:17.491303 # ok 47 Disabled ZA for VL 256
5940 10:12:17.491442 # ok 48 Data match for VL 256
5941 10:12:17.491581 # ok 49 Set VL 272
5942 10:12:17.491719 # ok 50 # SKIP Disabled ZA for VL 272
5943 10:12:17.491859 # ok 51 # SKIP Get and set data for VL 272
5944 10:12:17.491998 # ok 52 Set VL 288
5945 10:12:17.492136 # ok 53 # SKIP Disabled ZA for VL 288
5946 10:12:17.492275 # ok 54 # SKIP Get and set data for VL 288
5947 10:12:17.492414 # ok 55 Set VL 304
5948 10:12:17.492594 # ok 56 # SKIP Disabled ZA for VL 304
5949 10:12:17.492730 # ok 57 # SKIP Get and set data for VL 304
5950 10:12:17.492870 # ok 58 Set VL 320
5951 10:12:17.493010 # ok 59 # SKIP Disabled ZA for VL 320
5952 10:12:17.493151 # ok 60 # SKIP Get and set data for VL 320
5953 10:12:17.493289 # ok 61 Set VL 336
5954 10:12:17.493429 # ok 62 # SKIP Disabled ZA for VL 336
5955 10:12:17.493568 # ok 63 # SKIP Get and set data for VL 336
5956 10:12:17.493719 # ok 64 Set VL 352
5957 10:12:17.493861 # ok 65 # SKIP Disabled ZA for VL 352
5958 10:12:17.494000 # ok 66 # SKIP Get and set data for VL 352
5959 10:12:17.494140 # ok 67 Set VL 368
5960 10:12:17.494495 # ok 68 # SKIP Disabled ZA for VL 368
5961 10:12:17.494629 # ok 69 # SKIP Get and set data for VL 368
5962 10:12:17.494772 # ok 70 Set VL 384
5963 10:12:17.494912 # ok 71 # SKIP Disabled ZA for VL 384
5964 10:12:17.495053 # ok 72 # SKIP Get and set data for VL 384
5965 10:12:17.495192 # ok 73 Set VL 400
5966 10:12:17.496433 # ok 74 # SKIP Disabled ZA for VL 400
5967 10:12:17.496783 # ok 75 # SKIP Get and set data for VL 400
5968 10:12:17.496886 # ok 76 Set VL 416
5969 10:12:17.496966 # ok 77 # SKIP Disabled ZA for VL 416
5970 10:12:17.497045 # ok 78 # SKIP Get and set data for VL 416
5971 10:12:17.497121 # ok 79 Set VL 432
5972 10:12:17.497212 # ok 80 # SKIP Disabled ZA for VL 432
5973 10:12:17.497293 # ok 81 # SKIP Get and set data for VL 432
5974 10:12:17.497375 # ok 82 Set VL 448
5975 10:12:17.497452 # ok 83 # SKIP Disabled ZA for VL 448
5976 10:12:17.497544 # ok 84 # SKIP Get and set data for VL 448
5977 10:12:17.497624 # ok 85 Set VL 464
5978 10:12:17.497709 # ok 86 # SKIP Disabled ZA for VL 464
5979 10:12:17.497789 # ok 87 # SKIP Get and set data for VL 464
5980 10:12:17.497866 # ok 88 Set VL 480
5981 10:12:17.497958 # ok 89 # SKIP Disabled ZA for VL 480
5982 10:12:17.498038 # ok 90 # SKIP Get and set data for VL 480
5983 10:12:17.498115 # ok 91 Set VL 496
5984 10:12:17.498194 # ok 92 # SKIP Disabled ZA for VL 496
5985 10:12:17.498273 # ok 93 # SKIP Get and set data for VL 496
5986 10:12:17.498365 # ok 94 Set VL 512
5987 10:12:17.498445 # ok 95 # SKIP Disabled ZA for VL 512
5988 10:12:17.498524 # ok 96 # SKIP Get and set data for VL 512
5989 10:12:17.498601 # ok 97 Set VL 528
5990 10:12:17.498692 # ok 98 # SKIP Disabled ZA for VL 528
5991 10:12:17.498772 # ok 99 # SKIP Get and set data for VL 528
5992 10:12:17.498848 # ok 100 Set VL 544
5993 10:12:17.498925 # ok 101 # SKIP Disabled ZA for VL 544
5994 10:12:17.499016 # ok 102 # SKIP Get and set data for VL 544
5995 10:12:17.499095 # ok 103 Set VL 560
5996 10:12:17.499173 # ok 104 # SKIP Disabled ZA for VL 560
5997 10:12:17.499267 # ok 105 # SKIP Get and set data for VL 560
5998 10:12:17.499346 # ok 106 Set VL 576
5999 10:12:17.499424 # ok 107 # SKIP Disabled ZA for VL 576
6000 10:12:17.499515 # ok 108 # SKIP Get and set data for VL 576
6001 10:12:17.499596 # ok 109 Set VL 592
6002 10:12:17.499672 # ok 110 # SKIP Disabled ZA for VL 592
6003 10:12:17.499763 # ok 111 # SKIP Get and set data for VL 592
6004 10:12:17.499842 # ok 112 Set VL 608
6005 10:12:17.499919 # ok 113 # SKIP Disabled ZA for VL 608
6006 10:12:17.500009 # ok 114 # SKIP Get and set data for VL 608
6007 10:12:17.500089 # ok 115 Set VL 624
6008 10:12:17.500178 # ok 116 # SKIP Disabled ZA for VL 624
6009 10:12:17.500261 # ok 117 # SKIP Get and set data for VL 624
6010 10:12:17.500350 # ok 118 Set VL 640
6011 10:12:17.500429 # ok 119 # SKIP Disabled ZA for VL 640
6012 10:12:17.500517 # ok 120 # SKIP Get and set data for VL 640
6013 10:12:17.500595 # ok 121 Set VL 656
6014 10:12:17.500682 # ok 122 # SKIP Disabled ZA for VL 656
6015 10:12:17.500772 # ok 123 # SKIP Get and set data for VL 656
6016 10:12:17.500850 # ok 124 Set VL 672
6017 10:12:17.512847 # ok 125 # SKIP Disabled ZA for VL 672
6018 10:12:17.513308 # ok 126 # SKIP Get and set data for VL 672
6019 10:12:17.513469 # ok 127 Set VL 688
6020 10:12:17.513594 # ok 128 # SKIP Disabled ZA for VL 688
6021 10:12:17.513726 # ok 129 # SKIP Get and set data for VL 688
6022 10:12:17.513841 # ok 130 Set VL 704
6023 10:12:17.513976 # ok 131 # SKIP Disabled ZA for VL 704
6024 10:12:17.520554 # ok 132 # SKIP Get and set data for VL 704
6025 10:12:17.520910 # ok 133 Set VL 720
6026 10:12:17.521086 # ok 134 # SKIP Disabled ZA for VL 720
6027 10:12:17.521227 # ok 135 # SKIP Get and set data for VL 720
6028 10:12:17.521384 # ok 136 Set VL 736
6029 10:12:17.521575 # ok 137 # SKIP Disabled ZA for VL 736
6030 10:12:17.521736 # ok 138 # SKIP Get and set data for VL 736
6031 10:12:17.521856 # ok 139 Set VL 752
6032 10:12:17.522000 # ok 140 # SKIP Disabled ZA for VL 752
6033 10:12:17.522220 # ok 141 # SKIP Get and set data for VL 752
6034 10:12:17.522371 # ok 142 Set VL 768
6035 10:12:17.522563 # ok 143 # SKIP Disabled ZA for VL 768
6036 10:12:17.522756 # ok 144 # SKIP Get and set data for VL 768
6037 10:12:17.522947 # ok 145 Set VL 784
6038 10:12:17.523192 # ok 146 # SKIP Disabled ZA for VL 784
6039 10:12:17.523379 # ok 147 # SKIP Get and set data for VL 784
6040 10:12:17.523576 # ok 148 Set VL 800
6041 10:12:17.523752 # ok 149 # SKIP Disabled ZA for VL 800
6042 10:12:17.523894 # ok 150 # SKIP Get and set data for VL 800
6043 10:12:17.524052 # ok 151 Set VL 816
6044 10:12:17.524240 # ok 152 # SKIP Disabled ZA for VL 816
6045 10:12:17.524430 # ok 153 # SKIP Get and set data for VL 816
6046 10:12:17.524616 # ok 154 Set VL 832
6047 10:12:17.524804 # ok 155 # SKIP Disabled ZA for VL 832
6048 10:12:17.525031 # ok 156 # SKIP Get and set data for VL 832
6049 10:12:17.525232 # ok 157 Set VL 848
6050 10:12:17.525432 # ok 158 # SKIP Disabled ZA for VL 848
6051 10:12:17.525579 # ok 159 # SKIP Get and set data for VL 848
6052 10:12:17.525776 # ok 160 Set VL 864
6053 10:12:17.525970 # ok 161 # SKIP Disabled ZA for VL 864
6054 10:12:17.526152 # ok 162 # SKIP Get and set data for VL 864
6055 10:12:17.526333 # ok 163 Set VL 880
6056 10:12:17.526482 # ok 164 # SKIP Disabled ZA for VL 880
6057 10:12:17.526623 # ok 165 # SKIP Get and set data for VL 880
6058 10:12:17.526763 # ok 166 Set VL 896
6059 10:12:17.526902 # ok 167 # SKIP Disabled ZA for VL 896
6060 10:12:17.527042 # ok 168 # SKIP Get and set data for VL 896
6061 10:12:17.527181 # ok 169 Set VL 912
6062 10:12:17.527320 # ok 170 # SKIP Disabled ZA for VL 912
6063 10:12:17.527459 # ok 171 # SKIP Get and set data for VL 912
6064 10:12:17.527598 # ok 172 Set VL 928
6065 10:12:17.527737 # ok 173 # SKIP Disabled ZA for VL 928
6066 10:12:17.527875 # ok 174 # SKIP Get and set data for VL 928
6067 10:12:17.528014 # ok 175 Set VL 944
6068 10:12:17.528152 # ok 176 # SKIP Disabled ZA for VL 944
6069 10:12:17.528290 # ok 177 # SKIP Get and set data for VL 944
6070 10:12:17.528433 # ok 178 Set VL 960
6071 10:12:17.528610 # ok 179 # SKIP Disabled ZA for VL 960
6072 10:12:17.528745 # ok 180 # SKIP Get and set data for VL 960
6073 10:12:17.528892 # ok 181 Set VL 976
6074 10:12:17.529032 # ok 182 # SKIP Disabled ZA for VL 976
6075 10:12:17.529173 # ok 183 # SKIP Get and set data for VL 976
6076 10:12:17.529312 # ok 184 Set VL 992
6077 10:12:17.532614 # ok 185 # SKIP Disabled ZA for VL 992
6078 10:12:17.532917 # ok 186 # SKIP Get and set data for VL 992
6079 10:12:17.533016 # ok 187 Set VL 1008
6080 10:12:17.533095 # ok 188 # SKIP Disabled ZA for VL 1008
6081 10:12:17.533171 # ok 189 # SKIP Get and set data for VL 1008
6082 10:12:17.533269 # ok 190 Set VL 1024
6083 10:12:17.533349 # ok 191 # SKIP Disabled ZA for VL 1024
6084 10:12:17.533430 # ok 192 # SKIP Get and set data for VL 1024
6085 10:12:17.533521 # ok 193 Set VL 1040
6086 10:12:17.533601 # ok 194 # SKIP Disabled ZA for VL 1040
6087 10:12:17.533686 # ok 195 # SKIP Get and set data for VL 1040
6088 10:12:17.534039 # ok 196 Set VL 1056
6089 10:12:17.534339 # ok 197 # SKIP Disabled ZA for VL 1056
6090 10:12:17.534438 # ok 198 # SKIP Get and set data for VL 1056
6091 10:12:17.534517 # ok 199 Set VL 1072
6092 10:12:17.534609 # ok 200 # SKIP Disabled ZA for VL 1072
6093 10:12:17.534686 # ok 201 # SKIP Get and set data for VL 1072
6094 10:12:17.534765 # ok 202 Set VL 1088
6095 10:12:17.534840 # ok 203 # SKIP Disabled ZA for VL 1088
6096 10:12:17.534929 # ok 204 # SKIP Get and set data for VL 1088
6097 10:12:17.535006 # ok 205 Set VL 1104
6098 10:12:17.535082 # ok 206 # SKIP Disabled ZA for VL 1104
6099 10:12:17.535170 # ok 207 # SKIP Get and set data for VL 1104
6100 10:12:17.535247 # ok 208 Set VL 1120
6101 10:12:17.535335 # ok 209 # SKIP Disabled ZA for VL 1120
6102 10:12:17.535413 # ok 210 # SKIP Get and set data for VL 1120
6103 10:12:17.535488 # ok 211 Set VL 1136
6104 10:12:17.535576 # ok 212 # SKIP Disabled ZA for VL 1136
6105 10:12:17.535653 # ok 213 # SKIP Get and set data for VL 1136
6106 10:12:17.535729 # ok 214 Set VL 1152
6107 10:12:17.535817 # ok 215 # SKIP Disabled ZA for VL 1152
6108 10:12:17.535895 # ok 216 # SKIP Get and set data for VL 1152
6109 10:12:17.535982 # ok 217 Set VL 1168
6110 10:12:17.536059 # ok 218 # SKIP Disabled ZA for VL 1168
6111 10:12:17.536134 # ok 219 # SKIP Get and set data for VL 1168
6112 10:12:17.536222 # ok 220 Set VL 1184
6113 10:12:17.536300 # ok 221 # SKIP Disabled ZA for VL 1184
6114 10:12:17.536389 # ok 222 # SKIP Get and set data for VL 1184
6115 10:12:17.536466 # ok 223 Set VL 1200
6116 10:12:17.536541 # ok 224 # SKIP Disabled ZA for VL 1200
6117 10:12:17.536617 # ok 225 # SKIP Get and set data for VL 1200
6118 10:12:17.536706 # ok 226 Set VL 1216
6119 10:12:17.536783 # ok 227 # SKIP Disabled ZA for VL 1216
6120 10:12:17.536858 # ok 228 # SKIP Get and set data for VL 1216
6121 10:12:17.536933 # ok 229 Set VL 1232
6122 10:12:17.537021 # ok 230 # SKIP Disabled ZA for VL 1232
6123 10:12:17.537099 # ok 231 # SKIP Get and set data for VL 1232
6124 10:12:17.537194 # ok 232 Set VL 1248
6125 10:12:17.537272 # ok 233 # SKIP Disabled ZA for VL 1248
6126 10:12:17.537347 # ok 234 # SKIP Get and set data for VL 1248
6127 10:12:17.537437 # ok 235 Set VL 1264
6128 10:12:17.537514 # ok 236 # SKIP Disabled ZA for VL 1264
6129 10:12:17.537590 # ok 237 # SKIP Get and set data for VL 1264
6130 10:12:17.538134 # ok 238 Set VL 1280
6131 10:12:17.538229 # ok 239 # SKIP Disabled ZA for VL 1280
6132 10:12:17.544464 # ok 240 # SKIP Get and set data for VL 1280
6133 10:12:17.544792 # ok 241 Set VL 1296
6134 10:12:17.544991 # ok 242 # SKIP Disabled ZA for VL 1296
6135 10:12:17.545156 # ok 243 # SKIP Get and set data for VL 1296
6136 10:12:17.545307 # ok 244 Set VL 1312
6137 10:12:17.545523 # ok 245 # SKIP Disabled ZA for VL 1312
6138 10:12:17.545727 # ok 246 # SKIP Get and set data for VL 1312
6139 10:12:17.545924 # ok 247 Set VL 1328
6140 10:12:17.546083 # ok 248 # SKIP Disabled ZA for VL 1328
6141 10:12:17.546295 # ok 249 # SKIP Get and set data for VL 1328
6142 10:12:17.546469 # ok 250 Set VL 1344
6143 10:12:17.546641 # ok 251 # SKIP Disabled ZA for VL 1344
6144 10:12:17.546861 # ok 252 # SKIP Get and set data for VL 1344
6145 10:12:17.547032 # ok 253 Set VL 1360
6146 10:12:17.547225 # ok 254 # SKIP Disabled ZA for VL 1360
6147 10:12:17.547423 # ok 255 # SKIP Get and set data for VL 1360
6148 10:12:17.547600 # ok 256 Set VL 1376
6149 10:12:17.547781 # ok 257 # SKIP Disabled ZA for VL 1376
6150 10:12:17.547930 # ok 258 # SKIP Get and set data for VL 1376
6151 10:12:17.548052 # ok 259 Set VL 1392
6152 10:12:17.548215 # ok 260 # SKIP Disabled ZA for VL 1392
6153 10:12:17.548384 # ok 261 # SKIP Get and set data for VL 1392
6154 10:12:17.548515 # ok 262 Set VL 1408
6155 10:12:17.548662 # ok 263 # SKIP Disabled ZA for VL 1408
6156 10:12:17.548814 # ok 264 # SKIP Get and set data for VL 1408
6157 10:12:17.548951 # ok 265 Set VL 1424
6158 10:12:17.549076 # ok 266 # SKIP Disabled ZA for VL 1424
6159 10:12:17.549202 # ok 267 # SKIP Get and set data for VL 1424
6160 10:12:17.549377 # ok 268 Set VL 1440
6161 10:12:17.549562 # ok 269 # SKIP Disabled ZA for VL 1440
6162 10:12:17.549773 # ok 270 # SKIP Get and set data for VL 1440
6163 10:12:17.549969 # ok 271 Set VL 1456
6164 10:12:17.550150 # ok 272 # SKIP Disabled ZA for VL 1456
6165 10:12:17.550330 # ok 273 # SKIP Get and set data for VL 1456
6166 10:12:17.550511 # ok 274 Set VL 1472
6167 10:12:17.550707 # ok 275 # SKIP Disabled ZA for VL 1472
6168 10:12:17.550842 # ok 276 # SKIP Get and set data for VL 1472
6169 10:12:17.550982 # ok 277 Set VL 1488
6170 10:12:17.551121 # ok 278 # SKIP Disabled ZA for VL 1488
6171 10:12:17.551262 # ok 279 # SKIP Get and set data for VL 1488
6172 10:12:17.551401 # ok 280 Set VL 1504
6173 10:12:17.551540 # ok 281 # SKIP Disabled ZA for VL 1504
6174 10:12:17.551677 # ok 282 # SKIP Get and set data for VL 1504
6175 10:12:17.551816 # ok 283 Set VL 1520
6176 10:12:17.551955 # ok 284 # SKIP Disabled ZA for VL 1520
6177 10:12:17.552095 # ok 285 # SKIP Get and set data for VL 1520
6178 10:12:17.552235 # ok 286 Set VL 1536
6179 10:12:17.552374 # ok 287 # SKIP Disabled ZA for VL 1536
6180 10:12:17.556909 # ok 288 # SKIP Get and set data for VL 1536
6181 10:12:17.557306 # ok 289 Set VL 1552
6182 10:12:17.557407 # ok 290 # SKIP Disabled ZA for VL 1552
6183 10:12:17.557489 # ok 291 # SKIP Get and set data for VL 1552
6184 10:12:17.557568 # ok 292 Set VL 1568
6185 10:12:17.557652 # ok 293 # SKIP Disabled ZA for VL 1568
6186 10:12:17.557746 # ok 294 # SKIP Get and set data for VL 1568
6187 10:12:17.557827 # ok 295 Set VL 1584
6188 10:12:17.557904 # ok 296 # SKIP Disabled ZA for VL 1584
6189 10:12:17.562757 # ok 297 # SKIP Get and set data for VL 1584
6190 10:12:17.562863 # ok 298 Set VL 1600
6191 10:12:17.563152 # ok 299 # SKIP Disabled ZA for VL 1600
6192 10:12:17.563255 # ok 300 # SKIP Get and set data for VL 1600
6193 10:12:17.563336 # ok 301 Set VL 1616
6194 10:12:17.563416 # ok 302 # SKIP Disabled ZA for VL 1616
6195 10:12:17.563507 # ok 303 # SKIP Get and set data for VL 1616
6196 10:12:17.563586 # ok 304 Set VL 1632
6197 10:12:17.563663 # ok 305 # SKIP Disabled ZA for VL 1632
6198 10:12:17.563753 # ok 306 # SKIP Get and set data for VL 1632
6199 10:12:17.563833 # ok 307 Set VL 1648
6200 10:12:17.563910 # ok 308 # SKIP Disabled ZA for VL 1648
6201 10:12:17.563999 # ok 309 # SKIP Get and set data for VL 1648
6202 10:12:17.564078 # ok 310 Set VL 1664
6203 10:12:17.564155 # ok 311 # SKIP Disabled ZA for VL 1664
6204 10:12:17.564245 # ok 312 # SKIP Get and set data for VL 1664
6205 10:12:17.564323 # ok 313 Set VL 1680
6206 10:12:17.564413 # ok 314 # SKIP Disabled ZA for VL 1680
6207 10:12:17.564504 # ok 315 # SKIP Get and set data for VL 1680
6208 10:12:17.564596 # ok 316 Set VL 1696
6209 10:12:17.564687 # ok 317 # SKIP Disabled ZA for VL 1696
6210 10:12:17.564778 # ok 318 # SKIP Get and set data for VL 1696
6211 10:12:17.565064 # ok 319 Set VL 1712
6212 10:12:17.565162 # ok 320 # SKIP Disabled ZA for VL 1712
6213 10:12:17.565253 # ok 321 # SKIP Get and set data for VL 1712
6214 10:12:17.565331 # ok 322 Set VL 1728
6215 10:12:17.565406 # ok 323 # SKIP Disabled ZA for VL 1728
6216 10:12:17.565494 # ok 324 # SKIP Get and set data for VL 1728
6217 10:12:17.565571 # ok 325 Set VL 1744
6218 10:12:17.565666 # ok 326 # SKIP Disabled ZA for VL 1744
6219 10:12:17.592037 # ok 327 # SKIP Get and set data for VL 1744
6220 10:12:17.592137 # ok 328 Set VL 1760
6221 10:12:17.592233 # ok 329 # SKIP Disabled ZA for VL 1760
6222 10:12:17.592310 # ok 330 # SKIP Get and set data for VL 1760
6223 10:12:17.592389 # ok 331 Set VL 1776
6224 10:12:17.592478 # ok 332 # SKIP Disabled ZA for VL 1776
6225 10:12:17.592557 # ok 333 # SKIP Get and set data for VL 1776
6226 10:12:17.592647 # ok 334 Set VL 1792
6227 10:12:17.592726 # ok 335 # SKIP Disabled ZA for VL 1792
6228 10:12:17.592814 # ok 336 # SKIP Get and set data for VL 1792
6229 10:12:17.592894 # ok 337 Set VL 1808
6230 10:12:17.592984 # ok 338 # SKIP Disabled ZA for VL 1808
6231 10:12:17.593063 # ok 339 # SKIP Get and set data for VL 1808
6232 10:12:17.593154 # ok 340 Set VL 1824
6233 10:12:17.593233 # ok 341 # SKIP Disabled ZA for VL 1824
6234 10:12:17.593549 # ok 342 # SKIP Get and set data for VL 1824
6235 10:12:17.593634 # ok 343 Set VL 1840
6236 10:12:17.593728 # ok 344 # SKIP Disabled ZA for VL 1840
6237 10:12:17.602755 # ok 345 # SKIP Get and set data for VL 1840
6238 10:12:17.603159 # ok 346 Set VL 1856
6239 10:12:17.603317 # ok 347 # SKIP Disabled ZA for VL 1856
6240 10:12:17.603500 # ok 348 # SKIP Get and set data for VL 1856
6241 10:12:17.603687 # ok 349 Set VL 1872
6242 10:12:17.603912 # ok 350 # SKIP Disabled ZA for VL 1872
6243 10:12:17.604074 # ok 351 # SKIP Get and set data for VL 1872
6244 10:12:17.604202 # ok 352 Set VL 1888
6245 10:12:17.604318 # ok 353 # SKIP Disabled ZA for VL 1888
6246 10:12:17.604435 # ok 354 # SKIP Get and set data for VL 1888
6247 10:12:17.604550 # ok 355 Set VL 1904
6248 10:12:17.604664 # ok 356 # SKIP Disabled ZA for VL 1904
6249 10:12:17.604778 # ok 357 # SKIP Get and set data for VL 1904
6250 10:12:17.604917 # ok 358 Set VL 1920
6251 10:12:17.605115 # ok 359 # SKIP Disabled ZA for VL 1920
6252 10:12:17.605343 # ok 360 # SKIP Get and set data for VL 1920
6253 10:12:17.605555 # ok 361 Set VL 1936
6254 10:12:17.605733 # ok 362 # SKIP Disabled ZA for VL 1936
6255 10:12:17.605888 # ok 363 # SKIP Get and set data for VL 1936
6256 10:12:17.606012 # ok 364 Set VL 1952
6257 10:12:17.621410 # ok 365 # SKIP Disabled ZA for VL 1952
6258 10:12:17.621837 # ok 366 # SKIP Get and set data for VL 1952
6259 10:12:17.621990 # ok 367 Set VL 1968
6260 10:12:17.636333 # ok 368 # SKIP Disabled ZA for VL 1968
6261 10:12:17.636633 # ok 369 # SKIP Get and set data for VL 1968
6262 10:12:17.636732 # ok 370 Set VL 1984
6263 10:12:17.636815 # ok 371 # SKIP Disabled ZA for VL 1984
6264 10:12:17.636905 # ok 372 # SKIP Get and set data for VL 1984
6265 10:12:17.636984 # ok 373 Set VL 2000
6266 10:12:17.637062 # ok 374 # SKIP Disabled ZA for VL 2000
6267 10:12:17.637153 # ok 375 # SKIP Get and set data for VL 2000
6268 10:12:17.637232 # ok 376 Set VL 2016
6269 10:12:17.637323 # ok 377 # SKIP Disabled ZA for VL 2016
6270 10:12:17.637401 # ok 378 # SKIP Get and set data for VL 2016
6271 10:12:17.637477 # ok 379 Set VL 2032
6272 10:12:17.637553 # ok 380 # SKIP Disabled ZA for VL 2032
6273 10:12:17.637643 # ok 381 # SKIP Get and set data for VL 2032
6274 10:12:17.637731 # ok 382 Set VL 2048
6275 10:12:17.648181 # ok 383 # SKIP Disabled ZA for VL 2048
6276 10:12:17.648294 # ok 384 # SKIP Get and set data for VL 2048
6277 10:12:17.648377 # ok 385 Set VL 2064
6278 10:12:17.648468 # ok 386 # SKIP Disabled ZA for VL 2064
6279 10:12:17.648560 # ok 387 # SKIP Get and set data for VL 2064
6280 10:12:17.648640 # ok 388 Set VL 2080
6281 10:12:17.648730 # ok 389 # SKIP Disabled ZA for VL 2080
6282 10:12:17.648823 # ok 390 # SKIP Get and set data for VL 2080
6283 10:12:17.648901 # ok 391 Set VL 2096
6284 10:12:17.648992 # ok 392 # SKIP Disabled ZA for VL 2096
6285 10:12:17.649072 # ok 393 # SKIP Get and set data for VL 2096
6286 10:12:17.649149 # ok 394 Set VL 2112
6287 10:12:17.649238 # ok 395 # SKIP Disabled ZA for VL 2112
6288 10:12:17.649316 # ok 396 # SKIP Get and set data for VL 2112
6289 10:12:17.649406 # ok 397 Set VL 2128
6290 10:12:17.649486 # ok 398 # SKIP Disabled ZA for VL 2128
6291 10:12:17.649576 # ok 399 # SKIP Get and set data for VL 2128
6292 10:12:17.649663 # ok 400 Set VL 2144
6293 10:12:17.656806 # ok 401 # SKIP Disabled ZA for VL 2144
6294 10:12:17.657128 # ok 402 # SKIP Get and set data for VL 2144
6295 10:12:17.657319 # ok 403 Set VL 2160
6296 10:12:17.657525 # ok 404 # SKIP Disabled ZA for VL 2160
6297 10:12:17.657741 # ok 405 # SKIP Get and set data for VL 2160
6298 10:12:17.657883 # ok 406 Set VL 2176
6299 10:12:17.658027 # ok 407 # SKIP Disabled ZA for VL 2176
6300 10:12:17.658167 # ok 408 # SKIP Get and set data for VL 2176
6301 10:12:17.658306 # ok 409 Set VL 2192
6302 10:12:17.659058 # ok 410 # SKIP Disabled ZA for VL 2192
6303 10:12:17.659469 # ok 411 # SKIP Get and set data for VL 2192
6304 10:12:17.659658 # ok 412 Set VL 2208
6305 10:12:17.659815 # ok 413 # SKIP Disabled ZA for VL 2208
6306 10:12:17.659952 # ok 414 # SKIP Get and set data for VL 2208
6307 10:12:17.660116 # ok 415 Set VL 2224
6308 10:12:17.660305 # ok 416 # SKIP Disabled ZA for VL 2224
6309 10:12:17.660458 # ok 417 # SKIP Get and set data for VL 2224
6310 10:12:17.660666 # ok 418 Set VL 2240
6311 10:12:17.660857 # ok 419 # SKIP Disabled ZA for VL 2240
6312 10:12:17.661013 # ok 420 # SKIP Get and set data for VL 2240
6313 10:12:17.661176 # ok 421 Set VL 2256
6314 10:12:17.661338 # ok 422 # SKIP Disabled ZA for VL 2256
6315 10:12:17.661583 # ok 423 # SKIP Get and set data for VL 2256
6316 10:12:17.661786 # ok 424 Set VL 2272
6317 10:12:17.661977 # ok 425 # SKIP Disabled ZA for VL 2272
6318 10:12:17.662157 # ok 426 # SKIP Get and set data for VL 2272
6319 10:12:17.662301 # ok 427 Set VL 2288
6320 10:12:17.662443 # ok 428 # SKIP Disabled ZA for VL 2288
6321 10:12:17.662581 # ok 429 # SKIP Get and set data for VL 2288
6322 10:12:17.662719 # ok 430 Set VL 2304
6323 10:12:17.662859 # ok 431 # SKIP Disabled ZA for VL 2304
6324 10:12:17.662998 # ok 432 # SKIP Get and set data for VL 2304
6325 10:12:17.663135 # ok 433 Set VL 2320
6326 10:12:17.663273 # ok 434 # SKIP Disabled ZA for VL 2320
6327 10:12:17.663411 # ok 435 # SKIP Get and set data for VL 2320
6328 10:12:17.663549 # ok 436 Set VL 2336
6329 10:12:17.663686 # ok 437 # SKIP Disabled ZA for VL 2336
6330 10:12:17.667263 # ok 438 # SKIP Get and set data for VL 2336
6331 10:12:17.667442 # ok 439 Set VL 2352
6332 10:12:17.667640 # ok 440 # SKIP Disabled ZA for VL 2352
6333 10:12:17.667798 # ok 441 # SKIP Get and set data for VL 2352
6334 10:12:17.667942 # ok 442 Set VL 2368
6335 10:12:17.668072 # ok 443 # SKIP Disabled ZA for VL 2368
6336 10:12:17.668209 # ok 444 # SKIP Get and set data for VL 2368
6337 10:12:17.668386 # ok 445 Set VL 2384
6338 10:12:17.668540 # ok 446 # SKIP Disabled ZA for VL 2384
6339 10:12:17.668697 # ok 447 # SKIP Get and set data for VL 2384
6340 10:12:17.668837 # ok 448 Set VL 2400
6341 10:12:17.668954 # ok 449 # SKIP Disabled ZA for VL 2400
6342 10:12:17.669083 # ok 450 # SKIP Get and set data for VL 2400
6343 10:12:17.669217 # ok 451 Set VL 2416
6344 10:12:17.669381 # ok 452 # SKIP Disabled ZA for VL 2416
6345 10:12:17.669511 # ok 453 # SKIP Get and set data for VL 2416
6346 10:12:17.669631 # ok 454 Set VL 2432
6347 10:12:17.669833 # ok 455 # SKIP Disabled ZA for VL 2432
6348 10:12:17.670022 # ok 456 # SKIP Get and set data for VL 2432
6349 10:12:17.670202 # ok 457 Set VL 2448
6350 10:12:17.670361 # ok 458 # SKIP Disabled ZA for VL 2448
6351 10:12:17.670501 # ok 459 # SKIP Get and set data for VL 2448
6352 10:12:17.670640 # ok 460 Set VL 2464
6353 10:12:17.670783 # ok 461 # SKIP Disabled ZA for VL 2464
6354 10:12:17.670923 # ok 462 # SKIP Get and set data for VL 2464
6355 10:12:17.671096 # ok 463 Set VL 2480
6356 10:12:17.675222 # ok 464 # SKIP Disabled ZA for VL 2480
6357 10:12:17.675645 # ok 465 # SKIP Get and set data for VL 2480
6358 10:12:17.675834 # ok 466 Set VL 2496
6359 10:12:17.675984 # ok 467 # SKIP Disabled ZA for VL 2496
6360 10:12:17.676137 # ok 468 # SKIP Get and set data for VL 2496
6361 10:12:17.676329 # ok 469 Set VL 2512
6362 10:12:17.676491 # ok 470 # SKIP Disabled ZA for VL 2512
6363 10:12:17.676624 # ok 471 # SKIP Get and set data for VL 2512
6364 10:12:17.676759 # ok 472 Set VL 2528
6365 10:12:17.676879 # ok 473 # SKIP Disabled ZA for VL 2528
6366 10:12:17.676995 # ok 474 # SKIP Get and set data for VL 2528
6367 10:12:17.677116 # ok 475 Set VL 2544
6368 10:12:17.677255 # ok 476 # SKIP Disabled ZA for VL 2544
6369 10:12:17.677420 # ok 477 # SKIP Get and set data for VL 2544
6370 10:12:17.677605 # ok 478 Set VL 2560
6371 10:12:17.677817 # ok 479 # SKIP Disabled ZA for VL 2560
6372 10:12:17.678008 # ok 480 # SKIP Get and set data for VL 2560
6373 10:12:17.678196 # ok 481 Set VL 2576
6374 10:12:17.678337 # ok 482 # SKIP Disabled ZA for VL 2576
6375 10:12:17.678477 # ok 483 # SKIP Get and set data for VL 2576
6376 10:12:17.678615 # ok 484 Set VL 2592
6377 10:12:17.678753 # ok 485 # SKIP Disabled ZA for VL 2592
6378 10:12:17.678893 # ok 486 # SKIP Get and set data for VL 2592
6379 10:12:17.679033 # ok 487 Set VL 2608
6380 10:12:17.679172 # ok 488 # SKIP Disabled ZA for VL 2608
6381 10:12:17.679344 # ok 489 # SKIP Get and set data for VL 2608
6382 10:12:17.679479 # ok 490 Set VL 2624
6383 10:12:17.683411 # ok 491 # SKIP Disabled ZA for VL 2624
6384 10:12:17.683819 # ok 492 # SKIP Get and set data for VL 2624
6385 10:12:17.684003 # ok 493 Set VL 2640
6386 10:12:17.684200 # ok 494 # SKIP Disabled ZA for VL 2640
6387 10:12:17.684402 # ok 495 # SKIP Get and set data for VL 2640
6388 10:12:17.684671 # ok 496 Set VL 2656
6389 10:12:17.684891 # ok 497 # SKIP Disabled ZA for VL 2656
6390 10:12:17.685072 # ok 498 # SKIP Get and set data for VL 2656
6391 10:12:17.685261 # ok 499 Set VL 2672
6392 10:12:17.685461 # ok 500 # SKIP Disabled ZA for VL 2672
6393 10:12:17.685607 # ok 501 # SKIP Get and set data for VL 2672
6394 10:12:17.685800 # ok 502 Set VL 2688
6395 10:12:17.685949 # ok 503 # SKIP Disabled ZA for VL 2688
6396 10:12:17.686137 # ok 504 # SKIP Get and set data for VL 2688
6397 10:12:17.686305 # ok 505 Set VL 2704
6398 10:12:17.686497 # ok 506 # SKIP Disabled ZA for VL 2704
6399 10:12:17.686660 # ok 507 # SKIP Get and set data for VL 2704
6400 10:12:17.686817 # ok 508 Set VL 2720
6401 10:12:17.686963 # ok 509 # SKIP Disabled ZA for VL 2720
6402 10:12:17.687118 # ok 510 # SKIP Get and set data for VL 2720
6403 10:12:17.687257 # ok 511 Set VL 2736
6404 10:12:17.687393 # ok 512 # SKIP Disabled ZA for VL 2736
6405 10:12:17.687546 # ok 513 # SKIP Get and set data for VL 2736
6406 10:12:17.687699 # ok 514 Set VL 2752
6407 10:12:17.687848 # ok 515 # SKIP Disabled ZA for VL 2752
6408 10:12:17.687995 # ok 516 # SKIP Get and set data for VL 2752
6409 10:12:17.688181 # ok 517 Set VL 2768
6410 10:12:17.688359 # ok 518 # SKIP Disabled ZA for VL 2768
6411 10:12:17.688510 # ok 519 # SKIP Get and set data for VL 2768
6412 10:12:17.688653 # ok 520 Set VL 2784
6413 10:12:17.688819 # ok 521 # SKIP Disabled ZA for VL 2784
6414 10:12:17.688953 # ok 522 # SKIP Get and set data for VL 2784
6415 10:12:17.689101 # ok 523 Set VL 2800
6416 10:12:17.689259 # ok 524 # SKIP Disabled ZA for VL 2800
6417 10:12:17.689417 # ok 525 # SKIP Get and set data for VL 2800
6418 10:12:17.689551 # ok 526 Set VL 2816
6419 10:12:17.689711 # ok 527 # SKIP Disabled ZA for VL 2816
6420 10:12:17.689918 # ok 528 # SKIP Get and set data for VL 2816
6421 10:12:17.690100 # ok 529 Set VL 2832
6422 10:12:17.690281 # ok 530 # SKIP Disabled ZA for VL 2832
6423 10:12:17.690451 # ok 531 # SKIP Get and set data for VL 2832
6424 10:12:17.690593 # ok 532 Set VL 2848
6425 10:12:17.690733 # ok 533 # SKIP Disabled ZA for VL 2848
6426 10:12:17.690871 # ok 534 # SKIP Get and set data for VL 2848
6427 10:12:17.691010 # ok 535 Set VL 2864
6428 10:12:17.691148 # ok 536 # SKIP Disabled ZA for VL 2864
6429 10:12:17.691286 # ok 537 # SKIP Get and set data for VL 2864
6430 10:12:17.691424 # ok 538 Set VL 2880
6431 10:12:17.691562 # ok 539 # SKIP Disabled ZA for VL 2880
6432 10:12:17.691700 # ok 540 # SKIP Get and set data for VL 2880
6433 10:12:17.691840 # ok 541 Set VL 2896
6434 10:12:17.691979 # ok 542 # SKIP Disabled ZA for VL 2896
6435 10:12:17.692117 # ok 543 # SKIP Get and set data for VL 2896
6436 10:12:17.692256 # ok 544 Set VL 2912
6437 10:12:17.692610 # ok 545 # SKIP Disabled ZA for VL 2912
6438 10:12:17.692750 # ok 546 # SKIP Get and set data for VL 2912
6439 10:12:17.692894 # ok 547 Set VL 2928
6440 10:12:17.693035 # ok 548 # SKIP Disabled ZA for VL 2928
6441 10:12:17.693175 # ok 549 # SKIP Get and set data for VL 2928
6442 10:12:17.693314 # ok 550 Set VL 2944
6443 10:12:17.693454 # ok 551 # SKIP Disabled ZA for VL 2944
6444 10:12:17.693592 # ok 552 # SKIP Get and set data for VL 2944
6445 10:12:17.693744 # ok 553 Set VL 2960
6446 10:12:17.693883 # ok 554 # SKIP Disabled ZA for VL 2960
6447 10:12:17.696300 # ok 555 # SKIP Get and set data for VL 2960
6448 10:12:17.696711 # ok 556 Set VL 2976
6449 10:12:17.696876 # ok 557 # SKIP Disabled ZA for VL 2976
6450 10:12:17.697055 # ok 558 # SKIP Get and set data for VL 2976
6451 10:12:17.697261 # ok 559 Set VL 2992
6452 10:12:17.697493 # ok 560 # SKIP Disabled ZA for VL 2992
6453 10:12:17.697640 # ok 561 # SKIP Get and set data for VL 2992
6454 10:12:17.697838 # ok 562 Set VL 3008
6455 10:12:17.697984 # ok 563 # SKIP Disabled ZA for VL 3008
6456 10:12:17.698122 # ok 564 # SKIP Get and set data for VL 3008
6457 10:12:17.698260 # ok 565 Set VL 3024
6458 10:12:17.698398 # ok 566 # SKIP Disabled ZA for VL 3024
6459 10:12:17.698535 # ok 567 # SKIP Get and set data for VL 3024
6460 10:12:17.698673 # ok 568 Set VL 3040
6461 10:12:17.703919 # ok 569 # SKIP Disabled ZA for VL 3040
6462 10:12:17.704378 # ok 570 # SKIP Get and set data for VL 3040
6463 10:12:17.704553 # ok 571 Set VL 3056
6464 10:12:17.704704 # ok 572 # SKIP Disabled ZA for VL 3056
6465 10:12:17.704901 # ok 573 # SKIP Get and set data for VL 3056
6466 10:12:17.705164 # ok 574 Set VL 3072
6467 10:12:17.705371 # ok 575 # SKIP Disabled ZA for VL 3072
6468 10:12:17.705569 # ok 576 # SKIP Get and set data for VL 3072
6469 10:12:17.705717 # ok 577 Set VL 3088
6470 10:12:17.705835 # ok 578 # SKIP Disabled ZA for VL 3088
6471 10:12:17.705950 # ok 579 # SKIP Get and set data for VL 3088
6472 10:12:17.706064 # ok 580 Set VL 3104
6473 10:12:17.706179 # ok 581 # SKIP Disabled ZA for VL 3104
6474 10:12:17.706322 # ok 582 # SKIP Get and set data for VL 3104
6475 10:12:17.706445 # ok 583 Set VL 3120
6476 10:12:17.706560 # ok 584 # SKIP Disabled ZA for VL 3120
6477 10:12:17.706676 # ok 585 # SKIP Get and set data for VL 3120
6478 10:12:17.706791 # ok 586 Set VL 3136
6479 10:12:17.711398 # ok 587 # SKIP Disabled ZA for VL 3136
6480 10:12:17.711567 # ok 588 # SKIP Get and set data for VL 3136
6481 10:12:17.711712 # ok 589 Set VL 3152
6482 10:12:17.712630 # ok 590 # SKIP Disabled ZA for VL 3152
6483 10:12:17.713009 # ok 591 # SKIP Get and set data for VL 3152
6484 10:12:17.713168 # ok 592 Set VL 3168
6485 10:12:17.713357 # ok 593 # SKIP Disabled ZA for VL 3168
6486 10:12:17.713567 # ok 594 # SKIP Get and set data for VL 3168
6487 10:12:17.713716 # ok 595 Set VL 3184
6488 10:12:17.713836 # ok 596 # SKIP Disabled ZA for VL 3184
6489 10:12:17.713950 # ok 597 # SKIP Get and set data for VL 3184
6490 10:12:17.714063 # ok 598 Set VL 3200
6491 10:12:17.714175 # ok 599 # SKIP Disabled ZA for VL 3200
6492 10:12:17.719170 # ok 600 # SKIP Get and set data for VL 3200
6493 10:12:17.719606 # ok 601 Set VL 3216
6494 10:12:17.719793 # ok 602 # SKIP Disabled ZA for VL 3216
6495 10:12:17.719948 # ok 603 # SKIP Get and set data for VL 3216
6496 10:12:17.720110 # ok 604 Set VL 3232
6497 10:12:17.720244 # ok 605 # SKIP Disabled ZA for VL 3232
6498 10:12:17.720434 # ok 606 # SKIP Get and set data for VL 3232
6499 10:12:17.720607 # ok 607 Set VL 3248
6500 10:12:17.720755 # ok 608 # SKIP Disabled ZA for VL 3248
6501 10:12:17.720903 # ok 609 # SKIP Get and set data for VL 3248
6502 10:12:17.721040 # ok 610 Set VL 3264
6503 10:12:17.721189 # ok 611 # SKIP Disabled ZA for VL 3264
6504 10:12:17.721334 # ok 612 # SKIP Get and set data for VL 3264
6505 10:12:17.721488 # ok 613 Set VL 3280
6506 10:12:17.721638 # ok 614 # SKIP Disabled ZA for VL 3280
6507 10:12:17.721890 # ok 615 # SKIP Get and set data for VL 3280
6508 10:12:17.722077 # ok 616 Set VL 3296
6509 10:12:17.722247 # ok 617 # SKIP Disabled ZA for VL 3296
6510 10:12:17.722387 # ok 618 # SKIP Get and set data for VL 3296
6511 10:12:17.722531 # ok 619 Set VL 3312
6512 10:12:17.722687 # ok 620 # SKIP Disabled ZA for VL 3312
6513 10:12:17.722846 # ok 621 # SKIP Get and set data for VL 3312
6514 10:12:17.722998 # ok 622 Set VL 3328
6515 10:12:17.723152 # ok 623 # SKIP Disabled ZA for VL 3328
6516 10:12:17.723303 # ok 624 # SKIP Get and set data for VL 3328
6517 10:12:17.723456 # ok 625 Set VL 3344
6518 10:12:17.723578 # ok 626 # SKIP Disabled ZA for VL 3344
6519 10:12:17.723699 # ok 627 # SKIP Get and set data for VL 3344
6520 10:12:17.723818 # ok 628 Set VL 3360
6521 10:12:17.723978 # ok 629 # SKIP Disabled ZA for VL 3360
6522 10:12:17.724141 # ok 630 # SKIP Get and set data for VL 3360
6523 10:12:17.724282 # ok 631 Set VL 3376
6524 10:12:17.724426 # ok 632 # SKIP Disabled ZA for VL 3376
6525 10:12:17.724559 # ok 633 # SKIP Get and set data for VL 3376
6526 10:12:17.724682 # ok 634 Set VL 3392
6527 10:12:17.724808 # ok 635 # SKIP Disabled ZA for VL 3392
6528 10:12:17.724946 # ok 636 # SKIP Get and set data for VL 3392
6529 10:12:17.725068 # ok 637 Set VL 3408
6530 10:12:17.725187 # ok 638 # SKIP Disabled ZA for VL 3408
6531 10:12:17.725307 # ok 639 # SKIP Get and set data for VL 3408
6532 10:12:17.725428 # ok 640 Set VL 3424
6533 10:12:17.725548 # ok 641 # SKIP Disabled ZA for VL 3424
6534 10:12:17.725716 # ok 642 # SKIP Get and set data for VL 3424
6535 10:12:17.725922 # ok 643 Set VL 3440
6536 10:12:17.726102 # ok 644 # SKIP Disabled ZA for VL 3440
6537 10:12:17.726282 # ok 645 # SKIP Get and set data for VL 3440
6538 10:12:17.726461 # ok 646 Set VL 3456
6539 10:12:17.726638 # ok 647 # SKIP Disabled ZA for VL 3456
6540 10:12:17.726800 # ok 648 # SKIP Get and set data for VL 3456
6541 10:12:17.726981 # ok 649 Set VL 3472
6542 10:12:17.727118 # ok 650 # SKIP Disabled ZA for VL 3472
6543 10:12:17.727260 # ok 651 # SKIP Get and set data for VL 3472
6544 10:12:17.727401 # ok 652 Set VL 3488
6545 10:12:17.727541 # ok 653 # SKIP Disabled ZA for VL 3488
6546 10:12:17.727681 # ok 654 # SKIP Get and set data for VL 3488
6547 10:12:17.728035 # ok 655 Set VL 3504
6548 10:12:17.728175 # ok 656 # SKIP Disabled ZA for VL 3504
6549 10:12:17.728319 # ok 657 # SKIP Get and set data for VL 3504
6550 10:12:17.728461 # ok 658 Set VL 3520
6551 10:12:17.728601 # ok 659 # SKIP Disabled ZA for VL 3520
6552 10:12:17.728742 # ok 660 # SKIP Get and set data for VL 3520
6553 10:12:17.728884 # ok 661 Set VL 3536
6554 10:12:17.729024 # ok 662 # SKIP Disabled ZA for VL 3536
6555 10:12:17.729164 # ok 663 # SKIP Get and set data for VL 3536
6556 10:12:17.729306 # ok 664 Set VL 3552
6557 10:12:17.729447 # ok 665 # SKIP Disabled ZA for VL 3552
6558 10:12:17.731444 # ok 666 # SKIP Get and set data for VL 3552
6559 10:12:17.731808 # ok 667 Set VL 3568
6560 10:12:17.731909 # ok 668 # SKIP Disabled ZA for VL 3568
6561 10:12:17.731989 # ok 669 # SKIP Get and set data for VL 3568
6562 10:12:17.732065 # ok 670 Set VL 3584
6563 10:12:17.732156 # ok 671 # SKIP Disabled ZA for VL 3584
6564 10:12:17.732233 # ok 672 # SKIP Get and set data for VL 3584
6565 10:12:17.732309 # ok 673 Set VL 3600
6566 10:12:17.732384 # ok 674 # SKIP Disabled ZA for VL 3600
6567 10:12:17.732472 # ok 675 # SKIP Get and set data for VL 3600
6568 10:12:17.732550 # ok 676 Set VL 3616
6569 10:12:17.732625 # ok 677 # SKIP Disabled ZA for VL 3616
6570 10:12:17.732700 # ok 678 # SKIP Get and set data for VL 3616
6571 10:12:17.732789 # ok 679 Set VL 3632
6572 10:12:17.732866 # ok 680 # SKIP Disabled ZA for VL 3632
6573 10:12:17.732942 # ok 681 # SKIP Get and set data for VL 3632
6574 10:12:17.733030 # ok 682 Set VL 3648
6575 10:12:17.733108 # ok 683 # SKIP Disabled ZA for VL 3648
6576 10:12:17.733183 # ok 684 # SKIP Get and set data for VL 3648
6577 10:12:17.733259 # ok 685 Set VL 3664
6578 10:12:17.733348 # ok 686 # SKIP Disabled ZA for VL 3664
6579 10:12:17.733426 # ok 687 # SKIP Get and set data for VL 3664
6580 10:12:17.733507 # ok 688 Set VL 3680
6581 10:12:17.733582 # ok 689 # SKIP Disabled ZA for VL 3680
6582 10:12:17.733678 # ok 690 # SKIP Get and set data for VL 3680
6583 10:12:17.733757 # ok 691 Set VL 3696
6584 10:12:17.734179 # ok 692 # SKIP Disabled ZA for VL 3696
6585 10:12:17.734511 # ok 693 # SKIP Get and set data for VL 3696
6586 10:12:17.734687 # ok 694 Set VL 3712
6587 10:12:17.734848 # ok 695 # SKIP Disabled ZA for VL 3712
6588 10:12:17.734984 # ok 696 # SKIP Get and set data for VL 3712
6589 10:12:17.735149 # ok 697 Set VL 3728
6590 10:12:17.735285 # ok 698 # SKIP Disabled ZA for VL 3728
6591 10:12:17.735418 # ok 699 # SKIP Get and set data for VL 3728
6592 10:12:17.735571 # ok 700 Set VL 3744
6593 10:12:17.735727 # ok 701 # SKIP Disabled ZA for VL 3744
6594 10:12:17.735918 # ok 702 # SKIP Get and set data for VL 3744
6595 10:12:17.736071 # ok 703 Set VL 3760
6596 10:12:17.736227 # ok 704 # SKIP Disabled ZA for VL 3760
6597 10:12:17.736365 # ok 705 # SKIP Get and set data for VL 3760
6598 10:12:17.736523 # ok 706 Set VL 3776
6599 10:12:17.736687 # ok 707 # SKIP Disabled ZA for VL 3776
6600 10:12:17.736845 # ok 708 # SKIP Get and set data for VL 3776
6601 10:12:17.736981 # ok 709 Set VL 3792
6602 10:12:17.737114 # ok 710 # SKIP Disabled ZA for VL 3792
6603 10:12:17.737276 # ok 711 # SKIP Get and set data for VL 3792
6604 10:12:17.737435 # ok 712 Set VL 3808
6605 10:12:17.737602 # ok 713 # SKIP Disabled ZA for VL 3808
6606 10:12:17.737751 # ok 714 # SKIP Get and set data for VL 3808
6607 10:12:17.737872 # ok 715 Set VL 3824
6608 10:12:17.737984 # ok 716 # SKIP Disabled ZA for VL 3824
6609 10:12:17.738097 # ok 717 # SKIP Get and set data for VL 3824
6610 10:12:17.738210 # ok 718 Set VL 3840
6611 10:12:17.738321 # ok 719 # SKIP Disabled ZA for VL 3840
6612 10:12:17.738434 # ok 720 # SKIP Get and set data for VL 3840
6613 10:12:17.738545 # ok 721 Set VL 3856
6614 10:12:17.738657 # ok 722 # SKIP Disabled ZA for VL 3856
6615 10:12:17.738769 # ok 723 # SKIP Get and set data for VL 3856
6616 10:12:17.738882 # ok 724 Set VL 3872
6617 10:12:17.738993 # ok 725 # SKIP Disabled ZA for VL 3872
6618 10:12:17.739105 # ok 726 # SKIP Get and set data for VL 3872
6619 10:12:17.739244 # ok 727 Set VL 3888
6620 10:12:17.739365 # ok 728 # SKIP Disabled ZA for VL 3888
6621 10:12:17.739479 # ok 729 # SKIP Get and set data for VL 3888
6622 10:12:17.739592 # ok 730 Set VL 3904
6623 10:12:17.745478 # ok 731 # SKIP Disabled ZA for VL 3904
6624 10:12:17.745762 # ok 732 # SKIP Get and set data for VL 3904
6625 10:12:17.752552 # ok 733 Set VL 3920
6626 10:12:17.753059 # ok 734 # SKIP Disabled ZA for VL 3920
6627 10:12:17.753217 # ok 735 # SKIP Get and set data for VL 3920
6628 10:12:17.753344 # ok 736 Set VL 3936
6629 10:12:17.753465 # ok 737 # SKIP Disabled ZA for VL 3936
6630 10:12:17.753588 # ok 738 # SKIP Get and set data for VL 3936
6631 10:12:17.753752 # ok 739 Set VL 3952
6632 10:12:17.753949 # ok 740 # SKIP Disabled ZA for VL 3952
6633 10:12:17.754112 # ok 741 # SKIP Get and set data for VL 3952
6634 10:12:17.754275 # ok 742 Set VL 3968
6635 10:12:17.754435 # ok 743 # SKIP Disabled ZA for VL 3968
6636 10:12:17.754616 # ok 744 # SKIP Get and set data for VL 3968
6637 10:12:17.754794 # ok 745 Set VL 3984
6638 10:12:17.754951 # ok 746 # SKIP Disabled ZA for VL 3984
6639 10:12:17.755078 # ok 747 # SKIP Get and set data for VL 3984
6640 10:12:17.755260 # ok 748 Set VL 4000
6641 10:12:17.755392 # ok 749 # SKIP Disabled ZA for VL 4000
6642 10:12:17.759238 # ok 750 # SKIP Get and set data for VL 4000
6643 10:12:17.759645 # ok 751 Set VL 4016
6644 10:12:17.759839 # ok 752 # SKIP Disabled ZA for VL 4016
6645 10:12:17.760002 # ok 753 # SKIP Get and set data for VL 4016
6646 10:12:17.760157 # ok 754 Set VL 4032
6647 10:12:17.760350 # ok 755 # SKIP Disabled ZA for VL 4032
6648 10:12:17.760520 # ok 756 # SKIP Get and set data for VL 4032
6649 10:12:17.760669 # ok 757 Set VL 4048
6650 10:12:17.760802 # ok 758 # SKIP Disabled ZA for VL 4048
6651 10:12:17.760985 # ok 759 # SKIP Get and set data for VL 4048
6652 10:12:17.761148 # ok 760 Set VL 4064
6653 10:12:17.761307 # ok 761 # SKIP Disabled ZA for VL 4064
6654 10:12:17.761494 # ok 762 # SKIP Get and set data for VL 4064
6655 10:12:17.761640 # ok 763 Set VL 4080
6656 10:12:17.761772 # ok 764 # SKIP Disabled ZA for VL 4080
6657 10:12:17.761886 # ok 765 # SKIP Get and set data for VL 4080
6658 10:12:17.762001 # ok 766 Set VL 4096
6659 10:12:17.762114 # ok 767 # SKIP Disabled ZA for VL 4096
6660 10:12:17.762225 # ok 768 # SKIP Get and set data for VL 4096
6661 10:12:17.762338 # ok 769 Set VL 4112
6662 10:12:17.762450 # ok 770 # SKIP Disabled ZA for VL 4112
6663 10:12:17.762562 # ok 771 # SKIP Get and set data for VL 4112
6664 10:12:17.762700 # ok 772 Set VL 4128
6665 10:12:17.762819 # ok 773 # SKIP Disabled ZA for VL 4128
6666 10:12:17.766891 # ok 774 # SKIP Get and set data for VL 4128
6667 10:12:17.767047 # ok 775 Set VL 4144
6668 10:12:17.767206 # ok 776 # SKIP Disabled ZA for VL 4144
6669 10:12:17.767359 # ok 777 # SKIP Get and set data for VL 4144
6670 10:12:17.767509 # ok 778 Set VL 4160
6671 10:12:17.767653 # ok 779 # SKIP Disabled ZA for VL 4160
6672 10:12:17.767772 # ok 780 # SKIP Get and set data for VL 4160
6673 10:12:17.767886 # ok 781 Set VL 4176
6674 10:12:17.768000 # ok 782 # SKIP Disabled ZA for VL 4176
6675 10:12:17.768137 # ok 783 # SKIP Get and set data for VL 4176
6676 10:12:17.768256 # ok 784 Set VL 4192
6677 10:12:17.768371 # ok 785 # SKIP Disabled ZA for VL 4192
6678 10:12:17.768490 # ok 786 # SKIP Get and set data for VL 4192
6679 10:12:17.768605 # ok 787 Set VL 4208
6680 10:12:17.768743 # ok 788 # SKIP Disabled ZA for VL 4208
6681 10:12:17.768862 # ok 789 # SKIP Get and set data for VL 4208
6682 10:12:17.768976 # ok 790 Set VL 4224
6683 10:12:17.769088 # ok 791 # SKIP Disabled ZA for VL 4224
6684 10:12:17.769202 # ok 792 # SKIP Get and set data for VL 4224
6685 10:12:17.769314 # ok 793 Set VL 4240
6686 10:12:17.769452 # ok 794 # SKIP Disabled ZA for VL 4240
6687 10:12:17.769572 # ok 795 # SKIP Get and set data for VL 4240
6688 10:12:17.769698 # ok 796 Set VL 4256
6689 10:12:17.769817 # ok 797 # SKIP Disabled ZA for VL 4256
6690 10:12:17.769932 # ok 798 # SKIP Get and set data for VL 4256
6691 10:12:17.770044 # ok 799 Set VL 4272
6692 10:12:17.770157 # ok 800 # SKIP Disabled ZA for VL 4272
6693 10:12:17.770293 # ok 801 # SKIP Get and set data for VL 4272
6694 10:12:17.782921 # ok 802 Set VL 4288
6695 10:12:17.783298 # ok 803 # SKIP Disabled ZA for VL 4288
6696 10:12:17.783504 # ok 804 # SKIP Get and set data for VL 4288
6697 10:12:17.783675 # ok 805 Set VL 4304
6698 10:12:17.783889 # ok 806 # SKIP Disabled ZA for VL 4304
6699 10:12:17.784053 # ok 807 # SKIP Get and set data for VL 4304
6700 10:12:17.784198 # ok 808 Set VL 4320
6701 10:12:17.784354 # ok 809 # SKIP Disabled ZA for VL 4320
6702 10:12:17.784508 # ok 810 # SKIP Get and set data for VL 4320
6703 10:12:17.784660 # ok 811 Set VL 4336
6704 10:12:17.784809 # ok 812 # SKIP Disabled ZA for VL 4336
6705 10:12:17.784955 # ok 813 # SKIP Get and set data for VL 4336
6706 10:12:17.785075 # ok 814 Set VL 4352
6707 10:12:17.785190 # ok 815 # SKIP Disabled ZA for VL 4352
6708 10:12:17.785303 # ok 816 # SKIP Get and set data for VL 4352
6709 10:12:17.785415 # ok 817 Set VL 4368
6710 10:12:17.785527 # ok 818 # SKIP Disabled ZA for VL 4368
6711 10:12:17.785639 # ok 819 # SKIP Get and set data for VL 4368
6712 10:12:17.785770 # ok 820 Set VL 4384
6713 10:12:17.785885 # ok 821 # SKIP Disabled ZA for VL 4384
6714 10:12:17.800492 # ok 822 # SKIP Get and set data for VL 4384
6715 10:12:17.800877 # ok 823 Set VL 4400
6716 10:12:17.801078 # ok 824 # SKIP Disabled ZA for VL 4400
6717 10:12:17.801315 # ok 825 # SKIP Get and set data for VL 4400
6718 10:12:17.801484 # ok 826 Set VL 4416
6719 10:12:17.801701 # ok 827 # SKIP Disabled ZA for VL 4416
6720 10:12:17.801836 # ok 828 # SKIP Get and set data for VL 4416
6721 10:12:17.801956 # ok 829 Set VL 4432
6722 10:12:17.802069 # ok 830 # SKIP Disabled ZA for VL 4432
6723 10:12:17.802208 # ok 831 # SKIP Get and set data for VL 4432
6724 10:12:17.802331 # ok 832 Set VL 4448
6725 10:12:17.802448 # ok 833 # SKIP Disabled ZA for VL 4448
6726 10:12:17.811126 # ok 834 # SKIP Get and set data for VL 4448
6727 10:12:17.811485 # ok 835 Set VL 4464
6728 10:12:17.811662 # ok 836 # SKIP Disabled ZA for VL 4464
6729 10:12:17.811846 # ok 837 # SKIP Get and set data for VL 4464
6730 10:12:17.812040 # ok 838 Set VL 4480
6731 10:12:17.812217 # ok 839 # SKIP Disabled ZA for VL 4480
6732 10:12:17.812388 # ok 840 # SKIP Get and set data for VL 4480
6733 10:12:17.812568 # ok 841 Set VL 4496
6734 10:12:17.812750 # ok 842 # SKIP Disabled ZA for VL 4496
6735 10:12:17.812924 # ok 843 # SKIP Get and set data for VL 4496
6736 10:12:17.813080 # ok 844 Set VL 4512
6737 10:12:17.813234 # ok 845 # SKIP Disabled ZA for VL 4512
6738 10:12:17.813389 # ok 846 # SKIP Get and set data for VL 4512
6739 10:12:17.813536 # ok 847 Set VL 4528
6740 10:12:17.813721 # ok 848 # SKIP Disabled ZA for VL 4528
6741 10:12:17.813850 # ok 849 # SKIP Get and set data for VL 4528
6742 10:12:17.813965 # ok 850 Set VL 4544
6743 10:12:17.814078 # ok 851 # SKIP Disabled ZA for VL 4544
6744 10:12:17.814192 # ok 852 # SKIP Get and set data for VL 4544
6745 10:12:17.814306 # ok 853 Set VL 4560
6746 10:12:17.814418 # ok 854 # SKIP Disabled ZA for VL 4560
6747 10:12:17.814532 # ok 855 # SKIP Get and set data for VL 4560
6748 10:12:17.814645 # ok 856 Set VL 4576
6749 10:12:17.814758 # ok 857 # SKIP Disabled ZA for VL 4576
6750 10:12:17.814877 # ok 858 # SKIP Get and set data for VL 4576
6751 10:12:17.814991 # ok 859 Set VL 4592
6752 10:12:17.815105 # ok 860 # SKIP Disabled ZA for VL 4592
6753 10:12:17.815219 # ok 861 # SKIP Get and set data for VL 4592
6754 10:12:17.827156 # ok 862 Set VL 4608
6755 10:12:17.827560 # ok 863 # SKIP Disabled ZA for VL 4608
6756 10:12:17.827737 # ok 864 # SKIP Get and set data for VL 4608
6757 10:12:17.827903 # ok 865 Set VL 4624
6758 10:12:17.828087 # ok 866 # SKIP Disabled ZA for VL 4624
6759 10:12:17.828246 # ok 867 # SKIP Get and set data for VL 4624
6760 10:12:17.828402 # ok 868 Set VL 4640
6761 10:12:17.828551 # ok 869 # SKIP Disabled ZA for VL 4640
6762 10:12:17.828691 # ok 870 # SKIP Get and set data for VL 4640
6763 10:12:17.828822 # ok 871 Set VL 4656
6764 10:12:17.828996 # ok 872 # SKIP Disabled ZA for VL 4656
6765 10:12:17.829143 # ok 873 # SKIP Get and set data for VL 4656
6766 10:12:17.829260 # ok 874 Set VL 4672
6767 10:12:17.829399 # ok 875 # SKIP Disabled ZA for VL 4672
6768 10:12:17.829563 # ok 876 # SKIP Get and set data for VL 4672
6769 10:12:17.829729 # ok 877 Set VL 4688
6770 10:12:17.829848 # ok 878 # SKIP Disabled ZA for VL 4688
6771 10:12:17.829967 # ok 879 # SKIP Get and set data for VL 4688
6772 10:12:17.830098 # ok 880 Set VL 4704
6773 10:12:17.830242 # ok 881 # SKIP Disabled ZA for VL 4704
6774 10:12:17.830364 # ok 882 # SKIP Get and set data for VL 4704
6775 10:12:17.830482 # ok 883 Set VL 4720
6776 10:12:17.830597 # ok 884 # SKIP Disabled ZA for VL 4720
6777 10:12:17.830712 # ok 885 # SKIP Get and set data for VL 4720
6778 10:12:17.830827 # ok 886 Set VL 4736
6779 10:12:17.830941 # ok 887 # SKIP Disabled ZA for VL 4736
6780 10:12:17.841152 # ok 888 # SKIP Get and set data for VL 4736
6781 10:12:17.841330 # ok 889 Set VL 4752
6782 10:12:17.841700 # ok 890 # SKIP Disabled ZA for VL 4752
6783 10:12:17.841840 # ok 891 # SKIP Get and set data for VL 4752
6784 10:12:17.841962 # ok 892 Set VL 4768
6785 10:12:17.842080 # ok 893 # SKIP Disabled ZA for VL 4768
6786 10:12:17.842196 # ok 894 # SKIP Get and set data for VL 4768
6787 10:12:17.848456 # ok 895 Set VL 4784
6788 10:12:17.848635 # ok 896 # SKIP Disabled ZA for VL 4784
6789 10:12:17.848788 # ok 897 # SKIP Get and set data for VL 4784
6790 10:12:17.848911 # ok 898 Set VL 4800
6791 10:12:17.849047 # ok 899 # SKIP Disabled ZA for VL 4800
6792 10:12:17.849196 # ok 900 # SKIP Get and set data for VL 4800
6793 10:12:17.849344 # ok 901 Set VL 4816
6794 10:12:17.849472 # ok 902 # SKIP Disabled ZA for VL 4816
6795 10:12:17.849665 # ok 903 # SKIP Get and set data for VL 4816
6796 10:12:17.849809 # ok 904 Set VL 4832
6797 10:12:17.849929 # ok 905 # SKIP Disabled ZA for VL 4832
6798 10:12:17.850072 # ok 906 # SKIP Get and set data for VL 4832
6799 10:12:17.850237 # ok 907 Set VL 4848
6800 10:12:17.850364 # ok 908 # SKIP Disabled ZA for VL 4848
6801 10:12:17.857549 # ok 909 # SKIP Get and set data for VL 4848
6802 10:12:17.857841 # ok 910 Set VL 4864
6803 10:12:17.859097 # ok 911 # SKIP Disabled ZA for VL 4864
6804 10:12:17.859396 # ok 912 # SKIP Get and set data for VL 4864
6805 10:12:17.859494 # ok 913 Set VL 4880
6806 10:12:17.859572 # ok 914 # SKIP Disabled ZA for VL 4880
6807 10:12:17.859661 # ok 915 # SKIP Get and set data for VL 4880
6808 10:12:17.859740 # ok 916 Set VL 4896
6809 10:12:17.859813 # ok 917 # SKIP Disabled ZA for VL 4896
6810 10:12:17.859900 # ok 918 # SKIP Get and set data for VL 4896
6811 10:12:17.859979 # ok 919 Set VL 4912
6812 10:12:17.860054 # ok 920 # SKIP Disabled ZA for VL 4912
6813 10:12:17.860144 # ok 921 # SKIP Get and set data for VL 4912
6814 10:12:17.860221 # ok 922 Set VL 4928
6815 10:12:17.860308 # ok 923 # SKIP Disabled ZA for VL 4928
6816 10:12:17.860644 # ok 924 # SKIP Get and set data for VL 4928
6817 10:12:17.860821 # ok 925 Set VL 4944
6818 10:12:17.860995 # ok 926 # SKIP Disabled ZA for VL 4944
6819 10:12:17.861180 # ok 927 # SKIP Get and set data for VL 4944
6820 10:12:17.861354 # ok 928 Set VL 4960
6821 10:12:17.861530 # ok 929 # SKIP Disabled ZA for VL 4960
6822 10:12:17.861675 # ok 930 # SKIP Get and set data for VL 4960
6823 10:12:17.861914 # ok 931 Set VL 4976
6824 10:12:17.862060 # ok 932 # SKIP Disabled ZA for VL 4976
6825 10:12:17.862203 # ok 933 # SKIP Get and set data for VL 4976
6826 10:12:17.862342 # ok 934 Set VL 4992
6827 10:12:17.868878 # ok 935 # SKIP Disabled ZA for VL 4992
6828 10:12:17.869299 # ok 936 # SKIP Get and set data for VL 4992
6829 10:12:17.869480 # ok 937 Set VL 5008
6830 10:12:17.869643 # ok 938 # SKIP Disabled ZA for VL 5008
6831 10:12:17.869785 # ok 939 # SKIP Get and set data for VL 5008
6832 10:12:17.869936 # ok 940 Set VL 5024
6833 10:12:17.870061 # ok 941 # SKIP Disabled ZA for VL 5024
6834 10:12:17.870178 # ok 942 # SKIP Get and set data for VL 5024
6835 10:12:17.872966 # ok 943 Set VL 5040
6836 10:12:17.873331 # ok 944 # SKIP Disabled ZA for VL 5040
6837 10:12:17.873470 # ok 945 # SKIP Get and set data for VL 5040
6838 10:12:17.873635 # ok 946 Set VL 5056
6839 10:12:17.873845 # ok 947 # SKIP Disabled ZA for VL 5056
6840 10:12:17.873978 # ok 948 # SKIP Get and set data for VL 5056
6841 10:12:17.874094 # ok 949 Set VL 5072
6842 10:12:17.880070 # ok 950 # SKIP Disabled ZA for VL 5072
6843 10:12:17.880192 # ok 951 # SKIP Get and set data for VL 5072
6844 10:12:17.880300 # ok 952 Set VL 5088
6845 10:12:17.880390 # ok 953 # SKIP Disabled ZA for VL 5088
6846 10:12:17.880552 # ok 954 # SKIP Get and set data for VL 5088
6847 10:12:17.880679 # ok 955 Set VL 5104
6848 10:12:17.880828 # ok 956 # SKIP Disabled ZA for VL 5104
6849 10:12:17.881011 # ok 957 # SKIP Get and set data for VL 5104
6850 10:12:17.881133 # ok 958 Set VL 5120
6851 10:12:17.881263 # ok 959 # SKIP Disabled ZA for VL 5120
6852 10:12:17.881392 # ok 960 # SKIP Get and set data for VL 5120
6853 10:12:17.881501 # ok 961 Set VL 5136
6854 10:12:17.881637 # ok 962 # SKIP Disabled ZA for VL 5136
6855 10:12:17.881751 # ok 963 # SKIP Get and set data for VL 5136
6856 10:12:17.881857 # ok 964 Set VL 5152
6857 10:12:17.881962 # ok 965 # SKIP Disabled ZA for VL 5152
6858 10:12:17.882067 # ok 966 # SKIP Get and set data for VL 5152
6859 10:12:17.882178 # ok 967 Set VL 5168
6860 10:12:17.882283 # ok 968 # SKIP Disabled ZA for VL 5168
6861 10:12:17.888967 # ok 969 # SKIP Get and set data for VL 5168
6862 10:12:17.889302 # ok 970 Set VL 5184
6863 10:12:17.889424 # ok 971 # SKIP Disabled ZA for VL 5184
6864 10:12:17.889593 # ok 972 # SKIP Get and set data for VL 5184
6865 10:12:17.889728 # ok 973 Set VL 5200
6866 10:12:17.889838 # ok 974 # SKIP Disabled ZA for VL 5200
6867 10:12:17.889966 # ok 975 # SKIP Get and set data for VL 5200
6868 10:12:17.890936 # ok 976 Set VL 5216
6869 10:12:17.891311 # ok 977 # SKIP Disabled ZA for VL 5216
6870 10:12:17.891438 # ok 978 # SKIP Get and set data for VL 5216
6871 10:12:17.891580 # ok 979 Set VL 5232
6872 10:12:17.891697 # ok 980 # SKIP Disabled ZA for VL 5232
6873 10:12:17.891872 # ok 981 # SKIP Get and set data for VL 5232
6874 10:12:17.891999 # ok 982 Set VL 5248
6875 10:12:17.892139 # ok 983 # SKIP Disabled ZA for VL 5248
6876 10:12:17.892275 # ok 984 # SKIP Get and set data for VL 5248
6877 10:12:17.892457 # ok 985 Set VL 5264
6878 10:12:17.892632 # ok 986 # SKIP Disabled ZA for VL 5264
6879 10:12:17.892774 # ok 987 # SKIP Get and set data for VL 5264
6880 10:12:17.892954 # ok 988 Set VL 5280
6881 10:12:17.893129 # ok 989 # SKIP Disabled ZA for VL 5280
6882 10:12:17.893297 # ok 990 # SKIP Get and set data for VL 5280
6883 10:12:17.893464 # ok 991 Set VL 5296
6884 10:12:17.893633 # ok 992 # SKIP Disabled ZA for VL 5296
6885 10:12:17.893836 # ok 993 # SKIP Get and set data for VL 5296
6886 10:12:17.894019 # ok 994 Set VL 5312
6887 10:12:17.894187 # ok 995 # SKIP Disabled ZA for VL 5312
6888 10:12:17.894328 # ok 996 # SKIP Get and set data for VL 5312
6889 10:12:17.894467 # ok 997 Set VL 5328
6890 10:12:17.894643 # ok 998 # SKIP Disabled ZA for VL 5328
6891 10:12:17.894778 # ok 999 # SKIP Get and set data for VL 5328
6892 10:12:17.894917 # ok 1000 Set VL 5344
6893 10:12:17.895057 # ok 1001 # SKIP Disabled ZA for VL 5344
6894 10:12:17.895201 # ok 1002 # SKIP Get and set data for VL 5344
6895 10:12:17.895341 # ok 1003 Set VL 5360
6896 10:12:17.895479 # ok 1004 # SKIP Disabled ZA for VL 5360
6897 10:12:17.895619 # ok 1005 # SKIP Get and set data for VL 5360
6898 10:12:17.895758 # ok 1006 Set VL 5376
6899 10:12:17.899118 # ok 1007 # SKIP Disabled ZA for VL 5376
6900 10:12:17.899418 # ok 1008 # SKIP Get and set data for VL 5376
6901 10:12:17.899518 # ok 1009 Set VL 5392
6902 10:12:17.899612 # ok 1010 # SKIP Disabled ZA for VL 5392
6903 10:12:17.899693 # ok 1011 # SKIP Get and set data for VL 5392
6904 10:12:17.899784 # ok 1012 Set VL 5408
6905 10:12:17.899863 # ok 1013 # SKIP Disabled ZA for VL 5408
6906 10:12:17.899940 # ok 1014 # SKIP Get and set data for VL 5408
6907 10:12:17.900031 # ok 1015 Set VL 5424
6908 10:12:17.900110 # ok 1016 # SKIP Disabled ZA for VL 5424
6909 10:12:17.900199 # ok 1017 # SKIP Get and set data for VL 5424
6910 10:12:17.900278 # ok 1018 Set VL 5440
6911 10:12:17.900368 # ok 1019 # SKIP Disabled ZA for VL 5440
6912 10:12:17.900446 # ok 1020 # SKIP Get and set data for VL 5440
6913 10:12:17.900537 # ok 1021 Set VL 5456
6914 10:12:17.900627 # ok 1022 # SKIP Disabled ZA for VL 5456
6915 10:12:17.900720 # ok 1023 # SKIP Get and set data for VL 5456
6916 10:12:17.900810 # ok 1024 Set VL 5472
6917 10:12:17.900899 # ok 1025 # SKIP Disabled ZA for VL 5472
6918 10:12:17.900988 # ok 1026 # SKIP Get and set data for VL 5472
6919 10:12:17.901066 # ok 1027 Set VL 5488
6920 10:12:17.901154 # ok 1028 # SKIP Disabled ZA for VL 5488
6921 10:12:17.901243 # ok 1029 # SKIP Get and set data for VL 5488
6922 10:12:17.901332 # ok 1030 Set VL 5504
6923 10:12:17.901420 # ok 1031 # SKIP Disabled ZA for VL 5504
6924 10:12:17.901735 # ok 1032 # SKIP Get and set data for VL 5504
6925 10:12:17.901893 # ok 1033 Set VL 5520
6926 10:12:17.907225 # ok 1034 # SKIP Disabled ZA for VL 5520
6927 10:12:17.907622 # ok 1035 # SKIP Get and set data for VL 5520
6928 10:12:17.907811 # ok 1036 Set VL 5536
6929 10:12:17.907969 # ok 1037 # SKIP Disabled ZA for VL 5536
6930 10:12:17.908158 # ok 1038 # SKIP Get and set data for VL 5536
6931 10:12:17.908295 # ok 1039 Set VL 5552
6932 10:12:17.908426 # ok 1040 # SKIP Disabled ZA for VL 5552
6933 10:12:17.908564 # ok 1041 # SKIP Get and set data for VL 5552
6934 10:12:17.908711 # ok 1042 Set VL 5568
6935 10:12:17.908860 # ok 1043 # SKIP Disabled ZA for VL 5568
6936 10:12:17.909015 # ok 1044 # SKIP Get and set data for VL 5568
6937 10:12:17.909139 # ok 1045 Set VL 5584
6938 10:12:17.909254 # ok 1046 # SKIP Disabled ZA for VL 5584
6939 10:12:17.909372 # ok 1047 # SKIP Get and set data for VL 5584
6940 10:12:17.909486 # ok 1048 Set VL 5600
6941 10:12:17.909643 # ok 1049 # SKIP Disabled ZA for VL 5600
6942 10:12:17.909792 # ok 1050 # SKIP Get and set data for VL 5600
6943 10:12:17.909912 # ok 1051 Set VL 5616
6944 10:12:17.910051 # ok 1052 # SKIP Disabled ZA for VL 5616
6945 10:12:17.917082 # ok 1053 # SKIP Get and set data for VL 5616
6946 10:12:17.917181 # ok 1054 Set VL 5632
6947 10:12:17.917275 # ok 1055 # SKIP Disabled ZA for VL 5632
6948 10:12:17.917355 # ok 1056 # SKIP Get and set data for VL 5632
6949 10:12:17.917446 # ok 1057 Set VL 5648
6950 10:12:17.917523 # ok 1058 # SKIP Disabled ZA for VL 5648
6951 10:12:17.917611 # ok 1059 # SKIP Get and set data for VL 5648
6952 10:12:17.917707 # ok 1060 Set VL 5664
6953 10:12:17.918478 # ok 1061 # SKIP Disabled ZA for VL 5664
6954 10:12:17.918580 # ok 1062 # SKIP Get and set data for VL 5664
6955 10:12:17.918883 # ok 1063 Set VL 5680
6956 10:12:17.919085 # ok 1064 # SKIP Disabled ZA for VL 5680
6957 10:12:17.919246 # ok 1065 # SKIP Get and set data for VL 5680
6958 10:12:17.919409 # ok 1066 Set VL 5696
6959 10:12:17.919600 # ok 1067 # SKIP Disabled ZA for VL 5696
6960 10:12:17.919746 # ok 1068 # SKIP Get and set data for VL 5696
6961 10:12:17.919911 # ok 1069 Set VL 5712
6962 10:12:17.920062 # ok 1070 # SKIP Disabled ZA for VL 5712
6963 10:12:17.920208 # ok 1071 # SKIP Get and set data for VL 5712
6964 10:12:17.920366 # ok 1072 Set VL 5728
6965 10:12:17.920528 # ok 1073 # SKIP Disabled ZA for VL 5728
6966 10:12:17.920696 # ok 1074 # SKIP Get and set data for VL 5728
6967 10:12:17.920893 # ok 1075 Set VL 5744
6968 10:12:17.921066 # ok 1076 # SKIP Disabled ZA for VL 5744
6969 10:12:17.921224 # ok 1077 # SKIP Get and set data for VL 5744
6970 10:12:17.921361 # ok 1078 Set VL 5760
6971 10:12:17.921500 # ok 1079 # SKIP Disabled ZA for VL 5760
6972 10:12:17.921630 # ok 1080 # SKIP Get and set data for VL 5760
6973 10:12:17.921802 # ok 1081 Set VL 5776
6974 10:12:17.921939 # ok 1082 # SKIP Disabled ZA for VL 5776
6975 10:12:17.922060 # ok 1083 # SKIP Get and set data for VL 5776
6976 10:12:17.922178 # ok 1084 Set VL 5792
6977 10:12:17.922297 # ok 1085 # SKIP Disabled ZA for VL 5792
6978 10:12:17.922412 # ok 1086 # SKIP Get and set data for VL 5792
6979 10:12:17.922528 # ok 1087 Set VL 5808
6980 10:12:17.922674 # ok 1088 # SKIP Disabled ZA for VL 5808
6981 10:12:17.922799 # ok 1089 # SKIP Get and set data for VL 5808
6982 10:12:17.922915 # ok 1090 Set VL 5824
6983 10:12:17.923030 # ok 1091 # SKIP Disabled ZA for VL 5824
6984 10:12:17.923145 # ok 1092 # SKIP Get and set data for VL 5824
6985 10:12:17.923261 # ok 1093 Set VL 5840
6986 10:12:17.923382 # ok 1094 # SKIP Disabled ZA for VL 5840
6987 10:12:17.923497 # ok 1095 # SKIP Get and set data for VL 5840
6988 10:12:17.931324 # ok 1096 Set VL 5856
6989 10:12:17.931762 # ok 1097 # SKIP Disabled ZA for VL 5856
6990 10:12:17.931935 # ok 1098 # SKIP Get and set data for VL 5856
6991 10:12:17.932107 # ok 1099 Set VL 5872
6992 10:12:17.932264 # ok 1100 # SKIP Disabled ZA for VL 5872
6993 10:12:17.932505 # ok 1101 # SKIP Get and set data for VL 5872
6994 10:12:17.932687 # ok 1102 Set VL 5888
6995 10:12:17.932884 # ok 1103 # SKIP Disabled ZA for VL 5888
6996 10:12:17.933056 # ok 1104 # SKIP Get and set data for VL 5888
6997 10:12:17.933198 # ok 1105 Set VL 5904
6998 10:12:17.933339 # ok 1106 # SKIP Disabled ZA for VL 5904
6999 10:12:17.933482 # ok 1107 # SKIP Get and set data for VL 5904
7000 10:12:17.933722 # ok 1108 Set VL 5920
7001 10:12:17.933879 # ok 1109 # SKIP Disabled ZA for VL 5920
7002 10:12:17.934022 # ok 1110 # SKIP Get and set data for VL 5920
7003 10:12:17.934165 # ok 1111 Set VL 5936
7004 10:12:17.934305 # ok 1112 # SKIP Disabled ZA for VL 5936
7005 10:12:17.934446 # ok 1113 # SKIP Get and set data for VL 5936
7006 10:12:17.934587 # ok 1114 Set VL 5952
7007 10:12:17.934728 # ok 1115 # SKIP Disabled ZA for VL 5952
7008 10:12:17.934901 # ok 1116 # SKIP Get and set data for VL 5952
7009 10:12:17.935036 # ok 1117 Set VL 5968
7010 10:12:17.935175 # ok 1118 # SKIP Disabled ZA for VL 5968
7011 10:12:17.935532 # ok 1119 # SKIP Get and set data for VL 5968
7012 10:12:17.935698 # ok 1120 Set VL 5984
7013 10:12:17.935865 # ok 1121 # SKIP Disabled ZA for VL 5984
7014 10:12:17.936043 # ok 1122 # SKIP Get and set data for VL 5984
7015 10:12:17.936226 # ok 1123 Set VL 6000
7016 10:12:17.936407 # ok 1124 # SKIP Disabled ZA for VL 6000
7017 10:12:17.936543 # ok 1125 # SKIP Get and set data for VL 6000
7018 10:12:17.936684 # ok 1126 Set VL 6016
7019 10:12:17.936824 # ok 1127 # SKIP Disabled ZA for VL 6016
7020 10:12:17.936964 # ok 1128 # SKIP Get and set data for VL 6016
7021 10:12:17.937137 # ok 1129 Set VL 6032
7022 10:12:17.937271 # ok 1130 # SKIP Disabled ZA for VL 6032
7023 10:12:17.937411 # ok 1131 # SKIP Get and set data for VL 6032
7024 10:12:17.937551 # ok 1132 Set VL 6048
7025 10:12:17.937706 # ok 1133 # SKIP Disabled ZA for VL 6048
7026 10:12:17.937848 # ok 1134 # SKIP Get and set data for VL 6048
7027 10:12:17.937988 # ok 1135 Set VL 6064
7028 10:12:17.938161 # ok 1136 # SKIP Disabled ZA for VL 6064
7029 10:12:17.938297 # ok 1137 # SKIP Get and set data for VL 6064
7030 10:12:17.938436 # ok 1138 Set VL 6080
7031 10:12:17.938575 # ok 1139 # SKIP Disabled ZA for VL 6080
7032 10:12:17.938714 # ok 1140 # SKIP Get and set data for VL 6080
7033 10:12:17.944223 # ok 1141 Set VL 6096
7034 10:12:17.944661 # ok 1142 # SKIP Disabled ZA for VL 6096
7035 10:12:17.944844 # ok 1143 # SKIP Get and set data for VL 6096
7036 10:12:17.945037 # ok 1144 Set VL 6112
7037 10:12:17.945221 # ok 1145 # SKIP Disabled ZA for VL 6112
7038 10:12:17.945381 # ok 1146 # SKIP Get and set data for VL 6112
7039 10:12:17.945569 # ok 1147 Set VL 6128
7040 10:12:17.945783 # ok 1148 # SKIP Disabled ZA for VL 6128
7041 10:12:17.945953 # ok 1149 # SKIP Get and set data for VL 6128
7042 10:12:17.946094 # ok 1150 Set VL 6144
7043 10:12:17.946233 # ok 1151 # SKIP Disabled ZA for VL 6144
7044 10:12:17.946409 # ok 1152 # SKIP Get and set data for VL 6144
7045 10:12:17.946577 # ok 1153 Set VL 6160
7046 10:12:17.946718 # ok 1154 # SKIP Disabled ZA for VL 6160
7047 10:12:17.946857 # ok 1155 # SKIP Get and set data for VL 6160
7048 10:12:17.947029 # ok 1156 Set VL 6176
7049 10:12:17.951283 # ok 1157 # SKIP Disabled ZA for VL 6176
7050 10:12:17.951770 # ok 1158 # SKIP Get and set data for VL 6176
7051 10:12:17.951963 # ok 1159 Set VL 6192
7052 10:12:17.952115 # ok 1160 # SKIP Disabled ZA for VL 6192
7053 10:12:17.952269 # ok 1161 # SKIP Get and set data for VL 6192
7054 10:12:17.952420 # ok 1162 Set VL 6208
7055 10:12:17.952642 # ok 1163 # SKIP Disabled ZA for VL 6208
7056 10:12:17.952825 # ok 1164 # SKIP Get and set data for VL 6208
7057 10:12:17.952960 # ok 1165 Set VL 6224
7058 10:12:17.953079 # ok 1166 # SKIP Disabled ZA for VL 6224
7059 10:12:17.953222 # ok 1167 # SKIP Get and set data for VL 6224
7060 10:12:17.953358 # ok 1168 Set VL 6240
7061 10:12:17.953502 # ok 1169 # SKIP Disabled ZA for VL 6240
7062 10:12:17.953629 # ok 1170 # SKIP Get and set data for VL 6240
7063 10:12:17.953771 # ok 1171 Set VL 6256
7064 10:12:17.953919 # ok 1172 # SKIP Disabled ZA for VL 6256
7065 10:12:17.954040 # ok 1173 # SKIP Get and set data for VL 6256
7066 10:12:17.954157 # ok 1174 Set VL 6272
7067 10:12:17.954272 # ok 1175 # SKIP Disabled ZA for VL 6272
7068 10:12:17.954387 # ok 1176 # SKIP Get and set data for VL 6272
7069 10:12:17.954500 # ok 1177 Set VL 6288
7070 10:12:17.954615 # ok 1178 # SKIP Disabled ZA for VL 6288
7071 10:12:17.954729 # ok 1179 # SKIP Get and set data for VL 6288
7072 10:12:17.955242 # ok 1180 Set VL 6304
7073 10:12:17.955372 # ok 1181 # SKIP Disabled ZA for VL 6304
7074 10:12:17.957598 # ok 1182 # SKIP Get and set data for VL 6304
7075 10:12:17.957771 # ok 1183 Set VL 6320
7076 10:12:17.958814 # ok 1184 # SKIP Disabled ZA for VL 6320
7077 10:12:17.959267 # ok 1185 # SKIP Get and set data for VL 6320
7078 10:12:17.959469 # ok 1186 Set VL 6336
7079 10:12:17.959634 # ok 1187 # SKIP Disabled ZA for VL 6336
7080 10:12:17.959790 # ok 1188 # SKIP Get and set data for VL 6336
7081 10:12:17.959943 # ok 1189 Set VL 6352
7082 10:12:17.960130 # ok 1190 # SKIP Disabled ZA for VL 6352
7083 10:12:17.960276 # ok 1191 # SKIP Get and set data for VL 6352
7084 10:12:17.960423 # ok 1192 Set VL 6368
7085 10:12:17.960572 # ok 1193 # SKIP Disabled ZA for VL 6368
7086 10:12:17.960719 # ok 1194 # SKIP Get and set data for VL 6368
7087 10:12:17.960880 # ok 1195 Set VL 6384
7088 10:12:17.961015 # ok 1196 # SKIP Disabled ZA for VL 6384
7089 10:12:17.961160 # ok 1197 # SKIP Get and set data for VL 6384
7090 10:12:17.961315 # ok 1198 Set VL 6400
7091 10:12:17.961506 # ok 1199 # SKIP Disabled ZA for VL 6400
7092 10:12:17.961681 # ok 1200 # SKIP Get and set data for VL 6400
7093 10:12:17.961888 # ok 1201 Set VL 6416
7094 10:12:17.962071 # ok 1202 # SKIP Disabled ZA for VL 6416
7095 10:12:17.962252 # ok 1203 # SKIP Get and set data for VL 6416
7096 10:12:17.962399 # ok 1204 Set VL 6432
7097 10:12:17.962540 # ok 1205 # SKIP Disabled ZA for VL 6432
7098 10:12:17.962679 # ok 1206 # SKIP Get and set data for VL 6432
7099 10:12:17.962817 # ok 1207 Set VL 6448
7100 10:12:17.962955 # ok 1208 # SKIP Disabled ZA for VL 6448
7101 10:12:17.963093 # ok 1209 # SKIP Get and set data for VL 6448
7102 10:12:17.963231 # ok 1210 Set VL 6464
7103 10:12:17.963369 # ok 1211 # SKIP Disabled ZA for VL 6464
7104 10:12:17.963506 # ok 1212 # SKIP Get and set data for VL 6464
7105 10:12:17.963645 # ok 1213 Set VL 6480
7106 10:12:17.963819 # ok 1214 # SKIP Disabled ZA for VL 6480
7107 10:12:17.966891 # ok 1215 # SKIP Get and set data for VL 6480
7108 10:12:17.967334 # ok 1216 Set VL 6496
7109 10:12:17.967527 # ok 1217 # SKIP Disabled ZA for VL 6496
7110 10:12:17.967716 # ok 1218 # SKIP Get and set data for VL 6496
7111 10:12:17.967903 # ok 1219 Set VL 6512
7112 10:12:17.968103 # ok 1220 # SKIP Disabled ZA for VL 6512
7113 10:12:17.968280 # ok 1221 # SKIP Get and set data for VL 6512
7114 10:12:17.968440 # ok 1222 Set VL 6528
7115 10:12:17.968583 # ok 1223 # SKIP Disabled ZA for VL 6528
7116 10:12:17.968708 # ok 1224 # SKIP Get and set data for VL 6528
7117 10:12:17.968821 # ok 1225 Set VL 6544
7118 10:12:17.968933 # ok 1226 # SKIP Disabled ZA for VL 6544
7119 10:12:17.969045 # ok 1227 # SKIP Get and set data for VL 6544
7120 10:12:17.969193 # ok 1228 Set VL 6560
7121 10:12:17.969340 # ok 1229 # SKIP Disabled ZA for VL 6560
7122 10:12:17.969477 # ok 1230 # SKIP Get and set data for VL 6560
7123 10:12:17.969672 # ok 1231 Set VL 6576
7124 10:12:17.969823 # ok 1232 # SKIP Disabled ZA for VL 6576
7125 10:12:17.969939 # ok 1233 # SKIP Get and set data for VL 6576
7126 10:12:17.970056 # ok 1234 Set VL 6592
7127 10:12:17.970211 # ok 1235 # SKIP Disabled ZA for VL 6592
7128 10:12:17.970339 # ok 1236 # SKIP Get and set data for VL 6592
7129 10:12:17.970456 # ok 1237 Set VL 6608
7130 10:12:17.970569 # ok 1238 # SKIP Disabled ZA for VL 6608
7131 10:12:17.970682 # ok 1239 # SKIP Get and set data for VL 6608
7132 10:12:17.970796 # ok 1240 Set VL 6624
7133 10:12:17.970938 # ok 1241 # SKIP Disabled ZA for VL 6624
7134 10:12:17.971059 # ok 1242 # SKIP Get and set data for VL 6624
7135 10:12:17.971174 # ok 1243 Set VL 6640
7136 10:12:17.971288 # ok 1244 # SKIP Disabled ZA for VL 6640
7137 10:12:17.971402 # ok 1245 # SKIP Get and set data for VL 6640
7138 10:12:17.971516 # ok 1246 Set VL 6656
7139 10:12:17.974776 # ok 1247 # SKIP Disabled ZA for VL 6656
7140 10:12:17.974959 # ok 1248 # SKIP Get and set data for VL 6656
7141 10:12:17.975148 # ok 1249 Set VL 6672
7142 10:12:17.975313 # ok 1250 # SKIP Disabled ZA for VL 6672
7143 10:12:17.975482 # ok 1251 # SKIP Get and set data for VL 6672
7144 10:12:17.975633 # ok 1252 Set VL 6688
7145 10:12:17.975834 # ok 1253 # SKIP Disabled ZA for VL 6688
7146 10:12:17.976071 # ok 1254 # SKIP Get and set data for VL 6688
7147 10:12:17.976267 # ok 1255 Set VL 6704
7148 10:12:17.976432 # ok 1256 # SKIP Disabled ZA for VL 6704
7149 10:12:17.976608 # ok 1257 # SKIP Get and set data for VL 6704
7150 10:12:17.976765 # ok 1258 Set VL 6720
7151 10:12:17.976919 # ok 1259 # SKIP Disabled ZA for VL 6720
7152 10:12:17.977080 # ok 1260 # SKIP Get and set data for VL 6720
7153 10:12:17.977244 # ok 1261 Set VL 6736
7154 10:12:17.977427 # ok 1262 # SKIP Disabled ZA for VL 6736
7155 10:12:17.977557 # ok 1263 # SKIP Get and set data for VL 6736
7156 10:12:17.977764 # ok 1264 Set VL 6752
7157 10:12:17.977889 # ok 1265 # SKIP Disabled ZA for VL 6752
7158 10:12:17.978011 # ok 1266 # SKIP Get and set data for VL 6752
7159 10:12:17.978136 # ok 1267 Set VL 6768
7160 10:12:17.978251 # ok 1268 # SKIP Disabled ZA for VL 6768
7161 10:12:17.978365 # ok 1269 # SKIP Get and set data for VL 6768
7162 10:12:17.978478 # ok 1270 Set VL 6784
7163 10:12:17.978591 # ok 1271 # SKIP Disabled ZA for VL 6784
7164 10:12:17.978704 # ok 1272 # SKIP Get and set data for VL 6784
7165 10:12:17.978817 # ok 1273 Set VL 6800
7166 10:12:17.978929 # ok 1274 # SKIP Disabled ZA for VL 6800
7167 10:12:17.979042 # ok 1275 # SKIP Get and set data for VL 6800
7168 10:12:17.979154 # ok 1276 Set VL 6816
7169 10:12:17.979266 # ok 1277 # SKIP Disabled ZA for VL 6816
7170 10:12:17.983942 # ok 1278 # SKIP Get and set data for VL 6816
7171 10:12:17.984042 # ok 1279 Set VL 6832
7172 10:12:17.984123 # ok 1280 # SKIP Disabled ZA for VL 6832
7173 10:12:17.984214 # ok 1281 # SKIP Get and set data for VL 6832
7174 10:12:17.984301 # ok 1282 Set VL 6848
7175 10:12:17.984389 # ok 1283 # SKIP Disabled ZA for VL 6848
7176 10:12:17.984481 # ok 1284 # SKIP Get and set data for VL 6848
7177 10:12:17.984561 # ok 1285 Set VL 6864
7178 10:12:17.984649 # ok 1286 # SKIP Disabled ZA for VL 6864
7179 10:12:17.984738 # ok 1287 # SKIP Get and set data for VL 6864
7180 10:12:17.984818 # ok 1288 Set VL 6880
7181 10:12:17.984906 # ok 1289 # SKIP Disabled ZA for VL 6880
7182 10:12:17.984995 # ok 1290 # SKIP Get and set data for VL 6880
7183 10:12:17.985083 # ok 1291 Set VL 6896
7184 10:12:17.985172 # ok 1292 # SKIP Disabled ZA for VL 6896
7185 10:12:17.985260 # ok 1293 # SKIP Get and set data for VL 6896
7186 10:12:17.985349 # ok 1294 Set VL 6912
7187 10:12:17.985438 # ok 1295 # SKIP Disabled ZA for VL 6912
7188 10:12:17.985729 # ok 1296 # SKIP Get and set data for VL 6912
7189 10:12:17.985886 # ok 1297 Set VL 6928
7190 10:12:17.986006 # ok 1298 # SKIP Disabled ZA for VL 6928
7191 10:12:17.993506 # ok 1299 # SKIP Get and set data for VL 6928
7192 10:12:17.993737 # ok 1300 Set VL 6944
7193 10:12:17.994021 # ok 1301 # SKIP Disabled ZA for VL 6944
7194 10:12:17.994564 # ok 1302 # SKIP Get and set data for VL 6944
7195 10:12:17.994850 # ok 1303 Set VL 6960
7196 10:12:17.994947 # ok 1304 # SKIP Disabled ZA for VL 6960
7197 10:12:17.995049 # ok 1305 # SKIP Get and set data for VL 6960
7198 10:12:17.995137 # ok 1306 Set VL 6976
7199 10:12:17.995221 # ok 1307 # SKIP Disabled ZA for VL 6976
7200 10:12:17.995326 # ok 1308 # SKIP Get and set data for VL 6976
7201 10:12:17.995411 # ok 1309 Set VL 6992
7202 10:12:17.995496 # ok 1310 # SKIP Disabled ZA for VL 6992
7203 10:12:17.995595 # ok 1311 # SKIP Get and set data for VL 6992
7204 10:12:17.995683 # ok 1312 Set VL 7008
7205 10:12:17.995780 # ok 1313 # SKIP Disabled ZA for VL 7008
7206 10:12:17.995881 # ok 1314 # SKIP Get and set data for VL 7008
7207 10:12:17.995982 # ok 1315 Set VL 7024
7208 10:12:17.996081 # ok 1316 # SKIP Disabled ZA for VL 7024
7209 10:12:17.996188 # ok 1317 # SKIP Get and set data for VL 7024
7210 10:12:17.996295 # ok 1318 Set VL 7040
7211 10:12:17.996402 # ok 1319 # SKIP Disabled ZA for VL 7040
7212 10:12:17.996755 # ok 1320 # SKIP Get and set data for VL 7040
7213 10:12:17.996967 # ok 1321 Set VL 7056
7214 10:12:17.997193 # ok 1322 # SKIP Disabled ZA for VL 7056
7215 10:12:17.997376 # ok 1323 # SKIP Get and set data for VL 7056
7216 10:12:17.997538 # ok 1324 Set VL 7072
7217 10:12:17.997714 # ok 1325 # SKIP Disabled ZA for VL 7072
7218 10:12:17.997960 # ok 1326 # SKIP Get and set data for VL 7072
7219 10:12:17.998121 # ok 1327 Set VL 7088
7220 10:12:17.998268 # ok 1328 # SKIP Disabled ZA for VL 7088
7221 10:12:17.998409 # ok 1329 # SKIP Get and set data for VL 7088
7222 10:12:17.998551 # ok 1330 Set VL 7104
7223 10:12:17.998691 # ok 1331 # SKIP Disabled ZA for VL 7104
7224 10:12:18.007477 # ok 1332 # SKIP Get and set data for VL 7104
7225 10:12:18.008009 # ok 1333 Set VL 7120
7226 10:12:18.008205 # ok 1334 # SKIP Disabled ZA for VL 7120
7227 10:12:18.008384 # ok 1335 # SKIP Get and set data for VL 7120
7228 10:12:18.008570 # ok 1336 Set VL 7136
7229 10:12:18.008803 # ok 1337 # SKIP Disabled ZA for VL 7136
7230 10:12:18.009000 # ok 1338 # SKIP Get and set data for VL 7136
7231 10:12:18.009196 # ok 1339 Set VL 7152
7232 10:12:18.009356 # ok 1340 # SKIP Disabled ZA for VL 7152
7233 10:12:18.009551 # ok 1341 # SKIP Get and set data for VL 7152
7234 10:12:18.009762 # ok 1342 Set VL 7168
7235 10:12:18.009898 # ok 1343 # SKIP Disabled ZA for VL 7168
7236 10:12:18.010051 # ok 1344 # SKIP Get and set data for VL 7168
7237 10:12:18.010178 # ok 1345 Set VL 7184
7238 10:12:18.010298 # ok 1346 # SKIP Disabled ZA for VL 7184
7239 10:12:18.010414 # ok 1347 # SKIP Get and set data for VL 7184
7240 10:12:18.010530 # ok 1348 Set VL 7200
7241 10:12:18.010645 # ok 1349 # SKIP Disabled ZA for VL 7200
7242 10:12:18.010759 # ok 1350 # SKIP Get and set data for VL 7200
7243 10:12:18.010874 # ok 1351 Set VL 7216
7244 10:12:18.010988 # ok 1352 # SKIP Disabled ZA for VL 7216
7245 10:12:18.011104 # ok 1353 # SKIP Get and set data for VL 7216
7246 10:12:18.011219 # ok 1354 Set VL 7232
7247 10:12:18.019982 # ok 1355 # SKIP Disabled ZA for VL 7232
7248 10:12:18.020281 # ok 1356 # SKIP Get and set data for VL 7232
7249 10:12:18.020478 # ok 1357 Set VL 7248
7250 10:12:18.020660 # ok 1358 # SKIP Disabled ZA for VL 7248
7251 10:12:18.020823 # ok 1359 # SKIP Get and set data for VL 7248
7252 10:12:18.020993 # ok 1360 Set VL 7264
7253 10:12:18.021211 # ok 1361 # SKIP Disabled ZA for VL 7264
7254 10:12:18.021414 # ok 1362 # SKIP Get and set data for VL 7264
7255 10:12:18.021592 # ok 1363 Set VL 7280
7256 10:12:18.021732 # ok 1364 # SKIP Disabled ZA for VL 7280
7257 10:12:18.021849 # ok 1365 # SKIP Get and set data for VL 7280
7258 10:12:18.021963 # ok 1366 Set VL 7296
7259 10:12:18.022077 # ok 1367 # SKIP Disabled ZA for VL 7296
7260 10:12:18.022190 # ok 1368 # SKIP Get and set data for VL 7296
7261 10:12:18.022301 # ok 1369 Set VL 7312
7262 10:12:18.022443 # ok 1370 # SKIP Disabled ZA for VL 7312
7263 10:12:18.022565 # ok 1371 # SKIP Get and set data for VL 7312
7264 10:12:18.022681 # ok 1372 Set VL 7328
7265 10:12:18.031920 # ok 1373 # SKIP Disabled ZA for VL 7328
7266 10:12:18.032494 # ok 1374 # SKIP Get and set data for VL 7328
7267 10:12:18.032707 # ok 1375 Set VL 7344
7268 10:12:18.032898 # ok 1376 # SKIP Disabled ZA for VL 7344
7269 10:12:18.033084 # ok 1377 # SKIP Get and set data for VL 7344
7270 10:12:18.033230 # ok 1378 Set VL 7360
7271 10:12:18.033476 # ok 1379 # SKIP Disabled ZA for VL 7360
7272 10:12:18.033709 # ok 1380 # SKIP Get and set data for VL 7360
7273 10:12:18.033864 # ok 1381 Set VL 7376
7274 10:12:18.033984 # ok 1382 # SKIP Disabled ZA for VL 7376
7275 10:12:18.034100 # ok 1383 # SKIP Get and set data for VL 7376
7276 10:12:18.034214 # ok 1384 Set VL 7392
7277 10:12:18.034327 # ok 1385 # SKIP Disabled ZA for VL 7392
7278 10:12:18.034468 # ok 1386 # SKIP Get and set data for VL 7392
7279 10:12:18.034592 # ok 1387 Set VL 7408
7280 10:12:18.045148 # ok 1388 # SKIP Disabled ZA for VL 7408
7281 10:12:18.045760 # ok 1389 # SKIP Get and set data for VL 7408
7282 10:12:18.045928 # ok 1390 Set VL 7424
7283 10:12:18.046058 # ok 1391 # SKIP Disabled ZA for VL 7424
7284 10:12:18.046180 # ok 1392 # SKIP Get and set data for VL 7424
7285 10:12:18.046298 # ok 1393 Set VL 7440
7286 10:12:18.056050 # ok 1394 # SKIP Disabled ZA for VL 7440
7287 10:12:18.056627 # ok 1395 # SKIP Get and set data for VL 7440
7288 10:12:18.056827 # ok 1396 Set VL 7456
7289 10:12:18.057024 # ok 1397 # SKIP Disabled ZA for VL 7456
7290 10:12:18.057198 # ok 1398 # SKIP Get and set data for VL 7456
7291 10:12:18.057360 # ok 1399 Set VL 7472
7292 10:12:18.057544 # ok 1400 # SKIP Disabled ZA for VL 7472
7293 10:12:18.057737 # ok 1401 # SKIP Get and set data for VL 7472
7294 10:12:18.057885 # ok 1402 Set VL 7488
7295 10:12:18.058002 # ok 1403 # SKIP Disabled ZA for VL 7488
7296 10:12:18.058115 # ok 1404 # SKIP Get and set data for VL 7488
7297 10:12:18.058229 # ok 1405 Set VL 7504
7298 10:12:18.058340 # ok 1406 # SKIP Disabled ZA for VL 7504
7299 10:12:18.058451 # ok 1407 # SKIP Get and set data for VL 7504
7300 10:12:18.058590 # ok 1408 Set VL 7520
7301 10:12:18.067901 # ok 1409 # SKIP Disabled ZA for VL 7520
7302 10:12:18.068262 # ok 1410 # SKIP Get and set data for VL 7520
7303 10:12:18.068361 # ok 1411 Set VL 7536
7304 10:12:18.068444 # ok 1412 # SKIP Disabled ZA for VL 7536
7305 10:12:18.068544 # ok 1413 # SKIP Get and set data for VL 7536
7306 10:12:18.068624 # ok 1414 Set VL 7552
7307 10:12:18.068716 # ok 1415 # SKIP Disabled ZA for VL 7552
7308 10:12:18.068810 # ok 1416 # SKIP Get and set data for VL 7552
7309 10:12:18.068902 # ok 1417 Set VL 7568
7310 10:12:18.069192 # ok 1418 # SKIP Disabled ZA for VL 7568
7311 10:12:18.069291 # ok 1419 # SKIP Get and set data for VL 7568
7312 10:12:18.069385 # ok 1420 Set VL 7584
7313 10:12:18.069468 # ok 1421 # SKIP Disabled ZA for VL 7584
7314 10:12:18.069755 # ok 1422 # SKIP Get and set data for VL 7584
7315 10:12:18.069853 # ok 1423 Set VL 7600
7316 10:12:18.079872 # ok 1424 # SKIP Disabled ZA for VL 7600
7317 10:12:18.080262 # ok 1425 # SKIP Get and set data for VL 7600
7318 10:12:18.080361 # ok 1426 Set VL 7616
7319 10:12:18.080441 # ok 1427 # SKIP Disabled ZA for VL 7616
7320 10:12:18.080552 # ok 1428 # SKIP Get and set data for VL 7616
7321 10:12:18.080632 # ok 1429 Set VL 7632
7322 10:12:18.080719 # ok 1430 # SKIP Disabled ZA for VL 7632
7323 10:12:18.080810 # ok 1431 # SKIP Get and set data for VL 7632
7324 10:12:18.080902 # ok 1432 Set VL 7648
7325 10:12:18.080981 # ok 1433 # SKIP Disabled ZA for VL 7648
7326 10:12:18.081260 # ok 1434 # SKIP Get and set data for VL 7648
7327 10:12:18.081359 # ok 1435 Set VL 7664
7328 10:12:18.081450 # ok 1436 # SKIP Disabled ZA for VL 7664
7329 10:12:18.081529 # ok 1437 # SKIP Get and set data for VL 7664
7330 10:12:18.081755 # ok 1438 Set VL 7680
7331 10:12:18.081849 # ok 1439 # SKIP Disabled ZA for VL 7680
7332 10:12:18.092156 # ok 1440 # SKIP Get and set data for VL 7680
7333 10:12:18.092468 # ok 1441 Set VL 7696
7334 10:12:18.092567 # ok 1442 # SKIP Disabled ZA for VL 7696
7335 10:12:18.092659 # ok 1443 # SKIP Get and set data for VL 7696
7336 10:12:18.092738 # ok 1444 Set VL 7712
7337 10:12:18.092826 # ok 1445 # SKIP Disabled ZA for VL 7712
7338 10:12:18.093112 # ok 1446 # SKIP Get and set data for VL 7712
7339 10:12:18.093210 # ok 1447 Set VL 7728
7340 10:12:18.093303 # ok 1448 # SKIP Disabled ZA for VL 7728
7341 10:12:18.093395 # ok 1449 # SKIP Get and set data for VL 7728
7342 10:12:18.093490 # ok 1450 Set VL 7744
7343 10:12:18.093585 # ok 1451 # SKIP Disabled ZA for VL 7744
7344 10:12:18.093787 # ok 1452 # SKIP Get and set data for VL 7744
7345 10:12:18.103910 # ok 1453 Set VL 7760
7346 10:12:18.104015 # ok 1454 # SKIP Disabled ZA for VL 7760
7347 10:12:18.104096 # ok 1455 # SKIP Get and set data for VL 7760
7348 10:12:18.104186 # ok 1456 Set VL 7776
7349 10:12:18.104264 # ok 1457 # SKIP Disabled ZA for VL 7776
7350 10:12:18.104340 # ok 1458 # SKIP Get and set data for VL 7776
7351 10:12:18.104415 # ok 1459 Set VL 7792
7352 10:12:18.104508 # ok 1460 # SKIP Disabled ZA for VL 7792
7353 10:12:18.104588 # ok 1461 # SKIP Get and set data for VL 7792
7354 10:12:18.104665 # ok 1462 Set VL 7808
7355 10:12:18.104742 # ok 1463 # SKIP Disabled ZA for VL 7808
7356 10:12:18.104836 # ok 1464 # SKIP Get and set data for VL 7808
7357 10:12:18.104917 # ok 1465 Set VL 7824
7358 10:12:18.104993 # ok 1466 # SKIP Disabled ZA for VL 7824
7359 10:12:18.105083 # ok 1467 # SKIP Get and set data for VL 7824
7360 10:12:18.105164 # ok 1468 Set VL 7840
7361 10:12:18.105244 # ok 1469 # SKIP Disabled ZA for VL 7840
7362 10:12:18.105333 # ok 1470 # SKIP Get and set data for VL 7840
7363 10:12:18.105415 # ok 1471 Set VL 7856
7364 10:12:18.105495 # ok 1472 # SKIP Disabled ZA for VL 7856
7365 10:12:18.105584 # ok 1473 # SKIP Get and set data for VL 7856
7366 10:12:18.105674 # ok 1474 Set VL 7872
7367 10:12:18.105750 # ok 1475 # SKIP Disabled ZA for VL 7872
7368 10:12:18.105841 # ok 1476 # SKIP Get and set data for VL 7872
7369 10:12:18.114709 # ok 1477 Set VL 7888
7370 10:12:18.115045 # ok 1478 # SKIP Disabled ZA for VL 7888
7371 10:12:18.115238 # ok 1479 # SKIP Get and set data for VL 7888
7372 10:12:18.115408 # ok 1480 Set VL 7904
7373 10:12:18.115608 # ok 1481 # SKIP Disabled ZA for VL 7904
7374 10:12:18.115773 # ok 1482 # SKIP Get and set data for VL 7904
7375 10:12:18.115930 # ok 1483 Set VL 7920
7376 10:12:18.116084 # ok 1484 # SKIP Disabled ZA for VL 7920
7377 10:12:18.116242 # ok 1485 # SKIP Get and set data for VL 7920
7378 10:12:18.116400 # ok 1486 Set VL 7936
7379 10:12:18.116537 # ok 1487 # SKIP Disabled ZA for VL 7936
7380 10:12:18.116725 # ok 1488 # SKIP Get and set data for VL 7936
7381 10:12:18.116886 # ok 1489 Set VL 7952
7382 10:12:18.117005 # ok 1490 # SKIP Disabled ZA for VL 7952
7383 10:12:18.117118 # ok 1491 # SKIP Get and set data for VL 7952
7384 10:12:18.117230 # ok 1492 Set VL 7968
7385 10:12:18.117342 # ok 1493 # SKIP Disabled ZA for VL 7968
7386 10:12:18.117456 # ok 1494 # SKIP Get and set data for VL 7968
7387 10:12:18.117568 # ok 1495 Set VL 7984
7388 10:12:18.117733 # ok 1496 # SKIP Disabled ZA for VL 7984
7389 10:12:18.117935 # ok 1497 # SKIP Get and set data for VL 7984
7390 10:12:18.118117 # ok 1498 Set VL 8000
7391 10:12:18.118300 # ok 1499 # SKIP Disabled ZA for VL 8000
7392 10:12:18.118475 # ok 1500 # SKIP Get and set data for VL 8000
7393 10:12:18.118609 # ok 1501 Set VL 8016
7394 10:12:18.118748 # ok 1502 # SKIP Disabled ZA for VL 8016
7395 10:12:18.125734 # ok 1503 # SKIP Get and set data for VL 8016
7396 10:12:18.125952 # ok 1504 Set VL 8032
7397 10:12:18.126031 # ok 1505 # SKIP Disabled ZA for VL 8032
7398 10:12:18.126105 # ok 1506 # SKIP Get and set data for VL 8032
7399 10:12:18.126751 # ok 1507 Set VL 8048
7400 10:12:18.127080 # ok 1508 # SKIP Disabled ZA for VL 8048
7401 10:12:18.127262 # ok 1509 # SKIP Get and set data for VL 8048
7402 10:12:18.127465 # ok 1510 Set VL 8064
7403 10:12:18.127638 # ok 1511 # SKIP Disabled ZA for VL 8064
7404 10:12:18.127833 # ok 1512 # SKIP Get and set data for VL 8064
7405 10:12:18.127999 # ok 1513 Set VL 8080
7406 10:12:18.128153 # ok 1514 # SKIP Disabled ZA for VL 8080
7407 10:12:18.128305 # ok 1515 # SKIP Get and set data for VL 8080
7408 10:12:18.128458 # ok 1516 Set VL 8096
7409 10:12:18.128583 # ok 1517 # SKIP Disabled ZA for VL 8096
7410 10:12:18.128712 # ok 1518 # SKIP Get and set data for VL 8096
7411 10:12:18.128870 # ok 1519 Set VL 8112
7412 10:12:18.129034 # ok 1520 # SKIP Disabled ZA for VL 8112
7413 10:12:18.129234 # ok 1521 # SKIP Get and set data for VL 8112
7414 10:12:18.129363 # ok 1522 Set VL 8128
7415 10:12:18.129479 # ok 1523 # SKIP Disabled ZA for VL 8128
7416 10:12:18.129593 # ok 1524 # SKIP Get and set data for VL 8128
7417 10:12:18.129721 # ok 1525 Set VL 8144
7418 10:12:18.129835 # ok 1526 # SKIP Disabled ZA for VL 8144
7419 10:12:18.129947 # ok 1527 # SKIP Get and set data for VL 8144
7420 10:12:18.130058 # ok 1528 Set VL 8160
7421 10:12:18.130169 # ok 1529 # SKIP Disabled ZA for VL 8160
7422 10:12:18.130281 # ok 1530 # SKIP Get and set data for VL 8160
7423 10:12:18.130394 # ok 1531 Set VL 8176
7424 10:12:18.130505 # ok 1532 # SKIP Disabled ZA for VL 8176
7425 10:12:18.130617 # ok 1533 # SKIP Get and set data for VL 8176
7426 10:12:18.130729 # ok 1534 Set VL 8192
7427 10:12:18.130840 # ok 1535 # SKIP Disabled ZA for VL 8192
7428 10:12:18.130952 # ok 1536 # SKIP Get and set data for VL 8192
7429 10:12:18.131064 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7430 10:12:18.131177 ok 34 selftests: arm64: za-ptrace
7431 10:12:18.131318 # selftests: arm64: check_buffer_fill
7432 10:12:18.563640 # 1..20
7433 10:12:18.564230 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7434 10:12:18.564417 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7435 10:12:18.564563 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7436 10:12:18.564751 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7437 10:12:18.564990 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7438 10:12:18.565166 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7439 10:12:18.565344 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7440 10:12:18.565498 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7441 10:12:18.565815 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7442 10:12:18.566011 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 10:12:18.566180 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7444 10:12:18.566361 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7445 10:12:18.566499 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7446 10:12:18.591750 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7447 10:12:18.592461 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7448 10:12:18.592887 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7449 10:12:18.593088 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7450 10:12:18.593300 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7451 10:12:18.593543 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7452 10:12:18.593725 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7453 10:12:18.593867 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7454 10:12:18.599703 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7455 10:12:18.764983 # selftests: arm64: check_child_memory
7456 10:12:19.364119 # 1..12
7457 10:12:19.364698 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7458 10:12:19.364904 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7459 10:12:19.365076 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7460 10:12:19.365274 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7461 10:12:19.365420 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7462 10:12:19.365547 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7463 10:12:19.365744 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7464 10:12:19.365916 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7465 10:12:19.366126 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7466 10:12:19.366320 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7467 10:12:19.370098 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7468 10:12:19.380947 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7469 10:12:19.381373 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7470 10:12:19.400089 not ok 36 selftests: arm64: check_child_memory # exit=1
7471 10:12:19.553005 # selftests: arm64: check_gcr_el1_cswitch
7472 10:13:04.747771 <47>[ 104.438791] systemd-journald[105]: Sent WATCHDOG=1 notification.
7473 10:13:05.651548 <47>[ 105.343855] systemd-journald[105]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3328 of 4437 items, 2555904 file size, 768 bytes per hash table item), suggesting rotation.
7474 10:13:05.652098 <47>[ 105.344431] systemd-journald[105]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
7475 10:13:05.652269 <47>[ 105.344745] systemd-journald[105]: Rotating...
7476 10:13:05.708287 <47>[ 105.400873] systemd-journald[105]: Reserving 333 entries in field hash table.
7477 10:13:05.760401 <47>[ 105.452888] systemd-journald[105]: Reserving 4437 entries in data hash table.
7478 10:13:05.794780 <47>[ 105.487378] systemd-journald[105]: Vacuuming...
7479 10:13:05.816735 <47>[ 105.509220] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
7480 10:13:06.506713 # 1..1
7481 10:13:06.507241 # 1..1
7482 10:13:06.507345 # 1..1
7483 10:13:06.507429 # 1..1
7484 10:13:06.507506 # 1..1
7485 10:13:06.507583 # 1..1
7486 10:13:06.507658 # 1..1
7487 10:13:06.507733 # 1..1
7488 10:13:06.507808 # 1..1
7489 10:13:06.507887 # 1..1
7490 10:13:06.507963 # 1..1
7491 10:13:06.508038 # 1..1
7492 10:13:06.508117 # 1..1
7493 10:13:06.508198 # 1..1
7494 10:13:06.508277 # 1..1
7495 10:13:06.508351 # 1..1
7496 10:13:06.508428 # 1..1
7497 10:13:06.508503 # 1..1
7498 10:13:06.508582 # 1..1
7499 10:13:06.508661 # 1..1
7500 10:13:06.508739 # 1..1
7501 10:13:06.508815 # 1..1
7502 10:13:06.508892 # 1..1
7503 10:13:06.508967 # 1..1
7504 10:13:06.509044 # 1..1
7505 10:13:06.509121 # 1..1
7506 10:13:06.509198 # 1..1
7507 10:13:06.509275 # 1..1
7508 10:13:06.509352 # 1..1
7509 10:13:06.509430 # 1..1
7510 10:13:06.509507 # 1..1
7511 10:13:06.509585 # 1..1
7512 10:13:06.509693 # 1..1
7513 10:13:06.509775 # 1..1
7514 10:13:06.509852 # 1..1
7515 10:13:06.509928 # 1..1
7516 10:13:06.510006 # 1..1
7517 10:13:06.510083 # 1..1
7518 10:13:06.510164 # 1..1
7519 10:13:06.510243 # 1..1
7520 10:13:06.510322 # 1..1
7521 10:13:06.510399 # 1..1
7522 10:13:06.510477 # 1..1
7523 10:13:06.510555 # 1..1
7524 10:13:06.510633 # 1..1
7525 10:13:06.510710 # 1..1
7526 10:13:06.510788 # 1..1
7527 10:13:06.510864 # 1..1
7528 10:13:06.510939 # 1..1
7529 10:13:06.511014 # 1..1
7530 10:13:06.511089 # 1..1
7531 10:13:06.511163 # 1..1
7532 10:13:06.511239 # 1..1
7533 10:13:06.511317 # 1..1
7534 10:13:06.511393 # 1..1
7535 10:13:06.511468 # 1..1
7536 10:13:06.511542 # 1..1
7537 10:13:06.511617 # 1..1
7538 10:13:06.511690 # 1..1
7539 10:13:06.511765 # 1..1
7540 10:13:06.511839 # 1..1
7541 10:13:06.511914 # 1..1
7542 10:13:06.511989 # 1..1
7543 10:13:06.512063 # 1..1
7544 10:13:06.512137 # 1..1
7545 10:13:06.512211 # 1..1
7546 10:13:06.512285 # 1..1
7547 10:13:06.512359 # 1..1
7548 10:13:06.512433 # 1..1
7549 10:13:06.512507 # 1..1
7550 10:13:06.512582 # 1..1
7551 10:13:06.512659 # 1..1
7552 10:13:06.512734 # 1..1
7553 10:13:06.512808 # 1..1
7554 10:13:06.512884 # 1..1
7555 10:13:06.512959 # 1..1
7556 10:13:06.513035 # 1..1
7557 10:13:06.513112 # 1..1
7558 10:13:06.513190 # 1..1
7559 10:13:06.513265 # 1..1
7560 10:13:06.513341 # 1..1
7561 10:13:06.513417 # 1..1
7562 10:13:06.513492 # 1..1
7563 10:13:06.571952 # 1..1
7564 10:13:06.572177 # 1..1
7565 10:13:06.572271 # 1..1
7566 10:13:06.572365 # 1..1
7567 10:13:06.572658 # 1..1
7568 10:13:06.572758 # 1..1
7569 10:13:06.572847 # 1..1
7570 10:13:06.572935 # 1..1
7571 10:13:06.573023 # 1..1
7572 10:13:06.573108 # 1..1
7573 10:13:06.573191 # 1..1
7574 10:13:06.573278 # 1..1
7575 10:13:06.573362 # 1..1
7576 10:13:06.573444 # 1..1
7577 10:13:06.573525 # 1..1
7578 10:13:06.573608 # 1..1
7579 10:13:06.573698 # 1..1
7580 10:13:06.573780 # 1..1
7581 10:13:06.573863 # 1..1
7582 10:13:06.573946 # 1..1
7583 10:13:06.574028 # 1..1
7584 10:13:06.594498 # 1..1
7585 10:13:06.594685 # 1..1
7586 10:13:06.594779 # 1..1
7587 10:13:06.594865 # 1..1
7588 10:13:06.594947 # 1..1
7589 10:13:06.595238 # 1..1
7590 10:13:06.595337 # 1..1
7591 10:13:06.595421 # 1..1
7592 10:13:06.595503 # 1..1
7593 10:13:06.595585 # 1..1
7594 10:13:06.595670 # 1..1
7595 10:13:06.595749 # 1..1
7596 10:13:06.595828 # 1..1
7597 10:13:06.595908 # 1..1
7598 10:13:06.595995 # 1..1
7599 10:13:06.596081 # 1..1
7600 10:13:06.596164 # 1..1
7601 10:13:06.596243 # 1..1
7602 10:13:06.596323 # 1..1
7603 10:13:06.596412 # 1..1
7604 10:13:06.596492 # 1..1
7605 10:13:06.596573 # 1..1
7606 10:13:06.596654 # 1..1
7607 10:13:06.596733 # 1..1
7608 10:13:06.596813 # 1..1
7609 10:13:06.596916 # 1..1
7610 10:13:06.597003 # 1..1
7611 10:13:06.597085 # 1..1
7612 10:13:06.597167 # 1..1
7613 10:13:06.597248 # 1..1
7614 10:13:06.597332 # 1..1
7615 10:13:06.597411 # 1..1
7616 10:13:06.597493 # 1..1
7617 10:13:06.597574 # 1..1
7618 10:13:06.597662 # 1..1
7619 10:13:06.597744 # 1..1
7620 10:13:06.597825 # 1..1
7621 10:13:06.597905 # 1..1
7622 10:13:06.597986 # 1..1
7623 10:13:06.598067 # 1..1
7624 10:13:06.598148 # 1..1
7625 10:13:06.598232 # 1..1
7626 10:13:06.598321 # 1..1
7627 10:13:06.598406 # 1..1
7628 10:13:06.598489 # 1..1
7629 10:13:06.598573 # 1..1
7630 10:13:06.598655 # 1..1
7631 10:13:06.598739 # 1..1
7632 10:13:06.598821 # 1..1
7633 10:13:06.598903 # 1..1
7634 10:13:06.598985 # 1..1
7635 10:13:06.599068 # 1..1
7636 10:13:06.599152 # 1..1
7637 10:13:06.599234 # 1..1
7638 10:13:06.599316 # 1..1
7639 10:13:06.599400 # 1..1
7640 10:13:06.599483 # 1..1
7641 10:13:06.599565 # 1..1
7642 10:13:06.610598 # 1..1
7643 10:13:06.610897 # 1..1
7644 10:13:06.611100 # 1..1
7645 10:13:06.611540 # 1..1
7646 10:13:06.611738 # 1..1
7647 10:13:06.611905 # 1..1
7648 10:13:06.612061 # 1..1
7649 10:13:06.612219 # 1..1
7650 10:13:06.612373 # 1..1
7651 10:13:06.612524 # 1..1
7652 10:13:06.612679 # 1..1
7653 10:13:06.612833 # 1..1
7654 10:13:06.612989 # 1..1
7655 10:13:06.613142 # 1..1
7656 10:13:06.613295 # 1..1
7657 10:13:06.613457 # 1..1
7658 10:13:06.613617 # 1..1
7659 10:13:06.613773 # 1..1
7660 10:13:06.613906 # 1..1
7661 10:13:06.614078 # 1..1
7662 10:13:06.614221 # 1..1
7663 10:13:06.614364 # 1..1
7664 10:13:06.614507 # 1..1
7665 10:13:06.614648 # 1..1
7666 10:13:06.614787 # 1..1
7667 10:13:06.614927 # 1..1
7668 10:13:06.615066 # 1..1
7669 10:13:06.615205 # 1..1
7670 10:13:06.615345 # 1..1
7671 10:13:06.615485 # 1..1
7672 10:13:06.615625 # 1..1
7673 10:13:06.615763 # 1..1
7674 10:13:06.615902 # 1..1
7675 10:13:06.616098 # 1..1
7676 10:13:06.616236 # 1..1
7677 10:13:06.616381 # 1..1
7678 10:13:06.616525 # 1..1
7679 10:13:06.616665 # 1..1
7680 10:13:06.616805 # 1..1
7681 10:13:06.616944 # 1..1
7682 10:13:06.617083 # 1..1
7683 10:13:06.617223 # 1..1
7684 10:13:06.617364 # 1..1
7685 10:13:06.617503 # 1..1
7686 10:13:06.617642 # 1..1
7687 10:13:06.617803 # 1..1
7688 10:13:06.617941 # 1..1
7689 10:13:06.618081 # 1..1
7690 10:13:06.618219 # 1..1
7691 10:13:06.618363 # 1..1
7692 10:13:06.618503 # 1..1
7693 10:13:06.618642 # 1..1
7694 10:13:06.618781 # 1..1
7695 10:13:06.618921 # 1..1
7696 10:13:06.619059 # 1..1
7697 10:13:06.619199 # 1..1
7698 10:13:06.619339 # 1..1
7699 10:13:06.619481 # 1..1
7700 10:13:06.619622 # 1..1
7701 10:13:06.619761 # 1..1
7702 10:13:06.619901 # 1..1
7703 10:13:06.620041 # 1..1
7704 10:13:06.620182 # 1..1
7705 10:13:06.620322 # 1..1
7706 10:13:06.620508 # 1..1
7707 10:13:06.620683 # 1..1
7708 10:13:06.620825 # 1..1
7709 10:13:06.620966 # 1..1
7710 10:13:06.621106 # 1..1
7711 10:13:06.621283 # 1..1
7712 10:13:06.621453 # 1..1
7713 10:13:06.621594 # 1..1
7714 10:13:06.621750 # 1..1
7715 10:13:06.621891 # 1..1
7716 10:13:06.622031 # 1..1
7717 10:13:06.622170 # 1..1
7718 10:13:06.622309 # 1..1
7719 10:13:06.622451 # 1..1
7720 10:13:06.622590 # 1..1
7721 10:13:06.622731 # 1..1
7722 10:13:06.622871 # 1..1
7723 10:13:06.623011 # 1..1
7724 10:13:06.623150 # 1..1
7725 10:13:06.623290 # 1..1
7726 10:13:06.623431 # 1..1
7727 10:13:06.623571 # 1..1
7728 10:13:06.623709 # 1..1
7729 10:13:06.623849 # 1..1
7730 10:13:06.623986 # 1..1
7731 10:13:06.624124 # 1..1
7732 10:13:06.624263 # 1..1
7733 10:13:06.624413 # 1..1
7734 10:13:06.624568 # 1..1
7735 10:13:06.624686 # 1..1
7736 10:13:06.624801 # 1..1
7737 10:13:06.624915 # 1..1
7738 10:13:06.625034 # 1..1
7739 10:13:06.625154 # 1..1
7740 10:13:06.625267 # 1..1
7741 10:13:06.625383 # 1..1
7742 10:13:06.625496 # 1..1
7743 10:13:06.625609 # 1..1
7744 10:13:06.625739 # 1..1
7745 10:13:06.625852 # 1..1
7746 10:13:06.625966 # 1..1
7747 10:13:06.626079 # 1..1
7748 10:13:06.626192 # 1..1
7749 10:13:06.626305 # 1..1
7750 10:13:06.626421 # 1..1
7751 10:13:06.626536 # 1..1
7752 10:13:06.626650 # 1..1
7753 10:13:06.626764 # 1..1
7754 10:13:06.626880 # 1..1
7755 10:13:06.626992 # 1..1
7756 10:13:06.627106 # 1..1
7757 10:13:06.627220 # 1..1
7758 10:13:06.627333 # 1..1
7759 10:13:06.627446 # 1..1
7760 10:13:06.639050 # 1..1
7761 10:13:06.639363 # 1..1
7762 10:13:06.639550 # 1..1
7763 10:13:06.639708 # 1..1
7764 10:13:06.639871 # 1..1
7765 10:13:06.640021 # 1..1
7766 10:13:06.640431 # 1..1
7767 10:13:06.640591 # 1..1
7768 10:13:06.640719 # 1..1
7769 10:13:06.640837 # 1..1
7770 10:13:06.640953 # 1..1
7771 10:13:06.641076 # 1..1
7772 10:13:06.641193 # 1..1
7773 10:13:06.641308 # 1..1
7774 10:13:06.641425 # 1..1
7775 10:13:06.641539 # 1..1
7776 10:13:06.641668 # 1..1
7777 10:13:06.641788 # 1..1
7778 10:13:06.641903 # 1..1
7779 10:13:06.642017 # 1..1
7780 10:13:06.642129 # 1..1
7781 10:13:06.642243 # 1..1
7782 10:13:06.642357 # 1..1
7783 10:13:06.642470 # 1..1
7784 10:13:06.642591 # 1..1
7785 10:13:06.642704 # 1..1
7786 10:13:06.642818 # 1..1
7787 10:13:06.642932 # 1..1
7788 10:13:06.643054 # 1..1
7789 10:13:06.643171 # 1..1
7790 10:13:06.643286 # 1..1
7791 10:13:06.643401 # 1..1
7792 10:13:06.643516 # 1..1
7793 10:13:06.643630 # 1..1
7794 10:13:06.643745 # 1..1
7795 10:13:06.643874 # 1..1
7796 10:13:06.644038 # 1..1
7797 10:13:06.644160 # 1..1
7798 10:13:06.644276 # 1..1
7799 10:13:06.644390 # 1..1
7800 10:13:06.644505 # 1..1
7801 10:13:06.644619 # 1..1
7802 10:13:06.644733 # 1..1
7803 10:13:06.644845 # 1..1
7804 10:13:06.644958 # 1..1
7805 10:13:06.645071 # 1..1
7806 10:13:06.645184 # 1..1
7807 10:13:06.645336 # 1..1
7808 10:13:06.645461 # 1..1
7809 10:13:06.645584 # 1..1
7810 10:13:06.654991 # 1..1
7811 10:13:06.655263 # 1..1
7812 10:13:06.655689 # 1..1
7813 10:13:06.655883 # 1..1
7814 10:13:06.656081 # 1..1
7815 10:13:06.656248 # 1..1
7816 10:13:06.656423 # 1..1
7817 10:13:06.656572 # 1..1
7818 10:13:06.656694 # 1..1
7819 10:13:06.656810 # 1..1
7820 10:13:06.656923 # 1..1
7821 10:13:06.657045 # 1..1
7822 10:13:06.657163 # 1..1
7823 10:13:06.657277 # 1..1
7824 10:13:06.657390 # 1..1
7825 10:13:06.657503 # 1..1
7826 10:13:06.657615 # 1..1
7827 10:13:06.657747 # 1..1
7828 10:13:06.657860 # 1..1
7829 10:13:06.657973 # 1..1
7830 10:13:06.658090 # 1..1
7831 10:13:06.658207 # 1..1
7832 10:13:06.658321 # 1..1
7833 10:13:06.658437 # 1..1
7834 10:13:06.658557 # 1..1
7835 10:13:06.658672 # 1..1
7836 10:13:06.658789 # 1..1
7837 10:13:06.658906 # 1..1
7838 10:13:06.659058 # 1..1
7839 10:13:06.659186 # 1..1
7840 10:13:06.659305 # 1..1
7841 10:13:06.659422 # 1..1
7842 10:13:06.659541 # 1..1
7843 10:13:06.659655 # 1..1
7844 10:13:06.659769 # 1..1
7845 10:13:06.659912 # 1..1
7846 10:13:06.660068 # 1..1
7847 10:13:06.660190 # 1..1
7848 10:13:06.660307 # 1..1
7849 10:13:06.660448 # 1..1
7850 10:13:06.660595 # 1..1
7851 10:13:06.660714 # 1..1
7852 10:13:06.660832 # 1..1
7853 10:13:06.660947 # 1..1
7854 10:13:06.661075 # 1..1
7855 10:13:06.661192 # 1..1
7856 10:13:06.661307 # 1..1
7857 10:13:06.661422 # 1..1
7858 10:13:06.661540 # 1..1
7859 10:13:06.661703 # 1..1
7860 10:13:06.661832 # 1..1
7861 10:13:06.661949 # 1..1
7862 10:13:06.662065 # 1..1
7863 10:13:06.662180 # 1..1
7864 10:13:06.662296 # 1..1
7865 10:13:06.662411 # 1..1
7866 10:13:06.682425 # 1..1
7867 10:13:06.682814 # 1..1
7868 10:13:06.683030 # 1..1
7869 10:13:06.683236 # 1..1
7870 10:13:06.683413 # 1..1
7871 10:13:06.683572 # 1..1
7872 10:13:06.684024 # 1..1
7873 10:13:06.684201 # 1..1
7874 10:13:06.684365 # 1..1
7875 10:13:06.684514 # 1..1
7876 10:13:06.684635 # 1..1
7877 10:13:06.684749 # 1..1
7878 10:13:06.684863 # 1..1
7879 10:13:06.684977 # 1..1
7880 10:13:06.685091 # 1..1
7881 10:13:06.685206 # 1..1
7882 10:13:06.685321 # 1..1
7883 10:13:06.685449 # 1..1
7884 10:13:06.685599 # 1..1
7885 10:13:06.685745 # 1..1
7886 10:13:06.685919 # 1..1
7887 10:13:06.686066 # 1..1
7888 10:13:06.686208 # 1..1
7889 10:13:06.686349 # 1..1
7890 10:13:06.686490 # 1..1
7891 10:13:06.686629 # 1..1
7892 10:13:06.686769 # 1..1
7893 10:13:06.686909 # 1..1
7894 10:13:06.687048 # 1..1
7895 10:13:06.687187 # 1..1
7896 10:13:06.687327 # 1..1
7897 10:13:06.687466 # 1..1
7898 10:13:06.687609 # 1..1
7899 10:13:06.687749 # 1..1
7900 10:13:06.687888 # 1..1
7901 10:13:06.688027 # 1..1
7902 10:13:06.688167 # 1..1
7903 10:13:06.688307 # 1..1
7904 10:13:06.688448 # 1..1
7905 10:13:06.688589 # 1..1
7906 10:13:06.688728 # 1..1
7907 10:13:06.688867 # 1..1
7908 10:13:06.689006 # 1..1
7909 10:13:06.689144 # 1..1
7910 10:13:06.689282 # 1..1
7911 10:13:06.689422 # 1..1
7912 10:13:06.689566 # 1..1
7913 10:13:06.689722 # 1..1
7914 10:13:06.689866 # 1..1
7915 10:13:06.690007 # 1..1
7916 10:13:06.690148 # 1..1
7917 10:13:06.690290 # 1..1
7918 10:13:06.690429 # 1..1
7919 10:13:06.690571 # 1..1
7920 10:13:06.690711 # 1..1
7921 10:13:06.690851 # 1..1
7922 10:13:06.690992 # 1..1
7923 10:13:06.691174 # 1..1
7924 10:13:06.691313 # 1..1
7925 10:13:06.691456 # 1..1
7926 10:13:06.691599 # 1..1
7927 10:13:06.691742 # 1..1
7928 10:13:06.691883 # 1..1
7929 10:13:06.692025 # 1..1
7930 10:13:06.692166 # 1..1
7931 10:13:06.692307 # 1..1
7932 10:13:06.692446 # 1..1
7933 10:13:06.692588 # 1..1
7934 10:13:06.692728 # 1..1
7935 10:13:06.692868 # 1..1
7936 10:13:06.702990 # 1..1
7937 10:13:06.703126 # 1..1
7938 10:13:06.703222 # 1..1
7939 10:13:06.703514 # 1..1
7940 10:13:06.703619 # 1..1
7941 10:13:06.703707 # 1..1
7942 10:13:06.703794 # 1..1
7943 10:13:06.703879 # 1..1
7944 10:13:06.703966 # 1..1
7945 10:13:06.704051 # 1..1
7946 10:13:06.704136 # 1..1
7947 10:13:06.704221 # 1..1
7948 10:13:06.704304 # 1..1
7949 10:13:06.704386 # 1..1
7950 10:13:06.704469 # 1..1
7951 10:13:06.704558 # 1..1
7952 10:13:06.704645 # 1..1
7953 10:13:06.704728 # 1..1
7954 10:13:06.704812 # 1..1
7955 10:13:06.704898 # 1..1
7956 10:13:06.705004 # 1..1
7957 10:13:06.705093 # 1..1
7958 10:13:06.705176 # 1..1
7959 10:13:06.705260 # 1..1
7960 10:13:06.705344 # 1..1
7961 10:13:06.705428 # 1..1
7962 10:13:06.705517 # 1..1
7963 10:13:06.705600 # 1..1
7964 10:13:06.705691 # 1..1
7965 10:13:06.705775 # 1..1
7966 10:13:06.705858 # 1..1
7967 10:13:06.705941 # 1..1
7968 10:13:06.706023 # 1..1
7969 10:13:06.706105 # 1..1
7970 10:13:06.706188 # 1..1
7971 10:13:06.706272 # 1..1
7972 10:13:06.706356 # 1..1
7973 10:13:06.706440 # 1..1
7974 10:13:06.706522 # 1..1
7975 10:13:06.706605 # 1..1
7976 10:13:06.706687 # 1..1
7977 10:13:06.706771 # 1..1
7978 10:13:06.706855 # 1..1
7979 10:13:06.706937 # 1..1
7980 10:13:06.719124 # 1..1
7981 10:13:06.719272 # 1..1
7982 10:13:06.719360 # 1..1
7983 10:13:06.720103 #
7984 10:13:06.720430 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
7985 10:13:07.142980 # selftests: arm64: check_ksm_options
7986 10:13:07.650467 # 1..4
7987 10:13:07.650706 # # Invalid MTE synchronous exception caught!
7988 10:13:07.730102 not ok 38 selftests: arm64: check_ksm_options # exit=1
7989 10:13:08.251585 # selftests: arm64: check_mmap_options
7990 10:13:09.839622 # 1..22
7991 10:13:09.840577 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
7992 10:13:09.840832 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
7993 10:13:09.840970 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
7994 10:13:09.849679 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
7995 10:13:09.850117 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
7996 10:13:09.850232 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
7997 10:13:09.850548 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
7998 10:13:09.850900 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
7999 10:13:09.851084 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
8000 10:13:09.851263 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8001 10:13:09.851457 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
8002 10:13:09.851819 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8003 10:13:09.852182 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
8004 10:13:09.852570 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8005 10:13:09.914313 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
8006 10:13:09.914893 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8007 10:13:09.915058 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
8008 10:13:09.915444 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8009 10:13:09.915650 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
8010 10:13:09.915858 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8011 10:13:09.916065 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
8012 10:13:09.916215 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
8013 10:13:09.916361 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
8014 10:13:09.991023 not ok 39 selftests: arm64: check_mmap_options # exit=1
8015 10:13:10.606636 # selftests: arm64: check_prctl
8016 10:13:11.203985 # TAP version 13
8017 10:13:11.204287 # 1..5
8018 10:13:11.204445 # ok 1 check_basic_read
8019 10:13:11.204594 # ok 2 NONE
8020 10:13:11.204717 # ok 3 SYNC
8021 10:13:11.204834 # ok 4 ASYNC
8022 10:13:11.205183 # ok 5 SYNC+ASYNC
8023 10:13:11.205321 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8024 10:13:11.279776 ok 40 selftests: arm64: check_prctl
8025 10:13:11.926708 # selftests: arm64: check_tags_inclusion
8026 10:13:12.679528 # 1..4
8027 10:13:12.680019 # # Unexpected fault recorded for 0x700ffff9efeb000-0x700ffff9efeb050 in mode 1
8028 10:13:12.680189 # not ok 1 Check an included tag value with sync mode
8029 10:13:12.680320 # # Unexpected fault recorded for 0xc00ffff9efeb000-0xc00ffff9efeb050 in mode 1
8030 10:13:12.680467 # not ok 2 Check different included tags value with sync mode
8031 10:13:12.680589 # ok 3 Check none included tags value with sync mode
8032 10:13:12.680708 # # Unexpected fault recorded for 0x100ffff9efeb000-0x100ffff9efeb050 in mode 1
8033 10:13:12.699179 # not ok 4 Check all included tags value with sync mode
8034 10:13:12.699688 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
8035 10:13:12.799338 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
8036 10:13:13.299135 # selftests: arm64: check_user_mem
8037 10:13:22.275282 # 1..64
8038 10:13:22.275876 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8039 10:13:22.276084 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8040 10:13:22.276266 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8041 10:13:22.276507 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8042 10:13:22.276685 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8043 10:13:22.276817 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8044 10:13:22.278992 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8045 10:13:22.279445 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8046 10:13:22.279637 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8047 10:13:22.279794 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8048 10:13:22.279997 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8049 10:13:22.280253 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8050 10:13:22.280493 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8051 10:13:22.281814 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8052 10:13:22.282291 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8053 10:13:22.282496 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8054 10:13:22.282696 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8055 10:13:22.282886 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8056 10:13:22.283127 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8057 10:13:22.283328 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8058 10:13:22.283522 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8059 10:13:22.283712 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8060 10:13:22.283899 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8061 10:13:22.284136 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8062 10:13:22.284333 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8063 10:13:22.284526 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8064 10:13:22.284718 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8065 10:13:22.284908 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8066 10:13:22.285096 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8067 10:13:22.285278 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8068 10:13:22.285499 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8069 10:13:22.285710 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8070 10:13:22.285902 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8071 10:13:22.293192 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8072 10:13:22.293744 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8073 10:13:22.293965 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8074 10:13:22.294168 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8075 10:13:22.294399 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8076 10:13:22.294596 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8077 10:13:22.294780 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8078 10:13:22.295035 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8079 10:13:22.295237 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8080 10:13:22.295430 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8081 10:13:22.295622 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8082 10:13:22.295812 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8083 10:13:22.296041 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8084 10:13:22.296231 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8085 10:13:22.296422 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8086 10:13:22.296609 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8087 10:13:22.296799 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8088 10:13:22.297027 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8089 10:13:24.150763 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8090 10:13:24.151073 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8091 10:13:24.151286 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8092 10:13:24.151466 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8093 10:13:24.151650 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8094 10:13:24.151831 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8095 10:13:24.152342 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8096 10:13:24.152510 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8097 10:13:24.152648 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8098 10:13:24.152793 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8099 10:13:24.152916 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8100 10:13:24.158323 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8101 10:13:24.158858 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8102 10:13:24.159037 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
8103 10:13:24.186563 ok 42 selftests: arm64: check_user_mem
8104 10:13:24.396765 # selftests: arm64: btitest
8105 10:13:24.630780 # TAP version 13
8106 10:13:24.631208 # 1..18
8107 10:13:24.631299 # # HWCAP_PACA present
8108 10:13:24.631377 # # HWCAP2_BTI present
8109 10:13:24.631454 # # Test binary built for BTI
8110 10:13:24.631547 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
8111 10:13:24.631630 # ok 1 nohint_func/call_using_br_x0
8112 10:13:24.631706 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
8113 10:13:24.631794 # ok 2 nohint_func/call_using_br_x16
8114 10:13:24.631882 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
8115 10:13:24.632170 # ok 3 nohint_func/call_using_blr
8116 10:13:24.632270 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
8117 10:13:24.632363 # ok 4 bti_none_func/call_using_br_x0
8118 10:13:24.632454 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
8119 10:13:24.636019 # ok 5 bti_none_func/call_using_br_x16
8120 10:13:24.636318 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
8121 10:13:24.636417 # ok 6 bti_none_func/call_using_blr
8122 10:13:24.636526 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
8123 10:13:24.650510 # ok 7 bti_c_func/call_using_br_x0
8124 10:13:24.650819 # ok 8 bti_c_func/call_using_br_x16
8125 10:13:24.650907 # ok 9 bti_c_func/call_using_blr
8126 10:13:24.650985 # ok 10 bti_j_func/call_using_br_x0
8127 10:13:24.651074 # ok 11 bti_j_func/call_using_br_x16
8128 10:13:24.651165 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
8129 10:13:24.651254 # ok 12 bti_j_func/call_using_blr
8130 10:13:24.651348 # ok 13 bti_jc_func/call_using_br_x0
8131 10:13:24.651439 # ok 14 bti_jc_func/call_using_br_x16
8132 10:13:24.651750 # ok 15 bti_jc_func/call_using_blr
8133 10:13:24.651950 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
8134 10:13:24.652154 # ok 16 paciasp_func/call_using_br_x0
8135 10:13:24.652286 # ok 17 paciasp_func/call_using_br_x16
8136 10:13:24.652407 # ok 18 paciasp_func/call_using_blr
8137 10:13:24.652524 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8138 10:13:24.667953 ok 43 selftests: arm64: btitest
8139 10:13:24.924432 # selftests: arm64: nobtitest
8140 10:13:25.139049 # TAP version 13
8141 10:13:25.139381 # 1..18
8142 10:13:25.139560 # # HWCAP_PACA present
8143 10:13:25.139749 # # HWCAP2_BTI present
8144 10:13:25.140148 # # Test binary not built for BTI
8145 10:13:25.140310 # ok 1 nohint_func/call_using_br_x0
8146 10:13:25.140466 # ok 2 nohint_func/call_using_br_x16
8147 10:13:25.140611 # ok 3 nohint_func/call_using_blr
8148 10:13:25.140755 # ok 4 bti_none_func/call_using_br_x0
8149 10:13:25.140898 # ok 5 bti_none_func/call_using_br_x16
8150 10:13:25.141040 # ok 6 bti_none_func/call_using_blr
8151 10:13:25.141182 # ok 7 bti_c_func/call_using_br_x0
8152 10:13:25.141324 # ok 8 bti_c_func/call_using_br_x16
8153 10:13:25.141465 # ok 9 bti_c_func/call_using_blr
8154 10:13:25.141607 # ok 10 bti_j_func/call_using_br_x0
8155 10:13:25.141763 # ok 11 bti_j_func/call_using_br_x16
8156 10:13:25.141908 # ok 12 bti_j_func/call_using_blr
8157 10:13:25.142089 # ok 13 bti_jc_func/call_using_br_x0
8158 10:13:25.142229 # ok 14 bti_jc_func/call_using_br_x16
8159 10:13:25.142371 # ok 15 bti_jc_func/call_using_blr
8160 10:13:25.142512 # ok 16 paciasp_func/call_using_br_x0
8161 10:13:25.150335 # ok 17 paciasp_func/call_using_br_x16
8162 10:13:25.150848 # ok 18 paciasp_func/call_using_blr
8163 10:13:25.151002 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8164 10:13:25.184388 ok 44 selftests: arm64: nobtitest
8165 10:13:25.343852 # selftests: arm64: hwcap
8166 10:13:25.583336 # TAP version 13
8167 10:13:25.583838 # 1..28
8168 10:13:25.584080 # # RNG present
8169 10:13:25.584308 # ok 1 cpuinfo_match_RNG
8170 10:13:25.584524 # ok 2 sigill_RNG
8171 10:13:25.584674 # # SME present
8172 10:13:25.584800 # ok 3 cpuinfo_match_SME
8173 10:13:25.584917 # ok 4 sigill_SME
8174 10:13:25.585061 # # SVE present
8175 10:13:25.585187 # ok 5 cpuinfo_match_SVE
8176 10:13:25.585305 # ok 6 sigill_SVE
8177 10:13:25.585422 # # SVE 2 present
8178 10:13:25.585588 # ok 7 cpuinfo_match_SVE 2
8179 10:13:25.585806 # ok 8 sigill_SVE 2
8180 10:13:25.585941 # # SVE AES present
8181 10:13:25.586059 # ok 9 cpuinfo_match_SVE AES
8182 10:13:25.586177 # ok 10 sigill_SVE AES
8183 10:13:25.586292 # # SVE2 PMULL present
8184 10:13:25.588575 # ok 11 cpuinfo_match_SVE2 PMULL
8185 10:13:25.599328 # ok 12 sigill_SVE2 PMULL
8186 10:13:25.599668 # # SVE2 BITPERM present
8187 10:13:25.600134 # ok 13 cpuinfo_match_SVE2 BITPERM
8188 10:13:25.600345 # ok 14 sigill_SVE2 BITPERM
8189 10:13:25.600523 # # SVE2 SHA3 present
8190 10:13:25.600650 # ok 15 cpuinfo_match_SVE2 SHA3
8191 10:13:25.600767 # ok 16 sigill_SVE2 SHA3
8192 10:13:25.600881 # # SVE2 SM4 present
8193 10:13:25.601230 # ok 17 cpuinfo_match_SVE2 SM4
8194 10:13:25.601391 # ok 18 sigill_SVE2 SM4
8195 10:13:25.601516 # # SVE2 I8MM present
8196 10:13:25.601631 # ok 19 cpuinfo_match_SVE2 I8MM
8197 10:13:25.601762 # ok 20 sigill_SVE2 I8MM
8198 10:13:25.607169 # # SVE2 F32MM present
8199 10:13:25.607744 # ok 21 cpuinfo_match_SVE2 F32MM
8200 10:13:25.607941 # ok 22 sigill_SVE2 F32MM
8201 10:13:25.608150 # # SVE2 F64MM present
8202 10:13:25.608294 # ok 23 cpuinfo_match_SVE2 F64MM
8203 10:13:25.608409 # ok 24 sigill_SVE2 F64MM
8204 10:13:25.608519 # # SVE2 BF16 present
8205 10:13:25.608658 # ok 25 cpuinfo_match_SVE2 BF16
8206 10:13:25.608780 # ok 26 sigill_SVE2 BF16
8207 10:13:25.608894 # ok 27 cpuinfo_match_SVE2 EBF16
8208 10:13:25.609005 # ok 28 # SKIP sigill_SVE2 EBF16
8209 10:13:25.609118 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8210 10:13:25.642564 ok 45 selftests: arm64: hwcap
8211 10:13:25.892166 # selftests: arm64: ptrace
8212 10:13:26.119952 # TAP version 13
8213 10:13:26.120169 # 1..7
8214 10:13:26.120252 # # Parent is 4286, child is 4287
8215 10:13:26.120527 # ok 1 read_tpidr_one
8216 10:13:26.120608 # ok 2 write_tpidr_one
8217 10:13:26.120670 # ok 3 verify_tpidr_one
8218 10:13:26.120729 # ok 4 count_tpidrs
8219 10:13:26.120787 # ok 5 tpidr2_write
8220 10:13:26.120846 # ok 6 tpidr2_read
8221 10:13:26.120904 # ok 7 write_tpidr_only
8222 10:13:26.126076 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8223 10:13:26.155789 ok 46 selftests: arm64: ptrace
8224 10:13:26.323523 # selftests: arm64: syscall-abi
8225 10:13:28.969538 # TAP version 13
8226 10:13:28.970187 # 1..514
8227 10:13:28.970369 # # SME with FA64
8228 10:13:28.970543 # ok 1 getpid() FPSIMD
8229 10:13:28.970691 # ok 2 getpid() SVE VL 256
8230 10:13:28.970830 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8231 10:13:28.970970 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8232 10:13:28.971108 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8233 10:13:28.971280 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8234 10:13:28.971417 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8235 10:13:28.971808 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8236 10:13:28.972001 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8237 10:13:28.972163 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8238 10:13:28.972352 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8239 10:13:28.972557 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8240 10:13:28.972719 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8241 10:13:28.972837 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8242 10:13:28.972957 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8243 10:13:28.973120 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8244 10:13:28.973243 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8245 10:13:28.973353 # ok 18 getpid() SVE VL 240
8246 10:13:28.973462 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8247 10:13:28.973570 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8248 10:13:28.973703 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8249 10:13:28.973814 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8250 10:13:28.973924 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8251 10:13:28.974035 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8252 10:13:28.974177 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8253 10:13:28.974299 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8254 10:13:28.974413 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8255 10:13:28.974525 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8256 10:13:28.974636 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8257 10:13:28.977179 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8258 10:13:28.977661 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8259 10:13:28.977826 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8260 10:13:28.977951 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8261 10:13:28.978067 # ok 34 getpid() SVE VL 224
8262 10:13:28.978206 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8263 10:13:28.978326 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8264 10:13:28.978439 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8265 10:13:28.978552 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8266 10:13:28.978663 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8267 10:13:28.978798 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8268 10:13:28.978915 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8269 10:13:28.979029 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8270 10:13:28.979142 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8271 10:13:28.979275 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8272 10:13:28.979392 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8273 10:13:28.979505 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8274 10:13:28.979616 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8275 10:13:28.979748 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8276 10:13:28.979865 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8277 10:13:28.979997 # ok 50 getpid() SVE VL 208
8278 10:13:28.980114 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8279 10:13:28.980247 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8280 10:13:28.980363 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8281 10:13:28.980495 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8282 10:13:28.980666 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8283 10:13:28.984862 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8284 10:13:28.985247 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8285 10:13:28.985439 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8286 10:13:28.985610 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8287 10:13:28.985769 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8288 10:13:28.985888 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8289 10:13:28.986001 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8290 10:13:28.986111 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8291 10:13:28.986246 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8292 10:13:28.986405 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8293 10:13:28.986573 # ok 66 getpid() SVE VL 192
8294 10:13:28.986719 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8295 10:13:28.986860 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8296 10:13:28.986976 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8297 10:13:28.987090 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8298 10:13:28.987204 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8299 10:13:28.987399 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8300 10:13:28.987531 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8301 10:13:28.987645 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8302 10:13:28.987757 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8303 10:13:28.987867 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8304 10:13:28.988001 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8305 10:13:28.988119 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8306 10:13:28.988231 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8307 10:13:28.988341 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8308 10:13:28.988453 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8309 10:13:28.988585 # ok 82 getpid() SVE VL 176
8310 10:13:28.988700 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8311 10:13:28.988812 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8312 10:13:28.988923 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8313 10:13:28.992890 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8314 10:13:28.993244 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8315 10:13:28.993373 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8316 10:13:28.993507 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8317 10:13:28.993623 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8318 10:13:28.993747 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8319 10:13:28.993882 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8320 10:13:28.994000 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8321 10:13:28.994131 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8322 10:13:28.994248 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8323 10:13:28.994379 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8324 10:13:28.994495 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8325 10:13:28.994625 # ok 98 getpid() SVE VL 160
8326 10:13:31.429691 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8327 10:13:31.429971 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8328 10:13:31.430328 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8329 10:13:31.430455 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8330 10:13:31.430570 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8331 10:13:31.430681 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8332 10:13:31.430793 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8333 10:13:31.430927 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8334 10:13:31.431043 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8335 10:13:31.431154 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8336 10:13:31.431265 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8337 10:13:31.431398 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8338 10:13:31.431513 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8339 10:13:31.431624 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8340 10:13:31.431755 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8341 10:13:31.431870 # ok 114 getpid() SVE VL 144
8342 10:13:31.431980 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8343 10:13:31.432111 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8344 10:13:31.432226 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8345 10:13:31.432335 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8346 10:13:31.432466 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8347 10:13:31.432581 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8348 10:13:31.432710 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8349 10:13:31.437404 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8350 10:13:31.437790 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8351 10:13:31.437998 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8352 10:13:31.438219 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8353 10:13:31.438423 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8354 10:13:31.438596 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8355 10:13:31.438751 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8356 10:13:31.438901 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8357 10:13:31.439045 # ok 130 getpid() SVE VL 128
8358 10:13:31.439202 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8359 10:13:31.439362 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8360 10:13:31.439492 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8361 10:13:31.439615 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8362 10:13:31.439746 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8363 10:13:31.439929 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8364 10:13:31.440091 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8365 10:13:31.440308 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8366 10:13:31.440475 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8367 10:13:31.440605 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8368 10:13:31.440720 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8369 10:13:31.440832 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8370 10:13:31.440944 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8371 10:13:31.441055 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8372 10:13:31.441168 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8373 10:13:31.441279 # ok 146 getpid() SVE VL 112
8374 10:13:31.441392 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8375 10:13:31.441535 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8376 10:13:31.441670 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8377 10:13:31.445191 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8378 10:13:31.445616 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8379 10:13:31.445719 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8380 10:13:31.445820 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8381 10:13:31.445905 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8382 10:13:31.445990 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8383 10:13:31.446089 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8384 10:13:31.446173 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8385 10:13:31.446273 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8386 10:13:31.446375 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8387 10:13:31.446482 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8388 10:13:31.446783 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8389 10:13:31.446883 # ok 162 getpid() SVE VL 96
8390 10:13:31.446988 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8391 10:13:31.447074 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8392 10:13:31.447171 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8393 10:13:31.447270 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8394 10:13:31.447611 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8395 10:13:31.447709 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8396 10:13:31.447810 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8397 10:13:31.447896 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8398 10:13:31.448206 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8399 10:13:31.448304 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8400 10:13:31.448408 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8401 10:13:31.448511 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8402 10:13:31.448797 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8403 10:13:31.448888 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8404 10:13:31.456803 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8405 10:13:31.457162 # ok 178 getpid() SVE VL 80
8406 10:13:31.457256 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8407 10:13:31.457334 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8408 10:13:31.457426 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8409 10:13:31.457494 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8410 10:13:31.457569 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8411 10:13:31.457819 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8412 10:13:31.457889 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8413 10:13:31.457963 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8414 10:13:31.458039 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8415 10:13:31.458121 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8416 10:13:31.458389 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8417 10:13:31.458490 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8418 10:13:31.458588 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8419 10:13:31.458680 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8420 10:13:31.458758 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8421 10:13:31.458840 # ok 194 getpid() SVE VL 64
8422 10:13:31.458928 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8423 10:13:33.674126 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8424 10:13:33.674698 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8425 10:13:33.674940 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8426 10:13:33.675181 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8427 10:13:33.675405 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8428 10:13:33.675600 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8429 10:13:33.675797 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8430 10:13:33.675974 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8431 10:13:33.676141 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8432 10:13:33.676308 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8433 10:13:33.676519 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8434 10:13:33.676676 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8435 10:13:33.676838 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8436 10:13:33.676961 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8437 10:13:33.677077 # ok 210 getpid() SVE VL 48
8438 10:13:33.677249 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8439 10:13:33.677405 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8440 10:13:33.677530 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8441 10:13:33.677686 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8442 10:13:33.677810 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8443 10:13:33.677924 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8444 10:13:33.678038 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8445 10:13:33.678153 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8446 10:13:33.684858 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8447 10:13:33.685291 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8448 10:13:33.685404 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8449 10:13:33.685495 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8450 10:13:33.685585 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8451 10:13:33.685681 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8452 10:13:33.685792 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8453 10:13:33.685879 # ok 226 getpid() SVE VL 32
8454 10:13:33.685962 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8455 10:13:33.686047 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8456 10:13:33.686148 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8457 10:13:33.686235 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8458 10:13:33.686320 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8459 10:13:33.686423 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8460 10:13:33.686509 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8461 10:13:33.686613 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8462 10:13:33.686703 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8463 10:13:33.686790 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8464 10:13:33.686893 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8465 10:13:33.686992 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8466 10:13:33.687089 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8467 10:13:33.687195 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8468 10:13:33.687292 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8469 10:13:33.687389 # ok 242 getpid() SVE VL 16
8470 10:13:33.687673 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8471 10:13:33.687775 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8472 10:13:33.687863 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8473 10:13:33.688345 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8474 10:13:33.688633 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8475 10:13:33.692923 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8476 10:13:33.693225 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8477 10:13:33.693329 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8478 10:13:33.693433 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8479 10:13:33.693522 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8480 10:13:33.693607 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8481 10:13:33.693724 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8482 10:13:33.693815 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8483 10:13:33.693917 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8484 10:13:33.694023 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8485 10:13:33.694129 # ok 258 sched_yield() FPSIMD
8486 10:13:33.694218 # ok 259 sched_yield() SVE VL 256
8487 10:13:33.694319 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8488 10:13:33.694424 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8489 10:13:33.694787 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8490 10:13:33.694992 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8491 10:13:33.695170 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8492 10:13:33.695418 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8493 10:13:33.695618 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8494 10:13:33.695799 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8495 10:13:33.695957 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8496 10:13:33.696109 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8497 10:13:33.696301 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8498 10:13:33.696470 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8499 10:13:33.696607 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8500 10:13:33.696724 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8501 10:13:33.696838 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8502 10:13:33.696953 # ok 275 sched_yield() SVE VL 240
8503 10:13:33.697068 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8504 10:13:33.697181 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8505 10:13:33.697320 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8506 10:13:33.700874 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8507 10:13:33.701275 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8508 10:13:33.701453 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8509 10:13:33.701669 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8510 10:13:33.701814 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8511 10:13:33.701958 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8512 10:13:33.702132 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8513 10:13:33.702268 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8514 10:13:33.702409 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8515 10:13:33.702549 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8516 10:13:33.702719 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8517 10:13:35.691411 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8518 10:13:35.691894 # ok 291 sched_yield() SVE VL 224
8519 10:13:35.692047 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8520 10:13:35.692229 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8521 10:13:35.692365 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8522 10:13:35.692505 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8523 10:13:35.692675 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8524 10:13:35.692807 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8525 10:13:35.692943 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8526 10:13:35.697179 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8527 10:13:35.697370 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8528 10:13:35.697772 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8529 10:13:35.697955 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8530 10:13:35.698162 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8531 10:13:35.698325 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8532 10:13:35.698483 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8533 10:13:35.698668 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8534 10:13:35.698835 # ok 307 sched_yield() SVE VL 208
8535 10:13:35.699036 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8536 10:13:35.699205 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8537 10:13:35.699357 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8538 10:13:35.699554 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8539 10:13:35.699722 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8540 10:13:35.699864 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8541 10:13:35.700006 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8542 10:13:35.700188 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8543 10:13:35.700316 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8544 10:13:35.700484 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8545 10:13:35.700630 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8546 10:13:35.700772 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8547 10:13:35.700888 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8548 10:13:35.700998 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8549 10:13:35.701107 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8550 10:13:35.701216 # ok 323 sched_yield() SVE VL 192
8551 10:13:35.701325 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8552 10:13:35.701434 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8553 10:13:35.701542 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8554 10:13:35.701667 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8555 10:13:35.704779 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8556 10:13:35.705187 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8557 10:13:35.705355 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8558 10:13:35.705481 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8559 10:13:35.705680 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8560 10:13:35.705861 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8561 10:13:35.706110 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8562 10:13:35.706371 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8563 10:13:35.706562 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8564 10:13:35.706721 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8565 10:13:35.706925 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8566 10:13:35.707122 # ok 339 sched_yield() SVE VL 176
8567 10:13:35.707279 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8568 10:13:35.707440 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8569 10:13:35.707617 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8570 10:13:35.707775 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8571 10:13:35.707932 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8572 10:13:35.708162 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8573 10:13:35.708326 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8574 10:13:35.708522 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8575 10:13:35.708712 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8576 10:13:35.708901 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8577 10:13:35.709076 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8578 10:13:35.709224 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8579 10:13:35.709389 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8580 10:13:35.709540 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8581 10:13:35.709694 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8582 10:13:35.709866 # ok 355 sched_yield() SVE VL 160
8583 10:13:35.710047 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8584 10:13:35.710211 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8585 10:13:35.710370 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8586 10:13:35.710515 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8587 10:13:35.712863 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8588 10:13:35.713302 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8589 10:13:35.713490 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8590 10:13:35.713666 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8591 10:13:35.713831 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8592 10:13:35.714022 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8593 10:13:35.714188 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8594 10:13:35.714349 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8595 10:13:35.714505 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8596 10:13:35.714650 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8597 10:13:35.714764 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8598 10:13:35.714901 # ok 371 sched_yield() SVE VL 144
8599 10:13:35.715015 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8600 10:13:35.715125 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8601 10:13:35.715232 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8602 10:13:35.715339 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8603 10:13:35.715448 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8604 10:13:37.767624 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8605 10:13:37.767983 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8606 10:13:37.768172 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8607 10:13:37.768342 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8608 10:13:37.768546 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8609 10:13:37.768718 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8610 10:13:37.768879 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8611 10:13:37.769029 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8612 10:13:37.769178 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8613 10:13:37.769675 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8614 10:13:37.770061 # ok 387 sched_yield() SVE VL 128
8615 10:13:37.770221 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8616 10:13:37.770371 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8617 10:13:37.770546 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8618 10:13:37.770697 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8619 10:13:37.770845 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8620 10:13:37.770990 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8621 10:13:37.771163 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8622 10:13:37.771316 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8623 10:13:37.771464 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8624 10:13:37.771639 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8625 10:13:37.771791 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8626 10:13:37.771939 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8627 10:13:37.772085 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8628 10:13:37.772259 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8629 10:13:37.772406 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8630 10:13:37.772543 # ok 403 sched_yield() SVE VL 112
8631 10:13:37.772677 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8632 10:13:37.772853 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8633 10:13:37.772997 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8634 10:13:37.773162 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8635 10:13:37.773332 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8636 10:13:37.777169 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8637 10:13:37.777609 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8638 10:13:37.777718 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8639 10:13:37.777808 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8640 10:13:37.777893 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8641 10:13:37.777999 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8642 10:13:37.778087 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8643 10:13:37.778188 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8644 10:13:37.778289 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8645 10:13:37.778573 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8646 10:13:37.778668 # ok 419 sched_yield() SVE VL 96
8647 10:13:37.778975 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8648 10:13:37.779077 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8649 10:13:37.779176 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8650 10:13:37.779488 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8651 10:13:37.779589 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8652 10:13:37.779691 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8653 10:13:37.779792 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8654 10:13:37.779894 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8655 10:13:37.780246 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8656 10:13:37.780455 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8657 10:13:37.780645 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8658 10:13:37.780803 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8659 10:13:37.780932 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8660 10:13:37.781054 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8661 10:13:37.781203 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8662 10:13:37.781329 # ok 435 sched_yield() SVE VL 80
8663 10:13:37.781452 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8664 10:13:37.781573 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8665 10:13:37.781708 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8666 10:13:37.781857 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8667 10:13:37.781987 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8668 10:13:37.782110 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8669 10:13:37.782287 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8670 10:13:37.782473 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8671 10:13:37.782643 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8672 10:13:37.782834 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8673 10:13:37.782976 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8674 10:13:37.783144 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8675 10:13:37.783340 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8676 10:13:37.783514 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8677 10:13:37.783636 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8678 10:13:37.783756 # ok 451 sched_yield() SVE VL 64
8679 10:13:37.783901 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8680 10:13:37.784050 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8681 10:13:37.784215 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8682 10:13:37.784356 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8683 10:13:37.784476 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8684 10:13:37.784588 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8685 10:13:37.784701 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8686 10:13:37.784813 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8687 10:13:37.784926 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8688 10:13:37.785037 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8689 10:13:37.785148 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8690 10:13:37.785259 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8691 10:13:38.435899 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8692 10:13:38.436479 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8693 10:13:38.436671 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8694 10:13:38.436811 # ok 467 sched_yield() SVE VL 48
8695 10:13:38.436931 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8696 10:13:38.437046 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8697 10:13:38.437158 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8698 10:13:38.437269 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8699 10:13:38.438394 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8700 10:13:38.438835 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8701 10:13:38.438946 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8702 10:13:38.439038 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8703 10:13:38.439125 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8704 10:13:38.439228 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8705 10:13:38.439315 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8706 10:13:38.439398 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8707 10:13:38.439497 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8708 10:13:38.439582 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8709 10:13:38.439678 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8710 10:13:38.439776 # ok 483 sched_yield() SVE VL 32
8711 10:13:38.440119 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8712 10:13:38.440304 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8713 10:13:38.440494 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8714 10:13:38.440642 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8715 10:13:38.440764 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8716 10:13:38.440879 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8717 10:13:38.446980 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8718 10:13:38.447450 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8719 10:13:38.447656 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8720 10:13:38.447882 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8721 10:13:38.448089 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8722 10:13:38.448271 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8723 10:13:38.448465 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8724 10:13:38.448652 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8725 10:13:38.448801 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8726 10:13:38.448987 # ok 499 sched_yield() SVE VL 16
8727 10:13:38.449162 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8728 10:13:38.449338 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8729 10:13:38.449547 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8730 10:13:38.449794 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8731 10:13:38.449981 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8732 10:13:38.450140 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8733 10:13:38.450272 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8734 10:13:38.450387 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8735 10:13:38.450500 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8736 10:13:38.450630 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8737 10:13:38.450749 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8738 10:13:38.450860 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8739 10:13:38.451001 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8740 10:13:38.451122 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8741 10:13:38.451237 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8742 10:13:38.451350 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8743 10:13:38.451464 ok 47 selftests: arm64: syscall-abi
8744 10:13:38.495476 # selftests: arm64: tpidr2
8745 10:13:38.650071 # TAP version 13
8746 10:13:38.650395 # 1..5
8747 10:13:38.650548 # # PID: 4321
8748 10:13:38.650951 # ok 1 default_value
8749 10:13:38.651119 # ok 2 write_read
8750 10:13:38.651253 # ok 3 write_sleep_read
8751 10:13:38.651376 # ok 4 write_fork_read
8752 10:13:38.651495 # ok 5 write_clone_read
8753 10:13:38.651615 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8754 10:13:38.661964 ok 48 selftests: arm64: tpidr2
8755 10:13:39.151360 arm64_tags_test pass
8756 10:13:39.151696 arm64_run_tags_test_sh pass
8757 10:13:39.151859 arm64_fake_sigreturn_bad_magic pass
8758 10:13:39.152028 arm64_fake_sigreturn_bad_size pass
8759 10:13:39.152191 arm64_fake_sigreturn_bad_size_for_magic0 pass
8760 10:13:39.152345 arm64_fake_sigreturn_duplicated_fpsimd pass
8761 10:13:39.152498 arm64_fake_sigreturn_misaligned_sp pass
8762 10:13:39.152632 arm64_fake_sigreturn_missing_fpsimd pass
8763 10:13:39.152789 arm64_fake_sigreturn_sme_change_vl pass
8764 10:13:39.152947 arm64_fake_sigreturn_sve_change_vl pass
8765 10:13:39.153459 arm64_mangle_pstate_invalid_compat_toggle pass
8766 10:13:39.153660 arm64_mangle_pstate_invalid_daif_bits pass
8767 10:13:39.153820 arm64_mangle_pstate_invalid_mode_el1h pass
8768 10:13:39.153949 arm64_mangle_pstate_invalid_mode_el1t pass
8769 10:13:39.154103 arm64_mangle_pstate_invalid_mode_el2h pass
8770 10:13:39.154254 arm64_mangle_pstate_invalid_mode_el2t pass
8771 10:13:39.154408 arm64_mangle_pstate_invalid_mode_el3h pass
8772 10:13:39.154563 arm64_mangle_pstate_invalid_mode_el3t pass
8773 10:13:39.154727 arm64_sme_trap_no_sm pass
8774 10:13:39.154898 arm64_sme_trap_non_streaming skip
8775 10:13:39.155043 arm64_sme_trap_za pass
8776 10:13:39.155185 arm64_sme_vl pass
8777 10:13:39.155325 arm64_ssve_regs pass
8778 10:13:39.155465 arm64_sve_regs pass
8779 10:13:39.155605 arm64_sve_vl pass
8780 10:13:39.155744 arm64_za_no_regs pass
8781 10:13:39.155881 arm64_za_regs pass
8782 10:13:39.156020 arm64_pac_global_corrupt_pac pass
8783 10:13:39.156180 arm64_pac_global_pac_instructions_not_nop pass
8784 10:13:39.156369 arm64_pac_global_pac_instructions_not_nop_generic pass
8785 10:13:39.156575 arm64_pac_global_single_thread_different_keys pass
8786 10:13:39.156757 arm64_pac_global_exec_changed_keys pass
8787 10:13:39.156972 arm64_pac_global_context_switch_keep_keys pass
8788 10:13:39.157153 arm64_pac_global_context_switch_keep_keys_generic pass
8789 10:13:39.157319 arm64_pac pass
8790 10:13:39.157482 arm64_fp-stress_FPSIMD-0-0 pass
8791 10:13:39.157657 arm64_fp-stress_SVE-VL-256-0 pass
8792 10:13:39.157828 arm64_fp-stress_SVE-VL-240-0 pass
8793 10:13:39.157996 arm64_fp-stress_SVE-VL-224-0 pass
8794 10:13:39.158136 arm64_fp-stress_SVE-VL-208-0 pass
8795 10:13:39.158267 arm64_fp-stress_SVE-VL-192-0 pass
8796 10:13:39.158396 arm64_fp-stress_SVE-VL-176-0 pass
8797 10:13:39.158525 arm64_fp-stress_SVE-VL-160-0 pass
8798 10:13:39.158654 arm64_fp-stress_SVE-VL-144-0 pass
8799 10:13:39.158782 arm64_fp-stress_SVE-VL-128-0 pass
8800 10:13:39.158908 arm64_fp-stress_SVE-VL-112-0 pass
8801 10:13:39.159054 arm64_fp-stress_SVE-VL-96-0 pass
8802 10:13:39.159203 arm64_fp-stress_SVE-VL-80-0 pass
8803 10:13:39.159349 arm64_fp-stress_SVE-VL-64-0 pass
8804 10:13:39.159497 arm64_fp-stress_SVE-VL-48-0 pass
8805 10:13:39.159644 arm64_fp-stress_SVE-VL-32-0 pass
8806 10:13:39.159794 arm64_fp-stress_SVE-VL-16-0 pass
8807 10:13:39.159944 arm64_fp-stress_SSVE-VL-256-0 pass
8808 10:13:39.160095 arm64_fp-stress_ZA-VL-256-0 pass
8809 10:13:39.160244 arm64_fp-stress_SSVE-VL-128-0 pass
8810 10:13:39.160391 arm64_fp-stress_ZA-VL-128-0 pass
8811 10:13:39.160540 arm64_fp-stress_SSVE-VL-64-0 pass
8812 10:13:39.160687 arm64_fp-stress_ZA-VL-64-0 pass
8813 10:13:39.160833 arm64_fp-stress_SSVE-VL-32-0 pass
8814 10:13:39.160973 arm64_fp-stress_ZA-VL-32-0 pass
8815 10:13:39.161100 arm64_fp-stress_SSVE-VL-16-0 pass
8816 10:13:39.161181 arm64_fp-stress_ZA-VL-16-0 pass
8817 10:13:39.161261 arm64_fp-stress pass
8818 10:13:39.161342 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8819 10:13:39.161628 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8820 10:13:39.161739 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8821 10:13:39.161827 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8822 10:13:39.161911 arm64_sve-ptrace_Set_SVE_VL_16 pass
8823 10:13:39.161994 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8824 10:13:39.162081 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8825 10:13:39.162162 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8826 10:13:39.162244 arm64_sve-ptrace_Set_SVE_VL_32 pass
8827 10:13:39.162346 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8828 10:13:39.162429 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8829 10:13:39.162510 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8830 10:13:39.162591 arm64_sve-ptrace_Set_SVE_VL_48 pass
8831 10:13:39.162671 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8832 10:13:39.162769 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8833 10:13:39.162850 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8834 10:13:39.162945 arm64_sve-ptrace_Set_SVE_VL_64 pass
8835 10:13:39.163027 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8836 10:13:39.163124 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8837 10:13:39.163414 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8838 10:13:39.163505 arm64_sve-ptrace_Set_SVE_VL_80 pass
8839 10:13:39.163588 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8840 10:13:39.163848 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8841 10:13:39.163932 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8842 10:13:39.164027 arm64_sve-ptrace_Set_SVE_VL_96 pass
8843 10:13:39.164116 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8844 10:13:39.164204 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8845 10:13:39.164284 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8846 10:13:39.164372 arm64_sve-ptrace_Set_SVE_VL_112 pass
8847 10:13:39.164479 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8848 10:13:39.168641 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8849 10:13:39.168973 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8850 10:13:39.169087 arm64_sve-ptrace_Set_SVE_VL_128 pass
8851 10:13:39.169188 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8852 10:13:39.169288 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8853 10:13:39.169374 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8854 10:13:39.169465 arm64_sve-ptrace_Set_SVE_VL_144 pass
8855 10:13:39.169547 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8856 10:13:39.169830 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8857 10:13:39.169913 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8858 10:13:39.169991 arm64_sve-ptrace_Set_SVE_VL_160 pass
8859 10:13:39.170067 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8860 10:13:39.170143 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8861 10:13:39.170455 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8862 10:13:39.170647 arm64_sve-ptrace_Set_SVE_VL_176 pass
8863 10:13:39.170843 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8864 10:13:39.171007 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8865 10:13:39.171170 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8866 10:13:39.171327 arm64_sve-ptrace_Set_SVE_VL_192 pass
8867 10:13:39.171484 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8868 10:13:39.171672 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8869 10:13:39.171833 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8870 10:13:39.171975 arm64_sve-ptrace_Set_SVE_VL_208 pass
8871 10:13:39.172128 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8872 10:13:39.172281 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8873 10:13:39.172464 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8874 10:13:39.172608 arm64_sve-ptrace_Set_SVE_VL_224 pass
8875 10:13:39.172785 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8876 10:13:39.172920 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8877 10:13:39.173061 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8878 10:13:39.173200 arm64_sve-ptrace_Set_SVE_VL_240 pass
8879 10:13:39.173337 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8880 10:13:39.173473 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8881 10:13:39.176621 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8882 10:13:39.177026 arm64_sve-ptrace_Set_SVE_VL_256 pass
8883 10:13:39.177206 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8884 10:13:39.177365 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8885 10:13:39.177552 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8886 10:13:39.177724 arm64_sve-ptrace_Set_SVE_VL_272 pass
8887 10:13:39.177879 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8888 10:13:39.178025 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8889 10:13:39.178186 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8890 10:13:39.178337 arm64_sve-ptrace_Set_SVE_VL_288 pass
8891 10:13:39.178501 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8892 10:13:39.178652 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8893 10:13:39.178788 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8894 10:13:39.178922 arm64_sve-ptrace_Set_SVE_VL_304 pass
8895 10:13:39.179092 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8896 10:13:39.179215 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8897 10:13:39.179354 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8898 10:13:39.179487 arm64_sve-ptrace_Set_SVE_VL_320 pass
8899 10:13:39.179640 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8900 10:13:39.179779 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8901 10:13:39.179933 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8902 10:13:39.180076 arm64_sve-ptrace_Set_SVE_VL_336 pass
8903 10:13:39.180266 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8904 10:13:39.180408 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8905 10:13:39.180535 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8906 10:13:39.180649 arm64_sve-ptrace_Set_SVE_VL_352 pass
8907 10:13:39.180760 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8908 10:13:39.180872 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8909 10:13:39.180983 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8910 10:13:39.181095 arm64_sve-ptrace_Set_SVE_VL_368 pass
8911 10:13:39.181206 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8912 10:13:39.181317 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8913 10:13:39.181427 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8914 10:13:39.181538 arm64_sve-ptrace_Set_SVE_VL_384 pass
8915 10:13:39.181715 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8916 10:13:39.184686 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8917 10:13:39.185065 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8918 10:13:39.185214 arm64_sve-ptrace_Set_SVE_VL_400 pass
8919 10:13:39.185356 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8920 10:13:39.185496 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8921 10:13:39.185681 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8922 10:13:39.185815 arm64_sve-ptrace_Set_SVE_VL_416 pass
8923 10:13:39.185955 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8924 10:13:39.186093 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8925 10:13:39.186231 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8926 10:13:39.186368 arm64_sve-ptrace_Set_SVE_VL_432 pass
8927 10:13:39.186540 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
8928 10:13:39.186672 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
8929 10:13:39.186809 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
8930 10:13:39.186946 arm64_sve-ptrace_Set_SVE_VL_448 pass
8931 10:13:39.187082 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
8932 10:13:39.187222 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
8933 10:13:39.201605 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
8934 10:13:39.202031 arm64_sve-ptrace_Set_SVE_VL_464 pass
8935 10:13:39.202234 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
8936 10:13:39.202405 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
8937 10:13:39.202621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
8938 10:13:39.202826 arm64_sve-ptrace_Set_SVE_VL_480 pass
8939 10:13:39.203033 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
8940 10:13:39.203208 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
8941 10:13:39.203369 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
8942 10:13:39.203531 arm64_sve-ptrace_Set_SVE_VL_496 pass
8943 10:13:39.203737 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
8944 10:13:39.203953 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
8945 10:13:39.204130 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
8946 10:13:39.204294 arm64_sve-ptrace_Set_SVE_VL_512 pass
8947 10:13:39.204486 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
8948 10:13:39.204612 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
8949 10:13:39.204726 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
8950 10:13:39.204838 arm64_sve-ptrace_Set_SVE_VL_528 pass
8951 10:13:39.204948 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
8952 10:13:39.205057 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
8953 10:13:39.205171 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
8954 10:13:39.205281 arm64_sve-ptrace_Set_SVE_VL_544 pass
8955 10:13:39.205392 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
8956 10:13:39.205503 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
8957 10:13:39.205614 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
8958 10:13:39.205814 arm64_sve-ptrace_Set_SVE_VL_560 pass
8959 10:13:39.208666 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
8960 10:13:39.209085 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
8961 10:13:39.209266 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
8962 10:13:39.209439 arm64_sve-ptrace_Set_SVE_VL_576 pass
8963 10:13:39.209563 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
8964 10:13:39.209699 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
8965 10:13:39.209871 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
8966 10:13:39.210112 arm64_sve-ptrace_Set_SVE_VL_592 pass
8967 10:13:39.210291 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
8968 10:13:39.210461 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
8969 10:13:39.210608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
8970 10:13:39.210739 arm64_sve-ptrace_Set_SVE_VL_608 pass
8971 10:13:39.210918 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
8972 10:13:39.211130 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
8973 10:13:39.211299 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
8974 10:13:39.211434 arm64_sve-ptrace_Set_SVE_VL_624 pass
8975 10:13:39.211558 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
8976 10:13:39.211697 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
8977 10:13:39.211870 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
8978 10:13:39.212058 arm64_sve-ptrace_Set_SVE_VL_640 pass
8979 10:13:39.212261 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
8980 10:13:39.212483 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
8981 10:13:39.212632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
8982 10:13:39.212774 arm64_sve-ptrace_Set_SVE_VL_656 pass
8983 10:13:39.212889 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
8984 10:13:39.212998 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
8985 10:13:39.213106 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
8986 10:13:39.213216 arm64_sve-ptrace_Set_SVE_VL_672 pass
8987 10:13:39.213325 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
8988 10:13:39.213432 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
8989 10:13:39.213540 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
8990 10:13:39.213677 arm64_sve-ptrace_Set_SVE_VL_688 pass
8991 10:13:39.216694 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
8992 10:13:39.217109 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
8993 10:13:39.217308 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
8994 10:13:39.217480 arm64_sve-ptrace_Set_SVE_VL_704 pass
8995 10:13:39.217637 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
8996 10:13:39.217841 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
8997 10:13:39.217997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
8998 10:13:39.218137 arm64_sve-ptrace_Set_SVE_VL_720 pass
8999 10:13:39.218282 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
9000 10:13:39.218473 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
9001 10:13:39.218688 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
9002 10:13:39.218876 arm64_sve-ptrace_Set_SVE_VL_736 pass
9003 10:13:39.219054 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
9004 10:13:39.219222 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
9005 10:13:39.219373 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
9006 10:13:39.219524 arm64_sve-ptrace_Set_SVE_VL_752 pass
9007 10:13:39.219661 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
9008 10:13:39.219798 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
9009 10:13:39.219982 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
9010 10:13:39.220125 arm64_sve-ptrace_Set_SVE_VL_768 pass
9011 10:13:39.220269 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
9012 10:13:39.220451 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
9013 10:13:39.220599 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
9014 10:13:39.220714 arm64_sve-ptrace_Set_SVE_VL_784 pass
9015 10:13:39.220827 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
9016 10:13:39.220953 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
9017 10:13:39.221067 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
9018 10:13:39.221180 arm64_sve-ptrace_Set_SVE_VL_800 pass
9019 10:13:39.221319 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
9020 10:13:39.221438 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
9021 10:13:39.221553 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
9022 10:13:39.221711 arm64_sve-ptrace_Set_SVE_VL_816 pass
9023 10:13:39.221918 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
9024 10:13:39.224689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
9025 10:13:39.225032 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
9026 10:13:39.225133 arm64_sve-ptrace_Set_SVE_VL_832 pass
9027 10:13:39.225220 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
9028 10:13:39.225319 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
9029 10:13:39.225403 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
9030 10:13:39.225500 arm64_sve-ptrace_Set_SVE_VL_848 pass
9031 10:13:39.225582 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
9032 10:13:39.225881 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
9033 10:13:39.225980 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
9034 10:13:39.226077 arm64_sve-ptrace_Set_SVE_VL_864 pass
9035 10:13:39.226176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
9036 10:13:39.226470 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
9037 10:13:39.226569 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
9038 10:13:39.226668 arm64_sve-ptrace_Set_SVE_VL_880 pass
9039 10:13:39.226765 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
9040 10:13:39.227059 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
9041 10:13:39.227158 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
9042 10:13:39.227255 arm64_sve-ptrace_Set_SVE_VL_896 pass
9043 10:13:39.227349 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
9044 10:13:39.227444 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
9045 10:13:39.227622 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
9046 10:13:39.227812 arm64_sve-ptrace_Set_SVE_VL_912 pass
9047 10:13:39.227947 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
9048 10:13:39.228097 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
9049 10:13:39.228231 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
9050 10:13:39.228382 arm64_sve-ptrace_Set_SVE_VL_928 pass
9051 10:13:39.228509 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
9052 10:13:39.228653 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
9053 10:13:39.232674 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
9054 10:13:39.233095 arm64_sve-ptrace_Set_SVE_VL_944 pass
9055 10:13:39.233267 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
9056 10:13:39.233443 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
9057 10:13:39.233656 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
9058 10:13:39.233838 arm64_sve-ptrace_Set_SVE_VL_960 pass
9059 10:13:39.234057 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
9060 10:13:39.234233 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
9061 10:13:39.234414 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
9062 10:13:39.234582 arm64_sve-ptrace_Set_SVE_VL_976 pass
9063 10:13:39.234750 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
9064 10:13:39.234897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
9065 10:13:39.235101 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
9066 10:13:39.235293 arm64_sve-ptrace_Set_SVE_VL_992 pass
9067 10:13:39.235482 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
9068 10:13:39.235713 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
9069 10:13:39.235902 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
9070 10:13:39.236108 arm64_sve-ptrace_Set_SVE_VL_1008 pass
9071 10:13:39.236295 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
9072 10:13:39.236477 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
9073 10:13:39.236636 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
9074 10:13:39.236803 arm64_sve-ptrace_Set_SVE_VL_1024 pass
9075 10:13:39.236944 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
9076 10:13:39.237083 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
9077 10:13:39.237260 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
9078 10:13:39.237394 arm64_sve-ptrace_Set_SVE_VL_1040 pass
9079 10:13:39.237533 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
9080 10:13:39.237683 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
9081 10:13:39.237825 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
9082 10:13:39.237967 arm64_sve-ptrace_Set_SVE_VL_1056 pass
9083 10:13:39.240649 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
9084 10:13:39.240947 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
9085 10:13:39.241080 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
9086 10:13:39.241420 arm64_sve-ptrace_Set_SVE_VL_1072 pass
9087 10:13:39.241618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
9088 10:13:39.241816 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
9089 10:13:39.242038 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
9090 10:13:39.242193 arm64_sve-ptrace_Set_SVE_VL_1088 pass
9091 10:13:39.242322 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
9092 10:13:39.242437 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
9093 10:13:39.242573 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
9094 10:13:39.242689 arm64_sve-ptrace_Set_SVE_VL_1104 pass
9095 10:13:39.251630 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
9096 10:13:39.251999 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
9097 10:13:39.252221 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
9098 10:13:39.252429 arm64_sve-ptrace_Set_SVE_VL_1120 pass
9099 10:13:39.252601 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
9100 10:13:39.252756 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
9101 10:13:39.252908 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
9102 10:13:39.253092 arm64_sve-ptrace_Set_SVE_VL_1136 pass
9103 10:13:39.253282 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
9104 10:13:39.253446 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
9105 10:13:39.253609 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
9106 10:13:39.253774 arm64_sve-ptrace_Set_SVE_VL_1152 pass
9107 10:13:39.253924 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
9108 10:13:39.254094 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
9109 10:13:39.254246 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
9110 10:13:39.254406 arm64_sve-ptrace_Set_SVE_VL_1168 pass
9111 10:13:39.254598 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
9112 10:13:39.254770 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
9113 10:13:39.254926 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
9114 10:13:39.255158 arm64_sve-ptrace_Set_SVE_VL_1184 pass
9115 10:13:39.255325 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
9116 10:13:39.255464 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
9117 10:13:39.255604 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
9118 10:13:39.255763 arm64_sve-ptrace_Set_SVE_VL_1200 pass
9119 10:13:39.255948 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
9120 10:13:39.256175 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
9121 10:13:39.256387 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
9122 10:13:39.256580 arm64_sve-ptrace_Set_SVE_VL_1216 pass
9123 10:13:39.256737 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
9124 10:13:39.256894 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
9125 10:13:39.257016 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
9126 10:13:39.257131 arm64_sve-ptrace_Set_SVE_VL_1232 pass
9127 10:13:39.257246 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
9128 10:13:39.257360 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
9129 10:13:39.257473 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
9130 10:13:39.257586 arm64_sve-ptrace_Set_SVE_VL_1248 pass
9131 10:13:39.257780 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
9132 10:13:39.257981 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
9133 10:13:39.258162 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
9134 10:13:39.258581 arm64_sve-ptrace_Set_SVE_VL_1264 pass
9135 10:13:39.260732 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
9136 10:13:39.261128 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
9137 10:13:39.261315 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
9138 10:13:39.261474 arm64_sve-ptrace_Set_SVE_VL_1280 pass
9139 10:13:39.261682 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
9140 10:13:39.261882 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
9141 10:13:39.262070 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
9142 10:13:39.262233 arm64_sve-ptrace_Set_SVE_VL_1296 pass
9143 10:13:39.262380 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
9144 10:13:39.262543 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
9145 10:13:39.262726 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
9146 10:13:39.262943 arm64_sve-ptrace_Set_SVE_VL_1312 pass
9147 10:13:39.263116 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
9148 10:13:39.263284 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
9149 10:13:39.263448 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
9150 10:13:39.263605 arm64_sve-ptrace_Set_SVE_VL_1328 pass
9151 10:13:39.263761 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
9152 10:13:39.263917 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
9153 10:13:39.264071 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
9154 10:13:39.264321 arm64_sve-ptrace_Set_SVE_VL_1344 pass
9155 10:13:39.264538 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
9156 10:13:39.264666 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
9157 10:13:39.264783 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
9158 10:13:39.264897 arm64_sve-ptrace_Set_SVE_VL_1360 pass
9159 10:13:39.265012 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
9160 10:13:39.265124 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
9161 10:13:39.265239 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
9162 10:13:39.265355 arm64_sve-ptrace_Set_SVE_VL_1376 pass
9163 10:13:39.265470 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
9164 10:13:39.265583 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
9165 10:13:39.265708 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
9166 10:13:39.265822 arm64_sve-ptrace_Set_SVE_VL_1392 pass
9167 10:13:39.265936 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
9168 10:13:39.268691 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
9169 10:13:39.269074 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
9170 10:13:39.269253 arm64_sve-ptrace_Set_SVE_VL_1408 pass
9171 10:13:39.269414 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
9172 10:13:39.269595 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9173 10:13:39.269789 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9174 10:13:39.269972 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9175 10:13:39.270184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9176 10:13:39.270434 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9177 10:13:39.270603 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9178 10:13:39.270804 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9179 10:13:39.271034 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9180 10:13:39.271240 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9181 10:13:39.271431 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9182 10:13:39.271608 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9183 10:13:39.271813 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9184 10:13:39.272016 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9185 10:13:39.272179 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9186 10:13:39.272327 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9187 10:13:39.272517 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9188 10:13:39.272666 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9189 10:13:39.272781 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9190 10:13:39.272893 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9191 10:13:39.273004 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9192 10:13:39.273116 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9193 10:13:39.273256 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9194 10:13:39.273378 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9195 10:13:39.273491 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9196 10:13:39.273603 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9197 10:13:39.273808 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9198 10:13:39.274000 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9199 10:13:39.276712 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9200 10:13:39.276885 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9201 10:13:39.277264 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9202 10:13:39.277371 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9203 10:13:39.277456 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9204 10:13:39.277553 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9205 10:13:39.277638 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9206 10:13:39.277726 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9207 10:13:39.277823 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9208 10:13:39.278104 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9209 10:13:39.278204 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9210 10:13:39.278308 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9211 10:13:39.278403 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9212 10:13:39.278732 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9213 10:13:39.278895 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9214 10:13:39.279125 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9215 10:13:39.279308 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9216 10:13:39.279512 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9217 10:13:39.279766 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9218 10:13:39.279946 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9219 10:13:39.280155 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9220 10:13:39.280356 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9221 10:13:39.280554 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9222 10:13:39.280761 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9223 10:13:39.280899 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9224 10:13:39.281040 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9225 10:13:39.281181 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9226 10:13:39.281320 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9227 10:13:39.284646 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9228 10:13:39.285008 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9229 10:13:39.285175 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9230 10:13:39.285327 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9231 10:13:39.285458 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9232 10:13:39.285583 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9233 10:13:39.285692 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9234 10:13:39.285804 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9235 10:13:39.285917 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9236 10:13:39.286036 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9237 10:13:39.286157 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9238 10:13:39.286254 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9239 10:13:39.286355 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9240 10:13:39.286665 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9241 10:13:39.286808 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9242 10:13:39.286928 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9243 10:13:39.287051 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9244 10:13:39.287190 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9245 10:13:39.287298 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9246 10:13:39.287403 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9247 10:13:39.287519 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9248 10:13:39.287663 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9249 10:13:39.287825 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9250 10:13:39.287952 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9251 10:13:39.288079 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9252 10:13:39.288196 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9253 10:13:39.288348 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9254 10:13:39.288469 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9255 10:13:39.301141 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9256 10:13:39.301485 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9257 10:13:39.301621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9258 10:13:39.301752 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9259 10:13:39.301899 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9260 10:13:39.302029 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9261 10:13:39.302176 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9262 10:13:39.302352 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9263 10:13:39.302513 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9264 10:13:39.302649 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9265 10:13:39.302810 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9266 10:13:39.302944 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9267 10:13:39.303071 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9268 10:13:39.303199 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9269 10:13:39.303322 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9270 10:13:39.303451 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9271 10:13:39.303576 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9272 10:13:39.303741 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9273 10:13:39.303879 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9274 10:13:39.303997 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9275 10:13:39.304134 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9276 10:13:39.304283 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9277 10:13:39.304406 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9278 10:13:39.304570 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9279 10:13:39.304680 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9280 10:13:39.308670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9281 10:13:39.309034 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9282 10:13:39.309173 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9283 10:13:39.309314 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9284 10:13:39.309471 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9285 10:13:39.309576 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9286 10:13:39.309717 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9287 10:13:39.309857 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9288 10:13:39.310036 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9289 10:13:39.310173 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9290 10:13:39.310298 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9291 10:13:39.310410 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9292 10:13:39.310581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9293 10:13:39.310715 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9294 10:13:39.310831 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9295 10:13:39.310936 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9296 10:13:39.311087 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9297 10:13:39.311216 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9298 10:13:39.311326 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9299 10:13:39.311482 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9300 10:13:39.311626 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9301 10:13:39.311776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9302 10:13:39.311915 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9303 10:13:39.312045 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9304 10:13:39.312182 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9305 10:13:39.312310 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9306 10:13:39.312789 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9307 10:13:39.312908 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9308 10:13:39.313016 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9309 10:13:39.313122 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9310 10:13:39.313227 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9311 10:13:39.316660 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9312 10:13:39.317049 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9313 10:13:39.317190 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9314 10:13:39.317381 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9315 10:13:39.317644 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9316 10:13:39.317857 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9317 10:13:39.318061 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9318 10:13:39.318284 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9319 10:13:39.318469 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9320 10:13:39.318651 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9321 10:13:39.318843 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9322 10:13:39.319025 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9323 10:13:39.319233 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9324 10:13:39.319456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9325 10:13:39.319651 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9326 10:13:39.319842 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9327 10:13:39.320049 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9328 10:13:39.320231 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9329 10:13:39.320385 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9330 10:13:39.320571 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9331 10:13:39.320729 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9332 10:13:39.320855 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9333 10:13:39.320998 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9334 10:13:39.321118 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9335 10:13:39.321233 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9336 10:13:39.321345 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9337 10:13:39.321458 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9338 10:13:39.321569 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9339 10:13:39.321738 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9340 10:13:39.321941 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9341 10:13:39.324664 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9342 10:13:39.325029 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9343 10:13:39.325163 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9344 10:13:39.325282 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9345 10:13:39.325403 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9346 10:13:39.325523 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9347 10:13:39.325669 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9348 10:13:39.325836 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9349 10:13:39.325993 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9350 10:13:39.326148 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9351 10:13:39.326299 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9352 10:13:39.326425 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9353 10:13:39.326535 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9354 10:13:39.326675 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9355 10:13:39.326815 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9356 10:13:39.326943 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9357 10:13:39.327105 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9358 10:13:39.327232 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9359 10:13:39.327370 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9360 10:13:39.327521 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9361 10:13:39.327682 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9362 10:13:39.327819 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9363 10:13:39.327928 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9364 10:13:39.328032 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9365 10:13:39.328148 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9366 10:13:39.328246 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9367 10:13:39.328340 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9368 10:13:39.328441 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9369 10:13:39.328596 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9370 10:13:39.328698 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9371 10:13:39.332678 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9372 10:13:39.332947 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9373 10:13:39.333108 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9374 10:13:39.333205 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9375 10:13:39.333307 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9376 10:13:39.333417 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9377 10:13:39.333525 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9378 10:13:39.333641 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9379 10:13:39.333778 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9380 10:13:39.333870 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9381 10:13:39.333980 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9382 10:13:39.334128 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9383 10:13:39.334253 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9384 10:13:39.334373 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9385 10:13:39.334508 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9386 10:13:39.334631 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9387 10:13:39.334749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9388 10:13:39.334886 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9389 10:13:39.335004 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9390 10:13:39.335114 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9391 10:13:39.335219 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9392 10:13:39.335309 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9393 10:13:39.335403 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9394 10:13:39.335512 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9395 10:13:39.335601 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9396 10:13:39.335692 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9397 10:13:39.335811 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9398 10:13:39.335928 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9399 10:13:39.336044 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9400 10:13:39.336180 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9401 10:13:39.336299 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9402 10:13:39.336418 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9403 10:13:39.336534 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9404 10:13:39.336624 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9405 10:13:39.336709 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9406 10:13:39.340734 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9407 10:13:39.341053 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9408 10:13:39.341170 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9409 10:13:39.341308 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9410 10:13:39.341432 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9411 10:13:39.341532 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9412 10:13:39.341718 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9413 10:13:39.341832 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9414 10:13:39.341939 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9415 10:13:39.350494 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9416 10:13:39.350908 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9417 10:13:39.351080 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9418 10:13:39.351222 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9419 10:13:39.351376 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9420 10:13:39.351530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9421 10:13:39.351713 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9422 10:13:39.351866 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9423 10:13:39.352023 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9424 10:13:39.352172 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9425 10:13:39.352326 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9426 10:13:39.352466 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9427 10:13:39.352603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9428 10:13:39.352793 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9429 10:13:39.352947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9430 10:13:39.353102 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9431 10:13:39.353257 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9432 10:13:39.353411 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9433 10:13:39.353589 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9434 10:13:39.353794 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9435 10:13:39.353955 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9436 10:13:39.354158 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9437 10:13:39.354399 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9438 10:13:39.354549 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9439 10:13:39.354733 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9440 10:13:39.354897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9441 10:13:39.355051 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9442 10:13:39.355206 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9443 10:13:39.355363 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9444 10:13:39.355518 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9445 10:13:39.355666 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9446 10:13:39.355818 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9447 10:13:39.355970 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9448 10:13:39.356125 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9449 10:13:39.356278 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9450 10:13:39.356454 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9451 10:13:39.356656 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9452 10:13:39.356783 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9453 10:13:39.356897 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9454 10:13:39.357205 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9455 10:13:39.357283 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9456 10:13:39.357343 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9457 10:13:39.357403 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9458 10:13:39.357465 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9459 10:13:39.357523 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9460 10:13:39.357580 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9461 10:13:39.357638 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9462 10:13:39.357705 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9463 10:13:39.357763 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9464 10:13:39.357820 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9465 10:13:39.357877 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9466 10:13:39.357934 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9467 10:13:39.357991 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9468 10:13:39.360646 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9469 10:13:39.360966 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9470 10:13:39.361067 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9471 10:13:39.361163 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9472 10:13:39.361243 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9473 10:13:39.361333 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9474 10:13:39.361421 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9475 10:13:39.361638 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9476 10:13:39.361825 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9477 10:13:39.362021 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9478 10:13:39.362219 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9479 10:13:39.362389 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9480 10:13:39.362599 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9481 10:13:39.362801 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9482 10:13:39.363050 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9483 10:13:39.363248 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9484 10:13:39.363464 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9485 10:13:39.363675 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9486 10:13:39.363857 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9487 10:13:39.364016 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9488 10:13:39.364200 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9489 10:13:39.364358 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9490 10:13:39.364489 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9491 10:13:39.364602 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9492 10:13:39.364712 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9493 10:13:39.364824 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9494 10:13:39.364932 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9495 10:13:39.365041 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9496 10:13:39.365153 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9497 10:13:39.365261 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9498 10:13:39.365394 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9499 10:13:39.365513 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9500 10:13:39.365624 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9501 10:13:39.369057 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9502 10:13:39.369256 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9503 10:13:39.369424 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9504 10:13:39.369530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9505 10:13:39.369823 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9506 10:13:39.369913 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9507 10:13:39.370009 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9508 10:13:39.370104 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9509 10:13:39.370421 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9510 10:13:39.370615 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9511 10:13:39.370807 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9512 10:13:39.370971 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9513 10:13:39.371126 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9514 10:13:39.371309 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9515 10:13:39.371470 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9516 10:13:39.371625 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9517 10:13:39.371780 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9518 10:13:39.371964 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9519 10:13:39.372123 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9520 10:13:39.372277 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9521 10:13:39.372430 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9522 10:13:39.372561 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9523 10:13:39.372739 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9524 10:13:39.372869 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9525 10:13:39.372984 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9526 10:13:39.373096 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9527 10:13:39.373207 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9528 10:13:39.376669 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9529 10:13:39.377096 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9530 10:13:39.377298 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9531 10:13:39.377507 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9532 10:13:39.377707 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9533 10:13:39.377858 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9534 10:13:39.378021 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9535 10:13:39.378153 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9536 10:13:39.378275 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9537 10:13:39.378480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9538 10:13:39.378641 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9539 10:13:39.378790 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9540 10:13:39.378950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9541 10:13:39.379111 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9542 10:13:39.379246 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9543 10:13:39.379374 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9544 10:13:39.379542 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9545 10:13:39.379700 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9546 10:13:39.379856 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9547 10:13:39.380047 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9548 10:13:39.380213 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9549 10:13:39.380353 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9550 10:13:39.380525 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9551 10:13:39.380660 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9552 10:13:39.380772 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9553 10:13:39.380881 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9554 10:13:39.381016 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9555 10:13:39.381131 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9556 10:13:39.381240 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9557 10:13:39.381349 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9558 10:13:39.381459 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9559 10:13:39.381566 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9560 10:13:39.381743 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9561 10:13:39.384666 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9562 10:13:39.385086 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9563 10:13:39.385186 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9564 10:13:39.385274 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9565 10:13:39.385370 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9566 10:13:39.385454 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9567 10:13:39.385537 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9568 10:13:39.385636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9569 10:13:39.385742 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9570 10:13:39.385865 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9571 10:13:39.385975 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9572 10:13:39.386273 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9573 10:13:39.386387 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9574 10:13:39.386487 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9575 10:13:39.402863 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9576 10:13:39.403170 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9577 10:13:39.403272 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9578 10:13:39.403355 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9579 10:13:39.403453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9580 10:13:39.403537 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9581 10:13:39.403632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9582 10:13:39.403727 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9583 10:13:39.404016 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9584 10:13:39.404130 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9585 10:13:39.404232 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9586 10:13:39.404564 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9587 10:13:39.404749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9588 10:13:39.404934 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9589 10:13:39.405108 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9590 10:13:39.405275 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9591 10:13:39.405495 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9592 10:13:39.405716 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9593 10:13:39.405890 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9594 10:13:39.406049 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9595 10:13:39.406238 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9596 10:13:39.406401 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9597 10:13:39.406558 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9598 10:13:39.406709 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9599 10:13:39.406851 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9600 10:13:39.407002 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9601 10:13:39.407187 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9602 10:13:39.407348 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9603 10:13:39.407504 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9604 10:13:39.407659 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9605 10:13:39.407812 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9606 10:13:39.407968 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9607 10:13:39.408122 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9608 10:13:39.408273 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9609 10:13:39.408427 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9610 10:13:39.408578 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9611 10:13:39.408696 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9612 10:13:39.408809 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9613 10:13:39.408918 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9614 10:13:39.409026 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9615 10:13:39.409133 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9616 10:13:39.409241 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9617 10:13:39.409348 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9618 10:13:39.409456 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9619 10:13:39.409565 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9620 10:13:39.409733 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9621 10:13:39.412887 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9622 10:13:39.413091 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9623 10:13:39.413337 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9624 10:13:39.413521 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9625 10:13:39.413700 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9626 10:13:39.413871 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9627 10:13:39.414020 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9628 10:13:39.414168 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9629 10:13:39.414314 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9630 10:13:39.414450 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9631 10:13:39.414629 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9632 10:13:39.414791 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9633 10:13:39.414922 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9634 10:13:39.415040 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9635 10:13:39.415155 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9636 10:13:39.415274 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9637 10:13:39.415389 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9638 10:13:39.415538 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9639 10:13:39.415663 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9640 10:13:39.415787 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9641 10:13:39.415905 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9642 10:13:39.416055 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9643 10:13:39.416175 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9644 10:13:39.416313 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9645 10:13:39.416430 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9646 10:13:39.416543 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9647 10:13:39.416653 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9648 10:13:39.416761 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9649 10:13:39.416869 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9650 10:13:39.416977 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9651 10:13:39.417107 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9652 10:13:39.420723 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9653 10:13:39.421147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9654 10:13:39.421316 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9655 10:13:39.421469 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9656 10:13:39.421624 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9657 10:13:39.421821 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9658 10:13:39.421978 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9659 10:13:39.422126 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9660 10:13:39.422269 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9661 10:13:39.422411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9662 10:13:39.422552 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9663 10:13:39.422690 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9664 10:13:39.422859 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9665 10:13:39.423001 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9666 10:13:39.423140 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9667 10:13:39.423278 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9668 10:13:39.423415 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9669 10:13:39.423552 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9670 10:13:39.423703 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9671 10:13:39.423870 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9672 10:13:39.424072 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9673 10:13:39.424208 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9674 10:13:39.424345 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9675 10:13:39.424514 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9676 10:13:39.424688 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9677 10:13:39.424856 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9678 10:13:39.425027 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9679 10:13:39.425201 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9680 10:13:39.425407 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9681 10:13:39.425580 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9682 10:13:39.425714 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9683 10:13:39.425828 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9684 10:13:39.428805 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9685 10:13:39.428995 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9686 10:13:39.429387 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9687 10:13:39.429584 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9688 10:13:39.429790 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9689 10:13:39.429936 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9690 10:13:39.430053 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9691 10:13:39.430277 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9692 10:13:39.430468 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9693 10:13:39.430664 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9694 10:13:39.430843 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9695 10:13:39.430991 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9696 10:13:39.431124 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9697 10:13:39.431259 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9698 10:13:39.431460 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9699 10:13:39.431663 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9700 10:13:39.431820 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9701 10:13:39.431973 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9702 10:13:39.432126 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9703 10:13:39.432281 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9704 10:13:39.432434 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9705 10:13:39.432560 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9706 10:13:39.432672 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9707 10:13:39.432816 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9708 10:13:39.432934 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9709 10:13:39.433045 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9710 10:13:39.433154 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9711 10:13:39.433264 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9712 10:13:39.433373 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9713 10:13:39.433483 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9714 10:13:39.433596 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9715 10:13:39.433718 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9716 10:13:39.433830 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9717 10:13:39.433940 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9718 10:13:39.436720 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9719 10:13:39.437020 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9720 10:13:39.437118 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9721 10:13:39.437215 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9722 10:13:39.437302 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9723 10:13:39.437405 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9724 10:13:39.437693 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9725 10:13:39.437803 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9726 10:13:39.437888 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9727 10:13:39.437986 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9728 10:13:39.438276 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9729 10:13:39.438373 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9730 10:13:39.438468 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9731 10:13:39.438755 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9732 10:13:39.438852 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9733 10:13:39.438951 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9734 10:13:39.439047 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9735 10:13:39.453302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9736 10:13:39.453609 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9737 10:13:39.453716 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9738 10:13:39.453815 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9739 10:13:39.453910 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9740 10:13:39.454299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9741 10:13:39.454626 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9742 10:13:39.454847 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9743 10:13:39.455031 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9744 10:13:39.455192 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9745 10:13:39.455382 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9746 10:13:39.455587 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9747 10:13:39.455767 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9748 10:13:39.455947 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9749 10:13:39.456105 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9750 10:13:39.456287 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9751 10:13:39.456492 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9752 10:13:39.456672 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9753 10:13:39.456841 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9754 10:13:39.457001 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9755 10:13:39.457156 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9756 10:13:39.457306 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9757 10:13:39.460758 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9758 10:13:39.461042 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9759 10:13:39.461435 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9760 10:13:39.461608 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9761 10:13:39.461764 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9762 10:13:39.461895 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9763 10:13:39.462020 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9764 10:13:39.462177 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9765 10:13:39.462316 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9766 10:13:39.462454 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9767 10:13:39.462589 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9768 10:13:39.462726 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9769 10:13:39.462861 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9770 10:13:39.463051 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9771 10:13:39.463223 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9772 10:13:39.463361 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9773 10:13:39.463503 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9774 10:13:39.463700 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9775 10:13:39.463877 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9776 10:13:39.464183 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9777 10:13:39.464445 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9778 10:13:39.464623 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9779 10:13:39.464770 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9780 10:13:39.464945 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9781 10:13:39.465082 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9782 10:13:39.465230 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9783 10:13:39.465345 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9784 10:13:39.465455 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9785 10:13:39.465563 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9786 10:13:39.465685 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9787 10:13:39.465825 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9788 10:13:39.465944 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9789 10:13:39.468946 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9790 10:13:39.469190 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9791 10:13:39.469453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9792 10:13:39.469630 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9793 10:13:39.469798 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9794 10:13:39.469998 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9795 10:13:39.470158 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9796 10:13:39.470333 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9797 10:13:39.470495 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9798 10:13:39.470634 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9799 10:13:39.470753 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9800 10:13:39.470884 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9801 10:13:39.471017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9802 10:13:39.471149 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9803 10:13:39.471265 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9804 10:13:39.471410 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9805 10:13:39.471531 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9806 10:13:39.471647 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9807 10:13:39.471763 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9808 10:13:39.471876 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9809 10:13:39.471990 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9810 10:13:39.472106 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9811 10:13:39.472229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9812 10:13:39.472346 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9813 10:13:39.472443 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9814 10:13:39.472587 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9815 10:13:39.472700 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9816 10:13:39.472790 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9817 10:13:39.472876 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9818 10:13:39.472962 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9819 10:13:39.473048 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9820 10:13:39.473133 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9821 10:13:39.473219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9822 10:13:39.476752 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9823 10:13:39.477039 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9824 10:13:39.477432 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9825 10:13:39.477580 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9826 10:13:39.477717 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9827 10:13:39.477803 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9828 10:13:39.477867 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9829 10:13:39.477947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9830 10:13:39.478025 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9831 10:13:39.478120 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9832 10:13:39.478202 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9833 10:13:39.478312 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9834 10:13:39.478410 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9835 10:13:39.478492 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9836 10:13:39.478590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9837 10:13:39.478707 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9838 10:13:39.478804 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9839 10:13:39.478895 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9840 10:13:39.479004 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9841 10:13:39.479103 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9842 10:13:39.479225 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9843 10:13:39.479320 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9844 10:13:39.479420 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9845 10:13:39.479537 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9846 10:13:39.479628 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9847 10:13:39.479721 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9848 10:13:39.479808 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9849 10:13:39.479888 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9850 10:13:39.479966 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9851 10:13:39.480045 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9852 10:13:39.480141 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9853 10:13:39.480235 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9854 10:13:39.480311 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9855 10:13:39.480383 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9856 10:13:39.484677 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9857 10:13:39.485093 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9858 10:13:39.485281 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9859 10:13:39.485438 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9860 10:13:39.485621 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9861 10:13:39.485792 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9862 10:13:39.485933 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9863 10:13:39.486087 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9864 10:13:39.486234 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9865 10:13:39.486409 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9866 10:13:39.486555 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9867 10:13:39.486691 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9868 10:13:39.486840 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9869 10:13:39.486979 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9870 10:13:39.487125 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9871 10:13:39.487326 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9872 10:13:39.487470 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9873 10:13:39.487608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9874 10:13:39.487768 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9875 10:13:39.487912 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9876 10:13:39.488065 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9877 10:13:39.488227 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9878 10:13:39.488448 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9879 10:13:39.488600 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9880 10:13:39.488720 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9881 10:13:39.488834 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9882 10:13:39.488947 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9883 10:13:39.489059 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9884 10:13:39.489170 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9885 10:13:39.489283 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9886 10:13:39.489395 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9887 10:13:39.489506 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9888 10:13:39.492725 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9889 10:13:39.493187 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9890 10:13:39.493298 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9891 10:13:39.493395 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9892 10:13:39.493470 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9893 10:13:39.493555 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9894 10:13:39.493687 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9895 10:13:39.503911 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9896 10:13:39.504249 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9897 10:13:39.504695 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9898 10:13:39.504830 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9899 10:13:39.504935 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9900 10:13:39.505033 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9901 10:13:39.505130 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9902 10:13:39.505225 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9903 10:13:39.505341 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9904 10:13:39.505440 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9905 10:13:39.505536 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9906 10:13:39.505631 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9907 10:13:39.505743 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9908 10:13:39.505858 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9909 10:13:39.505956 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9910 10:13:39.506053 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9911 10:13:39.506147 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9912 10:13:39.506270 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9913 10:13:39.506392 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9914 10:13:39.506507 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9915 10:13:39.506649 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9916 10:13:39.506738 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9917 10:13:39.506826 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9918 10:13:39.506915 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9919 10:13:39.507021 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9920 10:13:39.507111 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9921 10:13:39.507198 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9922 10:13:39.507286 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9923 10:13:39.507391 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9924 10:13:39.507481 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9925 10:13:39.507567 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9926 10:13:39.507673 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9927 10:13:39.507768 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
9928 10:13:39.507856 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
9929 10:13:39.507956 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
9930 10:13:39.508046 arm64_sve-ptrace_Set_SVE_VL_4448 pass
9931 10:13:39.508150 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
9932 10:13:39.508254 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
9933 10:13:39.508343 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
9934 10:13:39.508632 arm64_sve-ptrace_Set_SVE_VL_4464 pass
9935 10:13:39.508726 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
9936 10:13:39.512837 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
9937 10:13:39.513045 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
9938 10:13:39.513204 arm64_sve-ptrace_Set_SVE_VL_4480 pass
9939 10:13:39.513380 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
9940 10:13:39.513513 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
9941 10:13:39.513635 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
9942 10:13:39.513801 arm64_sve-ptrace_Set_SVE_VL_4496 pass
9943 10:13:39.513982 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
9944 10:13:39.514131 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
9945 10:13:39.514293 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
9946 10:13:39.514424 arm64_sve-ptrace_Set_SVE_VL_4512 pass
9947 10:13:39.514547 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
9948 10:13:39.514670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
9949 10:13:39.514815 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
9950 10:13:39.514940 arm64_sve-ptrace_Set_SVE_VL_4528 pass
9951 10:13:39.515059 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
9952 10:13:39.515178 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
9953 10:13:39.515321 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
9954 10:13:39.515468 arm64_sve-ptrace_Set_SVE_VL_4544 pass
9955 10:13:39.515618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
9956 10:13:39.515742 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
9957 10:13:39.515900 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
9958 10:13:39.516037 arm64_sve-ptrace_Set_SVE_VL_4560 pass
9959 10:13:39.516192 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
9960 10:13:39.516349 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
9961 10:13:39.516499 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
9962 10:13:39.516653 arm64_sve-ptrace_Set_SVE_VL_4576 pass
9963 10:13:39.516771 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
9964 10:13:39.516883 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
9965 10:13:39.516998 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
9966 10:13:39.517111 arm64_sve-ptrace_Set_SVE_VL_4592 pass
9967 10:13:39.517222 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
9968 10:13:39.520676 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
9969 10:13:39.521045 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
9970 10:13:39.521183 arm64_sve-ptrace_Set_SVE_VL_4608 pass
9971 10:13:39.521304 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
9972 10:13:39.521447 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
9973 10:13:39.521597 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
9974 10:13:39.521756 arm64_sve-ptrace_Set_SVE_VL_4624 pass
9975 10:13:39.521962 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
9976 10:13:39.522121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
9977 10:13:39.522287 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
9978 10:13:39.522430 arm64_sve-ptrace_Set_SVE_VL_4640 pass
9979 10:13:39.522596 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
9980 10:13:39.522780 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
9981 10:13:39.522943 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
9982 10:13:39.523096 arm64_sve-ptrace_Set_SVE_VL_4656 pass
9983 10:13:39.523248 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
9984 10:13:39.523430 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
9985 10:13:39.523595 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
9986 10:13:39.523755 arm64_sve-ptrace_Set_SVE_VL_4672 pass
9987 10:13:39.523919 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
9988 10:13:39.524067 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
9989 10:13:39.524217 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
9990 10:13:39.524347 arm64_sve-ptrace_Set_SVE_VL_4688 pass
9991 10:13:39.524496 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
9992 10:13:39.524616 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
9993 10:13:39.524731 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
9994 10:13:39.524844 arm64_sve-ptrace_Set_SVE_VL_4704 pass
9995 10:13:39.524956 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
9996 10:13:39.525068 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
9997 10:13:39.525179 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
9998 10:13:39.525291 arm64_sve-ptrace_Set_SVE_VL_4720 pass
9999 10:13:39.528691 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
10000 10:13:39.528993 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
10001 10:13:39.529104 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
10002 10:13:39.529196 arm64_sve-ptrace_Set_SVE_VL_4736 pass
10003 10:13:39.529302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
10004 10:13:39.529393 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
10005 10:13:39.529695 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
10006 10:13:39.529800 arm64_sve-ptrace_Set_SVE_VL_4752 pass
10007 10:13:39.529890 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
10008 10:13:39.529978 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
10009 10:13:39.530083 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
10010 10:13:39.530173 arm64_sve-ptrace_Set_SVE_VL_4768 pass
10011 10:13:39.530262 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
10012 10:13:39.530366 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
10013 10:13:39.530472 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
10014 10:13:39.530563 arm64_sve-ptrace_Set_SVE_VL_4784 pass
10015 10:13:39.530668 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
10016 10:13:39.530982 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
10017 10:13:39.531086 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
10018 10:13:39.531177 arm64_sve-ptrace_Set_SVE_VL_4800 pass
10019 10:13:39.531282 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
10020 10:13:39.531373 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
10021 10:13:39.531478 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
10022 10:13:39.531584 arm64_sve-ptrace_Set_SVE_VL_4816 pass
10023 10:13:39.531690 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
10024 10:13:39.531799 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
10025 10:13:39.531903 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
10026 10:13:39.532009 arm64_sve-ptrace_Set_SVE_VL_4832 pass
10027 10:13:39.532113 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
10028 10:13:39.532220 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
10029 10:13:39.532524 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
10030 10:13:39.532628 arm64_sve-ptrace_Set_SVE_VL_4848 pass
10031 10:13:39.536733 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
10032 10:13:39.537110 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
10033 10:13:39.537209 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
10034 10:13:39.537285 arm64_sve-ptrace_Set_SVE_VL_4864 pass
10035 10:13:39.537356 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
10036 10:13:39.537792 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
10037 10:13:39.537985 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
10038 10:13:39.538146 arm64_sve-ptrace_Set_SVE_VL_4880 pass
10039 10:13:39.538298 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
10040 10:13:39.538458 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
10041 10:13:39.538615 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
10042 10:13:39.538969 arm64_sve-ptrace_Set_SVE_VL_4896 pass
10043 10:13:39.539063 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
10044 10:13:39.539535 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
10045 10:13:39.539605 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
10046 10:13:39.539673 arm64_sve-ptrace_Set_SVE_VL_4912 pass
10047 10:13:39.539741 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
10048 10:13:39.539806 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
10049 10:13:39.539867 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
10050 10:13:39.539925 arm64_sve-ptrace_Set_SVE_VL_4928 pass
10051 10:13:39.539983 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
10052 10:13:39.540041 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
10053 10:13:39.540100 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
10054 10:13:39.540158 arm64_sve-ptrace_Set_SVE_VL_4944 pass
10055 10:13:39.553576 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
10056 10:13:39.553890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
10057 10:13:39.554009 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
10058 10:13:39.554140 arm64_sve-ptrace_Set_SVE_VL_4960 pass
10059 10:13:39.554262 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
10060 10:13:39.554363 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
10061 10:13:39.554457 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
10062 10:13:39.554607 arm64_sve-ptrace_Set_SVE_VL_4976 pass
10063 10:13:39.554710 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
10064 10:13:39.554809 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
10065 10:13:39.554930 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
10066 10:13:39.555015 arm64_sve-ptrace_Set_SVE_VL_4992 pass
10067 10:13:39.555088 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
10068 10:13:39.555210 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
10069 10:13:39.555303 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
10070 10:13:39.555417 arm64_sve-ptrace_Set_SVE_VL_5008 pass
10071 10:13:39.555511 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
10072 10:13:39.555635 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
10073 10:13:39.555737 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
10074 10:13:39.555862 arm64_sve-ptrace_Set_SVE_VL_5024 pass
10075 10:13:39.555943 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
10076 10:13:39.556042 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
10077 10:13:39.556145 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
10078 10:13:39.556246 arm64_sve-ptrace_Set_SVE_VL_5040 pass
10079 10:13:39.556334 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
10080 10:13:39.556416 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
10081 10:13:39.560644 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
10082 10:13:39.560968 arm64_sve-ptrace_Set_SVE_VL_5056 pass
10083 10:13:39.561129 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
10084 10:13:39.561492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
10085 10:13:39.561693 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
10086 10:13:39.561864 arm64_sve-ptrace_Set_SVE_VL_5072 pass
10087 10:13:39.562040 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
10088 10:13:39.562184 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
10089 10:13:39.562374 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
10090 10:13:39.562595 arm64_sve-ptrace_Set_SVE_VL_5088 pass
10091 10:13:39.562785 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
10092 10:13:39.562974 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
10093 10:13:39.563167 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
10094 10:13:39.563312 arm64_sve-ptrace_Set_SVE_VL_5104 pass
10095 10:13:39.563463 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
10096 10:13:39.563631 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
10097 10:13:39.563782 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
10098 10:13:39.563967 arm64_sve-ptrace_Set_SVE_VL_5120 pass
10099 10:13:39.564205 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
10100 10:13:39.564388 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
10101 10:13:39.564563 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
10102 10:13:39.564740 arm64_sve-ptrace_Set_SVE_VL_5136 pass
10103 10:13:39.564875 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
10104 10:13:39.564997 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
10105 10:13:39.565134 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
10106 10:13:39.565251 arm64_sve-ptrace_Set_SVE_VL_5152 pass
10107 10:13:39.565361 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
10108 10:13:39.565473 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
10109 10:13:39.565583 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
10110 10:13:39.565707 arm64_sve-ptrace_Set_SVE_VL_5168 pass
10111 10:13:39.565819 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
10112 10:13:39.565929 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
10113 10:13:39.566066 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
10114 10:13:39.566185 arm64_sve-ptrace_Set_SVE_VL_5184 pass
10115 10:13:39.566296 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
10116 10:13:39.568680 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
10117 10:13:39.569101 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
10118 10:13:39.569291 arm64_sve-ptrace_Set_SVE_VL_5200 pass
10119 10:13:39.569450 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
10120 10:13:39.569636 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
10121 10:13:39.569817 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
10122 10:13:39.569952 arm64_sve-ptrace_Set_SVE_VL_5216 pass
10123 10:13:39.570123 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
10124 10:13:39.570298 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
10125 10:13:39.570496 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
10126 10:13:39.570730 arm64_sve-ptrace_Set_SVE_VL_5232 pass
10127 10:13:39.570928 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
10128 10:13:39.571118 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
10129 10:13:39.571320 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
10130 10:13:39.571506 arm64_sve-ptrace_Set_SVE_VL_5248 pass
10131 10:13:39.571661 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
10132 10:13:39.571814 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
10133 10:13:39.571947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
10134 10:13:39.572096 arm64_sve-ptrace_Set_SVE_VL_5264 pass
10135 10:13:39.572247 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
10136 10:13:39.572433 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
10137 10:13:39.572579 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
10138 10:13:39.572690 arm64_sve-ptrace_Set_SVE_VL_5280 pass
10139 10:13:39.572799 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
10140 10:13:39.572908 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
10141 10:13:39.573017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
10142 10:13:39.573125 arm64_sve-ptrace_Set_SVE_VL_5296 pass
10143 10:13:39.573233 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
10144 10:13:39.573342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
10145 10:13:39.573450 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
10146 10:13:39.573558 arm64_sve-ptrace_Set_SVE_VL_5312 pass
10147 10:13:39.573715 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
10148 10:13:39.573912 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
10149 10:13:39.574089 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
10150 10:13:39.574298 arm64_sve-ptrace_Set_SVE_VL_5328 pass
10151 10:13:39.576723 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
10152 10:13:39.577161 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
10153 10:13:39.577351 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
10154 10:13:39.577512 arm64_sve-ptrace_Set_SVE_VL_5344 pass
10155 10:13:39.577685 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
10156 10:13:39.577832 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
10157 10:13:39.578020 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
10158 10:13:39.578171 arm64_sve-ptrace_Set_SVE_VL_5360 pass
10159 10:13:39.578325 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
10160 10:13:39.578469 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
10161 10:13:39.578621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
10162 10:13:39.578772 arm64_sve-ptrace_Set_SVE_VL_5376 pass
10163 10:13:39.578945 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
10164 10:13:39.579133 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
10165 10:13:39.579263 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
10166 10:13:39.579422 arm64_sve-ptrace_Set_SVE_VL_5392 pass
10167 10:13:39.579572 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
10168 10:13:39.579750 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
10169 10:13:39.579905 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
10170 10:13:39.580042 arm64_sve-ptrace_Set_SVE_VL_5408 pass
10171 10:13:39.580231 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
10172 10:13:39.580428 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10173 10:13:39.580556 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10174 10:13:39.580697 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10175 10:13:39.580812 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10176 10:13:39.580920 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10177 10:13:39.581027 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10178 10:13:39.581133 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10179 10:13:39.581238 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10180 10:13:39.581343 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10181 10:13:39.581448 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10182 10:13:39.581554 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10183 10:13:39.581675 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10184 10:13:39.581784 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10185 10:13:39.581877 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10186 10:13:39.584655 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10187 10:13:39.585009 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10188 10:13:39.585144 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10189 10:13:39.585271 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10190 10:13:39.585403 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10191 10:13:39.585537 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10192 10:13:39.585676 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10193 10:13:39.585841 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10194 10:13:39.585994 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10195 10:13:39.586123 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10196 10:13:39.586257 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10197 10:13:39.586376 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10198 10:13:39.586555 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10199 10:13:39.586700 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10200 10:13:39.586839 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10201 10:13:39.586980 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10202 10:13:39.587110 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10203 10:13:39.587224 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10204 10:13:39.587386 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10205 10:13:39.587515 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10206 10:13:39.587629 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10207 10:13:39.587721 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10208 10:13:39.587805 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10209 10:13:39.587891 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10210 10:13:39.587981 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10211 10:13:39.588081 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10212 10:13:39.588189 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10213 10:13:39.588278 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10214 10:13:39.588364 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10215 10:13:39.601722 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10216 10:13:39.602160 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10217 10:13:39.602288 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10218 10:13:39.602390 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10219 10:13:39.602485 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10220 10:13:39.602614 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10221 10:13:39.602734 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10222 10:13:39.602853 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10223 10:13:39.602989 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10224 10:13:39.603158 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10225 10:13:39.603312 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10226 10:13:39.603460 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10227 10:13:39.603584 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10228 10:13:39.603734 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10229 10:13:39.603860 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10230 10:13:39.603983 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10231 10:13:39.604103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10232 10:13:39.604232 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10233 10:13:39.604446 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10234 10:13:39.604620 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10235 10:13:39.604784 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10236 10:13:39.604924 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10237 10:13:39.605061 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10238 10:13:39.608670 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10239 10:13:39.609017 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10240 10:13:39.609189 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10241 10:13:39.609406 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10242 10:13:39.609587 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10243 10:13:39.609737 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10244 10:13:39.609978 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10245 10:13:39.610141 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10246 10:13:39.610309 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10247 10:13:39.610462 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10248 10:13:39.610602 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10249 10:13:39.610804 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10250 10:13:39.610961 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10251 10:13:39.611150 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10252 10:13:39.611329 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10253 10:13:39.611481 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10254 10:13:39.611627 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10255 10:13:39.611771 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10256 10:13:39.611989 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10257 10:13:39.612159 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10258 10:13:39.612293 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10259 10:13:39.612466 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10260 10:13:39.612619 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10261 10:13:39.612739 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10262 10:13:39.612849 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10263 10:13:39.612954 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10264 10:13:39.613088 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10265 10:13:39.613228 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10266 10:13:39.613389 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10267 10:13:39.613524 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10268 10:13:39.613643 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10269 10:13:39.613919 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10270 10:13:39.616667 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10271 10:13:39.617087 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10272 10:13:39.617285 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10273 10:13:39.617437 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10274 10:13:39.617590 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10275 10:13:39.617772 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10276 10:13:39.617906 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10277 10:13:39.618056 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10278 10:13:39.618214 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10279 10:13:39.618360 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10280 10:13:39.618486 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10281 10:13:39.618659 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10282 10:13:39.618813 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10283 10:13:39.618962 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10284 10:13:39.619127 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10285 10:13:39.619288 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10286 10:13:39.619402 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10287 10:13:39.619557 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10288 10:13:39.619735 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10289 10:13:39.619898 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10290 10:13:39.620010 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10291 10:13:39.620163 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10292 10:13:39.620292 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10293 10:13:39.620458 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10294 10:13:39.620572 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10295 10:13:39.620734 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10296 10:13:39.620884 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10297 10:13:39.621066 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10298 10:13:39.621214 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10299 10:13:39.621340 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10300 10:13:39.621488 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10301 10:13:39.622391 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10302 10:13:39.622578 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10303 10:13:39.624681 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10304 10:13:39.625133 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10305 10:13:39.625350 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10306 10:13:39.625567 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10307 10:13:39.625746 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10308 10:13:39.625952 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10309 10:13:39.626160 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10310 10:13:39.626389 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10311 10:13:39.626608 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10312 10:13:39.626813 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10313 10:13:39.626992 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10314 10:13:39.627203 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10315 10:13:39.627396 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10316 10:13:39.627548 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10317 10:13:39.627722 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10318 10:13:39.627892 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10319 10:13:39.628098 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10320 10:13:39.628276 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10321 10:13:39.628460 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10322 10:13:39.628610 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10323 10:13:39.628738 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10324 10:13:39.628864 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10325 10:13:39.628988 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10326 10:13:39.629112 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10327 10:13:39.629273 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10328 10:13:39.629406 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10329 10:13:39.629534 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10330 10:13:39.629703 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10331 10:13:39.629936 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10332 10:13:39.630139 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10333 10:13:39.630340 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10334 10:13:39.630540 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10335 10:13:39.630741 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10336 10:13:39.630897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10337 10:13:39.631051 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10338 10:13:39.632658 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10339 10:13:39.633067 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10340 10:13:39.633266 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10341 10:13:39.633453 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10342 10:13:39.633638 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10343 10:13:39.633846 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10344 10:13:39.634008 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10345 10:13:39.634161 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10346 10:13:39.634364 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10347 10:13:39.634561 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10348 10:13:39.634727 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10349 10:13:39.634927 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10350 10:13:39.635123 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10351 10:13:39.635322 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10352 10:13:39.635496 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10353 10:13:39.635662 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10354 10:13:39.635834 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10355 10:13:39.636019 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10356 10:13:39.636139 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10357 10:13:39.636234 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10358 10:13:39.636325 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10359 10:13:39.636415 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10360 10:13:39.636505 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10361 10:13:39.636594 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10362 10:13:39.636680 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10363 10:13:39.636765 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10364 10:13:39.636850 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10365 10:13:39.636937 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10366 10:13:39.637022 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10367 10:13:39.637106 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10368 10:13:39.637191 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10369 10:13:39.637297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10370 10:13:39.637389 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10371 10:13:39.637477 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10372 10:13:39.640699 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10373 10:13:39.641104 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10374 10:13:39.641266 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10375 10:13:39.650483 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10376 10:13:39.650857 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10377 10:13:39.651061 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10378 10:13:39.651267 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10379 10:13:39.651496 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10380 10:13:39.651682 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10381 10:13:39.651866 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10382 10:13:39.652017 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10383 10:13:39.652157 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10384 10:13:39.652355 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10385 10:13:39.652514 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10386 10:13:39.652687 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10387 10:13:39.652854 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10388 10:13:39.652997 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10389 10:13:39.653164 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10390 10:13:39.653350 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10391 10:13:39.653569 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10392 10:13:39.653772 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10393 10:13:39.653958 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10394 10:13:39.654144 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10395 10:13:39.654327 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10396 10:13:39.654528 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10397 10:13:39.654695 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10398 10:13:39.654855 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10399 10:13:39.654995 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10400 10:13:39.655212 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10401 10:13:39.655380 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10402 10:13:39.655519 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10403 10:13:39.655658 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10404 10:13:39.655820 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10405 10:13:39.655965 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10406 10:13:39.656111 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10407 10:13:39.656232 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10408 10:13:39.656355 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10409 10:13:39.656491 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10410 10:13:39.656609 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10411 10:13:39.656720 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10412 10:13:39.656831 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10413 10:13:39.656941 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10414 10:13:39.657285 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10415 10:13:39.657439 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10416 10:13:39.657560 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10417 10:13:39.657686 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10418 10:13:39.657802 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10419 10:13:39.657913 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10420 10:13:39.658020 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10421 10:13:39.658105 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10422 10:13:39.658189 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10423 10:13:39.658272 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10424 10:13:39.658356 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10425 10:13:39.660661 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10426 10:13:39.661086 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10427 10:13:39.661286 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10428 10:13:39.661455 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10429 10:13:39.661644 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10430 10:13:39.661851 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10431 10:13:39.661992 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10432 10:13:39.662119 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10433 10:13:39.662211 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10434 10:13:39.662303 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10435 10:13:39.662450 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10436 10:13:39.662569 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10437 10:13:39.662696 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10438 10:13:39.662814 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10439 10:13:39.662911 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10440 10:13:39.663052 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10441 10:13:39.663172 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10442 10:13:39.663311 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10443 10:13:39.663455 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10444 10:13:39.663630 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10445 10:13:39.663760 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10446 10:13:39.663888 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10447 10:13:39.663997 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10448 10:13:39.664102 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10449 10:13:39.664237 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10450 10:13:39.664343 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10451 10:13:39.664434 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10452 10:13:39.664546 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10453 10:13:39.664636 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10454 10:13:39.664721 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10455 10:13:39.664805 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10456 10:13:39.664889 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10457 10:13:39.664973 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10458 10:13:39.665058 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10459 10:13:39.668653 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10460 10:13:39.669032 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10461 10:13:39.669175 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10462 10:13:39.669325 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10463 10:13:39.669498 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10464 10:13:39.669632 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10465 10:13:39.669778 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10466 10:13:39.669896 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10467 10:13:39.670067 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10468 10:13:39.670188 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10469 10:13:39.670297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10470 10:13:39.670424 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10471 10:13:39.670564 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10472 10:13:39.670692 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10473 10:13:39.670872 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10474 10:13:39.671031 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10475 10:13:39.671172 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10476 10:13:39.671281 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10477 10:13:39.671395 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10478 10:13:39.671528 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10479 10:13:39.671658 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10480 10:13:39.671833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10481 10:13:39.671967 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10482 10:13:39.672107 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10483 10:13:39.672248 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10484 10:13:39.672365 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10485 10:13:39.672476 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10486 10:13:39.672570 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10487 10:13:39.672678 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10488 10:13:39.672770 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10489 10:13:39.672857 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10490 10:13:39.672941 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10491 10:13:39.673026 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10492 10:13:39.673111 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10493 10:13:39.676687 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10494 10:13:39.677072 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10495 10:13:39.677228 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10496 10:13:39.677357 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10497 10:13:39.677544 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10498 10:13:39.677707 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10499 10:13:39.677839 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10500 10:13:39.677989 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10501 10:13:39.678141 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10502 10:13:39.678299 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10503 10:13:39.678454 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10504 10:13:39.678612 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10505 10:13:39.678764 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10506 10:13:39.678919 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10507 10:13:39.679069 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10508 10:13:39.679243 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10509 10:13:39.679365 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10510 10:13:39.679479 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10511 10:13:39.679626 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10512 10:13:39.679775 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10513 10:13:39.679896 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10514 10:13:39.680002 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10515 10:13:39.680129 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10516 10:13:39.680242 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10517 10:13:39.680354 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10518 10:13:39.680485 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10519 10:13:39.680612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10520 10:13:39.680741 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10521 10:13:39.680850 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10522 10:13:39.680957 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10523 10:13:39.681063 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10524 10:13:39.681169 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10525 10:13:39.681275 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10526 10:13:39.681381 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10527 10:13:39.681487 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10528 10:13:39.681594 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10529 10:13:39.684678 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10530 10:13:39.685123 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10531 10:13:39.685316 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10532 10:13:39.685461 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10533 10:13:39.685617 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10534 10:13:39.685794 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10535 10:13:39.699039 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10536 10:13:39.699144 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10537 10:13:39.699458 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10538 10:13:39.699658 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10539 10:13:39.699833 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10540 10:13:39.700015 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10541 10:13:39.700178 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10542 10:13:39.700334 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10543 10:13:39.700477 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10544 10:13:39.700613 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10545 10:13:39.700775 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10546 10:13:39.700935 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10547 10:13:39.701081 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10548 10:13:39.701221 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10549 10:13:39.701352 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10550 10:13:39.701554 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10551 10:13:39.701781 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10552 10:13:39.701955 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10553 10:13:39.702119 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10554 10:13:39.702268 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10555 10:13:39.702410 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10556 10:13:39.702558 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10557 10:13:39.702723 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10558 10:13:39.702883 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10559 10:13:39.703010 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10560 10:13:39.703192 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10561 10:13:39.703347 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10562 10:13:39.703493 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10563 10:13:39.703630 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10564 10:13:39.703803 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10565 10:13:39.703964 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10566 10:13:39.704131 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10567 10:13:39.704282 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10568 10:13:39.704485 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10569 10:13:39.704691 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10570 10:13:39.704839 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10571 10:13:39.704967 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10572 10:13:39.705121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10573 10:13:39.705255 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10574 10:13:39.705383 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10575 10:13:39.705713 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10576 10:13:39.705831 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10577 10:13:39.705922 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10578 10:13:39.706011 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10579 10:13:39.706097 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10580 10:13:39.706181 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10581 10:13:39.706267 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10582 10:13:39.706356 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10583 10:13:39.708676 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10584 10:13:39.709087 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10585 10:13:39.709292 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10586 10:13:39.709506 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10587 10:13:39.709759 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10588 10:13:39.709939 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10589 10:13:39.710124 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10590 10:13:39.710332 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10591 10:13:39.710546 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10592 10:13:39.710729 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10593 10:13:39.710942 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10594 10:13:39.711116 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10595 10:13:39.711311 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10596 10:13:39.711500 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10597 10:13:39.711708 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10598 10:13:39.711902 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10599 10:13:39.712052 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10600 10:13:39.712207 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10601 10:13:39.712419 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10602 10:13:39.712617 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10603 10:13:39.712765 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10604 10:13:39.712929 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10605 10:13:39.713068 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10606 10:13:39.713195 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10607 10:13:39.713321 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10608 10:13:39.713448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10609 10:13:39.713572 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10610 10:13:39.713714 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10611 10:13:39.713841 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10612 10:13:39.713965 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10613 10:13:39.714090 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10614 10:13:39.714216 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10615 10:13:39.714341 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10616 10:13:39.714466 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10617 10:13:39.716661 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10618 10:13:39.717030 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10619 10:13:39.717229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10620 10:13:39.717403 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10621 10:13:39.717614 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10622 10:13:39.717806 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10623 10:13:39.718016 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10624 10:13:39.718237 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10625 10:13:39.718437 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10626 10:13:39.718614 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10627 10:13:39.718805 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10628 10:13:39.718980 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10629 10:13:39.719178 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10630 10:13:39.719372 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10631 10:13:39.719541 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10632 10:13:39.719757 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10633 10:13:39.719938 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10634 10:13:39.720136 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10635 10:13:39.720315 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10636 10:13:39.720548 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10637 10:13:39.720690 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10638 10:13:39.720818 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10639 10:13:39.720945 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10640 10:13:39.721076 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10641 10:13:39.721201 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10642 10:13:39.721327 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10643 10:13:39.721453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10644 10:13:39.721577 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10645 10:13:39.721717 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10646 10:13:39.721843 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10647 10:13:39.721969 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10648 10:13:39.722093 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10649 10:13:39.722218 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10650 10:13:39.722343 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10651 10:13:39.722469 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10652 10:13:39.724639 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10653 10:13:39.725002 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10654 10:13:39.725138 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10655 10:13:39.725245 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10656 10:13:39.725352 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10657 10:13:39.725447 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10658 10:13:39.725580 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10659 10:13:39.725711 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10660 10:13:39.725851 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10661 10:13:39.725973 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10662 10:13:39.726099 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10663 10:13:39.726178 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10664 10:13:39.726270 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10665 10:13:39.726347 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10666 10:13:39.726438 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10667 10:13:39.726532 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10668 10:13:39.726626 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10669 10:13:39.726903 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10670 10:13:39.726996 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10671 10:13:39.727087 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10672 10:13:39.727180 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10673 10:13:39.727270 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10674 10:13:39.727361 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10675 10:13:39.727452 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10676 10:13:39.727737 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10677 10:13:39.727829 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10678 10:13:39.727919 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10679 10:13:39.727990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10680 10:13:39.728079 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10681 10:13:39.728168 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10682 10:13:39.728437 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10683 10:13:39.728526 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10684 10:13:39.732722 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10685 10:13:39.733043 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10686 10:13:39.733152 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10687 10:13:39.733233 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10688 10:13:39.733318 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10689 10:13:39.733405 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10690 10:13:39.733520 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10691 10:13:39.733644 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10692 10:13:39.733749 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10693 10:13:39.733842 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10694 10:13:39.733950 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10695 10:13:39.747619 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10696 10:13:39.748040 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10697 10:13:39.748216 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10698 10:13:39.748354 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10699 10:13:39.748518 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10700 10:13:39.748643 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10701 10:13:39.748787 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10702 10:13:39.748925 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10703 10:13:39.749104 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10704 10:13:39.749239 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10705 10:13:39.749383 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10706 10:13:39.749506 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10707 10:13:39.749673 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10708 10:13:39.749807 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10709 10:13:39.749940 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10710 10:13:39.750066 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10711 10:13:39.750182 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10712 10:13:39.750345 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10713 10:13:39.750500 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10714 10:13:39.750657 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10715 10:13:39.750814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10716 10:13:39.750965 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10717 10:13:39.751150 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10718 10:13:39.751308 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10719 10:13:39.751474 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10720 10:13:39.751628 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10721 10:13:39.751772 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10722 10:13:39.751899 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10723 10:13:39.752061 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10724 10:13:39.752268 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10725 10:13:39.752411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10726 10:13:39.752544 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10727 10:13:39.752657 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10728 10:13:39.752768 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10729 10:13:39.752876 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10730 10:13:39.752985 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10731 10:13:39.753093 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10732 10:13:39.753203 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10733 10:13:39.753533 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10734 10:13:39.753669 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10735 10:13:39.756893 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10736 10:13:39.757099 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10737 10:13:39.757271 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10738 10:13:39.757474 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10739 10:13:39.757661 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10740 10:13:39.757835 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10741 10:13:39.758014 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10742 10:13:39.758145 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10743 10:13:39.758273 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10744 10:13:39.758402 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10745 10:13:39.758579 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10746 10:13:39.758784 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10747 10:13:39.758948 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10748 10:13:39.759096 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10749 10:13:39.759229 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10750 10:13:39.759371 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10751 10:13:39.759514 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10752 10:13:39.759689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10753 10:13:39.759855 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10754 10:13:39.760020 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10755 10:13:39.760172 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10756 10:13:39.760303 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10757 10:13:39.760436 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10758 10:13:39.760550 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10759 10:13:39.760687 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10760 10:13:39.760803 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10761 10:13:39.760915 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10762 10:13:39.761026 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10763 10:13:39.761136 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10764 10:13:39.761248 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10765 10:13:39.764690 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10766 10:13:39.765107 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10767 10:13:39.765298 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10768 10:13:39.765448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10769 10:13:39.765635 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10770 10:13:39.765817 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10771 10:13:39.765969 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10772 10:13:39.766119 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10773 10:13:39.766274 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10774 10:13:39.766461 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10775 10:13:39.766613 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10776 10:13:39.766764 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10777 10:13:39.766905 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10778 10:13:39.767033 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10779 10:13:39.767152 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10780 10:13:39.767301 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10781 10:13:39.767436 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10782 10:13:39.767593 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10783 10:13:39.767756 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10784 10:13:39.767908 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10785 10:13:39.768039 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10786 10:13:39.768158 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10787 10:13:39.768307 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10788 10:13:39.768432 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10789 10:13:39.768553 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10790 10:13:39.768670 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10791 10:13:39.768781 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10792 10:13:39.768890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10793 10:13:39.769000 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10794 10:13:39.769110 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10795 10:13:39.769219 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10796 10:13:39.769351 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10797 10:13:39.772645 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10798 10:13:39.773010 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10799 10:13:39.773192 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10800 10:13:39.773402 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10801 10:13:39.773621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10802 10:13:39.773815 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10803 10:13:39.773971 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10804 10:13:39.774106 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10805 10:13:39.774260 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10806 10:13:39.774445 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10807 10:13:39.774645 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10808 10:13:39.774800 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10809 10:13:39.774981 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10810 10:13:39.775137 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10811 10:13:39.775319 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10812 10:13:39.775469 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10813 10:13:39.775629 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10814 10:13:39.775779 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10815 10:13:39.775959 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10816 10:13:39.776102 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10817 10:13:39.776252 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10818 10:13:39.776436 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10819 10:13:39.776610 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10820 10:13:39.776754 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10821 10:13:39.776902 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10822 10:13:39.777020 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10823 10:13:39.777155 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10824 10:13:39.777274 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10825 10:13:39.777456 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10826 10:13:39.777606 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10827 10:13:39.777755 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10828 10:13:39.777871 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10829 10:13:39.780685 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10830 10:13:39.781061 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10831 10:13:39.781251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10832 10:13:39.781414 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10833 10:13:39.781599 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10834 10:13:39.781750 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10835 10:13:39.781904 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10836 10:13:39.782050 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10837 10:13:39.782240 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10838 10:13:39.782409 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10839 10:13:39.782576 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10840 10:13:39.782762 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10841 10:13:39.782925 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10842 10:13:39.783154 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10843 10:13:39.783370 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10844 10:13:39.783580 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10845 10:13:39.783753 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10846 10:13:39.783879 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10847 10:13:39.783994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10848 10:13:39.784134 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10849 10:13:39.784282 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10850 10:13:39.784402 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10851 10:13:39.784516 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10852 10:13:39.784629 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10853 10:13:39.784740 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10854 10:13:39.784851 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10855 10:13:39.796460 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10856 10:13:39.796843 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10857 10:13:39.796947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10858 10:13:39.797050 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10859 10:13:39.797349 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10860 10:13:39.797507 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10861 10:13:39.797638 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10862 10:13:39.797803 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10863 10:13:39.797933 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10864 10:13:39.798059 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10865 10:13:39.798252 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10866 10:13:39.798418 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10867 10:13:39.798538 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10868 10:13:39.798672 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10869 10:13:39.798998 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10870 10:13:39.799179 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10871 10:13:39.799330 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10872 10:13:39.799483 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10873 10:13:39.799698 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10874 10:13:39.799911 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10875 10:13:39.800074 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10876 10:13:39.800222 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10877 10:13:39.800401 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10878 10:13:39.800591 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10879 10:13:39.800745 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10880 10:13:39.800883 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10881 10:13:39.800998 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10882 10:13:39.801109 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10883 10:13:39.801217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10884 10:13:39.801325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10885 10:13:39.804750 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10886 10:13:39.805115 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10887 10:13:39.805251 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10888 10:13:39.805348 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10889 10:13:39.805449 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10890 10:13:39.805540 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10891 10:13:39.805644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10892 10:13:39.805734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10893 10:13:39.805826 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10894 10:13:39.805908 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10895 10:13:39.806012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10896 10:13:39.806352 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10897 10:13:39.806541 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10898 10:13:39.806773 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10899 10:13:39.806955 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10900 10:13:39.807095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10901 10:13:39.807388 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10902 10:13:39.807572 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10903 10:13:39.807773 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10904 10:13:39.807934 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10905 10:13:39.808160 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10906 10:13:39.808341 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10907 10:13:39.808482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10908 10:13:39.808601 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10909 10:13:39.808740 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10910 10:13:39.808859 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10911 10:13:39.808973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10912 10:13:39.812816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10913 10:13:39.813030 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10914 10:13:39.813447 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10915 10:13:39.813660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10916 10:13:39.813822 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10917 10:13:39.813969 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10918 10:13:39.814170 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10919 10:13:39.814324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10920 10:13:39.814470 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10921 10:13:39.814618 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10922 10:13:39.814785 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10923 10:13:39.814996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10924 10:13:39.815197 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10925 10:13:39.815474 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10926 10:13:39.815689 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10927 10:13:39.815907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
10928 10:13:39.816139 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
10929 10:13:39.816334 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
10930 10:13:39.816554 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
10931 10:13:39.816699 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
10932 10:13:39.816825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
10933 10:13:39.816949 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
10934 10:13:39.817074 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
10935 10:13:39.817197 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
10936 10:13:39.817351 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
10937 10:13:39.817485 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
10938 10:13:39.817612 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
10939 10:13:39.817752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
10940 10:13:39.817877 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
10941 10:13:39.820675 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
10942 10:13:39.821151 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
10943 10:13:39.821422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
10944 10:13:39.821623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
10945 10:13:39.821864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
10946 10:13:39.822041 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
10947 10:13:39.822193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
10948 10:13:39.822314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
10949 10:13:39.822407 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
10950 10:13:39.822515 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
10951 10:13:39.822647 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
10952 10:13:39.822766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
10953 10:13:39.822863 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
10954 10:13:39.822966 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
10955 10:13:39.823069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
10956 10:13:39.823171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
10957 10:13:39.823301 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
10958 10:13:39.823419 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
10959 10:13:39.823535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
10960 10:13:39.823648 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
10961 10:13:39.823784 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
10962 10:13:39.823904 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
10963 10:13:39.824030 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
10964 10:13:39.824153 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
10965 10:13:39.824293 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
10966 10:13:39.824418 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
10967 10:13:39.824526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
10968 10:13:39.824624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
10969 10:13:39.824729 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
10970 10:13:39.824819 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
10971 10:13:39.828667 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
10972 10:13:39.829040 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
10973 10:13:39.829216 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
10974 10:13:39.829392 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
10975 10:13:39.829522 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
10976 10:13:39.829656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
10977 10:13:39.829812 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
10978 10:13:39.829942 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
10979 10:13:39.830067 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
10980 10:13:39.830209 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
10981 10:13:39.830335 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
10982 10:13:39.830460 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
10983 10:13:39.830611 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
10984 10:13:39.830743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
10985 10:13:39.830892 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
10986 10:13:39.831022 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
10987 10:13:39.831174 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
10988 10:13:39.831303 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
10989 10:13:39.831456 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
10990 10:13:39.831586 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
10991 10:13:39.831733 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
10992 10:13:39.844194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
10993 10:13:39.844580 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
10994 10:13:39.844721 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
10995 10:13:39.844871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
10996 10:13:39.844999 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
10997 10:13:39.845147 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
10998 10:13:39.845294 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
10999 10:13:39.845445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
11000 10:13:39.845572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
11001 10:13:39.845742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
11002 10:13:39.845869 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
11003 10:13:39.846014 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
11004 10:13:39.846159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
11005 10:13:39.846280 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
11006 10:13:39.846420 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
11007 10:13:39.846543 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
11008 10:13:39.846687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
11009 10:13:39.846813 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
11010 10:13:39.846957 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
11011 10:13:39.847083 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
11012 10:13:39.847225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
11013 10:13:39.847350 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
11014 10:13:39.847500 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
11015 10:13:39.847626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
11016 10:13:39.847773 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
11017 10:13:39.847900 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
11018 10:13:39.848048 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
11019 10:13:39.848177 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
11020 10:13:39.848326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
11021 10:13:39.848452 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
11022 10:13:39.848576 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
11023 10:13:39.852799 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
11024 10:13:39.853243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
11025 10:13:39.853398 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
11026 10:13:39.853510 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
11027 10:13:39.853642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
11028 10:13:39.853772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
11029 10:13:39.853891 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
11030 10:13:39.854050 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
11031 10:13:39.854165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
11032 10:13:39.854268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
11033 10:13:39.854401 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
11034 10:13:39.854511 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
11035 10:13:39.854635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
11036 10:13:39.854739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
11037 10:13:39.854875 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
11038 10:13:39.855000 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
11039 10:13:39.855134 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
11040 10:13:39.855276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
11041 10:13:39.855400 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
11042 10:13:39.855500 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
11043 10:13:39.855616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
11044 10:13:39.855722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
11045 10:13:39.856026 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
11046 10:13:39.856118 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
11047 10:13:39.856192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
11048 10:13:39.856264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
11049 10:13:39.856371 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
11050 10:13:39.860726 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
11051 10:13:39.861102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
11052 10:13:39.861251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
11053 10:13:39.861374 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
11054 10:13:39.861458 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
11055 10:13:39.861555 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
11056 10:13:39.861637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
11057 10:13:39.861743 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
11058 10:13:39.861835 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
11059 10:13:39.861922 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
11060 10:13:39.862188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
11061 10:13:39.862269 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
11062 10:13:39.862355 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
11063 10:13:39.862430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
11064 10:13:39.862519 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
11065 10:13:39.862782 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
11066 10:13:39.862865 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
11067 10:13:39.862962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
11068 10:13:39.863047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
11069 10:13:39.863139 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
11070 10:13:39.863210 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
11071 10:13:39.863300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
11072 10:13:39.863384 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
11073 10:13:39.863469 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
11074 10:13:39.863554 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
11075 10:13:39.863824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
11076 10:13:39.863895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
11077 10:13:39.863985 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
11078 10:13:39.864070 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
11079 10:13:39.864325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
11080 10:13:39.864399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
11081 10:13:39.864488 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
11082 10:13:39.864559 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
11083 10:13:39.868668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
11084 10:13:39.868945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
11085 10:13:39.869031 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
11086 10:13:39.869166 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
11087 10:13:39.869267 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
11088 10:13:39.869404 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
11089 10:13:39.869506 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
11090 10:13:39.869592 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
11091 10:13:39.869884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
11092 10:13:39.869989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
11093 10:13:39.870092 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
11094 10:13:39.870404 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
11095 10:13:39.870506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
11096 10:13:39.870610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
11097 10:13:39.870917 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
11098 10:13:39.871018 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
11099 10:13:39.871117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
11100 10:13:39.871411 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
11101 10:13:39.871502 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
11102 10:13:39.871602 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
11103 10:13:39.871700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
11104 10:13:39.871990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
11105 10:13:39.872105 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
11106 10:13:39.872206 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
11107 10:13:39.872505 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
11108 10:13:39.876627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
11109 10:13:39.876924 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
11110 10:13:39.877025 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
11111 10:13:39.877123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
11112 10:13:39.877412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
11113 10:13:39.877495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
11114 10:13:39.877585 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
11115 10:13:39.877688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
11116 10:13:39.877976 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
11117 10:13:39.878089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
11118 10:13:39.878183 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
11119 10:13:39.878454 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
11120 10:13:39.878534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
11121 10:13:39.878638 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
11122 10:13:39.878738 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
11123 10:13:39.879043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
11124 10:13:39.879137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
11125 10:13:39.879252 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
11126 10:13:39.879338 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
11127 10:13:39.879625 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
11128 10:13:39.892389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
11129 10:13:39.892700 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
11130 10:13:39.892820 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
11131 10:13:39.892924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
11132 10:13:39.893032 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
11133 10:13:39.893332 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
11134 10:13:39.893431 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
11135 10:13:39.893535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
11136 10:13:39.893634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
11137 10:13:39.893745 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
11138 10:13:39.893997 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
11139 10:13:39.894106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
11140 10:13:39.894195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
11141 10:13:39.894473 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
11142 10:13:39.894573 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
11143 10:13:39.894670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
11144 10:13:39.894980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
11145 10:13:39.895066 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
11146 10:13:39.895162 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
11147 10:13:39.895265 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
11148 10:13:39.895564 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
11149 10:13:39.895681 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
11150 10:13:39.895783 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
11151 10:13:39.896085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
11152 10:13:39.896187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
11153 10:13:39.896495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
11154 10:13:39.896619 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
11155 10:13:39.900629 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
11156 10:13:39.900962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
11157 10:13:39.901073 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
11158 10:13:39.901225 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
11159 10:13:39.901333 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
11160 10:13:39.901431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
11161 10:13:39.901742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
11162 10:13:39.901836 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
11163 10:13:39.901927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
11164 10:13:39.902034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
11165 10:13:39.902148 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
11166 10:13:39.902241 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
11167 10:13:39.902394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
11168 10:13:39.902667 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
11169 10:13:39.902784 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
11170 10:13:39.902883 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
11171 10:13:39.902981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
11172 10:13:39.903072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11173 10:13:39.903361 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11174 10:13:39.903453 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11175 10:13:39.903537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11176 10:13:39.903630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11177 10:13:39.903941 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11178 10:13:39.904042 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11179 10:13:39.904145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11180 10:13:39.904251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11181 10:13:39.904367 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11182 10:13:39.908667 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11183 10:13:39.909067 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11184 10:13:39.909169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11185 10:13:39.909272 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11186 10:13:39.909357 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11187 10:13:39.909541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11188 10:13:39.909863 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11189 10:13:39.909965 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11190 10:13:39.910065 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11191 10:13:39.910375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11192 10:13:39.910556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11193 10:13:39.910697 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11194 10:13:39.910855 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11195 10:13:39.910991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11196 10:13:39.911126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11197 10:13:39.911228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11198 10:13:39.911363 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11199 10:13:39.911467 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11200 10:13:39.911551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11201 10:13:39.911631 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11202 10:13:39.911717 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11203 10:13:39.912007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11204 10:13:39.912118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11205 10:13:39.912231 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11206 10:13:39.912337 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11207 10:13:39.916652 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11208 10:13:39.916971 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11209 10:13:39.917073 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11210 10:13:39.917182 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11211 10:13:39.917300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11212 10:13:39.917438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11213 10:13:39.917691 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11214 10:13:39.917805 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11215 10:13:39.917889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11216 10:13:39.918168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11217 10:13:39.918278 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11218 10:13:39.918368 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11219 10:13:39.918665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11220 10:13:39.918781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11221 10:13:39.918908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11222 10:13:39.919026 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11223 10:13:39.919324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11224 10:13:39.919439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11225 10:13:39.919722 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11226 10:13:39.919816 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11227 10:13:39.919928 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11228 10:13:39.920042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11229 10:13:39.920335 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11230 10:13:39.920444 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11231 10:13:39.924673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11232 10:13:39.925107 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11233 10:13:39.925281 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11234 10:13:39.925433 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11235 10:13:39.925624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11236 10:13:39.925810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11237 10:13:39.925982 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11238 10:13:39.926152 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11239 10:13:39.926355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11240 10:13:39.926517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11241 10:13:39.926672 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11242 10:13:39.926832 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11243 10:13:39.926968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11244 10:13:39.927153 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11245 10:13:39.927310 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11246 10:13:39.927466 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11247 10:13:39.927627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11248 10:13:39.927782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11249 10:13:39.927970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11250 10:13:39.928121 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11251 10:13:39.928267 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11252 10:13:39.928409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11253 10:13:39.928556 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11254 10:13:39.928674 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11255 10:13:39.928788 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11256 10:13:39.928925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11257 10:13:39.929043 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11258 10:13:39.929157 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11259 10:13:39.932688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11260 10:13:39.932974 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11261 10:13:39.933054 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11262 10:13:39.941361 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11263 10:13:39.941675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11264 10:13:39.941771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11265 10:13:39.941871 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11266 10:13:39.941954 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11267 10:13:39.942223 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11268 10:13:39.942309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11269 10:13:39.942381 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11270 10:13:39.942471 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11271 10:13:39.942729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11272 10:13:39.942800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11273 10:13:39.942874 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11274 10:13:39.942963 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11275 10:13:39.943033 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11276 10:13:39.943122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11277 10:13:39.943386 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11278 10:13:39.943457 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11279 10:13:39.943549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11280 10:13:39.943633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11281 10:13:39.943885 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11282 10:13:39.943955 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11283 10:13:39.944043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11284 10:13:39.944303 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11285 10:13:39.944403 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11286 10:13:39.944498 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11287 10:13:39.948704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11288 10:13:39.949122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11289 10:13:39.949303 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11290 10:13:39.949466 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11291 10:13:39.949663 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11292 10:13:39.949834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11293 10:13:39.949999 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11294 10:13:39.950199 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11295 10:13:39.950370 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11296 10:13:39.950537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11297 10:13:39.950694 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11298 10:13:39.950848 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11299 10:13:39.951003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11300 10:13:39.951191 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11301 10:13:39.951352 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11302 10:13:39.951507 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11303 10:13:39.951662 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11304 10:13:39.951820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11305 10:13:39.951975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11306 10:13:39.952134 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11307 10:13:39.952337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11308 10:13:39.952508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11309 10:13:39.952632 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11310 10:13:39.952746 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11311 10:13:39.952858 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11312 10:13:39.952971 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11313 10:13:39.953083 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11314 10:13:39.953219 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11315 10:13:39.956716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11316 10:13:39.957154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11317 10:13:39.957339 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11318 10:13:39.957523 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11319 10:13:39.957718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11320 10:13:39.957860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11321 10:13:39.958035 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11322 10:13:39.958192 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11323 10:13:39.958321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11324 10:13:39.958512 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11325 10:13:39.958674 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11326 10:13:39.958860 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11327 10:13:39.959037 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11328 10:13:39.959186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11329 10:13:39.959347 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11330 10:13:39.959505 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11331 10:13:39.959664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11332 10:13:39.959866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11333 10:13:39.960037 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11334 10:13:39.960223 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11335 10:13:39.960382 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11336 10:13:39.960509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11337 10:13:39.960625 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11338 10:13:39.960765 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11339 10:13:39.960884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11340 10:13:39.960996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11341 10:13:39.961108 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11342 10:13:39.961219 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11343 10:13:39.964703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11344 10:13:39.965162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11345 10:13:39.965357 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11346 10:13:39.965534 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11347 10:13:39.965726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11348 10:13:39.965880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11349 10:13:39.966102 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11350 10:13:39.966280 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11351 10:13:39.966409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11352 10:13:39.966525 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11353 10:13:39.966664 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11354 10:13:39.966783 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11355 10:13:39.967965 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11356 10:13:39.968127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11357 10:13:39.968289 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11358 10:13:39.968421 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11359 10:13:39.968596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11360 10:13:39.968741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11361 10:13:39.968882 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11362 10:13:39.969021 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11363 10:13:39.969159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11364 10:13:39.969299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11365 10:13:39.969438 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11366 10:13:39.969579 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11367 10:13:39.969735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11368 10:13:39.969876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11369 10:13:39.970016 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11370 10:13:39.970366 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11371 10:13:39.970504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11372 10:13:39.970651 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11373 10:13:39.970792 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11374 10:13:39.972910 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11375 10:13:39.973116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11376 10:13:39.973324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11377 10:13:39.973494 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11378 10:13:39.973687 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11379 10:13:39.973898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11380 10:13:39.974088 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11381 10:13:39.974259 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11382 10:13:39.974438 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11383 10:13:39.974576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11384 10:13:39.974723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11385 10:13:39.974890 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11386 10:13:39.975081 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11387 10:13:39.975275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11388 10:13:39.975433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11389 10:13:39.975586 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11390 10:13:39.975729 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11391 10:13:39.975844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11392 10:13:39.975955 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11393 10:13:39.976167 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11394 10:13:39.976307 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11395 10:13:39.976422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11396 10:13:39.987922 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11397 10:13:39.988367 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11398 10:13:39.988555 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11399 10:13:39.988687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11400 10:13:39.988879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11401 10:13:39.989082 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11402 10:13:39.989297 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11403 10:13:39.989455 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11404 10:13:39.989615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11405 10:13:39.989801 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11406 10:13:39.989971 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11407 10:13:39.990133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11408 10:13:39.990320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11409 10:13:39.990484 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11410 10:13:39.990636 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11411 10:13:39.990796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11412 10:13:39.990987 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11413 10:13:39.991149 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11414 10:13:39.991299 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11415 10:13:39.991464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11416 10:13:39.991642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11417 10:13:39.991797 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11418 10:13:39.991943 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11419 10:13:39.992147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11420 10:13:39.992321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11421 10:13:39.993131 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11422 10:13:39.993266 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11423 10:13:39.993384 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11424 10:13:39.993498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11425 10:13:39.993611 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11426 10:13:39.993743 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11427 10:13:39.993857 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11428 10:13:39.996679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11429 10:13:39.997113 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11430 10:13:39.997300 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11431 10:13:39.997491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11432 10:13:39.997668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11433 10:13:39.997860 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11434 10:13:39.998028 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11435 10:13:39.998239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11436 10:13:39.998453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11437 10:13:39.998616 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11438 10:13:39.998790 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11439 10:13:39.998978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11440 10:13:39.999173 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11441 10:13:39.999340 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11442 10:13:39.999535 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11443 10:13:39.999705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11444 10:13:39.999927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11445 10:13:40.000116 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11446 10:13:40.000280 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11447 10:13:40.000437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11448 10:13:40.000587 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11449 10:13:40.000728 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11450 10:13:40.000844 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11451 10:13:40.000956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11452 10:13:40.001067 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11453 10:13:40.004703 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11454 10:13:40.005141 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11455 10:13:40.005337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11456 10:13:40.005539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11457 10:13:40.005767 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11458 10:13:40.005910 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11459 10:13:40.006053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11460 10:13:40.006221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11461 10:13:40.006418 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11462 10:13:40.006624 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11463 10:13:40.006796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11464 10:13:40.006958 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11465 10:13:40.007121 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11466 10:13:40.007282 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11467 10:13:40.007441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11468 10:13:40.007642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11469 10:13:40.007811 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11470 10:13:40.007963 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11471 10:13:40.008124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11472 10:13:40.008281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11473 10:13:40.008431 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11474 10:13:40.008583 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11475 10:13:40.008701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11476 10:13:40.008843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11477 10:13:40.008961 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11478 10:13:40.009074 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11479 10:13:40.009186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11480 10:13:40.009299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11481 10:13:40.009413 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11482 10:13:40.012751 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11483 10:13:40.013192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11484 10:13:40.013396 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11485 10:13:40.013578 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11486 10:13:40.013756 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11487 10:13:40.013928 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11488 10:13:40.014123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11489 10:13:40.014270 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11490 10:13:40.014407 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11491 10:13:40.014537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11492 10:13:40.014683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11493 10:13:40.014868 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11494 10:13:40.015031 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11495 10:13:40.015185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11496 10:13:40.015337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11497 10:13:40.015493 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11498 10:13:40.015684 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11499 10:13:40.015848 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11500 10:13:40.016008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11501 10:13:40.016165 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11502 10:13:40.016324 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11503 10:13:40.016499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11504 10:13:40.016674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11505 10:13:40.016802 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11506 10:13:40.016918 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11507 10:13:40.017032 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11508 10:13:40.017144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11509 10:13:40.017257 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11510 10:13:40.017369 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11511 10:13:40.020924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11512 10:13:40.021151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11513 10:13:40.021331 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11514 10:13:40.021518 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11515 10:13:40.021687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11516 10:13:40.021804 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11517 10:13:40.021947 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11518 10:13:40.022068 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11519 10:13:40.022177 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11520 10:13:40.022297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11521 10:13:40.022406 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11522 10:13:40.022511 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11523 10:13:40.022855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11524 10:13:40.022960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11525 10:13:40.023247 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11526 10:13:40.023349 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11527 10:13:40.023432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11528 10:13:40.023535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11529 10:13:40.023624 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11530 10:13:40.036369 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11531 10:13:40.036472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11532 10:13:40.036754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11533 10:13:40.036848 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11534 10:13:40.036947 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11535 10:13:40.037221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11536 10:13:40.037311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11537 10:13:40.037411 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11538 10:13:40.037510 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11539 10:13:40.037609 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11540 10:13:40.037924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11541 10:13:40.038026 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11542 10:13:40.038125 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11543 10:13:40.038421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11544 10:13:40.038626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11545 10:13:40.038864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11546 10:13:40.039065 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11547 10:13:40.039233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11548 10:13:40.039434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11549 10:13:40.039701 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11550 10:13:40.039860 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11551 10:13:40.040004 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11552 10:13:40.040195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11553 10:13:40.040348 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11554 10:13:40.040497 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11555 10:13:40.040628 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11556 10:13:40.040768 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11557 10:13:40.040886 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11558 10:13:40.040998 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11559 10:13:40.044709 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11560 10:13:40.045153 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11561 10:13:40.045344 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11562 10:13:40.045511 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11563 10:13:40.045687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11564 10:13:40.045903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11565 10:13:40.046182 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11566 10:13:40.046412 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11567 10:13:40.046594 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11568 10:13:40.046797 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11569 10:13:40.046984 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11570 10:13:40.047121 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11571 10:13:40.047274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11572 10:13:40.047427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11573 10:13:40.047589 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11574 10:13:40.047814 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11575 10:13:40.047994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11576 10:13:40.048162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11577 10:13:40.048372 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11578 10:13:40.048544 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11579 10:13:40.048686 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11580 10:13:40.048803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11581 10:13:40.048914 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11582 10:13:40.049025 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11583 10:13:40.049134 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11584 10:13:40.049243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11585 10:13:40.049353 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11586 10:13:40.049462 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11587 10:13:40.049596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11588 10:13:40.052707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11589 10:13:40.053140 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11590 10:13:40.053313 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11591 10:13:40.053474 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11592 10:13:40.053640 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11593 10:13:40.053786 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11594 10:13:40.053933 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11595 10:13:40.054079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11596 10:13:40.054237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11597 10:13:40.054366 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11598 10:13:40.054509 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11599 10:13:40.054634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11600 10:13:40.054783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11601 10:13:40.054971 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11602 10:13:40.055130 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11603 10:13:40.055270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11604 10:13:40.055413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11605 10:13:40.055555 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11606 10:13:40.055676 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11607 10:13:40.055819 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11608 10:13:40.055961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11609 10:13:40.056110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11610 10:13:40.056268 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11611 10:13:40.056426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11612 10:13:40.056582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11613 10:13:40.056702 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11614 10:13:40.056818 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11615 10:13:40.056930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11616 10:13:40.057042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11617 10:13:40.057154 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11618 10:13:40.060887 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11619 10:13:40.061081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11620 10:13:40.061471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11621 10:13:40.061639 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11622 10:13:40.061807 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11623 10:13:40.061968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11624 10:13:40.062122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11625 10:13:40.062304 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11626 10:13:40.062459 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11627 10:13:40.062616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11628 10:13:40.062777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11629 10:13:40.062929 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11630 10:13:40.063071 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11631 10:13:40.063253 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11632 10:13:40.063402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11633 10:13:40.063550 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11634 10:13:40.063697 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11635 10:13:40.063841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11636 10:13:40.063992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11637 10:13:40.064143 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11638 10:13:40.064297 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11639 10:13:40.064447 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11640 10:13:40.064598 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11641 10:13:40.064716 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11642 10:13:40.064834 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11643 10:13:40.064945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11644 10:13:40.065058 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11645 10:13:40.065170 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11646 10:13:40.065282 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11647 10:13:40.065394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11648 10:13:40.065506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11649 10:13:40.065617 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11650 10:13:40.068686 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11651 10:13:40.069085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11652 10:13:40.069260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11653 10:13:40.069445 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11654 10:13:40.069604 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11655 10:13:40.069807 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11656 10:13:40.069968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11657 10:13:40.070123 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11658 10:13:40.070308 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11659 10:13:40.070455 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11660 10:13:40.070570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11661 10:13:40.070682 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11662 10:13:40.070857 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11663 10:13:40.070977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11664 10:13:40.083090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11665 10:13:40.083560 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11666 10:13:40.083707 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11667 10:13:40.083827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11668 10:13:40.083954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11669 10:13:40.084106 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11670 10:13:40.084249 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11671 10:13:40.084387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11672 10:13:40.084539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11673 10:13:40.084692 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11674 10:13:40.084858 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11675 10:13:40.085018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11676 10:13:40.085175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11677 10:13:40.085362 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11678 10:13:40.085515 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11679 10:13:40.085681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11680 10:13:40.085835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11681 10:13:40.085988 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11682 10:13:40.086140 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11683 10:13:40.086329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11684 10:13:40.086491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11685 10:13:40.086658 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11686 10:13:40.086825 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11687 10:13:40.086988 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11688 10:13:40.087149 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11689 10:13:40.087316 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11690 10:13:40.087481 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11691 10:13:40.087681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11692 10:13:40.087851 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11693 10:13:40.088016 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11694 10:13:40.088174 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11695 10:13:40.088326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11696 10:13:40.088477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11697 10:13:40.088815 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11698 10:13:40.088939 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11699 10:13:40.089055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11700 10:13:40.089168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11701 10:13:40.089281 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11702 10:13:40.089394 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11703 10:13:40.089508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11704 10:13:40.089621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11705 10:13:40.089749 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11706 10:13:40.089865 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11707 10:13:40.089975 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11708 10:13:40.092732 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11709 10:13:40.093195 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11710 10:13:40.093386 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11711 10:13:40.093547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11712 10:13:40.093722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11713 10:13:40.093915 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11714 10:13:40.094080 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11715 10:13:40.094241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11716 10:13:40.094400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11717 10:13:40.094588 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11718 10:13:40.094752 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11719 10:13:40.094916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11720 10:13:40.095076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11721 10:13:40.095235 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11722 10:13:40.095392 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11723 10:13:40.095585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11724 10:13:40.095753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11725 10:13:40.095919 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11726 10:13:40.096078 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11727 10:13:40.096244 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11728 10:13:40.096405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11729 10:13:40.096547 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11730 10:13:40.096690 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11731 10:13:40.096808 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11732 10:13:40.096921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11733 10:13:40.097035 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11734 10:13:40.097147 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11735 10:13:40.097259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11736 10:13:40.100837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11737 10:13:40.101361 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11738 10:13:40.101543 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11739 10:13:40.101703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11740 10:13:40.101995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11741 10:13:40.102184 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11742 10:13:40.102314 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11743 10:13:40.102439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11744 10:13:40.102574 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11745 10:13:40.102721 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11746 10:13:40.102940 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11747 10:13:40.103100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11748 10:13:40.103263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11749 10:13:40.103418 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11750 10:13:40.103604 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11751 10:13:40.103865 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11752 10:13:40.104040 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11753 10:13:40.104200 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11754 10:13:40.104349 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11755 10:13:40.104582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11756 10:13:40.104742 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11757 10:13:40.104889 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11758 10:13:40.105030 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11759 10:13:40.105177 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11760 10:13:40.105327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11761 10:13:40.108751 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11762 10:13:40.109171 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11763 10:13:40.109346 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11764 10:13:40.109481 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11765 10:13:40.109667 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11766 10:13:40.109828 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11767 10:13:40.109996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11768 10:13:40.110140 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11769 10:13:40.110304 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11770 10:13:40.110442 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11771 10:13:40.110602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11772 10:13:40.110831 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11773 10:13:40.110995 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11774 10:13:40.111151 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11775 10:13:40.111339 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11776 10:13:40.111488 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11777 10:13:40.111631 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11778 10:13:40.111893 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11779 10:13:40.112070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11780 10:13:40.112214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11781 10:13:40.112403 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11782 10:13:40.112543 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11783 10:13:40.112662 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11784 10:13:40.112773 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11785 10:13:40.112909 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11786 10:13:40.116769 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11787 10:13:40.117118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11788 10:13:40.117262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11789 10:13:40.117443 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11790 10:13:40.117565 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11791 10:13:40.117734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11792 10:13:40.117859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11793 10:13:40.118000 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11794 10:13:40.118116 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11795 10:13:40.118251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11796 10:13:40.118482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11797 10:13:40.118630 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11798 10:13:40.131545 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11799 10:13:40.131812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11800 10:13:40.132239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11801 10:13:40.132436 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11802 10:13:40.132570 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11803 10:13:40.132694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11804 10:13:40.132852 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11805 10:13:40.132999 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11806 10:13:40.133123 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11807 10:13:40.133289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11808 10:13:40.133534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11809 10:13:40.133734 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11810 10:13:40.133903 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11811 10:13:40.134058 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11812 10:13:40.134356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11813 10:13:40.134533 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11814 10:13:40.134717 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11815 10:13:40.134916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11816 10:13:40.135114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11817 10:13:40.135287 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11818 10:13:40.135443 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11819 10:13:40.135624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11820 10:13:40.135761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11821 10:13:40.135929 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11822 10:13:40.136098 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11823 10:13:40.136260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11824 10:13:40.136416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11825 10:13:40.136543 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11826 10:13:40.136698 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11827 10:13:40.136841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11828 10:13:40.136993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11829 10:13:40.137110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11830 10:13:40.137246 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11831 10:13:40.137591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11832 10:13:40.141046 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11833 10:13:40.141482 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11834 10:13:40.141683 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11835 10:13:40.141829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11836 10:13:40.142024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11837 10:13:40.142192 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11838 10:13:40.142349 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11839 10:13:40.142667 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11840 10:13:40.142823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11841 10:13:40.143027 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11842 10:13:40.143229 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11843 10:13:40.143408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11844 10:13:40.143670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11845 10:13:40.143896 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11846 10:13:40.144053 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11847 10:13:40.144223 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11848 10:13:40.144382 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11849 10:13:40.144557 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11850 10:13:40.144707 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11851 10:13:40.144829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11852 10:13:40.144946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11853 10:13:40.145059 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11854 10:13:40.145261 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11855 10:13:40.148964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11856 10:13:40.149357 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11857 10:13:40.149524 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11858 10:13:40.149679 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11859 10:13:40.149851 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11860 10:13:40.149974 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11861 10:13:40.150113 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11862 10:13:40.150254 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11863 10:13:40.150414 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11864 10:13:40.150560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11865 10:13:40.150752 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11866 10:13:40.150895 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11867 10:13:40.151065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11868 10:13:40.151247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11869 10:13:40.151446 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11870 10:13:40.151598 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11871 10:13:40.151806 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11872 10:13:40.151989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11873 10:13:40.152152 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11874 10:13:40.152410 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11875 10:13:40.152581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11876 10:13:40.152709 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11877 10:13:40.152846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11878 10:13:40.156990 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11879 10:13:40.157381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11880 10:13:40.157556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11881 10:13:40.157776 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11882 10:13:40.157942 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11883 10:13:40.158098 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11884 10:13:40.158289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11885 10:13:40.158448 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11886 10:13:40.158609 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11887 10:13:40.158794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11888 10:13:40.158955 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11889 10:13:40.159118 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11890 10:13:40.159277 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11891 10:13:40.159453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11892 10:13:40.159608 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11893 10:13:40.159780 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11894 10:13:40.159977 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11895 10:13:40.160223 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11896 10:13:40.160420 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11897 10:13:40.160604 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11898 10:13:40.160746 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11899 10:13:40.160862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11900 10:13:40.161002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11901 10:13:40.161121 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11902 10:13:40.161234 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11903 10:13:40.164914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11904 10:13:40.165343 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11905 10:13:40.165561 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11906 10:13:40.165757 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11907 10:13:40.165986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11908 10:13:40.166164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11909 10:13:40.166306 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11910 10:13:40.166453 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11911 10:13:40.166602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11912 10:13:40.166803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11913 10:13:40.167006 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11914 10:13:40.167184 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11915 10:13:40.167348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11916 10:13:40.167487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11917 10:13:40.167677 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11918 10:13:40.167868 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11919 10:13:40.168065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11920 10:13:40.168269 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11921 10:13:40.168463 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11922 10:13:40.168644 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11923 10:13:40.168784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11924 10:13:40.168931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11925 10:13:40.169055 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11926 10:13:40.169172 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11927 10:13:40.169285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
11928 10:13:40.169399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
11929 10:13:40.169512 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
11930 10:13:40.172822 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
11931 10:13:40.173204 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
11932 10:13:40.184221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
11933 10:13:40.184648 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
11934 10:13:40.184849 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
11935 10:13:40.185049 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
11936 10:13:40.185191 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
11937 10:13:40.185314 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
11938 10:13:40.185457 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
11939 10:13:40.185583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
11940 10:13:40.185719 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
11941 10:13:40.185865 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
11942 10:13:40.186039 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
11943 10:13:40.186198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
11944 10:13:40.186381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
11945 10:13:40.186532 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
11946 10:13:40.186697 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
11947 10:13:40.186910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
11948 10:13:40.187077 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
11949 10:13:40.187211 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
11950 10:13:40.187343 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
11951 10:13:40.187504 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
11952 10:13:40.187658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
11953 10:13:40.187814 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
11954 10:13:40.187978 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
11955 10:13:40.188125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
11956 10:13:40.188270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
11957 10:13:40.188411 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
11958 10:13:40.188597 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
11959 10:13:40.188752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
11960 10:13:40.188870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
11961 10:13:40.188981 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
11962 10:13:40.192664 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
11963 10:13:40.192980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
11964 10:13:40.193070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
11965 10:13:40.193157 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
11966 10:13:40.193237 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
11967 10:13:40.193355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
11968 10:13:40.193653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
11969 10:13:40.193737 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
11970 10:13:40.193840 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
11971 10:13:40.193937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
11972 10:13:40.194055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
11973 10:13:40.194376 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
11974 10:13:40.194576 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
11975 10:13:40.194773 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
11976 10:13:40.194953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
11977 10:13:40.195135 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
11978 10:13:40.195296 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
11979 10:13:40.195427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
11980 10:13:40.195549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
11981 10:13:40.195717 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
11982 10:13:40.195914 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
11983 10:13:40.196051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
11984 10:13:40.196201 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
11985 10:13:40.196328 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
11986 10:13:40.196453 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
11987 10:13:40.196614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
11988 10:13:40.196774 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
11989 10:13:40.196894 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
11990 10:13:40.200808 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
11991 10:13:40.201115 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
11992 10:13:40.201232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
11993 10:13:40.201352 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
11994 10:13:40.201660 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
11995 10:13:40.201970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
11996 10:13:40.202071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
11997 10:13:40.202366 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
11998 10:13:40.202454 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
11999 10:13:40.202568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
12000 10:13:40.202695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
12001 10:13:40.203009 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
12002 10:13:40.203120 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
12003 10:13:40.203226 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
12004 10:13:40.203583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
12005 10:13:40.203912 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
12006 10:13:40.204108 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
12007 10:13:40.204291 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
12008 10:13:40.204449 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
12009 10:13:40.204633 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
12010 10:13:40.208669 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
12011 10:13:40.208998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
12012 10:13:40.209097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
12013 10:13:40.209205 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
12014 10:13:40.209281 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
12015 10:13:40.209389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
12016 10:13:40.209495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
12017 10:13:40.209583 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
12018 10:13:40.209975 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
12019 10:13:40.210145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
12020 10:13:40.210356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
12021 10:13:40.210536 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
12022 10:13:40.210716 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
12023 10:13:40.210903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
12024 10:13:40.211087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
12025 10:13:40.211243 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
12026 10:13:40.211368 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
12027 10:13:40.211502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
12028 10:13:40.211626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
12029 10:13:40.211795 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
12030 10:13:40.211916 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
12031 10:13:40.212022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
12032 10:13:40.212133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
12033 10:13:40.212244 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
12034 10:13:40.212356 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
12035 10:13:40.212487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
12036 10:13:40.212578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
12037 10:13:40.212662 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
12038 10:13:40.212746 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
12039 10:13:40.212829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
12040 10:13:40.216664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
12041 10:13:40.217110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
12042 10:13:40.217311 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
12043 10:13:40.217463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
12044 10:13:40.217640 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
12045 10:13:40.217830 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
12046 10:13:40.217989 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
12047 10:13:40.218182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
12048 10:13:40.218329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
12049 10:13:40.218486 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
12050 10:13:40.218652 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
12051 10:13:40.218898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
12052 10:13:40.219099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
12053 10:13:40.219270 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
12054 10:13:40.219434 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
12055 10:13:40.219596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
12056 10:13:40.219792 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
12057 10:13:40.219957 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
12058 10:13:40.220115 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
12059 10:13:40.220238 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
12060 10:13:40.220355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
12061 10:13:40.220468 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
12062 10:13:40.220606 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
12063 10:13:40.220726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
12064 10:13:40.220841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
12065 10:13:40.220954 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
12066 10:13:40.233684 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
12067 10:13:40.234011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
12068 10:13:40.234212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
12069 10:13:40.234508 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
12070 10:13:40.234674 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
12071 10:13:40.234844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
12072 10:13:40.234983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
12073 10:13:40.235178 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
12074 10:13:40.235354 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
12075 10:13:40.235496 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
12076 10:13:40.235633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
12077 10:13:40.235822 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
12078 10:13:40.236029 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
12079 10:13:40.236175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
12080 10:13:40.236321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
12081 10:13:40.236456 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
12082 10:13:40.236568 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
12083 10:13:40.236678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
12084 10:13:40.236812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
12085 10:13:40.236927 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
12086 10:13:40.237037 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
12087 10:13:40.240684 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
12088 10:13:40.241121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
12089 10:13:40.241281 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
12090 10:13:40.241421 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
12091 10:13:40.241567 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
12092 10:13:40.241711 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
12093 10:13:40.241845 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
12094 10:13:40.241982 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
12095 10:13:40.242083 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
12096 10:13:40.242157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
12097 10:13:40.242237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
12098 10:13:40.242311 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
12099 10:13:40.242386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
12100 10:13:40.242474 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
12101 10:13:40.242551 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
12102 10:13:40.242644 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
12103 10:13:40.242730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
12104 10:13:40.242848 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
12105 10:13:40.242973 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
12106 10:13:40.243070 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
12107 10:13:40.243176 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
12108 10:13:40.243282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
12109 10:13:40.243367 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
12110 10:13:40.243465 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
12111 10:13:40.243774 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
12112 10:13:40.243872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
12113 10:13:40.244000 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
12114 10:13:40.244083 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
12115 10:13:40.244196 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
12116 10:13:40.244301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
12117 10:13:40.244397 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
12118 10:13:40.244488 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
12119 10:13:40.248625 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
12120 10:13:40.248917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
12121 10:13:40.249045 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
12122 10:13:40.249190 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
12123 10:13:40.249363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
12124 10:13:40.249526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
12125 10:13:40.249719 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
12126 10:13:40.249874 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
12127 10:13:40.250064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
12128 10:13:40.250221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
12129 10:13:40.250407 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
12130 10:13:40.250593 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
12131 10:13:40.250770 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
12132 10:13:40.250925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
12133 10:13:40.251082 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
12134 10:13:40.251257 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
12135 10:13:40.251387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
12136 10:13:40.251507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
12137 10:13:40.251627 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
12138 10:13:40.251782 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
12139 10:13:40.251961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
12140 10:13:40.252115 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
12141 10:13:40.252256 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
12142 10:13:40.252404 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
12143 10:13:40.252573 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
12144 10:13:40.252695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
12145 10:13:40.252831 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
12146 10:13:40.256687 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
12147 10:13:40.257106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
12148 10:13:40.257303 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
12149 10:13:40.257507 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
12150 10:13:40.257723 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
12151 10:13:40.257894 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
12152 10:13:40.258059 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
12153 10:13:40.258206 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
12154 10:13:40.258387 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
12155 10:13:40.258569 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
12156 10:13:40.258735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
12157 10:13:40.258932 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
12158 10:13:40.259103 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
12159 10:13:40.259290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
12160 10:13:40.259449 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
12161 10:13:40.259608 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
12162 10:13:40.259761 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
12163 10:13:40.259994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
12164 10:13:40.260156 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
12165 10:13:40.260327 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
12166 10:13:40.260539 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
12167 10:13:40.260723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
12168 10:13:40.260877 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
12169 10:13:40.261016 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
12170 10:13:40.261130 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
12171 10:13:40.261243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
12172 10:13:40.261353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12173 10:13:40.261463 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12174 10:13:40.261572 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12175 10:13:40.261723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12176 10:13:40.264666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12177 10:13:40.265099 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12178 10:13:40.265288 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12179 10:13:40.265446 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12180 10:13:40.265608 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12181 10:13:40.265817 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12182 10:13:40.266012 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12183 10:13:40.266227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12184 10:13:40.266367 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12185 10:13:40.266491 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12186 10:13:40.266664 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12187 10:13:40.266800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12188 10:13:40.266933 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12189 10:13:40.267058 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12190 10:13:40.267178 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12191 10:13:40.267298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12192 10:13:40.267415 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12193 10:13:40.267540 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12194 10:13:40.267636 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12195 10:13:40.267725 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12196 10:13:40.267828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12197 10:13:40.267935 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12198 10:13:40.268024 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12199 10:13:40.268110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12200 10:13:40.279307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12201 10:13:40.279634 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12202 10:13:40.279743 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12203 10:13:40.279854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12204 10:13:40.279969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12205 10:13:40.280086 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12206 10:13:40.280260 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12207 10:13:40.280391 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12208 10:13:40.280558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12209 10:13:40.280969 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12210 10:13:40.281161 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12211 10:13:40.281357 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12212 10:13:40.281557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12213 10:13:40.281724 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12214 10:13:40.281866 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12215 10:13:40.282021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12216 10:13:40.282206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12217 10:13:40.282365 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12218 10:13:40.282518 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12219 10:13:40.282671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12220 10:13:40.282856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12221 10:13:40.283012 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12222 10:13:40.283164 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12223 10:13:40.283312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12224 10:13:40.283462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12225 10:13:40.283612 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12226 10:13:40.283764 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12227 10:13:40.283881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12228 10:13:40.283994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12229 10:13:40.284136 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12230 10:13:40.284285 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12231 10:13:40.284457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12232 10:13:40.284654 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12233 10:13:40.284792 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12234 10:13:40.284907 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12235 10:13:40.285019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12236 10:13:40.285128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12237 10:13:40.285238 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12238 10:13:40.288704 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12239 10:13:40.289243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12240 10:13:40.289453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12241 10:13:40.289622 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12242 10:13:40.289786 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12243 10:13:40.290000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12244 10:13:40.290191 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12245 10:13:40.290347 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12246 10:13:40.290490 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12247 10:13:40.290618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12248 10:13:40.290740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12249 10:13:40.290883 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12250 10:13:40.291004 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12251 10:13:40.291124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12252 10:13:40.291236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12253 10:13:40.291352 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12254 10:13:40.291485 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12255 10:13:40.291642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12256 10:13:40.291767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12257 10:13:40.291878 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12258 10:13:40.292039 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12259 10:13:40.292197 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12260 10:13:40.292347 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12261 10:13:40.292519 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12262 10:13:40.292643 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12263 10:13:40.292739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12264 10:13:40.292827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12265 10:13:40.292917 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12266 10:13:40.293006 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12267 10:13:40.293092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12268 10:13:40.296696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12269 10:13:40.297095 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12270 10:13:40.297324 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12271 10:13:40.297499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12272 10:13:40.297730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12273 10:13:40.297910 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12274 10:13:40.298076 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12275 10:13:40.298258 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12276 10:13:40.298452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12277 10:13:40.298620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12278 10:13:40.298819 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12279 10:13:40.298976 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12280 10:13:40.299142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12281 10:13:40.299347 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12282 10:13:40.299518 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12283 10:13:40.299692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12284 10:13:40.299850 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12285 10:13:40.300008 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12286 10:13:40.300171 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12287 10:13:40.300339 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12288 10:13:40.300550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12289 10:13:40.300714 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12290 10:13:40.300845 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12291 10:13:40.300974 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12292 10:13:40.301101 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12293 10:13:40.301229 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12294 10:13:40.301354 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12295 10:13:40.301507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12296 10:13:40.304780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12297 10:13:40.305191 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12298 10:13:40.305373 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12299 10:13:40.305540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12300 10:13:40.305753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12301 10:13:40.305945 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12302 10:13:40.306111 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12303 10:13:40.306276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12304 10:13:40.306464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12305 10:13:40.306641 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12306 10:13:40.306809 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12307 10:13:40.307003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12308 10:13:40.307187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12309 10:13:40.307355 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12310 10:13:40.307538 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12311 10:13:40.307720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12312 10:13:40.307924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12313 10:13:40.308125 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12314 10:13:40.308308 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12315 10:13:40.308478 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12316 10:13:40.308618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12317 10:13:40.308777 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12318 10:13:40.308912 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12319 10:13:40.309039 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12320 10:13:40.309163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12321 10:13:40.309288 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12322 10:13:40.309413 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12323 10:13:40.309537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12324 10:13:40.312671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12325 10:13:40.313013 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12326 10:13:40.313136 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12327 10:13:40.313283 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12328 10:13:40.313408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12329 10:13:40.313561 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12330 10:13:40.313714 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12331 10:13:40.313856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12332 10:13:40.313972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12333 10:13:40.314082 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12334 10:13:40.325604 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12335 10:13:40.325979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12336 10:13:40.326111 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12337 10:13:40.326263 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12338 10:13:40.326421 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12339 10:13:40.326528 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12340 10:13:40.326660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12341 10:13:40.326774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12342 10:13:40.326937 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12343 10:13:40.327061 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12344 10:13:40.327217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12345 10:13:40.327340 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12346 10:13:40.327504 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12347 10:13:40.327648 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12348 10:13:40.327783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12349 10:13:40.327901 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12350 10:13:40.328015 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12351 10:13:40.328154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12352 10:13:40.328315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12353 10:13:40.328438 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12354 10:13:40.328546 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12355 10:13:40.328636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12356 10:13:40.328743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12357 10:13:40.332729 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12358 10:13:40.333198 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12359 10:13:40.333410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12360 10:13:40.333590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12361 10:13:40.333778 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12362 10:13:40.333974 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12363 10:13:40.334160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12364 10:13:40.334328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12365 10:13:40.334487 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12366 10:13:40.334632 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12367 10:13:40.334768 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12368 10:13:40.334956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12369 10:13:40.335088 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12370 10:13:40.335215 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12371 10:13:40.335394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12372 10:13:40.335549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12373 10:13:40.335714 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12374 10:13:40.335857 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12375 10:13:40.336046 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12376 10:13:40.336210 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12377 10:13:40.336365 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12378 10:13:40.336510 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12379 10:13:40.336627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12380 10:13:40.336737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12381 10:13:40.336844 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12382 10:13:40.336952 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12383 10:13:40.337085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12384 10:13:40.337199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12385 10:13:40.337308 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12386 10:13:40.337418 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12387 10:13:40.340672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12388 10:13:40.341101 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12389 10:13:40.341280 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12390 10:13:40.341468 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12391 10:13:40.341634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12392 10:13:40.341837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12393 10:13:40.341992 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12394 10:13:40.342134 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12395 10:13:40.342252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12396 10:13:40.342445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12397 10:13:40.342620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12398 10:13:40.342762 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12399 10:13:40.342897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12400 10:13:40.343079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12401 10:13:40.343237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12402 10:13:40.343386 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12403 10:13:40.343535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12404 10:13:40.343674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12405 10:13:40.343856 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12406 10:13:40.343997 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12407 10:13:40.344117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12408 10:13:40.344258 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12409 10:13:40.344417 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12410 10:13:40.344624 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12411 10:13:40.344750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12412 10:13:40.344861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12413 10:13:40.344973 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12414 10:13:40.345084 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12415 10:13:40.348671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12416 10:13:40.349137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12417 10:13:40.349338 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12418 10:13:40.349487 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12419 10:13:40.349635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12420 10:13:40.349829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12421 10:13:40.349985 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12422 10:13:40.350132 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12423 10:13:40.350286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12424 10:13:40.350441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12425 10:13:40.350623 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12426 10:13:40.350778 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12427 10:13:40.350923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12428 10:13:40.351065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12429 10:13:40.351213 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12430 10:13:40.351417 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12431 10:13:40.351618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12432 10:13:40.351821 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12433 10:13:40.351980 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12434 10:13:40.352149 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12435 10:13:40.352351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12436 10:13:40.352508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12437 10:13:40.352625 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12438 10:13:40.352735 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12439 10:13:40.352844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12440 10:13:40.352952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12441 10:13:40.353063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12442 10:13:40.353194 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12443 10:13:40.356690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12444 10:13:40.357131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12445 10:13:40.357309 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12446 10:13:40.357469 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12447 10:13:40.357663 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12448 10:13:40.357827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12449 10:13:40.357976 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12450 10:13:40.358133 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12451 10:13:40.358309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12452 10:13:40.358431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12453 10:13:40.358549 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12454 10:13:40.358663 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12455 10:13:40.358772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12456 10:13:40.358908 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12457 10:13:40.359025 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12458 10:13:40.359133 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12459 10:13:40.359239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12460 10:13:40.359356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12461 10:13:40.359472 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12462 10:13:40.359592 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12463 10:13:40.359728 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12464 10:13:40.359844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12465 10:13:40.359942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12466 10:13:40.360047 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12467 10:13:40.360142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12468 10:13:40.371801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12469 10:13:40.372234 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12470 10:13:40.372431 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12471 10:13:40.372571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12472 10:13:40.372749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12473 10:13:40.372909 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12474 10:13:40.373068 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12475 10:13:40.373246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12476 10:13:40.373388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12477 10:13:40.373535 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12478 10:13:40.373729 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12479 10:13:40.373882 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12480 10:13:40.374010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12481 10:13:40.374138 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12482 10:13:40.374261 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12483 10:13:40.374409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12484 10:13:40.374531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12485 10:13:40.374667 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12486 10:13:40.374806 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12487 10:13:40.374986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12488 10:13:40.375138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12489 10:13:40.375294 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12490 10:13:40.375439 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12491 10:13:40.375611 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12492 10:13:40.375752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12493 10:13:40.375892 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12494 10:13:40.376026 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12495 10:13:40.376202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12496 10:13:40.376348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12497 10:13:40.376486 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12498 10:13:40.376624 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12499 10:13:40.376755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12500 10:13:40.376867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12501 10:13:40.380706 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12502 10:13:40.381120 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12503 10:13:40.381293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12504 10:13:40.381431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12505 10:13:40.381589 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12506 10:13:40.381750 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12507 10:13:40.381898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12508 10:13:40.382071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12509 10:13:40.382225 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12510 10:13:40.382371 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12511 10:13:40.382520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12512 10:13:40.382702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12513 10:13:40.382847 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12514 10:13:40.382977 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12515 10:13:40.383116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12516 10:13:40.383297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12517 10:13:40.383455 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12518 10:13:40.383607 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12519 10:13:40.383757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12520 10:13:40.383938 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12521 10:13:40.384090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12522 10:13:40.384230 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12523 10:13:40.384364 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12524 10:13:40.384502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12525 10:13:40.384662 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12526 10:13:40.384778 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12527 10:13:40.384888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12528 10:13:40.384998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12529 10:13:40.388673 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12530 10:13:40.389026 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12531 10:13:40.389220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12532 10:13:40.389396 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12533 10:13:40.389566 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12534 10:13:40.389765 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12535 10:13:40.390019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12536 10:13:40.390213 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12537 10:13:40.390384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12538 10:13:40.390558 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12539 10:13:40.390750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12540 10:13:40.390938 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12541 10:13:40.391157 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12542 10:13:40.391335 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12543 10:13:40.391541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12544 10:13:40.391759 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12545 10:13:40.391929 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12546 10:13:40.392089 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12547 10:13:40.392266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12548 10:13:40.392436 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12549 10:13:40.392602 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12550 10:13:40.392739 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12551 10:13:40.392893 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12552 10:13:40.393021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12553 10:13:40.393143 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12554 10:13:40.393264 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12555 10:13:40.393387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12556 10:13:40.393493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12557 10:13:40.396693 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12558 10:13:40.397132 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12559 10:13:40.397324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12560 10:13:40.397459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12561 10:13:40.397605 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12562 10:13:40.397742 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12563 10:13:40.397862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12564 10:13:40.397983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12565 10:13:40.398097 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12566 10:13:40.398192 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12567 10:13:40.398287 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12568 10:13:40.398394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12569 10:13:40.398518 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12570 10:13:40.398634 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12571 10:13:40.398748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12572 10:13:40.398881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12573 10:13:40.399013 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12574 10:13:40.399143 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12575 10:13:40.399508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12576 10:13:40.399635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12577 10:13:40.399774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12578 10:13:40.399897 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12579 10:13:40.400037 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12580 10:13:40.400176 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12581 10:13:40.400313 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12582 10:13:40.400401 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12583 10:13:40.400483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12584 10:13:40.404717 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12585 10:13:40.405065 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12586 10:13:40.405261 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12587 10:13:40.405444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12588 10:13:40.405605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12589 10:13:40.405803 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12590 10:13:40.405973 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12591 10:13:40.406137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12592 10:13:40.406331 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12593 10:13:40.406455 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12594 10:13:40.406576 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12595 10:13:40.406698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12596 10:13:40.406840 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12597 10:13:40.406967 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12598 10:13:40.407090 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12599 10:13:40.407200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12600 10:13:40.407290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12601 10:13:40.407377 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12602 10:13:40.419421 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12603 10:13:40.419582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12604 10:13:40.419982 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12605 10:13:40.420165 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12606 10:13:40.420364 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12607 10:13:40.420533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12608 10:13:40.420738 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12609 10:13:40.420917 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12610 10:13:40.421086 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12611 10:13:40.421240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12612 10:13:40.421423 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12613 10:13:40.421580 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12614 10:13:40.421747 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12615 10:13:40.421899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12616 10:13:40.422050 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12617 10:13:40.422232 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12618 10:13:40.422386 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12619 10:13:40.422537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12620 10:13:40.422685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12621 10:13:40.422835 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12622 10:13:40.422984 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12623 10:13:40.423162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12624 10:13:40.423315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12625 10:13:40.423465 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12626 10:13:40.423615 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12627 10:13:40.423765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12628 10:13:40.423915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12629 10:13:40.424093 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12630 10:13:40.424247 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12631 10:13:40.424397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12632 10:13:40.424547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12633 10:13:40.424695 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12634 10:13:40.424843 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12635 10:13:40.424991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12636 10:13:40.425363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12637 10:13:40.425529 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12638 10:13:40.428616 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12639 10:13:40.428969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12640 10:13:40.429081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12641 10:13:40.429186 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12642 10:13:40.429268 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12643 10:13:40.429360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12644 10:13:40.429452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12645 10:13:40.429540 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12646 10:13:40.429631 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12647 10:13:40.429984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12648 10:13:40.430071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12649 10:13:40.430162 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12650 10:13:40.430245 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12651 10:13:40.430331 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12652 10:13:40.430636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12653 10:13:40.430719 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12654 10:13:40.430816 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12655 10:13:40.431113 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12656 10:13:40.431204 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12657 10:13:40.431453 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12658 10:13:40.431520 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12659 10:13:40.431776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12660 10:13:40.431871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12661 10:13:40.431979 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12662 10:13:40.432068 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12663 10:13:40.432158 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12664 10:13:40.432469 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12665 10:13:40.432664 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12666 10:13:40.436660 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12667 10:13:40.437035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12668 10:13:40.437131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12669 10:13:40.437211 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12670 10:13:40.437288 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12671 10:13:40.437375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12672 10:13:40.437651 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12673 10:13:40.437734 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12674 10:13:40.438018 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12675 10:13:40.438114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12676 10:13:40.438214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12677 10:13:40.438308 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12678 10:13:40.438617 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12679 10:13:40.438828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12680 10:13:40.439002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12681 10:13:40.439190 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12682 10:13:40.439332 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12683 10:13:40.439508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12684 10:13:40.439644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12685 10:13:40.440619 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12686 10:13:40.440769 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12687 10:13:40.440887 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12688 10:13:40.440998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12689 10:13:40.441110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12690 10:13:40.441221 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12691 10:13:40.441332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12692 10:13:40.444687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12693 10:13:40.444999 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12694 10:13:40.445094 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12695 10:13:40.445190 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12696 10:13:40.445484 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12697 10:13:40.445589 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12698 10:13:40.445859 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12699 10:13:40.445948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12700 10:13:40.446064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12701 10:13:40.446198 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12702 10:13:40.446508 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12703 10:13:40.446650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12704 10:13:40.446762 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12705 10:13:40.446846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12706 10:13:40.447110 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12707 10:13:40.447216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12708 10:13:40.447315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12709 10:13:40.447568 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12710 10:13:40.447821 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12711 10:13:40.447902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12712 10:13:40.447987 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12713 10:13:40.448268 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12714 10:13:40.448535 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12715 10:13:40.452711 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12716 10:13:40.452984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12717 10:13:40.453097 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12718 10:13:40.453188 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12719 10:13:40.453465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12720 10:13:40.453747 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12721 10:13:40.453841 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12722 10:13:40.453938 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12723 10:13:40.454053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12724 10:13:40.454181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12725 10:13:40.454500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12726 10:13:40.454595 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12727 10:13:40.455175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12728 10:13:40.455274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12729 10:13:40.455360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12730 10:13:40.455639 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12731 10:13:40.455719 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12732 10:13:40.455782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12733 10:13:40.456053 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12734 10:13:40.456144 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12735 10:13:40.456222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12736 10:13:40.476121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12737 10:13:40.476553 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12738 10:13:40.476719 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12739 10:13:40.476874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12740 10:13:40.477043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12741 10:13:40.477210 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12742 10:13:40.477347 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12743 10:13:40.477535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12744 10:13:40.477691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12745 10:13:40.477841 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12746 10:13:40.478024 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12747 10:13:40.478196 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12748 10:13:40.478357 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12749 10:13:40.478548 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12750 10:13:40.478706 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12751 10:13:40.478862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12752 10:13:40.479017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12753 10:13:40.479188 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12754 10:13:40.479340 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12755 10:13:40.479493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12756 10:13:40.479673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12757 10:13:40.479818 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12758 10:13:40.479948 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12759 10:13:40.480084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12760 10:13:40.480250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12761 10:13:40.480424 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12762 10:13:40.480583 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12763 10:13:40.480734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12764 10:13:40.480853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12765 10:13:40.484677 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12766 10:13:40.485071 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12767 10:13:40.485233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12768 10:13:40.485373 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12769 10:13:40.485524 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12770 10:13:40.485672 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12771 10:13:40.485813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12772 10:13:40.486007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12773 10:13:40.486161 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12774 10:13:40.486326 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12775 10:13:40.486522 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12776 10:13:40.486664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12777 10:13:40.486791 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12778 10:13:40.486927 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12779 10:13:40.487112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12780 10:13:40.487271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12781 10:13:40.487417 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12782 10:13:40.487575 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12783 10:13:40.487789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12784 10:13:40.487964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12785 10:13:40.488119 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12786 10:13:40.488262 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12787 10:13:40.488439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12788 10:13:40.488575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12789 10:13:40.488690 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12790 10:13:40.488804 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12791 10:13:40.488916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12792 10:13:40.492927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12793 10:13:40.493367 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12794 10:13:40.493471 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12795 10:13:40.493564 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12796 10:13:40.493670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12797 10:13:40.493757 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12798 10:13:40.493855 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12799 10:13:40.494144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12800 10:13:40.494386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12801 10:13:40.494542 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12802 10:13:40.494699 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12803 10:13:40.494828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12804 10:13:40.494968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12805 10:13:40.495195 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12806 10:13:40.495382 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12807 10:13:40.495536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12808 10:13:40.495722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12809 10:13:40.495885 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12810 10:13:40.496036 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12811 10:13:40.496195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12812 10:13:40.496393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12813 10:13:40.496551 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12814 10:13:40.496673 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12815 10:13:40.496784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12816 10:13:40.496896 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12817 10:13:40.500659 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12818 10:13:40.501060 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12819 10:13:40.501167 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12820 10:13:40.501253 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12821 10:13:40.501352 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12822 10:13:40.501437 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12823 10:13:40.501692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12824 10:13:40.501809 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12825 10:13:40.502101 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12826 10:13:40.502190 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12827 10:13:40.502286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12828 10:13:40.502385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12829 10:13:40.502678 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12830 10:13:40.502765 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12831 10:13:40.502878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12832 10:13:40.503159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12833 10:13:40.503258 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12834 10:13:40.503356 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12835 10:13:40.503637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12836 10:13:40.503738 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12837 10:13:40.504026 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12838 10:13:40.504113 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12839 10:13:40.504209 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12840 10:13:40.504491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12841 10:13:40.508630 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12842 10:13:40.508916 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12843 10:13:40.509006 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12844 10:13:40.509105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12845 10:13:40.509239 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12846 10:13:40.509542 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12847 10:13:40.509638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12848 10:13:40.509744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12849 10:13:40.510029 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12850 10:13:40.510122 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12851 10:13:40.510221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12852 10:13:40.510565 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12853 10:13:40.510760 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12854 10:13:40.510954 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12855 10:13:40.511092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12856 10:13:40.511243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12857 10:13:40.511391 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12858 10:13:40.511509 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12859 10:13:40.511653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12860 10:13:40.511841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12861 10:13:40.512005 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12862 10:13:40.512168 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12863 10:13:40.512304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12864 10:13:40.512459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12865 10:13:40.512592 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12866 10:13:40.512704 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12867 10:13:40.512813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12868 10:13:40.516650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12869 10:13:40.516947 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12870 10:13:40.529179 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12871 10:13:40.529513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12872 10:13:40.529615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12873 10:13:40.529708 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12874 10:13:40.529826 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12875 10:13:40.529941 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12876 10:13:40.530301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12877 10:13:40.530505 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12878 10:13:40.530659 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12879 10:13:40.530857 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12880 10:13:40.531031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12881 10:13:40.531259 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12882 10:13:40.531429 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12883 10:13:40.531606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12884 10:13:40.531796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12885 10:13:40.531969 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12886 10:13:40.532166 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12887 10:13:40.532342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12888 10:13:40.532566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12889 10:13:40.532741 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12890 10:13:40.532873 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12891 10:13:40.532985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12892 10:13:40.533096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12893 10:13:40.536665 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12894 10:13:40.536951 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12895 10:13:40.537055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12896 10:13:40.537166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12897 10:13:40.537269 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12898 10:13:40.537374 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12899 10:13:40.537466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12900 10:13:40.537789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12901 10:13:40.537899 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12902 10:13:40.538002 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12903 10:13:40.538323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12904 10:13:40.538413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12905 10:13:40.538527 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12906 10:13:40.538636 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12907 10:13:40.538919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12908 10:13:40.539008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12909 10:13:40.539124 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12910 10:13:40.539234 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12911 10:13:40.539342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12912 10:13:40.539639 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12913 10:13:40.539724 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12914 10:13:40.539844 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12915 10:13:40.539964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12916 10:13:40.540078 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12917 10:13:40.540373 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12918 10:13:40.540465 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12919 10:13:40.540571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12920 10:13:40.544888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12921 10:13:40.545080 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12922 10:13:40.545257 arm64_sve-ptrace pass
12923 10:13:40.545413 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12924 10:13:40.545572 arm64_sve-probe-vls_All_vector_lengths_valid pass
12925 10:13:40.545739 arm64_sve-probe-vls pass
12926 10:13:40.545920 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12927 10:13:40.546101 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
12928 10:13:40.546299 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
12929 10:13:40.546474 arm64_vec-syscfg_SVE_current_VL_is_64 pass
12930 10:13:40.546635 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
12931 10:13:40.546783 arm64_vec-syscfg_SVE_prctl_set_min_max pass
12932 10:13:40.546944 arm64_vec-syscfg_SVE_vector_length_used_default pass
12933 10:13:40.547082 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
12934 10:13:40.547215 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
12935 10:13:40.547350 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
12936 10:13:40.547493 arm64_vec-syscfg_SME_default_vector_length_32 pass
12937 10:13:40.547623 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
12938 10:13:40.547773 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
12939 10:13:40.547958 arm64_vec-syscfg_SME_current_VL_is_32 pass
12940 10:13:40.548124 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
12941 10:13:40.548319 arm64_vec-syscfg_SME_prctl_set_min_max pass
12942 10:13:40.548475 arm64_vec-syscfg_SME_vector_length_used_default pass
12943 10:13:40.548591 arm64_vec-syscfg_SME_vector_length_was_inherited pass
12944 10:13:40.548704 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
12945 10:13:40.548814 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
12946 10:13:40.548922 arm64_vec-syscfg pass
12947 10:13:40.549030 arm64_za-fork_fork_test pass
12948 10:13:40.549138 arm64_za-fork pass
12949 10:13:40.549247 arm64_za-ptrace_Set_VL_16 pass
12950 10:13:40.549356 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
12951 10:13:40.549465 arm64_za-ptrace_Data_match_for_VL_16 pass
12952 10:13:40.549573 arm64_za-ptrace_Set_VL_32 pass
12953 10:13:40.549741 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
12954 10:13:40.549938 arm64_za-ptrace_Data_match_for_VL_32 pass
12955 10:13:40.550118 arm64_za-ptrace_Set_VL_48 pass
12956 10:13:40.550328 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
12957 10:13:40.550511 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
12958 10:13:40.552884 arm64_za-ptrace_Set_VL_64 pass
12959 10:13:40.553045 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
12960 10:13:40.553215 arm64_za-ptrace_Data_match_for_VL_64 pass
12961 10:13:40.553403 arm64_za-ptrace_Set_VL_80 pass
12962 10:13:40.553541 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
12963 10:13:40.553671 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
12964 10:13:40.553798 arm64_za-ptrace_Set_VL_96 pass
12965 10:13:40.553953 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
12966 10:13:40.554110 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
12967 10:13:40.554232 arm64_za-ptrace_Set_VL_112 pass
12968 10:13:40.554419 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
12969 10:13:40.554591 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
12970 10:13:40.554756 arm64_za-ptrace_Set_VL_128 pass
12971 10:13:40.554935 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
12972 10:13:40.555095 arm64_za-ptrace_Data_match_for_VL_128 pass
12973 10:13:40.555246 arm64_za-ptrace_Set_VL_144 pass
12974 10:13:40.555438 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
12975 10:13:40.555592 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
12976 10:13:40.555753 arm64_za-ptrace_Set_VL_160 pass
12977 10:13:40.555901 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
12978 10:13:40.556019 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
12979 10:13:40.556169 arm64_za-ptrace_Set_VL_176 pass
12980 10:13:40.556298 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
12981 10:13:40.556438 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
12982 10:13:40.556562 arm64_za-ptrace_Set_VL_192 pass
12983 10:13:40.556677 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
12984 10:13:40.556787 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
12985 10:13:40.556898 arm64_za-ptrace_Set_VL_208 pass
12986 10:13:40.557007 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
12987 10:13:40.557145 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
12988 10:13:40.557262 arm64_za-ptrace_Set_VL_224 pass
12989 10:13:40.557374 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
12990 10:13:40.557485 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
12991 10:13:40.557598 arm64_za-ptrace_Set_VL_240 pass
12992 10:13:40.557727 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
12993 10:13:40.557839 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
12994 10:13:40.557949 arm64_za-ptrace_Set_VL_256 pass
12995 10:13:40.558060 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
12996 10:13:40.558170 arm64_za-ptrace_Data_match_for_VL_256 pass
12997 10:13:40.558280 arm64_za-ptrace_Set_VL_272 pass
12998 10:13:40.560703 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
12999 10:13:40.560875 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
13000 10:13:40.561267 arm64_za-ptrace_Set_VL_288 pass
13001 10:13:40.561465 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
13002 10:13:40.561670 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
13003 10:13:40.561872 arm64_za-ptrace_Set_VL_304 pass
13004 10:13:40.562067 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
13005 10:13:40.562312 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
13006 10:13:40.562512 arm64_za-ptrace_Set_VL_320 pass
13007 10:13:40.562694 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
13008 10:13:40.562855 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
13009 10:13:40.563008 arm64_za-ptrace_Set_VL_336 pass
13010 10:13:40.563165 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
13011 10:13:40.563352 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
13012 10:13:40.563510 arm64_za-ptrace_Set_VL_352 pass
13013 10:13:40.563640 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
13014 10:13:40.563826 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
13015 10:13:40.563990 arm64_za-ptrace_Set_VL_368 pass
13016 10:13:40.564198 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
13017 10:13:40.564377 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
13018 10:13:40.564592 arm64_za-ptrace_Set_VL_384 pass
13019 10:13:40.564762 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
13020 10:13:40.564902 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
13021 10:13:40.565040 arm64_za-ptrace_Set_VL_400 pass
13022 10:13:40.565176 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
13023 10:13:40.565313 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
13024 10:13:40.565449 arm64_za-ptrace_Set_VL_416 pass
13025 10:13:40.565586 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
13026 10:13:40.565765 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
13027 10:13:40.565931 arm64_za-ptrace_Set_VL_432 pass
13028 10:13:40.566070 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
13029 10:13:40.566208 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
13030 10:13:40.566344 arm64_za-ptrace_Set_VL_448 pass
13031 10:13:40.566481 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
13032 10:13:40.566618 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
13033 10:13:40.566758 arm64_za-ptrace_Set_VL_464 pass
13034 10:13:40.566929 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
13035 10:13:40.567063 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
13036 10:13:40.567201 arm64_za-ptrace_Set_VL_480 pass
13037 10:13:40.568672 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
13038 10:13:40.569090 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
13039 10:13:40.569251 arm64_za-ptrace_Set_VL_496 pass
13040 10:13:40.569371 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
13041 10:13:40.581982 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
13042 10:13:40.582281 arm64_za-ptrace_Set_VL_512 pass
13043 10:13:40.582378 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
13044 10:13:40.582472 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
13045 10:13:40.582560 arm64_za-ptrace_Set_VL_528 pass
13046 10:13:40.582653 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
13047 10:13:40.582724 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
13048 10:13:40.582799 arm64_za-ptrace_Set_VL_544 pass
13049 10:13:40.582875 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
13050 10:13:40.582940 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
13051 10:13:40.583018 arm64_za-ptrace_Set_VL_560 pass
13052 10:13:40.583099 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
13053 10:13:40.583164 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
13054 10:13:40.583239 arm64_za-ptrace_Set_VL_576 pass
13055 10:13:40.583507 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
13056 10:13:40.583596 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
13057 10:13:40.583685 arm64_za-ptrace_Set_VL_592 pass
13058 10:13:40.583776 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
13059 10:13:40.583847 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
13060 10:13:40.583936 arm64_za-ptrace_Set_VL_608 pass
13061 10:13:40.584023 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
13062 10:13:40.584136 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
13063 10:13:40.584226 arm64_za-ptrace_Set_VL_624 pass
13064 10:13:40.584333 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
13065 10:13:40.584415 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
13066 10:13:40.584493 arm64_za-ptrace_Set_VL_640 pass
13067 10:13:40.584574 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
13068 10:13:40.584649 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
13069 10:13:40.584722 arm64_za-ptrace_Set_VL_656 pass
13070 10:13:40.584789 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
13071 10:13:40.584859 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
13072 10:13:40.584932 arm64_za-ptrace_Set_VL_672 pass
13073 10:13:40.585015 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
13074 10:13:40.585087 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
13075 10:13:40.585338 arm64_za-ptrace_Set_VL_688 pass
13076 10:13:40.585430 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
13077 10:13:40.585549 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
13078 10:13:40.585627 arm64_za-ptrace_Set_VL_704 pass
13079 10:13:40.585716 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
13080 10:13:40.585806 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
13081 10:13:40.585899 arm64_za-ptrace_Set_VL_720 pass
13082 10:13:40.586011 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
13083 10:13:40.586115 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
13084 10:13:40.586204 arm64_za-ptrace_Set_VL_736 pass
13085 10:13:40.586296 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
13086 10:13:40.586459 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
13087 10:13:40.586583 arm64_za-ptrace_Set_VL_752 pass
13088 10:13:40.586673 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
13089 10:13:40.586761 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
13090 10:13:40.587044 arm64_za-ptrace_Set_VL_768 pass
13091 10:13:40.587126 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
13092 10:13:40.587197 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
13093 10:13:40.587263 arm64_za-ptrace_Set_VL_784 pass
13094 10:13:40.587361 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
13095 10:13:40.587462 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
13096 10:13:40.587549 arm64_za-ptrace_Set_VL_800 pass
13097 10:13:40.587642 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
13098 10:13:40.587714 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
13099 10:13:40.587792 arm64_za-ptrace_Set_VL_816 pass
13100 10:13:40.587888 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
13101 10:13:40.587972 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
13102 10:13:40.588044 arm64_za-ptrace_Set_VL_832 pass
13103 10:13:40.588116 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
13104 10:13:40.588182 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
13105 10:13:40.588254 arm64_za-ptrace_Set_VL_848 pass
13106 10:13:40.588316 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
13107 10:13:40.588394 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
13108 10:13:40.588477 arm64_za-ptrace_Set_VL_864 pass
13109 10:13:40.592630 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
13110 10:13:40.592921 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
13111 10:13:40.593014 arm64_za-ptrace_Set_VL_880 pass
13112 10:13:40.593114 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
13113 10:13:40.593198 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
13114 10:13:40.593280 arm64_za-ptrace_Set_VL_896 pass
13115 10:13:40.593375 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
13116 10:13:40.593473 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
13117 10:13:40.593569 arm64_za-ptrace_Set_VL_912 pass
13118 10:13:40.593681 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
13119 10:13:40.593972 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
13120 10:13:40.594066 arm64_za-ptrace_Set_VL_928 pass
13121 10:13:40.594168 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
13122 10:13:40.594252 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
13123 10:13:40.594354 arm64_za-ptrace_Set_VL_944 pass
13124 10:13:40.594439 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
13125 10:13:40.594537 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
13126 10:13:40.594637 arm64_za-ptrace_Set_VL_960 pass
13127 10:13:40.594735 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
13128 10:13:40.594843 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
13129 10:13:40.594943 arm64_za-ptrace_Set_VL_976 pass
13130 10:13:40.595238 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
13131 10:13:40.595339 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
13132 10:13:40.595442 arm64_za-ptrace_Set_VL_992 pass
13133 10:13:40.595530 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
13134 10:13:40.595628 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
13135 10:13:40.595728 arm64_za-ptrace_Set_VL_1008 pass
13136 10:13:40.596017 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
13137 10:13:40.596107 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
13138 10:13:40.596207 arm64_za-ptrace_Set_VL_1024 pass
13139 10:13:40.596293 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
13140 10:13:40.596393 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
13141 10:13:40.596492 arm64_za-ptrace_Set_VL_1040 pass
13142 10:13:40.604631 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
13143 10:13:40.605058 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
13144 10:13:40.605236 arm64_za-ptrace_Set_VL_1056 pass
13145 10:13:40.605400 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
13146 10:13:40.605558 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
13147 10:13:40.605762 arm64_za-ptrace_Set_VL_1072 pass
13148 10:13:40.605924 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
13149 10:13:40.606076 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
13150 10:13:40.606236 arm64_za-ptrace_Set_VL_1088 pass
13151 10:13:40.606394 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
13152 10:13:40.606553 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
13153 10:13:40.606710 arm64_za-ptrace_Set_VL_1104 pass
13154 10:13:40.606870 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
13155 10:13:40.607064 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
13156 10:13:40.607211 arm64_za-ptrace_Set_VL_1120 pass
13157 10:13:40.607362 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
13158 10:13:40.607518 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
13159 10:13:40.607677 arm64_za-ptrace_Set_VL_1136 pass
13160 10:13:40.607826 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
13161 10:13:40.607977 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
13162 10:13:40.608120 arm64_za-ptrace_Set_VL_1152 pass
13163 10:13:40.608261 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
13164 10:13:40.608424 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
13165 10:13:40.608603 arm64_za-ptrace_Set_VL_1168 pass
13166 10:13:40.608743 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
13167 10:13:40.608895 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
13168 10:13:40.609016 arm64_za-ptrace_Set_VL_1184 pass
13169 10:13:40.609130 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
13170 10:13:40.609243 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
13171 10:13:40.609354 arm64_za-ptrace_Set_VL_1200 pass
13172 10:13:40.609467 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13173 10:13:40.609578 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13174 10:13:40.609765 arm64_za-ptrace_Set_VL_1216 pass
13175 10:13:40.609964 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13176 10:13:40.610145 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13177 10:13:40.610326 arm64_za-ptrace_Set_VL_1232 pass
13178 10:13:40.610504 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13179 10:13:40.610680 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13180 10:13:40.610821 arm64_za-ptrace_Set_VL_1248 pass
13181 10:13:40.610957 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13182 10:13:40.612716 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13183 10:13:40.612918 arm64_za-ptrace_Set_VL_1264 pass
13184 10:13:40.613345 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13185 10:13:40.613543 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13186 10:13:40.613731 arm64_za-ptrace_Set_VL_1280 pass
13187 10:13:40.613899 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13188 10:13:40.614062 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13189 10:13:40.614228 arm64_za-ptrace_Set_VL_1296 pass
13190 10:13:40.614438 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13191 10:13:40.614648 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13192 10:13:40.614820 arm64_za-ptrace_Set_VL_1312 pass
13193 10:13:40.615000 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13194 10:13:40.615145 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13195 10:13:40.615284 arm64_za-ptrace_Set_VL_1328 pass
13196 10:13:40.615462 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13197 10:13:40.615612 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13198 10:13:40.615761 arm64_za-ptrace_Set_VL_1344 pass
13199 10:13:40.615909 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13200 10:13:40.616062 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13201 10:13:40.616210 arm64_za-ptrace_Set_VL_1360 pass
13202 10:13:40.616402 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13203 10:13:40.616608 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13204 10:13:40.616736 arm64_za-ptrace_Set_VL_1376 pass
13205 10:13:40.616849 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13206 10:13:40.616960 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13207 10:13:40.617069 arm64_za-ptrace_Set_VL_1392 pass
13208 10:13:40.617178 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13209 10:13:40.617287 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13210 10:13:40.617396 arm64_za-ptrace_Set_VL_1408 pass
13211 10:13:40.617505 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13212 10:13:40.617614 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13213 10:13:40.617831 arm64_za-ptrace_Set_VL_1424 pass
13214 10:13:40.618019 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13215 10:13:40.618197 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13216 10:13:40.618356 arm64_za-ptrace_Set_VL_1440 pass
13217 10:13:40.618496 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13218 10:13:40.618633 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13219 10:13:40.618772 arm64_za-ptrace_Set_VL_1456 pass
13220 10:13:40.618947 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13221 10:13:40.619082 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13222 10:13:40.619221 arm64_za-ptrace_Set_VL_1472 pass
13223 10:13:40.619359 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13224 10:13:40.620680 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13225 10:13:40.621101 arm64_za-ptrace_Set_VL_1488 pass
13226 10:13:40.621272 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13227 10:13:40.621455 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13228 10:13:40.621603 arm64_za-ptrace_Set_VL_1504 pass
13229 10:13:40.621755 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13230 10:13:40.621890 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13231 10:13:40.622005 arm64_za-ptrace_Set_VL_1520 pass
13232 10:13:40.622113 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13233 10:13:40.622217 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13234 10:13:40.622321 arm64_za-ptrace_Set_VL_1536 pass
13235 10:13:40.622424 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13236 10:13:40.634237 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13237 10:13:40.634592 arm64_za-ptrace_Set_VL_1552 pass
13238 10:13:40.634789 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13239 10:13:40.634964 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13240 10:13:40.635171 arm64_za-ptrace_Set_VL_1568 pass
13241 10:13:40.635405 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13242 10:13:40.635591 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13243 10:13:40.635759 arm64_za-ptrace_Set_VL_1584 pass
13244 10:13:40.635919 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13245 10:13:40.636078 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13246 10:13:40.636206 arm64_za-ptrace_Set_VL_1600 pass
13247 10:13:40.636351 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13248 10:13:40.636547 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13249 10:13:40.636682 arm64_za-ptrace_Set_VL_1616 pass
13250 10:13:40.636834 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13251 10:13:40.636984 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13252 10:13:40.637133 arm64_za-ptrace_Set_VL_1632 pass
13253 10:13:40.637285 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13254 10:13:40.637439 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13255 10:13:40.637597 arm64_za-ptrace_Set_VL_1648 pass
13256 10:13:40.638211 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13257 10:13:40.638441 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13258 10:13:40.638613 arm64_za-ptrace_Set_VL_1664 pass
13259 10:13:40.638774 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13260 10:13:40.638920 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13261 10:13:40.639074 arm64_za-ptrace_Set_VL_1680 pass
13262 10:13:40.639228 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13263 10:13:40.639378 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13264 10:13:40.639533 arm64_za-ptrace_Set_VL_1696 pass
13265 10:13:40.639688 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13266 10:13:40.639848 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13267 10:13:40.639993 arm64_za-ptrace_Set_VL_1712 pass
13268 10:13:40.640147 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13269 10:13:40.640306 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13270 10:13:40.640461 arm64_za-ptrace_Set_VL_1728 pass
13271 10:13:40.640580 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13272 10:13:40.640693 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13273 10:13:40.640801 arm64_za-ptrace_Set_VL_1744 pass
13274 10:13:40.640907 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13275 10:13:40.641014 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13276 10:13:40.641120 arm64_za-ptrace_Set_VL_1760 pass
13277 10:13:40.641227 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13278 10:13:40.641334 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13279 10:13:40.641440 arm64_za-ptrace_Set_VL_1776 pass
13280 10:13:40.641571 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13281 10:13:40.641752 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13282 10:13:40.642192 arm64_za-ptrace_Set_VL_1792 pass
13283 10:13:40.642384 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13284 10:13:40.642530 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13285 10:13:40.642669 arm64_za-ptrace_Set_VL_1808 pass
13286 10:13:40.642807 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13287 10:13:40.642943 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13288 10:13:40.643079 arm64_za-ptrace_Set_VL_1824 pass
13289 10:13:40.643215 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13290 10:13:40.643351 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13291 10:13:40.643487 arm64_za-ptrace_Set_VL_1840 pass
13292 10:13:40.643623 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13293 10:13:40.643760 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13294 10:13:40.643896 arm64_za-ptrace_Set_VL_1856 pass
13295 10:13:40.644033 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13296 10:13:40.644705 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13297 10:13:40.645138 arm64_za-ptrace_Set_VL_1872 pass
13298 10:13:40.645327 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13299 10:13:40.645474 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13300 10:13:40.645632 arm64_za-ptrace_Set_VL_1888 pass
13301 10:13:40.645832 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13302 10:13:40.645996 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13303 10:13:40.646158 arm64_za-ptrace_Set_VL_1904 pass
13304 10:13:40.646317 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13305 10:13:40.646477 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13306 10:13:40.646627 arm64_za-ptrace_Set_VL_1920 pass
13307 10:13:40.646787 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13308 10:13:40.646941 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13309 10:13:40.647145 arm64_za-ptrace_Set_VL_1936 pass
13310 10:13:40.647300 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13311 10:13:40.647466 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13312 10:13:40.647633 arm64_za-ptrace_Set_VL_1952 pass
13313 10:13:40.647799 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13314 10:13:40.647971 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13315 10:13:40.648169 arm64_za-ptrace_Set_VL_1968 pass
13316 10:13:40.648359 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13317 10:13:40.648530 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13318 10:13:40.648654 arm64_za-ptrace_Set_VL_1984 pass
13319 10:13:40.648766 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13320 10:13:40.648878 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13321 10:13:40.649018 arm64_za-ptrace_Set_VL_2000 pass
13322 10:13:40.649134 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13323 10:13:40.649244 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13324 10:13:40.649352 arm64_za-ptrace_Set_VL_2016 pass
13325 10:13:40.649461 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13326 10:13:40.649569 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13327 10:13:40.649758 arm64_za-ptrace_Set_VL_2032 pass
13328 10:13:40.649963 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13329 10:13:40.650145 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13330 10:13:40.650325 arm64_za-ptrace_Set_VL_2048 pass
13331 10:13:40.650503 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13332 10:13:40.650681 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13333 10:13:40.652891 arm64_za-ptrace_Set_VL_2064 pass
13334 10:13:40.653082 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13335 10:13:40.653290 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13336 10:13:40.653515 arm64_za-ptrace_Set_VL_2080 pass
13337 10:13:40.653705 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13338 10:13:40.653896 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13339 10:13:40.654117 arm64_za-ptrace_Set_VL_2096 pass
13340 10:13:40.654285 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13341 10:13:40.654435 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13342 10:13:40.654579 arm64_za-ptrace_Set_VL_2112 pass
13343 10:13:40.654730 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13344 10:13:40.654879 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13345 10:13:40.655027 arm64_za-ptrace_Set_VL_2128 pass
13346 10:13:40.655183 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13347 10:13:40.655371 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13348 10:13:40.655537 arm64_za-ptrace_Set_VL_2144 pass
13349 10:13:40.655700 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13350 10:13:40.655857 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13351 10:13:40.656010 arm64_za-ptrace_Set_VL_2160 pass
13352 10:13:40.656163 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13353 10:13:40.656327 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13354 10:13:40.656469 arm64_za-ptrace_Set_VL_2176 pass
13355 10:13:40.656586 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13356 10:13:40.656698 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13357 10:13:40.656808 arm64_za-ptrace_Set_VL_2192 pass
13358 10:13:40.656922 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13359 10:13:40.657061 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13360 10:13:40.657178 arm64_za-ptrace_Set_VL_2208 pass
13361 10:13:40.657290 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13362 10:13:40.657401 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13363 10:13:40.657511 arm64_za-ptrace_Set_VL_2224 pass
13364 10:13:40.657621 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13365 10:13:40.657833 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13366 10:13:40.657976 arm64_za-ptrace_Set_VL_2240 pass
13367 10:13:40.658110 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13368 10:13:40.658244 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13369 10:13:40.658379 arm64_za-ptrace_Set_VL_2256 pass
13370 10:13:40.660833 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13371 10:13:40.660939 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13372 10:13:40.661038 arm64_za-ptrace_Set_VL_2272 pass
13373 10:13:40.661110 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13374 10:13:40.661222 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13375 10:13:40.661329 arm64_za-ptrace_Set_VL_2288 pass
13376 10:13:40.661424 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13377 10:13:40.661496 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13378 10:13:40.661599 arm64_za-ptrace_Set_VL_2304 pass
13379 10:13:40.661685 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13380 10:13:40.661775 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13381 10:13:40.661877 arm64_za-ptrace_Set_VL_2320 pass
13382 10:13:40.661982 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13383 10:13:40.662270 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13384 10:13:40.662351 arm64_za-ptrace_Set_VL_2336 pass
13385 10:13:40.662412 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13386 10:13:40.662484 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13387 10:13:40.662573 arm64_za-ptrace_Set_VL_2352 pass
13388 10:13:40.662659 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13389 10:13:40.662743 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13390 10:13:40.662822 arm64_za-ptrace_Set_VL_2368 pass
13391 10:13:40.662909 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13392 10:13:40.662998 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13393 10:13:40.663087 arm64_za-ptrace_Set_VL_2384 pass
13394 10:13:40.663177 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13395 10:13:40.663547 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13396 10:13:40.663647 arm64_za-ptrace_Set_VL_2400 pass
13397 10:13:40.663730 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13398 10:13:40.663806 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13399 10:13:40.664067 arm64_za-ptrace_Set_VL_2416 pass
13400 10:13:40.664153 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13401 10:13:40.664241 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13402 10:13:40.664324 arm64_za-ptrace_Set_VL_2432 pass
13403 10:13:40.664445 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13404 10:13:40.664535 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13405 10:13:40.664622 arm64_za-ptrace_Set_VL_2448 pass
13406 10:13:40.664695 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13407 10:13:40.668660 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13408 10:13:40.668996 arm64_za-ptrace_Set_VL_2464 pass
13409 10:13:40.669097 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13410 10:13:40.669184 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13411 10:13:40.669282 arm64_za-ptrace_Set_VL_2480 pass
13412 10:13:40.669369 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13413 10:13:40.669469 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13414 10:13:40.669556 arm64_za-ptrace_Set_VL_2496 pass
13415 10:13:40.669663 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13416 10:13:40.669767 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13417 10:13:40.669870 arm64_za-ptrace_Set_VL_2512 pass
13418 10:13:40.669970 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13419 10:13:40.670259 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13420 10:13:40.670356 arm64_za-ptrace_Set_VL_2528 pass
13421 10:13:40.670450 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13422 10:13:40.670531 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13423 10:13:40.670615 arm64_za-ptrace_Set_VL_2544 pass
13424 10:13:40.670691 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13425 10:13:40.670949 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13426 10:13:40.671040 arm64_za-ptrace_Set_VL_2560 pass
13427 10:13:40.671128 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13428 10:13:40.671436 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13429 10:13:40.687623 arm64_za-ptrace_Set_VL_2576 pass
13430 10:13:40.687818 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13431 10:13:40.688015 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13432 10:13:40.688180 arm64_za-ptrace_Set_VL_2592 pass
13433 10:13:40.688331 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13434 10:13:40.688485 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13435 10:13:40.688626 arm64_za-ptrace_Set_VL_2608 pass
13436 10:13:40.688820 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13437 10:13:40.688990 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13438 10:13:40.689152 arm64_za-ptrace_Set_VL_2624 pass
13439 10:13:40.689317 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13440 10:13:40.689484 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13441 10:13:40.689671 arm64_za-ptrace_Set_VL_2640 pass
13442 10:13:40.689864 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13443 10:13:40.690090 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13444 10:13:40.690281 arm64_za-ptrace_Set_VL_2656 pass
13445 10:13:40.690432 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13446 10:13:40.690583 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13447 10:13:40.690739 arm64_za-ptrace_Set_VL_2672 pass
13448 10:13:40.690943 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13449 10:13:40.691117 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13450 10:13:40.691261 arm64_za-ptrace_Set_VL_2688 pass
13451 10:13:40.691405 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13452 10:13:40.691564 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13453 10:13:40.691716 arm64_za-ptrace_Set_VL_2704 pass
13454 10:13:40.691862 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13455 10:13:40.692057 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13456 10:13:40.692214 arm64_za-ptrace_Set_VL_2720 pass
13457 10:13:40.692361 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13458 10:13:40.692496 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13459 10:13:40.692611 arm64_za-ptrace_Set_VL_2736 pass
13460 10:13:40.692725 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13461 10:13:40.692839 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13462 10:13:40.692951 arm64_za-ptrace_Set_VL_2752 pass
13463 10:13:40.693061 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13464 10:13:40.693171 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13465 10:13:40.693281 arm64_za-ptrace_Set_VL_2768 pass
13466 10:13:40.693391 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13467 10:13:40.693501 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13468 10:13:40.693611 arm64_za-ptrace_Set_VL_2784 pass
13469 10:13:40.693824 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13470 10:13:40.694012 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13471 10:13:40.694200 arm64_za-ptrace_Set_VL_2800 pass
13472 10:13:40.694376 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13473 10:13:40.694554 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13474 10:13:40.694959 arm64_za-ptrace_Set_VL_2816 pass
13475 10:13:40.695101 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13476 10:13:40.695244 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13477 10:13:40.695385 arm64_za-ptrace_Set_VL_2832 pass
13478 10:13:40.696655 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13479 10:13:40.697037 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13480 10:13:40.697131 arm64_za-ptrace_Set_VL_2848 pass
13481 10:13:40.697229 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13482 10:13:40.697314 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13483 10:13:40.697415 arm64_za-ptrace_Set_VL_2864 pass
13484 10:13:40.697503 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13485 10:13:40.697585 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13486 10:13:40.697693 arm64_za-ptrace_Set_VL_2880 pass
13487 10:13:40.697792 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13488 10:13:40.697873 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13489 10:13:40.697986 arm64_za-ptrace_Set_VL_2896 pass
13490 10:13:40.698077 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13491 10:13:40.698183 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13492 10:13:40.698275 arm64_za-ptrace_Set_VL_2912 pass
13493 10:13:40.698400 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13494 10:13:40.698523 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13495 10:13:40.698638 arm64_za-ptrace_Set_VL_2928 pass
13496 10:13:40.698744 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13497 10:13:40.699022 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13498 10:13:40.699123 arm64_za-ptrace_Set_VL_2944 pass
13499 10:13:40.699216 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13500 10:13:40.699287 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13501 10:13:40.699376 arm64_za-ptrace_Set_VL_2960 pass
13502 10:13:40.699451 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13503 10:13:40.699541 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13504 10:13:40.699625 arm64_za-ptrace_Set_VL_2976 pass
13505 10:13:40.699706 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13506 10:13:40.699791 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13507 10:13:40.699867 arm64_za-ptrace_Set_VL_2992 pass
13508 10:13:40.699959 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13509 10:13:40.700244 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13510 10:13:40.700336 arm64_za-ptrace_Set_VL_3008 pass
13511 10:13:40.700430 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13512 10:13:40.700514 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13513 10:13:40.704630 arm64_za-ptrace_Set_VL_3024 pass
13514 10:13:40.704943 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13515 10:13:40.705037 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13516 10:13:40.705115 arm64_za-ptrace_Set_VL_3040 pass
13517 10:13:40.705211 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13518 10:13:40.705283 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13519 10:13:40.705355 arm64_za-ptrace_Set_VL_3056 pass
13520 10:13:40.705441 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13521 10:13:40.705528 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13522 10:13:40.705634 arm64_za-ptrace_Set_VL_3072 pass
13523 10:13:40.705728 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13524 10:13:40.705820 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13525 10:13:40.705933 arm64_za-ptrace_Set_VL_3088 pass
13526 10:13:40.706018 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13527 10:13:40.706101 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13528 10:13:40.706196 arm64_za-ptrace_Set_VL_3104 pass
13529 10:13:40.706300 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13530 10:13:40.706394 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13531 10:13:40.706492 arm64_za-ptrace_Set_VL_3120 pass
13532 10:13:40.706772 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13533 10:13:40.706869 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13534 10:13:40.706978 arm64_za-ptrace_Set_VL_3136 pass
13535 10:13:40.707087 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13536 10:13:40.707190 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13537 10:13:40.707270 arm64_za-ptrace_Set_VL_3152 pass
13538 10:13:40.707360 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13539 10:13:40.707452 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13540 10:13:40.707577 arm64_za-ptrace_Set_VL_3168 pass
13541 10:13:40.707679 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13542 10:13:40.707794 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13543 10:13:40.707887 arm64_za-ptrace_Set_VL_3184 pass
13544 10:13:40.707984 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13545 10:13:40.708077 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13546 10:13:40.708158 arm64_za-ptrace_Set_VL_3200 pass
13547 10:13:40.708246 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13548 10:13:40.708338 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13549 10:13:40.708443 arm64_za-ptrace_Set_VL_3216 pass
13550 10:13:40.708557 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13551 10:13:40.712741 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13552 10:13:40.713180 arm64_za-ptrace_Set_VL_3232 pass
13553 10:13:40.713378 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13554 10:13:40.713584 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13555 10:13:40.713785 arm64_za-ptrace_Set_VL_3248 pass
13556 10:13:40.713993 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13557 10:13:40.714191 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13558 10:13:40.714375 arm64_za-ptrace_Set_VL_3264 pass
13559 10:13:40.714538 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13560 10:13:40.714696 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13561 10:13:40.714822 arm64_za-ptrace_Set_VL_3280 pass
13562 10:13:40.714937 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13563 10:13:40.715085 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13564 10:13:40.715251 arm64_za-ptrace_Set_VL_3296 pass
13565 10:13:40.715410 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13566 10:13:40.715564 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13567 10:13:40.715706 arm64_za-ptrace_Set_VL_3312 pass
13568 10:13:40.715855 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13569 10:13:40.716007 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13570 10:13:40.716161 arm64_za-ptrace_Set_VL_3328 pass
13571 10:13:40.716320 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13572 10:13:40.716472 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13573 10:13:40.716591 arm64_za-ptrace_Set_VL_3344 pass
13574 10:13:40.716704 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13575 10:13:40.716816 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13576 10:13:40.716956 arm64_za-ptrace_Set_VL_3360 pass
13577 10:13:40.717070 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13578 10:13:40.717180 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13579 10:13:40.717289 arm64_za-ptrace_Set_VL_3376 pass
13580 10:13:40.717398 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13581 10:13:40.717508 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13582 10:13:40.717618 arm64_za-ptrace_Set_VL_3392 pass
13583 10:13:40.717741 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13584 10:13:40.717850 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13585 10:13:40.717963 arm64_za-ptrace_Set_VL_3408 pass
13586 10:13:40.718071 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13587 10:13:40.718181 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13588 10:13:40.718290 arm64_za-ptrace_Set_VL_3424 pass
13589 10:13:40.720724 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13590 10:13:40.721133 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13591 10:13:40.721274 arm64_za-ptrace_Set_VL_3440 pass
13592 10:13:40.721450 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13593 10:13:40.721621 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13594 10:13:40.721781 arm64_za-ptrace_Set_VL_3456 pass
13595 10:13:40.721954 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13596 10:13:40.722107 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13597 10:13:40.722260 arm64_za-ptrace_Set_VL_3472 pass
13598 10:13:40.722414 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13599 10:13:40.722572 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13600 10:13:40.722740 arm64_za-ptrace_Set_VL_3488 pass
13601 10:13:40.722885 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13602 10:13:40.723008 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13603 10:13:40.723179 arm64_za-ptrace_Set_VL_3504 pass
13604 10:13:40.723384 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13605 10:13:40.723555 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13606 10:13:40.723718 arm64_za-ptrace_Set_VL_3520 pass
13607 10:13:40.723844 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13608 10:13:40.723956 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13609 10:13:40.724069 arm64_za-ptrace_Set_VL_3536 pass
13610 10:13:40.724193 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13611 10:13:40.724302 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13612 10:13:40.724411 arm64_za-ptrace_Set_VL_3552 pass
13613 10:13:40.724519 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13614 10:13:40.724628 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13615 10:13:40.724736 arm64_za-ptrace_Set_VL_3568 pass
13616 10:13:40.724873 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13617 10:13:40.724990 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13618 10:13:40.725100 arm64_za-ptrace_Set_VL_3584 pass
13619 10:13:40.725209 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13620 10:13:40.725317 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13621 10:13:40.740181 arm64_za-ptrace_Set_VL_3600 pass
13622 10:13:40.740521 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13623 10:13:40.740624 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13624 10:13:40.740711 arm64_za-ptrace_Set_VL_3616 pass
13625 10:13:40.740809 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13626 10:13:40.740926 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13627 10:13:40.741035 arm64_za-ptrace_Set_VL_3632 pass
13628 10:13:40.741319 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13629 10:13:40.741407 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13630 10:13:40.741487 arm64_za-ptrace_Set_VL_3648 pass
13631 10:13:40.741583 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13632 10:13:40.741674 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13633 10:13:40.741770 arm64_za-ptrace_Set_VL_3664 pass
13634 10:13:40.741864 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13635 10:13:40.742145 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13636 10:13:40.742231 arm64_za-ptrace_Set_VL_3680 pass
13637 10:13:40.742326 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13638 10:13:40.742421 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13639 10:13:40.742504 arm64_za-ptrace_Set_VL_3696 pass
13640 10:13:40.742597 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13641 10:13:40.742694 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13642 10:13:40.742789 arm64_za-ptrace_Set_VL_3712 pass
13643 10:13:40.743070 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13644 10:13:40.743155 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13645 10:13:40.743249 arm64_za-ptrace_Set_VL_3728 pass
13646 10:13:40.743343 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13647 10:13:40.743437 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13648 10:13:40.743530 arm64_za-ptrace_Set_VL_3744 pass
13649 10:13:40.743818 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13650 10:13:40.743904 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13651 10:13:40.743982 arm64_za-ptrace_Set_VL_3760 pass
13652 10:13:40.744079 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13653 10:13:40.744173 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13654 10:13:40.744266 arm64_za-ptrace_Set_VL_3776 pass
13655 10:13:40.744359 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13656 10:13:40.748739 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13657 10:13:40.749075 arm64_za-ptrace_Set_VL_3792 pass
13658 10:13:40.749164 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13659 10:13:40.749244 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13660 10:13:40.749326 arm64_za-ptrace_Set_VL_3808 pass
13661 10:13:40.749422 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13662 10:13:40.749504 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13663 10:13:40.749600 arm64_za-ptrace_Set_VL_3824 pass
13664 10:13:40.749691 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13665 10:13:40.749788 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13666 10:13:40.749882 arm64_za-ptrace_Set_VL_3840 pass
13667 10:13:40.750164 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13668 10:13:40.750265 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13669 10:13:40.750349 arm64_za-ptrace_Set_VL_3856 pass
13670 10:13:40.750443 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13671 10:13:40.750723 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13672 10:13:40.750809 arm64_za-ptrace_Set_VL_3872 pass
13673 10:13:40.750905 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13674 10:13:40.750987 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13675 10:13:40.751067 arm64_za-ptrace_Set_VL_3888 pass
13676 10:13:40.751161 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13677 10:13:40.751255 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13678 10:13:40.751359 arm64_za-ptrace_Set_VL_3904 pass
13679 10:13:40.751479 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13680 10:13:40.751759 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13681 10:13:40.751858 arm64_za-ptrace_Set_VL_3920 pass
13682 10:13:40.751941 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13683 10:13:40.752041 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13684 10:13:40.752122 arm64_za-ptrace_Set_VL_3936 pass
13685 10:13:40.752216 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13686 10:13:40.752499 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13687 10:13:40.752589 arm64_za-ptrace_Set_VL_3952 pass
13688 10:13:40.756680 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13689 10:13:40.756965 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13690 10:13:40.757051 arm64_za-ptrace_Set_VL_3968 pass
13691 10:13:40.757131 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13692 10:13:40.757227 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13693 10:13:40.757306 arm64_za-ptrace_Set_VL_3984 pass
13694 10:13:40.757400 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13695 10:13:40.757495 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13696 10:13:40.757591 arm64_za-ptrace_Set_VL_4000 pass
13697 10:13:40.757723 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13698 10:13:40.757821 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13699 10:13:40.757920 arm64_za-ptrace_Set_VL_4016 pass
13700 10:13:40.758026 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13701 10:13:40.758344 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13702 10:13:40.758460 arm64_za-ptrace_Set_VL_4032 pass
13703 10:13:40.758564 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13704 10:13:40.758651 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13705 10:13:40.758750 arm64_za-ptrace_Set_VL_4048 pass
13706 10:13:40.758837 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13707 10:13:40.758936 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13708 10:13:40.759023 arm64_za-ptrace_Set_VL_4064 pass
13709 10:13:40.759124 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13710 10:13:40.759209 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13711 10:13:40.759306 arm64_za-ptrace_Set_VL_4080 pass
13712 10:13:40.759392 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13713 10:13:40.759474 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13714 10:13:40.759572 arm64_za-ptrace_Set_VL_4096 pass
13715 10:13:40.759661 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13716 10:13:40.759759 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13717 10:13:40.759860 arm64_za-ptrace_Set_VL_4112 pass
13718 10:13:40.759947 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13719 10:13:40.760047 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13720 10:13:40.760132 arm64_za-ptrace_Set_VL_4128 pass
13721 10:13:40.760214 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13722 10:13:40.760312 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13723 10:13:40.760403 arm64_za-ptrace_Set_VL_4144 pass
13724 10:13:40.760502 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13725 10:13:40.760587 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13726 10:13:40.760671 arm64_za-ptrace_Set_VL_4160 pass
13727 10:13:40.764804 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13728 10:13:40.765157 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13729 10:13:40.765251 arm64_za-ptrace_Set_VL_4176 pass
13730 10:13:40.765337 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13731 10:13:40.765421 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13732 10:13:40.765505 arm64_za-ptrace_Set_VL_4192 pass
13733 10:13:40.765606 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13734 10:13:40.765729 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13735 10:13:40.765872 arm64_za-ptrace_Set_VL_4208 pass
13736 10:13:40.765994 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13737 10:13:40.766093 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13738 10:13:40.766178 arm64_za-ptrace_Set_VL_4224 pass
13739 10:13:40.766286 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13740 10:13:40.766375 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13741 10:13:40.766459 arm64_za-ptrace_Set_VL_4240 pass
13742 10:13:40.766543 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13743 10:13:40.766626 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13744 10:13:40.766708 arm64_za-ptrace_Set_VL_4256 pass
13745 10:13:40.766790 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13746 10:13:40.766872 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13747 10:13:40.766974 arm64_za-ptrace_Set_VL_4272 pass
13748 10:13:40.767059 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13749 10:13:40.767143 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13750 10:13:40.767225 arm64_za-ptrace_Set_VL_4288 pass
13751 10:13:40.767308 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13752 10:13:40.767394 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13753 10:13:40.767478 arm64_za-ptrace_Set_VL_4304 pass
13754 10:13:40.767560 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13755 10:13:40.767663 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13756 10:13:40.767750 arm64_za-ptrace_Set_VL_4320 pass
13757 10:13:40.767833 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13758 10:13:40.767916 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13759 10:13:40.767999 arm64_za-ptrace_Set_VL_4336 pass
13760 10:13:40.768086 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13761 10:13:40.768169 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13762 10:13:40.768252 arm64_za-ptrace_Set_VL_4352 pass
13763 10:13:40.768336 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13764 10:13:40.768437 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13765 10:13:40.768524 arm64_za-ptrace_Set_VL_4368 pass
13766 10:13:40.768642 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13767 10:13:40.768728 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13768 10:13:40.768815 arm64_za-ptrace_Set_VL_4384 pass
13769 10:13:40.768925 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13770 10:13:40.769037 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13771 10:13:40.769170 arm64_za-ptrace_Set_VL_4400 pass
13772 10:13:40.769261 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13773 10:13:40.769580 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13774 10:13:40.769746 arm64_za-ptrace_Set_VL_4416 pass
13775 10:13:40.772834 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13776 10:13:40.773305 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13777 10:13:40.773420 arm64_za-ptrace_Set_VL_4432 pass
13778 10:13:40.773514 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13779 10:13:40.773602 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13780 10:13:40.773724 arm64_za-ptrace_Set_VL_4448 pass
13781 10:13:40.773816 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13782 10:13:40.773908 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13783 10:13:40.773998 arm64_za-ptrace_Set_VL_4464 pass
13784 10:13:40.774109 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13785 10:13:40.774203 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13786 10:13:40.774292 arm64_za-ptrace_Set_VL_4480 pass
13787 10:13:40.774398 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13788 10:13:40.774489 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13789 10:13:40.774597 arm64_za-ptrace_Set_VL_4496 pass
13790 10:13:40.774690 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13791 10:13:40.774797 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13792 10:13:40.774891 arm64_za-ptrace_Set_VL_4512 pass
13793 10:13:40.775417 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13794 10:13:40.775632 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13795 10:13:40.775812 arm64_za-ptrace_Set_VL_4528 pass
13796 10:13:40.775984 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13797 10:13:40.776419 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13798 10:13:40.776614 arm64_za-ptrace_Set_VL_4544 pass
13799 10:13:40.776771 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13800 10:13:40.776924 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13801 10:13:40.777077 arm64_za-ptrace_Set_VL_4560 pass
13802 10:13:40.777214 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13803 10:13:40.777369 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13804 10:13:40.777539 arm64_za-ptrace_Set_VL_4576 pass
13805 10:13:40.777720 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13806 10:13:40.777890 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13807 10:13:40.778089 arm64_za-ptrace_Set_VL_4592 pass
13808 10:13:40.780770 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13809 10:13:40.781233 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13810 10:13:40.781441 arm64_za-ptrace_Set_VL_4608 pass
13811 10:13:40.781616 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13812 10:13:40.781808 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13813 10:13:40.782009 arm64_za-ptrace_Set_VL_4624 pass
13814 10:13:40.795782 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13815 10:13:40.796011 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13816 10:13:40.796228 arm64_za-ptrace_Set_VL_4640 pass
13817 10:13:40.796410 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13818 10:13:40.796586 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13819 10:13:40.796764 arm64_za-ptrace_Set_VL_4656 pass
13820 10:13:40.796979 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13821 10:13:40.797160 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13822 10:13:40.797336 arm64_za-ptrace_Set_VL_4672 pass
13823 10:13:40.797512 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13824 10:13:40.797700 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13825 10:13:40.797877 arm64_za-ptrace_Set_VL_4688 pass
13826 10:13:40.798057 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13827 10:13:40.798272 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13828 10:13:40.798453 arm64_za-ptrace_Set_VL_4704 pass
13829 10:13:40.798629 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13830 10:13:40.798804 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13831 10:13:40.798980 arm64_za-ptrace_Set_VL_4720 pass
13832 10:13:40.799157 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13833 10:13:40.799332 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13834 10:13:40.799508 arm64_za-ptrace_Set_VL_4736 pass
13835 10:13:40.799683 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13836 10:13:40.799860 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13837 10:13:40.800035 arm64_za-ptrace_Set_VL_4752 pass
13838 10:13:40.800210 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13839 10:13:40.800427 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13840 10:13:40.800607 arm64_za-ptrace_Set_VL_4768 pass
13841 10:13:40.800782 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13842 10:13:40.800956 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13843 10:13:40.801133 arm64_za-ptrace_Set_VL_4784 pass
13844 10:13:40.801307 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13845 10:13:40.801482 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13846 10:13:40.801666 arm64_za-ptrace_Set_VL_4800 pass
13847 10:13:40.801841 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13848 10:13:40.802014 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13849 10:13:40.802188 arm64_za-ptrace_Set_VL_4816 pass
13850 10:13:40.802361 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13851 10:13:40.802535 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13852 10:13:40.802710 arm64_za-ptrace_Set_VL_4832 pass
13853 10:13:40.802884 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13854 10:13:40.803058 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13855 10:13:40.803232 arm64_za-ptrace_Set_VL_4848 pass
13856 10:13:40.803408 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13857 10:13:40.803583 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13858 10:13:40.803758 arm64_za-ptrace_Set_VL_4864 pass
13859 10:13:40.804165 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13860 10:13:40.804352 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13861 10:13:40.804527 arm64_za-ptrace_Set_VL_4880 pass
13862 10:13:40.804725 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13863 10:13:40.804937 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13864 10:13:40.805119 arm64_za-ptrace_Set_VL_4896 pass
13865 10:13:40.805325 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13866 10:13:40.805505 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13867 10:13:40.805693 arm64_za-ptrace_Set_VL_4912 pass
13868 10:13:40.805905 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13869 10:13:40.806084 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13870 10:13:40.806260 arm64_za-ptrace_Set_VL_4928 pass
13871 10:13:40.806435 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13872 10:13:40.806610 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13873 10:13:40.806784 arm64_za-ptrace_Set_VL_4944 pass
13874 10:13:40.806994 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13875 10:13:40.807173 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13876 10:13:40.807347 arm64_za-ptrace_Set_VL_4960 pass
13877 10:13:40.807522 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13878 10:13:40.807696 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13879 10:13:40.807871 arm64_za-ptrace_Set_VL_4976 pass
13880 10:13:40.808046 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13881 10:13:40.808221 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13882 10:13:40.808396 arm64_za-ptrace_Set_VL_4992 pass
13883 10:13:40.808569 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13884 10:13:40.808783 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13885 10:13:40.808962 arm64_za-ptrace_Set_VL_5008 pass
13886 10:13:40.809138 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13887 10:13:40.809312 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13888 10:13:40.809488 arm64_za-ptrace_Set_VL_5024 pass
13889 10:13:40.809670 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13890 10:13:40.809847 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13891 10:13:40.810010 arm64_za-ptrace_Set_VL_5040 pass
13892 10:13:40.810184 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13893 10:13:40.810360 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13894 10:13:40.810534 arm64_za-ptrace_Set_VL_5056 pass
13895 10:13:40.810709 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13896 10:13:40.810883 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13897 10:13:40.811059 arm64_za-ptrace_Set_VL_5072 pass
13898 10:13:40.812920 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13899 10:13:40.813135 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13900 10:13:40.813318 arm64_za-ptrace_Set_VL_5088 pass
13901 10:13:40.813528 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13902 10:13:40.813722 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13903 10:13:40.813901 arm64_za-ptrace_Set_VL_5104 pass
13904 10:13:40.814076 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13905 10:13:40.814288 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13906 10:13:40.814468 arm64_za-ptrace_Set_VL_5120 pass
13907 10:13:40.814644 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13908 10:13:40.814820 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13909 10:13:40.814996 arm64_za-ptrace_Set_VL_5136 pass
13910 10:13:40.815171 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13911 10:13:40.815345 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13912 10:13:40.815521 arm64_za-ptrace_Set_VL_5152 pass
13913 10:13:40.815736 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13914 10:13:40.815916 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13915 10:13:40.816093 arm64_za-ptrace_Set_VL_5168 pass
13916 10:13:40.816270 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13917 10:13:40.816446 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13918 10:13:40.816619 arm64_za-ptrace_Set_VL_5184 pass
13919 10:13:40.816794 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13920 10:13:40.816970 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13921 10:13:40.817146 arm64_za-ptrace_Set_VL_5200 pass
13922 10:13:40.817320 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13923 10:13:40.817477 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13924 10:13:40.817628 arm64_za-ptrace_Set_VL_5216 pass
13925 10:13:40.817794 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13926 10:13:40.817945 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13927 10:13:40.818096 arm64_za-ptrace_Set_VL_5232 pass
13928 10:13:40.818270 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
13929 10:13:40.818483 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
13930 10:13:40.818659 arm64_za-ptrace_Set_VL_5248 pass
13931 10:13:40.818828 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
13932 10:13:40.818996 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
13933 10:13:40.819164 arm64_za-ptrace_Set_VL_5264 pass
13934 10:13:40.819317 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
13935 10:13:40.819468 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
13936 10:13:40.820741 arm64_za-ptrace_Set_VL_5280 pass
13937 10:13:40.821121 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
13938 10:13:40.821429 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
13939 10:13:40.821526 arm64_za-ptrace_Set_VL_5296 pass
13940 10:13:40.821609 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
13941 10:13:40.821713 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
13942 10:13:40.821797 arm64_za-ptrace_Set_VL_5312 pass
13943 10:13:40.821878 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
13944 10:13:40.821972 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
13945 10:13:40.822054 arm64_za-ptrace_Set_VL_5328 pass
13946 10:13:40.822147 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
13947 10:13:40.822243 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
13948 10:13:40.822338 arm64_za-ptrace_Set_VL_5344 pass
13949 10:13:40.822647 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
13950 10:13:40.822741 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
13951 10:13:40.822836 arm64_za-ptrace_Set_VL_5360 pass
13952 10:13:40.822929 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
13953 10:13:40.823236 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
13954 10:13:40.823333 arm64_za-ptrace_Set_VL_5376 pass
13955 10:13:40.823412 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
13956 10:13:40.823511 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
13957 10:13:40.823596 arm64_za-ptrace_Set_VL_5392 pass
13958 10:13:40.823690 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
13959 10:13:40.823972 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
13960 10:13:40.824060 arm64_za-ptrace_Set_VL_5408 pass
13961 10:13:40.824155 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
13962 10:13:40.824237 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
13963 10:13:40.824331 arm64_za-ptrace_Set_VL_5424 pass
13964 10:13:40.824424 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
13965 10:13:40.828866 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
13966 10:13:40.829274 arm64_za-ptrace_Set_VL_5440 pass
13967 10:13:40.829376 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
13968 10:13:40.829455 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
13969 10:13:40.829531 arm64_za-ptrace_Set_VL_5456 pass
13970 10:13:40.829624 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
13971 10:13:40.829712 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
13972 10:13:40.829783 arm64_za-ptrace_Set_VL_5472 pass
13973 10:13:40.829860 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
13974 10:13:40.829924 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
13975 10:13:40.829984 arm64_za-ptrace_Set_VL_5488 pass
13976 10:13:40.830059 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
13977 10:13:40.830123 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
13978 10:13:40.830195 arm64_za-ptrace_Set_VL_5504 pass
13979 10:13:40.830448 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
13980 10:13:40.830518 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
13981 10:13:40.830592 arm64_za-ptrace_Set_VL_5520 pass
13982 10:13:40.830666 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
13983 10:13:40.830729 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
13984 10:13:40.830971 arm64_za-ptrace_Set_VL_5536 pass
13985 10:13:40.831038 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
13986 10:13:40.831100 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
13987 10:13:40.831174 arm64_za-ptrace_Set_VL_5552 pass
13988 10:13:40.831237 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
13989 10:13:40.831310 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
13990 10:13:40.831372 arm64_za-ptrace_Set_VL_5568 pass
13991 10:13:40.831433 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
13992 10:13:40.831504 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
13993 10:13:40.831566 arm64_za-ptrace_Set_VL_5584 pass
13994 10:13:40.831808 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
13995 10:13:40.831874 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
13996 10:13:40.831936 arm64_za-ptrace_Set_VL_5600 pass
13997 10:13:40.831997 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
13998 10:13:40.832069 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
13999 10:13:40.832130 arm64_za-ptrace_Set_VL_5616 pass
14000 10:13:40.832201 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
14001 10:13:40.832265 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
14002 10:13:40.832336 arm64_za-ptrace_Set_VL_5632 pass
14003 10:13:40.832435 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
14004 10:13:40.836836 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
14005 10:13:40.837149 arm64_za-ptrace_Set_VL_5648 pass
14006 10:13:40.852996 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
14007 10:13:40.853170 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
14008 10:13:40.853446 arm64_za-ptrace_Set_VL_5664 pass
14009 10:13:40.853527 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
14010 10:13:40.853592 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
14011 10:13:40.853673 arm64_za-ptrace_Set_VL_5680 pass
14012 10:13:40.853749 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
14013 10:13:40.853865 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
14014 10:13:40.853941 arm64_za-ptrace_Set_VL_5696 pass
14015 10:13:40.854014 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
14016 10:13:40.854089 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
14017 10:13:40.854165 arm64_za-ptrace_Set_VL_5712 pass
14018 10:13:40.854234 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
14019 10:13:40.854298 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
14020 10:13:40.854377 arm64_za-ptrace_Set_VL_5728 pass
14021 10:13:40.854444 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
14022 10:13:40.854503 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
14023 10:13:40.854577 arm64_za-ptrace_Set_VL_5744 pass
14024 10:13:40.854641 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
14025 10:13:40.854718 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
14026 10:13:40.854783 arm64_za-ptrace_Set_VL_5760 pass
14027 10:13:40.854857 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
14028 10:13:40.854955 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
14029 10:13:40.855022 arm64_za-ptrace_Set_VL_5776 pass
14030 10:13:40.855096 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
14031 10:13:40.855190 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
14032 10:13:40.855263 arm64_za-ptrace_Set_VL_5792 pass
14033 10:13:40.855339 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
14034 10:13:40.855586 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
14035 10:13:40.855671 arm64_za-ptrace_Set_VL_5808 pass
14036 10:13:40.855749 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
14037 10:13:40.855841 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
14038 10:13:40.855923 arm64_za-ptrace_Set_VL_5824 pass
14039 10:13:40.856014 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
14040 10:13:40.856088 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
14041 10:13:40.856165 arm64_za-ptrace_Set_VL_5840 pass
14042 10:13:40.856249 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
14043 10:13:40.856337 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
14044 10:13:40.856612 arm64_za-ptrace_Set_VL_5856 pass
14045 10:13:40.856687 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
14046 10:13:40.860688 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
14047 10:13:40.860988 arm64_za-ptrace_Set_VL_5872 pass
14048 10:13:40.861084 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
14049 10:13:40.861171 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
14050 10:13:40.861251 arm64_za-ptrace_Set_VL_5888 pass
14051 10:13:40.861325 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
14052 10:13:40.861413 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
14053 10:13:40.861492 arm64_za-ptrace_Set_VL_5904 pass
14054 10:13:40.861564 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
14055 10:13:40.861635 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
14056 10:13:40.861730 arm64_za-ptrace_Set_VL_5920 pass
14057 10:13:40.861807 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
14058 10:13:40.861883 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
14059 10:13:40.861981 arm64_za-ptrace_Set_VL_5936 pass
14060 10:13:40.862073 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
14061 10:13:40.862166 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
14062 10:13:40.862286 arm64_za-ptrace_Set_VL_5952 pass
14063 10:13:40.862384 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
14064 10:13:40.862495 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
14065 10:13:40.862595 arm64_za-ptrace_Set_VL_5968 pass
14066 10:13:40.862711 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
14067 10:13:40.862804 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
14068 10:13:40.862897 arm64_za-ptrace_Set_VL_5984 pass
14069 10:13:40.862966 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
14070 10:13:40.863086 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
14071 10:13:40.863173 arm64_za-ptrace_Set_VL_6000 pass
14072 10:13:40.863252 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
14073 10:13:40.863326 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
14074 10:13:40.863390 arm64_za-ptrace_Set_VL_6016 pass
14075 10:13:40.863490 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
14076 10:13:40.863591 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
14077 10:13:40.863690 arm64_za-ptrace_Set_VL_6032 pass
14078 10:13:40.863786 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
14079 10:13:40.863865 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
14080 10:13:40.863929 arm64_za-ptrace_Set_VL_6048 pass
14081 10:13:40.864196 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
14082 10:13:40.864292 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
14083 10:13:40.864369 arm64_za-ptrace_Set_VL_6064 pass
14084 10:13:40.864471 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
14085 10:13:40.864558 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
14086 10:13:40.864629 arm64_za-ptrace_Set_VL_6080 pass
14087 10:13:40.864688 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
14088 10:13:40.868673 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
14089 10:13:40.869001 arm64_za-ptrace_Set_VL_6096 pass
14090 10:13:40.869104 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
14091 10:13:40.869199 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
14092 10:13:40.869285 arm64_za-ptrace_Set_VL_6112 pass
14093 10:13:40.869368 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
14094 10:13:40.869441 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
14095 10:13:40.869515 arm64_za-ptrace_Set_VL_6128 pass
14096 10:13:40.869585 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
14097 10:13:40.869678 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
14098 10:13:40.869753 arm64_za-ptrace_Set_VL_6144 pass
14099 10:13:40.869826 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
14100 10:13:40.869911 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
14101 10:13:40.869994 arm64_za-ptrace_Set_VL_6160 pass
14102 10:13:40.870085 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
14103 10:13:40.870150 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
14104 10:13:40.870229 arm64_za-ptrace_Set_VL_6176 pass
14105 10:13:40.870310 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
14106 10:13:40.870397 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
14107 10:13:40.870652 arm64_za-ptrace_Set_VL_6192 pass
14108 10:13:40.870721 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
14109 10:13:40.870798 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
14110 10:13:40.870886 arm64_za-ptrace_Set_VL_6208 pass
14111 10:13:40.870959 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
14112 10:13:40.871046 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
14113 10:13:40.871125 arm64_za-ptrace_Set_VL_6224 pass
14114 10:13:40.871225 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
14115 10:13:40.871325 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
14116 10:13:40.871418 arm64_za-ptrace_Set_VL_6240 pass
14117 10:13:40.871511 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
14118 10:13:40.871792 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
14119 10:13:40.871888 arm64_za-ptrace_Set_VL_6256 pass
14120 10:13:40.872005 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
14121 10:13:40.872097 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
14122 10:13:40.872203 arm64_za-ptrace_Set_VL_6272 pass
14123 10:13:40.872291 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
14124 10:13:40.872376 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
14125 10:13:40.872447 arm64_za-ptrace_Set_VL_6288 pass
14126 10:13:40.872534 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
14127 10:13:40.876756 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
14128 10:13:40.877030 arm64_za-ptrace_Set_VL_6304 pass
14129 10:13:40.877117 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
14130 10:13:40.877209 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
14131 10:13:40.877291 arm64_za-ptrace_Set_VL_6320 pass
14132 10:13:40.877380 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
14133 10:13:40.877449 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
14134 10:13:40.877521 arm64_za-ptrace_Set_VL_6336 pass
14135 10:13:40.877609 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
14136 10:13:40.877684 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
14137 10:13:40.877757 arm64_za-ptrace_Set_VL_6352 pass
14138 10:13:40.877845 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
14139 10:13:40.877914 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
14140 10:13:40.878002 arm64_za-ptrace_Set_VL_6368 pass
14141 10:13:40.878071 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
14142 10:13:40.878143 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
14143 10:13:40.878231 arm64_za-ptrace_Set_VL_6384 pass
14144 10:13:40.878304 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
14145 10:13:40.878391 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
14146 10:13:40.878461 arm64_za-ptrace_Set_VL_6400 pass
14147 10:13:40.878548 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
14148 10:13:40.878616 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
14149 10:13:40.878703 arm64_za-ptrace_Set_VL_6416 pass
14150 10:13:40.878787 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
14151 10:13:40.878856 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
14152 10:13:40.878943 arm64_za-ptrace_Set_VL_6432 pass
14153 10:13:40.879012 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
14154 10:13:40.879100 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
14155 10:13:40.879169 arm64_za-ptrace_Set_VL_6448 pass
14156 10:13:40.879259 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
14157 10:13:40.879341 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
14158 10:13:40.879424 arm64_za-ptrace_Set_VL_6464 pass
14159 10:13:40.879506 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
14160 10:13:40.879600 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
14161 10:13:40.879685 arm64_za-ptrace_Set_VL_6480 pass
14162 10:13:40.879952 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
14163 10:13:40.880049 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
14164 10:13:40.880141 arm64_za-ptrace_Set_VL_6496 pass
14165 10:13:40.880239 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
14166 10:13:40.880324 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
14167 10:13:40.880417 arm64_za-ptrace_Set_VL_6512 pass
14168 10:13:40.880497 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
14169 10:13:40.884691 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
14170 10:13:40.884824 arm64_za-ptrace_Set_VL_6528 pass
14171 10:13:40.885136 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
14172 10:13:40.885259 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14173 10:13:40.885346 arm64_za-ptrace_Set_VL_6544 pass
14174 10:13:40.885419 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14175 10:13:40.885513 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14176 10:13:40.885599 arm64_za-ptrace_Set_VL_6560 pass
14177 10:13:40.885682 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14178 10:13:40.885747 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14179 10:13:40.885820 arm64_za-ptrace_Set_VL_6576 pass
14180 10:13:40.885881 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14181 10:13:40.885940 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14182 10:13:40.886013 arm64_za-ptrace_Set_VL_6592 pass
14183 10:13:40.886079 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14184 10:13:40.886167 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14185 10:13:40.886258 arm64_za-ptrace_Set_VL_6608 pass
14186 10:13:40.886336 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14187 10:13:40.886601 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14188 10:13:40.886683 arm64_za-ptrace_Set_VL_6624 pass
14189 10:13:40.886793 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14190 10:13:40.886874 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14191 10:13:40.886946 arm64_za-ptrace_Set_VL_6640 pass
14192 10:13:40.887053 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14193 10:13:40.887129 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14194 10:13:40.887195 arm64_za-ptrace_Set_VL_6656 pass
14195 10:13:40.887278 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14196 10:13:40.887355 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14197 10:13:40.887449 arm64_za-ptrace_Set_VL_6672 pass
14198 10:13:40.887871 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14199 10:13:40.904708 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14200 10:13:40.904822 arm64_za-ptrace_Set_VL_6688 pass
14201 10:13:40.905123 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14202 10:13:40.905211 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14203 10:13:40.905304 arm64_za-ptrace_Set_VL_6704 pass
14204 10:13:40.905398 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14205 10:13:40.905516 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14206 10:13:40.905605 arm64_za-ptrace_Set_VL_6720 pass
14207 10:13:40.905700 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14208 10:13:40.905774 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14209 10:13:40.905845 arm64_za-ptrace_Set_VL_6736 pass
14210 10:13:40.905934 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14211 10:13:40.906003 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14212 10:13:40.906076 arm64_za-ptrace_Set_VL_6752 pass
14213 10:13:40.906163 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14214 10:13:40.906232 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14215 10:13:40.906305 arm64_za-ptrace_Set_VL_6768 pass
14216 10:13:40.906378 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14217 10:13:40.906465 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14218 10:13:40.906534 arm64_za-ptrace_Set_VL_6784 pass
14219 10:13:40.906605 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14220 10:13:40.906693 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14221 10:13:40.906760 arm64_za-ptrace_Set_VL_6800 pass
14222 10:13:40.906832 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14223 10:13:40.906920 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14224 10:13:40.906988 arm64_za-ptrace_Set_VL_6816 pass
14225 10:13:40.907074 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14226 10:13:40.907142 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14227 10:13:40.907229 arm64_za-ptrace_Set_VL_6832 pass
14228 10:13:40.907298 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14229 10:13:40.907385 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14230 10:13:40.907467 arm64_za-ptrace_Set_VL_6848 pass
14231 10:13:40.907549 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14232 10:13:40.907632 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14233 10:13:40.907700 arm64_za-ptrace_Set_VL_6864 pass
14234 10:13:40.907786 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14235 10:13:40.907868 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14236 10:13:40.907951 arm64_za-ptrace_Set_VL_6880 pass
14237 10:13:40.908033 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14238 10:13:40.908115 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14239 10:13:40.908197 arm64_za-ptrace_Set_VL_6896 pass
14240 10:13:40.908279 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14241 10:13:40.908537 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14242 10:13:40.908607 arm64_za-ptrace_Set_VL_6912 pass
14243 10:13:40.916621 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14244 10:13:40.916910 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14245 10:13:40.917018 arm64_za-ptrace_Set_VL_6928 pass
14246 10:13:40.917126 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14247 10:13:40.917216 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14248 10:13:40.917321 arm64_za-ptrace_Set_VL_6944 pass
14249 10:13:40.917391 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14250 10:13:40.917463 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14251 10:13:40.917534 arm64_za-ptrace_Set_VL_6960 pass
14252 10:13:40.917622 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14253 10:13:40.917697 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14254 10:13:40.917770 arm64_za-ptrace_Set_VL_6976 pass
14255 10:13:40.917841 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14256 10:13:40.917929 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14257 10:13:40.917997 arm64_za-ptrace_Set_VL_6992 pass
14258 10:13:40.918068 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14259 10:13:40.918156 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14260 10:13:40.918225 arm64_za-ptrace_Set_VL_7008 pass
14261 10:13:40.918296 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14262 10:13:40.918383 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14263 10:13:40.918451 arm64_za-ptrace_Set_VL_7024 pass
14264 10:13:40.918538 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14265 10:13:40.918606 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14266 10:13:40.918694 arm64_za-ptrace_Set_VL_7040 pass
14267 10:13:40.918762 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14268 10:13:40.918849 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14269 10:13:40.918917 arm64_za-ptrace_Set_VL_7056 pass
14270 10:13:40.919004 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14271 10:13:40.919097 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14272 10:13:40.919182 arm64_za-ptrace_Set_VL_7072 pass
14273 10:13:40.919448 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14274 10:13:40.919533 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14275 10:13:40.919609 arm64_za-ptrace_Set_VL_7088 pass
14276 10:13:40.919691 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14277 10:13:40.919764 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14278 10:13:40.919848 arm64_za-ptrace_Set_VL_7104 pass
14279 10:13:40.919919 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14280 10:13:40.919991 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14281 10:13:40.920089 arm64_za-ptrace_Set_VL_7120 pass
14282 10:13:40.920181 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14283 10:13:40.920264 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14284 10:13:40.920347 arm64_za-ptrace_Set_VL_7136 pass
14285 10:13:40.920421 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14286 10:13:40.920523 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14287 10:13:40.920635 arm64_za-ptrace_Set_VL_7152 pass
14288 10:13:40.920737 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14289 10:13:40.920833 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14290 10:13:40.920933 arm64_za-ptrace_Set_VL_7168 pass
14291 10:13:40.921038 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14292 10:13:40.921143 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14293 10:13:40.921244 arm64_za-ptrace_Set_VL_7184 pass
14294 10:13:40.921342 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14295 10:13:40.921457 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14296 10:13:40.921542 arm64_za-ptrace_Set_VL_7200 pass
14297 10:13:40.921651 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14298 10:13:40.921758 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14299 10:13:40.921844 arm64_za-ptrace_Set_VL_7216 pass
14300 10:13:40.921932 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14301 10:13:40.922028 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14302 10:13:40.922116 arm64_za-ptrace_Set_VL_7232 pass
14303 10:13:40.922203 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14304 10:13:40.922294 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14305 10:13:40.922366 arm64_za-ptrace_Set_VL_7248 pass
14306 10:13:40.922628 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14307 10:13:40.922726 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14308 10:13:40.922825 arm64_za-ptrace_Set_VL_7264 pass
14309 10:13:40.922915 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14310 10:13:40.923031 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14311 10:13:40.923118 arm64_za-ptrace_Set_VL_7280 pass
14312 10:13:40.923235 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14313 10:13:40.923322 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14314 10:13:40.923426 arm64_za-ptrace_Set_VL_7296 pass
14315 10:13:40.923508 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14316 10:13:40.923605 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14317 10:13:40.923713 arm64_za-ptrace_Set_VL_7312 pass
14318 10:13:40.923811 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14319 10:13:40.923907 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14320 10:13:40.924015 arm64_za-ptrace_Set_VL_7328 pass
14321 10:13:40.924120 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14322 10:13:40.924224 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14323 10:13:40.924333 arm64_za-ptrace_Set_VL_7344 pass
14324 10:13:40.924456 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14325 10:13:40.928631 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14326 10:13:40.928911 arm64_za-ptrace_Set_VL_7360 pass
14327 10:13:40.928987 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14328 10:13:40.929059 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14329 10:13:40.929150 arm64_za-ptrace_Set_VL_7376 pass
14330 10:13:40.929225 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14331 10:13:40.929318 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14332 10:13:40.929400 arm64_za-ptrace_Set_VL_7392 pass
14333 10:13:40.929490 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14334 10:13:40.929584 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14335 10:13:40.929706 arm64_za-ptrace_Set_VL_7408 pass
14336 10:13:40.929802 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14337 10:13:40.929889 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14338 10:13:40.929974 arm64_za-ptrace_Set_VL_7424 pass
14339 10:13:40.930050 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14340 10:13:40.930329 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14341 10:13:40.930424 arm64_za-ptrace_Set_VL_7440 pass
14342 10:13:40.930501 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14343 10:13:40.930601 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14344 10:13:40.930675 arm64_za-ptrace_Set_VL_7456 pass
14345 10:13:40.930749 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14346 10:13:40.930837 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14347 10:13:40.930907 arm64_za-ptrace_Set_VL_7472 pass
14348 10:13:40.930979 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14349 10:13:40.931067 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14350 10:13:40.931137 arm64_za-ptrace_Set_VL_7488 pass
14351 10:13:40.931224 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14352 10:13:40.931307 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14353 10:13:40.931383 arm64_za-ptrace_Set_VL_7504 pass
14354 10:13:40.931476 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14355 10:13:40.931567 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14356 10:13:40.931658 arm64_za-ptrace_Set_VL_7520 pass
14357 10:13:40.931728 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14358 10:13:40.931821 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14359 10:13:40.931909 arm64_za-ptrace_Set_VL_7536 pass
14360 10:13:40.931986 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14361 10:13:40.932071 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14362 10:13:40.932162 arm64_za-ptrace_Set_VL_7552 pass
14363 10:13:40.932252 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14364 10:13:40.932334 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14365 10:13:40.932428 arm64_za-ptrace_Set_VL_7568 pass
14366 10:13:40.936747 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14367 10:13:40.936857 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14368 10:13:40.937137 arm64_za-ptrace_Set_VL_7584 pass
14369 10:13:40.937236 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14370 10:13:40.937356 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14371 10:13:40.937436 arm64_za-ptrace_Set_VL_7600 pass
14372 10:13:40.937540 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14373 10:13:40.937626 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14374 10:13:40.937704 arm64_za-ptrace_Set_VL_7616 pass
14375 10:13:40.937778 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14376 10:13:40.937866 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14377 10:13:40.937944 arm64_za-ptrace_Set_VL_7632 pass
14378 10:13:40.938020 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14379 10:13:40.938108 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14380 10:13:40.938185 arm64_za-ptrace_Set_VL_7648 pass
14381 10:13:40.938266 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14382 10:13:40.938348 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14383 10:13:40.938437 arm64_za-ptrace_Set_VL_7664 pass
14384 10:13:40.938518 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14385 10:13:40.938604 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14386 10:13:40.938691 arm64_za-ptrace_Set_VL_7680 pass
14387 10:13:40.938777 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14388 10:13:40.938881 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14389 10:13:40.938967 arm64_za-ptrace_Set_VL_7696 pass
14390 10:13:40.939040 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14391 10:13:40.964248 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14392 10:13:40.964475 arm64_za-ptrace_Set_VL_7712 pass
14393 10:13:40.964858 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14394 10:13:40.964967 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14395 10:13:40.965053 arm64_za-ptrace_Set_VL_7728 pass
14396 10:13:40.965136 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14397 10:13:40.965219 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14398 10:13:40.965318 arm64_za-ptrace_Set_VL_7744 pass
14399 10:13:40.965403 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14400 10:13:40.965484 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14401 10:13:40.965565 arm64_za-ptrace_Set_VL_7760 pass
14402 10:13:40.965667 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14403 10:13:40.965750 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14404 10:13:40.965829 arm64_za-ptrace_Set_VL_7776 pass
14405 10:13:40.965922 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14406 10:13:40.966019 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14407 10:13:40.966135 arm64_za-ptrace_Set_VL_7792 pass
14408 10:13:40.966427 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14409 10:13:40.966534 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14410 10:13:40.966633 arm64_za-ptrace_Set_VL_7808 pass
14411 10:13:40.966730 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14412 10:13:40.966828 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14413 10:13:40.966923 arm64_za-ptrace_Set_VL_7824 pass
14414 10:13:40.967020 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14415 10:13:40.967314 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14416 10:13:40.967419 arm64_za-ptrace_Set_VL_7840 pass
14417 10:13:40.967519 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14418 10:13:40.967619 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14419 10:13:40.967716 arm64_za-ptrace_Set_VL_7856 pass
14420 10:13:40.967818 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14421 10:13:40.968138 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14422 10:13:40.968237 arm64_za-ptrace_Set_VL_7872 pass
14423 10:13:40.968335 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14424 10:13:40.968549 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14425 10:13:40.968660 arm64_za-ptrace_Set_VL_7888 pass
14426 10:13:40.972651 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14427 10:13:40.972941 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14428 10:13:40.973034 arm64_za-ptrace_Set_VL_7904 pass
14429 10:13:40.973129 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14430 10:13:40.973216 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14431 10:13:40.973311 arm64_za-ptrace_Set_VL_7920 pass
14432 10:13:40.973406 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14433 10:13:40.973512 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14434 10:13:40.973610 arm64_za-ptrace_Set_VL_7936 pass
14435 10:13:40.973740 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14436 10:13:40.974024 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14437 10:13:40.974128 arm64_za-ptrace_Set_VL_7952 pass
14438 10:13:40.974215 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14439 10:13:40.974315 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14440 10:13:40.974417 arm64_za-ptrace_Set_VL_7968 pass
14441 10:13:40.974517 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14442 10:13:40.974698 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14443 10:13:40.974912 arm64_za-ptrace_Set_VL_7984 pass
14444 10:13:40.975072 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14445 10:13:40.975247 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14446 10:13:40.975404 arm64_za-ptrace_Set_VL_8000 pass
14447 10:13:40.975568 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14448 10:13:40.975735 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14449 10:13:40.975882 arm64_za-ptrace_Set_VL_8016 pass
14450 10:13:40.976081 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14451 10:13:40.976255 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14452 10:13:40.976538 arm64_za-ptrace_Set_VL_8032 pass
14453 10:13:40.976686 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14454 10:13:40.976807 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14455 10:13:40.976922 arm64_za-ptrace_Set_VL_8048 pass
14456 10:13:40.977037 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14457 10:13:40.977150 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14458 10:13:40.977264 arm64_za-ptrace_Set_VL_8064 pass
14459 10:13:40.980885 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14460 10:13:40.980987 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14461 10:13:40.981071 arm64_za-ptrace_Set_VL_8080 pass
14462 10:13:40.981168 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14463 10:13:40.981253 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14464 10:13:40.981351 arm64_za-ptrace_Set_VL_8096 pass
14465 10:13:40.981449 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14466 10:13:40.981743 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14467 10:13:40.981842 arm64_za-ptrace_Set_VL_8112 pass
14468 10:13:40.981926 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14469 10:13:40.982021 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14470 10:13:40.982120 arm64_za-ptrace_Set_VL_8128 pass
14471 10:13:40.982203 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14472 10:13:40.982299 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14473 10:13:40.982404 arm64_za-ptrace_Set_VL_8144 pass
14474 10:13:40.982700 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14475 10:13:40.982804 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14476 10:13:40.982902 arm64_za-ptrace_Set_VL_8160 pass
14477 10:13:40.982989 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14478 10:13:40.983085 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14479 10:13:40.983169 arm64_za-ptrace_Set_VL_8176 pass
14480 10:13:40.983369 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14481 10:13:40.983490 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14482 10:13:40.983588 arm64_za-ptrace_Set_VL_8192 pass
14483 10:13:40.983910 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14484 10:13:40.984102 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14485 10:13:40.984302 arm64_za-ptrace pass
14486 10:13:40.984456 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14487 10:13:40.984592 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14488 10:13:40.984738 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14489 10:13:40.988709 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14490 10:13:40.989126 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14491 10:13:40.989318 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14492 10:13:40.989504 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14493 10:13:40.989677 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14494 10:13:40.989866 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14495 10:13:40.990239 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14496 10:13:40.990341 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14497 10:13:40.990437 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14498 10:13:40.990754 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14499 10:13:40.990928 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14500 10:13:40.991090 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14501 10:13:40.991272 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14502 10:13:40.991707 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14503 10:13:40.991953 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14504 10:13:40.992141 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14505 10:13:40.992347 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14506 10:13:40.992524 arm64_check_buffer_fill fail
14507 10:13:40.992724 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14508 10:13:40.996733 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14509 10:13:40.997164 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14510 10:13:40.997351 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14511 10:13:40.997537 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14512 10:13:40.997742 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14513 10:13:40.997927 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14514 10:13:40.998114 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14515 10:13:40.998298 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14516 10:13:40.998472 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14517 10:13:40.998876 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14518 10:13:40.998994 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14519 10:13:40.999099 arm64_check_child_memory fail
14520 10:13:40.999197 arm64_check_gcr_el1_cswitch fail
14521 10:13:40.999294 arm64_check_ksm_options fail
14522 10:13:40.999585 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14523 10:13:40.999901 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14524 10:13:41.000216 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14525 10:13:41.000330 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14526 10:13:41.004664 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14527 10:13:41.006410 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14528 10:13:41.006874 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14529 10:13:41.007102 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14530 10:13:41.007309 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14531 10:13:41.007511 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14532 10:13:41.007947 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14533 10:13:41.008169 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14534 10:13:41.008358 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14535 10:13:41.008752 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14536 10:13:41.008946 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14537 10:13:41.009126 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14538 10:13:41.009477 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14539 10:13:41.009832 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14540 10:13:41.009984 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14541 10:13:41.010133 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14542 10:13:41.010497 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14543 10:13:41.010657 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14544 10:13:41.010814 arm64_check_mmap_options fail
14545 10:13:41.010997 arm64_check_prctl_check_basic_read pass
14546 10:13:41.011146 arm64_check_prctl_NONE pass
14547 10:13:41.011297 arm64_check_prctl_SYNC pass
14548 10:13:41.011452 arm64_check_prctl_ASYNC pass
14549 10:13:41.011638 arm64_check_prctl_SYNC_ASYNC pass
14550 10:13:41.011791 arm64_check_prctl pass
14551 10:13:41.011946 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14552 10:13:41.012104 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14553 10:13:41.012266 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14554 10:13:41.012469 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14555 10:13:41.012663 arm64_check_tags_inclusion fail
14556 10:13:41.012819 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14557 10:13:41.012944 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14558 10:13:41.013082 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14559 10:13:41.020680 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14560 10:13:41.021113 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14561 10:13:41.021311 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14562 10:13:41.021507 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14563 10:13:41.021689 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14564 10:13:41.021897 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14565 10:13:41.022060 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14566 10:13:41.022298 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14567 10:13:41.022478 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14568 10:13:41.022626 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14569 10:13:41.022787 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14570 10:13:41.022974 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14571 10:13:41.023175 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14572 10:13:41.023402 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14573 10:13:41.023614 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14574 10:13:41.023846 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14575 10:13:41.024064 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14576 10:13:41.024255 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14577 10:13:41.024477 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14578 10:13:41.028694 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14579 10:13:41.029106 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14580 10:13:41.029304 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14581 10:13:41.029468 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14582 10:13:41.029680 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14583 10:13:41.029866 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14584 10:13:41.030098 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14585 10:13:41.030268 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14586 10:13:41.030416 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14587 10:13:41.030786 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14588 10:13:41.030964 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14589 10:13:41.031186 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14590 10:13:41.031391 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14591 10:13:41.031585 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14592 10:13:41.031755 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14593 10:13:41.031955 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14594 10:13:41.032160 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14595 10:13:41.032377 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14596 10:13:41.032704 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14597 10:13:41.036680 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14598 10:13:41.037166 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14599 10:13:41.037362 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14600 10:13:41.037551 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14601 10:13:41.037727 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14602 10:13:41.037910 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14603 10:13:41.038100 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14604 10:13:41.038291 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14605 10:13:41.038483 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14606 10:13:41.038652 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14607 10:13:41.038832 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14608 10:13:41.039015 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14609 10:13:41.039183 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14610 10:13:41.039374 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14611 10:13:41.039567 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14612 10:13:41.039759 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14613 10:13:41.039941 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14614 10:13:41.040133 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14615 10:13:41.040334 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14616 10:13:41.044675 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14617 10:13:41.045075 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14618 10:13:41.054203 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14619 10:13:41.054604 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14620 10:13:41.054780 arm64_check_user_mem pass
14621 10:13:41.054960 arm64_btitest_nohint_func_call_using_br_x0 pass
14622 10:13:41.055137 arm64_btitest_nohint_func_call_using_br_x16 pass
14623 10:13:41.055345 arm64_btitest_nohint_func_call_using_blr pass
14624 10:13:41.055533 arm64_btitest_bti_none_func_call_using_br_x0 pass
14625 10:13:41.055697 arm64_btitest_bti_none_func_call_using_br_x16 pass
14626 10:13:41.055869 arm64_btitest_bti_none_func_call_using_blr pass
14627 10:13:41.056036 arm64_btitest_bti_c_func_call_using_br_x0 pass
14628 10:13:41.056233 arm64_btitest_bti_c_func_call_using_br_x16 pass
14629 10:13:41.056393 arm64_btitest_bti_c_func_call_using_blr pass
14630 10:13:41.056520 arm64_btitest_bti_j_func_call_using_br_x0 pass
14631 10:13:41.056639 arm64_btitest_bti_j_func_call_using_br_x16 pass
14632 10:13:41.056752 arm64_btitest_bti_j_func_call_using_blr pass
14633 10:13:41.056888 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14634 10:13:41.057039 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14635 10:13:41.057187 arm64_btitest_bti_jc_func_call_using_blr pass
14636 10:13:41.057334 arm64_btitest_paciasp_func_call_using_br_x0 pass
14637 10:13:41.057515 arm64_btitest_paciasp_func_call_using_br_x16 pass
14638 10:13:41.057688 arm64_btitest_paciasp_func_call_using_blr pass
14639 10:13:41.057846 arm64_btitest pass
14640 10:13:41.057997 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14641 10:13:41.058146 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14642 10:13:41.058298 arm64_nobtitest_nohint_func_call_using_blr pass
14643 10:13:41.058465 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14644 10:13:41.058623 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14645 10:13:41.058778 arm64_nobtitest_bti_none_func_call_using_blr pass
14646 10:13:41.058935 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14647 10:13:41.059111 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14648 10:13:41.059247 arm64_nobtitest_bti_c_func_call_using_blr pass
14649 10:13:41.059384 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14650 10:13:41.059535 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14651 10:13:41.059690 arm64_nobtitest_bti_j_func_call_using_blr pass
14652 10:13:41.059844 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14653 10:13:41.059995 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14654 10:13:41.060145 arm64_nobtitest_bti_jc_func_call_using_blr pass
14655 10:13:41.060298 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14656 10:13:41.060449 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14657 10:13:41.060605 arm64_nobtitest_paciasp_func_call_using_blr pass
14658 10:13:41.060732 arm64_nobtitest pass
14659 10:13:41.060842 arm64_hwcap_cpuinfo_match_RNG pass
14660 10:13:41.061179 arm64_hwcap_sigill_RNG pass
14661 10:13:41.061307 arm64_hwcap_cpuinfo_match_SME pass
14662 10:13:41.061423 arm64_hwcap_sigill_SME pass
14663 10:13:41.061534 arm64_hwcap_cpuinfo_match_SVE pass
14664 10:13:41.061659 arm64_hwcap_sigill_SVE pass
14665 10:13:41.061774 arm64_hwcap_cpuinfo_match_SVE_2 pass
14666 10:13:41.061886 arm64_hwcap_sigill_SVE_2 pass
14667 10:13:41.061997 arm64_hwcap_cpuinfo_match_SVE_AES pass
14668 10:13:41.062107 arm64_hwcap_sigill_SVE_AES pass
14669 10:13:41.062219 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14670 10:13:41.062330 arm64_hwcap_sigill_SVE2_PMULL pass
14671 10:13:41.062443 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14672 10:13:41.062554 arm64_hwcap_sigill_SVE2_BITPERM pass
14673 10:13:41.062667 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14674 10:13:41.062780 arm64_hwcap_sigill_SVE2_SHA3 pass
14675 10:13:41.062890 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14676 10:13:41.063002 arm64_hwcap_sigill_SVE2_SM4 pass
14677 10:13:41.063112 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14678 10:13:41.063224 arm64_hwcap_sigill_SVE2_I8MM pass
14679 10:13:41.063336 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14680 10:13:41.063447 arm64_hwcap_sigill_SVE2_F32MM pass
14681 10:13:41.063559 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14682 10:13:41.064833 arm64_hwcap_sigill_SVE2_F64MM pass
14683 10:13:41.065229 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14684 10:13:41.065382 arm64_hwcap_sigill_SVE2_BF16 pass
14685 10:13:41.065529 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14686 10:13:41.065696 arm64_hwcap_sigill_SVE2_EBF16 skip
14687 10:13:41.065877 arm64_hwcap pass
14688 10:13:41.066025 arm64_ptrace_read_tpidr_one pass
14689 10:13:41.066149 arm64_ptrace_write_tpidr_one pass
14690 10:13:41.066268 arm64_ptrace_verify_tpidr_one pass
14691 10:13:41.066387 arm64_ptrace_count_tpidrs pass
14692 10:13:41.066521 arm64_ptrace_tpidr2_write pass
14693 10:13:41.066669 arm64_ptrace_tpidr2_read pass
14694 10:13:41.066815 arm64_ptrace_write_tpidr_only pass
14695 10:13:41.066993 arm64_ptrace pass
14696 10:13:41.067144 arm64_syscall-abi_getpid_FPSIMD pass
14697 10:13:41.067280 arm64_syscall-abi_getpid_SVE_VL_256 pass
14698 10:13:41.067427 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14699 10:13:41.067574 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14700 10:13:41.067714 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14701 10:13:41.067830 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14702 10:13:41.067979 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14703 10:13:41.068099 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14704 10:13:41.068218 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14705 10:13:41.068340 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14706 10:13:41.068505 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14707 10:13:41.068635 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14708 10:13:41.068790 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14709 10:13:41.068914 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14710 10:13:41.069029 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14711 10:13:41.069141 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14712 10:13:41.072964 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14713 10:13:41.073116 arm64_syscall-abi_getpid_SVE_VL_240 pass
14714 10:13:41.073255 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14715 10:13:41.073375 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14716 10:13:41.073511 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14717 10:13:41.073662 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14718 10:13:41.073804 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14719 10:13:41.073978 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14720 10:13:41.074199 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14721 10:13:41.074360 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14722 10:13:41.074514 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14723 10:13:41.074669 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14724 10:13:41.074815 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14725 10:13:41.074961 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14726 10:13:41.075113 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14727 10:13:41.075260 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14728 10:13:41.075406 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14729 10:13:41.075553 arm64_syscall-abi_getpid_SVE_VL_224 pass
14730 10:13:41.075905 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14731 10:13:41.076063 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14732 10:13:41.076192 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14733 10:13:41.076336 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14734 10:13:41.076527 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14735 10:13:41.080732 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14736 10:13:41.081106 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14737 10:13:41.081264 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14738 10:13:41.081435 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14739 10:13:41.081595 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14740 10:13:41.081799 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14741 10:13:41.081960 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14742 10:13:41.082145 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14743 10:13:41.082320 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14744 10:13:41.082550 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14745 10:13:41.082719 arm64_syscall-abi_getpid_SVE_VL_208 pass
14746 10:13:41.082874 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14747 10:13:41.083045 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14748 10:13:41.083200 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14749 10:13:41.083354 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14750 10:13:41.083532 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14751 10:13:41.083688 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14752 10:13:41.083830 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14753 10:13:41.083993 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14754 10:13:41.084137 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14755 10:13:41.084311 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14756 10:13:41.084454 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14757 10:13:41.084610 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14758 10:13:41.092800 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14759 10:13:41.093280 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14760 10:13:41.093420 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14761 10:13:41.093542 arm64_syscall-abi_getpid_SVE_VL_192 pass
14762 10:13:41.093703 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14763 10:13:41.093829 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14764 10:13:41.093950 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14765 10:13:41.094088 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14766 10:13:41.094214 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14767 10:13:41.094336 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14768 10:13:41.094476 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14769 10:13:41.094624 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14770 10:13:41.094788 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14771 10:13:41.094937 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14772 10:13:41.095105 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14773 10:13:41.095256 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14774 10:13:41.095421 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14775 10:13:41.095574 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14776 10:13:41.095752 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14777 10:13:41.095907 arm64_syscall-abi_getpid_SVE_VL_176 pass
14778 10:13:41.096054 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14779 10:13:41.096231 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14780 10:13:41.096366 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14781 10:13:41.096540 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14782 10:13:41.096709 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14783 10:13:41.100950 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14784 10:13:41.101423 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14785 10:13:41.101524 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14786 10:13:41.101602 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14787 10:13:41.102026 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14788 10:13:41.116108 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14789 10:13:41.116362 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14790 10:13:41.116490 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14791 10:13:41.116605 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14792 10:13:41.116706 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14793 10:13:41.116844 arm64_syscall-abi_getpid_SVE_VL_160 pass
14794 10:13:41.117058 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14795 10:13:41.117225 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14796 10:13:41.117402 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14797 10:13:41.117554 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14798 10:13:41.117757 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14799 10:13:41.117919 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14800 10:13:41.118109 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14801 10:13:41.118272 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14802 10:13:41.118427 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14803 10:13:41.118614 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14804 10:13:41.118777 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14805 10:13:41.118936 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14806 10:13:41.119093 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14807 10:13:41.119281 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14808 10:13:41.119472 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14809 10:13:41.119690 arm64_syscall-abi_getpid_SVE_VL_144 pass
14810 10:13:41.119885 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14811 10:13:41.120087 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14812 10:13:41.120334 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14813 10:13:41.120539 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14814 10:13:41.120728 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14815 10:13:41.120882 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14816 10:13:41.121000 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14817 10:13:41.121110 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14818 10:13:41.121221 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14819 10:13:41.121358 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14820 10:13:41.121476 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14821 10:13:41.124954 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14822 10:13:41.125486 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14823 10:13:41.125680 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14824 10:13:41.125842 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14825 10:13:41.126076 arm64_syscall-abi_getpid_SVE_VL_128 pass
14826 10:13:41.126246 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14827 10:13:41.126430 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14828 10:13:41.126608 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14829 10:13:41.126817 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14830 10:13:41.126986 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14831 10:13:41.127124 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14832 10:13:41.127261 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14833 10:13:41.127394 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14834 10:13:41.127550 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14835 10:13:41.127747 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14836 10:13:41.127904 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14837 10:13:41.128056 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14838 10:13:41.128202 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14839 10:13:41.128345 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14840 10:13:41.128500 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14841 10:13:41.128678 arm64_syscall-abi_getpid_SVE_VL_112 pass
14842 10:13:41.128831 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14843 10:13:41.128958 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14844 10:13:41.129084 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14845 10:13:41.129194 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14846 10:13:41.129318 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14847 10:13:41.132841 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14848 10:13:41.133286 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14849 10:13:41.133474 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14850 10:13:41.133625 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14851 10:13:41.133808 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14852 10:13:41.133938 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14853 10:13:41.134098 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14854 10:13:41.134240 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14855 10:13:41.134382 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14856 10:13:41.134536 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14857 10:13:41.134675 arm64_syscall-abi_getpid_SVE_VL_96 pass
14858 10:13:41.134833 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14859 10:13:41.135030 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14860 10:13:41.135178 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14861 10:13:41.135340 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14862 10:13:41.135503 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14863 10:13:41.135643 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14864 10:13:41.135783 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14865 10:13:41.135930 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14866 10:13:41.136107 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14867 10:13:41.136245 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14868 10:13:41.136381 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14869 10:13:41.136509 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14870 10:13:41.136680 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14871 10:13:41.136826 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14872 10:13:41.136947 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14873 10:13:41.137060 arm64_syscall-abi_getpid_SVE_VL_80 pass
14874 10:13:41.137212 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14875 10:13:41.137341 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14876 10:13:41.137455 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14877 10:13:41.140889 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14878 10:13:41.141066 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14879 10:13:41.141491 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14880 10:13:41.141738 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14881 10:13:41.141906 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14882 10:13:41.142066 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14883 10:13:41.142217 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14884 10:13:41.142410 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14885 10:13:41.142596 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14886 10:13:41.142757 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14887 10:13:41.142913 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14888 10:13:41.143084 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14889 10:13:41.143236 arm64_syscall-abi_getpid_SVE_VL_64 pass
14890 10:13:41.143373 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14891 10:13:41.143559 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14892 10:13:41.143706 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14893 10:13:41.143842 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14894 10:13:41.143996 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14895 10:13:41.144190 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14896 10:13:41.144346 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14897 10:13:41.144513 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14898 10:13:41.144631 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14899 10:13:41.144740 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14900 10:13:41.144879 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14901 10:13:41.144997 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14902 10:13:41.145107 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14903 10:13:41.145216 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14904 10:13:41.145325 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14905 10:13:41.145432 arm64_syscall-abi_getpid_SVE_VL_48 pass
14906 10:13:41.145539 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14907 10:13:41.145657 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14908 10:13:41.148690 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14909 10:13:41.149110 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14910 10:13:41.149290 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14911 10:13:41.149468 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14912 10:13:41.149672 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14913 10:13:41.149857 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14914 10:13:41.150029 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14915 10:13:41.150190 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14916 10:13:41.150340 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14917 10:13:41.150558 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14918 10:13:41.150744 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14919 10:13:41.150889 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14920 10:13:41.151049 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14921 10:13:41.151188 arm64_syscall-abi_getpid_SVE_VL_32 pass
14922 10:13:41.151334 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14923 10:13:41.151481 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14924 10:13:41.151652 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14925 10:13:41.151873 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14926 10:13:41.152054 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14927 10:13:41.152201 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
14928 10:13:41.152360 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
14929 10:13:41.152495 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
14930 10:13:41.152648 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
14931 10:13:41.152794 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
14932 10:13:41.152932 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
14933 10:13:41.153090 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
14934 10:13:41.153225 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
14935 10:13:41.153377 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
14936 10:13:41.153538 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
14937 10:13:41.153777 arm64_syscall-abi_getpid_SVE_VL_16 pass
14938 10:13:41.153940 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
14939 10:13:41.154102 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
14940 10:13:41.165164 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
14941 10:13:41.165668 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
14942 10:13:41.165853 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
14943 10:13:41.165978 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
14944 10:13:41.166114 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
14945 10:13:41.166572 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
14946 10:13:41.166775 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
14947 10:13:41.166942 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
14948 10:13:41.167109 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
14949 10:13:41.167293 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
14950 10:13:41.167691 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
14951 10:13:41.167869 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
14952 10:13:41.168035 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
14953 10:13:41.168189 arm64_syscall-abi_sched_yield_FPSIMD pass
14954 10:13:41.168339 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
14955 10:13:41.168521 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
14956 10:13:41.168690 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
14957 10:13:41.168812 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
14958 10:13:41.168944 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
14959 10:13:41.169071 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
14960 10:13:41.172728 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
14961 10:13:41.173229 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
14962 10:13:41.173465 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
14963 10:13:41.173787 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
14964 10:13:41.173981 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
14965 10:13:41.174232 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
14966 10:13:41.174434 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
14967 10:13:41.174624 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
14968 10:13:41.174834 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
14969 10:13:41.175028 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
14970 10:13:41.175222 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
14971 10:13:41.175420 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
14972 10:13:41.175604 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
14973 10:13:41.175784 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
14974 10:13:41.176016 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
14975 10:13:41.176269 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
14976 10:13:41.176454 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
14977 10:13:41.176642 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
14978 10:13:41.176775 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
14979 10:13:41.176902 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
14980 10:13:41.177026 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
14981 10:13:41.177150 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
14982 10:13:41.177274 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
14983 10:13:41.177399 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
14984 10:13:41.177525 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
14985 10:13:41.177688 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
14986 10:13:41.177924 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
14987 10:13:41.178126 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
14988 10:13:41.178327 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
14989 10:13:41.178571 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
14990 10:13:41.178733 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
14991 10:13:41.178892 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
14992 10:13:41.179049 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
14993 10:13:41.179204 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
14994 10:13:41.180731 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
14995 10:13:41.181308 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
14996 10:13:41.181493 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
14997 10:13:41.181662 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
14998 10:13:41.181864 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
14999 10:13:41.182069 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
15000 10:13:41.182262 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
15001 10:13:41.182445 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
15002 10:13:41.182577 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
15003 10:13:41.182735 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
15004 10:13:41.182898 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
15005 10:13:41.183028 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
15006 10:13:41.183152 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
15007 10:13:41.183271 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
15008 10:13:41.183385 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
15009 10:13:41.183551 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
15010 10:13:41.183743 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
15011 10:13:41.183889 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
15012 10:13:41.184028 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
15013 10:13:41.184168 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
15014 10:13:41.184295 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
15015 10:13:41.184453 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
15016 10:13:41.184619 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
15017 10:13:41.184739 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
15018 10:13:41.184854 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
15019 10:13:41.184966 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
15020 10:13:41.185080 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
15021 10:13:41.185191 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
15022 10:13:41.188664 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
15023 10:13:41.189079 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
15024 10:13:41.189248 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
15025 10:13:41.189395 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
15026 10:13:41.189582 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
15027 10:13:41.189753 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
15028 10:13:41.189905 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
15029 10:13:41.190056 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
15030 10:13:41.190211 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
15031 10:13:41.190387 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
15032 10:13:41.190546 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
15033 10:13:41.190711 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
15034 10:13:41.190855 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
15035 10:13:41.191003 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
15036 10:13:41.191147 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
15037 10:13:41.191285 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
15038 10:13:41.191480 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
15039 10:13:41.191646 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
15040 10:13:41.191788 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
15041 10:13:41.191945 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
15042 10:13:41.192105 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
15043 10:13:41.192260 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
15044 10:13:41.192420 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
15045 10:13:41.192560 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
15046 10:13:41.192677 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
15047 10:13:41.192819 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
15048 10:13:41.192941 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
15049 10:13:41.193057 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
15050 10:13:41.193171 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
15051 10:13:41.193284 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
15052 10:13:41.193397 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
15053 10:13:41.193510 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
15054 10:13:41.193624 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
15055 10:13:41.196627 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
15056 10:13:41.196934 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
15057 10:13:41.197025 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
15058 10:13:41.197135 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
15059 10:13:41.197225 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
15060 10:13:41.197307 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
15061 10:13:41.197584 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
15062 10:13:41.197676 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
15063 10:13:41.197771 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
15064 10:13:41.197871 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
15065 10:13:41.197981 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
15066 10:13:41.198090 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
15067 10:13:41.198196 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
15068 10:13:41.198304 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
15069 10:13:41.198385 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
15070 10:13:41.198650 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
15071 10:13:41.198753 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
15072 10:13:41.198865 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
15073 10:13:41.198984 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
15074 10:13:41.199095 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
15075 10:13:41.199180 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
15076 10:13:41.199494 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
15077 10:13:41.199708 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
15078 10:13:41.199837 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
15079 10:13:41.199973 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
15080 10:13:41.210716 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
15081 10:13:41.211047 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
15082 10:13:41.211151 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
15083 10:13:41.211237 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
15084 10:13:41.211336 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
15085 10:13:41.211435 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
15086 10:13:41.211607 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
15087 10:13:41.211723 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
15088 10:13:41.212025 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
15089 10:13:41.212133 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
15090 10:13:41.212431 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
15091 10:13:41.212533 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
15092 10:13:41.212632 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
15093 10:13:41.212917 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
15094 10:13:41.213008 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
15095 10:13:41.213112 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
15096 10:13:41.213198 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
15097 10:13:41.213298 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
15098 10:13:41.213593 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
15099 10:13:41.213680 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
15100 10:13:41.213771 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
15101 10:13:41.213853 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
15102 10:13:41.213937 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
15103 10:13:41.214020 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
15104 10:13:41.214103 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
15105 10:13:41.214363 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
15106 10:13:41.214445 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
15107 10:13:41.214516 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
15108 10:13:41.214779 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
15109 10:13:41.214848 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
15110 10:13:41.214937 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
15111 10:13:41.215005 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
15112 10:13:41.215090 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
15113 10:13:41.215173 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
15114 10:13:41.215255 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
15115 10:13:41.215504 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
15116 10:13:41.215572 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
15117 10:13:41.215659 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
15118 10:13:41.215742 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
15119 10:13:41.216001 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
15120 10:13:41.216250 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
15121 10:13:41.216318 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
15122 10:13:41.216393 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
15123 10:13:41.216479 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
15124 10:13:41.216580 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
15125 10:13:41.220695 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
15126 10:13:41.221009 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
15127 10:13:41.221129 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
15128 10:13:41.221262 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
15129 10:13:41.221434 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
15130 10:13:41.221555 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
15131 10:13:41.221672 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
15132 10:13:41.221781 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
15133 10:13:41.221925 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
15134 10:13:41.222057 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
15135 10:13:41.222194 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
15136 10:13:41.222363 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
15137 10:13:41.222498 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
15138 10:13:41.222636 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
15139 10:13:41.222775 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
15140 10:13:41.222951 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
15141 10:13:41.223083 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
15142 10:13:41.223219 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
15143 10:13:41.223357 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
15144 10:13:41.223494 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
15145 10:13:41.223632 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
15146 10:13:41.223807 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
15147 10:13:41.223940 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
15148 10:13:41.224077 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
15149 10:13:41.224215 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
15150 10:13:41.224352 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
15151 10:13:41.224490 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
15152 10:13:41.224626 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
15153 10:13:41.224763 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
15154 10:13:41.224934 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
15155 10:13:41.225066 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
15156 10:13:41.225203 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
15157 10:13:41.225341 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
15158 10:13:41.225475 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
15159 10:13:41.225821 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
15160 10:13:41.228647 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
15161 10:13:41.228987 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
15162 10:13:41.229121 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
15163 10:13:41.229264 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
15164 10:13:41.229436 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
15165 10:13:41.229570 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
15166 10:13:41.229753 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
15167 10:13:41.229923 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
15168 10:13:41.230102 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
15169 10:13:41.230238 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
15170 10:13:41.230378 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
15171 10:13:41.230516 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
15172 10:13:41.230653 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15173 10:13:41.230791 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15174 10:13:41.230966 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15175 10:13:41.231099 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15176 10:13:41.231239 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15177 10:13:41.231379 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15178 10:13:41.231516 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15179 10:13:41.231653 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15180 10:13:41.231791 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15181 10:13:41.231933 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15182 10:13:41.232110 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15183 10:13:41.232241 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15184 10:13:41.232380 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15185 10:13:41.232557 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15186 10:13:41.232726 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15187 10:13:41.232866 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15188 10:13:41.233005 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15189 10:13:41.233142 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15190 10:13:41.233279 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15191 10:13:41.233451 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15192 10:13:41.233584 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15193 10:13:41.233735 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15194 10:13:41.234083 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15195 10:13:41.236682 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15196 10:13:41.237070 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15197 10:13:41.237266 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15198 10:13:41.237412 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15199 10:13:41.237591 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15200 10:13:41.237753 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15201 10:13:41.237877 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15202 10:13:41.238001 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15203 10:13:41.238149 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15204 10:13:41.238274 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15205 10:13:41.238429 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15206 10:13:41.238565 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15207 10:13:41.238711 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15208 10:13:41.238841 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15209 10:13:41.238970 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15210 10:13:41.239090 arm64_syscall-abi pass
15211 10:13:41.239209 arm64_tpidr2_default_value pass
15212 10:13:41.239379 arm64_tpidr2_write_read pass
15213 10:13:41.239555 arm64_tpidr2_write_sleep_read pass
15214 10:13:41.239712 arm64_tpidr2_write_fork_read pass
15215 10:13:41.239879 arm64_tpidr2_write_clone_read pass
15216 10:13:41.239995 arm64_tpidr2 pass
15217 10:13:41.256532 + ../../utils/send-to-lava.sh ./output/result.txt
15218 10:13:41.300240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15220 10:13:41.300866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15221 10:13:41.333613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15223 10:13:41.334225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15224 10:13:41.366225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15225 10:13:41.366689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15227 10:13:41.399009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15228 10:13:41.399462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15230 10:13:41.429963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15231 10:13:41.430421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15233 10:13:41.461468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15234 10:13:41.461962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15236 10:13:41.492489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15237 10:13:41.492852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15239 10:13:41.522995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15240 10:13:41.523319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15242 10:13:41.554048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15244 10:13:41.554548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15245 10:13:41.584336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15246 10:13:41.584682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15248 10:13:41.615275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15249 10:13:41.615606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15251 10:13:41.645791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15252 10:13:41.646190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15254 10:13:41.675395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15255 10:13:41.675725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15257 10:13:41.706126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15258 10:13:41.706464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15260 10:13:41.736495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15261 10:13:41.736833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15263 10:13:41.767116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15264 10:13:41.767473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15266 10:13:41.797964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15268 10:13:41.798493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15269 10:13:41.828229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15270 10:13:41.828604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15272 10:13:41.859266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15274 10:13:41.859675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15275 10:13:41.889946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15277 10:13:41.890346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15278 10:13:41.920079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15280 10:13:41.920486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15281 10:13:41.950615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15283 10:13:41.951077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15284 10:13:41.981031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15286 10:13:41.981495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15287 10:13:42.010696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15289 10:13:42.011099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15290 10:13:42.040049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15291 10:13:42.040412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15293 10:13:42.069756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15295 10:13:42.070242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15296 10:13:42.100240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15298 10:13:42.100723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15299 10:13:42.130578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15301 10:13:42.130937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15302 10:13:42.162605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15303 10:13:42.162943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15305 10:13:42.193476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15306 10:13:42.193819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15308 10:13:42.223128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15309 10:13:42.223471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15311 10:13:42.252867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15313 10:13:42.253337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15314 10:13:42.282441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15315 10:13:42.282796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15317 10:13:42.312617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15318 10:13:42.312960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15320 10:13:42.343021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15322 10:13:42.343498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15323 10:13:42.372755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15325 10:13:42.373214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15326 10:13:42.403274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15328 10:13:42.403842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15329 10:13:42.433877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15331 10:13:42.434453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15332 10:13:42.463736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15333 10:13:42.464200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15335 10:13:42.493819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15336 10:13:42.494293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15338 10:13:42.523822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15339 10:13:42.524290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15341 10:13:42.553707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15342 10:13:42.554176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15344 10:13:42.583703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15345 10:13:42.584168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15347 10:13:42.613849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15348 10:13:42.614324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15350 10:13:42.643834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15352 10:13:42.644436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15353 10:13:42.673749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15354 10:13:42.674198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15356 10:13:42.708349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15357 10:13:42.708883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15359 10:13:42.740494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15360 10:13:42.740930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15362 10:13:42.770545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15363 10:13:42.770946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15365 10:13:42.801536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15366 10:13:42.801964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15368 10:13:42.832431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15369 10:13:42.833056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15371 10:13:42.863148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15372 10:13:42.863641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15374 10:13:42.893734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15375 10:13:42.894210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15377 10:13:42.930034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15378 10:13:42.930505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15380 10:13:42.961408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15381 10:13:42.961882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15383 10:13:42.991546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15384 10:13:42.991982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15386 10:13:43.022414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15388 10:13:43.022964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15389 10:13:43.052874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15391 10:13:43.053308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15392 10:13:43.083904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15394 10:13:43.084475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15395 10:13:43.114688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15397 10:13:43.115090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15398 10:13:43.144594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15399 10:13:43.144932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15401 10:13:43.174813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15403 10:13:43.175253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15404 10:13:43.205694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15406 10:13:43.206139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15407 10:13:43.236938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15409 10:13:43.237399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15410 10:13:43.267797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15411 10:13:43.268238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15413 10:13:43.298789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15414 10:13:43.299168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15416 10:13:43.329698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15418 10:13:43.330104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15419 10:13:43.360102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15421 10:13:43.360485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15422 10:13:43.392436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15423 10:13:43.392844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15425 10:13:43.425610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15426 10:13:43.426043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15428 10:13:43.457275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15429 10:13:43.457674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15431 10:13:43.487363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15433 10:13:43.487852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15434 10:13:43.517968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15436 10:13:43.518430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15437 10:13:43.548561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15439 10:13:43.549064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15440 10:13:43.583838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15441 10:13:43.584284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15443 10:13:43.618527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15444 10:13:43.619003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15446 10:13:43.649668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15448 10:13:43.650232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15449 10:13:43.680057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15450 10:13:43.680468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15452 10:13:43.710287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15453 10:13:43.710710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15455 10:13:43.740538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15456 10:13:43.741099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15458 10:13:43.773032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15460 10:13:43.773671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15461 10:13:43.805056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15463 10:13:43.805691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15464 10:13:43.837346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15466 10:13:43.837941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15467 10:13:43.868066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15468 10:13:43.868461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15470 10:13:43.898948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15471 10:13:43.899383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15473 10:13:43.930560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15474 10:13:43.930983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15476 10:13:43.961567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15478 10:13:43.962060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15479 10:13:43.992224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15480 10:13:43.992626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15482 10:13:44.023216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15483 10:13:44.023634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15485 10:13:44.054233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15486 10:13:44.054633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15488 10:13:44.085875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15489 10:13:44.086243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15491 10:13:44.118530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15493 10:13:44.119194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15494 10:13:44.150626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15496 10:13:44.151301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15497 10:13:44.182203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15498 10:13:44.182630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15500 10:13:44.213525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15501 10:13:44.213972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15503 10:13:44.243739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15505 10:13:44.244212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15506 10:13:44.274625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15507 10:13:44.275010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15509 10:13:44.305922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15511 10:13:44.306336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15512 10:13:44.337602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15513 10:13:44.337975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15515 10:13:44.368366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15517 10:13:44.368770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15518 10:13:44.399247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15519 10:13:44.399560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15521 10:13:44.430572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15523 10:13:44.431120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15524 10:13:44.463695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15526 10:13:44.464147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15527 10:13:44.495252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15528 10:13:44.495676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15530 10:13:44.526396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15531 10:13:44.526711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15533 10:13:44.557256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15534 10:13:44.557587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15536 10:13:44.589081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15538 10:13:44.589657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15539 10:13:44.619958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15540 10:13:44.620437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15542 10:13:44.651469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15543 10:13:44.651923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15545 10:13:44.682826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15546 10:13:44.683207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15548 10:13:44.713709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15549 10:13:44.714055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15551 10:13:44.743890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15553 10:13:44.744289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15554 10:13:44.774752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15555 10:13:44.775132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15557 10:13:44.805521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15558 10:13:44.805956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15560 10:13:44.836364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15562 10:13:44.836746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15563 10:13:44.866733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15564 10:13:44.867046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15566 10:13:44.897681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15567 10:13:44.898019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15569 10:13:44.928538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15570 10:13:44.928873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15572 10:13:44.958921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15573 10:13:44.959242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15575 10:13:44.989690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15577 10:13:44.990096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15578 10:13:45.020293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15579 10:13:45.020625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15581 10:13:45.050954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15582 10:13:45.051322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15584 10:13:45.081989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15585 10:13:45.082335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15587 10:13:45.112251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15588 10:13:45.112591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15590 10:13:45.143539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15592 10:13:45.143973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15593 10:13:45.174958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15595 10:13:45.175479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15596 10:13:45.205955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15598 10:13:45.206410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15599 10:13:45.236249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15600 10:13:45.236623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15602 10:13:45.266902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15604 10:13:45.267344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15605 10:13:45.297739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15606 10:13:45.298214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15608 10:13:45.329310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15609 10:13:45.329706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15611 10:13:45.359417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15613 10:13:45.359821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15614 10:13:45.389923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15615 10:13:45.390275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15617 10:13:45.421846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15618 10:13:45.422258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15620 10:13:45.452884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15622 10:13:45.453545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15623 10:13:45.484281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15625 10:13:45.484769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15626 10:13:45.515018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15627 10:13:45.515372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15629 10:13:45.546263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15630 10:13:45.546636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15632 10:13:45.577525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15633 10:13:45.577879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15635 10:13:45.608228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15636 10:13:45.608578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15638 10:13:45.638991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15639 10:13:45.639329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15641 10:13:45.670028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15642 10:13:45.670380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15644 10:13:45.700573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15646 10:13:45.701014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15647 10:13:45.731703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15648 10:13:45.732128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15650 10:13:45.762452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15651 10:13:45.762812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15653 10:13:45.793505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15654 10:13:45.793866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15656 10:13:45.824943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15658 10:13:45.825428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15659 10:13:45.856692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15661 10:13:45.857022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15662 10:13:45.888540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15663 10:13:45.888835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15665 10:13:45.921879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15667 10:13:45.922293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15668 10:13:45.954127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15670 10:13:45.954549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15671 10:13:45.985527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15672 10:13:45.985982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15674 10:13:46.017642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15675 10:13:46.018156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15677 10:13:46.050703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15678 10:13:46.051051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15680 10:13:46.087266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15681 10:13:46.087563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15683 10:13:46.123566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15684 10:13:46.123866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15686 10:13:46.156044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15688 10:13:46.156497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15689 10:13:46.193945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15690 10:13:46.194348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15692 10:13:46.230054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15693 10:13:46.230420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15695 10:13:46.264083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15696 10:13:46.264383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15698 10:13:46.304491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15699 10:13:46.304808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15701 10:13:46.344933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15703 10:13:46.345227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15704 10:13:46.380047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15705 10:13:46.380445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15707 10:13:46.416466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15709 10:13:46.416990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15710 10:13:46.454240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15711 10:13:46.454710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15713 10:13:46.503060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15715 10:13:46.503664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15716 10:13:46.537965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15717 10:13:46.538426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15719 10:13:46.578986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15720 10:13:46.579523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15722 10:13:46.613898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15724 10:13:46.614324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15725 10:13:46.647920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15726 10:13:46.648348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15728 10:13:46.682110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15729 10:13:46.682529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15731 10:13:46.716982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15733 10:13:46.717558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15734 10:13:46.752955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15736 10:13:46.753381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15737 10:13:46.787906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15738 10:13:46.788453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15740 10:13:46.822433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15742 10:13:46.823070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15743 10:13:46.857764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15744 10:13:46.858251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15746 10:13:46.892565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15747 10:13:46.893128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15749 10:13:46.929471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15750 10:13:46.929894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15752 10:13:46.964141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15754 10:13:46.964597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15755 10:13:46.997353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15757 10:13:46.997923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15758 10:13:47.030141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15759 10:13:47.030594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15761 10:13:47.061639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15762 10:13:47.062100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15764 10:13:47.092373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15766 10:13:47.092891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15767 10:13:47.122925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15769 10:13:47.123418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15770 10:13:47.153602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15771 10:13:47.154026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15773 10:13:47.184383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15774 10:13:47.184813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15776 10:13:47.215808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15777 10:13:47.216200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15779 10:13:47.246985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15781 10:13:47.247414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15782 10:13:47.278072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15784 10:13:47.278494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15785 10:13:47.308838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15787 10:13:47.309401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15788 10:13:47.339731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15789 10:13:47.340172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15791 10:13:47.370866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15793 10:13:47.371419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15794 10:13:47.401719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15795 10:13:47.402147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15797 10:13:47.432888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15799 10:13:47.433410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15800 10:13:47.464318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15801 10:13:47.464750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15803 10:13:47.495383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15805 10:13:47.495909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15806 10:13:47.526346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15807 10:13:47.526776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15809 10:13:47.557520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15811 10:13:47.558060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15812 10:13:47.588037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15814 10:13:47.588554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15815 10:13:47.618762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15816 10:13:47.619146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15818 10:13:47.649847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15819 10:13:47.650278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15821 10:13:47.680673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15823 10:13:47.681200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15824 10:13:47.712451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15825 10:13:47.712851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15827 10:13:47.743360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15829 10:13:47.743893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15830 10:13:47.774092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15831 10:13:47.774541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15833 10:13:47.805196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15834 10:13:47.805673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15836 10:13:47.836136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15837 10:13:47.836596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15839 10:13:47.867584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15840 10:13:47.868056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15842 10:13:47.898226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15843 10:13:47.898623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15845 10:13:47.930827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15846 10:13:47.931241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15848 10:13:47.963974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15849 10:13:47.964384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15851 10:13:47.997465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15853 10:13:47.997918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15854 10:13:48.030239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15855 10:13:48.030647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15857 10:13:48.063832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15859 10:13:48.064393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15860 10:13:48.096056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15861 10:13:48.096508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15863 10:13:48.128280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15865 10:13:48.128820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15866 10:13:48.164137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15867 10:13:48.164611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15869 10:13:48.197505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15871 10:13:48.198059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15872 10:13:48.231601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15874 10:13:48.232153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15875 10:13:48.264815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15877 10:13:48.265372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15878 10:13:48.298091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15879 10:13:48.298531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15881 10:13:48.330843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15882 10:13:48.331293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15884 10:13:48.363544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15885 10:13:48.363985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15887 10:13:48.396093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15888 10:13:48.396562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15890 10:13:48.429235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15891 10:13:48.429686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15893 10:13:48.461959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15894 10:13:48.462385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15896 10:13:48.495135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15898 10:13:48.495595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15899 10:13:48.527706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15901 10:13:48.528058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15902 10:13:48.559938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15904 10:13:48.560477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15905 10:13:48.592423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15906 10:13:48.592866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15908 10:13:48.625470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15909 10:13:48.625936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15911 10:13:48.657977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15913 10:13:48.658515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15914 10:13:48.690250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15916 10:13:48.690772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15917 10:13:48.722886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15918 10:13:48.723337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15920 10:13:48.755783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15922 10:13:48.756316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15923 10:13:48.788081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15924 10:13:48.788540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15926 10:13:48.820600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15927 10:13:48.821042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
15929 10:13:48.853414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
15930 10:13:48.853877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
15932 10:13:48.886145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
15933 10:13:48.886565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
15935 10:13:48.918116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
15937 10:13:48.918516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
15938 10:13:48.952157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
15939 10:13:48.952559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
15941 10:13:48.986391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
15943 10:13:48.986730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
15944 10:13:49.020084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
15946 10:13:49.020396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
15947 10:13:49.059909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
15948 10:13:49.060311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
15950 10:13:49.100009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
15951 10:13:49.100395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
15953 10:13:49.142908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
15954 10:13:49.143274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
15956 10:13:49.177889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
15958 10:13:49.178426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
15959 10:13:49.212057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
15960 10:13:49.212543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
15962 10:13:49.244401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
15963 10:13:49.244834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
15965 10:13:49.275944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
15966 10:13:49.276402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
15968 10:13:49.308186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
15969 10:13:49.308614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
15971 10:13:49.339005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
15973 10:13:49.339514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
15974 10:13:49.370120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
15975 10:13:49.370533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
15977 10:13:49.401948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
15978 10:13:49.402352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
15980 10:13:49.432976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
15982 10:13:49.433403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
15983 10:13:49.464354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
15984 10:13:49.464766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
15986 10:13:49.495831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
15987 10:13:49.496272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
15989 10:13:49.526498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
15990 10:13:49.526940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
15992 10:13:49.558598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
15994 10:13:49.559139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
15995 10:13:49.589806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
15997 10:13:49.590239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
15998 10:13:49.620818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
16000 10:13:49.621246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
16001 10:13:49.651929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
16002 10:13:49.652364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
16004 10:13:49.683264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
16005 10:13:49.683706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
16007 10:13:49.713829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
16008 10:13:49.714253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
16010 10:13:49.744556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
16012 10:13:49.745124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
16013 10:13:49.775004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
16014 10:13:49.775363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
16016 10:13:49.806946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
16017 10:13:49.807319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
16019 10:13:49.838028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
16020 10:13:49.838467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
16022 10:13:49.868615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
16023 10:13:49.869046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
16025 10:13:49.899321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
16026 10:13:49.899763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
16028 10:13:49.930181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
16029 10:13:49.930552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
16031 10:13:49.960700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
16033 10:13:49.961173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
16034 10:13:49.991481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
16035 10:13:49.991836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
16037 10:13:50.022680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
16038 10:13:50.023051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
16040 10:13:50.067944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
16041 10:13:50.068314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
16043 10:13:50.100262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
16044 10:13:50.100632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
16046 10:13:50.133301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
16047 10:13:50.133617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
16049 10:13:50.167933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
16051 10:13:50.168381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
16052 10:13:50.201914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
16053 10:13:50.202362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
16055 10:13:50.235540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
16056 10:13:50.235949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
16058 10:13:50.269373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
16059 10:13:50.269785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
16061 10:13:50.304321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
16063 10:13:50.304775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
16064 10:13:50.339931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
16065 10:13:50.340397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
16067 10:13:50.374092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
16069 10:13:50.374648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
16070 10:13:50.407545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
16071 10:13:50.408070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
16073 10:13:50.444101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
16074 10:13:50.444596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
16076 10:13:50.478791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
16078 10:13:50.479428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
16079 10:13:50.512777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
16081 10:13:50.513179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
16082 10:13:50.551450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
16083 10:13:50.551828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
16085 10:13:50.585295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
16086 10:13:50.585671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
16088 10:13:50.621321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
16089 10:13:50.621678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
16091 10:13:50.654962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
16092 10:13:50.655379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
16094 10:13:50.688532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
16095 10:13:50.688979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
16097 10:13:50.722531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
16098 10:13:50.723007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
16100 10:13:50.756347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
16101 10:13:50.756745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
16103 10:13:50.789464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
16105 10:13:50.789955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
16106 10:13:50.822357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
16107 10:13:50.822740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
16109 10:13:50.856131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
16110 10:13:50.856517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
16112 10:13:50.890344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
16113 10:13:50.890715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
16115 10:13:50.926786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
16116 10:13:50.927189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
16118 10:13:50.961008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
16120 10:13:50.961562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
16121 10:13:50.994471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
16122 10:13:50.994856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
16124 10:13:51.028261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
16126 10:13:51.028714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
16127 10:13:51.063161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
16129 10:13:51.063611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
16130 10:13:51.097389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
16132 10:13:51.097872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
16133 10:13:51.131106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
16134 10:13:51.131527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
16136 10:13:51.194826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
16137 10:13:51.195272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
16139 10:13:51.239935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
16140 10:13:51.240427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
16142 10:13:51.274447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
16143 10:13:51.274935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
16145 10:13:51.309366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
16146 10:13:51.309676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
16148 10:13:51.343218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
16149 10:13:51.343659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
16151 10:13:51.376354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
16153 10:13:51.376919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
16154 10:13:51.409908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
16156 10:13:51.410588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
16157 10:13:51.443055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
16158 10:13:51.443513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
16160 10:13:51.476409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
16162 10:13:51.476878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
16163 10:13:51.510980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
16164 10:13:51.511416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
16166 10:13:51.544563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
16167 10:13:51.544990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
16169 10:13:51.579922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
16170 10:13:51.580339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
16172 10:13:51.615114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16173 10:13:51.615659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16175 10:13:51.649287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16176 10:13:51.649681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16178 10:13:51.682518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16179 10:13:51.682994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16181 10:13:51.717544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16182 10:13:51.717963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16184 10:13:51.752232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16185 10:13:51.752766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16187 10:13:51.788563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16189 10:13:51.789031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16190 10:13:51.822856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16191 10:13:51.823272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16193 10:13:51.857052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16195 10:13:51.857515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16196 10:13:51.890740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16197 10:13:51.891206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16199 10:13:51.925819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16201 10:13:51.926259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16202 10:13:51.960440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16203 10:13:51.960846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16205 10:13:51.993999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16206 10:13:51.994417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16208 10:13:52.027806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16210 10:13:52.028371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16211 10:13:52.062471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16212 10:13:52.062865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16214 10:13:52.096391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16216 10:13:52.096915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16217 10:13:52.131174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16219 10:13:52.131693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16220 10:13:52.165769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16221 10:13:52.166155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16223 10:13:52.200000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16225 10:13:52.200499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16226 10:13:52.235669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16227 10:13:52.236088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16229 10:13:52.275434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16230 10:13:52.275833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16232 10:13:52.309835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16233 10:13:52.310150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16235 10:13:52.342367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16236 10:13:52.342727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16238 10:13:52.375169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16240 10:13:52.375734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16241 10:13:52.407359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16242 10:13:52.407772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16244 10:13:52.441382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16245 10:13:52.441795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16247 10:13:52.473579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16248 10:13:52.473998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16250 10:13:52.506805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16251 10:13:52.507216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16253 10:13:52.539245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16255 10:13:52.539687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16256 10:13:52.571798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16257 10:13:52.572256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16259 10:13:52.604271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16261 10:13:52.604828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16262 10:13:52.637712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16263 10:13:52.638201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16265 10:13:52.669603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16267 10:13:52.670056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16268 10:13:52.702019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16269 10:13:52.702490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16271 10:13:52.733936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16273 10:13:52.734562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16274 10:13:52.765916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16276 10:13:52.766524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16277 10:13:52.798080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16278 10:13:52.798448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16280 10:13:52.832967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16282 10:13:52.833502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16283 10:13:52.863951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16284 10:13:52.864312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16286 10:13:52.894513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16288 10:13:52.895029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16289 10:13:52.925946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16291 10:13:52.926352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16292 10:13:52.957683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16293 10:13:52.958018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16295 10:13:52.988279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16296 10:13:52.988646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16298 10:13:53.019172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16300 10:13:53.019738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16301 10:13:53.049966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16302 10:13:53.050412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16304 10:13:53.080549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16305 10:13:53.080978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16307 10:13:53.112520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16308 10:13:53.112967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16310 10:13:53.144313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16312 10:13:53.144759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16313 10:13:53.177713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16314 10:13:53.178087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16316 10:13:53.208103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16317 10:13:53.208479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16319 10:13:53.239551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16320 10:13:53.239942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16322 10:13:53.270103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16324 10:13:53.270586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16325 10:13:53.300535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16326 10:13:53.300895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16328 10:13:53.331055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16329 10:13:53.331444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16331 10:13:53.362219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16332 10:13:53.362579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16334 10:13:53.392492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16335 10:13:53.392789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16337 10:13:53.423338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16338 10:13:53.423680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16340 10:13:53.453897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16341 10:13:53.454217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16343 10:13:53.486847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16344 10:13:53.487307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16346 10:13:53.520234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16347 10:13:53.520640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16349 10:13:53.550824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16351 10:13:53.551286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16352 10:13:53.583729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16354 10:13:53.584407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16355 10:13:53.619327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16356 10:13:53.619747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16358 10:13:53.653992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16360 10:13:53.654639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16361 10:13:53.685680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16362 10:13:53.686135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16364 10:13:53.732275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16365 10:13:53.732758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16367 10:13:53.769864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16368 10:13:53.770339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16370 10:13:53.803069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16372 10:13:53.803642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16373 10:13:53.835701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16375 10:13:53.836242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16376 10:13:53.867439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16377 10:13:53.867928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16379 10:13:53.899906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16380 10:13:53.900343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16382 10:13:53.931579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16383 10:13:53.931977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16385 10:13:53.962927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16386 10:13:53.963379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16388 10:13:53.993768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16389 10:13:53.994261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16391 10:13:54.025448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16393 10:13:54.026030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16394 10:13:54.056303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16396 10:13:54.056776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16397 10:13:54.087100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16399 10:13:54.087564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16400 10:13:54.117431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16401 10:13:54.117882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16403 10:13:54.150538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16405 10:13:54.150927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16406 10:13:54.184540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16408 10:13:54.184945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16409 10:13:54.217936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16410 10:13:54.218442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16412 10:13:54.251310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16414 10:13:54.251868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16415 10:13:54.283551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16416 10:13:54.283968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16418 10:13:54.316235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16419 10:13:54.316657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16421 10:13:54.349005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16423 10:13:54.349512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16424 10:13:54.382159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16425 10:13:54.382491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16427 10:13:54.414613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16429 10:13:54.414969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16430 10:13:54.446536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16431 10:13:54.446871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16433 10:13:54.479671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16434 10:13:54.479970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16436 10:13:54.512841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16438 10:13:54.513231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16439 10:13:54.545740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16440 10:13:54.546063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16442 10:13:54.578142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16443 10:13:54.578456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16445 10:13:54.610206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16446 10:13:54.610599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16448 10:13:54.642971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16449 10:13:54.643257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16451 10:13:54.676430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16452 10:13:54.676888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16454 10:13:54.709804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16455 10:13:54.710247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16457 10:13:54.742815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16458 10:13:54.743228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16460 10:13:54.775740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16462 10:13:54.776198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16463 10:13:54.809542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16465 10:13:54.809999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16466 10:13:54.841687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16467 10:13:54.842069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16469 10:13:54.877935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16470 10:13:54.878343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16472 10:13:54.911909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16473 10:13:54.912315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16475 10:13:54.944731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16477 10:13:54.945201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16478 10:13:54.978516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16479 10:13:54.978925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16481 10:13:55.017888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16482 10:13:55.018340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16484 10:13:55.067589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16485 10:13:55.068085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16487 10:13:55.101925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16489 10:13:55.102725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16490 10:13:55.134401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16491 10:13:55.134849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16493 10:13:55.170248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16495 10:13:55.171012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16496 10:13:55.205558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16497 10:13:55.205958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16499 10:13:55.243883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16501 10:13:55.244295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16502 10:13:55.276122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16503 10:13:55.276610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16505 10:13:55.311559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16506 10:13:55.312148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16508 10:13:55.356154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16509 10:13:55.357148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16511 10:13:55.403350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16512 10:13:55.403739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16514 10:13:55.454576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16515 10:13:55.454958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16517 10:13:55.492182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16519 10:13:55.492654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16520 10:13:55.543855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16521 10:13:55.544340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16523 10:13:55.593688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16524 10:13:55.594234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16526 10:13:55.627127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16527 10:13:55.627592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16529 10:13:55.660157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16530 10:13:55.660545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16532 10:13:55.693921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16533 10:13:55.694335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16535 10:13:55.727213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16537 10:13:55.727675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16538 10:13:55.759890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16539 10:13:55.760303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16541 10:13:55.792902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16543 10:13:55.793570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16544 10:13:55.826630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16546 10:13:55.827244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16547 10:13:55.859973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16548 10:13:55.860469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16550 10:13:55.893901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16552 10:13:55.894569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16553 10:13:55.927661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16554 10:13:55.928083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16556 10:13:55.961034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16558 10:13:55.961673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16559 10:13:55.994055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16561 10:13:55.994647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16562 10:13:56.027578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16563 10:13:56.027940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16565 10:13:56.062861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16567 10:13:56.063260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16568 10:13:56.098123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16569 10:13:56.098520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16571 10:13:56.132905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16573 10:13:56.133221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16574 10:13:56.166558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16575 10:13:56.166905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16577 10:13:56.200237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16578 10:13:56.200610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16580 10:13:56.236359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16581 10:13:56.236718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16583 10:13:56.268817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16585 10:13:56.269117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16586 10:13:56.301673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16587 10:13:56.302050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16589 10:13:56.333866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16590 10:13:56.334256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16592 10:13:56.366272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16593 10:13:56.366757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16595 10:13:56.398727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16597 10:13:56.399395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16598 10:13:56.431014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16599 10:13:56.431463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16601 10:13:56.465594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16602 10:13:56.465981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16604 10:13:56.504032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16605 10:13:56.504422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16607 10:13:56.538354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16608 10:13:56.538813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16610 10:13:56.573808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16611 10:13:56.574263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16613 10:13:56.611291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16614 10:13:56.611768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16616 10:13:56.666703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16617 10:13:56.667180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16619 10:13:56.721561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16620 10:13:56.721982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16622 10:13:56.776404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16623 10:13:56.776971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16625 10:13:56.831516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16626 10:13:56.831980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16628 10:13:56.879180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16629 10:13:56.879600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16631 10:13:56.916864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16633 10:13:56.917584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16634 10:13:56.961135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16636 10:13:56.961735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16637 10:13:57.015393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16638 10:13:57.015821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16640 10:13:57.060775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16642 10:13:57.061201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16643 10:13:57.099226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16644 10:13:57.099783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16646 10:13:57.151668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16647 10:13:57.152114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16649 10:13:57.208263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16650 10:13:57.208679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16652 10:13:57.258098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16653 10:13:57.258471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16655 10:13:57.293281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16656 10:13:57.293622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16658 10:13:57.329592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16659 10:13:57.330010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16661 10:13:57.379392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16662 10:13:57.379816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16664 10:13:57.416170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16666 10:13:57.416596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16667 10:13:57.454662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16669 10:13:57.455136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16670 10:13:57.509451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16671 10:13:57.509849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16673 10:13:57.552551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16674 10:13:57.552962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16676 10:13:57.588232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16678 10:13:57.588669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16679 10:13:57.633708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16681 10:13:57.634166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16682 10:13:57.670153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16684 10:13:57.670624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16685 10:13:57.711843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16686 10:13:57.712260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16688 10:13:57.754749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16689 10:13:57.755293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16691 10:13:57.806054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16692 10:13:57.806471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16694 10:13:57.843187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16695 10:13:57.843713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16697 10:13:57.896102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16699 10:13:57.896600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16700 10:13:57.937848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16702 10:13:57.938314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16703 10:13:57.974459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16705 10:13:57.974927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16706 10:13:58.010647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16707 10:13:58.011074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16709 10:13:58.046469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16710 10:13:58.046876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16712 10:13:58.082431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16713 10:13:58.082867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16715 10:13:58.119114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16716 10:13:58.119526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16718 10:13:58.154009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16720 10:13:58.154582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16721 10:13:58.188445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16723 10:13:58.188977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16724 10:13:58.222130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16725 10:13:58.222661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16727 10:13:58.267031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16728 10:13:58.267580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16730 10:13:58.314526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16731 10:13:58.314969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16733 10:13:58.355049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16734 10:13:58.355483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16736 10:13:58.392075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16737 10:13:58.392502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16739 10:13:58.428649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16741 10:13:58.429120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16742 10:13:58.463069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16744 10:13:58.463540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16745 10:13:58.498709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16746 10:13:58.499126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16748 10:13:58.534178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16749 10:13:58.534599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16751 10:13:58.567400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16752 10:13:58.567885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16754 10:13:58.598852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16756 10:13:58.599437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16757 10:13:58.633512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16759 10:13:58.634174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16760 10:13:58.667048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16761 10:13:58.667464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16763 10:13:58.699914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16765 10:13:58.700567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16766 10:13:58.733085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16768 10:13:58.733545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16769 10:13:58.767256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16770 10:13:58.767648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16772 10:13:58.800935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16774 10:13:58.801389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16775 10:13:58.835874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16776 10:13:58.836344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16778 10:13:58.874316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16779 10:13:58.874801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16781 10:13:58.919243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16782 10:13:58.919679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16784 10:13:58.978292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16785 10:13:58.978681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16787 10:13:59.035084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16788 10:13:59.035516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16790 10:13:59.090918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16792 10:13:59.091391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16793 10:13:59.145716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16794 10:13:59.146147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16796 10:13:59.191693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16797 10:13:59.192115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16799 10:13:59.232742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16801 10:13:59.233151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16802 10:13:59.287728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16803 10:13:59.288138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16805 10:13:59.329022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16807 10:13:59.329571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16808 10:13:59.383609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16809 10:13:59.384116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16811 10:13:59.423406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16812 10:13:59.423772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16814 10:13:59.458643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16815 10:13:59.459008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16817 10:13:59.494141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16818 10:13:59.494545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16820 10:13:59.529378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16821 10:13:59.529863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16823 10:13:59.561772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16824 10:13:59.562113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16826 10:13:59.594130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16827 10:13:59.594486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16829 10:13:59.629574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16830 10:13:59.629897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16832 10:13:59.664815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16834 10:13:59.665406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16835 10:13:59.700962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16837 10:13:59.701427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16838 10:13:59.737581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16839 10:13:59.737986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16841 10:13:59.772799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16843 10:13:59.773229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16844 10:13:59.810863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16845 10:13:59.811276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16847 10:13:59.851696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16848 10:13:59.852072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16850 10:13:59.884518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16851 10:13:59.884922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16853 10:13:59.917223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16855 10:13:59.917795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16856 10:13:59.948947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16858 10:13:59.949489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16859 10:13:59.980385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16861 10:13:59.980965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16862 10:14:00.012006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16863 10:14:00.012468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16865 10:14:00.043106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16867 10:14:00.043653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16868 10:14:00.074604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16869 10:14:00.075014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16871 10:14:00.106304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16872 10:14:00.106734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16874 10:14:00.137809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16875 10:14:00.138211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16877 10:14:00.169719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16878 10:14:00.170124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16880 10:14:00.201574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16881 10:14:00.202056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16883 10:14:00.233634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16884 10:14:00.234112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16886 10:14:00.264507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16887 10:14:00.264977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16889 10:14:00.296451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16890 10:14:00.296902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16892 10:14:00.330348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16894 10:14:00.330902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16895 10:14:00.362499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16897 10:14:00.363080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16898 10:14:00.395291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16899 10:14:00.395742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16901 10:14:00.429556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16903 10:14:00.430045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16904 10:14:00.470825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16905 10:14:00.471198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16907 10:14:00.507739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16908 10:14:00.508188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16910 10:14:00.539920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16911 10:14:00.540372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16913 10:14:00.574999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16914 10:14:00.575418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16916 10:14:00.610322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16917 10:14:00.610682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16919 10:14:00.641938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16920 10:14:00.642322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16922 10:14:00.673546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16923 10:14:00.673941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16925 10:14:00.704973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
16927 10:14:00.705525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16928 10:14:00.736519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
16929 10:14:00.736978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
16931 10:14:00.768515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
16932 10:14:00.768965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
16934 10:14:00.803253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
16935 10:14:00.803705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
16937 10:14:00.856608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
16939 10:14:00.857345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
16940 10:14:00.910951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
16942 10:14:00.911698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
16943 10:14:00.963589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
16944 10:14:00.963966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
16946 10:14:01.018132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
16947 10:14:01.018562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
16949 10:14:01.063821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
16950 10:14:01.064186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
16952 10:14:01.098465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
16953 10:14:01.098864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
16955 10:14:01.135546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
16956 10:14:01.135968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
16958 10:14:01.170790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
16959 10:14:01.171256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
16961 10:14:01.217705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
16962 10:14:01.218098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
16964 10:14:01.254939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
16965 10:14:01.255319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
16967 10:14:01.288895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
16969 10:14:01.289545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
16970 10:14:01.326564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
16971 10:14:01.327069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
16973 10:14:01.363062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
16974 10:14:01.363478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
16976 10:14:01.397607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
16977 10:14:01.398194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
16979 10:14:01.432440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
16980 10:14:01.432943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
16982 10:14:01.468510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
16983 10:14:01.468867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
16985 10:14:01.504213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
16987 10:14:01.504967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
16988 10:14:01.538379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
16989 10:14:01.538793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
16991 10:14:01.572120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
16992 10:14:01.572566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
16994 10:14:01.606500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
16995 10:14:01.606991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
16997 10:14:01.642413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
16998 10:14:01.642754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
17000 10:14:01.694584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
17001 10:14:01.695113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
17003 10:14:01.732360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
17004 10:14:01.732801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
17006 10:14:01.769957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
17007 10:14:01.770479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
17009 10:14:01.811831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
17010 10:14:01.812303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
17012 10:14:01.852081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
17013 10:14:01.852570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
17015 10:14:01.900699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
17017 10:14:01.901072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
17018 10:14:01.936092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
17019 10:14:01.936510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
17021 10:14:01.976061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
17022 10:14:01.976480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
17024 10:14:02.013454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
17025 10:14:02.013881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
17027 10:14:02.055880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
17029 10:14:02.056557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
17030 10:14:02.103907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
17031 10:14:02.104294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
17033 10:14:02.144127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
17034 10:14:02.144556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
17036 10:14:02.187195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
17037 10:14:02.187556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
17039 10:14:02.228857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
17041 10:14:02.229265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
17042 10:14:02.273563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
17043 10:14:02.273949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
17045 10:14:02.310828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
17047 10:14:02.311256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
17048 10:14:02.342402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
17049 10:14:02.342688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
17051 10:14:02.378451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
17053 10:14:02.379178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
17054 10:14:02.414009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
17056 10:14:02.414443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
17057 10:14:02.458559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
17058 10:14:02.459069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
17060 10:14:02.494888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
17062 10:14:02.495328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
17063 10:14:02.530985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
17065 10:14:02.531422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
17066 10:14:02.566335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
17068 10:14:02.567069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
17069 10:14:02.607254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
17070 10:14:02.607644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
17072 10:14:02.647276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
17074 10:14:02.647669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
17075 10:14:02.686535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
17076 10:14:02.686980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
17078 10:14:02.728816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
17080 10:14:02.729461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
17081 10:14:02.773481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
17082 10:14:02.774061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
17084 10:14:02.814870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
17085 10:14:02.815275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
17087 10:14:02.857733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
17089 10:14:02.858475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
17090 10:14:02.896255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
17091 10:14:02.896610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
17093 10:14:02.932272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
17094 10:14:02.932637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
17096 10:14:02.970788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
17097 10:14:02.971235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
17099 10:14:03.007428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
17100 10:14:03.007967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
17102 10:14:03.047087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
17104 10:14:03.047508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
17105 10:14:03.087439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
17106 10:14:03.087844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
17108 10:14:03.128679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
17110 10:14:03.129239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
17111 10:14:03.170142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
17113 10:14:03.170878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
17114 10:14:03.206524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
17115 10:14:03.206947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
17117 10:14:03.242029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
17118 10:14:03.242561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
17120 10:14:03.278910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
17122 10:14:03.279548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
17123 10:14:03.320378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
17125 10:14:03.320799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
17126 10:14:03.364112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
17127 10:14:03.364528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
17129 10:14:03.407010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
17130 10:14:03.407396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
17132 10:14:03.445726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
17133 10:14:03.446197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
17135 10:14:03.483410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
17137 10:14:03.484000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
17138 10:14:03.519056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
17139 10:14:03.519463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
17141 10:14:03.560590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
17142 10:14:03.561060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
17144 10:14:03.602383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
17145 10:14:03.602811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
17147 10:14:03.644690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
17149 10:14:03.645159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
17150 10:14:03.695983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
17151 10:14:03.696331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
17153 10:14:03.740844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
17155 10:14:03.741463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
17156 10:14:03.783290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
17158 10:14:03.783752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
17159 10:14:03.820277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
17160 10:14:03.820640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
17162 10:14:03.855781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
17163 10:14:03.856323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
17165 10:14:03.891876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
17167 10:14:03.892417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
17168 10:14:03.930326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
17169 10:14:03.930787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
17171 10:14:03.965369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
17172 10:14:03.965803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17174 10:14:03.997934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17175 10:14:03.998371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17177 10:14:04.031790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17178 10:14:04.032226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17180 10:14:04.065320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17181 10:14:04.065738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17183 10:14:04.101353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17185 10:14:04.101818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17186 10:14:04.138768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17187 10:14:04.139239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17189 10:14:04.179805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17190 10:14:04.180355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17192 10:14:04.219737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17193 10:14:04.220173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17195 10:14:04.258560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17197 10:14:04.258935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17198 10:14:04.304291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17199 10:14:04.304678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17201 10:14:04.354926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17203 10:14:04.355361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17204 10:14:04.393966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17205 10:14:04.394501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17207 10:14:04.435927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17209 10:14:04.436367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17210 10:14:04.481946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17211 10:14:04.482379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17213 10:14:04.517744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17214 10:14:04.518305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17216 10:14:04.561914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17217 10:14:04.562350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17219 10:14:04.597686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17220 10:14:04.598076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17222 10:14:04.633401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17223 10:14:04.633908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17225 10:14:04.670570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17227 10:14:04.671045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17228 10:14:04.712435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17229 10:14:04.712958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17231 10:14:04.755620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17233 10:14:04.756024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17234 10:14:04.790282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17236 10:14:04.790742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17237 10:14:04.825826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17238 10:14:04.826249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17240 10:14:04.860130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17242 10:14:04.860594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17243 10:14:04.894146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17244 10:14:04.894591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17246 10:14:04.929010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17248 10:14:04.929463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17249 10:14:04.966066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17250 10:14:04.966487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17252 10:14:05.002959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17253 10:14:05.003377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17255 10:14:05.038294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17257 10:14:05.038956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17258 10:14:05.073796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17259 10:14:05.074291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17261 10:14:05.108068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17262 10:14:05.108546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17264 10:14:05.146416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17265 10:14:05.146916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17267 10:14:05.180911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17269 10:14:05.181537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17270 10:14:05.215857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17271 10:14:05.216315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17273 10:14:05.256076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17274 10:14:05.256622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17276 10:14:05.294131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17278 10:14:05.294499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17279 10:14:05.329147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17280 10:14:05.329629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17282 10:14:05.368397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17284 10:14:05.369227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17285 10:14:05.410884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17286 10:14:05.411300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17288 10:14:05.448834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17290 10:14:05.449273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17291 10:14:05.489433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17292 10:14:05.489825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17294 10:14:05.527433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17296 10:14:05.527784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17297 10:14:05.570732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17299 10:14:05.571036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17300 10:14:05.611961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17301 10:14:05.612282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17303 10:14:05.649339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17304 10:14:05.649677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17306 10:14:05.689763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17308 10:14:05.690197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17309 10:14:05.730063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17310 10:14:05.730533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17312 10:14:05.772908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17314 10:14:05.773247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17315 10:14:05.812330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17316 10:14:05.812667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17318 10:14:05.854382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17319 10:14:05.854749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17321 10:14:05.895036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17322 10:14:05.895329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17324 10:14:05.931383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17325 10:14:05.931887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17327 10:14:05.968349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17328 10:14:05.968814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17330 10:14:06.009914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17331 10:14:06.010269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17333 10:14:06.048147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17335 10:14:06.048592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17336 10:14:06.086511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17337 10:14:06.086882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17339 10:14:06.122276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17340 10:14:06.122694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17342 10:14:06.159205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17343 10:14:06.159653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17345 10:14:06.196390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17346 10:14:06.196793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17348 10:14:06.231480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17349 10:14:06.231914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17351 10:14:06.278517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17352 10:14:06.278901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17354 10:14:06.318168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17355 10:14:06.318596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17357 10:14:06.371054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17358 10:14:06.371420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17360 10:14:06.411355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17361 10:14:06.411841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17363 10:14:06.457403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17365 10:14:06.458020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17366 10:14:06.494968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17368 10:14:06.495577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17369 10:14:06.533826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17370 10:14:06.534175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17372 10:14:06.573936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17374 10:14:06.574409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17375 10:14:06.608861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17377 10:14:06.609514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17378 10:14:06.644205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17380 10:14:06.644854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17381 10:14:06.679777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17382 10:14:06.680181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17384 10:14:06.718529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17385 10:14:06.719027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17387 10:14:06.763285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17388 10:14:06.763704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17390 10:14:06.798490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17391 10:14:06.798870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17393 10:14:06.833375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17395 10:14:06.833799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17396 10:14:06.868367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17397 10:14:06.868801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17399 10:14:06.908305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17401 10:14:06.908727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17402 10:14:06.950310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17404 10:14:06.950723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17405 10:14:06.985332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17406 10:14:06.985873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17408 10:14:07.024502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17409 10:14:07.025004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17411 10:14:07.064433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17412 10:14:07.064894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17414 10:14:07.105858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17416 10:14:07.106323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17417 10:14:07.147516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17418 10:14:07.148059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17420 10:14:07.186963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17422 10:14:07.187529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17423 10:14:07.223349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17424 10:14:07.223833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17426 10:14:07.259450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17427 10:14:07.259935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17429 10:14:07.295346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17430 10:14:07.295822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17432 10:14:07.328910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17434 10:14:07.329500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17435 10:14:07.367716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17436 10:14:07.368152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17438 10:14:07.403474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17439 10:14:07.403932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17441 10:14:07.444403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17442 10:14:07.444872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17444 10:14:07.483570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17445 10:14:07.484123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17447 10:14:07.523166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17449 10:14:07.523726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17450 10:14:07.559268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17451 10:14:07.559808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17453 10:14:07.594765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17454 10:14:07.595236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17456 10:14:07.630369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17458 10:14:07.631128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17459 10:14:07.666674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17461 10:14:07.667293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17462 10:14:07.701922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17463 10:14:07.702368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17465 10:14:07.737020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17467 10:14:07.737478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17468 10:14:07.772051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17470 10:14:07.772510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17471 10:14:07.810592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17473 10:14:07.811046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17474 10:14:07.848668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17475 10:14:07.849055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17477 10:14:07.904078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17478 10:14:07.904480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17480 10:14:07.941704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17481 10:14:07.942080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17483 10:14:07.986418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17484 10:14:07.986809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17486 10:14:08.023756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17487 10:14:08.024166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17489 10:14:08.078094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17491 10:14:08.078571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17492 10:14:08.119572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17493 10:14:08.119983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17495 10:14:08.156961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17497 10:14:08.157608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17498 10:14:08.199469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17499 10:14:08.199875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17501 10:14:08.245428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17503 10:14:08.246191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17504 10:14:08.280088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17505 10:14:08.280547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17507 10:14:08.335892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17508 10:14:08.336333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17510 10:14:08.375062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17511 10:14:08.375540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17513 10:14:08.411271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17514 10:14:08.411827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17516 10:14:08.446662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17517 10:14:08.447148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17519 10:14:08.482675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17521 10:14:08.483338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17522 10:14:08.525839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17524 10:14:08.526297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17525 10:14:08.568483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17526 10:14:08.568954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17528 10:14:08.617677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17529 10:14:08.618105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17531 10:14:08.657807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17532 10:14:08.658178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17534 10:14:08.693703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17535 10:14:08.694096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17537 10:14:08.738794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17538 10:14:08.739229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17540 10:14:08.781618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17542 10:14:08.782089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17543 10:14:08.819068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17544 10:14:08.819504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17546 10:14:08.855073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17547 10:14:08.855525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17549 10:14:08.889818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17551 10:14:08.890487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17552 10:14:08.922478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17553 10:14:08.922964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17555 10:14:08.959803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17556 10:14:08.960308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17558 10:14:08.996217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17559 10:14:08.996706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17561 10:14:09.033633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17563 10:14:09.034432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17564 10:14:09.071168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17565 10:14:09.071549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17567 10:14:09.114898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17568 10:14:09.115371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17570 10:14:09.152694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17571 10:14:09.153173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17573 10:14:09.190442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17575 10:14:09.191016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17576 10:14:09.225270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17577 10:14:09.225747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17579 10:14:09.275679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17581 10:14:09.276320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17582 10:14:09.309543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17584 10:14:09.310006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17585 10:14:09.342959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17586 10:14:09.343524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17588 10:14:09.377462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17590 10:14:09.377903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17591 10:14:09.411534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17592 10:14:09.411988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17594 10:14:09.447738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17595 10:14:09.448149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17597 10:14:09.482800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17598 10:14:09.483245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17600 10:14:09.518838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17602 10:14:09.519489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17603 10:14:09.558729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17604 10:14:09.559289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17606 10:14:09.601657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17608 10:14:09.602115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17609 10:14:09.651601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17610 10:14:09.652073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17612 10:14:09.688096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17613 10:14:09.688529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17615 10:14:09.722018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17616 10:14:09.722466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17618 10:14:09.756989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17620 10:14:09.757447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17621 10:14:09.792286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17622 10:14:09.792734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17624 10:14:09.826138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17626 10:14:09.826505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17627 10:14:09.859548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17628 10:14:09.860101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17630 10:14:09.893114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17631 10:14:09.893586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17633 10:14:09.926169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17634 10:14:09.926634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17636 10:14:09.958370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17637 10:14:09.958873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17639 10:14:09.990467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17640 10:14:09.990919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17642 10:14:10.023738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17644 10:14:10.024194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17645 10:14:10.058194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17647 10:14:10.058644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17648 10:14:10.091190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17649 10:14:10.091604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17651 10:14:10.124484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17653 10:14:10.124941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17654 10:14:10.157600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17655 10:14:10.158101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17657 10:14:10.190523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17658 10:14:10.190997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17660 10:14:10.223840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17661 10:14:10.224312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17663 10:14:10.256443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17664 10:14:10.256922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17666 10:14:10.296221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17668 10:14:10.296817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17669 10:14:10.328159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17670 10:14:10.328637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17672 10:14:10.359962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17674 10:14:10.360419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17675 10:14:10.395040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17676 10:14:10.395472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17678 10:14:10.429277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17680 10:14:10.429724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17681 10:14:10.464259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17682 10:14:10.464695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17684 10:14:10.515237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17685 10:14:10.515653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17687 10:14:10.557849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17689 10:14:10.558590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17690 10:14:10.594067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17691 10:14:10.594568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17693 10:14:10.628704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17694 10:14:10.629186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17696 10:14:10.663697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17698 10:14:10.664440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17699 10:14:10.698773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17700 10:14:10.699214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17702 10:14:10.733928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17704 10:14:10.734402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17705 10:14:10.768705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17707 10:14:10.769178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17708 10:14:10.804979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17710 10:14:10.805438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17711 10:14:10.843845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17713 10:14:10.844306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17714 10:14:10.882873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17715 10:14:10.883383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17717 10:14:10.921677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17718 10:14:10.922060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17720 10:14:10.956561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17721 10:14:10.956968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17723 10:14:10.991341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17725 10:14:10.991775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17726 10:14:11.030897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17728 10:14:11.031422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17729 10:14:11.067141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17731 10:14:11.067545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17732 10:14:11.103302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17733 10:14:11.103850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17735 10:14:11.145981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17737 10:14:11.146369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17738 10:14:11.190943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17740 10:14:11.191541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17741 10:14:11.231083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17742 10:14:11.231502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17744 10:14:11.269427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17745 10:14:11.269855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17747 10:14:11.306414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17749 10:14:11.306872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17750 10:14:11.346144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17751 10:14:11.346587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17753 10:14:11.384995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17755 10:14:11.385501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17756 10:14:11.425625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17757 10:14:11.426113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17759 10:14:11.462106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17760 10:14:11.462592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17762 10:14:11.496450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17763 10:14:11.496927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17765 10:14:11.530128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17767 10:14:11.530571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17768 10:14:11.562956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17769 10:14:11.563498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17771 10:14:11.596022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17773 10:14:11.596434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17774 10:14:11.628425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17776 10:14:11.628790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17777 10:14:11.660177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17778 10:14:11.660661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17780 10:14:11.692555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17781 10:14:11.693027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17783 10:14:11.725982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17785 10:14:11.726533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17786 10:14:11.758321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17787 10:14:11.758773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17789 10:14:11.792259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17790 10:14:11.792772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17792 10:14:11.826796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17793 10:14:11.827337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17795 10:14:11.862185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17797 10:14:11.862629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17798 10:14:11.898069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17800 10:14:11.898536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17801 10:14:11.937136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17803 10:14:11.937815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17804 10:14:11.971841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17805 10:14:11.972383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17807 10:14:12.007226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17808 10:14:12.007672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17810 10:14:12.043094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17811 10:14:12.043630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17813 10:14:12.080754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17815 10:14:12.081367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17816 10:14:12.123950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17817 10:14:12.124366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17819 10:14:12.167706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17821 10:14:12.168168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17822 10:14:12.210086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17824 10:14:12.210759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17825 10:14:12.250492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17827 10:14:12.251117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17828 10:14:12.290752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17830 10:14:12.291396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17831 10:14:12.332670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17833 10:14:12.333398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17834 10:14:12.373896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17835 10:14:12.374317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17837 10:14:12.410046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17838 10:14:12.410487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17840 10:14:12.446497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17841 10:14:12.446924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17843 10:14:12.482896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17845 10:14:12.483351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17846 10:14:12.517841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17847 10:14:12.518281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17849 10:14:12.552219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17850 10:14:12.552604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17852 10:14:12.595433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17853 10:14:12.595905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17855 10:14:12.638242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17856 10:14:12.638670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17858 10:14:12.670491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17859 10:14:12.670923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17861 10:14:12.702971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17863 10:14:12.703411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17864 10:14:12.734747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17865 10:14:12.735237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17867 10:14:12.767795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17869 10:14:12.768426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17870 10:14:12.800985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17872 10:14:12.801666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17873 10:14:12.835929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17874 10:14:12.836358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17876 10:14:12.871363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17877 10:14:12.871778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17879 10:14:12.907645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17880 10:14:12.908155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17882 10:14:12.943974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17883 10:14:12.944461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17885 10:14:12.979440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17886 10:14:12.979920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17888 10:14:13.015367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17890 10:14:13.016018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17891 10:14:13.051323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17892 10:14:13.051764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17894 10:14:13.087271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17895 10:14:13.087675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17897 10:14:13.123557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17899 10:14:13.123965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17900 10:14:13.160218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17902 10:14:13.160703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17903 10:14:13.197614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17905 10:14:13.198401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17906 10:14:13.246431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17908 10:14:13.247078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17909 10:14:13.293351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17910 10:14:13.293837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17912 10:14:13.330458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17914 10:14:13.330935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17915 10:14:13.365741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17916 10:14:13.366226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17918 10:14:13.409789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17919 10:14:13.410247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17921 10:14:13.446329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17922 10:14:13.446795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17924 10:14:13.482525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17925 10:14:13.482986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17927 10:14:13.518993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
17929 10:14:13.519581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
17930 10:14:13.554986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
17931 10:14:13.555549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
17933 10:14:13.590398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
17934 10:14:13.590942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
17936 10:14:13.631130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
17937 10:14:13.631546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
17939 10:14:13.668447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
17940 10:14:13.668903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
17942 10:14:13.707553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
17944 10:14:13.708013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
17945 10:14:13.755830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
17946 10:14:13.756444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
17948 10:14:13.804284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
17949 10:14:13.804694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
17951 10:14:13.845113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
17952 10:14:13.845600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
17954 10:14:13.878432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
17955 10:14:13.878953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
17957 10:14:13.913132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
17959 10:14:13.913737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
17960 10:14:13.950813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
17961 10:14:13.951259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
17963 10:14:13.995625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
17964 10:14:13.996188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
17966 10:14:14.035885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
17967 10:14:14.036336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
17969 10:14:14.079593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
17970 10:14:14.080151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
17972 10:14:14.113977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
17974 10:14:14.114444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
17975 10:14:14.159665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
17976 10:14:14.160089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
17978 10:14:14.193691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
17980 10:14:14.194166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
17981 10:14:14.230678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
17982 10:14:14.231122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
17984 10:14:14.272145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
17985 10:14:14.272528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
17987 10:14:14.311717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
17988 10:14:14.312224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
17990 10:14:14.350315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
17991 10:14:14.350688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
17993 10:14:14.388295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
17994 10:14:14.388752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
17996 10:14:14.431182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
17997 10:14:14.431614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
17999 10:14:14.467529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
18001 10:14:14.468190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
18002 10:14:14.503363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
18003 10:14:14.503778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
18005 10:14:14.539568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
18006 10:14:14.540000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
18008 10:14:14.575127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
18009 10:14:14.575554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
18011 10:14:14.612068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
18013 10:14:14.612542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
18014 10:14:14.647898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
18016 10:14:14.648491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
18017 10:14:14.679854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
18018 10:14:14.680270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
18020 10:14:14.711488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
18021 10:14:14.711945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
18023 10:14:14.745728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
18024 10:14:14.746244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
18026 10:14:14.780516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
18027 10:14:14.781014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
18029 10:14:14.813964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
18030 10:14:14.814417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
18032 10:14:14.846489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
18033 10:14:14.846901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
18035 10:14:14.878403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
18036 10:14:14.878872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
18038 10:14:14.921672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
18039 10:14:14.922127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
18041 10:14:14.955413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
18042 10:14:14.955881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
18044 10:14:14.989293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
18046 10:14:14.989861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
18047 10:14:15.022479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
18049 10:14:15.022941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
18050 10:14:15.056463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
18051 10:14:15.056934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
18053 10:14:15.091762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
18055 10:14:15.092431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
18056 10:14:15.125329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
18057 10:14:15.125841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
18059 10:14:15.159212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
18060 10:14:15.159660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
18062 10:14:15.194124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
18063 10:14:15.194599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
18065 10:14:15.229040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
18067 10:14:15.229610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
18068 10:14:15.263546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
18070 10:14:15.264106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
18071 10:14:15.296892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
18073 10:14:15.297363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
18074 10:14:15.331791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
18075 10:14:15.332205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
18077 10:14:15.368970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
18079 10:14:15.369428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
18080 10:14:15.405278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
18081 10:14:15.405769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
18083 10:14:15.439552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
18084 10:14:15.439973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
18086 10:14:15.472088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
18087 10:14:15.472499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
18089 10:14:15.507895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
18091 10:14:15.508568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
18092 10:14:15.555988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
18093 10:14:15.556453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
18095 10:14:15.594107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
18096 10:14:15.594505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
18098 10:14:15.628136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
18100 10:14:15.628676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
18101 10:14:15.662618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
18102 10:14:15.663059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
18104 10:14:15.699064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
18105 10:14:15.699560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
18107 10:14:15.743229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
18108 10:14:15.743703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
18110 10:14:15.780180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
18111 10:14:15.780632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
18113 10:14:15.814776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
18114 10:14:15.815202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
18116 10:14:15.846789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
18118 10:14:15.847245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
18119 10:14:15.877898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
18121 10:14:15.878473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
18122 10:14:15.920124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
18124 10:14:15.920681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
18125 10:14:15.953195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
18126 10:14:15.953680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
18128 10:14:15.985973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
18129 10:14:15.986426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
18131 10:14:16.019310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
18133 10:14:16.019780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
18134 10:14:16.052039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
18136 10:14:16.052593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
18137 10:14:16.085422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
18139 10:14:16.085899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
18140 10:14:16.117152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
18141 10:14:16.117594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
18143 10:14:16.148126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
18144 10:14:16.148568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
18146 10:14:16.180373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
18148 10:14:16.180839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
18149 10:14:16.213684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
18150 10:14:16.214158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
18152 10:14:16.246023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
18154 10:14:16.246640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
18155 10:14:16.278060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
18157 10:14:16.278519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
18158 10:14:16.310113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
18159 10:14:16.310640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
18161 10:14:16.342091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
18162 10:14:16.342635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
18164 10:14:16.374216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
18165 10:14:16.374775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
18167 10:14:16.407873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
18168 10:14:16.408384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
18170 10:14:16.440594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18171 10:14:16.441080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
18173 10:14:16.476324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18174 10:14:16.476815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18176 10:14:16.514212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18177 10:14:16.514744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18179 10:14:16.567444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18181 10:14:16.568015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18182 10:14:16.620139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18184 10:14:16.620742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18185 10:14:16.655087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18186 10:14:16.655505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18188 10:14:16.703339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18189 10:14:16.703770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18191 10:14:16.736289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18192 10:14:16.736731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18194 10:14:16.770666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18196 10:14:16.771222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18197 10:14:16.804858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18199 10:14:16.805453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18200 10:14:16.839076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18202 10:14:16.839512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18203 10:14:16.871853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18204 10:14:16.872316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18206 10:14:16.905712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18208 10:14:16.906281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18209 10:14:16.943072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18210 10:14:16.943531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18212 10:14:16.978051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18213 10:14:16.978523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18215 10:14:17.015344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18217 10:14:17.015782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18218 10:14:17.050061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18219 10:14:17.050460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18221 10:14:17.090235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18222 10:14:17.090524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18224 10:14:17.122994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18225 10:14:17.123398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18227 10:14:17.157337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18228 10:14:17.157778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18230 10:14:17.190131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18231 10:14:17.190650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18233 10:14:17.222641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18235 10:14:17.223209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18236 10:14:17.264920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18238 10:14:17.265478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18239 10:14:17.298112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18240 10:14:17.298584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18242 10:14:17.341270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18243 10:14:17.341769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18245 10:14:17.374030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18246 10:14:17.374438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18248 10:14:17.406830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18249 10:14:17.407353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18251 10:14:17.441720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18252 10:14:17.442141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18254 10:14:17.474044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18255 10:14:17.474419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18257 10:14:17.517359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18258 10:14:17.517734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18260 10:14:17.550233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18261 10:14:17.550710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18263 10:14:17.590523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18264 10:14:17.591013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18266 10:14:17.632244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18267 10:14:17.632660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18269 10:14:17.667187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18271 10:14:17.667657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18272 10:14:17.702067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18273 10:14:17.702442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18275 10:14:17.734624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18276 10:14:17.735118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18278 10:14:17.777517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18279 10:14:17.778091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18281 10:14:17.812554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18282 10:14:17.812955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18284 10:14:17.847544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18285 10:14:17.847956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18287 10:14:17.883082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18288 10:14:17.883441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18290 10:14:17.918017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18291 10:14:17.918449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18293 10:14:17.952559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18294 10:14:17.953003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18296 10:14:17.986775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18297 10:14:17.987214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18299 10:14:18.022231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18301 10:14:18.022755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18302 10:14:18.058509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18304 10:14:18.058899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18305 10:14:18.095311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18307 10:14:18.095698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18308 10:14:18.132391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18309 10:14:18.132762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18311 10:14:18.168310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18312 10:14:18.168720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18314 10:14:18.204133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18315 10:14:18.204589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18317 10:14:18.235665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18319 10:14:18.236117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18320 10:14:18.266889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18321 10:14:18.267305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18323 10:14:18.298795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18325 10:14:18.299522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18326 10:14:18.329728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18327 10:14:18.330225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18329 10:14:18.360679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18331 10:14:18.361095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18332 10:14:18.392223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18333 10:14:18.392658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18335 10:14:18.424790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18337 10:14:18.425252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18338 10:14:18.456135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18340 10:14:18.456738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18341 10:14:18.487489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18342 10:14:18.487906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18344 10:14:18.519231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18346 10:14:18.519871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18347 10:14:18.550699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18349 10:14:18.551134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18350 10:14:18.582229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18352 10:14:18.582840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18353 10:14:18.614275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18355 10:14:18.614900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18356 10:14:18.646632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18358 10:14:18.647072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18359 10:14:18.677707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18361 10:14:18.678146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18362 10:14:18.709180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18363 10:14:18.709591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18365 10:14:18.740425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18366 10:14:18.740890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18368 10:14:18.772176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18369 10:14:18.772637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18371 10:14:18.804255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18372 10:14:18.804801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18374 10:14:18.837507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18376 10:14:18.838130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18377 10:14:18.869866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18379 10:14:18.870420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18380 10:14:18.907973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18381 10:14:18.908422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18383 10:14:18.947771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18384 10:14:18.948177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18386 10:14:18.979876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18387 10:14:18.980350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18389 10:14:19.011712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18390 10:14:19.012199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18392 10:14:19.044632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18393 10:14:19.045203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18395 10:14:19.079615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18396 10:14:19.080010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18398 10:14:19.117900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18399 10:14:19.118317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18401 10:14:19.155611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18402 10:14:19.156133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18404 10:14:19.193512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18405 10:14:19.193962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18407 10:14:19.231096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18409 10:14:19.231666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18410 10:14:19.267880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18412 10:14:19.268342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18413 10:14:19.304715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18415 10:14:19.305460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18416 10:14:19.343108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18417 10:14:19.343538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18419 10:14:19.382365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18420 10:14:19.382780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18422 10:14:19.416019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18423 10:14:19.416467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18425 10:14:19.448414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18426 10:14:19.448863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18428 10:14:19.481437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18429 10:14:19.482001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18431 10:14:19.517428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18432 10:14:19.517848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18434 10:14:19.553474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18436 10:14:19.554110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18437 10:14:19.587967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18439 10:14:19.588549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18440 10:14:19.622648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18442 10:14:19.623109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18443 10:14:19.658604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18444 10:14:19.659047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18446 10:14:19.694456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18448 10:14:19.694871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18449 10:14:19.732003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18451 10:14:19.732470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18452 10:14:19.768623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18453 10:14:19.769165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18455 10:14:19.802453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18456 10:14:19.802888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18458 10:14:19.837672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18459 10:14:19.838080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18461 10:14:19.875351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18463 10:14:19.875801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18464 10:14:19.910445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18465 10:14:19.910857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18467 10:14:19.947423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18468 10:14:19.947922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18470 10:14:19.982462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18471 10:14:19.982902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18473 10:14:20.018167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18474 10:14:20.018594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18476 10:14:20.054355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18478 10:14:20.054958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18479 10:14:20.089316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18481 10:14:20.089895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18482 10:14:20.123851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18483 10:14:20.124328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18485 10:14:20.159353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18486 10:14:20.159776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18488 10:14:20.193337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18490 10:14:20.193811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18491 10:14:20.226687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18492 10:14:20.227184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18494 10:14:20.260551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18495 10:14:20.261029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18497 10:14:20.294472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18498 10:14:20.294906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18500 10:14:20.328486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18502 10:14:20.328955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18503 10:14:20.362710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18505 10:14:20.363080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18506 10:14:20.396204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18507 10:14:20.396729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18509 10:14:20.430839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18510 10:14:20.431252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18512 10:14:20.465537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18513 10:14:20.465958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18515 10:14:20.501432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18517 10:14:20.502037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18518 10:14:20.537749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18519 10:14:20.538254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18521 10:14:20.575030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18523 10:14:20.575479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18524 10:14:20.611385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18526 10:14:20.611983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18527 10:14:20.646611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18528 10:14:20.648163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18530 10:14:20.682170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18531 10:14:20.682581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18533 10:14:20.716420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18534 10:14:20.716908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18536 10:14:20.751391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18538 10:14:20.752029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18539 10:14:20.787201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18540 10:14:20.787665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18542 10:14:20.822193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18543 10:14:20.822626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18545 10:14:20.858132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18547 10:14:20.858720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18548 10:14:20.894117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18550 10:14:20.894622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18551 10:14:20.927122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18552 10:14:20.927664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18554 10:14:20.960837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18556 10:14:20.961418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18557 10:14:20.995396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18558 10:14:20.995871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18560 10:14:21.030062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18562 10:14:21.030508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18563 10:14:21.067957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18565 10:14:21.068459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18566 10:14:21.107063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18567 10:14:21.107470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18569 10:14:21.150309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18570 10:14:21.150693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18572 10:14:21.185926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18573 10:14:21.186317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18575 10:14:21.220573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18576 10:14:21.221049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18578 10:14:21.256938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18580 10:14:21.257409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18581 10:14:21.294353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18583 10:14:21.294804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18584 10:14:21.330108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18585 10:14:21.330549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18587 10:14:21.365857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18588 10:14:21.366401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18590 10:14:21.400220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18591 10:14:21.400707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18593 10:14:21.433780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18595 10:14:21.434326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18596 10:14:21.467962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18598 10:14:21.468588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18599 10:14:21.504208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18601 10:14:21.504946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18602 10:14:21.539867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18603 10:14:21.540318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18605 10:14:21.580337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18606 10:14:21.580762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18608 10:14:21.617300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18609 10:14:21.617679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18611 10:14:21.653521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18613 10:14:21.653978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18614 10:14:21.687552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18616 10:14:21.688196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18617 10:14:21.722061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18619 10:14:21.722735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18620 10:14:21.763797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18621 10:14:21.764281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18623 10:14:21.811972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18624 10:14:21.812456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18626 10:14:21.846767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18627 10:14:21.847236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18629 10:14:21.895447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18631 10:14:21.895918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18632 10:14:21.934157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18633 10:14:21.934584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18635 10:14:21.971520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18636 10:14:21.971991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18638 10:14:22.007477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18639 10:14:22.007981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18641 10:14:22.041378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18642 10:14:22.041814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18644 10:14:22.075003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18645 10:14:22.075486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18647 10:14:22.106164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18649 10:14:22.106617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18650 10:14:22.138138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18651 10:14:22.138483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18653 10:14:22.172702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18655 10:14:22.173254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18656 10:14:22.205845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18657 10:14:22.206363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18659 10:14:22.240992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18661 10:14:22.241348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18662 10:14:22.272672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18663 10:14:22.273141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18665 10:14:22.303171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18666 10:14:22.303616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18668 10:14:22.334117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18669 10:14:22.334581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18671 10:14:22.365343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18672 10:14:22.365820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18674 10:14:22.397533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18676 10:14:22.398226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18677 10:14:22.430112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18678 10:14:22.430470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18680 10:14:22.463976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18681 10:14:22.464382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18683 10:14:22.497870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18685 10:14:22.498252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18686 10:14:22.531142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18688 10:14:22.531726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18689 10:14:22.566263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18690 10:14:22.566729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18692 10:14:22.599637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18693 10:14:22.600014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18695 10:14:22.639218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18696 10:14:22.639691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18698 10:14:22.671294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18699 10:14:22.671754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18701 10:14:22.705598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18702 10:14:22.706080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18704 10:14:22.740124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18706 10:14:22.740771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18707 10:14:22.774069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18709 10:14:22.774676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18710 10:14:22.809251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18712 10:14:22.809803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18713 10:14:22.843133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18715 10:14:22.843695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18716 10:14:22.878490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18718 10:14:22.878939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18719 10:14:22.910814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18720 10:14:22.911244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18722 10:14:22.944045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18723 10:14:22.944518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18725 10:14:22.977000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18727 10:14:22.977729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18728 10:14:23.017770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18729 10:14:23.018218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18731 10:14:23.051489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18732 10:14:23.051937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18734 10:14:23.083308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18735 10:14:23.083742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18737 10:14:23.114591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18738 10:14:23.115021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18740 10:14:23.145932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18741 10:14:23.146326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18743 10:14:23.177413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18744 10:14:23.177859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18746 10:14:23.211113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18748 10:14:23.211629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18749 10:14:23.242826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18750 10:14:23.243260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18752 10:14:23.274001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18753 10:14:23.274434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18755 10:14:23.306416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18757 10:14:23.306941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18758 10:14:23.337948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18759 10:14:23.338385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18761 10:14:23.370277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18763 10:14:23.370825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18764 10:14:23.403409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18765 10:14:23.403766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18767 10:14:23.434004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18768 10:14:23.434355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18770 10:14:23.464833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18772 10:14:23.465256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18773 10:14:23.496390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18774 10:14:23.496736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18776 10:14:23.527473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18777 10:14:23.527917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18779 10:14:23.561827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18780 10:14:23.562286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18782 10:14:23.593715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18784 10:14:23.594246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18785 10:14:23.625662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18786 10:14:23.626049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18788 10:14:23.657625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18790 10:14:23.658066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18791 10:14:23.689371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18793 10:14:23.689813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18794 10:14:23.725408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18795 10:14:23.725788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18797 10:14:23.757863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18798 10:14:23.758321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18800 10:14:23.789135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18801 10:14:23.789490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18803 10:14:23.821216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18805 10:14:23.821625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18806 10:14:23.852415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18808 10:14:23.852977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18809 10:14:23.884226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18810 10:14:23.884669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18812 10:14:23.918114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18814 10:14:23.918664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18815 10:14:23.948691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18817 10:14:23.949219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18818 10:14:23.979897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18819 10:14:23.980369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18821 10:14:24.013471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18823 10:14:24.014039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18824 10:14:24.046017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18825 10:14:24.046562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18827 10:14:24.081535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18828 10:14:24.081951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18830 10:14:24.115644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18831 10:14:24.116053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18833 10:14:24.149066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18835 10:14:24.149509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18836 10:14:24.182387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18837 10:14:24.182795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18839 10:14:24.215778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18840 10:14:24.216227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18842 10:14:24.249877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18843 10:14:24.250287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18845 10:14:24.284023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18846 10:14:24.284436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18848 10:14:24.318009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18850 10:14:24.318568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18851 10:14:24.350980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18852 10:14:24.351432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18854 10:14:24.382233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18855 10:14:24.382617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18857 10:14:24.415581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18859 10:14:24.416123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18860 10:14:24.446818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18861 10:14:24.447181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18863 10:14:24.477676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18864 10:14:24.478141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18866 10:14:24.509216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18867 10:14:24.509559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18869 10:14:24.541177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18870 10:14:24.541520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18872 10:14:24.573421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18873 10:14:24.573762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18875 10:14:24.605633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18876 10:14:24.605983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18878 10:14:24.636916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18880 10:14:24.637356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18881 10:14:24.667485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18882 10:14:24.667827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18884 10:14:24.698115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18885 10:14:24.698471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18887 10:14:24.728853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18889 10:14:24.729271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18890 10:14:24.763302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18892 10:14:24.763924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18893 10:14:24.799358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18894 10:14:24.799726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18896 10:14:24.830654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18898 10:14:24.831210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18899 10:14:24.862150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18901 10:14:24.862677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18902 10:14:24.893563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18904 10:14:24.894158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18905 10:14:24.924369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18906 10:14:24.924836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18908 10:14:24.955396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18909 10:14:24.955872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18911 10:14:24.986263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18912 10:14:24.986717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18914 10:14:25.017703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18915 10:14:25.018169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18917 10:14:25.048361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18918 10:14:25.048770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18920 10:14:25.079529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18921 10:14:25.079922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18923 10:14:25.110543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18925 10:14:25.110969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18926 10:14:25.141484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
18928 10:14:25.142028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18929 10:14:25.171906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
18930 10:14:25.172338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
18932 10:14:25.202336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
18933 10:14:25.202721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
18935 10:14:25.232693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
18937 10:14:25.233133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
18938 10:14:25.263476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
18939 10:14:25.263909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
18941 10:14:25.296638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
18943 10:14:25.297190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
18944 10:14:25.328429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
18945 10:14:25.328909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
18947 10:14:25.359871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
18948 10:14:25.360306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
18950 10:14:25.390361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
18952 10:14:25.390876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
18953 10:14:25.420869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
18955 10:14:25.421390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
18956 10:14:25.456072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
18957 10:14:25.456549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
18959 10:14:25.487554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
18961 10:14:25.488093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
18962 10:14:25.518513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
18963 10:14:25.518951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
18965 10:14:25.549990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
18966 10:14:25.550383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
18968 10:14:25.580930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
18970 10:14:25.581351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
18971 10:14:25.611923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
18973 10:14:25.612494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
18974 10:14:25.642377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
18976 10:14:25.642942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
18977 10:14:25.672815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
18979 10:14:25.673230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
18980 10:14:25.702872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
18981 10:14:25.703212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
18983 10:14:25.733212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
18984 10:14:25.733549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
18986 10:14:25.763398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
18987 10:14:25.763732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
18989 10:14:25.793674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
18990 10:14:25.794012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
18992 10:14:25.824061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
18993 10:14:25.824400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
18995 10:14:25.854966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
18996 10:14:25.855313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
18998 10:14:25.885514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
18999 10:14:25.885871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
19001 10:14:25.915511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
19002 10:14:25.915843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
19004 10:14:25.945852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
19005 10:14:25.946181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
19007 10:14:25.976586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
19008 10:14:25.976915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
19010 10:14:26.007681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
19011 10:14:26.008153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
19013 10:14:26.038657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
19014 10:14:26.039099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
19016 10:14:26.069505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
19017 10:14:26.069960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
19019 10:14:26.100088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
19020 10:14:26.100450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
19022 10:14:26.130196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
19023 10:14:26.130538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
19025 10:14:26.161212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
19026 10:14:26.161553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
19028 10:14:26.191964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
19029 10:14:26.192307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
19031 10:14:26.221777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
19033 10:14:26.222247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
19034 10:14:26.252035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
19036 10:14:26.252484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
19037 10:14:26.283913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
19039 10:14:26.284444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
19040 10:14:26.314160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
19041 10:14:26.314503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
19043 10:14:26.345574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
19044 10:14:26.345928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
19046 10:14:26.376260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
19048 10:14:26.376714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
19049 10:14:26.406580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
19050 10:14:26.406922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
19052 10:14:26.436875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
19054 10:14:26.437294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
19055 10:14:26.466913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
19056 10:14:26.467266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
19058 10:14:26.503895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
19059 10:14:26.504232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
19061 10:14:26.535168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
19062 10:14:26.535482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
19064 10:14:26.565563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
19065 10:14:26.565911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
19067 10:14:26.595329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
19068 10:14:26.595668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
19070 10:14:26.626397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
19072 10:14:26.626962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
19073 10:14:26.656851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
19075 10:14:26.657331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
19076 10:14:26.687443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
19077 10:14:26.687802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
19079 10:14:26.718292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
19080 10:14:26.718766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
19082 10:14:26.749890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
19083 10:14:26.750324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
19085 10:14:26.781312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
19087 10:14:26.781834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
19088 10:14:26.812191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
19089 10:14:26.812641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
19091 10:14:26.843873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
19093 10:14:26.844402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
19094 10:14:26.875034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
19095 10:14:26.875475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
19097 10:14:26.905848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
19098 10:14:26.906291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
19100 10:14:26.937555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
19101 10:14:26.938014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
19103 10:14:26.968568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
19104 10:14:26.969034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
19106 10:14:27.017669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
19107 10:14:27.018150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
19109 10:14:27.048645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
19110 10:14:27.049080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
19112 10:14:27.079975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
19113 10:14:27.080426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
19115 10:14:27.111691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
19117 10:14:27.112220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
19118 10:14:27.143322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
19119 10:14:27.143776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
19121 10:14:27.174729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
19122 10:14:27.175180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
19124 10:14:27.205677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
19125 10:14:27.206019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
19127 10:14:27.236259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
19128 10:14:27.236669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
19130 10:14:27.268568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
19131 10:14:27.268998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
19133 10:14:27.300480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
19134 10:14:27.300825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
19136 10:14:27.331241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
19137 10:14:27.331605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
19139 10:14:27.362500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
19141 10:14:27.362890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
19142 10:14:27.393644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
19143 10:14:27.393990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
19145 10:14:27.424525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
19146 10:14:27.424866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
19148 10:14:27.455465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
19149 10:14:27.455804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
19151 10:14:27.486289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
19152 10:14:27.486658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
19154 10:14:27.517466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
19155 10:14:27.517798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
19157 10:14:27.549343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
19158 10:14:27.549690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
19160 10:14:27.580045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
19162 10:14:27.580458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
19163 10:14:27.610845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
19164 10:14:27.611186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
19166 10:14:27.641902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
19167 10:14:27.642243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
19169 10:14:27.672584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
19170 10:14:27.672928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
19172 10:14:27.702781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19173 10:14:27.703134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19175 10:14:27.732914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19177 10:14:27.733346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19178 10:14:27.763114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19179 10:14:27.763454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19181 10:14:27.795058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19183 10:14:27.795576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19184 10:14:27.825704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19185 10:14:27.826129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19187 10:14:27.856160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19188 10:14:27.856526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19190 10:14:27.886390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19192 10:14:27.887011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19193 10:14:27.917113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19194 10:14:27.917565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19196 10:14:27.947769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19197 10:14:27.948210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19199 10:14:27.978083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19200 10:14:27.978521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19202 10:14:28.008625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19203 10:14:28.009054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19205 10:14:28.041580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19207 10:14:28.042285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19208 10:14:28.074105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19210 10:14:28.074648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19211 10:14:28.106112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19213 10:14:28.106651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19214 10:14:28.137311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19216 10:14:28.137841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19217 10:14:28.167938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19219 10:14:28.168467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19220 10:14:28.198516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19222 10:14:28.199104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19223 10:14:28.228626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19224 10:14:28.229061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19226 10:14:28.258862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19227 10:14:28.259292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19229 10:14:28.289785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19230 10:14:28.290181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19232 10:14:28.320505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19234 10:14:28.320960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19235 10:14:28.351515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19237 10:14:28.351990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19238 10:14:28.382533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19240 10:14:28.383043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19241 10:14:28.413971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19242 10:14:28.414395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19244 10:14:28.444648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19246 10:14:28.445142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19247 10:14:28.474809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19248 10:14:28.475218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19250 10:14:28.505582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19251 10:14:28.505994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19253 10:14:28.537449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19254 10:14:28.537912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19256 10:14:28.568218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19258 10:14:28.568789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19259 10:14:28.601299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19260 10:14:28.601693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19262 10:14:28.634682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19263 10:14:28.635097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19265 10:14:28.668359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19267 10:14:28.668822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19268 10:14:28.701586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19269 10:14:28.702026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19271 10:14:28.741326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19272 10:14:28.741779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19274 10:14:28.784969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19276 10:14:28.785415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19277 10:14:28.797619 <47>[ 188.490231] systemd-journald[105]: Sent WATCHDOG=1 notification.
19278 10:14:28.825241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19280 10:14:28.825990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19281 10:14:28.861860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19282 10:14:28.862320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19284 10:14:28.895217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19285 10:14:28.895578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19287 10:14:28.927624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19288 10:14:28.927969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19290 10:14:28.960299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19292 10:14:28.960758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19293 10:14:28.995048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19294 10:14:28.995470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19296 10:14:29.026617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19297 10:14:29.026979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19299 10:14:29.059237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19301 10:14:29.059688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19302 10:14:29.093371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19304 10:14:29.093818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19305 10:14:29.125800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19306 10:14:29.126203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19308 10:14:29.158513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19310 10:14:29.159040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19311 10:14:29.190375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19312 10:14:29.190752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19314 10:14:29.222100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19315 10:14:29.222572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19317 10:14:29.253429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19318 10:14:29.253906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19320 10:14:29.284486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19322 10:14:29.284939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19323 10:14:29.316088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19324 10:14:29.316561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19326 10:14:29.347432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19327 10:14:29.347914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19329 10:14:29.378579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19331 10:14:29.379199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19332 10:14:29.409910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19333 10:14:29.410354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19335 10:14:29.441034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19337 10:14:29.441614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19338 10:14:29.471808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19339 10:14:29.472251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19341 10:14:29.502634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19342 10:14:29.503105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19344 10:14:29.533734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19345 10:14:29.534185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19347 10:14:29.565210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19349 10:14:29.565832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19350 10:14:29.597400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19351 10:14:29.597859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19353 10:14:29.628179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19354 10:14:29.628622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19356 10:14:29.658965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19357 10:14:29.659420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19359 10:14:29.689902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19360 10:14:29.690363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19362 10:14:29.725917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19363 10:14:29.726284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19365 10:14:29.763268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19367 10:14:29.763866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19368 10:14:29.793696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19369 10:14:29.794151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19371 10:14:29.824657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19372 10:14:29.825067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19374 10:14:29.857368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19375 10:14:29.857859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19377 10:14:29.888298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19378 10:14:29.888765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19380 10:14:29.920263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19381 10:14:29.920718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19383 10:14:29.952551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19384 10:14:29.952970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19386 10:14:29.983631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19387 10:14:29.984085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19389 10:14:30.014458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19390 10:14:30.014914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19392 10:14:30.045892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19394 10:14:30.046450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19395 10:14:30.077119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19397 10:14:30.077679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19398 10:14:30.107921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19399 10:14:30.108387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19401 10:14:30.138752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19403 10:14:30.139281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19404 10:14:30.170386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19405 10:14:30.170868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19407 10:14:30.201665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19408 10:14:30.202061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19410 10:14:30.232485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19411 10:14:30.232894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19413 10:14:30.264484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19414 10:14:30.264899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19416 10:14:30.295636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19417 10:14:30.296089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19419 10:14:30.326176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19420 10:14:30.326575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19422 10:14:30.358272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19424 10:14:30.358718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19425 10:14:30.389308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19427 10:14:30.389886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19428 10:14:30.420372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19430 10:14:30.420958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19431 10:14:30.450685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19432 10:14:30.451128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19434 10:14:30.485034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19436 10:14:30.485788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19437 10:14:30.517081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19439 10:14:30.517703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19440 10:14:30.548546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19441 10:14:30.548946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19443 10:14:30.579382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19445 10:14:30.579916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19446 10:14:30.610580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19447 10:14:30.610967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19449 10:14:30.641622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19450 10:14:30.642097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19452 10:14:30.672018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19454 10:14:30.672439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19455 10:14:30.703292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19457 10:14:30.703723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19458 10:14:30.734319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19460 10:14:30.734865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19461 10:14:30.765858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19462 10:14:30.766312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19464 10:14:30.796348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19466 10:14:30.796944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19467 10:14:30.826979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19468 10:14:30.827452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19470 10:14:30.858008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19471 10:14:30.858468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19473 10:14:30.889940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19475 10:14:30.890490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19476 10:14:30.921250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19478 10:14:30.921807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19479 10:14:30.953467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19481 10:14:30.954027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19482 10:14:30.986144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19483 10:14:30.986619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19485 10:14:31.018655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19486 10:14:31.019112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19488 10:14:31.049561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19489 10:14:31.050048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19491 10:14:31.080935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19493 10:14:31.081383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19494 10:14:31.112163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19495 10:14:31.112610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19497 10:14:31.143589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19498 10:14:31.144031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19500 10:14:31.175262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19501 10:14:31.175728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19503 10:14:31.206868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19504 10:14:31.207342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19506 10:14:31.237736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19507 10:14:31.238162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19509 10:14:31.268995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19511 10:14:31.269611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19512 10:14:31.300240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19513 10:14:31.300695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19515 10:14:31.331145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19516 10:14:31.331600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19518 10:14:31.362391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19519 10:14:31.362854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19521 10:14:31.393680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19523 10:14:31.394294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19524 10:14:31.425047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19525 10:14:31.425508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19527 10:14:31.456035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19529 10:14:31.456596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19530 10:14:31.487166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19531 10:14:31.487608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19533 10:14:31.518583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19535 10:14:31.519198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19536 10:14:31.549291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19538 10:14:31.549905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19539 10:14:31.579975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19541 10:14:31.580529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19542 10:14:31.611660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19544 10:14:31.612092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19545 10:14:31.643200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19546 10:14:31.643605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19548 10:14:31.678836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19549 10:14:31.679266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19551 10:14:31.714660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19552 10:14:31.715171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19554 10:14:31.752057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19556 10:14:31.752513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19557 10:14:31.782909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19558 10:14:31.783307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19560 10:14:31.813732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19561 10:14:31.814138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19563 10:14:31.846634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19564 10:14:31.847113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19566 10:14:31.878583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19567 10:14:31.879036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19569 10:14:31.909701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19570 10:14:31.910157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19572 10:14:31.940982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19573 10:14:31.941430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19575 10:14:31.971609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19576 10:14:31.972058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19578 10:14:32.002694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19580 10:14:32.003245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19581 10:14:32.033931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19582 10:14:32.034375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19584 10:14:32.065569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19585 10:14:32.066001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19587 10:14:32.096452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19588 10:14:32.096894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19590 10:14:32.148080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19592 10:14:32.148633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19593 10:14:32.181415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19594 10:14:32.181853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19596 10:14:32.216881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19598 10:14:32.217488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19599 10:14:32.250034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19601 10:14:32.250579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19602 10:14:32.283902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19604 10:14:32.284341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19605 10:14:32.317335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19606 10:14:32.317733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19608 10:14:32.352329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19610 10:14:32.352796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19611 10:14:32.387184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19612 10:14:32.387602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19614 10:14:32.421395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19616 10:14:32.421855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19617 10:14:32.455037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19618 10:14:32.455474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19620 10:14:32.488387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19621 10:14:32.488832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19623 10:14:32.522865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19625 10:14:32.523444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19626 10:14:32.556284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19627 10:14:32.556769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19629 10:14:32.589495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19630 10:14:32.589890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19632 10:14:32.622256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19633 10:14:32.622644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19635 10:14:32.652834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19637 10:14:32.653412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19638 10:14:32.684074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19639 10:14:32.684582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19641 10:14:32.714953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19643 10:14:32.715359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19644 10:14:32.745365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19645 10:14:32.745824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19647 10:14:32.775468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19648 10:14:32.775855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19650 10:14:32.805695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19651 10:14:32.806041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19653 10:14:32.836153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19654 10:14:32.836648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19656 10:14:32.866793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19657 10:14:32.867261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19659 10:14:32.897636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19661 10:14:32.898171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19662 10:14:32.928213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19664 10:14:32.928776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19665 10:14:32.958675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19667 10:14:32.959281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19668 10:14:32.989560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19669 10:14:32.990090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19671 10:14:33.034708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19672 10:14:33.035132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19674 10:14:33.067846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19675 10:14:33.068262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19677 10:14:33.099094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19678 10:14:33.099509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19680 10:14:33.131018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19682 10:14:33.131477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19683 10:14:33.163650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19684 10:14:33.164059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19686 10:14:33.195110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19687 10:14:33.195579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19689 10:14:33.227272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19690 10:14:33.227697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19692 10:14:33.260087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19693 10:14:33.260537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19695 10:14:33.291187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19697 10:14:33.291719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19698 10:14:33.324143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19699 10:14:33.324575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19701 10:14:33.355539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19702 10:14:33.355993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19704 10:14:33.386838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19705 10:14:33.387226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19707 10:14:33.418594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19708 10:14:33.419054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19710 10:14:33.450683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19711 10:14:33.451169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19713 10:14:33.483415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19714 10:14:33.483865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19716 10:14:33.515573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19717 10:14:33.516071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19719 10:14:33.552077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19720 10:14:33.552483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19722 10:14:33.585013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19724 10:14:33.585350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19725 10:14:33.622090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19727 10:14:33.622709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19728 10:14:33.662557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19729 10:14:33.662996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19731 10:14:33.702313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19732 10:14:33.702691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19734 10:14:33.734448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19736 10:14:33.734886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19737 10:14:33.768398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19738 10:14:33.768803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19740 10:14:33.801207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19742 10:14:33.801656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19743 10:14:33.833530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19744 10:14:33.833969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19746 10:14:33.869973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19748 10:14:33.870424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19749 10:14:33.907139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19750 10:14:33.907602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19752 10:14:33.942073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19754 10:14:33.942521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19755 10:14:33.980091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19756 10:14:33.980483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19758 10:14:34.020671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19759 10:14:34.021136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19761 10:14:34.056493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19762 10:14:34.056990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19764 10:14:34.098260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19766 10:14:34.098918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19767 10:14:34.136293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19768 10:14:34.136716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19770 10:14:34.174687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19772 10:14:34.175282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19773 10:14:34.210816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19775 10:14:34.211218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19776 10:14:34.244407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19777 10:14:34.244811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19779 10:14:34.278385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19781 10:14:34.278820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19782 10:14:34.312923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19784 10:14:34.313311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19785 10:14:34.349541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19786 10:14:34.349953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19788 10:14:34.388731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19790 10:14:34.389177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19791 10:14:34.427102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19793 10:14:34.427511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19794 10:14:34.461480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19796 10:14:34.461856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19797 10:14:34.495785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19799 10:14:34.496389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19800 10:14:34.531628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19802 10:14:34.532169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19803 10:14:34.564855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19805 10:14:34.565250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19806 10:14:34.598960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19807 10:14:34.599333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19809 10:14:34.632305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19810 10:14:34.632687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19812 10:14:34.670797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19813 10:14:34.671163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19815 10:14:34.706215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19817 10:14:34.706597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19818 10:14:34.740374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19819 10:14:34.740739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19821 10:14:34.774829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19823 10:14:34.775414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19824 10:14:34.811649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19825 10:14:34.812136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19827 10:14:34.851151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19829 10:14:34.851693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19830 10:14:34.900834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19832 10:14:34.901549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19833 10:14:34.935262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19834 10:14:34.935736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19836 10:14:34.970419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19837 10:14:34.970890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19839 10:14:35.008935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19841 10:14:35.009621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19842 10:14:35.044194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19843 10:14:35.044684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19845 10:14:35.082504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19846 10:14:35.082925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19848 10:14:35.121915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19850 10:14:35.122519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19851 10:14:35.158312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19853 10:14:35.159044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19854 10:14:35.204078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19856 10:14:35.204534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19857 10:14:35.244873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19859 10:14:35.245602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19860 10:14:35.283345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19862 10:14:35.283788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19863 10:14:35.318711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19864 10:14:35.319216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19866 10:14:35.354849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19868 10:14:35.355461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19869 10:14:35.392343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19870 10:14:35.392765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19872 10:14:35.430742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19874 10:14:35.431199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19875 10:14:35.471227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19876 10:14:35.471760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19878 10:14:35.523336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19879 10:14:35.523773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19881 10:14:35.578310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19883 10:14:35.578762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19884 10:14:35.638998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19886 10:14:35.639452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19887 10:14:35.690811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19888 10:14:35.691260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19890 10:14:35.742985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19891 10:14:35.743376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19893 10:14:35.795871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19894 10:14:35.796276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19896 10:14:35.847337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19898 10:14:35.847823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19899 10:14:35.898679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19900 10:14:35.899149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19902 10:14:35.936304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19904 10:14:35.937079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19905 10:14:35.979608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19906 10:14:35.980078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19908 10:14:36.031184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19909 10:14:36.031673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19911 10:14:36.079412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19912 10:14:36.079877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19914 10:14:36.131135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19915 10:14:36.131480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19917 10:14:36.180278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19918 10:14:36.180747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19920 10:14:36.215087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19922 10:14:36.215653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19923 10:14:36.249564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19924 10:14:36.249987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19926 10:14:36.284861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19927 10:14:36.285353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
19929 10:14:36.323217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
19930 10:14:36.323647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
19932 10:14:36.358063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
19933 10:14:36.358561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
19935 10:14:36.393417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
19936 10:14:36.393848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
19938 10:14:36.428719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
19940 10:14:36.429187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
19941 10:14:36.463935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
19942 10:14:36.464455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
19944 10:14:36.499797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
19945 10:14:36.500283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
19947 10:14:36.535096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
19949 10:14:36.535672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
19950 10:14:36.571742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
19951 10:14:36.572274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
19953 10:14:36.610104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
19955 10:14:36.610851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
19956 10:14:36.647901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
19958 10:14:36.648537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
19959 10:14:36.686204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
19960 10:14:36.686743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
19962 10:14:36.721959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
19963 10:14:36.722506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
19965 10:14:36.759558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
19967 10:14:36.760128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
19968 10:14:36.795507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
19969 10:14:36.795962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
19971 10:14:36.830084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
19972 10:14:36.830622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
19974 10:14:36.865628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
19975 10:14:36.866124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
19977 10:14:36.899943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
19979 10:14:36.900419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
19980 10:14:36.935763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
19981 10:14:36.936182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
19983 10:14:36.971089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
19984 10:14:36.971567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
19986 10:14:37.006501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
19987 10:14:37.007030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
19989 10:14:37.041720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
19991 10:14:37.042175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
19992 10:14:37.076227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
19994 10:14:37.076971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
19995 10:14:37.111339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
19996 10:14:37.111813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
19998 10:14:37.146135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
19999 10:14:37.146549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
20001 10:14:37.182053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
20002 10:14:37.182473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
20004 10:14:37.219290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
20005 10:14:37.219761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
20007 10:14:37.278541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
20009 10:14:37.279300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
20010 10:14:37.317576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
20011 10:14:37.318122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
20013 10:14:37.360137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
20014 10:14:37.360623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
20016 10:14:37.404544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
20018 10:14:37.404965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
20019 10:14:37.443347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
20020 10:14:37.443821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
20022 10:14:37.487661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
20023 10:14:37.488112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
20025 10:14:37.529124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
20027 10:14:37.529664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
20028 10:14:37.571959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
20030 10:14:37.572391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
20031 10:14:37.605971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
20032 10:14:37.606355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
20034 10:14:37.639289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
20035 10:14:37.639722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
20037 10:14:37.673772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
20038 10:14:37.674187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
20040 10:14:37.708194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
20041 10:14:37.708594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
20043 10:14:37.743112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
20044 10:14:37.743503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
20046 10:14:37.778132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
20047 10:14:37.778517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
20049 10:14:37.813373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
20051 10:14:37.813740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
20052 10:14:37.851728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
20053 10:14:37.852106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
20055 10:14:37.891215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
20056 10:14:37.891613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
20058 10:14:37.926414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
20059 10:14:37.926819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
20061 10:14:37.968313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
20062 10:14:37.968700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
20064 10:14:38.007681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
20065 10:14:38.008199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
20067 10:14:38.044693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
20068 10:14:38.045118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
20070 10:14:38.086767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
20072 10:14:38.087235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
20073 10:14:38.122617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
20074 10:14:38.123033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
20076 10:14:38.160371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
20077 10:14:38.160935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
20079 10:14:38.203901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
20080 10:14:38.204356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
20082 10:14:38.242362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
20084 10:14:38.242903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
20085 10:14:38.290359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
20086 10:14:38.290785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
20088 10:14:38.339384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
20090 10:14:38.339798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
20091 10:14:38.378382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
20093 10:14:38.378798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
20094 10:14:38.414165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
20095 10:14:38.414596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
20097 10:14:38.459175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
20099 10:14:38.459639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
20100 10:14:38.502095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
20102 10:14:38.502568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
20103 10:14:38.541691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
20105 10:14:38.542162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
20106 10:14:38.585635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
20107 10:14:38.586070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
20109 10:14:38.625809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
20110 10:14:38.626231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
20112 10:14:38.671600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
20113 10:14:38.672029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
20115 10:14:38.717558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
20116 10:14:38.717961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
20118 10:14:38.760440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
20120 10:14:38.761196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
20121 10:14:38.807216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
20122 10:14:38.807662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
20124 10:14:38.847590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
20126 10:14:38.848041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
20127 10:14:38.884913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
20129 10:14:38.885340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
20130 10:14:38.921701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
20132 10:14:38.922168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
20133 10:14:38.957161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
20135 10:14:38.957626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
20136 10:14:38.993919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
20137 10:14:38.994449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
20139 10:14:39.028708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
20141 10:14:39.029305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
20142 10:14:39.066030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
20143 10:14:39.066452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
20145 10:14:39.100512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
20146 10:14:39.101009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
20148 10:14:39.139344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
20150 10:14:39.139797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
20151 10:14:39.181105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
20153 10:14:39.181777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
20154 10:14:39.223859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
20155 10:14:39.224321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
20157 10:14:39.260191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
20158 10:14:39.260637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
20160 10:14:39.303233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
20162 10:14:39.303637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
20163 10:14:39.351012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
20165 10:14:39.351442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
20166 10:14:39.393818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
20168 10:14:39.394603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
20169 10:14:39.431394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
20171 10:14:39.431842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
20172 10:14:39.478495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20174 10:14:39.478862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
20175 10:14:39.532904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20177 10:14:39.533528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20178 10:14:39.570540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20179 10:14:39.570893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20181 10:14:39.607858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20182 10:14:39.608216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20184 10:14:39.648734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20186 10:14:39.649291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20187 10:14:39.688610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20189 10:14:39.689174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20190 10:14:39.730940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20191 10:14:39.731375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20193 10:14:39.767303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20194 10:14:39.767775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20196 10:14:39.803718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20197 10:14:39.804123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20199 10:14:39.839585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20200 10:14:39.839930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20202 10:14:39.874087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20203 10:14:39.874505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20205 10:14:39.909371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20206 10:14:39.909774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20208 10:14:39.944568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20209 10:14:39.944997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20211 10:14:39.981273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20212 10:14:39.981698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20214 10:14:40.021657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20216 10:14:40.022303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20217 10:14:40.062712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20218 10:14:40.063111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20220 10:14:40.110623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20222 10:14:40.111442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20223 10:14:40.158279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20224 10:14:40.158731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20226 10:14:40.207062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20227 10:14:40.207533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20229 10:14:40.251894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20230 10:14:40.252320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20232 10:14:40.303796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20234 10:14:40.304340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20235 10:14:40.349620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20236 10:14:40.350083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20238 10:14:40.386460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20239 10:14:40.386808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20241 10:14:40.428153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20242 10:14:40.428624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20244 10:14:40.467068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20245 10:14:40.467513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20247 10:14:40.504481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20248 10:14:40.505003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20250 10:14:40.549783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20252 10:14:40.550386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20253 10:14:40.602627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20255 10:14:40.603034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20256 10:14:40.656402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20257 10:14:40.656824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20259 10:14:40.711057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20260 10:14:40.711384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20262 10:14:40.754648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20264 10:14:40.755262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20265 10:14:40.791932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20266 10:14:40.792409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20268 10:14:40.827680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20269 10:14:40.828177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20271 10:14:40.869517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20273 10:14:40.869938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20274 10:14:40.914430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20275 10:14:40.914836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20277 10:14:40.952590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20278 10:14:40.953017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20280 10:14:41.004105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20282 10:14:41.004848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20283 10:14:41.046502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20284 10:14:41.046907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20286 10:14:41.095230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20287 10:14:41.095659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20289 10:14:41.148691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20291 10:14:41.149161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20292 10:14:41.202382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20293 10:14:41.202825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20295 10:14:41.247947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20297 10:14:41.248418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20298 10:14:41.296433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20299 10:14:41.296854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20301 10:14:41.337451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20302 10:14:41.337921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20304 10:14:41.377356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20305 10:14:41.377937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20307 10:14:41.413034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20309 10:14:41.413489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20310 10:14:41.457800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20312 10:14:41.458263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20313 10:14:41.495608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20315 10:14:41.496059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20316 10:14:41.533364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20318 10:14:41.533830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20319 10:14:41.574201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20320 10:14:41.574616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20322 10:14:41.614150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20323 10:14:41.614603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20325 10:14:41.666878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20326 10:14:41.667304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20328 10:14:41.703211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20329 10:14:41.703658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20331 10:14:41.742427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20333 10:14:41.743024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20334 10:14:41.788760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20336 10:14:41.789206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20337 10:14:41.825050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20339 10:14:41.825472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20340 10:14:41.861259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20341 10:14:41.861678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20343 10:14:41.899104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20345 10:14:41.899557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20346 10:14:41.939335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20347 10:14:41.939759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20349 10:14:41.979925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20351 10:14:41.980356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20352 10:14:42.019553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20354 10:14:42.020223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20355 10:14:42.057606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20356 10:14:42.057971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20358 10:14:42.097679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20359 10:14:42.098029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20361 10:14:42.134677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20362 10:14:42.135042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20364 10:14:42.171927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20366 10:14:42.172252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20367 10:14:42.212655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20369 10:14:42.213120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20370 10:14:42.251525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20372 10:14:42.252127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20373 10:14:42.293455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20375 10:14:42.293942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20376 10:14:42.333450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20377 10:14:42.333942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20379 10:14:42.397487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20381 10:14:42.398157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20382 10:14:42.433720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20384 10:14:42.434183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20385 10:14:42.469900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20386 10:14:42.470356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20388 10:14:42.517548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20389 10:14:42.517942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20391 10:14:42.558548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20393 10:14:42.558923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20394 10:14:42.595874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20395 10:14:42.596361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20397 10:14:42.632260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20399 10:14:42.632731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20400 10:14:42.668257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20402 10:14:42.668898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20403 10:14:42.704581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20404 10:14:42.705087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20406 10:14:42.746777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20407 10:14:42.747276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20409 10:14:42.784940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20411 10:14:42.785692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20412 10:14:42.821633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20413 10:14:42.822074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20415 10:14:42.858950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20416 10:14:42.859342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20418 10:14:42.902420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20419 10:14:42.902766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20421 10:14:42.951232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20422 10:14:42.951635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20424 10:14:42.996347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20426 10:14:42.996993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20427 10:14:43.043500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20428 10:14:43.043957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20430 10:14:43.088083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20432 10:14:43.088783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20433 10:14:43.128001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20434 10:14:43.128475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20436 10:14:43.165671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20437 10:14:43.166057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20439 10:14:43.200856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20441 10:14:43.201270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20442 10:14:43.236114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20443 10:14:43.236645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20445 10:14:43.270563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20446 10:14:43.271100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20448 10:14:43.306723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20449 10:14:43.307130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20451 10:14:43.342477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20453 10:14:43.342942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20454 10:14:43.379085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20455 10:14:43.379504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20457 10:14:43.415673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20458 10:14:43.416112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20460 10:14:43.466934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20461 10:14:43.467350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20463 10:14:43.504734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20465 10:14:43.505205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20466 10:14:43.542744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20467 10:14:43.543222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20469 10:14:43.584183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20470 10:14:43.584704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20472 10:14:43.628083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20473 10:14:43.628579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20475 10:14:43.665710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20476 10:14:43.666104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20478 10:14:43.709636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20480 10:14:43.710272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20481 10:14:43.753690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20482 10:14:43.754048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20484 10:14:43.795890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20485 10:14:43.796268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20487 10:14:43.841824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20488 10:14:43.842289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20490 10:14:43.887105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20491 10:14:43.887647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20493 10:14:43.933922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20494 10:14:43.934346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20496 10:14:43.974324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20497 10:14:43.974798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20499 10:14:44.012862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20501 10:14:44.013490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20502 10:14:44.059526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20503 10:14:44.060061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20505 10:14:44.104772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20506 10:14:44.105256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20508 10:14:44.146219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20509 10:14:44.146659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20511 10:14:44.187351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20513 10:14:44.187706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20514 10:14:44.231098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20515 10:14:44.231543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20517 10:14:44.269368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20519 10:14:44.270130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20520 10:14:44.311042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20522 10:14:44.311566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20523 10:14:44.346869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20524 10:14:44.347306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20526 10:14:44.382167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20528 10:14:44.382941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20529 10:14:44.424063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20531 10:14:44.424671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20532 10:14:44.458331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20533 10:14:44.458797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20535 10:14:44.493864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20536 10:14:44.494310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20538 10:14:44.529500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20539 10:14:44.529942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20541 10:14:44.563883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20542 10:14:44.564299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20544 10:14:44.599270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20545 10:14:44.599685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20547 10:14:44.635315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20549 10:14:44.635971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20550 10:14:44.671189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20551 10:14:44.671603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20553 10:14:44.706650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20555 10:14:44.707269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20556 10:14:44.746467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20557 10:14:44.746891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20559 10:14:44.783934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20560 10:14:44.784442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20562 10:14:44.822764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20564 10:14:44.823456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20565 10:14:44.860182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20567 10:14:44.860891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20568 10:14:44.897951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20570 10:14:44.898379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20571 10:14:44.935555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20572 10:14:44.936029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20574 10:14:44.972049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20575 10:14:44.972418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20577 10:14:45.007032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20578 10:14:45.007433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20580 10:14:45.046538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20581 10:14:45.047031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20583 10:14:45.083426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20585 10:14:45.083889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20586 10:14:45.123445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20588 10:14:45.123787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20589 10:14:45.161618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20590 10:14:45.162095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20592 10:14:45.195508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20593 10:14:45.195985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20595 10:14:45.232174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20596 10:14:45.232620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20598 10:14:45.272336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20600 10:14:45.272804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20601 10:14:45.318174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20602 10:14:45.318636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20604 10:14:45.362652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20605 10:14:45.363091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20607 10:14:45.397833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20608 10:14:45.398274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20610 10:14:45.437901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20611 10:14:45.438469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20613 10:14:45.474238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20614 10:14:45.474714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20616 10:14:45.509599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20618 10:14:45.510024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20619 10:14:45.555748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20620 10:14:45.556138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20622 10:14:45.614970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20623 10:14:45.615505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20625 10:14:45.669532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20627 10:14:45.670039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20628 10:14:45.704252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20629 10:14:45.704688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20631 10:14:45.745683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20632 10:14:45.746080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20634 10:14:45.780331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20636 10:14:45.780904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20637 10:14:45.816075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20638 10:14:45.816620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20640 10:14:45.850594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20641 10:14:45.851001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20643 10:14:45.885676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20644 10:14:45.886066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20646 10:14:45.921756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20647 10:14:45.922224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20649 10:14:45.954985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20650 10:14:45.955312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20652 10:14:45.992173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20653 10:14:45.992481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20655 10:14:46.035093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20656 10:14:46.035452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20658 10:14:46.074607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20659 10:14:46.074997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20661 10:14:46.117600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20662 10:14:46.117952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20664 10:14:46.156307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20665 10:14:46.156707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20667 10:14:46.198739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20669 10:14:46.199055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20670 10:14:46.237309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20671 10:14:46.237783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20673 10:14:46.280480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20675 10:14:46.281056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20676 10:14:46.322499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20677 10:14:46.322977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20679 10:14:46.358093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20680 10:14:46.358601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20682 10:14:46.393745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20683 10:14:46.394229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20685 10:14:46.431255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20686 10:14:46.431811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20688 10:14:46.471434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20689 10:14:46.471897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20691 10:14:46.514262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20693 10:14:46.514833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20694 10:14:46.551688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20695 10:14:46.552201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20697 10:14:46.591388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20698 10:14:46.591772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20700 10:14:46.635091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20701 10:14:46.635570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20703 10:14:46.671949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20704 10:14:46.672487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20706 10:14:46.706553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20707 10:14:46.706946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20709 10:14:46.741787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20711 10:14:46.742237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20712 10:14:46.777138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20713 10:14:46.777523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20715 10:14:46.817714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20716 10:14:46.818175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20718 10:14:46.864397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20720 10:14:46.864971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20721 10:14:46.909766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20722 10:14:46.910254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20724 10:14:46.949294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20725 10:14:46.949696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20727 10:14:46.989130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20729 10:14:46.989925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20730 10:14:47.034377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20731 10:14:47.034803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20733 10:14:47.079082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20735 10:14:47.079463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20736 10:14:47.120005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20737 10:14:47.120322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20739 10:14:47.163166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20740 10:14:47.163524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20742 10:14:47.206319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20744 10:14:47.206705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20745 10:14:47.242073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20746 10:14:47.242516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20748 10:14:47.277918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20749 10:14:47.278394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20751 10:14:47.318474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20753 10:14:47.319014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20754 10:14:47.354643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20755 10:14:47.355122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20757 10:14:47.389500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20758 10:14:47.389900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20760 10:14:47.424049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20761 10:14:47.424443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20763 10:14:47.466008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20764 10:14:47.466371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20766 10:14:47.529981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20767 10:14:47.530383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20769 10:14:47.571853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20770 10:14:47.572197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20772 10:14:47.607728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20774 10:14:47.608386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20775 10:14:47.642250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20776 10:14:47.642631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20778 10:14:47.678399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20779 10:14:47.678733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20781 10:14:47.714284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20782 10:14:47.714827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20784 10:14:47.755228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20786 10:14:47.755742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20787 10:14:47.798718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20788 10:14:47.799183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20790 10:14:47.843655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20792 10:14:47.844039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20793 10:14:47.882293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20795 10:14:47.882905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20796 10:14:47.916903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20798 10:14:47.917625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20799 10:14:47.951083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20800 10:14:47.951631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20802 10:14:47.987028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20803 10:14:47.987425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20805 10:14:48.022040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20806 10:14:48.022639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20808 10:14:48.066064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20810 10:14:48.066483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20811 10:14:48.110955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20813 10:14:48.111397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20814 10:14:48.152682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20816 10:14:48.153365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20817 10:14:48.195555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20818 10:14:48.195976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20820 10:14:48.237467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20821 10:14:48.238034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20823 10:14:48.275466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20825 10:14:48.275927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20826 10:14:48.319062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20828 10:14:48.319585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20829 10:14:48.372729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20830 10:14:48.373089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20832 10:14:48.413695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20833 10:14:48.414189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20835 10:14:48.449530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20836 10:14:48.449958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20838 10:14:48.484639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20840 10:14:48.485332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20841 10:14:48.520819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20843 10:14:48.521471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20844 10:14:48.563884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20845 10:14:48.564294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20847 10:14:48.605486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20848 10:14:48.605882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20850 10:14:48.646793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20851 10:14:48.647159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20853 10:14:48.689016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20855 10:14:48.689678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20856 10:14:48.732123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20857 10:14:48.732598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20859 10:14:48.771831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20860 10:14:48.772191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20862 10:14:48.815270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20863 10:14:48.815677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20865 10:14:48.854542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20866 10:14:48.854877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20868 10:14:48.897786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20869 10:14:48.898141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20871 10:14:48.934906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20872 10:14:48.935221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20874 10:14:48.970140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20875 10:14:48.970454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20877 10:14:49.007043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20879 10:14:49.007458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20880 10:14:49.050767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20881 10:14:49.051176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20883 10:14:49.092447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20884 10:14:49.093036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20886 10:14:49.139020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20888 10:14:49.139728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20889 10:14:49.181006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20891 10:14:49.181719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20892 10:14:49.225286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20893 10:14:49.225790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20895 10:14:49.271526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20897 10:14:49.272257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20898 10:14:49.318715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20899 10:14:49.319293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20901 10:14:49.364975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20903 10:14:49.365623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20904 10:14:49.413230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20905 10:14:49.413759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20907 10:14:49.459324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20908 10:14:49.459736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20910 10:14:49.495609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20911 10:14:49.496149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20913 10:14:49.531308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20914 10:14:49.531776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20916 10:14:49.566182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20917 10:14:49.566683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20919 10:14:49.602042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20920 10:14:49.602431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20922 10:14:49.637727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20923 10:14:49.638116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20925 10:14:49.673706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20926 10:14:49.674091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20928 10:14:49.714345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
20929 10:14:49.714824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
20931 10:14:49.763413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
20933 10:14:49.763935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
20934 10:14:49.812433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
20935 10:14:49.812871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
20937 10:14:49.860025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
20939 10:14:49.860490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
20940 10:14:49.908187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
20941 10:14:49.908730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
20943 10:14:49.947874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
20944 10:14:49.948423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
20946 10:14:49.983646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
20948 10:14:49.984391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
20949 10:14:50.024494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
20951 10:14:50.024969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
20952 10:14:50.062125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
20954 10:14:50.062585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
20955 10:14:50.098015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
20957 10:14:50.098474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
20958 10:14:50.133479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
20959 10:14:50.133930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
20961 10:14:50.173212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
20962 10:14:50.173659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
20964 10:14:50.216347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
20966 10:14:50.216822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
20967 10:14:50.265680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
20968 10:14:50.266090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
20970 10:14:50.311510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
20972 10:14:50.312101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
20973 10:14:50.355382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
20974 10:14:50.355929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
20976 10:14:50.390162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
20977 10:14:50.390607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
20979 10:14:50.425788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
20980 10:14:50.426235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
20982 10:14:50.469940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
20984 10:14:50.470407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
20985 10:14:50.515629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
20986 10:14:50.516053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
20988 10:14:50.562392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
20989 10:14:50.562814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
20991 10:14:50.602859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
20992 10:14:50.603234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
20994 10:14:50.639627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
20995 10:14:50.640068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
20997 10:14:50.677828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
20999 10:14:50.678216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
21000 10:14:50.714083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
21002 10:14:50.714526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
21003 10:14:50.759493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
21004 10:14:50.759795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
21006 10:14:50.799568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
21007 10:14:50.799926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
21009 10:14:50.834859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
21010 10:14:50.835265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
21012 10:14:50.875580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
21013 10:14:50.875996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
21015 10:14:50.911202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
21016 10:14:50.911559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
21018 10:14:50.946391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
21019 10:14:50.946744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
21021 10:14:50.991826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
21022 10:14:50.992257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
21024 10:14:51.037532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
21025 10:14:51.037974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
21027 10:14:51.073862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
21029 10:14:51.074494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
21030 10:14:51.115846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
21032 10:14:51.116404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
21033 10:14:51.159637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
21034 10:14:51.160125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
21036 10:14:51.202330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
21037 10:14:51.202805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
21039 10:14:51.243063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
21040 10:14:51.243599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
21042 10:14:51.282927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
21043 10:14:51.283411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
21045 10:14:51.326872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
21046 10:14:51.327308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
21048 10:14:51.369207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
21049 10:14:51.369640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
21051 10:14:51.410467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
21052 10:14:51.410917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
21054 10:14:51.459037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
21055 10:14:51.459466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
21057 10:14:51.506352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
21059 10:14:51.507011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
21060 10:14:51.549659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
21061 10:14:51.550061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
21063 10:14:51.595208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
21065 10:14:51.595761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
21066 10:14:51.638539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
21067 10:14:51.638966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
21069 10:14:51.681792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
21070 10:14:51.682262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
21072 10:14:51.724239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
21073 10:14:51.724627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
21075 10:14:51.768694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
21077 10:14:51.769230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
21078 10:14:51.812145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
21079 10:14:51.812529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
21081 10:14:51.854423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
21082 10:14:51.854798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
21084 10:14:51.891132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
21085 10:14:51.891633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
21087 10:14:51.926821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
21089 10:14:51.927185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
21090 10:14:51.961485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
21091 10:14:51.961863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
21093 10:14:52.005894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
21095 10:14:52.006396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
21096 10:14:52.046410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
21098 10:14:52.046880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
21099 10:14:52.081220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
21100 10:14:52.081707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
21102 10:14:52.117512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
21104 10:14:52.118124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
21105 10:14:52.154084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
21106 10:14:52.154625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
21108 10:14:52.200753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
21110 10:14:52.201213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
21111 10:14:52.248650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
21112 10:14:52.249136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
21114 10:14:52.294488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
21115 10:14:52.294913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
21117 10:14:52.338567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
21118 10:14:52.338987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
21120 10:14:52.376121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
21122 10:14:52.376480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
21123 10:14:52.416166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
21124 10:14:52.416594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
21126 10:14:52.460664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
21128 10:14:52.461203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
21129 10:14:52.506909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
21130 10:14:52.507312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
21132 10:14:52.552461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
21133 10:14:52.552966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
21135 10:14:52.618845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
21136 10:14:52.619334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
21138 10:14:52.682668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
21139 10:14:52.683110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
21141 10:14:52.725617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
21142 10:14:52.726193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
21144 10:14:52.764151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
21146 10:14:52.764613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
21147 10:14:52.799643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
21149 10:14:52.800101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
21150 10:14:52.834769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
21152 10:14:52.835211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
21153 10:14:52.870428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
21155 10:14:52.870870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
21156 10:14:52.916543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
21157 10:14:52.916967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
21159 10:14:52.955049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
21160 10:14:52.955425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
21162 10:14:53.002512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
21163 10:14:53.002899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
21165 10:14:53.045375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
21166 10:14:53.045763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
21168 10:14:53.087446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
21170 10:14:53.087895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
21171 10:14:53.122447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21173 10:14:53.122874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
21174 10:14:53.157739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21175 10:14:53.158288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21177 10:14:53.193042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21179 10:14:53.193788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21180 10:14:53.227576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21181 10:14:53.228039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21183 10:14:53.262990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21184 10:14:53.263423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21186 10:14:53.298126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21187 10:14:53.298521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21189 10:14:53.338497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21190 10:14:53.338950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21192 10:14:53.373064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21193 10:14:53.373457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21195 10:14:53.420379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21196 10:14:53.420878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21198 10:14:53.462622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21199 10:14:53.463008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21201 10:14:53.505037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21203 10:14:53.505505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21204 10:14:53.546105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21205 10:14:53.546524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21207 10:14:53.582148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21208 10:14:53.582538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21210 10:14:53.616312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21211 10:14:53.616737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21213 10:14:53.656560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21214 10:14:53.657044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21216 10:14:53.696476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21217 10:14:53.696870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21219 10:14:53.735609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21220 10:14:53.736052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21222 10:14:53.775223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21224 10:14:53.775592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21225 10:14:53.813541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21227 10:14:53.813914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21228 10:14:53.850942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21230 10:14:53.851319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21231 10:14:53.894181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21232 10:14:53.894591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21234 10:14:53.932494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21235 10:14:53.932873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21237 10:14:53.967879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21238 10:14:53.968317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21240 10:14:54.003442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21241 10:14:54.003852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21243 10:14:54.039048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21244 10:14:54.039468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21246 10:14:54.074073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21247 10:14:54.074516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21249 10:14:54.123341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21251 10:14:54.123792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21252 10:14:54.166185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21253 10:14:54.166742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21255 10:14:54.201903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21256 10:14:54.202315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21258 10:14:54.238325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21259 10:14:54.238740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21261 10:14:54.273680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21262 10:14:54.274114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21264 10:14:54.309499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21266 10:14:54.309963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21267 10:14:54.344825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21269 10:14:54.345279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21270 10:14:54.381592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21271 10:14:54.382034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21273 10:14:54.418079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21274 10:14:54.418495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21276 10:14:54.453310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21277 10:14:54.453743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21279 10:14:54.490288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21280 10:14:54.490734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21282 10:14:54.526194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21283 10:14:54.526610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21285 10:14:54.562508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21286 10:14:54.562956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21288 10:14:54.599381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21289 10:14:54.599906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21291 10:14:54.635994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21292 10:14:54.636383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21294 10:14:54.671318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21295 10:14:54.671816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21297 10:14:54.710997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21299 10:14:54.711597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21300 10:14:54.750714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21301 10:14:54.751196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21303 10:14:54.790742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21304 10:14:54.791203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21306 10:14:54.833693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21307 10:14:54.834090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21309 10:14:54.871687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21310 10:14:54.872090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21312 10:14:54.912421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21313 10:14:54.912846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21315 10:14:54.951822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21316 10:14:54.952358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21318 10:14:54.987208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21319 10:14:54.987612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21321 10:14:55.033714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21323 10:14:55.034136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21324 10:14:55.073431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21326 10:14:55.073838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21327 10:14:55.115472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21328 10:14:55.115954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21330 10:14:55.155104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21331 10:14:55.155542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21333 10:14:55.194103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21334 10:14:55.194534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21336 10:14:55.230802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21338 10:14:55.231451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21339 10:14:55.270058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21340 10:14:55.270608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21342 10:14:55.314094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21343 10:14:55.314513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21345 10:14:55.356663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21346 10:14:55.357089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21348 10:14:55.398107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21349 10:14:55.398526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21351 10:14:55.436567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21352 10:14:55.437014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21354 10:14:55.474009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21356 10:14:55.474462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21357 10:14:55.514617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21358 10:14:55.515047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21360 10:14:55.556544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21361 10:14:55.556971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21363 10:14:55.600209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21364 10:14:55.600634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21366 10:14:55.651425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21367 10:14:55.651798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21369 10:14:55.695207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21370 10:14:55.695618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21372 10:14:55.739294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21374 10:14:55.739743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21375 10:14:55.779441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21376 10:14:55.779938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21378 10:14:55.824868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21380 10:14:55.825296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21381 10:14:55.870214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21382 10:14:55.870617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21384 10:14:55.911687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21385 10:14:55.912122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21387 10:14:55.950544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21389 10:14:55.950945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21390 10:14:55.992173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21392 10:14:55.993388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21393 10:14:56.039728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21394 10:14:56.040162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21396 10:14:56.085589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21397 10:14:56.086079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21399 10:14:56.131281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21400 10:14:56.131752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21402 10:14:56.175986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21403 10:14:56.176439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21405 10:14:56.222783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21406 10:14:56.223180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21408 10:14:56.267840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21409 10:14:56.268228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21411 10:14:56.308289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21412 10:14:56.308671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21414 10:14:56.347115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21415 10:14:56.347515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21417 10:14:56.386674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21419 10:14:56.387330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21420 10:14:56.424314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21421 10:14:56.424714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21423 10:14:56.464750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21424 10:14:56.465154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21426 10:14:56.509332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21427 10:14:56.509861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21429 10:14:56.553442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21431 10:14:56.553885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21432 10:14:56.597582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21433 10:14:56.598012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21435 10:14:56.644952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21437 10:14:56.645371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21438 10:14:56.692128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21439 10:14:56.692676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21441 10:14:56.735244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21442 10:14:56.735554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21444 10:14:56.775997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21445 10:14:56.776437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21447 10:14:56.818736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21449 10:14:56.819152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21450 10:14:56.859112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21451 10:14:56.859523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21453 10:14:56.895040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21454 10:14:56.895523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21456 10:14:56.935274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21457 10:14:56.935658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21459 10:14:56.974543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21460 10:14:56.974982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21462 10:14:57.020464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21463 10:14:57.020928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21465 10:14:57.068475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21467 10:14:57.069182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21468 10:14:57.106828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21469 10:14:57.107343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21471 10:14:57.144073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21472 10:14:57.144510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21474 10:14:57.189831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21476 10:14:57.190576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21477 10:14:57.230079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21478 10:14:57.230555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21480 10:14:57.271323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21481 10:14:57.271745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21483 10:14:57.313593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21484 10:14:57.314012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21486 10:14:57.358376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21488 10:14:57.358794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21489 10:14:57.408023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21491 10:14:57.408505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21492 10:14:57.461040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21494 10:14:57.461476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21495 10:14:57.511358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21496 10:14:57.511750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21498 10:14:57.571580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21499 10:14:57.571996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21501 10:14:57.618955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21502 10:14:57.619423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21504 10:14:57.662152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21505 10:14:57.662585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21507 10:14:57.699407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21508 10:14:57.699826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21510 10:14:57.758218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21511 10:14:57.758655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21513 10:14:57.805715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21514 10:14:57.806133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21516 10:14:57.847883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21517 10:14:57.848319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21519 10:14:57.885960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21520 10:14:57.886378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21522 10:14:57.930878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21524 10:14:57.931362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21525 10:14:57.976333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21526 10:14:57.976767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21528 10:14:58.022364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21529 10:14:58.022781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21531 10:14:58.058410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21532 10:14:58.058843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21534 10:14:58.100278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21536 10:14:58.100761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21537 10:14:58.140582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21538 10:14:58.141003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21540 10:14:58.186595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21541 10:14:58.186987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21543 10:14:58.231750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21544 10:14:58.232144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21546 10:14:58.278463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21548 10:14:58.278877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21549 10:14:58.327677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21550 10:14:58.328078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21552 10:14:58.372136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21553 10:14:58.372558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21555 10:14:58.419115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21556 10:14:58.419506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21558 10:14:58.467366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21559 10:14:58.467717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21561 10:14:58.517651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21563 10:14:58.518115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21564 10:14:58.565502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21565 10:14:58.565956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21567 10:14:58.602847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21568 10:14:58.603366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21570 10:14:58.643828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21572 10:14:58.644455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21573 10:14:58.682612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21575 10:14:58.683087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21576 10:14:58.727725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21578 10:14:58.728358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21579 10:14:58.774397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21580 10:14:58.774836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21582 10:14:58.819696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21583 10:14:58.820105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21585 10:14:58.861908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21587 10:14:58.862362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21588 10:14:58.898213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21590 10:14:58.898976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21591 10:14:58.940150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21593 10:14:58.940775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21594 10:14:58.980539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21595 10:14:58.981084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21597 10:14:59.036351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21598 10:14:59.036809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21600 10:14:59.091478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21601 10:14:59.091979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21603 10:14:59.137790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21605 10:14:59.138245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21606 10:14:59.178408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21607 10:14:59.178920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21609 10:14:59.215731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21610 10:14:59.216173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21612 10:14:59.259033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21613 10:14:59.259450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21615 10:14:59.302760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21616 10:14:59.303158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21618 10:14:59.348530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21619 10:14:59.348926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21621 10:14:59.392465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21623 10:14:59.392860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21624 10:14:59.435690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21625 10:14:59.436191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21627 10:14:59.479657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21628 10:14:59.480077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21630 10:14:59.518383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21631 10:14:59.518927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21633 10:14:59.560074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21634 10:14:59.560625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21636 10:14:59.600858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21638 10:14:59.601270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21639 10:14:59.640096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21640 10:14:59.640619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21642 10:14:59.688968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21644 10:14:59.689412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21645 10:14:59.738895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21646 10:14:59.739322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21648 10:14:59.790551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21649 10:14:59.790965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21651 10:14:59.840680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21653 10:14:59.841414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21654 10:14:59.886219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21655 10:14:59.886628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21657 10:14:59.936389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21659 10:14:59.937086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21660 10:14:59.990971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21661 10:14:59.991418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21663 10:15:00.032782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21664 10:15:00.033171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21666 10:15:00.081482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21667 10:15:00.081909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21669 10:15:00.123969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21670 10:15:00.124521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21672 10:15:00.161953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21673 10:15:00.162400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21675 10:15:00.198253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21676 10:15:00.198702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21678 10:15:00.235199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21679 10:15:00.235624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21681 10:15:00.274371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21682 10:15:00.274795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21684 10:15:00.314895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21685 10:15:00.315466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21687 10:15:00.358441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21689 10:15:00.358861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21690 10:15:00.395559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21692 10:15:00.396032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21693 10:15:00.432450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21695 10:15:00.432918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21696 10:15:00.476342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21698 10:15:00.476734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21699 10:15:00.526630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21700 10:15:00.527064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21702 10:15:00.570305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21703 10:15:00.570685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21705 10:15:00.615903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21706 10:15:00.616327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21708 10:15:00.658335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21709 10:15:00.658753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21711 10:15:00.709460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21712 10:15:00.709923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21714 10:15:00.748481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21715 10:15:00.748872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21717 10:15:00.793859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21718 10:15:00.794285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21720 10:15:00.829420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21721 10:15:00.829869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21723 10:15:00.866242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21724 10:15:00.866624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21726 10:15:00.905483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21727 10:15:00.905917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21729 10:15:00.952134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21730 10:15:00.952558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21732 10:15:00.990955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21733 10:15:00.991379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21735 10:15:01.030106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21736 10:15:01.030559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21738 10:15:01.074371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21739 10:15:01.074808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21741 10:15:01.122628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21743 10:15:01.123055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21744 10:15:01.168224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21745 10:15:01.168758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21747 10:15:01.219647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21748 10:15:01.220149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21750 10:15:01.267348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21752 10:15:01.267812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21753 10:15:01.316014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21754 10:15:01.316439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21756 10:15:01.363917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21757 10:15:01.364334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21759 10:15:01.409010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21761 10:15:01.409480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21762 10:15:01.467198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21763 10:15:01.467646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21765 10:15:01.519993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21766 10:15:01.520461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21768 10:15:01.567531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21770 10:15:01.568030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21771 10:15:01.618255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21772 10:15:01.618713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21774 10:15:01.671690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21775 10:15:01.672112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21777 10:15:01.724005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21779 10:15:01.724482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21780 10:15:01.776778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21782 10:15:01.777257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21783 10:15:01.820877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21785 10:15:01.821347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21786 10:15:01.867006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21787 10:15:01.867434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21789 10:15:01.914069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21790 10:15:01.914502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21792 10:15:01.955928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21793 10:15:01.956395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21795 10:15:01.993445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21797 10:15:01.993895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21798 10:15:02.037002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21800 10:15:02.037489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21801 10:15:02.078237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21802 10:15:02.078665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21804 10:15:02.129106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21806 10:15:02.129600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21807 10:15:02.182749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21809 10:15:02.183216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21810 10:15:02.227146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21811 10:15:02.227579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21813 10:15:02.279235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21815 10:15:02.279689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21816 10:15:02.334852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21817 10:15:02.335285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21819 10:15:02.378718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21821 10:15:02.379211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21822 10:15:02.426056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21823 10:15:02.426489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21825 10:15:02.476825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21827 10:15:02.477266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21828 10:15:02.521571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21829 10:15:02.521999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21831 10:15:02.566555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21832 10:15:02.566975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21834 10:15:02.617532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21835 10:15:02.617965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21837 10:15:02.663366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21838 10:15:02.663803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21840 10:15:02.710837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21841 10:15:02.711306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21843 10:15:02.758830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21845 10:15:02.759310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21846 10:15:02.808548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21847 10:15:02.808981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21849 10:15:02.892698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21850 10:15:02.893130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21852 10:15:02.939238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21853 10:15:02.939689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21855 10:15:02.982144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21856 10:15:02.982591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21858 10:15:03.033961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21859 10:15:03.034545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21861 10:15:03.082636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21862 10:15:03.083026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21864 10:15:03.126800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21865 10:15:03.127246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21867 10:15:03.170114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21868 10:15:03.170567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21870 10:15:03.219394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21871 10:15:03.219836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21873 10:15:03.279664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21874 10:15:03.280149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21876 10:15:03.326402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21877 10:15:03.326868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21879 10:15:03.376124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21880 10:15:03.376574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21882 10:15:03.434446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21883 10:15:03.434847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21885 10:15:03.482509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21887 10:15:03.482983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21888 10:15:03.543339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21889 10:15:03.543778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21891 10:15:03.595903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21892 10:15:03.596343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21894 10:15:03.644406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21895 10:15:03.644835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21897 10:15:03.689912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21898 10:15:03.690327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21900 10:15:03.739701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21902 10:15:03.740161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21903 10:15:03.786928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21904 10:15:03.787327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21906 10:15:03.838371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21907 10:15:03.838774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21909 10:15:03.889998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21910 10:15:03.890458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21912 10:15:03.935988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21914 10:15:03.936437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21915 10:15:03.990878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21916 10:15:03.991317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21918 10:15:04.033123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21920 10:15:04.033537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21921 10:15:04.078940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21922 10:15:04.079435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21924 10:15:04.127891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21925 10:15:04.128378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21927 10:15:04.171332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
21928 10:15:04.171797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
21930 10:15:04.216888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
21932 10:15:04.217533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
21933 10:15:04.271001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
21934 10:15:04.271442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
21936 10:15:04.321700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
21938 10:15:04.322183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
21939 10:15:04.363537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
21940 10:15:04.363980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
21942 10:15:04.410865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
21943 10:15:04.411312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
21945 10:15:04.454709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
21946 10:15:04.455137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
21948 10:15:04.498448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
21949 10:15:04.498885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
21951 10:15:04.546861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
21952 10:15:04.547308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
21954 10:15:04.598184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
21956 10:15:04.598644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
21957 10:15:04.660431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
21958 10:15:04.660865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
21960 10:15:04.708355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
21961 10:15:04.708813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
21963 10:15:04.754712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
21964 10:15:04.755156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
21966 10:15:04.805116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
21968 10:15:04.805742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
21969 10:15:04.850576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
21971 10:15:04.851047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
21972 10:15:04.888901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
21974 10:15:04.889322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
21975 10:15:04.929829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
21977 10:15:04.930279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
21978 10:15:04.972408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
21980 10:15:04.973132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
21981 10:15:05.014708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
21982 10:15:05.015108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
21984 10:15:05.063718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
21985 10:15:05.064181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
21987 10:15:05.110958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
21988 10:15:05.111468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
21990 10:15:05.157636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
21991 10:15:05.158138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
21993 10:15:05.212294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
21994 10:15:05.212749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
21996 10:15:05.264914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
21998 10:15:05.265728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
21999 10:15:05.315591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
22001 10:15:05.316016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
22002 10:15:05.369896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
22004 10:15:05.370284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
22005 10:15:05.414664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
22006 10:15:05.415071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
22008 10:15:05.458649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
22009 10:15:05.459069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
22011 10:15:05.503682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
22012 10:15:05.504115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
22014 10:15:05.546787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
22015 10:15:05.547193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
22017 10:15:05.582825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
22018 10:15:05.583240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
22020 10:15:05.619860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
22022 10:15:05.620314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
22023 10:15:05.660018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
22024 10:15:05.660432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
22026 10:15:05.704060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
22027 10:15:05.704489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
22029 10:15:05.745572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
22030 10:15:05.746018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
22032 10:15:05.789537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
22034 10:15:05.790076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
22035 10:15:05.825445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
22036 10:15:05.825877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
22038 10:15:05.863157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
22039 10:15:05.863579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
22041 10:15:05.904162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
22042 10:15:05.904563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
22044 10:15:05.954663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
22045 10:15:05.955046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
22047 10:15:05.996298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
22049 10:15:05.996749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
22050 10:15:06.033951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
22051 10:15:06.034399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
22053 10:15:06.078979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
22054 10:15:06.079414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
22056 10:15:06.120264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
22058 10:15:06.120758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
22059 10:15:06.166484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
22060 10:15:06.166908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
22062 10:15:06.204640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
22063 10:15:06.205064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
22065 10:15:06.243632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
22066 10:15:06.244184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
22068 10:15:06.285090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
22070 10:15:06.285503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
22071 10:15:06.319776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
22073 10:15:06.320511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
22074 10:15:06.358023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
22075 10:15:06.358477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
22077 10:15:06.396327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
22078 10:15:06.396737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
22080 10:15:06.433148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
22082 10:15:06.433731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
22083 10:15:06.470661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
22084 10:15:06.471092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
22086 10:15:06.517146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
22088 10:15:06.517714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
22089 10:15:06.556510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
22090 10:15:06.556954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
22092 10:15:06.614749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
22093 10:15:06.615166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
22095 10:15:06.668303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
22096 10:15:06.668675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
22098 10:15:06.717699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
22099 10:15:06.718083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
22101 10:15:06.771728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
22102 10:15:06.772151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
22104 10:15:06.821578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
22105 10:15:06.822041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
22107 10:15:06.858460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
22109 10:15:06.858921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
22110 10:15:06.893913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
22112 10:15:06.894382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
22113 10:15:06.935637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
22115 10:15:06.936134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
22116 10:15:06.980879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
22118 10:15:06.981365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
22119 10:15:07.022568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
22120 10:15:07.023022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
22122 10:15:07.064133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
22124 10:15:07.064568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
22125 10:15:07.103217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
22127 10:15:07.103613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
22128 10:15:07.151303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
22129 10:15:07.151769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
22131 10:15:07.206937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
22133 10:15:07.207422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
22134 10:15:07.258224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
22136 10:15:07.258725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
22137 10:15:07.306932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
22138 10:15:07.307372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
22140 10:15:07.357969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
22141 10:15:07.358386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
22143 10:15:07.394913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
22145 10:15:07.395472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
22146 10:15:07.432351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
22147 10:15:07.432871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
22149 10:15:07.471684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
22150 10:15:07.472190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
22152 10:15:07.510592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
22153 10:15:07.511078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
22155 10:15:07.566653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
22156 10:15:07.567082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
22158 10:15:07.617801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
22159 10:15:07.618233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
22161 10:15:07.654329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
22162 10:15:07.654767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
22164 10:15:07.689771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
22166 10:15:07.690240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
22167 10:15:07.725154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
22168 10:15:07.725594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
22170 10:15:07.762350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22171 10:15:07.762838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
22173 10:15:07.798612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22174 10:15:07.799091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22176 10:15:07.833879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22177 10:15:07.834300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22179 10:15:07.870252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22181 10:15:07.870727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22182 10:15:07.907851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22183 10:15:07.908289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22185 10:15:07.943355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22186 10:15:07.943757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22188 10:15:08.004975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22190 10:15:08.005442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22191 10:15:08.052952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22193 10:15:08.053528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22194 10:15:08.099114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22196 10:15:08.099582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22197 10:15:08.152582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22198 10:15:08.152969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22200 10:15:08.202326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22201 10:15:08.202740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22203 10:15:08.243608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22204 10:15:08.244012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22206 10:15:08.282345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22207 10:15:08.282911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22209 10:15:08.323305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22210 10:15:08.323797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22212 10:15:08.365900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22213 10:15:08.366359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22215 10:15:08.407538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22216 10:15:08.408003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22218 10:15:08.447235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22219 10:15:08.447667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22221 10:15:08.486922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22223 10:15:08.487390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22224 10:15:08.527692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22225 10:15:08.528120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22227 10:15:08.567908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22228 10:15:08.568341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22230 10:15:08.608899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22232 10:15:08.609298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22233 10:15:08.647901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22235 10:15:08.648333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22236 10:15:08.688176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22237 10:15:08.688571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22239 10:15:08.735583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22241 10:15:08.736055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22242 10:15:08.776660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22243 10:15:08.777039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22245 10:15:08.819482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22246 10:15:08.819852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22248 10:15:08.856349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22249 10:15:08.856749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22251 10:15:08.893408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22252 10:15:08.893790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22254 10:15:08.930245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22256 10:15:08.930738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22257 10:15:08.971131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22258 10:15:08.971643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22260 10:15:09.018030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22262 10:15:09.018508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22263 10:15:09.063235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22264 10:15:09.063634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22266 10:15:09.114081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22268 10:15:09.114580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22269 10:15:09.157822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22270 10:15:09.158309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22272 10:15:09.207095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22274 10:15:09.207706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22275 10:15:09.254783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22276 10:15:09.255217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22278 10:15:09.300163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22279 10:15:09.300589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22281 10:15:09.352561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22282 10:15:09.352984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22284 10:15:09.404577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22285 10:15:09.405021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22287 10:15:09.446952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22288 10:15:09.447366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22290 10:15:09.493009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22292 10:15:09.493434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22293 10:15:09.537978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22294 10:15:09.538430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22296 10:15:09.583619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22298 10:15:09.583997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22299 10:15:09.630329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22301 10:15:09.630706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22302 10:15:09.666716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22304 10:15:09.667163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22305 10:15:09.703296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22306 10:15:09.703776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22308 10:15:09.739803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22309 10:15:09.740321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22311 10:15:09.786880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22312 10:15:09.787566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22314 10:15:09.835706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22315 10:15:09.836102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22317 10:15:09.884454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22319 10:15:09.885009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22320 10:15:09.933893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22321 10:15:09.934292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22323 10:15:09.986011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22324 10:15:09.986422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22326 10:15:10.037702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22327 10:15:10.038093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22329 10:15:10.088282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22330 10:15:10.088695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22332 10:15:10.141311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22333 10:15:10.141782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22335 10:15:10.186473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22336 10:15:10.186908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22338 10:15:10.238734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22339 10:15:10.239082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22341 10:15:10.283267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22342 10:15:10.283828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22344 10:15:10.331933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22345 10:15:10.332350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22347 10:15:10.373335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22348 10:15:10.373776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22350 10:15:10.421952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22351 10:15:10.422381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22353 10:15:10.463900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22354 10:15:10.464369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22356 10:15:10.500260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22357 10:15:10.500742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22359 10:15:10.538245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22360 10:15:10.538684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22362 10:15:10.579975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22364 10:15:10.580428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22365 10:15:10.622684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22366 10:15:10.623078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22368 10:15:10.666548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22370 10:15:10.667018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22371 10:15:10.714891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22372 10:15:10.715270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22374 10:15:10.763802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22375 10:15:10.764201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22377 10:15:10.805574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22378 10:15:10.805980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22380 10:15:10.847169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22381 10:15:10.847567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22383 10:15:10.890705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22384 10:15:10.891136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22386 10:15:10.931520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22388 10:15:10.931952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22389 10:15:10.971137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22390 10:15:10.971554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22392 10:15:11.015715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22393 10:15:11.016120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22395 10:15:11.056595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22396 10:15:11.057067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22398 10:15:11.093146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22400 10:15:11.093621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22401 10:15:11.133577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22403 10:15:11.134066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22404 10:15:11.170719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22405 10:15:11.171096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22407 10:15:11.207003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22408 10:15:11.207454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22410 10:15:11.245526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22412 10:15:11.246030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22413 10:15:11.286717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22414 10:15:11.287207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22416 10:15:11.323648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22417 10:15:11.324068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22419 10:15:11.364047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22421 10:15:11.364719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22422 10:15:11.412375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22423 10:15:11.412780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22425 10:15:11.450914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22426 10:15:11.451369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22428 10:15:11.489875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22429 10:15:11.490296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22431 10:15:11.536860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22432 10:15:11.537283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22434 10:15:11.576893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22436 10:15:11.577389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22437 10:15:11.627145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22438 10:15:11.627554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22440 10:15:11.683732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22441 10:15:11.684202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22443 10:15:11.726684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22444 10:15:11.727065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22446 10:15:11.783731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22447 10:15:11.784105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22449 10:15:11.841187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22451 10:15:11.841937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22452 10:15:11.895972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22454 10:15:11.896731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22455 10:15:11.942159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22456 10:15:11.942618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22458 10:15:11.982601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22460 10:15:11.983055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22461 10:15:12.022090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22462 10:15:12.022566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22464 10:15:12.061587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22466 10:15:12.062213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22467 10:15:12.099330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22469 10:15:12.099812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22470 10:15:12.135303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22471 10:15:12.135837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22473 10:15:12.171288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22474 10:15:12.171696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22476 10:15:12.207982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22477 10:15:12.208423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22479 10:15:12.246937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22480 10:15:12.247357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22482 10:15:12.285348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22483 10:15:12.285859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22485 10:15:12.323508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22486 10:15:12.323927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22488 10:15:12.375296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22490 10:15:12.375997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22491 10:15:12.427546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22492 10:15:12.427990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22494 10:15:12.472528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22495 10:15:12.472993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22497 10:15:12.518177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22499 10:15:12.518594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22500 10:15:12.560096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22501 10:15:12.560521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22503 10:15:12.604530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22504 10:15:12.604964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22506 10:15:12.649890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22508 10:15:12.650357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22509 10:15:12.691598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22510 10:15:12.692019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22512 10:15:12.733086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22514 10:15:12.733559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22515 10:15:12.772543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22516 10:15:12.773057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22518 10:15:12.815896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22519 10:15:12.816296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22521 10:15:12.862951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22522 10:15:12.863361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22524 10:15:12.907971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22525 10:15:12.908502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22527 10:15:12.949152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22529 10:15:12.949689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22530 10:15:12.986758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22531 10:15:12.987195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22533 10:15:13.029571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22534 10:15:13.030010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22536 10:15:13.102881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22537 10:15:13.103297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22539 10:15:13.154475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22540 10:15:13.154931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22542 10:15:13.203993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22543 10:15:13.204430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22545 10:15:13.246730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22546 10:15:13.247303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22548 10:15:13.296703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22549 10:15:13.297162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22551 10:15:13.346693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22552 10:15:13.347077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22554 10:15:13.402282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22555 10:15:13.402680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22557 10:15:13.439785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22558 10:15:13.440210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22560 10:15:13.473961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22562 10:15:13.474546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22563 10:15:13.508207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22565 10:15:13.508850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22566 10:15:13.542269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22567 10:15:13.542744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22569 10:15:13.578861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22570 10:15:13.579278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22572 10:15:13.614842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22574 10:15:13.615293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22575 10:15:13.650438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22576 10:15:13.650819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22578 10:15:13.692638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22580 10:15:13.693223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22581 10:15:13.731351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22582 10:15:13.731783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22584 10:15:13.774271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22585 10:15:13.774692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22587 10:15:13.810362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22588 10:15:13.810843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22590 10:15:13.848443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22591 10:15:13.849000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22593 10:15:13.888610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22595 10:15:13.889020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22596 10:15:13.926955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22597 10:15:13.927373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22599 10:15:13.960763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22601 10:15:13.961212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22602 10:15:13.994825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22603 10:15:13.995228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22605 10:15:14.028667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22606 10:15:14.029075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22608 10:15:14.074566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22609 10:15:14.074979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22611 10:15:14.110849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22612 10:15:14.111321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22614 10:15:14.146871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22615 10:15:14.147278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22617 10:15:14.194466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22618 10:15:14.194848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22620 10:15:14.240277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22621 10:15:14.240728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22623 10:15:14.274518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22624 10:15:14.274964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22626 10:15:14.320852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22628 10:15:14.321485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22629 10:15:14.368314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22630 10:15:14.368778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22632 10:15:14.414419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22634 10:15:14.414989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22635 10:15:14.446437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22636 10:15:14.446930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22638 10:15:14.479136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22640 10:15:14.479581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22641 10:15:14.513122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22643 10:15:14.513543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22644 10:15:14.548982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22646 10:15:14.549644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22647 10:15:14.583624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22648 10:15:14.584030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22650 10:15:14.618065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22651 10:15:14.618543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22653 10:15:14.652110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22654 10:15:14.652571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22656 10:15:14.686289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22657 10:15:14.686806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22659 10:15:14.720601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22660 10:15:14.721028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22662 10:15:14.755453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22664 10:15:14.756202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22665 10:15:14.789936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22667 10:15:14.790580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22668 10:15:14.828812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22670 10:15:14.829499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22671 10:15:14.867324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22672 10:15:14.867870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22674 10:15:14.904058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22676 10:15:14.904507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22677 10:15:14.938728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22678 10:15:14.939143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22680 10:15:14.974123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22681 10:15:14.974531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22683 10:15:15.010327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22684 10:15:15.010820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22686 10:15:15.042330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22687 10:15:15.042816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22689 10:15:15.076120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22690 10:15:15.076539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22692 10:15:15.110303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22694 10:15:15.110904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22695 10:15:15.144083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22697 10:15:15.144543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22698 10:15:15.179015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22699 10:15:15.179431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22701 10:15:15.219278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22702 10:15:15.219749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22704 10:15:15.257595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22706 10:15:15.257982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22707 10:15:15.289680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22708 10:15:15.290073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22710 10:15:15.326021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22711 10:15:15.326567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22713 10:15:15.362182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22714 10:15:15.362607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22716 10:15:15.396159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22718 10:15:15.396609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22719 10:15:15.430384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22721 10:15:15.430847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22722 10:15:15.466919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22723 10:15:15.467409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22725 10:15:15.517987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22726 10:15:15.518423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22728 10:15:15.551984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22729 10:15:15.552547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22731 10:15:15.585963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22732 10:15:15.586515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22734 10:15:15.623996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22735 10:15:15.624536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22737 10:15:15.660744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22739 10:15:15.661127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22740 10:15:15.694530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22742 10:15:15.695071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22743 10:15:15.730006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22745 10:15:15.730619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22746 10:15:15.765087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22748 10:15:15.765669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22749 10:15:15.798758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22750 10:15:15.799132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22752 10:15:15.831150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22754 10:15:15.831784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22755 10:15:15.862954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22756 10:15:15.863414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22758 10:15:15.895867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22760 10:15:15.896438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22761 10:15:15.929678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22763 10:15:15.930139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22764 10:15:15.965073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22766 10:15:15.965827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22767 10:15:15.998697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22768 10:15:15.999235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22770 10:15:16.032128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22771 10:15:16.032550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22773 10:15:16.066283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22774 10:15:16.066690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22776 10:15:16.100745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22778 10:15:16.101212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22779 10:15:16.135724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22781 10:15:16.136377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22782 10:15:16.174797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22783 10:15:16.175294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22785 10:15:16.215070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22786 10:15:16.215513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22788 10:15:16.256143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22789 10:15:16.256686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22791 10:15:16.298884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22793 10:15:16.299345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22794 10:15:16.336890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22796 10:15:16.337556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22797 10:15:16.375177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22798 10:15:16.375590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22800 10:15:16.416733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22802 10:15:16.417374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22803 10:15:16.459877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22804 10:15:16.460358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22806 10:15:16.504367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22807 10:15:16.504870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22809 10:15:16.551229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22811 10:15:16.551707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22812 10:15:16.595332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22813 10:15:16.595733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22815 10:15:16.637631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22817 10:15:16.638006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22818 10:15:16.679109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22819 10:15:16.679661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22821 10:15:16.721784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22822 10:15:16.722231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22824 10:15:16.770063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22826 10:15:16.770709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22827 10:15:16.812821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22828 10:15:16.813224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22830 10:15:16.854520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22832 10:15:16.855162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22833 10:15:16.898100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22835 10:15:16.898723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22836 10:15:16.939930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22837 10:15:16.940403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22839 10:15:16.982266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22840 10:15:16.982723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22842 10:15:17.025414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22843 10:15:17.025831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22845 10:15:17.063416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22846 10:15:17.063869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22848 10:15:17.098337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22849 10:15:17.098808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22851 10:15:17.139790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22852 10:15:17.140261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22854 10:15:17.182533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22855 10:15:17.182911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22857 10:15:17.222678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22858 10:15:17.223188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22860 10:15:17.264480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22861 10:15:17.265040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22863 10:15:17.306377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22864 10:15:17.306900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22866 10:15:17.346280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22867 10:15:17.346825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22869 10:15:17.385465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22870 10:15:17.385945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22872 10:15:17.429913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22874 10:15:17.430332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22875 10:15:17.475673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22876 10:15:17.476071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22878 10:15:17.518159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22879 10:15:17.518568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22881 10:15:17.553893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22882 10:15:17.554313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22884 10:15:17.603013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22885 10:15:17.603384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22887 10:15:17.650575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22888 10:15:17.651065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22890 10:15:17.705206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22892 10:15:17.706040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22893 10:15:17.757548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22895 10:15:17.758312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22896 10:15:17.793474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22898 10:15:17.794086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22899 10:15:17.830371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22901 10:15:17.831105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22902 10:15:17.866930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22903 10:15:17.867481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22905 10:15:17.901032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22907 10:15:17.901704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22908 10:15:17.936044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22909 10:15:17.936612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22911 10:15:17.971129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22912 10:15:17.971602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22914 10:15:18.007280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22916 10:15:18.007983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22917 10:15:18.047030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22918 10:15:18.047419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22920 10:15:18.081238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22922 10:15:18.081770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22923 10:15:18.117011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22925 10:15:18.117463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22926 10:15:18.156145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22927 10:15:18.156638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
22929 10:15:18.220420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
22930 10:15:18.220810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
22932 10:15:18.259837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
22933 10:15:18.260201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
22935 10:15:18.299744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
22937 10:15:18.300316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
22938 10:15:18.334476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
22939 10:15:18.334963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
22941 10:15:18.375284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
22943 10:15:18.375902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
22944 10:15:18.418317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
22946 10:15:18.418892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
22947 10:15:18.459381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
22948 10:15:18.459756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
22950 10:15:18.502724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
22951 10:15:18.503142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
22953 10:15:18.543563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
22954 10:15:18.544017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
22956 10:15:18.593779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
22957 10:15:18.594202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
22959 10:15:18.627820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
22961 10:15:18.628491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
22962 10:15:18.663783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
22964 10:15:18.664228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
22965 10:15:18.701827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
22966 10:15:18.702310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
22968 10:15:18.746975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
22969 10:15:18.747452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
22971 10:15:18.791041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
22972 10:15:18.791583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
22974 10:15:18.835702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
22975 10:15:18.836235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
22977 10:15:18.874807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
22978 10:15:18.875261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
22980 10:15:18.916471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
22981 10:15:18.916968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
22983 10:15:18.956423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
22984 10:15:18.956856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
22986 10:15:18.991981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
22988 10:15:18.992556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
22989 10:15:19.026312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
22990 10:15:19.026748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
22992 10:15:19.065944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
22994 10:15:19.066364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
22995 10:15:19.101048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
22997 10:15:19.101423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
22998 10:15:19.137590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
22999 10:15:19.138164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
23001 10:15:19.180062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
23002 10:15:19.180448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
23004 10:15:19.219083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
23005 10:15:19.219467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
23007 10:15:19.254341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
23009 10:15:19.254852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
23010 10:15:19.289377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
23011 10:15:19.289853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
23013 10:15:19.325327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
23014 10:15:19.325738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
23016 10:15:19.360910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
23018 10:15:19.361300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
23019 10:15:19.397015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
23021 10:15:19.397725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
23022 10:15:19.434876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
23023 10:15:19.435244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
23025 10:15:19.474917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
23026 10:15:19.475447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
23028 10:15:19.511447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
23029 10:15:19.511958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
23031 10:15:19.548136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
23032 10:15:19.548556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
23034 10:15:19.586080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
23036 10:15:19.586810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
23037 10:15:19.626971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
23038 10:15:19.627463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
23040 10:15:19.667139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
23041 10:15:19.667648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
23043 10:15:19.707084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
23044 10:15:19.707594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
23046 10:15:19.747361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
23047 10:15:19.747882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
23049 10:15:19.783576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
23050 10:15:19.783974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
23052 10:15:19.819901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
23053 10:15:19.820332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
23055 10:15:19.856587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
23056 10:15:19.857034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
23058 10:15:19.893696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
23059 10:15:19.894125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
23061 10:15:19.937690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
23062 10:15:19.938145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
23064 10:15:19.985045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
23066 10:15:19.985511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
23067 10:15:20.028356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
23069 10:15:20.028827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
23070 10:15:20.072147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
23071 10:15:20.072587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
23073 10:15:20.113888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
23074 10:15:20.114311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
23076 10:15:20.156296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
23077 10:15:20.156655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
23079 10:15:20.196325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
23080 10:15:20.196710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
23082 10:15:20.232432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
23083 10:15:20.232911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
23085 10:15:20.269031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
23087 10:15:20.269663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
23088 10:15:20.304232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
23089 10:15:20.304758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
23091 10:15:20.339297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
23092 10:15:20.339717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
23094 10:15:20.375955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
23095 10:15:20.376375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
23097 10:15:20.410955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
23099 10:15:20.411581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
23100 10:15:20.446092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
23102 10:15:20.446793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
23103 10:15:20.482184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
23104 10:15:20.482586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
23106 10:15:20.520989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
23108 10:15:20.521407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
23109 10:15:20.560819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
23111 10:15:20.561262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
23112 10:15:20.602085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
23113 10:15:20.602492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
23115 10:15:20.646363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
23116 10:15:20.646761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
23118 10:15:20.683076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
23119 10:15:20.683500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
23121 10:15:20.725544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
23122 10:15:20.725929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
23124 10:15:20.767488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
23126 10:15:20.767856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
23127 10:15:20.812302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
23128 10:15:20.812725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
23130 10:15:20.846068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
23131 10:15:20.846482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
23133 10:15:20.878523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
23134 10:15:20.878932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
23136 10:15:20.910359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
23138 10:15:20.910997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
23139 10:15:20.944488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
23140 10:15:20.945017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
23142 10:15:20.980369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
23144 10:15:20.981117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
23145 10:15:21.016094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
23146 10:15:21.016555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
23148 10:15:21.058393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
23150 10:15:21.059131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
23151 10:15:21.098984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
23152 10:15:21.099479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
23154 10:15:21.143633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
23155 10:15:21.144100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
23157 10:15:21.181489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
23158 10:15:21.181910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
23160 10:15:21.216090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
23162 10:15:21.216546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
23163 10:15:21.250663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
23164 10:15:21.251073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
23166 10:15:21.287177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
23167 10:15:21.287614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
23169 10:15:21.328100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
23170 10:15:21.328531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
23172 10:15:21.368362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23174 10:15:21.368994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23175 10:15:21.411521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23176 10:15:21.412042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23178 10:15:21.447005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23179 10:15:21.447516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23181 10:15:21.481712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23183 10:15:21.482164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23184 10:15:21.518971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23185 10:15:21.519458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23187 10:15:21.555081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23189 10:15:21.555493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23190 10:15:21.591405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23192 10:15:21.591861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23193 10:15:21.626378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23195 10:15:21.626828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23196 10:15:21.661534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23197 10:15:21.661982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23199 10:15:21.697158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23201 10:15:21.697560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23202 10:15:21.745763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23203 10:15:21.746173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23205 10:15:21.793543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23207 10:15:21.794013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23208 10:15:21.828948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23210 10:15:21.829412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23211 10:15:21.864512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23213 10:15:21.864988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23214 10:15:21.900427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23215 10:15:21.900835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23217 10:15:21.938778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23218 10:15:21.939202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23220 10:15:21.975145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23222 10:15:21.975604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23223 10:15:22.008979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23225 10:15:22.009549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23226 10:15:22.043953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23227 10:15:22.044503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23229 10:15:22.080375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23230 10:15:22.080800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23232 10:15:22.118189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23233 10:15:22.118607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23235 10:15:22.153392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23237 10:15:22.153856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23238 10:15:22.187774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23240 10:15:22.188227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23241 10:15:22.233380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23242 10:15:22.233943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23244 10:15:22.275392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23245 10:15:22.275882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23247 10:15:22.310753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23248 10:15:22.311140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23250 10:15:22.346483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23252 10:15:22.347062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23253 10:15:22.394106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23254 10:15:22.394619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23256 10:15:22.430419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23258 10:15:22.430843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23259 10:15:22.466390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23260 10:15:22.466773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23262 10:15:22.502034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23263 10:15:22.502413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23265 10:15:22.538050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23267 10:15:22.538714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23268 10:15:22.574551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23269 10:15:22.574952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23271 10:15:22.629733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23272 10:15:22.630240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23274 10:15:22.684403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23275 10:15:22.684961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23277 10:15:22.739619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23278 10:15:22.740048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23280 10:15:22.779255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23281 10:15:22.779672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23283 10:15:22.815253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23284 10:15:22.815669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23286 10:15:22.852178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23287 10:15:22.852606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23289 10:15:22.890079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23290 10:15:22.890513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23292 10:15:22.931066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23293 10:15:22.931504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23295 10:15:22.973656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23297 10:15:22.974116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23298 10:15:23.010810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23300 10:15:23.011183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23301 10:15:23.047822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23303 10:15:23.048371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23304 10:15:23.084180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23305 10:15:23.084694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23307 10:15:23.134560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23309 10:15:23.135097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23310 10:15:23.183214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23311 10:15:23.183670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23313 10:15:23.231987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23314 10:15:23.232534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23316 10:15:23.273750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23317 10:15:23.274229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23319 10:15:23.331238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23320 10:15:23.331707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23322 10:15:23.389044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23324 10:15:23.389883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23325 10:15:23.431501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23326 10:15:23.431888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23328 10:15:23.486452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23329 10:15:23.486824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23331 10:15:23.540312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23332 10:15:23.540702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23334 10:15:23.583336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23335 10:15:23.583707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23337 10:15:23.624645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23338 10:15:23.625052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23340 10:15:23.676049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23342 10:15:23.676433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23343 10:15:23.724312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23344 10:15:23.724689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23346 10:15:23.766416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23348 10:15:23.766706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23349 10:15:23.814150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23350 10:15:23.814513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23352 10:15:23.860278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23353 10:15:23.860801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23355 10:15:23.896202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23357 10:15:23.896838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23358 10:15:23.931315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23359 10:15:23.931750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23361 10:15:23.972493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23363 10:15:23.973045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23364 10:15:24.029701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23366 10:15:24.030409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23367 10:15:24.083835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23368 10:15:24.084266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23370 10:15:24.138689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23372 10:15:24.139332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23373 10:15:24.194747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23374 10:15:24.195180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23376 10:15:24.239498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23378 10:15:24.240120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23379 10:15:24.285611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23380 10:15:24.286150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23382 10:15:24.327607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23383 10:15:24.328094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23385 10:15:24.362885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23386 10:15:24.363388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23388 10:15:24.397705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23389 10:15:24.398064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23391 10:15:24.433728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23392 10:15:24.434130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23394 10:15:24.470473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23396 10:15:24.470955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23397 10:15:24.508119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23398 10:15:24.508524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23400 10:15:24.543935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23401 10:15:24.544304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23403 10:15:24.579844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23405 10:15:24.580185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23406 10:15:24.620876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23408 10:15:24.621569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23409 10:15:24.659486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23410 10:15:24.659874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23412 10:15:24.700681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23414 10:15:24.701144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23415 10:15:24.743021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23416 10:15:24.743409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23418 10:15:24.784709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23420 10:15:24.785084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23421 10:15:24.827576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23423 10:15:24.828165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23424 10:15:24.866698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23425 10:15:24.867191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23427 10:15:24.903439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23428 10:15:24.904002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23430 10:15:24.940386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23431 10:15:24.940945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23433 10:15:24.976775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23435 10:15:24.977247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23436 10:15:25.011313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23437 10:15:25.011758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23439 10:15:25.047170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23440 10:15:25.047734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23442 10:15:25.083366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23443 10:15:25.083778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23445 10:15:25.119968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23447 10:15:25.120555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23448 10:15:25.157602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23450 10:15:25.158078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23451 10:15:25.198842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23452 10:15:25.199328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23454 10:15:25.239379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23456 10:15:25.239855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23457 10:15:25.276213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23458 10:15:25.276617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23460 10:15:25.314506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23461 10:15:25.314879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23463 10:15:25.367863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23464 10:15:25.368328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23466 10:15:25.410556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23467 10:15:25.411046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23469 10:15:25.451827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23471 10:15:25.452459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23472 10:15:25.489289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23473 10:15:25.489797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23475 10:15:25.534051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23476 10:15:25.534491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23478 10:15:25.580922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23480 10:15:25.581568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23481 10:15:25.627770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23482 10:15:25.628292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23484 10:15:25.668602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23485 10:15:25.669048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23487 10:15:25.709378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23488 10:15:25.709801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23490 10:15:25.761685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23491 10:15:25.762175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23493 10:15:25.818424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23494 10:15:25.818829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23496 10:15:25.859303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23498 10:15:25.859718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23499 10:15:25.894846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23500 10:15:25.895264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23502 10:15:25.930667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23503 10:15:25.931009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23505 10:15:25.979185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23506 10:15:25.979607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23508 10:15:26.026432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23509 10:15:26.026988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23511 10:15:26.075620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23512 10:15:26.076186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23514 10:15:26.122841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23515 10:15:26.123266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23517 10:15:26.157903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23518 10:15:26.158359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23520 10:15:26.191262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23522 10:15:26.191724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23523 10:15:26.226227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23524 10:15:26.226628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23526 10:15:26.261475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23527 10:15:26.261902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23529 10:15:26.294636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23531 10:15:26.295242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23532 10:15:26.331575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23533 10:15:26.332064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23535 10:15:26.367866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23537 10:15:26.368463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23538 10:15:26.406414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23539 10:15:26.406853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23541 10:15:26.446248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23542 10:15:26.446671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23544 10:15:26.482325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23545 10:15:26.482741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23547 10:15:26.519201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23549 10:15:26.519653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23550 10:15:26.559259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23551 10:15:26.559673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23553 10:15:26.594268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23554 10:15:26.594669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23556 10:15:26.630030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23558 10:15:26.630398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23559 10:15:26.663957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23560 10:15:26.664463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23562 10:15:26.699932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23563 10:15:26.700301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23565 10:15:26.735449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23566 10:15:26.735885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23568 10:15:26.769363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23569 10:15:26.769883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23571 10:15:26.807181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23572 10:15:26.807687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23574 10:15:26.846058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23575 10:15:26.846601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23577 10:15:26.883167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23578 10:15:26.883641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23580 10:15:26.921149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23582 10:15:26.921742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23583 10:15:26.957667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23584 10:15:26.958149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23586 10:15:26.995902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23587 10:15:26.996379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23589 10:15:27.033505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23591 10:15:27.034103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23592 10:15:27.070916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23594 10:15:27.071367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23595 10:15:27.109975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23596 10:15:27.110523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23598 10:15:27.149854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23600 10:15:27.150521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23601 10:15:27.190809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23602 10:15:27.191287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23604 10:15:27.230525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23605 10:15:27.230939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23607 10:15:27.269707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23609 10:15:27.270288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23610 10:15:27.308478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23611 10:15:27.308946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23613 10:15:27.350611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23614 10:15:27.351095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23616 10:15:27.394650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23618 10:15:27.395108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23619 10:15:27.437058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23621 10:15:27.437500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23622 10:15:27.477604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23623 10:15:27.478047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23625 10:15:27.522917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23626 10:15:27.523453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23628 10:15:27.564105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23629 10:15:27.564587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23631 10:15:27.605469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23632 10:15:27.605890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23634 10:15:27.648292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23636 10:15:27.648770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23637 10:15:27.686190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23638 10:15:27.686706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23640 10:15:27.731119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23641 10:15:27.731608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23643 10:15:27.766323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23645 10:15:27.766903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23646 10:15:27.803431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23647 10:15:27.803858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23649 10:15:27.843064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23650 10:15:27.843439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23652 10:15:27.879193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23653 10:15:27.879578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23655 10:15:27.914856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23656 10:15:27.915334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23658 10:15:27.954656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23659 10:15:27.955112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23661 10:15:28.000547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23663 10:15:28.000934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23664 10:15:28.044990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23666 10:15:28.045388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23667 10:15:28.085615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23668 10:15:28.085994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23670 10:15:28.127973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23672 10:15:28.128400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23673 10:15:28.166765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23674 10:15:28.167284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23676 10:15:28.203748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23677 10:15:28.204166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23679 10:15:28.241699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23680 10:15:28.242075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23682 10:15:28.280887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23684 10:15:28.281373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23685 10:15:28.317159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23687 10:15:28.317594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23688 10:15:28.353657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23690 10:15:28.354074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23691 10:15:28.389037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23693 10:15:28.389400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23694 10:15:28.426172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23695 10:15:28.426676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23697 10:15:28.482025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23698 10:15:28.482513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23700 10:15:28.535542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23701 10:15:28.536052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23703 10:15:28.588454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23704 10:15:28.588977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23706 10:15:28.623136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23707 10:15:28.623644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23709 10:15:28.659557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23710 10:15:28.660001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23712 10:15:28.698021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23714 10:15:28.698759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23715 10:15:28.746136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23717 10:15:28.746635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23718 10:15:28.793895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23719 10:15:28.794340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23721 10:15:28.828953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23723 10:15:28.829342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23724 10:15:28.874669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23725 10:15:28.875112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23727 10:15:28.908656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23729 10:15:28.909242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23730 10:15:28.953683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23732 10:15:28.954342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23733 10:15:28.993855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23734 10:15:28.994262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23736 10:15:29.038105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23738 10:15:29.038805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23739 10:15:29.079168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23740 10:15:29.079554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23742 10:15:29.125896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23743 10:15:29.126455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23745 10:15:29.175827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23746 10:15:29.176307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23748 10:15:29.230345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23750 10:15:29.230803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23751 10:15:29.271158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23752 10:15:29.271555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23754 10:15:29.317542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23755 10:15:29.317974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23757 10:15:29.360659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23758 10:15:29.361151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23760 10:15:29.414883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23762 10:15:29.415354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23763 10:15:29.465992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23764 10:15:29.466399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23766 10:15:29.505502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23767 10:15:29.506009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23769 10:15:29.543478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23771 10:15:29.543939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23772 10:15:29.581592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23773 10:15:29.582017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23775 10:15:29.617783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23777 10:15:29.618235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23778 10:15:29.655808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23780 10:15:29.656178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23781 10:15:29.691789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23782 10:15:29.692206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23784 10:15:29.737382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23786 10:15:29.738296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23787 10:15:29.791554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23788 10:15:29.792030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23790 10:15:29.834638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23791 10:15:29.835073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23793 10:15:29.868892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23795 10:15:29.869255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23796 10:15:29.904015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23797 10:15:29.904504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23799 10:15:29.938502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23800 10:15:29.938927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23802 10:15:29.974009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23803 10:15:29.974411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23805 10:15:30.009194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23807 10:15:30.009878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23808 10:15:30.045595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23809 10:15:30.046024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23811 10:15:30.081605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23813 10:15:30.082075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23814 10:15:30.117625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23815 10:15:30.118059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23817 10:15:30.161752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23818 10:15:30.162147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23820 10:15:30.204551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23821 10:15:30.205027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23823 10:15:30.248564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23824 10:15:30.248990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23826 10:15:30.292336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23827 10:15:30.292765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23829 10:15:30.339032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23830 10:15:30.339515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23832 10:15:30.378963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23834 10:15:30.379548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23835 10:15:30.418826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23837 10:15:30.419333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23838 10:15:30.455737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23839 10:15:30.456194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23841 10:15:30.495884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23842 10:15:30.496343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23844 10:15:30.531557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23845 10:15:30.532037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23847 10:15:30.567184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23848 10:15:30.567630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23850 10:15:30.602358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23851 10:15:30.602890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23853 10:15:30.638493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23855 10:15:30.638820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23856 10:15:30.687719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23857 10:15:30.688184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23859 10:15:30.738047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23860 10:15:30.738603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23862 10:15:30.788563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23864 10:15:30.789186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23865 10:15:30.838840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23866 10:15:30.839401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23868 10:15:30.890240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23869 10:15:30.890784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23871 10:15:30.941167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23873 10:15:30.941764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23874 10:15:30.989841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23875 10:15:30.990324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23877 10:15:31.039232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23879 10:15:31.039818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23880 10:15:31.085675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23881 10:15:31.086167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23883 10:15:31.123448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23884 10:15:31.123934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23886 10:15:31.158455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23887 10:15:31.158891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23889 10:15:31.200597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23890 10:15:31.201169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23892 10:15:31.239807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23893 10:15:31.240252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23895 10:15:31.277389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23896 10:15:31.277802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23898 10:15:31.322499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23899 10:15:31.322936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23901 10:15:31.368445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23902 10:15:31.368801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23904 10:15:31.413967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23906 10:15:31.414530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23907 10:15:31.459444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23908 10:15:31.460016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23910 10:15:31.499908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23911 10:15:31.500309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23913 10:15:31.537889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23914 10:15:31.538394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23916 10:15:31.573937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23917 10:15:31.574418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23919 10:15:31.612687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23920 10:15:31.613083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23922 10:15:31.647852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23924 10:15:31.648574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23925 10:15:31.687800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23926 10:15:31.688250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
23928 10:15:31.726492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
23930 10:15:31.727079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
23931 10:15:31.772613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
23932 10:15:31.773060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
23934 10:15:31.814111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
23936 10:15:31.814571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
23937 10:15:31.849368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
23938 10:15:31.849901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
23940 10:15:31.885741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
23941 10:15:31.886270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
23943 10:15:31.932641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
23945 10:15:31.933119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
23946 10:15:31.980791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
23948 10:15:31.981251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
23949 10:15:32.026943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
23950 10:15:32.027420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
23952 10:15:32.074037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
23953 10:15:32.074468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
23955 10:15:32.113337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
23956 10:15:32.113687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
23958 10:15:32.148742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
23959 10:15:32.149168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
23961 10:15:32.189005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
23963 10:15:32.189456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
23964 10:15:32.229482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
23966 10:15:32.229940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
23967 10:15:32.270882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
23969 10:15:32.271633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
23970 10:15:32.311008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
23971 10:15:32.311547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
23973 10:15:32.351191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
23974 10:15:32.351610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
23976 10:15:32.389791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
23978 10:15:32.390358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
23979 10:15:32.431469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
23981 10:15:32.431934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
23982 10:15:32.478700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
23983 10:15:32.479146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
23985 10:15:32.526659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
23986 10:15:32.527230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
23988 10:15:32.571092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
23990 10:15:32.571532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
23991 10:15:32.614320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
23992 10:15:32.614744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
23994 10:15:32.657571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
23995 10:15:32.657985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
23997 10:15:32.700494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
23999 10:15:32.700868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
24000 10:15:32.742029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
24002 10:15:32.742695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
24003 10:15:32.783686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
24005 10:15:32.784437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
24006 10:15:32.826582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
24007 10:15:32.827018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
24009 10:15:32.861925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
24010 10:15:32.862374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
24012 10:15:32.898331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
24013 10:15:32.898868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
24015 10:15:32.933392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
24016 10:15:32.933815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
24018 10:15:32.978194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
24019 10:15:32.978603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
24021 10:15:33.024183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
24022 10:15:33.024667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
24024 10:15:33.060534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
24025 10:15:33.060936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
24027 10:15:33.103953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
24029 10:15:33.104589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
24030 10:15:33.148032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
24032 10:15:33.148747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
24033 10:15:33.193692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
24034 10:15:33.194122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
24036 10:15:33.242313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
24037 10:15:33.242734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
24039 10:15:33.287166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
24040 10:15:33.287621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
24042 10:15:33.328718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
24044 10:15:33.329392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
24045 10:15:33.370399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
24046 10:15:33.370793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
24048 10:15:33.407495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
24049 10:15:33.408030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
24051 10:15:33.442629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
24052 10:15:33.443059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
24054 10:15:33.479888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
24055 10:15:33.480426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
24057 10:15:33.516307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
24058 10:15:33.516807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
24060 10:15:33.583111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
24061 10:15:33.583561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
24063 10:15:33.621991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
24064 10:15:33.622455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
24066 10:15:33.656741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
24067 10:15:33.657176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
24069 10:15:33.702027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
24070 10:15:33.702452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
24072 10:15:33.738642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
24073 10:15:33.739068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
24075 10:15:33.774374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
24076 10:15:33.774866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
24078 10:15:33.820342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
24079 10:15:33.820729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
24081 10:15:33.858294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
24082 10:15:33.858794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
24084 10:15:33.900047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
24085 10:15:33.900598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
24087 10:15:33.938473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
24088 10:15:33.938952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
24090 10:15:33.979475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
24092 10:15:33.980005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
24093 10:15:34.018176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
24094 10:15:34.018563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
24096 10:15:34.055330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
24097 10:15:34.055747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
24099 10:15:34.092440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
24100 10:15:34.092859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
24102 10:15:34.127763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
24103 10:15:34.128166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
24105 10:15:34.164375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
24106 10:15:34.164813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
24108 10:15:34.208161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
24109 10:15:34.208665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
24111 10:15:34.246516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
24112 10:15:34.246941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
24114 10:15:34.282866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
24115 10:15:34.283249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
24117 10:15:34.317973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
24118 10:15:34.318362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
24120 10:15:34.352259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
24121 10:15:34.352711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
24123 10:15:34.388270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
24124 10:15:34.388703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
24126 10:15:34.424167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
24127 10:15:34.424590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
24129 10:15:34.460900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
24131 10:15:34.461366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
24132 10:15:34.498335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
24133 10:15:34.498691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
24135 10:15:34.534960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
24137 10:15:34.535608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
24138 10:15:34.573737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
24140 10:15:34.574481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
24141 10:15:34.609983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
24142 10:15:34.610502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
24144 10:15:34.648206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
24145 10:15:34.648643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
24147 10:15:34.687614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
24148 10:15:34.687998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
24150 10:15:34.724518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
24151 10:15:34.724982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
24153 10:15:34.762131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
24155 10:15:34.762576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
24156 10:15:34.798515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
24158 10:15:34.798951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
24159 10:15:34.839524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
24161 10:15:34.839856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
24162 10:15:34.882211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
24163 10:15:34.882655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
24165 10:15:34.917865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
24167 10:15:34.918616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
24168 10:15:34.953537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
24170 10:15:34.954176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
24171 10:15:34.995090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
24172 10:15:34.995516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24174 10:15:35.039515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24175 10:15:35.039902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24177 10:15:35.081010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24179 10:15:35.081453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24180 10:15:35.119411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24182 10:15:35.120017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24183 10:15:35.159991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24184 10:15:35.160521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24186 10:15:35.209581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24188 10:15:35.210111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24189 10:15:35.252081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24191 10:15:35.252549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24192 10:15:35.287530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24194 10:15:35.287956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24195 10:15:35.323846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24197 10:15:35.324318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24198 10:15:35.359773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24199 10:15:35.360152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24201 10:15:35.396050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24202 10:15:35.396526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24204 10:15:35.442537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24205 10:15:35.442996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24207 10:15:35.479545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24209 10:15:35.479976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24210 10:15:35.516012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24211 10:15:35.516385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24213 10:15:35.551834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24214 10:15:35.552286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24216 10:15:35.592586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24217 10:15:35.593046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24219 10:15:35.634126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24220 10:15:35.634559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24222 10:15:35.674116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24224 10:15:35.674774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24225 10:15:35.717988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24227 10:15:35.718673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24228 10:15:35.763526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24229 10:15:35.763960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24231 10:15:35.809619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24233 10:15:35.810048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24234 10:15:35.853889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24235 10:15:35.854379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24237 10:15:35.892930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24239 10:15:35.893617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24240 10:15:35.935773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24241 10:15:35.936209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24243 10:15:35.971840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24245 10:15:35.972314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24246 10:15:36.012973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24248 10:15:36.013385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24249 10:15:36.062026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24251 10:15:36.062665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24252 10:15:36.106388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24253 10:15:36.106857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24255 10:15:36.154143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24257 10:15:36.154568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24258 10:15:36.202040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24260 10:15:36.202678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24261 10:15:36.247400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24262 10:15:36.247854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24264 10:15:36.288900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24266 10:15:36.289613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24267 10:15:36.324840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24269 10:15:36.325309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24270 10:15:36.359509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24272 10:15:36.359919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24273 10:15:36.394185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24274 10:15:36.394661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24276 10:15:36.430074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24277 10:15:36.430509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24279 10:15:36.469937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24280 10:15:36.470365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24282 10:15:36.506052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24283 10:15:36.506457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24285 10:15:36.543455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24287 10:15:36.543906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24288 10:15:36.579278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24289 10:15:36.579694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24291 10:15:36.615162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24292 10:15:36.615583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24294 10:15:36.651362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24295 10:15:36.651921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24297 10:15:36.707816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24298 10:15:36.708286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24300 10:15:36.746337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24301 10:15:36.746855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24303 10:15:36.790764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24304 10:15:36.791214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24306 10:15:36.837904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24307 10:15:36.838316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24309 10:15:36.883584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24310 10:15:36.883984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24312 10:15:36.927431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24313 10:15:36.927925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24315 10:15:36.973515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24316 10:15:36.974080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24318 10:15:37.016086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24319 10:15:37.016588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24321 10:15:37.065392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24322 10:15:37.065884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24324 10:15:37.114816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24326 10:15:37.115547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24327 10:15:37.166116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24328 10:15:37.166545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24330 10:15:37.211837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24331 10:15:37.212211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24333 10:15:37.251382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24334 10:15:37.251774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24336 10:15:37.295066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24337 10:15:37.295465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24339 10:15:37.341432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24340 10:15:37.341911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24342 10:15:37.376058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24344 10:15:37.376480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24345 10:15:37.412204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24346 10:15:37.412621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24348 10:15:37.456991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24350 10:15:37.457376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24351 10:15:37.501852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24353 10:15:37.502213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24354 10:15:37.539858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24356 10:15:37.540206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24357 10:15:37.577895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24358 10:15:37.578277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24360 10:15:37.614779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24361 10:15:37.615213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24363 10:15:37.651443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24364 10:15:37.651903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24366 10:15:37.688335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24368 10:15:37.688926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24369 10:15:37.725561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24370 10:15:37.725992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24372 10:15:37.762410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24373 10:15:37.762963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24375 10:15:37.799707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24377 10:15:37.800178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24378 10:15:37.842491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24379 10:15:37.842917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24381 10:15:37.882602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24382 10:15:37.883024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24384 10:15:37.923799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24385 10:15:37.924276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24387 10:15:37.961518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24388 10:15:37.962074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24390 10:15:37.999664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24391 10:15:38.000137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24393 10:15:38.037463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24395 10:15:38.037891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24396 10:15:38.076048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24397 10:15:38.076416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24399 10:15:38.114407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24400 10:15:38.114892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24402 10:15:38.164566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24403 10:15:38.165098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24405 10:15:38.213980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24406 10:15:38.214431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24408 10:15:38.262430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24410 10:15:38.263202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24411 10:15:38.312615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24412 10:15:38.313087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24414 10:15:38.363278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24415 10:15:38.363724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24417 10:15:38.413854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24418 10:15:38.414323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24420 10:15:38.463561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24421 10:15:38.464072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24423 10:15:38.514684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24425 10:15:38.515388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24426 10:15:38.566129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24427 10:15:38.566557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24429 10:15:38.610881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24430 10:15:38.611276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24432 10:15:38.656325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24433 10:15:38.656723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24435 10:15:38.720025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24436 10:15:38.720538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24438 10:15:38.762084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24439 10:15:38.762529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24441 10:15:38.809580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24442 10:15:38.810036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24444 10:15:38.863964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24446 10:15:38.864510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24447 10:15:38.914797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24449 10:15:38.915229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24450 10:15:38.957697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24451 10:15:38.958003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24453 10:15:39.004132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24454 10:15:39.004575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24456 10:15:39.050611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24458 10:15:39.051000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24459 10:15:39.095282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24460 10:15:39.095775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24462 10:15:39.139772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24463 10:15:39.140163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24465 10:15:39.183000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24466 10:15:39.183409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24468 10:15:39.229366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24469 10:15:39.229798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24471 10:15:39.264212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24472 10:15:39.264643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24474 10:15:39.303604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24475 10:15:39.304155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24477 10:15:39.344279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24478 10:15:39.344787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24480 10:15:39.383409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24481 10:15:39.383876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24483 10:15:39.424950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24485 10:15:39.425492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24486 10:15:39.465709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24487 10:15:39.466130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24489 10:15:39.501605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24490 10:15:39.502061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24492 10:15:39.537381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24493 10:15:39.537904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24495 10:15:39.571961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24496 10:15:39.572469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24498 10:15:39.606723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24499 10:15:39.607252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24501 10:15:39.651701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24503 10:15:39.652416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24504 10:15:39.697955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24505 10:15:39.698429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24507 10:15:39.742642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24509 10:15:39.743207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24510 10:15:39.788375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24512 10:15:39.788807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24513 10:15:39.834655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24514 10:15:39.835120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24516 10:15:39.882085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24518 10:15:39.882754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24519 10:15:39.927119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24520 10:15:39.927576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24522 10:15:39.972433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24523 10:15:39.972973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24525 10:15:40.018080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24526 10:15:40.018612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24528 10:15:40.062521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24529 10:15:40.062937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24531 10:15:40.103174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24532 10:15:40.103597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24534 10:15:40.155042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24536 10:15:40.155761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24537 10:15:40.203174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24538 10:15:40.203587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24540 10:15:40.239675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24541 10:15:40.240100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24543 10:15:40.274501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24544 10:15:40.275013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24546 10:15:40.309723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24547 10:15:40.310132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24549 10:15:40.345797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24550 10:15:40.346361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24552 10:15:40.385100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24554 10:15:40.385866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24555 10:15:40.425622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24556 10:15:40.426141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24558 10:15:40.462619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24560 10:15:40.463088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24561 10:15:40.503213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24562 10:15:40.503599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24564 10:15:40.547467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24565 10:15:40.547887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24567 10:15:40.583891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24568 10:15:40.584314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24570 10:15:40.619224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24572 10:15:40.619690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24573 10:15:40.655130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24575 10:15:40.655591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24576 10:15:40.690475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24577 10:15:40.690857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24579 10:15:40.723765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24580 10:15:40.724224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24582 10:15:40.768521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24583 10:15:40.769006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24585 10:15:40.803365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24586 10:15:40.803836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24588 10:15:40.838337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24589 10:15:40.838750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24591 10:15:40.874332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24592 10:15:40.874725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24594 10:15:40.912337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24595 10:15:40.912739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24597 10:15:40.947113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24598 10:15:40.947578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24600 10:15:40.982276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24601 10:15:40.982682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24603 10:15:41.018941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24604 10:15:41.019341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24606 10:15:41.058017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24607 10:15:41.058526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24609 10:15:41.102599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24611 10:15:41.103008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24612 10:15:41.138793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24613 10:15:41.139212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24615 10:15:41.176049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24617 10:15:41.176457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24618 10:15:41.212687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24620 10:15:41.213076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24621 10:15:41.262209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24622 10:15:41.262740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24624 10:15:41.296645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24626 10:15:41.297042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24627 10:15:41.331014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24628 10:15:41.331379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24630 10:15:41.375450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24631 10:15:41.375944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24633 10:15:41.418302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24634 10:15:41.418703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24636 10:15:41.458421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24638 10:15:41.458792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24639 10:15:41.501877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24640 10:15:41.502255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24642 10:15:41.545990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24644 10:15:41.546378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24645 10:15:41.586680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24646 10:15:41.587062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24648 10:15:41.621631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24649 10:15:41.622118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24651 10:15:41.657251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24652 10:15:41.657704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24654 10:15:41.700002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24656 10:15:41.700465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24657 10:15:41.736165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24658 10:15:41.736617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24660 10:15:41.776704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24661 10:15:41.777136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24663 10:15:41.823338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24665 10:15:41.823802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24666 10:15:41.868935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24668 10:15:41.869722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24669 10:15:41.910213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24670 10:15:41.910774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24672 10:15:41.956290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24673 10:15:41.956731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24675 10:15:41.997936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24677 10:15:41.998377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24678 10:15:42.035945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24680 10:15:42.036463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24681 10:15:42.074494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24682 10:15:42.074915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24684 10:15:42.114111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24686 10:15:42.114711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24687 10:15:42.150684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24688 10:15:42.151118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24690 10:15:42.186893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24692 10:15:42.187270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24693 10:15:42.224364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24694 10:15:42.224786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24696 10:15:42.261046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24698 10:15:42.261437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24699 10:15:42.296582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24701 10:15:42.296970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24702 10:15:42.335436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24704 10:15:42.335813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24705 10:15:42.370822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24706 10:15:42.371315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24708 10:15:42.407394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24710 10:15:42.408140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24711 10:15:42.442102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24713 10:15:42.442840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24714 10:15:42.477560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24715 10:15:42.478112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24717 10:15:42.512968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24719 10:15:42.513610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24720 10:15:42.547944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24721 10:15:42.548446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24723 10:15:42.583455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24724 10:15:42.583897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24726 10:15:42.619791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24727 10:15:42.620209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24729 10:15:42.654868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24730 10:15:42.655297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24732 10:15:42.689713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24734 10:15:42.690174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24735 10:15:42.725085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24737 10:15:42.725547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24738 10:15:42.760728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24739 10:15:42.761149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24741 10:15:42.796625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24742 10:15:42.797048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24744 10:15:42.832578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24745 10:15:42.833000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24747 10:15:42.868433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24748 10:15:42.868963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24750 10:15:42.904115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24751 10:15:42.904540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24753 10:15:42.941014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24755 10:15:42.941480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24756 10:15:42.976345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24758 10:15:42.976813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24759 10:15:43.010795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24760 10:15:43.011336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24762 10:15:43.048853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24764 10:15:43.049316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24765 10:15:43.085800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24766 10:15:43.086223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24768 10:15:43.129942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24770 10:15:43.130494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24771 10:15:43.175450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24772 10:15:43.175831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24774 10:15:43.219413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24775 10:15:43.219881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24777 10:15:43.264014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24778 10:15:43.264450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24780 10:15:43.300012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24781 10:15:43.300390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24783 10:15:43.348408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24784 10:15:43.348802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24786 10:15:43.388430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24787 10:15:43.388787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24789 10:15:43.421820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24791 10:15:43.422538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24792 10:15:43.455377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24794 10:15:43.456104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24795 10:15:43.490168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24796 10:15:43.490548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24798 10:15:43.524230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24799 10:15:43.524680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24801 10:15:43.559993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24802 10:15:43.560450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24804 10:15:43.595728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24805 10:15:43.596142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24807 10:15:43.631759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24809 10:15:43.632476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24810 10:15:43.677861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24811 10:15:43.678330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24813 10:15:43.718244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24814 10:15:43.718662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24816 10:15:43.756706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24818 10:15:43.757109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24819 10:15:43.810492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24820 10:15:43.810836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24822 10:15:43.870311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24824 10:15:43.870858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24825 10:15:43.920256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24826 10:15:43.920615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24828 10:15:43.969768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24829 10:15:43.970233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24831 10:15:44.019505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24833 10:15:44.020256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24834 10:15:44.055390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24836 10:15:44.056136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24837 10:15:44.101010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24839 10:15:44.101579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24840 10:15:44.146167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24841 10:15:44.146598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24843 10:15:44.191585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24845 10:15:44.192235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24846 10:15:44.239216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24847 10:15:44.239690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24849 10:15:44.286845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24850 10:15:44.287306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24852 10:15:44.331475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24853 10:15:44.331867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24855 10:15:44.375375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24856 10:15:44.375763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24858 10:15:44.418938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24859 10:15:44.419365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24861 10:15:44.454150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24862 10:15:44.454576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24864 10:15:44.489789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24865 10:15:44.490283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24867 10:15:44.530990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24868 10:15:44.531421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24870 10:15:44.568948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24872 10:15:44.569442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24873 10:15:44.605817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24875 10:15:44.606270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24876 10:15:44.652366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24878 10:15:44.652787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24879 10:15:44.689010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24881 10:15:44.689391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24882 10:15:44.725933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24883 10:15:44.726452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24885 10:15:44.764690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24887 10:15:44.765268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24888 10:15:44.805049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24890 10:15:44.805465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24891 10:15:44.842065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24892 10:15:44.842494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24894 10:15:44.877562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24895 10:15:44.877994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24897 10:15:44.918452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24898 10:15:44.918858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24900 10:15:44.954002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24902 10:15:44.954752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24903 10:15:44.989563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24904 10:15:44.990056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24906 10:15:45.025017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24908 10:15:45.025608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24909 10:15:45.060593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24911 10:15:45.061348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24912 10:15:45.095825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24913 10:15:45.096276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24915 10:15:45.131213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24916 10:15:45.131773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24918 10:15:45.170165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24920 10:15:45.170757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24921 10:15:45.206930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24922 10:15:45.207463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24924 10:15:45.243850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24926 10:15:45.244586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24927 10:15:45.279361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
24928 10:15:45.279827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
24930 10:15:45.314932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
24931 10:15:45.315336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
24933 10:15:45.350671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
24934 10:15:45.351076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
24936 10:15:45.385662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
24938 10:15:45.386232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
24939 10:15:45.420951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
24941 10:15:45.421561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
24942 10:15:45.455865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
24944 10:15:45.456310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
24945 10:15:45.490316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
24946 10:15:45.490697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
24948 10:15:45.526816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
24950 10:15:45.527267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
24951 10:15:45.562312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
24952 10:15:45.562789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
24954 10:15:45.609685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
24956 10:15:45.610415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
24957 10:15:45.648532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
24958 10:15:45.648973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
24960 10:15:45.685354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
24961 10:15:45.685792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
24963 10:15:45.719865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
24964 10:15:45.720282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
24966 10:15:45.755347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
24967 10:15:45.755762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
24969 10:15:45.794418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
24971 10:15:45.794872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
24972 10:15:45.831312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
24973 10:15:45.831725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
24975 10:15:45.869969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
24976 10:15:45.870404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
24978 10:15:45.911127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
24979 10:15:45.911564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
24981 10:15:45.952270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
24982 10:15:45.952700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
24984 10:15:45.987762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
24986 10:15:45.988148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
24987 10:15:46.022820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
24988 10:15:46.023190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
24990 10:15:46.058071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
24991 10:15:46.058496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
24993 10:15:46.093599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
24994 10:15:46.094020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
24996 10:15:46.145718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
24997 10:15:46.146063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
24999 10:15:46.188847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
25001 10:15:46.189309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
25002 10:15:46.222904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
25003 10:15:46.223312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
25005 10:15:46.258688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
25007 10:15:46.259144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
25008 10:15:46.294141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
25009 10:15:46.294595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
25011 10:15:46.335544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
25012 10:15:46.335964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
25014 10:15:46.373856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
25015 10:15:46.374280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
25017 10:15:46.409370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
25018 10:15:46.409744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
25020 10:15:46.443403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
25021 10:15:46.443790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
25023 10:15:46.478293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
25025 10:15:46.478960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
25026 10:15:46.513200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
25028 10:15:46.513663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
25029 10:15:46.548805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
25031 10:15:46.549515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
25032 10:15:46.584093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
25034 10:15:46.584727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
25035 10:15:46.620607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
25036 10:15:46.621031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
25038 10:15:46.655610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
25039 10:15:46.656034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
25041 10:15:46.690356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
25042 10:15:46.690776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
25044 10:15:46.724643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
25045 10:15:46.725069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
25047 10:15:46.757720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
25048 10:15:46.758134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
25050 10:15:46.799794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
25051 10:15:46.800221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
25053 10:15:46.846830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
25054 10:15:46.847253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
25056 10:15:46.891268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
25057 10:15:46.891674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
25059 10:15:46.930255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
25061 10:15:46.930985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
25062 10:15:46.971716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
25063 10:15:46.972093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
25065 10:15:47.012337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
25066 10:15:47.012766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
25068 10:15:47.052030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
25070 10:15:47.052450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
25071 10:15:47.088609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
25072 10:15:47.089112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
25074 10:15:47.130437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
25076 10:15:47.131144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
25077 10:15:47.166960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
25078 10:15:47.167386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
25080 10:15:47.203254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
25081 10:15:47.203696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
25083 10:15:47.251295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
25084 10:15:47.251711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
25086 10:15:47.288630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
25088 10:15:47.289277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
25089 10:15:47.330746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
25090 10:15:47.331140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
25092 10:15:47.372075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
25093 10:15:47.372595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
25095 10:15:47.409602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
25096 10:15:47.410150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
25098 10:15:47.446165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
25100 10:15:47.446865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
25101 10:15:47.482391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
25102 10:15:47.482873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
25104 10:15:47.519132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
25105 10:15:47.519675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
25107 10:15:47.555879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
25109 10:15:47.556615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
25110 10:15:47.596174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
25111 10:15:47.596660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
25113 10:15:47.636585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
25114 10:15:47.637025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
25116 10:15:47.675291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
25118 10:15:47.675893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
25119 10:15:47.715606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
25120 10:15:47.716021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
25122 10:15:47.752622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
25124 10:15:47.753087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
25125 10:15:47.787098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
25126 10:15:47.787639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
25128 10:15:47.821047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
25130 10:15:47.821775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
25131 10:15:47.856274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
25132 10:15:47.856694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
25134 10:15:47.891192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
25135 10:15:47.891577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
25137 10:15:47.932556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
25138 10:15:47.932979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
25140 10:15:47.968253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
25141 10:15:47.968749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
25143 10:15:48.005478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
25144 10:15:48.005909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
25146 10:15:48.042202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
25148 10:15:48.042666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
25149 10:15:48.079563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
25150 10:15:48.080003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
25152 10:15:48.129938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
25153 10:15:48.130371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
25155 10:15:48.171425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
25156 10:15:48.171780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
25158 10:15:48.214293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
25159 10:15:48.214703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
25161 10:15:48.258891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
25163 10:15:48.259512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
25164 10:15:48.304528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
25165 10:15:48.304966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
25167 10:15:48.351209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
25169 10:15:48.351572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
25170 10:15:48.398832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25171 10:15:48.399207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
25173 10:15:48.442076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25174 10:15:48.442500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25176 10:15:48.486478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25177 10:15:48.486915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25179 10:15:48.522455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25180 10:15:48.522862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25182 10:15:48.569852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25184 10:15:48.570276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25185 10:15:48.611392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25186 10:15:48.611891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25188 10:15:48.654165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25190 10:15:48.654660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25191 10:15:48.696333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25192 10:15:48.696719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25194 10:15:48.734157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25195 10:15:48.734550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25197 10:15:48.770069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25198 10:15:48.770499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25200 10:15:48.807963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25201 10:15:48.808359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25203 10:15:48.841351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25204 10:15:48.841770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25206 10:15:48.875929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25207 10:15:48.876349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25209 10:15:48.914248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25210 10:15:48.914689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25212 10:15:48.973721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25213 10:15:48.974189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25215 10:15:49.015416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25217 10:15:49.015885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25218 10:15:49.062230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25219 10:15:49.062649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25221 10:15:49.118842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25222 10:15:49.119259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25224 10:15:49.172497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25225 10:15:49.172931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25227 10:15:49.219724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25228 10:15:49.220100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25230 10:15:49.260475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25231 10:15:49.260893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25233 10:15:49.303661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25234 10:15:49.304203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25236 10:15:49.348157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25237 10:15:49.348587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25239 10:15:49.391354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25240 10:15:49.391792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25242 10:15:49.442255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25244 10:15:49.442728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25245 10:15:49.483637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25246 10:15:49.484035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25248 10:15:49.531593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25249 10:15:49.532138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25251 10:15:49.577639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25252 10:15:49.578080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25254 10:15:49.623776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25255 10:15:49.624203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25257 10:15:49.671860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25258 10:15:49.672286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25260 10:15:49.721087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25262 10:15:49.721456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25263 10:15:49.771499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25265 10:15:49.771882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25266 10:15:49.823203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25267 10:15:49.823648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25269 10:15:49.874819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25270 10:15:49.875202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25272 10:15:49.919438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25274 10:15:49.919825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25275 10:15:49.961867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25276 10:15:49.962326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25278 10:15:49.998767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25279 10:15:49.999197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25281 10:15:50.035577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25282 10:15:50.036029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25284 10:15:50.074150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25285 10:15:50.074700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25287 10:15:50.122391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25289 10:15:50.122759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25290 10:15:50.158279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25291 10:15:50.158808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25293 10:15:50.194083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25295 10:15:50.194552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25296 10:15:50.232010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25298 10:15:50.232752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25299 10:15:50.275202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25300 10:15:50.275581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25302 10:15:50.326340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25303 10:15:50.326784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25305 10:15:50.373613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25306 10:15:50.374183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25308 10:15:50.419840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25309 10:15:50.420320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25311 10:15:50.474351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25312 10:15:50.474759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25314 10:15:50.523360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25315 10:15:50.523812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25317 10:15:50.565847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25318 10:15:50.566235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25320 10:15:50.600767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25322 10:15:50.601222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25323 10:15:50.645367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25324 10:15:50.645785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25326 10:15:50.686851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25327 10:15:50.687279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25329 10:15:50.724500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25331 10:15:50.724973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25332 10:15:50.759673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25333 10:15:50.760091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25335 10:15:50.809080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25337 10:15:50.809536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25338 10:15:50.852910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25340 10:15:50.853379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25341 10:15:50.893969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25342 10:15:50.894353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25344 10:15:50.929219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25346 10:15:50.929697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25347 10:15:50.964178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25349 10:15:50.964560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25350 10:15:50.998708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25351 10:15:50.999136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25353 10:15:51.033033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25355 10:15:51.033420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25356 10:15:51.069035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25358 10:15:51.069884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25359 10:15:51.106118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25360 10:15:51.106745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25362 10:15:51.141209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25363 10:15:51.141592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25365 10:15:51.174784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25367 10:15:51.175174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25368 10:15:51.208571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25369 10:15:51.208963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25371 10:15:51.246988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25372 10:15:51.247413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25374 10:15:51.283083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25375 10:15:51.283495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25377 10:15:51.323197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25378 10:15:51.323611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25380 10:15:51.364755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25382 10:15:51.365194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25383 10:15:51.406912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25384 10:15:51.407339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25386 10:15:51.442725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25388 10:15:51.443135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25389 10:15:51.478568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25390 10:15:51.478998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25392 10:15:51.516220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25393 10:15:51.516727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25395 10:15:51.556216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25396 10:15:51.556681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25398 10:15:51.599916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25400 10:15:51.600370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25401 10:15:51.641713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25403 10:15:51.642183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25404 10:15:51.682600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25405 10:15:51.682985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25407 10:15:51.722038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25408 10:15:51.722448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25410 10:15:51.764131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25411 10:15:51.764598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25413 10:15:51.811340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25414 10:15:51.811769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25416 10:15:51.858747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25417 10:15:51.859165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25419 10:15:51.898256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25420 10:15:51.898679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25422 10:15:51.939630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25423 10:15:51.940014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25425 10:15:51.975595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25427 10:15:51.975998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25428 10:15:52.016207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25430 10:15:52.016580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25431 10:15:52.052086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25432 10:15:52.052552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25434 10:15:52.091212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25435 10:15:52.091587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25437 10:15:52.132686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25438 10:15:52.133144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25440 10:15:52.177736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25441 10:15:52.178212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25443 10:15:52.234009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25444 10:15:52.234419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25446 10:15:52.289106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25448 10:15:52.289581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25449 10:15:52.338507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25450 10:15:52.338933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25452 10:15:52.388417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25453 10:15:52.388859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25455 10:15:52.438183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25456 10:15:52.438569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25458 10:15:52.479104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25459 10:15:52.479492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25461 10:15:52.520373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25463 10:15:52.520748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25464 10:15:52.562522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25466 10:15:52.563006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25467 10:15:52.604435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25468 10:15:52.604841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25470 10:15:52.644160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25472 10:15:52.644638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25473 10:15:52.696819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25475 10:15:52.697527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25476 10:15:52.738616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25477 10:15:52.739027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25479 10:15:52.778287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25480 10:15:52.778707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25482 10:15:52.819666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25483 10:15:52.820055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25485 10:15:52.855384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25487 10:15:52.855962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25488 10:15:52.895417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25490 10:15:52.895938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25491 10:15:52.930793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25492 10:15:52.931169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25494 10:15:52.970025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25495 10:15:52.970503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25497 10:15:53.017337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25499 10:15:53.017808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25500 10:15:53.052103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25502 10:15:53.052631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25503 10:15:53.086362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25505 10:15:53.086830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25506 10:15:53.121273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25507 10:15:53.121662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25509 10:15:53.158655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25510 10:15:53.159211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25512 10:15:53.195801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25514 10:15:53.196556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25515 10:15:53.229419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25517 10:15:53.230039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25518 10:15:53.260948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25520 10:15:53.261399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25521 10:15:53.293685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25523 10:15:53.294142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25524 10:15:53.327116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25525 10:15:53.327695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25527 10:15:53.374457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25528 10:15:53.374956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25530 10:15:53.407583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25531 10:15:53.408073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25533 10:15:53.441378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25535 10:15:53.441867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25536 10:15:53.475826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25538 10:15:53.476486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25539 10:15:53.512995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25541 10:15:53.513677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25542 10:15:53.549738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25543 10:15:53.550112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25545 10:15:53.585501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25546 10:15:53.585960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25548 10:15:53.622124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25549 10:15:53.622510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25551 10:15:53.659957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25552 10:15:53.660343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25554 10:15:53.699484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25555 10:15:53.699912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25557 10:15:53.742066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25559 10:15:53.742854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25560 10:15:53.791537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25561 10:15:53.791994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25563 10:15:53.839427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25564 10:15:53.839827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25566 10:15:53.886085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25567 10:15:53.886513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25569 10:15:53.931805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25570 10:15:53.932184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25572 10:15:53.969946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25573 10:15:53.970338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25575 10:15:54.009010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25577 10:15:54.009394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25578 10:15:54.072088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25579 10:15:54.072478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25581 10:15:54.118579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25582 10:15:54.119089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25584 10:15:54.154977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25585 10:15:54.155397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25587 10:15:54.191494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25588 10:15:54.191921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25590 10:15:54.227758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25591 10:15:54.228182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25593 10:15:54.263893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25594 10:15:54.264316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25596 10:15:54.299021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25597 10:15:54.299437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25599 10:15:54.335385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25600 10:15:54.335817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25602 10:15:54.374836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25603 10:15:54.375257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25605 10:15:54.417925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25606 10:15:54.418357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25608 10:15:54.453087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25610 10:15:54.453801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25611 10:15:54.496238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25612 10:15:54.496710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25614 10:15:54.540249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25616 10:15:54.540666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25617 10:15:54.586733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25618 10:15:54.587115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25620 10:15:54.636654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25622 10:15:54.637121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25623 10:15:54.677943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25625 10:15:54.678345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25626 10:15:54.719529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25627 10:15:54.719948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25629 10:15:54.762997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25630 10:15:54.763425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25632 10:15:54.807608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25633 10:15:54.808029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25635 10:15:54.855634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25637 10:15:54.856046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25638 10:15:54.895148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25639 10:15:54.895538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25641 10:15:54.942815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25642 10:15:54.943314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25644 10:15:54.987054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25645 10:15:54.987456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25647 10:15:55.026485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25648 10:15:55.026908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25650 10:15:55.063055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25651 10:15:55.063436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25653 10:15:55.111515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25655 10:15:55.112247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25656 10:15:55.156621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25657 10:15:55.157031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25659 10:15:55.196588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25660 10:15:55.197032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25662 10:15:55.235084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25663 10:15:55.235522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25665 10:15:55.284381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25666 10:15:55.284768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25668 10:15:55.322066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25669 10:15:55.322519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25671 10:15:55.362998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25672 10:15:55.363489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25674 10:15:55.398562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25676 10:15:55.399276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25677 10:15:55.435928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25678 10:15:55.436356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25680 10:15:55.475983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25682 10:15:55.476716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25683 10:15:55.515455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25684 10:15:55.515939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25686 10:15:55.557102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25688 10:15:55.557561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25689 10:15:55.591698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25690 10:15:55.592166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25692 10:15:55.634903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25693 10:15:55.635326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25695 10:15:55.671155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25696 10:15:55.671569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25698 10:15:55.708412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25700 10:15:55.708857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25701 10:15:55.749899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25702 10:15:55.750280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25704 10:15:55.785259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25705 10:15:55.785686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25707 10:15:55.834592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25709 10:15:55.835073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25710 10:15:55.884057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25711 10:15:55.884467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25713 10:15:55.934446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25714 10:15:55.934844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25716 10:15:55.973513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25718 10:15:55.973989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25719 10:15:56.007595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25720 10:15:56.008004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25722 10:15:56.040616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25723 10:15:56.041013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25725 10:15:56.081426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25727 10:15:56.081804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25728 10:15:56.118397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25730 10:15:56.118822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25731 10:15:56.158781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25732 10:15:56.159313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25734 10:15:56.195547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25736 10:15:56.196129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25737 10:15:56.227927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25738 10:15:56.228382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25740 10:15:56.264518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25741 10:15:56.264972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25743 10:15:56.307990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25744 10:15:56.308462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25746 10:15:56.350340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25748 10:15:56.350799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25749 10:15:56.387622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25750 10:15:56.388044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25752 10:15:56.422174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25753 10:15:56.422609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25755 10:15:56.467278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25757 10:15:56.467741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25758 10:15:56.502161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25759 10:15:56.502583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25761 10:15:56.546087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25762 10:15:56.546513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25764 10:15:56.582983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25765 10:15:56.583423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25767 10:15:56.623167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25769 10:15:56.623865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25770 10:15:56.660367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25771 10:15:56.660830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25773 10:15:56.698275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25774 10:15:56.698833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25776 10:15:56.736889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25778 10:15:56.737474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25779 10:15:56.771425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25780 10:15:56.771855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25782 10:15:56.815598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25784 10:15:56.816147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25785 10:15:56.852070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25786 10:15:56.852484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25788 10:15:56.890406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25789 10:15:56.890831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25791 10:15:56.929958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25792 10:15:56.930379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25794 10:15:56.967656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25795 10:15:56.968091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25797 10:15:57.005903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25798 10:15:57.006459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25800 10:15:57.041632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25801 10:15:57.042058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25803 10:15:57.080027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25804 10:15:57.080446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25806 10:15:57.116000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25808 10:15:57.116760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25809 10:15:57.152579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25810 10:15:57.153102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25812 10:15:57.192518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25813 10:15:57.193004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25815 10:15:57.227396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25817 10:15:57.228162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25818 10:15:57.276448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25819 10:15:57.276873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25821 10:15:57.328148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25822 10:15:57.328611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25824 10:15:57.381740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25825 10:15:57.382191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25827 10:15:57.426488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25828 10:15:57.426907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25830 10:15:57.461212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25831 10:15:57.461636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25833 10:15:57.497601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25834 10:15:57.498174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25836 10:15:57.534234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25837 10:15:57.534725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25839 10:15:57.568085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25840 10:15:57.568602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25842 10:15:57.611915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25844 10:15:57.612689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25845 10:15:57.662100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25847 10:15:57.662796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25848 10:15:57.720563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25849 10:15:57.721015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25851 10:15:57.774936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25852 10:15:57.775352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25854 10:15:57.826092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25855 10:15:57.826518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25857 10:15:57.867574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25858 10:15:57.867997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25860 10:15:57.916393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25861 10:15:57.916815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25863 10:15:57.968248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25864 10:15:57.968691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25866 10:15:58.021937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25867 10:15:58.022368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25869 10:15:58.075839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25870 10:15:58.076328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25872 10:15:58.124018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25874 10:15:58.124450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25875 10:15:58.170060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25876 10:15:58.170426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25878 10:15:58.208334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25879 10:15:58.208845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25881 10:15:58.245778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25882 10:15:58.246148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25884 10:15:58.281974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25885 10:15:58.282421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25887 10:15:58.319196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25888 10:15:58.319627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25890 10:15:58.358980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25891 10:15:58.359453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25893 10:15:58.396443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25894 10:15:58.396953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25896 10:15:58.434278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25898 10:15:58.434658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25899 10:15:58.479317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25900 10:15:58.479745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25902 10:15:58.519398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25903 10:15:58.519816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25905 10:15:58.556335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25906 10:15:58.556704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25908 10:15:58.597899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25910 10:15:58.598633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25911 10:15:58.637737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25912 10:15:58.638232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25914 10:15:58.683753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25915 10:15:58.684164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25917 10:15:58.732039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25918 10:15:58.732573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25920 10:15:58.779219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25921 10:15:58.779723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25923 10:15:58.819756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25924 10:15:58.820232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25926 10:15:58.864863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
25928 10:15:58.865486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25929 10:15:58.906478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
25931 10:15:58.907014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
25932 10:15:58.962708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
25933 10:15:58.963105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
25935 10:15:59.016315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
25937 10:15:59.016764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
25938 10:15:59.059112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
25939 10:15:59.059548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
25941 10:15:59.103977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
25943 10:15:59.104414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
25944 10:15:59.147259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
25945 10:15:59.147695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
25947 10:15:59.208578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
25948 10:15:59.209044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
25950 10:15:59.243898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
25951 10:15:59.244299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
25953 10:15:59.278673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
25954 10:15:59.279098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
25956 10:15:59.321995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
25957 10:15:59.322416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
25959 10:15:59.357248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
25960 10:15:59.357661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
25962 10:15:59.392418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
25963 10:15:59.392786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
25965 10:15:59.431618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
25967 10:15:59.432333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
25968 10:15:59.472151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
25969 10:15:59.472694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
25971 10:15:59.520190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
25972 10:15:59.520646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
25974 10:15:59.571955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
25975 10:15:59.572410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
25977 10:15:59.607872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
25979 10:15:59.608507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
25980 10:15:59.658653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
25982 10:15:59.659165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
25983 10:15:59.714857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
25984 10:15:59.715406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
25986 10:15:59.771277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
25987 10:15:59.771795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
25989 10:15:59.826697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
25990 10:15:59.827130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
25992 10:15:59.870872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
25993 10:15:59.871294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
25995 10:15:59.916947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
25997 10:15:59.917874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
25998 10:15:59.964351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
26000 10:15:59.964729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
26001 10:16:00.013330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
26002 10:16:00.013688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
26004 10:16:00.061839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
26005 10:16:00.062390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
26007 10:16:00.107941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
26009 10:16:00.108354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
26010 10:16:00.156284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
26011 10:16:00.156677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
26013 10:16:00.200314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
26014 10:16:00.200747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
26016 10:16:00.248371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
26017 10:16:00.248790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
26019 10:16:00.294925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
26020 10:16:00.295304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
26022 10:16:00.341561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
26023 10:16:00.341969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
26025 10:16:00.388971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
26027 10:16:00.389604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
26028 10:16:00.437864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
26029 10:16:00.438278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
26031 10:16:00.485773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
26032 10:16:00.486167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
26034 10:16:00.533724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
26035 10:16:00.534220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
26037 10:16:00.576074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
26038 10:16:00.576574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
26040 10:16:00.621128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
26041 10:16:00.621518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
26043 10:16:00.664863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
26045 10:16:00.665524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
26046 10:16:00.705534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
26047 10:16:00.706033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
26049 10:16:00.745728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
26050 10:16:00.746245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
26052 10:16:00.782792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
26053 10:16:00.783314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
26055 10:16:00.826233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
26056 10:16:00.826644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
26058 10:16:00.875937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
26060 10:16:00.876413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
26061 10:16:00.919981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
26062 10:16:00.920400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
26064 10:16:00.959616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
26065 10:16:00.960047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
26067 10:16:01.007061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
26068 10:16:01.007482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
26070 10:16:01.058497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
26071 10:16:01.058961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
26073 10:16:01.106275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
26074 10:16:01.106633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
26076 10:16:01.152760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
26078 10:16:01.153176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
26079 10:16:01.199969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
26080 10:16:01.200362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
26082 10:16:01.249048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
26084 10:16:01.249463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
26085 10:16:01.296993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
26087 10:16:01.297382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
26088 10:16:01.340134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
26089 10:16:01.340670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
26091 10:16:01.376719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
26092 10:16:01.377225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
26094 10:16:01.420473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
26096 10:16:01.421244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
26097 10:16:01.464389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
26099 10:16:01.464829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
26100 10:16:01.511982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
26101 10:16:01.512471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
26103 10:16:01.554550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
26104 10:16:01.554928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
26106 10:16:01.594300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
26107 10:16:01.594714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
26109 10:16:01.636270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
26110 10:16:01.636667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
26112 10:16:01.684325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
26113 10:16:01.684819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
26115 10:16:01.726837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
26116 10:16:01.727287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
26118 10:16:01.763284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
26119 10:16:01.763706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
26121 10:16:01.812111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
26122 10:16:01.812518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
26124 10:16:01.851605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
26125 10:16:01.852062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
26127 10:16:01.897123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
26129 10:16:01.897589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
26130 10:16:01.932641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
26131 10:16:01.933066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
26133 10:16:01.971755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
26134 10:16:01.972261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
26136 10:16:02.012255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
26138 10:16:02.012698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
26139 10:16:02.052455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
26141 10:16:02.052891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
26142 10:16:02.095888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
26144 10:16:02.096342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
26145 10:16:02.141880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
26146 10:16:02.142306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
26148 10:16:02.187908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
26150 10:16:02.188323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
26151 10:16:02.230480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
26153 10:16:02.230933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
26154 10:16:02.275605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
26155 10:16:02.276110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
26157 10:16:02.322897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
26159 10:16:02.323523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
26160 10:16:02.361138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
26162 10:16:02.361878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
26163 10:16:02.409585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
26164 10:16:02.409986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
26166 10:16:02.458916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
26167 10:16:02.459336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
26169 10:16:02.506291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26171 10:16:02.506991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
26172 10:16:02.554678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26174 10:16:02.555390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26175 10:16:02.595834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26176 10:16:02.596362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26178 10:16:02.631085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26179 10:16:02.631480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26181 10:16:02.672134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26183 10:16:02.672837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26184 10:16:02.706578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26185 10:16:02.707148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26187 10:16:02.742834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26188 10:16:02.743265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26190 10:16:02.781918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26191 10:16:02.782455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26193 10:16:02.820247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26195 10:16:02.820835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26196 10:16:02.855588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26198 10:16:02.855998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26199 10:16:02.891280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26201 10:16:02.891722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26202 10:16:02.926400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26204 10:16:02.926859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26205 10:16:02.962176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26207 10:16:02.962624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26208 10:16:02.998578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26209 10:16:02.999019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26211 10:16:03.035442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26212 10:16:03.035887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26214 10:16:03.083757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26215 10:16:03.084192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26217 10:16:03.130370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26219 10:16:03.130778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26220 10:16:03.171823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26221 10:16:03.172215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26223 10:16:03.213437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26224 10:16:03.213865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26226 10:16:03.250378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26227 10:16:03.250755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26229 10:16:03.298385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26230 10:16:03.298818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26232 10:16:03.340087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26233 10:16:03.340554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26235 10:16:03.376115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26237 10:16:03.376556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26238 10:16:03.422930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26240 10:16:03.423289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26241 10:16:03.478677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26242 10:16:03.479152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26244 10:16:03.534804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26245 10:16:03.535257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26247 10:16:03.590948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26248 10:16:03.591326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26250 10:16:03.646485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26251 10:16:03.646919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26253 10:16:03.692453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26254 10:16:03.692854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26256 10:16:03.730734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26257 10:16:03.731147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26259 10:16:03.767129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26260 10:16:03.767532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26262 10:16:03.807471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26263 10:16:03.807876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26265 10:16:03.851917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26266 10:16:03.852295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26268 10:16:03.891721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26270 10:16:03.892126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26271 10:16:03.932493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26273 10:16:03.932964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26274 10:16:03.972180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26275 10:16:03.972568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26277 10:16:04.012162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26278 10:16:04.012555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26280 10:16:04.048250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26282 10:16:04.048701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26283 10:16:04.092342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26285 10:16:04.093052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26286 10:16:04.143898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26287 10:16:04.144364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26289 10:16:04.190403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26290 10:16:04.190809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26292 10:16:04.239465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26293 10:16:04.239839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26295 10:16:04.304510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26296 10:16:04.304932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26298 10:16:04.345757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26299 10:16:04.346126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26301 10:16:04.382048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26302 10:16:04.382384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26304 10:16:04.418604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26306 10:16:04.419158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26307 10:16:04.454441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26308 10:16:04.454856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26310 10:16:04.490586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26311 10:16:04.491021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26313 10:16:04.528549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26314 10:16:04.528984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26316 10:16:04.573911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26317 10:16:04.574451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26319 10:16:04.618438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26321 10:16:04.618902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26322 10:16:04.658440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26324 10:16:04.658895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26325 10:16:04.693708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26327 10:16:04.694144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26328 10:16:04.728735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26329 10:16:04.729221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26331 10:16:04.762965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26332 10:16:04.763368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26334 10:16:04.798701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26336 10:16:04.799117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26337 10:16:04.832725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26339 10:16:04.833405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26340 10:16:04.868485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26342 10:16:04.868940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26343 10:16:04.905957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26344 10:16:04.906383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26346 10:16:04.943413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26347 10:16:04.943831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26349 10:16:04.983713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26350 10:16:04.984163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26352 10:16:05.029834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26353 10:16:05.030316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26355 10:16:05.076081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26357 10:16:05.076756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26358 10:16:05.114333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26360 10:16:05.114726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26361 10:16:05.152364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26362 10:16:05.152742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26364 10:16:05.185711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26366 10:16:05.186175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26367 10:16:05.219679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26368 10:16:05.220098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26370 10:16:05.257597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26371 10:16:05.258019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26373 10:16:05.295422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26374 10:16:05.295832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26376 10:16:05.330970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26377 10:16:05.331449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26379 10:16:05.366649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26380 10:16:05.367068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26382 10:16:05.405908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26383 10:16:05.406422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26385 10:16:05.440406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26386 10:16:05.440814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26388 10:16:05.478567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26389 10:16:05.478983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26391 10:16:05.515667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26392 10:16:05.516216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26394 10:16:05.562715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26395 10:16:05.563201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26397 10:16:05.609058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26399 10:16:05.609685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26400 10:16:05.656249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26401 10:16:05.656718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26403 10:16:05.702375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26404 10:16:05.702790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26406 10:16:05.736621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26408 10:16:05.737079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26409 10:16:05.775229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26410 10:16:05.775646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26412 10:16:05.809963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26413 10:16:05.810396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26415 10:16:05.848518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26417 10:16:05.848942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26418 10:16:05.891734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26420 10:16:05.892186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26421 10:16:05.932436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26422 10:16:05.932877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26424 10:16:05.968230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26426 10:16:05.968711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26427 10:16:06.010746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26428 10:16:06.011161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26430 10:16:06.044901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26432 10:16:06.045360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26433 10:16:06.083331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26434 10:16:06.083745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26436 10:16:06.122708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26437 10:16:06.123270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26439 10:16:06.162788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26440 10:16:06.163267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26442 10:16:06.198871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26443 10:16:06.199285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26445 10:16:06.237878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26446 10:16:06.238318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26448 10:16:06.275815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26449 10:16:06.276231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26451 10:16:06.316949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26453 10:16:06.317402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26454 10:16:06.352958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26456 10:16:06.353393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26457 10:16:06.386215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26458 10:16:06.386711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26460 10:16:06.419479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26461 10:16:06.419965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26463 10:16:06.452207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26464 10:16:06.452623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26466 10:16:06.484643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26467 10:16:06.485080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26469 10:16:06.517790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26471 10:16:06.518423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26472 10:16:06.550300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26473 10:16:06.550737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26475 10:16:06.583345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26476 10:16:06.583780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26478 10:16:06.618279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26479 10:16:06.618688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26481 10:16:06.651656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26483 10:16:06.652100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26484 10:16:06.690861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26486 10:16:06.691314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26487 10:16:06.735850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26488 10:16:06.736314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26490 10:16:06.773815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26491 10:16:06.774292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26493 10:16:06.810851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26494 10:16:06.811394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26496 10:16:06.848554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26497 10:16:06.849040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26499 10:16:06.890597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26500 10:16:06.891062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26502 10:16:06.939865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26503 10:16:06.940300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26505 10:16:06.991592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26506 10:16:06.992068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26508 10:16:07.041349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26509 10:16:07.041798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26511 10:16:07.075569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26513 10:16:07.076021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26514 10:16:07.110846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26515 10:16:07.111292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26517 10:16:07.146820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26518 10:16:07.147235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26520 10:16:07.181618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26521 10:16:07.182035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26523 10:16:07.215247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26524 10:16:07.215652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26526 10:16:07.251078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26527 10:16:07.251503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26529 10:16:07.287203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26531 10:16:07.287666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26532 10:16:07.323363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26533 10:16:07.323784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26535 10:16:07.360143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26537 10:16:07.360649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26538 10:16:07.396232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26539 10:16:07.396626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26541 10:16:07.434511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26542 10:16:07.434857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26544 10:16:07.469404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26545 10:16:07.469824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26547 10:16:07.504077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26548 10:16:07.504506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26550 10:16:07.541229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26552 10:16:07.541632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26553 10:16:07.587697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26554 10:16:07.588075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26556 10:16:07.635923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26558 10:16:07.636417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26559 10:16:07.682535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26560 10:16:07.682990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26562 10:16:07.723149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26563 10:16:07.723545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26565 10:16:07.761953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26567 10:16:07.762626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26568 10:16:07.804442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26569 10:16:07.804875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26571 10:16:07.842635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26572 10:16:07.843027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26574 10:16:07.879310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26576 10:16:07.879747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26577 10:16:07.916101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26578 10:16:07.916477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26580 10:16:07.953373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26581 10:16:07.953788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26583 10:16:07.990473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26585 10:16:07.990823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26586 10:16:08.028566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26587 10:16:08.028993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26589 10:16:08.068069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26590 10:16:08.068493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26592 10:16:08.107896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26594 10:16:08.108631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26595 10:16:08.144619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26597 10:16:08.145200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26598 10:16:08.180187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26599 10:16:08.180591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26601 10:16:08.214745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26602 10:16:08.215145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26604 10:16:08.249858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26605 10:16:08.250273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26607 10:16:08.285590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26608 10:16:08.286146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26610 10:16:08.321833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26611 10:16:08.322299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26613 10:16:08.356008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26614 10:16:08.356434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26616 10:16:08.396527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26618 10:16:08.397122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26619 10:16:08.442049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26621 10:16:08.442503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26622 10:16:08.477001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26624 10:16:08.477480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26625 10:16:08.514154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26626 10:16:08.514582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26628 10:16:08.550810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26629 10:16:08.551302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26631 10:16:08.587483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26632 10:16:08.587975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26634 10:16:08.630102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26635 10:16:08.630670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26637 10:16:08.670662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26638 10:16:08.671077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26640 10:16:08.718574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26641 10:16:08.718973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26643 10:16:08.760224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26644 10:16:08.760640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26646 10:16:08.801667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26647 10:16:08.802087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26649 10:16:08.838481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26650 10:16:08.838902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26652 10:16:08.877981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26653 10:16:08.878420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26655 10:16:08.926017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26657 10:16:08.926776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26658 10:16:08.974587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26659 10:16:08.975074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26661 10:16:09.015138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26663 10:16:09.015700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26664 10:16:09.059465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26666 10:16:09.059915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26667 10:16:09.104585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26669 10:16:09.105041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26670 10:16:09.143785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26671 10:16:09.144205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26673 10:16:09.188158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26674 10:16:09.188567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26676 10:16:09.229764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26677 10:16:09.230281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26679 10:16:09.272310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26680 10:16:09.272743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26682 10:16:09.312188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26683 10:16:09.312623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26685 10:16:09.352273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26686 10:16:09.352710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26688 10:16:09.398540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26689 10:16:09.398938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26691 10:16:09.449426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26692 10:16:09.449982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26694 10:16:09.484212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26695 10:16:09.484595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26697 10:16:09.521440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26699 10:16:09.521877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26700 10:16:09.560875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26702 10:16:09.561330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26703 10:16:09.597277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26704 10:16:09.597686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26706 10:16:09.631469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26707 10:16:09.631944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26709 10:16:09.666874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26711 10:16:09.667332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26712 10:16:09.702382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26714 10:16:09.703124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26715 10:16:09.737983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26717 10:16:09.738467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26718 10:16:09.786311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26720 10:16:09.786920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26721 10:16:09.822105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26722 10:16:09.822608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26724 10:16:09.861813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26726 10:16:09.862242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26727 10:16:09.897957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26729 10:16:09.898416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26730 10:16:09.933997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26731 10:16:09.934441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26733 10:16:09.967786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26734 10:16:09.968202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26736 10:16:10.000122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26738 10:16:10.000566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26739 10:16:10.035590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26740 10:16:10.036002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26742 10:16:10.079662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26743 10:16:10.080074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26745 10:16:10.127871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26746 10:16:10.128343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26748 10:16:10.176666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26749 10:16:10.177156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26751 10:16:10.223307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26753 10:16:10.223960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26754 10:16:10.272914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26756 10:16:10.273448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26757 10:16:10.316390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26758 10:16:10.316756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26760 10:16:10.357576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26761 10:16:10.358161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26763 10:16:10.402422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26764 10:16:10.402821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26766 10:16:10.435509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26767 10:16:10.435926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26769 10:16:10.467853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26771 10:16:10.468500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26772 10:16:10.500162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26773 10:16:10.500568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26775 10:16:10.532483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26776 10:16:10.532884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26778 10:16:10.565388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26780 10:16:10.565817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26781 10:16:10.597961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26783 10:16:10.598539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26784 10:16:10.630949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26785 10:16:10.631373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26787 10:16:10.665792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26788 10:16:10.666227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26790 10:16:10.706470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26792 10:16:10.707206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26793 10:16:10.740972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26795 10:16:10.741391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26796 10:16:10.776776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26797 10:16:10.777275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26799 10:16:10.820158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26801 10:16:10.820617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26802 10:16:10.870320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26804 10:16:10.870809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26805 10:16:10.923791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26807 10:16:10.924272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26808 10:16:10.973909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26809 10:16:10.974313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26811 10:16:11.018067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26812 10:16:11.018480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26814 10:16:11.053147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26815 10:16:11.053548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26817 10:16:11.089466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26818 10:16:11.089906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26820 10:16:11.134388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26821 10:16:11.134764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26823 10:16:11.169713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26824 10:16:11.170064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26826 10:16:11.205983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26827 10:16:11.206590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26829 10:16:11.243748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26830 10:16:11.244156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26832 10:16:11.281118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26833 10:16:11.281562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26835 10:16:11.320190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26837 10:16:11.320649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26838 10:16:11.356310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26840 10:16:11.356782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26841 10:16:11.393354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26842 10:16:11.393776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26844 10:16:11.430316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26846 10:16:11.430762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26847 10:16:11.469126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26849 10:16:11.469664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26850 10:16:11.507376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26851 10:16:11.507770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26853 10:16:11.544322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26855 10:16:11.544780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26856 10:16:11.579010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26857 10:16:11.579419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26859 10:16:11.612560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26861 10:16:11.613032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26862 10:16:11.650320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26863 10:16:11.650739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26865 10:16:11.700297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26866 10:16:11.700855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26868 10:16:11.750799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26869 10:16:11.751243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26871 10:16:11.786158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26873 10:16:11.786631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26874 10:16:11.822006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26875 10:16:11.822462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26877 10:16:11.862195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26878 10:16:11.862674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26880 10:16:11.906895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26881 10:16:11.907479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26883 10:16:11.951129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26884 10:16:11.951522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26886 10:16:11.986236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26887 10:16:11.986650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26889 10:16:12.021584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26891 10:16:12.022044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26892 10:16:12.056256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26893 10:16:12.056659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26895 10:16:12.093151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26897 10:16:12.093618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26898 10:16:12.132097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26899 10:16:12.132550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26901 10:16:12.168671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26903 10:16:12.169145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26904 10:16:12.205432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26906 10:16:12.205898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26907 10:16:12.247890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26908 10:16:12.248347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26910 10:16:12.299816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26911 10:16:12.300232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26913 10:16:12.336453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26914 10:16:12.336888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26916 10:16:12.374845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26917 10:16:12.375264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26919 10:16:12.414230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26920 10:16:12.414663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26922 10:16:12.458471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26924 10:16:12.458942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26925 10:16:12.498307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26926 10:16:12.498740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
26928 10:16:12.535016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
26930 10:16:12.535454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
26931 10:16:12.571719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
26932 10:16:12.572148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
26934 10:16:12.609419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
26935 10:16:12.609839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
26937 10:16:12.644827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
26939 10:16:12.645278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
26940 10:16:12.684256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
26941 10:16:12.684666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
26943 10:16:12.722201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
26944 10:16:12.722715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
26946 10:16:12.760882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
26947 10:16:12.761310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
26949 10:16:12.799525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
26950 10:16:12.799997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
26952 10:16:12.838304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
26954 10:16:12.838776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
26955 10:16:12.877909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
26956 10:16:12.878341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
26958 10:16:12.916959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
26960 10:16:12.917386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
26961 10:16:12.954241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
26962 10:16:12.954631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
26964 10:16:12.991049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
26966 10:16:12.991512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
26967 10:16:13.030469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
26968 10:16:13.030897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
26970 10:16:13.067842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
26972 10:16:13.068314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
26973 10:16:13.118258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
26974 10:16:13.118655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
26976 10:16:13.155060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
26977 10:16:13.155919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
26979 10:16:13.195071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
26980 10:16:13.195506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
26982 10:16:13.231320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
26983 10:16:13.231721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
26985 10:16:13.275139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
26986 10:16:13.275622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
26988 10:16:13.316102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
26990 10:16:13.316569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
26991 10:16:13.366591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
26992 10:16:13.367019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
26994 10:16:13.407600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
26996 10:16:13.408044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
26997 10:16:13.453490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
26998 10:16:13.454012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
27000 10:16:13.497109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
27002 10:16:13.497581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
27003 10:16:13.532109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
27005 10:16:13.532574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
27006 10:16:13.576044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
27007 10:16:13.576458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
27009 10:16:13.619956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
27010 10:16:13.620377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
27012 10:16:13.656396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
27014 10:16:13.657129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
27015 10:16:13.695488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
27016 10:16:13.695921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
27018 10:16:13.736421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
27020 10:16:13.736854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
27021 10:16:13.775380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
27023 10:16:13.775854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
27024 10:16:13.817485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
27025 10:16:13.817938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
27027 10:16:13.862703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
27028 10:16:13.863280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
27030 10:16:13.914171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
27031 10:16:13.914609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
27033 10:16:13.966850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
27034 10:16:13.967337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
27036 10:16:14.013837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
27037 10:16:14.014282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
27039 10:16:14.060044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
27040 10:16:14.060427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
27042 10:16:14.100402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
27043 10:16:14.100831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
27045 10:16:14.144160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
27046 10:16:14.144705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
27048 10:16:14.182533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
27049 10:16:14.182964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
27051 10:16:14.220726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
27053 10:16:14.221257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
27054 10:16:14.266469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
27055 10:16:14.266958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
27057 10:16:14.314861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
27058 10:16:14.315350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
27060 10:16:14.356250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
27061 10:16:14.356707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
27063 10:16:14.398511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
27064 10:16:14.398940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
27066 10:16:14.449809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
27067 10:16:14.450307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
27069 10:16:14.491861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
27070 10:16:14.492317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
27072 10:16:14.559853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
27073 10:16:14.560423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
27075 10:16:14.604584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
27076 10:16:14.605020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
27078 10:16:14.651748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
27079 10:16:14.652195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
27081 10:16:14.706688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
27082 10:16:14.707114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
27084 10:16:14.752507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
27086 10:16:14.752995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
27087 10:16:14.797634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
27089 10:16:14.798120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
27090 10:16:14.844422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
27091 10:16:14.844879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
27093 10:16:14.887561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
27094 10:16:14.888013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
27096 10:16:14.937592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
27097 10:16:14.938013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
27099 10:16:14.978239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
27100 10:16:14.978674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
27102 10:16:15.026334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
27103 10:16:15.026766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
27105 10:16:15.070308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
27106 10:16:15.070747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
27108 10:16:15.119266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
27110 10:16:15.119742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
27111 10:16:15.170974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
27113 10:16:15.171598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
27114 10:16:15.222998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
27115 10:16:15.223436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
27117 10:16:15.275553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
27118 10:16:15.276051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
27120 10:16:15.326634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
27121 10:16:15.327067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
27123 10:16:15.371636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
27124 10:16:15.372038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
27126 10:16:15.421663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
27127 10:16:15.422045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
27129 10:16:15.465710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
27130 10:16:15.466226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
27132 10:16:15.515075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
27134 10:16:15.515556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
27135 10:16:15.567783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
27137 10:16:15.568396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
27138 10:16:15.618060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
27140 10:16:15.618709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
27141 10:16:15.666001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
27143 10:16:15.666617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
27144 10:16:15.715955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
27145 10:16:15.716393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
27147 10:16:15.767466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
27148 10:16:15.768005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
27150 10:16:15.819021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
27151 10:16:15.819451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
27153 10:16:15.862795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
27155 10:16:15.863207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
27156 10:16:15.916586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
27158 10:16:15.917260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
27159 10:16:15.970325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
27160 10:16:15.970745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
27162 10:16:16.016425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
27163 10:16:16.016863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
27165 10:16:16.076363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
27166 10:16:16.076888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
27168 10:16:16.118501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
27170 10:16:16.118923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
27171 10:16:16.166739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27172 10:16:16.167161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27174 10:16:16.211821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27175 10:16:16.212258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27177 10:16:16.272232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27178 10:16:16.272669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27180 10:16:16.323647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27181 10:16:16.324209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27183 10:16:16.369703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27184 10:16:16.370102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27186 10:16:16.413924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27188 10:16:16.414384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27189 10:16:16.462656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27190 10:16:16.463108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27192 10:16:16.511210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27193 10:16:16.511670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27195 10:16:16.564145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27196 10:16:16.564578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27198 10:16:16.618033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27199 10:16:16.618442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27201 10:16:16.670050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27202 10:16:16.670505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27204 10:16:16.717457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27206 10:16:16.717899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27207 10:16:16.768999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27209 10:16:16.769457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27210 10:16:16.820641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27211 10:16:16.821067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27213 10:16:16.871961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27214 10:16:16.872505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27216 10:16:16.918399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27217 10:16:16.918839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27219 10:16:16.959260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27220 10:16:16.959678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27222 10:16:17.000944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27224 10:16:17.001513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27225 10:16:17.043434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27227 10:16:17.043902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27228 10:16:17.082552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27229 10:16:17.083010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27231 10:16:17.122372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27232 10:16:17.122799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27234 10:16:17.166515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27235 10:16:17.166955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27237 10:16:17.207352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27238 10:16:17.207793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27240 10:16:17.254736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27241 10:16:17.255188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27243 10:16:17.303502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27244 10:16:17.304050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27246 10:16:17.349102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27248 10:16:17.349574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27249 10:16:17.394507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27250 10:16:17.394910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27252 10:16:17.440692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27253 10:16:17.441112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27255 10:16:17.481375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27257 10:16:17.481807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27258 10:16:17.528163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27260 10:16:17.528539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27261 10:16:17.573629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27262 10:16:17.574104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27264 10:16:17.621808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27266 10:16:17.622221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27267 10:16:17.662636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27269 10:16:17.663119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27270 10:16:17.706759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27271 10:16:17.707198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27273 10:16:17.747091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27274 10:16:17.747480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27276 10:16:17.797356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27278 10:16:17.797792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27279 10:16:17.837767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27280 10:16:17.838187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27282 10:16:17.883519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27283 10:16:17.883977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27285 10:16:17.925605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27286 10:16:17.926106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27288 10:16:17.981051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27290 10:16:17.981454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27291 10:16:18.034603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27292 10:16:18.035156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27294 10:16:18.083119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27295 10:16:18.083660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27297 10:16:18.121786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27298 10:16:18.122207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27300 10:16:18.166969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27301 10:16:18.167345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27303 10:16:18.211569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27304 10:16:18.211961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27306 10:16:18.249374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27308 10:16:18.249855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27309 10:16:18.286620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27310 10:16:18.287056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27312 10:16:18.323157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27314 10:16:18.323932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27315 10:16:18.361602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27316 10:16:18.362065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27318 10:16:18.413116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27320 10:16:18.413926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27321 10:16:18.470204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27322 10:16:18.470696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27324 10:16:18.526591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27325 10:16:18.527107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27327 10:16:18.582553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27328 10:16:18.582964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27330 10:16:18.616995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27332 10:16:18.617443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27333 10:16:18.654552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27335 10:16:18.655277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27336 10:16:18.696583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27337 10:16:18.697002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27339 10:16:18.747648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27340 10:16:18.748076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27342 10:16:18.794715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27343 10:16:18.795214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27345 10:16:18.844552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27346 10:16:18.844999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27348 10:16:18.893513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27350 10:16:18.894130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27351 10:16:18.942706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27352 10:16:18.943166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27354 10:16:18.984115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27356 10:16:18.984643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27357 10:16:19.022307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27358 10:16:19.022718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27360 10:16:19.066837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27361 10:16:19.067302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27363 10:16:19.111509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27364 10:16:19.112054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27366 10:16:19.164870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27368 10:16:19.165242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27369 10:16:19.215129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27370 10:16:19.215594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27372 10:16:19.255217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27373 10:16:19.255702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27375 10:16:19.291146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27376 10:16:19.291539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27378 10:16:19.328910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27380 10:16:19.329355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27381 10:16:19.382018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27383 10:16:19.382723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27384 10:16:19.435873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27385 10:16:19.436357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27387 10:16:19.482453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27388 10:16:19.482911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27390 10:16:19.526245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27391 10:16:19.526707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27393 10:16:19.571463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27394 10:16:19.571844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27396 10:16:19.613837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27397 10:16:19.614348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27399 10:16:19.683754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27400 10:16:19.684182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27402 10:16:19.734270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27403 10:16:19.734703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27405 10:16:19.782913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27406 10:16:19.783308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27408 10:16:19.833486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27409 10:16:19.833931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27411 10:16:19.876635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27412 10:16:19.877069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27414 10:16:19.925524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27415 10:16:19.925969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27417 10:16:19.967162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27418 10:16:19.967579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27420 10:16:20.008113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27421 10:16:20.008559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27423 10:16:20.053774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27424 10:16:20.054215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27426 10:16:20.094223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27428 10:16:20.094759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27429 10:16:20.133801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27430 10:16:20.134190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27432 10:16:20.180424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27434 10:16:20.180844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27435 10:16:20.220048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27436 10:16:20.220472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27438 10:16:20.259632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27440 10:16:20.260092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27441 10:16:20.299628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27442 10:16:20.300050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27444 10:16:20.343657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27445 10:16:20.344080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27447 10:16:20.388596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27448 10:16:20.388987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27450 10:16:20.432147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27451 10:16:20.432573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27453 10:16:20.474107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27455 10:16:20.474529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27456 10:16:20.514644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27457 10:16:20.515065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27459 10:16:20.555042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27460 10:16:20.555459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27462 10:16:20.595290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27463 10:16:20.595729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27465 10:16:20.636584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27466 10:16:20.637103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27468 10:16:20.678648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27470 10:16:20.679267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27471 10:16:20.719888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27473 10:16:20.720637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27474 10:16:20.764258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27476 10:16:20.765005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27477 10:16:20.807218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27479 10:16:20.807612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27480 10:16:20.850495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27482 10:16:20.851239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27483 10:16:20.894439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27484 10:16:20.894931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27486 10:16:20.935307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27487 10:16:20.935810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27489 10:16:20.982876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27490 10:16:20.983300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27492 10:16:21.028338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27494 10:16:21.028753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27495 10:16:21.079878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27497 10:16:21.080275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27498 10:16:21.131565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27499 10:16:21.132010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27501 10:16:21.181971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27503 10:16:21.182457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27504 10:16:21.227067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27506 10:16:21.227529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27507 10:16:21.272130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27508 10:16:21.272538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27510 10:16:21.314234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27511 10:16:21.314753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27513 10:16:21.359303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27515 10:16:21.360044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27516 10:16:21.402978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27518 10:16:21.403728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27519 10:16:21.447965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27520 10:16:21.448455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27522 10:16:21.493014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27524 10:16:21.493718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27525 10:16:21.532691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27526 10:16:21.533208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27528 10:16:21.568117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27529 10:16:21.568573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27531 10:16:21.605455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27532 10:16:21.605918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27534 10:16:21.643112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27535 10:16:21.643555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27537 10:16:21.686844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27538 10:16:21.687302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27540 10:16:21.725030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27542 10:16:21.725706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27543 10:16:21.773714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27544 10:16:21.774196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27546 10:16:21.814566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27547 10:16:21.814977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27549 10:16:21.871664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27550 10:16:21.872155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27552 10:16:21.917567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27553 10:16:21.917972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27555 10:16:21.953724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27556 10:16:21.954152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27558 10:16:21.997191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27560 10:16:21.997679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27561 10:16:22.043806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27562 10:16:22.044236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27564 10:16:22.098836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27566 10:16:22.099313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27567 10:16:22.144590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27569 10:16:22.145075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27570 10:16:22.192872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27572 10:16:22.193492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27573 10:16:22.238320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27575 10:16:22.238746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27576 10:16:22.287555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27577 10:16:22.287963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27579 10:16:22.332556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27580 10:16:22.332985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27582 10:16:22.383790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27583 10:16:22.384230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27585 10:16:22.435224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27586 10:16:22.435682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27588 10:16:22.487019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27589 10:16:22.487481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27591 10:16:22.536713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27593 10:16:22.537202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27594 10:16:22.586554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27595 10:16:22.586986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27597 10:16:22.635927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27598 10:16:22.636312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27600 10:16:22.686628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27602 10:16:22.687108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27603 10:16:22.739594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27604 10:16:22.740105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27606 10:16:22.794946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27607 10:16:22.795495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27609 10:16:22.842190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27610 10:16:22.842645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27612 10:16:22.883463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27614 10:16:22.883936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27615 10:16:22.923760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27617 10:16:22.924226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27618 10:16:22.963659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27620 10:16:22.964113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27621 10:16:23.017086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27623 10:16:23.017535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27624 10:16:23.067036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27625 10:16:23.067448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27627 10:16:23.116332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27628 10:16:23.116773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27630 10:16:23.166649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27632 10:16:23.168101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27633 10:16:23.217616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27635 10:16:23.218106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27636 10:16:23.262984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27638 10:16:23.263644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27639 10:16:23.305148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27641 10:16:23.305606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27642 10:16:23.350459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27643 10:16:23.350886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27645 10:16:23.390624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27647 10:16:23.391087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27648 10:16:23.427118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27649 10:16:23.427562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27651 10:16:23.463907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27653 10:16:23.464289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27654 10:16:23.507476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27655 10:16:23.507922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27657 10:16:23.548807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27658 10:16:23.549228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27660 10:16:23.589975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27661 10:16:23.590430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27663 10:16:23.634066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27664 10:16:23.634620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27666 10:16:23.680298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27667 10:16:23.680761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27669 10:16:23.731926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27670 10:16:23.732357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27672 10:16:23.778738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27673 10:16:23.779170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27675 10:16:23.823090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27676 10:16:23.823584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27678 10:16:23.863162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27679 10:16:23.863708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27681 10:16:23.906120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27682 10:16:23.906567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27684 10:16:23.942816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27685 10:16:23.943275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27687 10:16:23.978519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27689 10:16:23.978980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27690 10:16:24.014709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27691 10:16:24.015130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27693 10:16:24.050411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27695 10:16:24.050878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27696 10:16:24.087224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27698 10:16:24.087998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27699 10:16:24.133812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27701 10:16:24.134371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27702 10:16:24.171505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27703 10:16:24.171983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27705 10:16:24.207576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27706 10:16:24.207987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27708 10:16:24.243107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27709 10:16:24.243552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27711 10:16:24.288244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27712 10:16:24.288752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27714 10:16:24.337664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27716 10:16:24.338068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27717 10:16:24.388222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27718 10:16:24.388797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27720 10:16:24.431784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27721 10:16:24.432242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27723 10:16:24.478953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27724 10:16:24.479450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27726 10:16:24.526609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27727 10:16:24.527028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27729 10:16:24.570871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27731 10:16:24.571289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27732 10:16:24.605415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27733 10:16:24.605842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27735 10:16:24.652458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27736 10:16:24.653019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27738 10:16:24.710141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27739 10:16:24.710569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27741 10:16:24.758862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27742 10:16:24.759303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27744 10:16:24.815122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27745 10:16:24.815534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27747 10:16:24.850112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27748 10:16:24.850592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27750 10:16:24.890101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27751 10:16:24.890575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27753 10:16:24.933919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27754 10:16:24.934339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27756 10:16:24.983517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27757 10:16:24.983936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27759 10:16:25.022289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27760 10:16:25.022717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27762 10:16:25.062779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27764 10:16:25.063238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27765 10:16:25.098164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27766 10:16:25.098589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27768 10:16:25.134625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27769 10:16:25.134995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27771 10:16:25.170431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27772 10:16:25.170926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27774 10:16:25.214711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27776 10:16:25.215355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27777 10:16:25.254601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27779 10:16:25.255246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27780 10:16:25.292354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27781 10:16:25.292790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27783 10:16:25.326169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27784 10:16:25.326649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27786 10:16:25.362218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27787 10:16:25.362734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27789 10:16:25.399681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27790 10:16:25.400227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27792 10:16:25.434598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27793 10:16:25.435086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27795 10:16:25.470141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27796 10:16:25.470597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27798 10:16:25.511855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27800 10:16:25.512313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27801 10:16:25.554783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27802 10:16:25.555202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27804 10:16:25.591513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27805 10:16:25.591929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27807 10:16:25.626282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27808 10:16:25.626724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27810 10:16:25.674248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27811 10:16:25.674680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27813 10:16:25.715552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27815 10:16:25.716322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27816 10:16:25.752268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27817 10:16:25.752801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27819 10:16:25.792089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27820 10:16:25.792552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27822 10:16:25.836525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27823 10:16:25.836938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27825 10:16:25.883801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27826 10:16:25.884245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27828 10:16:25.937404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27830 10:16:25.937872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27831 10:16:25.988271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27833 10:16:25.988751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27834 10:16:26.030579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27835 10:16:26.031005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27837 10:16:26.082969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27839 10:16:26.083454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27840 10:16:26.127008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27842 10:16:26.127428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27843 10:16:26.169883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27845 10:16:26.170345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27846 10:16:26.205914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27848 10:16:26.206377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27849 10:16:26.242743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27850 10:16:26.243167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27852 10:16:26.287754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27853 10:16:26.288320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27855 10:16:26.334774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27856 10:16:26.335268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27858 10:16:26.382952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27860 10:16:26.383375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27861 10:16:26.418363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27862 10:16:26.418856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27864 10:16:26.456473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27865 10:16:26.457026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27867 10:16:26.504659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27868 10:16:26.505172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27870 10:16:26.548428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27871 10:16:26.549006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27873 10:16:26.584899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27875 10:16:26.585298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27876 10:16:26.628052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27878 10:16:26.628511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27879 10:16:26.669805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27880 10:16:26.670218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27882 10:16:26.706842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27884 10:16:26.707231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27885 10:16:26.744263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27886 10:16:26.744654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27888 10:16:26.788337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27889 10:16:26.788731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27891 10:16:26.824701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27892 10:16:26.825129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27894 10:16:26.867181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27895 10:16:26.867599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27897 10:16:26.903538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27898 10:16:26.903961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27900 10:16:26.947766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27901 10:16:26.948173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27903 10:16:26.984559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27904 10:16:26.985118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27906 10:16:27.020601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27907 10:16:27.021078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27909 10:16:27.074600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27910 10:16:27.074999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27912 10:16:27.119571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27914 10:16:27.119995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27915 10:16:27.158321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27916 10:16:27.158757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27918 10:16:27.197048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27920 10:16:27.197517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27921 10:16:27.233685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27922 10:16:27.234266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27924 10:16:27.278995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
27926 10:16:27.279452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27927 10:16:27.314259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
27928 10:16:27.314674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
27930 10:16:27.356696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
27931 10:16:27.357128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
27933 10:16:27.399408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
27935 10:16:27.399874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
27936 10:16:27.443212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
27937 10:16:27.443633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
27939 10:16:27.487821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
27940 10:16:27.488237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
27942 10:16:27.531908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
27944 10:16:27.532390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
27945 10:16:27.574839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
27947 10:16:27.575253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
27948 10:16:27.610495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
27950 10:16:27.610965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
27951 10:16:27.646269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
27953 10:16:27.646727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
27954 10:16:27.682039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
27956 10:16:27.682480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
27957 10:16:27.727450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
27958 10:16:27.727824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
27960 10:16:27.772675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
27961 10:16:27.773091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
27963 10:16:27.812048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
27964 10:16:27.812461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
27966 10:16:27.846989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
27967 10:16:27.847385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
27969 10:16:27.882472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
27970 10:16:27.882914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
27972 10:16:27.928273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
27974 10:16:27.928740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
27975 10:16:27.978731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
27977 10:16:27.979399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
27978 10:16:28.020365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
27979 10:16:28.020800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
27981 10:16:28.058713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
27983 10:16:28.059179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
27984 10:16:28.096041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
27985 10:16:28.096488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
27987 10:16:28.138443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
27989 10:16:28.138891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
27990 10:16:28.174943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
27991 10:16:28.175455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
27993 10:16:28.215076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
27994 10:16:28.215486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
27996 10:16:28.251509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
27998 10:16:28.251909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
27999 10:16:28.289982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
28001 10:16:28.290681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
28002 10:16:28.329581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
28003 10:16:28.330015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
28005 10:16:28.371757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
28006 10:16:28.372192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
28008 10:16:28.406686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
28009 10:16:28.407075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
28011 10:16:28.439029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
28013 10:16:28.439760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
28014 10:16:28.472384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
28016 10:16:28.472855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
28017 10:16:28.506663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
28018 10:16:28.507087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
28020 10:16:28.550763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
28021 10:16:28.551203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
28023 10:16:28.591777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
28024 10:16:28.592224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
28026 10:16:28.627398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
28027 10:16:28.627845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
28029 10:16:28.663060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
28030 10:16:28.663505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
28032 10:16:28.699611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
28033 10:16:28.700053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
28035 10:16:28.739786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
28036 10:16:28.740196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
28038 10:16:28.782626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
28039 10:16:28.782989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
28041 10:16:28.796419 <47>[ 308.488815] systemd-journald[105]: Sent WATCHDOG=1 notification.
28042 10:16:28.825455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
28043 10:16:28.825877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
28045 10:16:28.861525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
28046 10:16:28.862017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
28048 10:16:28.899311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
28050 10:16:28.899849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
28051 10:16:28.935491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
28053 10:16:28.935960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
28054 10:16:28.972272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
28056 10:16:28.972727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
28057 10:16:29.015028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
28058 10:16:29.015478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
28060 10:16:29.059995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
28062 10:16:29.060775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
28063 10:16:29.104820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
28065 10:16:29.105250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
28066 10:16:29.149651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
28067 10:16:29.150029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
28069 10:16:29.198259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
28070 10:16:29.198864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
28072 10:16:29.246537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
28073 10:16:29.246949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
28075 10:16:29.289698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
28076 10:16:29.290246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
28078 10:16:29.328950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
28080 10:16:29.329365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
28081 10:16:29.376233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
28082 10:16:29.376667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
28084 10:16:29.424111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
28086 10:16:29.424640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
28087 10:16:29.473250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
28088 10:16:29.473689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
28090 10:16:29.510518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
28091 10:16:29.510936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
28093 10:16:29.546743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
28094 10:16:29.547244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
28096 10:16:29.586123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
28097 10:16:29.586500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
28099 10:16:29.621715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
28101 10:16:29.622181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
28102 10:16:29.661808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
28103 10:16:29.662249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
28105 10:16:29.703931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
28106 10:16:29.704353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
28108 10:16:29.745577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
28109 10:16:29.746031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
28111 10:16:29.782814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
28112 10:16:29.783260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
28114 10:16:29.815958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
28115 10:16:29.816403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
28117 10:16:29.849168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
28118 10:16:29.849608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
28120 10:16:29.910068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
28122 10:16:29.910529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
28123 10:16:29.949369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
28124 10:16:29.949783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
28126 10:16:29.983008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
28127 10:16:29.983531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
28129 10:16:30.020219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
28130 10:16:30.020674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
28132 10:16:30.066205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
28134 10:16:30.067580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
28135 10:16:30.105389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
28136 10:16:30.105835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
28138 10:16:30.146892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
28139 10:16:30.147289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
28141 10:16:30.188919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
28142 10:16:30.189357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
28144 10:16:30.233231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
28145 10:16:30.233706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
28147 10:16:30.274422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
28148 10:16:30.274902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
28150 10:16:30.313985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
28152 10:16:30.314613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
28153 10:16:30.350269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
28154 10:16:30.350709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
28156 10:16:30.385792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
28157 10:16:30.386276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
28159 10:16:30.426166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
28161 10:16:30.426844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
28162 10:16:30.461717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
28164 10:16:30.462175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
28165 10:16:30.504776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
28167 10:16:30.505246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
28168 10:16:30.546790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
28170 10:16:30.547248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
28171 10:16:30.591336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28173 10:16:30.591805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28174 10:16:30.628527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28175 10:16:30.628918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28177 10:16:30.665485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28178 10:16:30.665976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28180 10:16:30.699511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28181 10:16:30.699997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28183 10:16:30.736151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28185 10:16:30.736607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28186 10:16:30.773715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28187 10:16:30.774217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28189 10:16:30.824248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28190 10:16:30.824681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28192 10:16:30.858811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28193 10:16:30.859280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28195 10:16:30.909742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28196 10:16:30.910233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28198 10:16:30.952344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28200 10:16:30.952817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28201 10:16:30.994363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28203 10:16:30.995081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28204 10:16:31.041841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28205 10:16:31.042268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28207 10:16:31.079469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28209 10:16:31.079913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28210 10:16:31.129031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28212 10:16:31.129508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28213 10:16:31.168443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28214 10:16:31.168827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28216 10:16:31.211060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28218 10:16:31.211517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28219 10:16:31.250422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28221 10:16:31.250931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28222 10:16:31.288521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28223 10:16:31.288943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28225 10:16:31.324622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28227 10:16:31.325082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28228 10:16:31.361465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28229 10:16:31.361832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28231 10:16:31.397552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28232 10:16:31.398009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28234 10:16:31.437892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28235 10:16:31.438281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28237 10:16:31.474676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28238 10:16:31.475192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28240 10:16:31.510416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28241 10:16:31.510858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28243 10:16:31.545764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28244 10:16:31.546202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28246 10:16:31.585485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28247 10:16:31.586150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28249 10:16:31.622035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28251 10:16:31.622497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28252 10:16:31.656699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28254 10:16:31.657169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28255 10:16:31.691197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28256 10:16:31.691680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28258 10:16:31.725350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28260 10:16:31.725813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28261 10:16:31.763100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28263 10:16:31.763556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28264 10:16:31.797897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28266 10:16:31.798356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28267 10:16:31.831866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28268 10:16:31.832280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28270 10:16:31.867427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28272 10:16:31.867889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28273 10:16:31.902964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28274 10:16:31.903383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28276 10:16:31.939564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28278 10:16:31.940014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28279 10:16:31.975735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28280 10:16:31.976195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28282 10:16:32.011216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28283 10:16:32.011744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28285 10:16:32.058825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28286 10:16:32.059236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28288 10:16:32.106918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28289 10:16:32.107358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28291 10:16:32.146156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28292 10:16:32.146607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28294 10:16:32.187341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28296 10:16:32.187794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28297 10:16:32.230173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28299 10:16:32.230633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28300 10:16:32.274506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28302 10:16:32.274978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28303 10:16:32.324165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28304 10:16:32.324549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28306 10:16:32.368638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28308 10:16:32.369385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28309 10:16:32.413795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28310 10:16:32.414230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28312 10:16:32.455871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28314 10:16:32.456342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28315 10:16:32.489993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28317 10:16:32.490472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28318 10:16:32.532956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28320 10:16:32.533613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28321 10:16:32.587577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28322 10:16:32.587980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28324 10:16:32.644255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28326 10:16:32.644887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28327 10:16:32.698465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28328 10:16:32.698981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28330 10:16:32.740672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28331 10:16:32.741099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28333 10:16:32.789792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28334 10:16:32.790309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28336 10:16:32.831434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28337 10:16:32.831974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28339 10:16:32.879055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28340 10:16:32.879468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28342 10:16:32.922488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28343 10:16:32.922930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28345 10:16:32.970432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28347 10:16:32.970883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28348 10:16:33.006003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28349 10:16:33.006430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28351 10:16:33.049724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28352 10:16:33.050151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28354 10:16:33.091920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28355 10:16:33.092485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28357 10:16:33.136327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28359 10:16:33.137092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28360 10:16:33.172460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28361 10:16:33.173022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28363 10:16:33.222022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28365 10:16:33.222666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28366 10:16:33.269107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28368 10:16:33.269839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28369 10:16:33.310948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28371 10:16:33.311404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28372 10:16:33.347013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28374 10:16:33.347470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28375 10:16:33.384121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28377 10:16:33.384792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28378 10:16:33.419345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28380 10:16:33.420073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28381 10:16:33.455218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28382 10:16:33.455750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28384 10:16:33.490605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28385 10:16:33.491156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28387 10:16:33.525959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28388 10:16:33.526526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28390 10:16:33.563444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28391 10:16:33.563929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28393 10:16:33.599386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28394 10:16:33.599808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28396 10:16:33.635589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28397 10:16:33.636010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28399 10:16:33.671640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28400 10:16:33.672182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28402 10:16:33.711524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28403 10:16:33.711962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28405 10:16:33.756263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28406 10:16:33.756693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28408 10:16:33.798564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28410 10:16:33.799016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28411 10:16:33.844472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28413 10:16:33.844943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28414 10:16:33.889811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28415 10:16:33.890200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28417 10:16:33.932828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28419 10:16:33.933306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28420 10:16:33.969987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28422 10:16:33.970463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28423 10:16:34.010081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28424 10:16:34.010498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28426 10:16:34.046479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28428 10:16:34.046948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28429 10:16:34.086511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28430 10:16:34.086891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28432 10:16:34.126449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28434 10:16:34.126880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28435 10:16:34.165790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28437 10:16:34.166502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28438 10:16:34.219508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28439 10:16:34.219919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28441 10:16:34.262346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28443 10:16:34.262736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28444 10:16:34.299545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28445 10:16:34.299987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28447 10:16:34.344296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28449 10:16:34.344915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28450 10:16:34.378667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28451 10:16:34.379070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28453 10:16:34.419502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28454 10:16:34.419911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28456 10:16:34.460433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28458 10:16:34.460902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28459 10:16:34.503717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28461 10:16:34.504384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28462 10:16:34.539149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28463 10:16:34.539570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28465 10:16:34.575204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28466 10:16:34.575555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28468 10:16:34.614478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28470 10:16:34.614870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28471 10:16:34.651811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28472 10:16:34.652339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28474 10:16:34.687912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28475 10:16:34.688298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28477 10:16:34.723612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28478 10:16:34.724022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28480 10:16:34.759345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28481 10:16:34.759774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28483 10:16:34.806229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28484 10:16:34.806681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28486 10:16:34.862791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28487 10:16:34.863158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28489 10:16:34.898365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28490 10:16:34.898788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28492 10:16:34.941697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28494 10:16:34.942354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28495 10:16:34.986581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28496 10:16:34.987081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28498 10:16:35.050444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28499 10:16:35.050950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28501 10:16:35.095083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28502 10:16:35.095644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28504 10:16:35.138929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28505 10:16:35.139408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28507 10:16:35.178852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28509 10:16:35.179556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28510 10:16:35.224187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28512 10:16:35.224877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28513 10:16:35.271130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28514 10:16:35.271553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28516 10:16:35.308137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28517 10:16:35.308622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28519 10:16:35.351337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28520 10:16:35.351741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28522 10:16:35.391204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28523 10:16:35.391621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28525 10:16:35.431172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28526 10:16:35.431589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28528 10:16:35.473424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28529 10:16:35.473870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28531 10:16:35.510027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28533 10:16:35.510442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28534 10:16:35.546379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28535 10:16:35.546841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28537 10:16:35.590960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28538 10:16:35.591468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28540 10:16:35.634718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28541 10:16:35.635152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28543 10:16:35.680341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28544 10:16:35.680825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28546 10:16:35.725255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28547 10:16:35.725688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28549 10:16:35.771285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28550 10:16:35.771840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28552 10:16:35.814397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28553 10:16:35.814900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28555 10:16:35.859692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28556 10:16:35.860140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28558 10:16:35.904480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28559 10:16:35.904895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28561 10:16:35.950261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28562 10:16:35.950682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28564 10:16:35.997817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28566 10:16:35.998577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28567 10:16:36.047773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28569 10:16:36.048173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28570 10:16:36.098110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28572 10:16:36.098606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28573 10:16:36.146452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28574 10:16:36.146934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28576 10:16:36.194586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28578 10:16:36.194954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28579 10:16:36.242942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28580 10:16:36.243421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28582 10:16:36.294638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28584 10:16:36.295371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28585 10:16:36.338308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28587 10:16:36.338781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28588 10:16:36.374027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28590 10:16:36.374487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28591 10:16:36.409329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28593 10:16:36.409780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28594 10:16:36.444902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28596 10:16:36.445347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28597 10:16:36.482060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28599 10:16:36.482507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28600 10:16:36.518215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28601 10:16:36.518641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28603 10:16:36.556205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28605 10:16:36.556670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28606 10:16:36.592181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28607 10:16:36.592601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28609 10:16:36.626857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28610 10:16:36.627273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28612 10:16:36.661261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28613 10:16:36.661815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28615 10:16:36.698418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28616 10:16:36.698887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28618 10:16:36.735253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28619 10:16:36.735748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28621 10:16:36.772427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28623 10:16:36.772793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28624 10:16:36.820660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28625 10:16:36.821075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28627 10:16:36.862667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28629 10:16:36.863055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28630 10:16:36.907015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28632 10:16:36.907418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28633 10:16:36.956421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28634 10:16:36.956920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28636 10:16:37.006530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28638 10:16:37.006993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28639 10:16:37.045857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28640 10:16:37.046287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28642 10:16:37.083463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28643 10:16:37.083867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28645 10:16:37.128075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28647 10:16:37.128508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28648 10:16:37.168208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28649 10:16:37.168533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28651 10:16:37.208503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28652 10:16:37.208952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28654 10:16:37.251933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28655 10:16:37.252415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28657 10:16:37.290258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28659 10:16:37.290715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28660 10:16:37.326188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28661 10:16:37.326615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28663 10:16:37.364695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28665 10:16:37.365198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28666 10:16:37.408886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28668 10:16:37.409392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28669 10:16:37.448327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28670 10:16:37.448814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28672 10:16:37.487891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28673 10:16:37.488210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28675 10:16:37.525412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28676 10:16:37.525952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28678 10:16:37.566204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28679 10:16:37.566707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28681 10:16:37.602477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28683 10:16:37.603037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28684 10:16:37.639055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28685 10:16:37.639535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28687 10:16:37.674950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28688 10:16:37.675390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28690 10:16:37.717406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28691 10:16:37.717816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28693 10:16:37.762363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28695 10:16:37.762819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28696 10:16:37.808139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28697 10:16:37.808538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28699 10:16:37.855667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28700 10:16:37.856070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28702 10:16:37.897266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28703 10:16:37.897774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28705 10:16:37.934525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28706 10:16:37.934924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28708 10:16:37.981890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28710 10:16:37.982528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28711 10:16:38.026110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28712 10:16:38.026549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28714 10:16:38.066580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28715 10:16:38.067008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28717 10:16:38.111062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28718 10:16:38.111628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28720 10:16:38.149890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28722 10:16:38.150515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28723 10:16:38.188485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28724 10:16:38.189003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28726 10:16:38.227006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28728 10:16:38.227435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28729 10:16:38.266947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28730 10:16:38.267328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28732 10:16:38.312920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28734 10:16:38.313364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28735 10:16:38.353538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28736 10:16:38.353958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28738 10:16:38.394327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28739 10:16:38.394731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28741 10:16:38.432466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28743 10:16:38.432903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28744 10:16:38.469584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28746 10:16:38.470015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28747 10:16:38.507705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28748 10:16:38.508091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28750 10:16:38.547508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28751 10:16:38.548026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28753 10:16:38.592588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28755 10:16:38.593051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28756 10:16:38.632238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28758 10:16:38.632634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28759 10:16:38.675289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28761 10:16:38.675747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28762 10:16:38.715676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28763 10:16:38.716113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28765 10:16:38.753658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28766 10:16:38.754072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28768 10:16:38.803004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28769 10:16:38.803437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28771 10:16:38.850957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28772 10:16:38.851374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28774 10:16:38.895135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28776 10:16:38.895881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28777 10:16:38.938508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28778 10:16:38.938918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28780 10:16:38.980069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28782 10:16:38.980579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28783 10:16:39.019188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28784 10:16:39.019666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28786 10:16:39.062566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28787 10:16:39.063118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28789 10:16:39.106604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28791 10:16:39.107287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28792 10:16:39.148222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28793 10:16:39.148742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28795 10:16:39.183456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28796 10:16:39.183885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28798 10:16:39.218167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28800 10:16:39.218585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28801 10:16:39.255623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28802 10:16:39.256134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28804 10:16:39.290791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28806 10:16:39.291373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28807 10:16:39.326208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28808 10:16:39.326744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28810 10:16:39.361574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28811 10:16:39.361992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28813 10:16:39.398239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28815 10:16:39.398700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28816 10:16:39.437953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28817 10:16:39.438377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28819 10:16:39.474304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28820 10:16:39.474817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28822 10:16:39.508718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28823 10:16:39.509199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28825 10:16:39.552016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28826 10:16:39.552437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28828 10:16:39.594110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28829 10:16:39.594541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28831 10:16:39.634287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28833 10:16:39.634993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28834 10:16:39.679784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28835 10:16:39.680237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28837 10:16:39.715798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28838 10:16:39.716212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28840 10:16:39.760362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28842 10:16:39.760833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28843 10:16:39.811059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28844 10:16:39.811459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28846 10:16:39.863100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28848 10:16:39.863471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28849 10:16:39.899952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28850 10:16:39.900322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28852 10:16:39.954022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28854 10:16:39.954575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28855 10:16:40.006704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28857 10:16:40.007144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28858 10:16:40.043618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28859 10:16:40.044056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28861 10:16:40.083796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28862 10:16:40.084222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28864 10:16:40.146017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28865 10:16:40.146471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28867 10:16:40.182741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28868 10:16:40.183207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28870 10:16:40.218233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28871 10:16:40.218783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28873 10:16:40.265135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28875 10:16:40.265601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28876 10:16:40.309571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28877 10:16:40.310016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28879 10:16:40.345415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28881 10:16:40.345892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28882 10:16:40.380472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28883 10:16:40.380919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28885 10:16:40.421870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28886 10:16:40.422314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28888 10:16:40.468362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28889 10:16:40.468802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28891 10:16:40.517045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28893 10:16:40.517507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28894 10:16:40.554562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28895 10:16:40.555058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28897 10:16:40.596569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28898 10:16:40.596962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28900 10:16:40.633929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28901 10:16:40.634449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28903 10:16:40.673374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28904 10:16:40.673820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28906 10:16:40.710710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28907 10:16:40.711247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28909 10:16:40.746862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28911 10:16:40.747326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28912 10:16:40.788121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28913 10:16:40.788555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28915 10:16:40.843914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28916 10:16:40.844355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28918 10:16:40.896646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28919 10:16:40.897039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28921 10:16:40.950526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28922 10:16:40.951007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28924 10:16:41.005951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28925 10:16:41.006359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28927 10:16:41.047297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
28928 10:16:41.047712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
28930 10:16:41.086115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
28932 10:16:41.086589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
28933 10:16:41.134350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
28934 10:16:41.134766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
28936 10:16:41.171669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
28937 10:16:41.172047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
28939 10:16:41.213712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
28940 10:16:41.214101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
28942 10:16:41.258154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
28943 10:16:41.258648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
28945 10:16:41.298771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
28946 10:16:41.299190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
28948 10:16:41.339719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
28949 10:16:41.340116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
28951 10:16:41.379619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
28952 10:16:41.380045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
28954 10:16:41.419572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
28955 10:16:41.420006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
28957 10:16:41.460618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
28959 10:16:41.461075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
28960 10:16:41.498403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
28962 10:16:41.498861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
28963 10:16:41.538737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
28965 10:16:41.539189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
28966 10:16:41.578190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
28968 10:16:41.578650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
28969 10:16:41.618858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
28971 10:16:41.619361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
28972 10:16:41.655121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
28974 10:16:41.655692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
28975 10:16:41.689063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
28977 10:16:41.689687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
28978 10:16:41.722868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
28979 10:16:41.723292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
28981 10:16:41.759460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
28982 10:16:41.759879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
28984 10:16:41.802319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
28985 10:16:41.802734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
28987 10:16:41.838874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
28988 10:16:41.839319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
28990 10:16:41.874798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
28992 10:16:41.875256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
28993 10:16:41.911789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
28994 10:16:41.912208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
28996 10:16:41.948476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
28997 10:16:41.948900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
28999 10:16:41.985391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
29000 10:16:41.986017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
29002 10:16:42.028792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
29003 10:16:42.029336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
29005 10:16:42.078723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
29007 10:16:42.079126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
29008 10:16:42.126310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
29009 10:16:42.126847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
29011 10:16:42.165779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
29012 10:16:42.166194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
29014 10:16:42.200131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
29015 10:16:42.200675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
29017 10:16:42.236449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
29019 10:16:42.237012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
29020 10:16:42.274207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
29022 10:16:42.274870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
29023 10:16:42.318607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
29024 10:16:42.319077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
29026 10:16:42.363611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
29027 10:16:42.364068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
29029 10:16:42.406052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
29030 10:16:42.406484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
29032 10:16:42.446455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
29033 10:16:42.446958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
29035 10:16:42.484970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
29037 10:16:42.485510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
29038 10:16:42.530227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
29039 10:16:42.530656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
29041 10:16:42.574852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
29042 10:16:42.575276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
29044 10:16:42.618707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
29045 10:16:42.619135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
29047 10:16:42.667367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
29048 10:16:42.667815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
29050 10:16:42.712031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
29051 10:16:42.712464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
29053 10:16:42.762808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
29054 10:16:42.763242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
29056 10:16:42.818481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
29058 10:16:42.819170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
29059 10:16:42.873680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
29060 10:16:42.874105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
29062 10:16:42.925036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
29064 10:16:42.925490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
29065 10:16:42.966053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
29066 10:16:42.966485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
29068 10:16:43.005062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
29070 10:16:43.005519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
29071 10:16:43.039301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
29072 10:16:43.039742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
29074 10:16:43.074250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
29075 10:16:43.074636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
29077 10:16:43.108509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
29078 10:16:43.108936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
29080 10:16:43.147743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
29082 10:16:43.148311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
29083 10:16:43.185421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
29084 10:16:43.185912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
29086 10:16:43.218004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
29087 10:16:43.218494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
29089 10:16:43.254959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
29091 10:16:43.255414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
29092 10:16:43.295745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
29093 10:16:43.296160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
29095 10:16:43.335024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
29096 10:16:43.335458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
29098 10:16:43.368249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
29099 10:16:43.368685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
29101 10:16:43.406200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
29102 10:16:43.406622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
29104 10:16:43.440659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
29105 10:16:43.441066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
29107 10:16:43.481319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
29108 10:16:43.481868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
29110 10:16:43.523305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
29111 10:16:43.523826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
29113 10:16:43.567171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
29114 10:16:43.567592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
29116 10:16:43.610204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
29117 10:16:43.610801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
29119 10:16:43.646796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
29120 10:16:43.647257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
29122 10:16:43.682192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
29123 10:16:43.682644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
29125 10:16:43.720509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
29126 10:16:43.720960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
29128 10:16:43.754866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
29129 10:16:43.755255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
29131 10:16:43.798429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
29132 10:16:43.798834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
29134 10:16:43.847770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
29136 10:16:43.848369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
29137 10:16:43.888820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
29138 10:16:43.889186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
29140 10:16:43.926514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
29142 10:16:43.926850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
29143 10:16:43.975851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
29144 10:16:43.976405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
29146 10:16:44.018388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
29147 10:16:44.018791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
29149 10:16:44.063269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
29151 10:16:44.063983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
29152 10:16:44.108479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
29154 10:16:44.108887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
29155 10:16:44.152616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
29156 10:16:44.153046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
29158 10:16:44.202155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
29160 10:16:44.202792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
29161 10:16:44.250396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
29162 10:16:44.250933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
29164 10:16:44.298181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
29166 10:16:44.298650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
29167 10:16:44.341016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
29169 10:16:44.341426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
29170 10:16:44.390881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
29171 10:16:44.391275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29173 10:16:44.432493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29174 10:16:44.432844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29176 10:16:44.473006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29178 10:16:44.473409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29179 10:16:44.520849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29181 10:16:44.521231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29182 10:16:44.563486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29183 10:16:44.563904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29185 10:16:44.610140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29186 10:16:44.610566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29188 10:16:44.651692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29190 10:16:44.652280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29191 10:16:44.693856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29192 10:16:44.694316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29194 10:16:44.738075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29196 10:16:44.738496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29197 10:16:44.783119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29199 10:16:44.783453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29200 10:16:44.827747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29201 10:16:44.828038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29203 10:16:44.866987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29204 10:16:44.867373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29206 10:16:44.906419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29207 10:16:44.906778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29209 10:16:44.947180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29210 10:16:44.947570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29212 10:16:44.988583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29214 10:16:44.989010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29215 10:16:45.030434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29216 10:16:45.030762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29218 10:16:45.078782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29219 10:16:45.079252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29221 10:16:45.116044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29223 10:16:45.116598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29224 10:16:45.152616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29225 10:16:45.153047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29227 10:16:45.190098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29229 10:16:45.190616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29230 10:16:45.227667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29232 10:16:45.228081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29233 10:16:45.287709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29235 10:16:45.288345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29236 10:16:45.331148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29237 10:16:45.331564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29239 10:16:45.375616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29240 10:16:45.376030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29242 10:16:45.414251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29243 10:16:45.414740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29245 10:16:45.454012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29247 10:16:45.454475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29248 10:16:45.496165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29249 10:16:45.496601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29251 10:16:45.531980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29252 10:16:45.532423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29254 10:16:45.569823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29255 10:16:45.570243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29257 10:16:45.613603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29259 10:16:45.614085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29260 10:16:45.650404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29262 10:16:45.650765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29263 10:16:45.694605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29264 10:16:45.695079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29266 10:16:45.738852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29267 10:16:45.739232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29269 10:16:45.785943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29270 10:16:45.786351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29272 10:16:45.834223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29273 10:16:45.834662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29275 10:16:45.881718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29277 10:16:45.882192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29278 10:16:45.928161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29279 10:16:45.928600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29281 10:16:45.981813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29282 10:16:45.982251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29284 10:16:46.034050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29285 10:16:46.034449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29287 10:16:46.090448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29289 10:16:46.090911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29290 10:16:46.143115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29291 10:16:46.143511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29293 10:16:46.188413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29295 10:16:46.188877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29296 10:16:46.236214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29298 10:16:46.236685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29299 10:16:46.287129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29301 10:16:46.287588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29302 10:16:46.332581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29303 10:16:46.333011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29305 10:16:46.376459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29306 10:16:46.376909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29308 10:16:46.417613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29309 10:16:46.418068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29311 10:16:46.458006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29312 10:16:46.458453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29314 10:16:46.497555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29315 10:16:46.497991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29317 10:16:46.545676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29318 10:16:46.546068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29320 10:16:46.590126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29321 10:16:46.590566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29323 10:16:46.637545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29324 10:16:46.637966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29326 10:16:46.683384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29328 10:16:46.684082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29329 10:16:46.721656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29330 10:16:46.722079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29332 10:16:46.758859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29333 10:16:46.759294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29335 10:16:46.797256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29336 10:16:46.797689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29338 10:16:46.840091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29340 10:16:46.840853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29341 10:16:46.882022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29342 10:16:46.882564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29344 10:16:46.927523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29345 10:16:46.927950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29347 10:16:46.969106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29349 10:16:46.969510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29350 10:16:47.012800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29352 10:16:47.013212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29353 10:16:47.058839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29354 10:16:47.059231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29356 10:16:47.102965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29357 10:16:47.103414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29359 10:16:47.144100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29360 10:16:47.144537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29362 10:16:47.181730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29363 10:16:47.182288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29365 10:16:47.218501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29366 10:16:47.218900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29368 10:16:47.258275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29370 10:16:47.258656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29371 10:16:47.299955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29372 10:16:47.300394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29374 10:16:47.343007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29376 10:16:47.343472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29377 10:16:47.386929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29379 10:16:47.387505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29380 10:16:47.438801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29382 10:16:47.439324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29383 10:16:47.484548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29385 10:16:47.485235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29386 10:16:47.529263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29387 10:16:47.529776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29389 10:16:47.577907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29390 10:16:47.578444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29392 10:16:47.616539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29394 10:16:47.617307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29395 10:16:47.654083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29396 10:16:47.654587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29398 10:16:47.690311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29399 10:16:47.690690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29401 10:16:47.727322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29402 10:16:47.727704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29404 10:16:47.763094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29405 10:16:47.763533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29407 10:16:47.799496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29408 10:16:47.799915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29410 10:16:47.835873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29411 10:16:47.836301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29413 10:16:47.880218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29415 10:16:47.880678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29416 10:16:47.917606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29418 10:16:47.918075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29419 10:16:47.960353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29420 10:16:47.960905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29422 10:16:47.998035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29423 10:16:47.998466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29425 10:16:48.046085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29426 10:16:48.046506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29428 10:16:48.089939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29429 10:16:48.090360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29431 10:16:48.129587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29433 10:16:48.130379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29434 10:16:48.164774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29436 10:16:48.165206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29437 10:16:48.202658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29439 10:16:48.203113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29440 10:16:48.239365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29442 10:16:48.239832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29443 10:16:48.279094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29444 10:16:48.279502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29446 10:16:48.322106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29447 10:16:48.322537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29449 10:16:48.370624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29450 10:16:48.371049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29452 10:16:48.418601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29453 10:16:48.419010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29455 10:16:48.466394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29456 10:16:48.466850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29458 10:16:48.502899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29459 10:16:48.503403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29461 10:16:48.540384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29462 10:16:48.540949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29464 10:16:48.583041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29465 10:16:48.583426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29467 10:16:48.638361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29468 10:16:48.638803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29470 10:16:48.690875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29471 10:16:48.691310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29473 10:16:48.743989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29474 10:16:48.744375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29476 10:16:48.797911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29477 10:16:48.798402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29479 10:16:48.843207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29480 10:16:48.843651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29482 10:16:48.889750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29483 10:16:48.890197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29485 10:16:48.938358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29486 10:16:48.938798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29488 10:16:48.984182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29489 10:16:48.984698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29491 10:16:49.025962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29492 10:16:49.026385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29494 10:16:49.070791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29495 10:16:49.071221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29497 10:16:49.119718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29498 10:16:49.120106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29500 10:16:49.174624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29501 10:16:49.175057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29503 10:16:49.227117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29504 10:16:49.227561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29506 10:16:49.276666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29507 10:16:49.277110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29509 10:16:49.326950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29510 10:16:49.327332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29512 10:16:49.374689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29514 10:16:49.375114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29515 10:16:49.426313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29516 10:16:49.426744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29518 10:16:49.475886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29519 10:16:49.476319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29521 10:16:49.529571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29522 10:16:49.530006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29524 10:16:49.579488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29526 10:16:49.579967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29527 10:16:49.631229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29528 10:16:49.631651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29530 10:16:49.667625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29532 10:16:49.668100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29533 10:16:49.714347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29534 10:16:49.714764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29536 10:16:49.757034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29538 10:16:49.757492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29539 10:16:49.793834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29540 10:16:49.794342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29542 10:16:49.831615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29543 10:16:49.832036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29545 10:16:49.882431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29547 10:16:49.882865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29548 10:16:49.931104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29549 10:16:49.931501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29551 10:16:49.971622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29552 10:16:49.972031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29554 10:16:50.007681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29556 10:16:50.008150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29557 10:16:50.048456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29559 10:16:50.048931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29560 10:16:50.094686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29562 10:16:50.095147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29563 10:16:50.139520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29564 10:16:50.139981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29566 10:16:50.183045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29568 10:16:50.183583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29569 10:16:50.227193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29570 10:16:50.227690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29572 10:16:50.271928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29574 10:16:50.272390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29575 10:16:50.316112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29576 10:16:50.316628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29578 10:16:50.359624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29579 10:16:50.360189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29581 10:16:50.419087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29582 10:16:50.419477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29584 10:16:50.470081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29585 10:16:50.470493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29587 10:16:50.510361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29589 10:16:50.510834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29590 10:16:50.557434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29592 10:16:50.557795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29593 10:16:50.597678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29594 10:16:50.598129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29596 10:16:50.642566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29597 10:16:50.642987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29599 10:16:50.683050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29600 10:16:50.683470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29602 10:16:50.719356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29604 10:16:50.719765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29605 10:16:50.763038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29607 10:16:50.763485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29608 10:16:50.804076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29610 10:16:50.804481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29611 10:16:50.847163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29612 10:16:50.847566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29614 10:16:50.890460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29615 10:16:50.890868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29617 10:16:50.937582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29618 10:16:50.938003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29620 10:16:50.987298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29621 10:16:50.987705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29623 10:16:51.038774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29624 10:16:51.039167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29626 10:16:51.088020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29627 10:16:51.088443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29629 10:16:51.130689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29630 10:16:51.131062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29632 10:16:51.178023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29633 10:16:51.178469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29635 10:16:51.224492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29636 10:16:51.224925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29638 10:16:51.267311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29639 10:16:51.267763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29641 10:16:51.312988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29643 10:16:51.314425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29644 10:16:51.362309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29645 10:16:51.362720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29647 10:16:51.410950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29648 10:16:51.411442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29650 10:16:51.449861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29652 10:16:51.450311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29653 10:16:51.488342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29654 10:16:51.488775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29656 10:16:51.524451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29658 10:16:51.524936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29659 10:16:51.562066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29660 10:16:51.562517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29662 10:16:51.599298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29663 10:16:51.599725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29665 10:16:51.639673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29666 10:16:51.640116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29668 10:16:51.683907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29669 10:16:51.684334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29671 10:16:51.729726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29673 10:16:51.730200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29674 10:16:51.765711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29675 10:16:51.766145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29677 10:16:51.810678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29678 10:16:51.811098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29680 10:16:51.854295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29681 10:16:51.854717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29683 10:16:51.891453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29685 10:16:51.891914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29686 10:16:51.942917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29688 10:16:51.943375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29689 10:16:51.990268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29691 10:16:51.990731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29692 10:16:52.038317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29693 10:16:52.038766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29695 10:16:52.075159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29696 10:16:52.075582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29698 10:16:52.114481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29700 10:16:52.114956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29701 10:16:52.156282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29702 10:16:52.156709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29704 10:16:52.198045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29706 10:16:52.198496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29707 10:16:52.240933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29709 10:16:52.241392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29710 10:16:52.279221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29711 10:16:52.279678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29713 10:16:52.327547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29714 10:16:52.327955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29716 10:16:52.370375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29717 10:16:52.370805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29719 10:16:52.411378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29720 10:16:52.411815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29722 10:16:52.455573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29723 10:16:52.455997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29725 10:16:52.493055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29727 10:16:52.493489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29728 10:16:52.531826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29729 10:16:52.532387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29731 10:16:52.578127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29733 10:16:52.578802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29734 10:16:52.627641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29735 10:16:52.628034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29737 10:16:52.676932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29739 10:16:52.677350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29740 10:16:52.715231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29741 10:16:52.715700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29743 10:16:52.762686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29744 10:16:52.763102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29746 10:16:52.806266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29747 10:16:52.806641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29749 10:16:52.849989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29751 10:16:52.850613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29752 10:16:52.894794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29753 10:16:52.895206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29755 10:16:52.936765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29757 10:16:52.937213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29758 10:16:52.987213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29759 10:16:52.987659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29761 10:16:53.032823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29763 10:16:53.033260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29764 10:16:53.084278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29765 10:16:53.084693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29767 10:16:53.126420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29768 10:16:53.126846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29770 10:16:53.167358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29772 10:16:53.167835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29773 10:16:53.211155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29775 10:16:53.211736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29776 10:16:53.255677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29777 10:16:53.256099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29779 10:16:53.304331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29780 10:16:53.304765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29782 10:16:53.348427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29784 10:16:53.348899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29785 10:16:53.387698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29786 10:16:53.388111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29788 10:16:53.435514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29789 10:16:53.435938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29791 10:16:53.478480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29792 10:16:53.478924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29794 10:16:53.524097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29795 10:16:53.524525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29797 10:16:53.563203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29799 10:16:53.563951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29800 10:16:53.601626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29801 10:16:53.602050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29803 10:16:53.643968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29804 10:16:53.644387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29806 10:16:53.686835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29807 10:16:53.687320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29809 10:16:53.732419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29810 10:16:53.732843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29812 10:16:53.789719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29813 10:16:53.790116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29815 10:16:53.848915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29817 10:16:53.849382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29818 10:16:53.889032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29820 10:16:53.889596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29821 10:16:53.927742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29822 10:16:53.928174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29824 10:16:53.973782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29825 10:16:53.974203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29827 10:16:54.019312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29828 10:16:54.019743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29830 10:16:54.062465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29832 10:16:54.062925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29833 10:16:54.103747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29834 10:16:54.104190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29836 10:16:54.141877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29838 10:16:54.142339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29839 10:16:54.186818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29841 10:16:54.187294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29842 10:16:54.223815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29843 10:16:54.224255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29845 10:16:54.263396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29847 10:16:54.263854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29848 10:16:54.311546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29849 10:16:54.311978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29851 10:16:54.355986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29852 10:16:54.356418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29854 10:16:54.400715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29855 10:16:54.401145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29857 10:16:54.446883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29858 10:16:54.447270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29860 10:16:54.491479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29861 10:16:54.491986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29863 10:16:54.535933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29864 10:16:54.536365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29866 10:16:54.579967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29868 10:16:54.580412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29869 10:16:54.631872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29870 10:16:54.632299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29872 10:16:54.682310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29874 10:16:54.682788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29875 10:16:54.724521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29877 10:16:54.724931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29878 10:16:54.774501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29879 10:16:54.774916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29881 10:16:54.818341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29883 10:16:54.818813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29884 10:16:54.860298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29885 10:16:54.860791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29887 10:16:54.900265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29888 10:16:54.900726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29890 10:16:54.940220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29892 10:16:54.940693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29893 10:16:54.981003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29895 10:16:54.981430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29896 10:16:55.031393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29897 10:16:55.031797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29899 10:16:55.091675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29900 10:16:55.092089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29902 10:16:55.151101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29903 10:16:55.151538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29905 10:16:55.194341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29906 10:16:55.194748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29908 10:16:55.243526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29909 10:16:55.243976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29911 10:16:55.293036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29913 10:16:55.293457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29914 10:16:55.337685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29915 10:16:55.338082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29917 10:16:55.387472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29918 10:16:55.387917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29920 10:16:55.430099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29921 10:16:55.430546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29923 10:16:55.492097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29924 10:16:55.492660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29926 10:16:55.567200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29927 10:16:55.567679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
29929 10:16:55.626058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
29930 10:16:55.626506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
29932 10:16:55.684523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
29933 10:16:55.684919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
29935 10:16:55.743066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
29936 10:16:55.743572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
29938 10:16:55.791593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
29939 10:16:55.792033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
29941 10:16:55.838701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
29943 10:16:55.839433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
29944 10:16:55.887796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
29945 10:16:55.888280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
29947 10:16:55.935772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
29948 10:16:55.936238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
29950 10:16:55.978797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
29951 10:16:55.979201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
29953 10:16:56.026477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
29954 10:16:56.026917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
29956 10:16:56.062067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
29957 10:16:56.062573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
29959 10:16:56.114958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
29960 10:16:56.115381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
29962 10:16:56.175569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
29963 10:16:56.175996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
29965 10:16:56.220389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
29966 10:16:56.220774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
29968 10:16:56.262569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
29969 10:16:56.262969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
29971 10:16:56.302120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
29972 10:16:56.302563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
29974 10:16:56.342234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
29975 10:16:56.342657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
29977 10:16:56.382489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
29978 10:16:56.382928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
29980 10:16:56.417972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
29981 10:16:56.418417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
29983 10:16:56.454716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
29984 10:16:56.455095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
29986 10:16:56.499780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
29987 10:16:56.500272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
29989 10:16:56.542591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
29991 10:16:56.543231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
29992 10:16:56.586076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
29993 10:16:56.586459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
29995 10:16:56.625208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
29996 10:16:56.625606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
29998 10:16:56.663878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
29999 10:16:56.664240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
30001 10:16:56.718878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
30002 10:16:56.719290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
30004 10:16:56.772461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
30005 10:16:56.772946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
30007 10:16:56.821988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
30008 10:16:56.822403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
30010 10:16:56.876191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
30011 10:16:56.876625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
30013 10:16:56.931641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
30014 10:16:56.932026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
30016 10:16:56.985699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
30018 10:16:56.986176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
30019 10:16:57.027461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
30020 10:16:57.027878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
30022 10:16:57.067547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
30023 10:16:57.067946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
30025 10:16:57.103985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
30027 10:16:57.104464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
30028 10:16:57.138421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
30029 10:16:57.138843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
30031 10:16:57.174083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
30033 10:16:57.174540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
30034 10:16:57.210465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
30036 10:16:57.210952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
30037 10:16:57.246186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
30039 10:16:57.246859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
30040 10:16:57.282432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
30042 10:16:57.283191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
30043 10:16:57.324241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
30045 10:16:57.324956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
30046 10:16:57.371609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
30048 10:16:57.372333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
30049 10:16:57.418002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
30051 10:16:57.418471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
30052 10:16:57.453884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
30053 10:16:57.454366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
30055 10:16:57.492120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
30056 10:16:57.492548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
30058 10:16:57.529705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
30059 10:16:57.530129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
30061 10:16:57.575398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
30062 10:16:57.575779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
30064 10:16:57.622923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
30065 10:16:57.623334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
30067 10:16:57.670266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
30068 10:16:57.670723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
30070 10:16:57.717577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
30072 10:16:57.718068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
30073 10:16:57.763479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
30075 10:16:57.763950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
30076 10:16:57.814697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
30077 10:16:57.815135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
30079 10:16:57.858688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
30080 10:16:57.859061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
30082 10:16:57.902085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
30083 10:16:57.902503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
30085 10:16:57.950258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
30087 10:16:57.950705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
30088 10:16:58.002155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
30089 10:16:58.002612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
30091 10:16:58.049076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
30093 10:16:58.049537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
30094 10:16:58.096629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
30095 10:16:58.097067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
30097 10:16:58.146432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
30099 10:16:58.146882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
30100 10:16:58.195041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
30102 10:16:58.195462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
30103 10:16:58.235732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
30105 10:16:58.236181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
30106 10:16:58.282825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
30108 10:16:58.283295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
30109 10:16:58.330888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
30110 10:16:58.331453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
30112 10:16:58.368290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
30113 10:16:58.368695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
30115 10:16:58.403014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
30117 10:16:58.403468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
30118 10:16:58.449775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
30119 10:16:58.450193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
30121 10:16:58.494729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
30122 10:16:58.495129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
30124 10:16:58.540368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
30126 10:16:58.540765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
30127 10:16:58.587588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
30128 10:16:58.588148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
30130 10:16:58.632867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
30132 10:16:58.633336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
30133 10:16:58.678869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
30134 10:16:58.679338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
30136 10:16:58.725791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
30137 10:16:58.726382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
30139 10:16:58.772123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
30140 10:16:58.772598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
30142 10:16:58.807603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
30143 10:16:58.808146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
30145 10:16:58.842943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
30147 10:16:58.843398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
30148 10:16:58.877671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
30149 10:16:58.878106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
30151 10:16:58.919417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
30152 10:16:58.919870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
30154 10:16:58.970042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
30155 10:16:58.970482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
30157 10:16:59.015143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
30158 10:16:59.015707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
30160 10:16:59.051296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
30162 10:16:59.051712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
30163 10:16:59.087862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
30164 10:16:59.088295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
30166 10:16:59.123546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
30167 10:16:59.123929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
30169 10:16:59.159447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
30171 10:16:59.159809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
30172 10:16:59.195212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30173 10:16:59.195629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30175 10:16:59.231752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30176 10:16:59.232187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30178 10:16:59.267184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30179 10:16:59.267628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30181 10:16:59.311882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30182 10:16:59.312454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30184 10:16:59.358022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30186 10:16:59.358746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30187 10:16:59.404941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30189 10:16:59.405307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30190 10:16:59.451636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30191 10:16:59.452055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30193 10:16:59.497593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30194 10:16:59.498040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30196 10:16:59.539786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30197 10:16:59.540184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30199 10:16:59.581078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30201 10:16:59.581678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30202 10:16:59.619885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30203 10:16:59.620348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30205 10:16:59.662599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30207 10:16:59.663033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30208 10:16:59.702986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30210 10:16:59.703397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30211 10:16:59.746530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30212 10:16:59.747072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30214 10:16:59.783340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30215 10:16:59.783767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30217 10:16:59.825711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30219 10:16:59.826127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30220 10:16:59.868488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30222 10:16:59.868956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30223 10:16:59.904057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30224 10:16:59.904461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30226 10:16:59.939718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30227 10:16:59.940141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30229 10:16:59.976104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30231 10:16:59.976543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30232 10:17:00.012509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30233 10:17:00.013064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30235 10:17:00.047476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30236 10:17:00.047945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30238 10:17:00.086867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30239 10:17:00.087379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30241 10:17:00.133581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30243 10:17:00.134321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30244 10:17:00.168339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30245 10:17:00.168779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30247 10:17:00.203252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30248 10:17:00.203674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30250 10:17:00.238674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30251 10:17:00.239219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30253 10:17:00.275210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30255 10:17:00.275814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30256 10:17:00.315893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30257 10:17:00.316358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30259 10:17:00.363329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30261 10:17:00.364066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30262 10:17:00.401988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30263 10:17:00.402470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30265 10:17:00.446230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30266 10:17:00.446650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30268 10:17:00.481977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30269 10:17:00.482423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30271 10:17:00.518074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30272 10:17:00.518586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30274 10:17:00.562460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30276 10:17:00.562931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30277 10:17:00.636453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30279 10:17:00.636935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30280 10:17:00.693904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30281 10:17:00.694355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30283 10:17:00.739428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30284 10:17:00.739873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30286 10:17:00.783336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30288 10:17:00.783799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30289 10:17:00.828166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30291 10:17:00.828563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30292 10:17:00.863862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30293 10:17:00.864247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30295 10:17:00.912073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30296 10:17:00.912528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30298 10:17:00.950121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30300 10:17:00.950552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30301 10:17:00.993920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30302 10:17:00.994307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30304 10:17:01.043116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30305 10:17:01.043581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30307 10:17:01.092059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30308 10:17:01.092588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30310 10:17:01.141775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30311 10:17:01.142193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30313 10:17:01.189821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30314 10:17:01.190233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30316 10:17:01.232311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30318 10:17:01.232707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30319 10:17:01.282849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30321 10:17:01.283313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30322 10:17:01.328445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30323 10:17:01.328859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30325 10:17:01.374666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30326 10:17:01.375081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30328 10:17:01.410977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30329 10:17:01.411398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30331 10:17:01.446916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30333 10:17:01.447378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30334 10:17:01.482797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30335 10:17:01.483314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30337 10:17:01.518556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30339 10:17:01.519120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30340 10:17:01.551493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30341 10:17:01.551931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30343 10:17:01.587162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30345 10:17:01.587621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30346 10:17:01.621334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30347 10:17:01.621750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30349 10:17:01.656619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30351 10:17:01.656993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30352 10:17:01.691230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30353 10:17:01.691632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30355 10:17:01.726308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30356 10:17:01.726715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30358 10:17:01.761371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30359 10:17:01.761951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30361 10:17:01.796935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30363 10:17:01.797630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30364 10:17:01.838482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30366 10:17:01.839090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30367 10:17:01.871856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30368 10:17:01.872231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30370 10:17:01.914600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30371 10:17:01.914974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30373 10:17:01.950754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30374 10:17:01.951175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30376 10:17:01.990613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30378 10:17:01.990997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30379 10:17:02.025717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30381 10:17:02.026177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30382 10:17:02.062636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30383 10:17:02.063049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30385 10:17:02.099420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30386 10:17:02.099901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30388 10:17:02.136028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30389 10:17:02.136459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30391 10:17:02.174352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30392 10:17:02.174797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30394 10:17:02.212317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30396 10:17:02.213096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30397 10:17:02.249719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30398 10:17:02.250135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30400 10:17:02.284087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30401 10:17:02.284654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30403 10:17:02.320617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30404 10:17:02.321145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30406 10:17:02.367595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30408 10:17:02.368194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30409 10:17:02.413262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30410 10:17:02.413683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30412 10:17:02.460017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30414 10:17:02.460460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30415 10:17:02.503375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30416 10:17:02.503800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30418 10:17:02.547255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30419 10:17:02.547658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30421 10:17:02.590046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30422 10:17:02.590569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30424 10:17:02.630904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30425 10:17:02.631441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30427 10:17:02.666553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30428 10:17:02.667012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30430 10:17:02.702301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30431 10:17:02.702719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30433 10:17:02.739559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30434 10:17:02.739917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30436 10:17:02.776135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30437 10:17:02.776623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30439 10:17:02.821387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30440 10:17:02.821784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30442 10:17:02.867290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30444 10:17:02.867674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30445 10:17:02.914124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30446 10:17:02.914538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30448 10:17:02.960904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30450 10:17:02.961500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30451 10:17:03.010083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30452 10:17:03.010481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30454 10:17:03.050920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30455 10:17:03.051301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30457 10:17:03.089995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30458 10:17:03.090443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30460 10:17:03.126828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30461 10:17:03.127184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30463 10:17:03.163572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30464 10:17:03.163947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30466 10:17:03.214258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30467 10:17:03.214714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30469 10:17:03.262491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30470 10:17:03.262936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30472 10:17:03.307402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30473 10:17:03.307780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30475 10:17:03.355054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30476 10:17:03.355480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30478 10:17:03.402996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30479 10:17:03.403382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30481 10:17:03.449752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30482 10:17:03.450292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30484 10:17:03.496184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30485 10:17:03.496714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30487 10:17:03.544057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30488 10:17:03.544604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30490 10:17:03.593599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30491 10:17:03.594013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30493 10:17:03.642776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30494 10:17:03.643341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30496 10:17:03.691779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30497 10:17:03.692205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30499 10:17:03.742715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30501 10:17:03.743320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30502 10:17:03.785949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30504 10:17:03.786380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30505 10:17:03.821893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30506 10:17:03.822385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30508 10:17:03.859409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30509 10:17:03.859803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30511 10:17:03.907462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30512 10:17:03.907835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30514 10:17:03.952039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30516 10:17:03.952465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30517 10:17:03.991055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30518 10:17:03.991555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30520 10:17:04.024533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30522 10:17:04.024994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30523 10:17:04.058766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30524 10:17:04.059207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30526 10:17:04.093502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30527 10:17:04.093934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30529 10:17:04.130827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30530 10:17:04.131264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30532 10:17:04.168300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30534 10:17:04.168768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30535 10:17:04.214285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30536 10:17:04.214696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30538 10:17:04.251661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30540 10:17:04.252118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30541 10:17:04.286396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30543 10:17:04.286859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30544 10:17:04.320200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30546 10:17:04.320659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30547 10:17:04.353797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30548 10:17:04.354235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30550 10:17:04.391804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30551 10:17:04.392243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30553 10:17:04.444296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30555 10:17:04.444758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30556 10:17:04.478382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30558 10:17:04.478847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30559 10:17:04.514405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30561 10:17:04.515015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30562 10:17:04.548683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30564 10:17:04.549333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30565 10:17:04.589451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30566 10:17:04.589911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30568 10:17:04.634976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30569 10:17:04.635413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30571 10:17:04.671941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30572 10:17:04.672357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30574 10:17:04.718044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30575 10:17:04.718394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30577 10:17:04.752362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30579 10:17:04.752823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30580 10:17:04.788393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30581 10:17:04.788837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30583 10:17:04.827881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30584 10:17:04.828407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30586 10:17:04.862942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30588 10:17:04.863539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30589 10:17:04.901597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30590 10:17:04.902046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30592 10:17:04.936216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30594 10:17:04.936677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30595 10:17:04.973486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30596 10:17:04.974028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30598 10:17:05.026102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30599 10:17:05.026543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30601 10:17:05.079272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30602 10:17:05.079719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30604 10:17:05.119272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30606 10:17:05.119658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30607 10:17:05.161388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30608 10:17:05.161820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30610 10:17:05.198432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30612 10:17:05.198803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30613 10:17:05.234899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30615 10:17:05.235336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30616 10:17:05.269644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30618 10:17:05.270067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30619 10:17:05.302627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30620 10:17:05.303035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30622 10:17:05.336818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30624 10:17:05.337265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30625 10:17:05.372354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30626 10:17:05.372692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30628 10:17:05.407224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30629 10:17:05.407616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30631 10:17:05.442372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30633 10:17:05.442828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30634 10:17:05.486492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30635 10:17:05.486834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30637 10:17:05.525959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30638 10:17:05.526322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30640 10:17:05.560219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30642 10:17:05.560681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30643 10:17:05.594056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30644 10:17:05.594533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30646 10:17:05.630855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30647 10:17:05.631329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30649 10:17:05.680224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30651 10:17:05.680661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30652 10:17:05.733088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30654 10:17:05.733543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30655 10:17:05.770461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30656 10:17:05.770912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30658 10:17:05.804453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30659 10:17:05.804919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30661 10:17:05.838475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30662 10:17:05.838918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30664 10:17:05.872284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30666 10:17:05.872937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30667 10:17:05.907404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30668 10:17:05.907805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30670 10:17:05.942985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30671 10:17:05.943425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30673 10:17:05.978270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30674 10:17:05.978669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30676 10:17:06.014469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30677 10:17:06.014857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30679 10:17:06.051604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30680 10:17:06.052031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30682 10:17:06.088430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30683 10:17:06.088799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30685 10:17:06.128048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30687 10:17:06.128762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30688 10:17:06.168122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30689 10:17:06.168575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30691 10:17:06.205417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30692 10:17:06.205993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30694 10:17:06.244205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30695 10:17:06.244624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30697 10:17:06.286616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30698 10:17:06.287063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30700 10:17:06.327028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30702 10:17:06.327795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30703 10:17:06.371498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30705 10:17:06.372080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30706 10:17:06.414162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30707 10:17:06.414551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30709 10:17:06.451386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30711 10:17:06.452025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30712 10:17:06.490224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30714 10:17:06.490925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30715 10:17:06.526636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30716 10:17:06.527076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30718 10:17:06.564471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30719 10:17:06.564943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30721 10:17:06.601920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30723 10:17:06.602321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30724 10:17:06.639637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30725 10:17:06.640114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30727 10:17:06.679204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30729 10:17:06.679779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30730 10:17:06.725023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30732 10:17:06.725485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30733 10:17:06.764476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30734 10:17:06.764872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30736 10:17:06.804395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30737 10:17:06.804867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30739 10:17:06.842352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30740 10:17:06.842776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30742 10:17:06.880919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30744 10:17:06.881414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30745 10:17:06.918900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30747 10:17:06.919543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30748 10:17:06.957866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30750 10:17:06.958472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30751 10:17:06.998301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30753 10:17:06.998692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30754 10:17:07.038819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30756 10:17:07.039320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30757 10:17:07.085503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30758 10:17:07.085887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30760 10:17:07.127189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30761 10:17:07.127584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30763 10:17:07.167153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30764 10:17:07.167559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30766 10:17:07.223211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30768 10:17:07.223683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30769 10:17:07.280262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30771 10:17:07.280742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30772 10:17:07.330917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30773 10:17:07.331339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30775 10:17:07.378382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30776 10:17:07.378781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30778 10:17:07.430173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30779 10:17:07.430595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30781 10:17:07.480417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30783 10:17:07.481094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30784 10:17:07.523172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30785 10:17:07.523530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30787 10:17:07.563402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30789 10:17:07.563986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30790 10:17:07.618203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30791 10:17:07.618593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30793 10:17:07.672944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30795 10:17:07.673727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30796 10:17:07.727329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30797 10:17:07.727782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30799 10:17:07.781737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30800 10:17:07.782193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30802 10:17:07.838744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30803 10:17:07.839174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30805 10:17:07.894626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30806 10:17:07.895054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30808 10:17:07.948597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30810 10:17:07.949062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30811 10:17:07.989607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30813 10:17:07.990077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30814 10:17:08.024002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30815 10:17:08.024404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30817 10:17:08.064345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30818 10:17:08.064766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30820 10:17:08.117982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30821 10:17:08.118437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30823 10:17:08.162446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30825 10:17:08.162856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30826 10:17:08.200696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30827 10:17:08.201110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30829 10:17:08.242897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30831 10:17:08.243362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30832 10:17:08.285718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30834 10:17:08.286173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30835 10:17:08.333659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30836 10:17:08.334108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30838 10:17:08.380208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30839 10:17:08.380590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30841 10:17:08.422840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30842 10:17:08.423260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30844 10:17:08.458816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30845 10:17:08.459164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30847 10:17:08.495090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30848 10:17:08.495631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30850 10:17:08.542541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30852 10:17:08.543050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30853 10:17:08.586561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30854 10:17:08.586997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30856 10:17:08.628036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30858 10:17:08.628463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30859 10:17:08.666164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30860 10:17:08.666591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30862 10:17:08.708927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30864 10:17:08.709387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30865 10:17:08.742706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30866 10:17:08.743140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30868 10:17:08.777040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30870 10:17:08.777507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30871 10:17:08.818222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30873 10:17:08.818697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30874 10:17:08.854482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30876 10:17:08.854909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30877 10:17:08.899306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30878 10:17:08.899736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30880 10:17:08.934532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30882 10:17:08.934992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30883 10:17:08.975795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30884 10:17:08.976276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30886 10:17:09.022234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30887 10:17:09.022586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30889 10:17:09.067272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30890 10:17:09.067671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30892 10:17:09.106210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30893 10:17:09.106635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30895 10:17:09.149847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30896 10:17:09.150380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30898 10:17:09.187141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30899 10:17:09.187574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30901 10:17:09.238258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30902 10:17:09.238710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30904 10:17:09.280023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30905 10:17:09.280448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30907 10:17:09.325557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30909 10:17:09.326234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30910 10:17:09.370985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30911 10:17:09.371556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30913 10:17:09.426462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30914 10:17:09.426964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30916 10:17:09.472315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30917 10:17:09.472762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30919 10:17:09.507355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30920 10:17:09.507793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30922 10:17:09.543012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30923 10:17:09.543393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30925 10:17:09.590136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
30926 10:17:09.590575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30928 10:17:09.626664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
30929 10:17:09.627081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
30931 10:17:09.663257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
30932 10:17:09.663680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
30934 10:17:09.698847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
30935 10:17:09.699248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
30937 10:17:09.741804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
30939 10:17:09.742458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
30940 10:17:09.783540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
30941 10:17:09.783960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
30943 10:17:09.826079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
30945 10:17:09.826624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
30946 10:17:09.872252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
30947 10:17:09.872719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
30949 10:17:09.909654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
30950 10:17:09.910099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
30952 10:17:09.945077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
30954 10:17:09.945546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
30955 10:17:09.989536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
30956 10:17:09.990104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
30958 10:17:10.032174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
30959 10:17:10.032619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
30961 10:17:10.072260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
30962 10:17:10.072653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
30964 10:17:10.107360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
30965 10:17:10.107802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
30967 10:17:10.147871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
30968 10:17:10.148314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
30970 10:17:10.183855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
30971 10:17:10.184271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
30973 10:17:10.219854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
30975 10:17:10.220322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
30976 10:17:10.255268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
30977 10:17:10.255697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
30979 10:17:10.290338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
30981 10:17:10.290808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
30982 10:17:10.325713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
30984 10:17:10.326144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
30985 10:17:10.362647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
30987 10:17:10.363104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
30988 10:17:10.397623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
30990 10:17:10.398054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
30991 10:17:10.441135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
30992 10:17:10.441491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
30994 10:17:10.480367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
30995 10:17:10.480727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
30997 10:17:10.517555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
30999 10:17:10.518278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
31000 10:17:10.558267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
31001 10:17:10.558623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
31003 10:17:10.593289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
31004 10:17:10.593829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
31006 10:17:10.627263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
31007 10:17:10.627814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
31009 10:17:10.662010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
31011 10:17:10.662443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
31012 10:17:10.704916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
31014 10:17:10.705285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
31015 10:17:10.760820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
31017 10:17:10.761428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
31018 10:17:10.812167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
31019 10:17:10.812706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
31021 10:17:10.867964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
31022 10:17:10.868408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
31024 10:17:10.907121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
31026 10:17:10.907528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
31027 10:17:10.946762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
31028 10:17:10.947188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
31030 10:17:10.980378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
31031 10:17:10.980786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
31033 10:17:11.015333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
31034 10:17:11.015751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
31036 10:17:11.050178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
31037 10:17:11.050720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
31039 10:17:11.086040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
31041 10:17:11.086502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
31042 10:17:11.121384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
31043 10:17:11.121797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
31045 10:17:11.158124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
31047 10:17:11.158597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
31048 10:17:11.205886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
31049 10:17:11.206309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
31051 10:17:11.255717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
31052 10:17:11.256139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
31054 10:17:11.303649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
31056 10:17:11.304164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
31057 10:17:11.350089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
31058 10:17:11.350520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
31060 10:17:11.403626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
31061 10:17:11.404143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
31063 10:17:11.455239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
31065 10:17:11.455617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
31066 10:17:11.492168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
31068 10:17:11.492814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
31069 10:17:11.535980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
31070 10:17:11.536535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
31072 10:17:11.591546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
31073 10:17:11.591956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
31075 10:17:11.630890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
31076 10:17:11.631318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
31078 10:17:11.673802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
31080 10:17:11.674222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
31081 10:17:11.719380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
31082 10:17:11.719779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
31084 10:17:11.759637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
31085 10:17:11.760058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
31087 10:17:11.797618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
31088 10:17:11.798071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
31090 10:17:11.837975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
31091 10:17:11.838419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
31093 10:17:11.887345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
31095 10:17:11.887820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
31096 10:17:11.932782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
31098 10:17:11.933397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
31099 10:17:11.975578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
31100 10:17:11.976115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
31102 10:17:12.010355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
31104 10:17:12.010977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
31105 10:17:12.048569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
31106 10:17:12.049064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
31108 10:17:12.091403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
31109 10:17:12.091809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
31111 10:17:12.127899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
31113 10:17:12.128282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
31114 10:17:12.182233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
31116 10:17:12.182759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
31117 10:17:12.228411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
31118 10:17:12.228925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
31120 10:17:12.274417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
31121 10:17:12.274891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
31123 10:17:12.321980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
31124 10:17:12.322430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
31126 10:17:12.355101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
31128 10:17:12.355524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
31129 10:17:12.393827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
31130 10:17:12.394387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
31132 10:17:12.446671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
31133 10:17:12.447056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
31135 10:17:12.494363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
31136 10:17:12.494784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
31138 10:17:12.536465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
31140 10:17:12.537046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
31141 10:17:12.570237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
31143 10:17:12.570674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
31144 10:17:12.621826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
31145 10:17:12.622250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
31147 10:17:12.661830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
31148 10:17:12.662249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
31150 10:17:12.702352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
31152 10:17:12.702814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
31153 10:17:12.738108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
31154 10:17:12.738526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
31156 10:17:12.772296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
31157 10:17:12.772765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
31159 10:17:12.807536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
31160 10:17:12.807985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
31162 10:17:12.842626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
31164 10:17:12.843081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
31165 10:17:12.877358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
31166 10:17:12.877829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
31168 10:17:12.920622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
31169 10:17:12.921071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
31171 10:17:12.958676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31173 10:17:12.959140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31174 10:17:12.999498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31175 10:17:12.999936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31177 10:17:13.035662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31178 10:17:13.036099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31180 10:17:13.073892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31182 10:17:13.074353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31183 10:17:13.113778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31185 10:17:13.114170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31186 10:17:13.149264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31188 10:17:13.149729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31189 10:17:13.185506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31191 10:17:13.186190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31192 10:17:13.225735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31193 10:17:13.226305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31195 10:17:13.262651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31197 10:17:13.263116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31198 10:17:13.296031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31199 10:17:13.296442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31201 10:17:13.330138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31203 10:17:13.330604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31204 10:17:13.364549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31206 10:17:13.365158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31207 10:17:13.399167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31209 10:17:13.399780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31210 10:17:13.433886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31212 10:17:13.434631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31213 10:17:13.473980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31214 10:17:13.474434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31216 10:17:13.511579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31217 10:17:13.512074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31219 10:17:13.554478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31221 10:17:13.554938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31222 10:17:13.592469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31223 10:17:13.592958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31225 10:17:13.633976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31226 10:17:13.634400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31228 10:17:13.669157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31230 10:17:13.669625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31231 10:17:13.704176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31233 10:17:13.704639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31234 10:17:13.743183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31236 10:17:13.743835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31237 10:17:13.776546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31239 10:17:13.777150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31240 10:17:13.809674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31241 10:17:13.810124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31243 10:17:13.862189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31244 10:17:13.862611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31246 10:17:13.917504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31247 10:17:13.917949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31249 10:17:13.951926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31251 10:17:13.952402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31252 10:17:13.987197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31253 10:17:13.987698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31255 10:17:14.023625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31256 10:17:14.024068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31258 10:17:14.061795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31259 10:17:14.062213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31261 10:17:14.098427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31262 10:17:14.098897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31264 10:17:14.136566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31266 10:17:14.137028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31267 10:17:14.174793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31268 10:17:14.175235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31270 10:17:14.214336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31272 10:17:14.214803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31273 10:17:14.253318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31274 10:17:14.253737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31276 10:17:14.286901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31277 10:17:14.287344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31279 10:17:14.321095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31281 10:17:14.321547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31282 10:17:14.353984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31283 10:17:14.354450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31285 10:17:14.388431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31287 10:17:14.388900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31288 10:17:14.422221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31289 10:17:14.422636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31291 10:17:14.454678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31292 10:17:14.455152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31294 10:17:14.486911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31295 10:17:14.487341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31297 10:17:14.519831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31298 10:17:14.520272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31300 10:17:14.555785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31301 10:17:14.556356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31303 10:17:14.602356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31305 10:17:14.602719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31306 10:17:14.640866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31308 10:17:14.641283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31309 10:17:14.678457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31310 10:17:14.678818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31312 10:17:14.718098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31313 10:17:14.718476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31315 10:17:14.766241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31316 10:17:14.766506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31318 10:17:14.809745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31319 10:17:14.810038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31321 10:17:14.846859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31322 10:17:14.847192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31324 10:17:14.883802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31325 10:17:14.884270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31327 10:17:14.920484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31328 10:17:14.920846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31330 10:17:14.957953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31332 10:17:14.958522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31333 10:17:15.004099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31334 10:17:15.004563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31336 10:17:15.040363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31338 10:17:15.041006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31339 10:17:15.076069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31340 10:17:15.076496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31342 10:17:15.119670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31343 10:17:15.120192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31345 10:17:15.157405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31346 10:17:15.157729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31348 10:17:15.195128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31350 10:17:15.195526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31351 10:17:15.231759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31352 10:17:15.232121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31354 10:17:15.271615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31355 10:17:15.272057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31357 10:17:15.308491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31358 10:17:15.308858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31360 10:17:15.347618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31361 10:17:15.348038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31363 10:17:15.384051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31364 10:17:15.384461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31366 10:17:15.420912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31368 10:17:15.421423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31369 10:17:15.456940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31371 10:17:15.457372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31372 10:17:15.495173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31374 10:17:15.495588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31375 10:17:15.531802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31376 10:17:15.532228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31378 10:17:15.566890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31380 10:17:15.567340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31381 10:17:15.601914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31382 10:17:15.602337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31384 10:17:15.637984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31386 10:17:15.638365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31387 10:17:15.672320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31388 10:17:15.672746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31390 10:17:15.706104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31391 10:17:15.706673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31393 10:17:15.740139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31394 10:17:15.740600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31396 10:17:15.774846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31397 10:17:15.775303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31399 10:17:15.809267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31400 10:17:15.809708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31402 10:17:15.843162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31403 10:17:15.843698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31405 10:17:15.893567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31406 10:17:15.894036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31408 10:17:15.945914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31410 10:17:15.946363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31411 10:17:16.003380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31412 10:17:16.003778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31414 10:17:16.039237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31415 10:17:16.039612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31417 10:17:16.075596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31418 10:17:16.076020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31420 10:17:16.114591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31422 10:17:16.115042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31423 10:17:16.157911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31424 10:17:16.158329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31426 10:17:16.195979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31428 10:17:16.196452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31429 10:17:16.236941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31431 10:17:16.237393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31432 10:17:16.283888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31434 10:17:16.284340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31435 10:17:16.323724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31436 10:17:16.324140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31438 10:17:16.358167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31439 10:17:16.358589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31441 10:17:16.393226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31443 10:17:16.393692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31444 10:17:16.428444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31445 10:17:16.428835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31447 10:17:16.467994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31448 10:17:16.468472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31450 10:17:16.507979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31452 10:17:16.508397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31453 10:17:16.542614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31455 10:17:16.542974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31456 10:17:16.576228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31457 10:17:16.576678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31459 10:17:16.610159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31460 10:17:16.610554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31462 10:17:16.644395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31464 10:17:16.644841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31465 10:17:16.677976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31466 10:17:16.678439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31468 10:17:16.713569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31470 10:17:16.714040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31471 10:17:16.746642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31472 10:17:16.747050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31474 10:17:16.779854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31476 10:17:16.780310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31477 10:17:16.812165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31478 10:17:16.812582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31480 10:17:16.845085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31482 10:17:16.845537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31483 10:17:16.878069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31485 10:17:16.878520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31486 10:17:16.913717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31487 10:17:16.914133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31489 10:17:16.948616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31491 10:17:16.949076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31492 10:17:16.985929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31493 10:17:16.986455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31495 10:17:17.021955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31496 10:17:17.022407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31498 10:17:17.058118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31499 10:17:17.058672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31501 10:17:17.094199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31503 10:17:17.094622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31504 10:17:17.129436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31505 10:17:17.129738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31507 10:17:17.167644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31508 10:17:17.168021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31510 10:17:17.202190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31512 10:17:17.202595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31513 10:17:17.235546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31515 10:17:17.236330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31516 10:17:17.270377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31517 10:17:17.270732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31519 10:17:17.313006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31521 10:17:17.313694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31522 10:17:17.346720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31524 10:17:17.347193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31525 10:17:17.381007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31527 10:17:17.381602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31528 10:17:17.414584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31530 10:17:17.415155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31531 10:17:17.448026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31532 10:17:17.448495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31534 10:17:17.481566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31536 10:17:17.482175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31537 10:17:17.513893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31538 10:17:17.514372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31540 10:17:17.548423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31541 10:17:17.548870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31543 10:17:17.585064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31545 10:17:17.585632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31546 10:17:17.621351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31547 10:17:17.621816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31549 10:17:17.660415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31550 10:17:17.660841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31552 10:17:17.698367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31554 10:17:17.698832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31555 10:17:17.733174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31556 10:17:17.733605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31558 10:17:17.768139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31560 10:17:17.768621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31561 10:17:17.802261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31562 10:17:17.802636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31564 10:17:17.835593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31565 10:17:17.836002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31567 10:17:17.870590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31569 10:17:17.871053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31570 10:17:17.907804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31572 10:17:17.908251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31573 10:17:17.948319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31574 10:17:17.948757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31576 10:17:17.986452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31577 10:17:17.986882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31579 10:17:18.025148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31580 10:17:18.025581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31582 10:17:18.066901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31583 10:17:18.067349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31585 10:17:18.109155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31587 10:17:18.109885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31588 10:17:18.142507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31589 10:17:18.142921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31591 10:17:18.176173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31593 10:17:18.176781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31594 10:17:18.211139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31595 10:17:18.211607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31597 10:17:18.246337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31598 10:17:18.246751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31600 10:17:18.281476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31602 10:17:18.281936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31603 10:17:18.314632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31604 10:17:18.315053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31606 10:17:18.347800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31607 10:17:18.348214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31609 10:17:18.382488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31610 10:17:18.382904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31612 10:17:18.417861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31613 10:17:18.418305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31615 10:17:18.453636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31616 10:17:18.454062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31618 10:17:18.491720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31619 10:17:18.492145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31621 10:17:18.527579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31622 10:17:18.528007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31624 10:17:18.564435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31625 10:17:18.564861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31627 10:17:18.619727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31628 10:17:18.620205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31630 10:17:18.663106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31632 10:17:18.663619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31633 10:17:18.698688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31635 10:17:18.699343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31636 10:17:18.747716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31638 10:17:18.748377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31639 10:17:18.791965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31640 10:17:18.792408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31642 10:17:18.829713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31644 10:17:18.830173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31645 10:17:18.865677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31646 10:17:18.866114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31648 10:17:18.903285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31650 10:17:18.903754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31651 10:17:18.941965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31652 10:17:18.942448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31654 10:17:18.998646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31656 10:17:18.999114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31657 10:17:19.046082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31659 10:17:19.046545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31660 10:17:19.084747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31662 10:17:19.085209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31663 10:17:19.129365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31665 10:17:19.129825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31666 10:17:19.166484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31668 10:17:19.166904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31669 10:17:19.201491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31670 10:17:19.201897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31672 10:17:19.241891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31673 10:17:19.242321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31675 10:17:19.276509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31676 10:17:19.276943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31678 10:17:19.311099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31679 10:17:19.311506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31681 10:17:19.346088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31683 10:17:19.346542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31684 10:17:19.382544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31686 10:17:19.383003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31687 10:17:19.418462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31689 10:17:19.418887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31690 10:17:19.453706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31691 10:17:19.454161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31693 10:17:19.489375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31694 10:17:19.489801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31696 10:17:19.531584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31698 10:17:19.532052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31699 10:17:19.570795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31700 10:17:19.571181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31702 10:17:19.617616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31703 10:17:19.617982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31705 10:17:19.654130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31706 10:17:19.654531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31708 10:17:19.704427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31709 10:17:19.704960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31711 10:17:19.741957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31712 10:17:19.742386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31714 10:17:19.775409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31715 10:17:19.775823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31717 10:17:19.821714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31719 10:17:19.822172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31720 10:17:19.855518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31721 10:17:19.855961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31723 10:17:19.889671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31724 10:17:19.890066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31726 10:17:19.925501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31728 10:17:19.925964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31729 10:17:19.962919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31730 10:17:19.963352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31732 10:17:20.003025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31733 10:17:20.003464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31735 10:17:20.037777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31736 10:17:20.038213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31738 10:17:20.078004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31740 10:17:20.078466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31741 10:17:20.114296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31742 10:17:20.114716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31744 10:17:20.148383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31745 10:17:20.148809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31747 10:17:20.197056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31749 10:17:20.197508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31750 10:17:20.239336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31751 10:17:20.239792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31753 10:17:20.284129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31754 10:17:20.284540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31756 10:17:20.328530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31758 10:17:20.329000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31759 10:17:20.363741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31760 10:17:20.364116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31762 10:17:20.401046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31764 10:17:20.401414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31765 10:17:20.433809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31766 10:17:20.434185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31768 10:17:20.466684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31770 10:17:20.467058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31771 10:17:20.508461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31772 10:17:20.508887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31774 10:17:20.547748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31775 10:17:20.548118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31777 10:17:20.600284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31779 10:17:20.600751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31780 10:17:20.644023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31781 10:17:20.644436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31783 10:17:20.680942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31785 10:17:20.681424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31786 10:17:20.717808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31787 10:17:20.718303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31789 10:17:20.754308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31791 10:17:20.754778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31792 10:17:20.789800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31794 10:17:20.790592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31795 10:17:20.826231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31796 10:17:20.826731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31798 10:17:20.879646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31799 10:17:20.880046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31801 10:17:20.933498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31803 10:17:20.933939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31804 10:17:20.975302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31805 10:17:20.975732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31807 10:17:21.025539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31808 10:17:21.026114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31810 10:17:21.062495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31812 10:17:21.062969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31813 10:17:21.131610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31815 10:17:21.132066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31816 10:17:21.167692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31817 10:17:21.168122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31819 10:17:21.219411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31821 10:17:21.219866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31822 10:17:21.267627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31824 10:17:21.268010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31825 10:17:21.316794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31827 10:17:21.317269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31828 10:17:21.352742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31829 10:17:21.353183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31831 10:17:21.398855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31833 10:17:21.399286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31834 10:17:21.454223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31835 10:17:21.454678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31837 10:17:21.498252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31839 10:17:21.498712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31840 10:17:21.536168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31841 10:17:21.536626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31843 10:17:21.586757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31845 10:17:21.587215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31846 10:17:21.643179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31848 10:17:21.643643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31849 10:17:21.697529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31850 10:17:21.697924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31852 10:17:21.750196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31853 10:17:21.750652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31855 10:17:21.786506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31856 10:17:21.786946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31858 10:17:21.828045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31860 10:17:21.828486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31861 10:17:21.878101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31863 10:17:21.878577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31864 10:17:21.926028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31865 10:17:21.926516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31867 10:17:21.961983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31868 10:17:21.962408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31870 10:17:21.997743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31872 10:17:21.998506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31873 10:17:22.039989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31875 10:17:22.040731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31876 10:17:22.083516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31877 10:17:22.083919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31879 10:17:22.126899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31880 10:17:22.127350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31882 10:17:22.171241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31883 10:17:22.171745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31885 10:17:22.208166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31886 10:17:22.208620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31888 10:17:22.244572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31889 10:17:22.245024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31891 10:17:22.280702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31893 10:17:22.281177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31894 10:17:22.316020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31895 10:17:22.316425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31897 10:17:22.354702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31898 10:17:22.355124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31900 10:17:22.394623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31901 10:17:22.395024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31903 10:17:22.437934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31904 10:17:22.438367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31906 10:17:22.473979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31907 10:17:22.474432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31909 10:17:22.525602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31910 10:17:22.526187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31912 10:17:22.577020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31914 10:17:22.577591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31915 10:17:22.616031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31917 10:17:22.616464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31918 10:17:22.658405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31920 10:17:22.658864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31921 10:17:22.694778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31923 10:17:22.695238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31924 10:17:22.731296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31925 10:17:22.731716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31927 10:17:22.781437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
31928 10:17:22.781857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
31930 10:17:22.832257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
31931 10:17:22.832666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
31933 10:17:22.869713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
31935 10:17:22.870378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
31936 10:17:22.903818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
31937 10:17:22.904260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
31939 10:17:22.943836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
31940 10:17:22.944258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
31942 10:17:22.978170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
31943 10:17:22.978588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
31945 10:17:23.010786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
31946 10:17:23.011194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
31948 10:17:23.042976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
31950 10:17:23.043550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
31951 10:17:23.075156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
31952 10:17:23.075611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
31954 10:17:23.107325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
31956 10:17:23.107930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
31957 10:17:23.141635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
31958 10:17:23.142140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
31960 10:17:23.178593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
31961 10:17:23.179096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
31963 10:17:23.213464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
31964 10:17:23.213962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
31966 10:17:23.248126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
31968 10:17:23.248691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
31969 10:17:23.281709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
31970 10:17:23.282180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
31972 10:17:23.317297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
31973 10:17:23.317797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
31975 10:17:23.362644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
31976 10:17:23.363067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
31978 10:17:23.403639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
31979 10:17:23.404057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
31981 10:17:23.439387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
31983 10:17:23.439846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
31984 10:17:23.482275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
31985 10:17:23.482729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
31987 10:17:23.516384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
31988 10:17:23.516841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
31990 10:17:23.550680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
31991 10:17:23.551096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
31993 10:17:23.583422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
31994 10:17:23.583833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
31996 10:17:23.617445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
31997 10:17:23.617952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
31999 10:17:23.652111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
32001 10:17:23.652723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
32002 10:17:23.686411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
32003 10:17:23.686831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
32005 10:17:23.724098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
32006 10:17:23.724592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
32008 10:17:23.761187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
32009 10:17:23.761634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
32011 10:17:23.795466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
32013 10:17:23.795920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
32014 10:17:23.832078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
32016 10:17:23.832532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
32017 10:17:23.881063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
32019 10:17:23.881762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
32020 10:17:23.926062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
32021 10:17:23.926504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
32023 10:17:23.970622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
32024 10:17:23.971082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
32026 10:17:24.013928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
32028 10:17:24.014372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
32029 10:17:24.058701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
32030 10:17:24.059133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
32032 10:17:24.107101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
32033 10:17:24.107537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
32035 10:17:24.154860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
32036 10:17:24.155300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
32038 10:17:24.190957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
32039 10:17:24.191398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
32041 10:17:24.227390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
32042 10:17:24.227841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
32044 10:17:24.263509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
32045 10:17:24.264031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
32047 10:17:24.299499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
32048 10:17:24.299897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
32050 10:17:24.335128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
32051 10:17:24.335601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
32053 10:17:24.370204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
32054 10:17:24.370704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
32056 10:17:24.406199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
32057 10:17:24.406751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
32059 10:17:24.442738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
32060 10:17:24.443232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
32062 10:17:24.479035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
32063 10:17:24.479482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
32065 10:17:24.523600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
32066 10:17:24.524101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
32068 10:17:24.560533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
32070 10:17:24.561006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
32071 10:17:24.601578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
32073 10:17:24.602042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
32074 10:17:24.641571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
32076 10:17:24.642037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
32077 10:17:24.678377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
32079 10:17:24.678841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
32080 10:17:24.715353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
32081 10:17:24.715781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
32083 10:17:24.751680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
32085 10:17:24.752107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
32086 10:17:24.787709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
32088 10:17:24.788190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
32089 10:17:24.823381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
32090 10:17:24.823801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
32092 10:17:24.858931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
32093 10:17:24.859359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
32095 10:17:24.906633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
32097 10:17:24.907294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
32098 10:17:24.951532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
32099 10:17:24.951942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
32101 10:17:24.992427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
32102 10:17:24.992828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
32104 10:17:25.029542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
32106 10:17:25.030006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
32107 10:17:25.065931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
32108 10:17:25.066329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
32110 10:17:25.102865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
32112 10:17:25.103325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
32113 10:17:25.145030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
32115 10:17:25.145469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
32116 10:17:25.181091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
32118 10:17:25.181540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
32119 10:17:25.222903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
32120 10:17:25.223266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
32122 10:17:25.258713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
32123 10:17:25.259046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
32125 10:17:25.312894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
32127 10:17:25.313249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
32128 10:17:25.360326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
32129 10:17:25.360763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
32131 10:17:25.400883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
32133 10:17:25.401259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
32134 10:17:25.448057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
32135 10:17:25.448324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
32137 10:17:25.489986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
32138 10:17:25.490346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
32140 10:17:25.530264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
32141 10:17:25.530602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
32143 10:17:25.569845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
32144 10:17:25.570321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
32146 10:17:25.606423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
32147 10:17:25.606887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
32149 10:17:25.650096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
32151 10:17:25.650754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
32152 10:17:25.701573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
32153 10:17:25.702013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
32155 10:17:25.735797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
32156 10:17:25.736205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
32158 10:17:25.774638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
32160 10:17:25.775103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
32161 10:17:25.814749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
32162 10:17:25.815122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
32164 10:17:25.855881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
32165 10:17:25.856270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
32167 10:17:25.898916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
32168 10:17:25.899306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
32170 10:17:25.939720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32172 10:17:25.940423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
32173 10:17:25.975962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32175 10:17:25.976714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32176 10:17:26.011049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32178 10:17:26.011638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32179 10:17:26.054315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32181 10:17:26.054785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32182 10:17:26.091634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32183 10:17:26.092070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32185 10:17:26.138738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32187 10:17:26.139165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32188 10:17:26.184076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32190 10:17:26.184788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32191 10:17:26.242861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32192 10:17:26.243307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32194 10:17:26.278040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32196 10:17:26.278653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32197 10:17:26.314299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32198 10:17:26.314790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32200 10:17:26.352529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32201 10:17:26.352928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32203 10:17:26.395313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32204 10:17:26.395733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32206 10:17:26.442050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32208 10:17:26.442513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32209 10:17:26.476893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32211 10:17:26.477369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32212 10:17:26.512210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32213 10:17:26.512563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32215 10:17:26.570020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32217 10:17:26.570490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32218 10:17:26.606880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32219 10:17:26.607308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32221 10:17:26.643359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32223 10:17:26.643965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32224 10:17:26.679668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32225 10:17:26.680069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32227 10:17:26.721709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32228 10:17:26.722093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32230 10:17:26.777991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32231 10:17:26.778384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32233 10:17:26.814927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32234 10:17:26.815372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32236 10:17:26.864000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32237 10:17:26.864432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32239 10:17:26.914361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32240 10:17:26.914800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32242 10:17:26.959229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32243 10:17:26.959738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32245 10:17:27.006165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32246 10:17:27.006590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32248 10:17:27.042312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32250 10:17:27.042758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32251 10:17:27.082504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32252 10:17:27.083074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32254 10:17:27.126363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32256 10:17:27.126739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32257 10:17:27.170495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32258 10:17:27.170880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32260 10:17:27.206474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32261 10:17:27.206912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32263 10:17:27.242478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32264 10:17:27.242897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32266 10:17:27.285800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32267 10:17:27.286373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32269 10:17:27.331902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32270 10:17:27.332486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32272 10:17:27.378091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32274 10:17:27.378580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32275 10:17:27.418178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32276 10:17:27.418555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32278 10:17:27.460248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32279 10:17:27.460760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32281 10:17:27.502292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32282 10:17:27.502772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32284 10:17:27.542367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32286 10:17:27.542741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32287 10:17:27.589018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32289 10:17:27.589404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32290 10:17:27.641795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32291 10:17:27.642181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32293 10:17:27.694232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32295 10:17:27.694876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32296 10:17:27.733798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32298 10:17:27.734274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32299 10:17:27.782779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32300 10:17:27.783217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32302 10:17:27.826286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32303 10:17:27.826720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32305 10:17:27.865692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32306 10:17:27.866018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32308 10:17:27.914568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32310 10:17:27.915035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32311 10:17:27.955052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32312 10:17:27.955472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32314 10:17:28.011139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32315 10:17:28.011537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32317 10:17:28.059307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32319 10:17:28.059760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32320 10:17:28.092956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32322 10:17:28.093522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32323 10:17:28.130545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32324 10:17:28.130991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32326 10:17:28.168924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32328 10:17:28.169311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32329 10:17:28.205926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32330 10:17:28.206366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32332 10:17:28.242388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32333 10:17:28.242799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32335 10:17:28.276165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32336 10:17:28.276579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32338 10:17:28.311141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32340 10:17:28.311604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32341 10:17:28.345592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32342 10:17:28.346036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32344 10:17:28.380421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32345 10:17:28.380837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32347 10:17:28.415621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32349 10:17:28.416372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32350 10:17:28.455320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32352 10:17:28.455961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32353 10:17:28.494549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32354 10:17:28.494984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32356 10:17:28.531566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32357 10:17:28.531950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32359 10:17:28.571209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32360 10:17:28.571632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32362 10:17:28.608934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32364 10:17:28.609373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32365 10:17:28.648527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32367 10:17:28.648975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32368 10:17:28.695149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32369 10:17:28.695613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32371 10:17:28.738444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32373 10:17:28.738886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32374 10:17:28.775035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32376 10:17:28.775458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32377 10:17:28.810628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32378 10:17:28.811056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32380 10:17:28.852226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32382 10:17:28.852688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32383 10:17:28.885755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32384 10:17:28.886185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32386 10:17:28.923276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32387 10:17:28.923682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32389 10:17:28.958168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32391 10:17:28.958545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32392 10:17:28.993132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32393 10:17:28.993534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32395 10:17:29.027258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32396 10:17:29.027681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32398 10:17:29.062729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32400 10:17:29.063174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32401 10:17:29.100044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32402 10:17:29.100534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32404 10:17:29.150535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32405 10:17:29.150964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32407 10:17:29.198586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32409 10:17:29.199056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32410 10:17:29.239511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32411 10:17:29.239960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32413 10:17:29.280984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32415 10:17:29.281481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32416 10:17:29.331425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32417 10:17:29.331848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32419 10:17:29.374347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32420 10:17:29.374806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32422 10:17:29.429542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32423 10:17:29.429982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32425 10:17:29.470515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32426 10:17:29.471002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32428 10:17:29.516255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32429 10:17:29.516633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32431 10:17:29.561423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32432 10:17:29.561859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32434 10:17:29.602490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32435 10:17:29.602921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32437 10:17:29.638432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32438 10:17:29.638835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32440 10:17:29.679319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32441 10:17:29.679812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32443 10:17:29.717414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32444 10:17:29.717858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32446 10:17:29.753492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32448 10:17:29.754284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32449 10:17:29.792720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32450 10:17:29.793139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32452 10:17:29.827176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32453 10:17:29.827643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32455 10:17:29.863292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32456 10:17:29.863673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32458 10:17:29.901828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32459 10:17:29.902274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32461 10:17:29.943137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32462 10:17:29.943569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32464 10:17:29.981269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32465 10:17:29.981700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32467 10:17:30.022302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32468 10:17:30.022727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32470 10:17:30.058781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32471 10:17:30.059170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32473 10:17:30.093896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32474 10:17:30.094336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32476 10:17:30.131050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32477 10:17:30.131475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32479 10:17:30.167306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32480 10:17:30.167828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32482 10:17:30.203066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32483 10:17:30.203558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32485 10:17:30.242637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32486 10:17:30.243134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32488 10:17:30.278506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32489 10:17:30.278927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32491 10:17:30.319718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32492 10:17:30.320146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32494 10:17:30.355136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32496 10:17:30.355610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32497 10:17:30.390098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32498 10:17:30.390523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32500 10:17:30.425182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32502 10:17:30.425644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32503 10:17:30.460080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32504 10:17:30.460514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32506 10:17:30.495693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32507 10:17:30.496122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32509 10:17:30.530488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32510 10:17:30.530895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32512 10:17:30.568478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32513 10:17:30.568881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32515 10:17:30.607145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32516 10:17:30.607549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32518 10:17:30.647315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32519 10:17:30.647758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32521 10:17:30.686116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32522 10:17:30.686607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32524 10:17:30.722759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32525 10:17:30.723182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32527 10:17:30.759370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32528 10:17:30.759749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32530 10:17:30.814621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32531 10:17:30.815061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32533 10:17:30.856148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32534 10:17:30.856537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32536 10:17:30.894377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32537 10:17:30.894694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32539 10:17:30.931362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32540 10:17:30.931777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32542 10:17:30.969535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32544 10:17:30.970134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32545 10:17:31.003660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32546 10:17:31.004074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32548 10:17:31.038081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32549 10:17:31.038515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32551 10:17:31.073046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32553 10:17:31.073843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32554 10:17:31.121701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32555 10:17:31.122113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32557 10:17:31.166801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32558 10:17:31.167197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32560 10:17:31.207728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32562 10:17:31.208185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32563 10:17:31.247918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32564 10:17:31.248342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32566 10:17:31.287773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32567 10:17:31.288239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32569 10:17:31.355985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32570 10:17:31.356384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32572 10:17:31.399405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32573 10:17:31.399795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32575 10:17:31.456224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32576 10:17:31.456722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32578 10:17:31.491972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32579 10:17:31.492501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32581 10:17:31.526948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32582 10:17:31.527453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32584 10:17:31.561064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32586 10:17:31.561525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32587 10:17:31.594181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32589 10:17:31.594642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32590 10:17:31.629716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32591 10:17:31.630132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32593 10:17:31.663549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32595 10:17:31.664027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32596 10:17:31.696930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32598 10:17:31.697382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32599 10:17:31.731489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32600 10:17:31.731928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32602 10:17:31.775230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32604 10:17:31.775631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32605 10:17:31.818464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32606 10:17:31.818865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32608 10:17:31.859560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32610 10:17:31.859970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32611 10:17:31.905847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32612 10:17:31.906262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32614 10:17:31.940817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32616 10:17:31.941210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32617 10:17:31.974427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32618 10:17:31.974918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32620 10:17:32.010278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32622 10:17:32.010921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32623 10:17:32.055646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32624 10:17:32.056068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32626 10:17:32.091094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32627 10:17:32.091497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32629 10:17:32.130177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32631 10:17:32.130883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32632 10:17:32.186637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32634 10:17:32.187097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32635 10:17:32.222336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32636 10:17:32.222772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32638 10:17:32.263358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32639 10:17:32.263771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32641 10:17:32.298539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32642 10:17:32.298960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32644 10:17:32.349052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32646 10:17:32.349660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32647 10:17:32.403658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32648 10:17:32.404060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32650 10:17:32.459235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32651 10:17:32.459664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32653 10:17:32.514368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32654 10:17:32.514907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32656 10:17:32.558405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32657 10:17:32.558911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32659 10:17:32.599525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32660 10:17:32.599944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32662 10:17:32.646360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32663 10:17:32.646758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32665 10:17:32.691952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32666 10:17:32.692395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32668 10:17:32.727237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32669 10:17:32.727686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32671 10:17:32.762750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32672 10:17:32.763142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32674 10:17:32.801924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32675 10:17:32.802433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32677 10:17:32.848349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32679 10:17:32.848825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32680 10:17:32.883030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32682 10:17:32.883482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32683 10:17:32.918387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32685 10:17:32.918845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32686 10:17:32.958291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32687 10:17:32.958729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32689 10:17:32.994060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32690 10:17:32.994489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32692 10:17:33.030256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32693 10:17:33.030679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32695 10:17:33.085698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32696 10:17:33.086185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32698 10:17:33.124479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32699 10:17:33.124950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32701 10:17:33.163521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32702 10:17:33.163944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32704 10:17:33.206174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32705 10:17:33.206667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32707 10:17:33.247265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32708 10:17:33.247805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32710 10:17:33.283416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32711 10:17:33.283794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32713 10:17:33.318164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32714 10:17:33.318595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32716 10:17:33.353946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32717 10:17:33.354497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32719 10:17:33.392510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32720 10:17:33.392951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32722 10:17:33.439083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32723 10:17:33.439531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32725 10:17:33.485707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32726 10:17:33.486090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32728 10:17:33.522069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32730 10:17:33.522515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32731 10:17:33.556845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32733 10:17:33.557310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32734 10:17:33.590746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32735 10:17:33.591184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32737 10:17:33.628202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32738 10:17:33.628603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32740 10:17:33.662567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32741 10:17:33.662951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32743 10:17:33.696273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32744 10:17:33.696771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32746 10:17:33.734619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32747 10:17:33.735047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32749 10:17:33.777698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32750 10:17:33.778143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32752 10:17:33.821597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32753 10:17:33.822032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32755 10:17:33.868016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32756 10:17:33.868437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32758 10:17:33.914421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32759 10:17:33.914821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32761 10:17:33.958565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32762 10:17:33.959032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32764 10:17:33.994125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32765 10:17:33.994545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32767 10:17:34.029633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32768 10:17:34.030059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32770 10:17:34.075219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32771 10:17:34.075646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32773 10:17:34.110886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32774 10:17:34.111304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32776 10:17:34.144510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32777 10:17:34.145003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32779 10:17:34.179092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32780 10:17:34.179543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32782 10:17:34.212532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32783 10:17:34.212956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32785 10:17:34.247027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32787 10:17:34.247775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32788 10:17:34.282808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32789 10:17:34.283227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32791 10:17:34.320175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32792 10:17:34.320624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32794 10:17:34.358152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32796 10:17:34.358618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32797 10:17:34.398059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32798 10:17:34.398353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32800 10:17:34.435641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32801 10:17:34.435961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32803 10:17:34.470410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32804 10:17:34.470781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32806 10:17:34.507376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32807 10:17:34.507781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32809 10:17:34.545038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32811 10:17:34.545496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32812 10:17:34.582469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32813 10:17:34.582886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32815 10:17:34.623043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32816 10:17:34.623426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32818 10:17:34.670688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32819 10:17:34.671134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32821 10:17:34.708735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32823 10:17:34.709208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32824 10:17:34.762917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32825 10:17:34.763333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32827 10:17:34.814785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32828 10:17:34.815131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32830 10:17:34.860120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32831 10:17:34.860535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32833 10:17:34.894380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32834 10:17:34.894870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32836 10:17:34.936052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32837 10:17:34.936496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32839 10:17:34.975150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32841 10:17:34.975606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32842 10:17:35.011288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32844 10:17:35.011708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32845 10:17:35.045903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32847 10:17:35.046346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32848 10:17:35.086405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32850 10:17:35.086978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32851 10:17:35.141656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32852 10:17:35.142079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32854 10:17:35.188270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32855 10:17:35.188691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32857 10:17:35.222236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32858 10:17:35.222627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32860 10:17:35.266531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32862 10:17:35.267277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32863 10:17:35.311776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32864 10:17:35.312338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32866 10:17:35.367213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32867 10:17:35.367635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32869 10:17:35.407975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32871 10:17:35.408359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32872 10:17:35.452098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32874 10:17:35.452524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32875 10:17:35.501055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32877 10:17:35.501825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32878 10:17:35.540530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32879 10:17:35.541072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32881 10:17:35.577464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32882 10:17:35.577918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32884 10:17:35.614366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32886 10:17:35.614822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32887 10:17:35.652836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32889 10:17:35.653376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32890 10:17:35.691162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32891 10:17:35.691541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32893 10:17:35.728406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32895 10:17:35.728855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32896 10:17:35.772237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32898 10:17:35.772704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32899 10:17:35.810471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32901 10:17:35.810959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32902 10:17:35.846971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32904 10:17:35.847359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32905 10:17:35.894040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32906 10:17:35.894572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32908 10:17:35.932403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32909 10:17:35.932932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32911 10:17:35.971167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32913 10:17:35.971487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32914 10:17:36.019389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32915 10:17:36.019904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32917 10:17:36.058280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32918 10:17:36.058630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32920 10:17:36.095933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32921 10:17:36.096250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32923 10:17:36.146031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32924 10:17:36.146419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32926 10:17:36.188429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
32928 10:17:36.188797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
32929 10:17:36.230931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
32930 10:17:36.231395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
32932 10:17:36.268575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
32934 10:17:36.269050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
32935 10:17:36.314291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
32936 10:17:36.314741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
32938 10:17:36.362872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
32940 10:17:36.363308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
32941 10:17:36.415704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
32942 10:17:36.416149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
32944 10:17:36.488669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
32946 10:17:36.489141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
32947 10:17:36.535398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
32948 10:17:36.535807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
32950 10:17:36.574257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
32951 10:17:36.574704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
32953 10:17:36.619052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
32954 10:17:36.619491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
32956 10:17:36.654477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
32957 10:17:36.654874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
32959 10:17:36.697812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
32960 10:17:36.698214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
32962 10:17:36.737849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
32963 10:17:36.738394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
32965 10:17:36.784176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
32967 10:17:36.784603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
32968 10:17:36.823954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
32969 10:17:36.824393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
32971 10:17:36.864176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
32972 10:17:36.864595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
32974 10:17:36.901905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
32976 10:17:36.902320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
32977 10:17:36.943442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
32978 10:17:36.943897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
32980 10:17:36.992963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
32982 10:17:36.993455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
32983 10:17:37.043088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
32984 10:17:37.043659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
32986 10:17:37.087514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
32987 10:17:37.087998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
32989 10:17:37.129743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
32991 10:17:37.130378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
32992 10:17:37.170497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
32994 10:17:37.170956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
32995 10:17:37.216263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
32997 10:17:37.216637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
32998 10:17:37.271921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
32999 10:17:37.272499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
33001 10:17:37.320379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
33002 10:17:37.320945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
33004 10:17:37.373867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
33005 10:17:37.374342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
33007 10:17:37.410404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
33008 10:17:37.410817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
33010 10:17:37.453661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
33011 10:17:37.454112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
33013 10:17:37.488950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
33015 10:17:37.489640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
33016 10:17:37.538836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
33017 10:17:37.539273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
33019 10:17:37.582601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
33021 10:17:37.583080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
33022 10:17:37.625935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
33024 10:17:37.626401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
33025 10:17:37.674757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
33027 10:17:37.675158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
33028 10:17:37.713577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
33029 10:17:37.714106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
33031 10:17:37.765464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
33033 10:17:37.765924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
33034 10:17:37.809705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
33036 10:17:37.810164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
33037 10:17:37.859128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
33038 10:17:37.859556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
33040 10:17:37.901373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
33041 10:17:37.901830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
33043 10:17:37.941330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
33045 10:17:37.941805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
33046 10:17:37.979887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
33048 10:17:37.980558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
33049 10:17:38.019526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33050 10:17:38.019903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33052 10:17:38.067000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33053 10:17:38.067425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
33055 10:17:38.110942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33056 10:17:38.111348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33058 10:17:38.159170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33059 10:17:38.159566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33061 10:17:38.197080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
33063 10:17:38.197456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33064 10:17:38.239246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33065 10:17:38.239674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33067 10:17:38.279650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33068 10:17:38.280037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33070 10:17:38.316476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33071 10:17:38.316943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
33073 10:17:38.356924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33074 10:17:38.357492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33076 10:17:38.406591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33077 10:17:38.407018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33079 10:17:38.447229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33080 10:17:38.447648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
33082 10:17:38.487173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33083 10:17:38.487722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33085 10:17:38.529009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33087 10:17:38.529746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33088 10:17:38.566373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33089 10:17:38.566799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
33091 10:17:38.600318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33093 10:17:38.600783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33094 10:17:38.637691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
33096 10:17:38.638426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
33097 10:17:38.674677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33098 10:17:38.675247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33100 10:17:38.710346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
33102 10:17:38.710759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33103 10:17:38.754517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33104 10:17:38.754894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33106 10:17:38.792477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33107 10:17:38.792850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33109 10:17:38.799135 <47>[ 378.491444] systemd-journald[105]: Sent WATCHDOG=1 notification.
33110 10:17:38.852746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
33112 10:17:38.853321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33113 10:17:38.894960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33115 10:17:38.895353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33116 10:17:38.929570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33117 10:17:38.929994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33119 10:17:38.965971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33120 10:17:38.966391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
33122 10:17:39.003487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33123 10:17:39.003998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33125 10:17:39.050323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33126 10:17:39.050679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33128 10:17:39.100994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
33130 10:17:39.101626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33131 10:17:39.146661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33132 10:17:39.147155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33134 10:17:39.186959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33135 10:17:39.187373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33137 10:17:39.231989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33138 10:17:39.232408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
33140 10:17:39.270334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33141 10:17:39.270704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33143 10:17:39.306856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
33145 10:17:39.307611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
33146 10:17:39.347590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33147 10:17:39.348060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33149 10:17:39.388353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33150 10:17:39.388924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
33152 10:17:39.432069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33153 10:17:39.432448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33155 10:17:39.469396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33156 10:17:39.469883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33158 10:17:39.507180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33159 10:17:39.507598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
33161 10:17:39.542213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33162 10:17:39.542669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33164 10:17:39.578417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33165 10:17:39.578842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33167 10:17:39.615899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
33169 10:17:39.616379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33170 10:17:39.654109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33171 10:17:39.654527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33173 10:17:39.690516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33174 10:17:39.690926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33176 10:17:39.731201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33177 10:17:39.731688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33179 10:17:39.769793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33180 10:17:39.770216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33182 10:17:39.808268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33183 10:17:39.808696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33185 10:17:39.863136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33186 10:17:39.863688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33188 10:17:39.907662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33190 10:17:39.908262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33191 10:17:39.944333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33192 10:17:39.944765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33194 10:17:39.982688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33196 10:17:39.983450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33197 10:17:40.031632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33199 10:17:40.032056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33200 10:17:40.075419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33202 10:17:40.075947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33203 10:17:40.119154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33204 10:17:40.119635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33206 10:17:40.158500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33208 10:17:40.158883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33209 10:17:40.194069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33211 10:17:40.194506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33212 10:17:40.230286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33213 10:17:40.230709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33215 10:17:40.276510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33216 10:17:40.276893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33218 10:17:40.321872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33219 10:17:40.322296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33221 10:17:40.368109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33222 10:17:40.368534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33224 10:17:40.405597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33226 10:17:40.406066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33227 10:17:40.447028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33228 10:17:40.447460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33230 10:17:40.496546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33232 10:17:40.497022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33233 10:17:40.538673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33235 10:17:40.539117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33236 10:17:40.579291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33238 10:17:40.579752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33239 10:17:40.615467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33240 10:17:40.615972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33242 10:17:40.665796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33243 10:17:40.666227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33245 10:17:40.711257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33247 10:17:40.711727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33248 10:17:40.756868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33250 10:17:40.757318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33251 10:17:40.802514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33253 10:17:40.803120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33254 10:17:40.840041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33255 10:17:40.840524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33257 10:17:40.886899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33258 10:17:40.887291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33260 10:17:40.924172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33262 10:17:40.924651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33263 10:17:40.961518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33264 10:17:40.961942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33266 10:17:40.998174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33267 10:17:40.998605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33269 10:17:41.037896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33270 10:17:41.038307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33272 10:17:41.077541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33273 10:17:41.078007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33275 10:17:41.122757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33276 10:17:41.123219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33278 10:17:41.158126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33279 10:17:41.158546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33281 10:17:41.198498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33282 10:17:41.198892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33284 10:17:41.232672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33286 10:17:41.233139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33287 10:17:41.283795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33289 10:17:41.284257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33290 10:17:41.336117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33292 10:17:41.336576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33293 10:17:41.392174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33294 10:17:41.392565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33296 10:17:41.444449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33297 10:17:41.444857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33299 10:17:41.483850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33301 10:17:41.484227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33302 10:17:41.539692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33303 10:17:41.540122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33305 10:17:41.598678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33306 10:17:41.599122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33308 10:17:41.637368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33309 10:17:41.637800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33311 10:17:41.677985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33312 10:17:41.678481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33314 10:17:41.722891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33316 10:17:41.723529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33317 10:17:41.766181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33318 10:17:41.766669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33320 10:17:41.814389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33321 10:17:41.814829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33323 10:17:41.856789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33325 10:17:41.857262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33326 10:17:41.895172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33327 10:17:41.895611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33329 10:17:41.938417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33331 10:17:41.938985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33332 10:17:41.977827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33333 10:17:41.978123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33335 10:17:42.014796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33336 10:17:42.015139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33338 10:17:42.048705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33340 10:17:42.049298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33341 10:17:42.086116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33342 10:17:42.086661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33344 10:17:42.122019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33346 10:17:42.122777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33347 10:17:42.156793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33348 10:17:42.157249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33350 10:17:42.190315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33351 10:17:42.190794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33353 10:17:42.224359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33354 10:17:42.224775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33356 10:17:42.258364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33358 10:17:42.258839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33359 10:17:42.292068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33360 10:17:42.292485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33362 10:17:42.326235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33363 10:17:42.326719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33365 10:17:42.360527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33367 10:17:42.361003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33368 10:17:42.394845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33370 10:17:42.395562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33371 10:17:42.428166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33373 10:17:42.428739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33374 10:17:42.462642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33376 10:17:42.463210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33377 10:17:42.504495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33378 10:17:42.504962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33380 10:17:42.540027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33381 10:17:42.540601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33383 10:17:42.577351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33385 10:17:42.577944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33386 10:17:42.611295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33387 10:17:42.611717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33389 10:17:42.647122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33390 10:17:42.647484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33392 10:17:42.687609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33393 10:17:42.687967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33395 10:17:42.723317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33396 10:17:42.723658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33398 10:17:42.766839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33399 10:17:42.767211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33401 10:17:42.811341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33402 10:17:42.811659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33404 10:17:42.846951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33406 10:17:42.847597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33407 10:17:42.886009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33409 10:17:42.886387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33410 10:17:42.931035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33412 10:17:42.931804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33413 10:17:42.975110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33415 10:17:42.975670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33416 10:17:43.014539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33417 10:17:43.014963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33419 10:17:43.047546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33421 10:17:43.048183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33422 10:17:43.084454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33424 10:17:43.084862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33425 10:17:43.122926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33426 10:17:43.123333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33428 10:17:43.160370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33429 10:17:43.160702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33431 10:17:43.197669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33432 10:17:43.198002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33434 10:17:43.233915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33435 10:17:43.234239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33437 10:17:43.270654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33439 10:17:43.270976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33440 10:17:43.309450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33441 10:17:43.309918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33443 10:17:43.344137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33444 10:17:43.344567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33446 10:17:43.380123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33447 10:17:43.380677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33449 10:17:43.416294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33451 10:17:43.416543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33452 10:17:43.464414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33454 10:17:43.464872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33455 10:17:43.500437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33456 10:17:43.500773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33458 10:17:43.534994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33459 10:17:43.535390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33461 10:17:43.569873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33463 10:17:43.570470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33464 10:17:43.605310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33466 10:17:43.605665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33467 10:17:43.642537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33468 10:17:43.642856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33470 10:17:43.681794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33471 10:17:43.682105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33473 10:17:43.725337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33474 10:17:43.725680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33476 10:17:43.762753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33478 10:17:43.763091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33479 10:17:43.798624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33481 10:17:43.799066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33482 10:17:43.839333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33484 10:17:43.839752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33485 10:17:43.880508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33487 10:17:43.881132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33488 10:17:43.925962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33489 10:17:43.926391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33491 10:17:43.980666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33492 10:17:43.981069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33494 10:17:44.022690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33495 10:17:44.023085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33497 10:17:44.065502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33499 10:17:44.066277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33500 10:17:44.103292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33501 10:17:44.103656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33503 10:17:44.140259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33504 10:17:44.140585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33506 10:17:44.176906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33508 10:17:44.177466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33509 10:17:44.216104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33510 10:17:44.216470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33512 10:17:44.252368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33514 10:17:44.252785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33515 10:17:44.290439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33516 10:17:44.290921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33518 10:17:44.327183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33519 10:17:44.327662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33521 10:17:44.364300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33522 10:17:44.364715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33524 10:17:44.400444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33525 10:17:44.400868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33527 10:17:44.435861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33529 10:17:44.436320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33530 10:17:44.471986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33531 10:17:44.472419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33533 10:17:44.510797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33534 10:17:44.511223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33536 10:17:44.546328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33538 10:17:44.546936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33539 10:17:44.583038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33540 10:17:44.583500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33542 10:17:44.620101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33544 10:17:44.620482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33545 10:17:44.660394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33546 10:17:44.660805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33548 10:17:44.697826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33549 10:17:44.698213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33551 10:17:44.736507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33553 10:17:44.736963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33554 10:17:44.774355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33555 10:17:44.774709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33557 10:17:44.816544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33559 10:17:44.817159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33560 10:17:44.861115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33562 10:17:44.861553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33563 10:17:44.903392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33564 10:17:44.903813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33566 10:17:44.944878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33568 10:17:44.945543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33569 10:17:44.987605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33570 10:17:44.987948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33572 10:17:45.031614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33573 10:17:45.031991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33575 10:17:45.066401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33576 10:17:45.066753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33578 10:17:45.103156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33579 10:17:45.103489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33581 10:17:45.139846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33582 10:17:45.140220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33584 10:17:45.176863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33586 10:17:45.177207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33587 10:17:45.213867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33588 10:17:45.214351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33590 10:17:45.254550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33592 10:17:45.255047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33593 10:17:45.293996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33594 10:17:45.294496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33596 10:17:45.329819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33597 10:17:45.330355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33599 10:17:45.380021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33600 10:17:45.380395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33602 10:17:45.415696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33604 10:17:45.416098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33605 10:17:45.450872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33606 10:17:45.451256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33608 10:17:45.487544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33610 10:17:45.487933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33611 10:17:45.529602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33612 10:17:45.530053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33614 10:17:45.563284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33616 10:17:45.563945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33617 10:17:45.602480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33618 10:17:45.603046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33620 10:17:45.637978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33622 10:17:45.638449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33623 10:17:45.677393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33624 10:17:45.677808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33626 10:17:45.723239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33627 10:17:45.723658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33629 10:17:45.774890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33630 10:17:45.775387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33632 10:17:45.824134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33633 10:17:45.824559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33635 10:17:45.859158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33636 10:17:45.859599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33638 10:17:45.891822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33639 10:17:45.892234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33641 10:17:45.924197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33642 10:17:45.924632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33644 10:17:45.956914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33646 10:17:45.957345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33647 10:17:45.990126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33649 10:17:45.990769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33650 10:17:46.023458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33652 10:17:46.024098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33653 10:17:46.056306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33654 10:17:46.056807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33656 10:17:46.089229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33657 10:17:46.089699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33659 10:17:46.122030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33660 10:17:46.122507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33662 10:17:46.154307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33663 10:17:46.154787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33665 10:17:46.187680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33666 10:17:46.188159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33668 10:17:46.220044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33669 10:17:46.220511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33671 10:17:46.252523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33672 10:17:46.252937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33674 10:17:46.287070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33675 10:17:46.287486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33677 10:17:46.323487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33678 10:17:46.323903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33680 10:17:46.361620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33681 10:17:46.362054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33683 10:17:46.398683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33684 10:17:46.399108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33686 10:17:46.433215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33687 10:17:46.433667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33689 10:17:46.466873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33690 10:17:46.467288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33692 10:17:46.501720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33693 10:17:46.502131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33695 10:17:46.534613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33697 10:17:46.535068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33698 10:17:46.566602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33699 10:17:46.567017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33701 10:17:46.599775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33702 10:17:46.600197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33704 10:17:46.632282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33705 10:17:46.632711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33707 10:17:46.687069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33708 10:17:46.687581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33710 10:17:46.733938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33711 10:17:46.734351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33713 10:17:46.769392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33715 10:17:46.769871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33716 10:17:46.808059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33717 10:17:46.808423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33719 10:17:46.856524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33720 10:17:46.856923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33722 10:17:46.891968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33724 10:17:46.892615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33725 10:17:46.924892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33727 10:17:46.925486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33728 10:17:46.957885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33729 10:17:46.958427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33731 10:17:46.992518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33732 10:17:46.992995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33734 10:17:47.026586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33735 10:17:47.027047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33737 10:17:47.061758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33738 10:17:47.062300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33740 10:17:47.098996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33741 10:17:47.099422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33743 10:17:47.135313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33744 10:17:47.135727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33746 10:17:47.171446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33747 10:17:47.171867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33749 10:17:47.207211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33750 10:17:47.207675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33752 10:17:47.242974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33754 10:17:47.243432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33755 10:17:47.278341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33756 10:17:47.278715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33758 10:17:47.312643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33760 10:17:47.313116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33761 10:17:47.350934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33762 10:17:47.351472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33764 10:17:47.389938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33765 10:17:47.390435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33767 10:17:47.428113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33769 10:17:47.428771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33770 10:17:47.467968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33771 10:17:47.468530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33773 10:17:47.505329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33774 10:17:47.505747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33776 10:17:47.544314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33777 10:17:47.544755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33779 10:17:47.579253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33780 10:17:47.579683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33782 10:17:47.623036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33784 10:17:47.623411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33785 10:17:47.658030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33787 10:17:47.658395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33788 10:17:47.691703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33789 10:17:47.692070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33791 10:17:47.730250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33793 10:17:47.730933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33794 10:17:47.767198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33795 10:17:47.767714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33797 10:17:47.812112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33799 10:17:47.812507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33800 10:17:47.846899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33801 10:17:47.847310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33803 10:17:47.882264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33804 10:17:47.882786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33806 10:17:47.922866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33808 10:17:47.923266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33809 10:17:47.976428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33810 10:17:47.976923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33812 10:17:48.011327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33813 10:17:48.011896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33815 10:17:48.044983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33817 10:17:48.045560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33818 10:17:48.079213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33819 10:17:48.079615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33821 10:17:48.112517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33822 10:17:48.112916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33824 10:17:48.146327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33825 10:17:48.146796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33827 10:17:48.182142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33829 10:17:48.182787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33830 10:17:48.216384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33832 10:17:48.216852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33833 10:17:48.270816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33834 10:17:48.271227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33836 10:17:48.312447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33837 10:17:48.312867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33839 10:17:48.354130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33840 10:17:48.354561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33842 10:17:48.389004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33844 10:17:48.389464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33845 10:17:48.423858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33846 10:17:48.424279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33848 10:17:48.458675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33849 10:17:48.459094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33851 10:17:48.493902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33852 10:17:48.494337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33854 10:17:48.528417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33856 10:17:48.528881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33857 10:17:48.567201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33859 10:17:48.567655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33860 10:17:48.604020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33862 10:17:48.604506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33863 10:17:48.646463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33864 10:17:48.646804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33866 10:17:48.695119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33867 10:17:48.695497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33869 10:17:48.731706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33870 10:17:48.732022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33872 10:17:48.771624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33874 10:17:48.772202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33875 10:17:48.804284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33877 10:17:48.804844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33878 10:17:48.837497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33879 10:17:48.837919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33881 10:17:48.872518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33882 10:17:48.873064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33884 10:17:48.917633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33886 10:17:48.918106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33887 10:17:48.959582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33888 10:17:48.959981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33890 10:17:48.998775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33891 10:17:48.999117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33893 10:17:49.037619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33894 10:17:49.037990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33896 10:17:49.085555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33898 10:17:49.085876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33899 10:17:49.121624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33901 10:17:49.121941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33902 10:17:49.157402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33903 10:17:49.157769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33905 10:17:49.195942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33906 10:17:49.196305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33908 10:17:49.235945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33909 10:17:49.236372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33911 10:17:49.272232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33912 10:17:49.272631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33914 10:17:49.316567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33916 10:17:49.317067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33917 10:17:49.361089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33919 10:17:49.361560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33920 10:17:49.406469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33921 10:17:49.406896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33923 10:17:49.451531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33924 10:17:49.451918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33926 10:17:49.503401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33927 10:17:49.503793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33929 10:17:49.541188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33930 10:17:49.541711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
33932 10:17:49.575771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33933 10:17:49.576194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33935 10:17:49.609856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33936 10:17:49.610257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33938 10:17:49.648890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
33940 10:17:49.649457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33941 10:17:49.699305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33942 10:17:49.699612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33944 10:17:49.736838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33946 10:17:49.737138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33947 10:17:49.772815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
33949 10:17:49.773214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33950 10:17:49.811505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33952 10:17:49.811890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33953 10:17:49.848309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33954 10:17:49.848606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33956 10:17:49.884276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33957 10:17:49.884686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
33959 10:17:49.928298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33961 10:17:49.929024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33962 10:17:49.963325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
33963 10:17:49.963730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
33965 10:17:49.998760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33967 10:17:49.999409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33968 10:17:50.043651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33969 10:17:50.043989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
33971 10:17:50.086777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33972 10:17:50.087144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33974 10:17:50.126074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33976 10:17:50.126724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33977 10:17:50.159980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
33979 10:17:50.160360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33980 10:17:50.192315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33982 10:17:50.192872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33983 10:17:50.224684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33984 10:17:50.225152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33986 10:17:50.257840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33987 10:17:50.258258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
33989 10:17:50.291373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33990 10:17:50.291799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33992 10:17:50.326763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33994 10:17:50.327233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33995 10:17:50.360635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33996 10:17:50.360991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
33998 10:17:50.394241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33999 10:17:50.394637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
34001 10:17:50.433504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
34002 10:17:50.433902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
34004 10:17:50.470319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
34005 10:17:50.470706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
34007 10:17:50.503641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
34008 10:17:50.504023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
34010 10:17:50.537718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
34012 10:17:50.538188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
34013 10:17:50.572086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
34014 10:17:50.572522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
34016 10:17:50.606416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
34017 10:17:50.606841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
34019 10:17:50.646726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
34020 10:17:50.647078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
34022 10:17:50.682447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
34023 10:17:50.682857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
34025 10:17:50.718777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
34026 10:17:50.719194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
34028 10:17:50.758551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
34029 10:17:50.758945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
34031 10:17:50.802304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
34033 10:17:50.802792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
34034 10:17:50.852124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
34036 10:17:50.852507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
34037 10:17:50.904325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
34039 10:17:50.904754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
34040 10:17:50.958681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
34042 10:17:50.959085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
34043 10:17:51.008209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
34044 10:17:51.008634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
34046 10:17:51.056301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
34047 10:17:51.056846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
34049 10:17:51.115348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
34050 10:17:51.115782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
34052 10:17:51.154352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
34053 10:17:51.154790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
34055 10:17:51.190727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
34056 10:17:51.191156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
34058 10:17:51.228938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
34060 10:17:51.229362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
34061 10:17:51.270684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
34062 10:17:51.271073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
34064 10:17:51.325143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
34066 10:17:51.325613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
34067 10:17:51.374239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
34068 10:17:51.374679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
34070 10:17:51.428246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
34071 10:17:51.428648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
34073 10:17:51.470214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
34074 10:17:51.470639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
34076 10:17:51.508530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
34077 10:17:51.508956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
34079 10:17:51.543620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
34081 10:17:51.544080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
34082 10:17:51.580046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
34083 10:17:51.580453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
34085 10:17:51.616682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
34087 10:17:51.617103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
34088 10:17:51.652608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
34090 10:17:51.653373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
34091 10:17:51.688589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
34092 10:17:51.689028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
34094 10:17:51.724747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
34096 10:17:51.725216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
34097 10:17:51.763718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
34099 10:17:51.764176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
34100 10:17:51.847590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
34101 10:17:51.848109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
34103 10:17:51.884346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
34104 10:17:51.884781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
34106 10:17:51.921727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
34108 10:17:51.922182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
34109 10:17:51.961321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
34110 10:17:51.961740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
34112 10:17:52.008102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
34113 10:17:52.008503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
34115 10:17:52.058971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
34116 10:17:52.059405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
34118 10:17:52.098523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
34119 10:17:52.099021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
34121 10:17:52.138467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
34122 10:17:52.139026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
34124 10:17:52.186287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
34126 10:17:52.187048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
34127 10:17:52.222392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
34129 10:17:52.222768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
34130 10:17:52.262153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
34131 10:17:52.262530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
34133 10:17:52.298957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
34134 10:17:52.299447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
34136 10:17:52.333808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
34138 10:17:52.334272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
34139 10:17:52.368471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
34141 10:17:52.368946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
34142 10:17:52.413718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
34143 10:17:52.414229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
34145 10:17:52.459758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
34146 10:17:52.460109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
34148 10:17:52.506594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
34149 10:17:52.506972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
34151 10:17:52.553029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
34153 10:17:52.553442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
34154 10:17:52.594639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
34155 10:17:52.594980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
34157 10:17:52.630420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
34158 10:17:52.630861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
34160 10:17:52.673843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
34161 10:17:52.674292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
34163 10:17:52.719758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
34164 10:17:52.720112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
34166 10:17:52.754240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
34168 10:17:52.754687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
34169 10:17:52.787434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
34170 10:17:52.787827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
34172 10:17:52.822259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34173 10:17:52.822673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34175 10:17:52.875805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34176 10:17:52.876241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34178 10:17:52.930123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34179 10:17:52.930459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34181 10:17:52.983908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34182 10:17:52.984277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34184 10:17:53.027275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34185 10:17:53.027627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34187 10:17:53.061933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34188 10:17:53.062361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34190 10:17:53.096044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34191 10:17:53.096515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34193 10:17:53.131791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34194 10:17:53.132351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34196 10:17:53.166166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34198 10:17:53.166635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34199 10:17:53.214121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34201 10:17:53.214546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34202 10:17:53.250556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34203 10:17:53.250898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34205 10:17:53.304704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34206 10:17:53.305176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34208 10:17:53.359739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34209 10:17:53.360147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34211 10:17:53.396927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34213 10:17:53.397301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34214 10:17:53.432452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34216 10:17:53.433187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34217 10:17:53.467539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34218 10:17:53.468012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34220 10:17:53.503293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34221 10:17:53.503695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34223 10:17:53.547441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34224 10:17:53.547860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34226 10:17:53.582015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34228 10:17:53.582637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34229 10:17:53.616494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34230 10:17:53.616901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34232 10:17:53.651239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34233 10:17:53.651602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34235 10:17:53.685061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34237 10:17:53.685466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34238 10:17:53.720447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34239 10:17:53.720946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34241 10:17:53.764436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34242 10:17:53.764877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34244 10:17:53.806511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34245 10:17:53.806934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34247 10:17:53.842265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34248 10:17:53.842588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34250 10:17:53.886533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34251 10:17:53.886913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34253 10:17:53.926714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34254 10:17:53.927085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34256 10:17:53.972627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34258 10:17:53.973209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34259 10:17:54.019398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34261 10:17:54.019879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34262 10:17:54.056472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34264 10:17:54.056941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34265 10:17:54.092494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34266 10:17:54.093012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34268 10:17:54.129718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34269 10:17:54.130189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34271 10:17:54.171589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34273 10:17:54.172281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34274 10:17:54.215244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34275 10:17:54.215814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34277 10:17:54.252950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34279 10:17:54.253433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34280 10:17:54.287112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34281 10:17:54.287582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34283 10:17:54.330125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34284 10:17:54.330516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34286 10:17:54.367793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34287 10:17:54.368202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34289 10:17:54.406133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34290 10:17:54.406523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34292 10:17:54.440341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34293 10:17:54.440725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34295 10:17:54.477174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34297 10:17:54.477933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34298 10:17:54.513587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34300 10:17:54.514081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34301 10:17:54.547729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34302 10:17:54.548110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34304 10:17:54.582767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34305 10:17:54.583162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34307 10:17:54.616629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34308 10:17:54.617109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34310 10:17:54.650721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34311 10:17:54.651179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34313 10:17:54.684396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34314 10:17:54.684865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34316 10:17:54.719065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34317 10:17:54.719517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34319 10:17:54.759210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34320 10:17:54.759629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34322 10:17:54.794927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34324 10:17:54.795389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34325 10:17:54.830188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34326 10:17:54.830603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34328 10:17:54.865039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34330 10:17:54.865491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34331 10:17:54.899698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34332 10:17:54.900161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34334 10:17:54.937877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34335 10:17:54.938435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34337 10:17:54.974805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34338 10:17:54.975280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34340 10:17:55.009989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34342 10:17:55.010498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34343 10:17:55.044090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34345 10:17:55.044661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34346 10:17:55.078628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34348 10:17:55.079368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34349 10:17:55.116076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34350 10:17:55.116637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34352 10:17:55.160285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34353 10:17:55.160755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34355 10:17:55.195418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34357 10:17:55.196158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34358 10:17:55.230783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34359 10:17:55.231201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34361 10:17:55.266284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34362 10:17:55.266836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34364 10:17:55.300333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34366 10:17:55.301080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34367 10:17:55.334826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34369 10:17:55.335280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34370 10:17:55.370017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34372 10:17:55.370599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34373 10:17:55.405449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34375 10:17:55.406045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34376 10:17:55.439354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34377 10:17:55.439814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34379 10:17:55.473794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34380 10:17:55.474210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34382 10:17:55.509962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34383 10:17:55.510349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34385 10:17:55.546148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34386 10:17:55.546558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34388 10:17:55.580475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34389 10:17:55.580889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34391 10:17:55.625893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34392 10:17:55.626325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34394 10:17:55.660583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34396 10:17:55.661162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34397 10:17:55.710303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34398 10:17:55.710775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34400 10:17:55.746500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34401 10:17:55.746819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34403 10:17:55.782121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34404 10:17:55.782550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34406 10:17:55.815401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34407 10:17:55.815829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34409 10:17:55.848976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34411 10:17:55.849354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34412 10:17:55.883887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34413 10:17:55.884276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34415 10:17:55.918797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34416 10:17:55.919219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34418 10:17:55.955420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34419 10:17:55.955795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34421 10:17:55.992120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34423 10:17:55.992625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34424 10:17:56.028110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34425 10:17:56.028646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34427 10:17:56.064574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34428 10:17:56.065106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34430 10:17:56.101458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34431 10:17:56.102014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34433 10:17:56.138670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34434 10:17:56.139045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34436 10:17:56.173558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34437 10:17:56.174048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34439 10:17:56.210575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34440 10:17:56.211042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34442 10:17:56.247829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34444 10:17:56.248467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34445 10:17:56.282627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34446 10:17:56.283037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34448 10:17:56.330064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34449 10:17:56.330489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34451 10:17:56.370738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34452 10:17:56.371162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34454 10:17:56.426922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34455 10:17:56.427332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34457 10:17:56.460309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34458 10:17:56.460660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34460 10:17:56.492534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34462 10:17:56.492937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34463 10:17:56.535488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34464 10:17:56.535867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34466 10:17:56.573762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34467 10:17:56.574070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34469 10:17:56.620217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34471 10:17:56.620971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34472 10:17:56.658349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34473 10:17:56.658785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34475 10:17:56.701594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34476 10:17:56.702055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34478 10:17:56.735824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34480 10:17:56.736410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34481 10:17:56.783089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34482 10:17:56.783523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34484 10:17:56.832985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34486 10:17:56.833421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34487 10:17:56.881978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34488 10:17:56.882408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34490 10:17:56.943723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34492 10:17:56.944333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34493 10:17:56.992475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34494 10:17:56.992890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34496 10:17:57.030495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34497 10:17:57.030920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34499 10:17:57.067086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34500 10:17:57.067516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34502 10:17:57.103277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34503 10:17:57.103694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34505 10:17:57.142459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34506 10:17:57.142884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34508 10:17:57.186924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34509 10:17:57.187425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34511 10:17:57.233581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34512 10:17:57.234028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34514 10:17:57.279979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34515 10:17:57.280411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34517 10:17:57.315153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34518 10:17:57.315602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34520 10:17:57.364635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34522 10:17:57.365111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34523 10:17:57.398980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34524 10:17:57.399377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34526 10:17:57.433247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34528 10:17:57.433747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34529 10:17:57.467819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34530 10:17:57.468237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34532 10:17:57.503480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34533 10:17:57.503949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34535 10:17:57.551524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34537 10:17:57.551975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34538 10:17:57.597997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34540 10:17:57.598754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34541 10:17:57.632877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34543 10:17:57.633296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34544 10:17:57.672400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34546 10:17:57.672773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34547 10:17:57.708118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34548 10:17:57.708516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34550 10:17:57.748628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34551 10:17:57.749050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34553 10:17:57.787370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34554 10:17:57.787805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34556 10:17:57.830641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34557 10:17:57.831028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34559 10:17:57.874510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34560 10:17:57.874928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34562 10:17:57.918569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34563 10:17:57.918846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34565 10:17:57.963558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34566 10:17:57.963969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34568 10:17:58.006213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34569 10:17:58.006636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34571 10:17:58.047610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34572 10:17:58.048042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34574 10:17:58.090516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34575 10:17:58.090977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34577 10:17:58.142774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34578 10:17:58.143159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34580 10:17:58.178218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34581 10:17:58.178648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34583 10:17:58.215079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34584 10:17:58.215518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34586 10:17:58.254567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34588 10:17:58.254991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34589 10:17:58.308992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34591 10:17:58.309596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34592 10:17:58.357136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34593 10:17:58.357552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34595 10:17:58.390828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34596 10:17:58.391209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34598 10:17:58.426224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34599 10:17:58.426721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34601 10:17:58.462025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34602 10:17:58.462516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34604 10:17:58.500551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34605 10:17:58.501125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34607 10:17:58.503995 + set +x
34608 10:17:58.504307 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 592458_1.1.3.5>
34609 10:17:58.504731 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 592458_1.1.3.5
34610 10:17:58.504943 Ending use of test pattern.
34611 10:17:58.505131 Ending test lava.1_kselftest-arm64_qemu (592458_1.1.3.5), duration 375.14
34613 10:17:58.508247 ok: lava_test_shell seems to have completed
34614 10:17:58.613099 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34615 10:17:58.616338 end: 3.1 lava-test-shell (duration 00:06:17) [common]
34616 10:17:58.616461 end: 3 lava-test-retry (duration 00:06:17) [common]
34617 10:17:58.616573 start: 4 finalize (timeout 00:02:35) [common]
34618 10:17:58.616684 start: 4.1 power-off (timeout 00:00:30) [common]
34619 10:17:58.616784 end: 4.1 power-off (duration 00:00:00) [common]
34620 10:17:58.616880 start: 4.2 read-feedback (timeout 00:02:35) [common]
34622 10:17:58.617366 Listened to connection for namespace 'common' for up to 1s
34623 10:17:59.621753 Finalising connection for namespace 'common'
34625 10:17:59.722658 / # poweroff
34626 10:17:59.723135 Already disconnected
34627 10:17:59.723244 poweroff
34628 10:17:59.824023 end: 4.2 read-feedback (duration 00:00:01) [common]
34629 10:17:59.824241 Already disconnected
34630 10:17:59.824369 end: 4 finalize (duration 00:00:01) [common]
34631 10:17:59.824503 Cleaning after the job
34632 10:17:59.824655 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/592458/deployimages-om5uhj3c/kernel
34633 10:17:59.830985 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/592458/deployimages-om5uhj3c/ramdisk
34634 10:17:59.845476 Stopping the qemu container lava-docker-qemu-592458-2.1.1-sta8tig9s0
34635 10:18:00.836147 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/592458
34636 10:18:00.927397 Job finished correctly