Boot log: qemu_arm64-virt-gicv3
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
- Errors: 0
1 11:43:01.411117 lava-dispatcher, installed at version: 2023.01
2 11:43:01.411336 start: 0 validate
3 11:43:01.411462 Start time: 2023-06-15 11:43:01.411455+00:00 (UTC)
4 11:43:01.412606 Validating that http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image exists
5 11:43:01.755390 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/rootfs.cpio.gz exists
6 11:43:01.926723 cmd: ['docker', 'pull', 'kernelci/qemu']
7 11:43:01.926922 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 11:43:02.085339 >> Using default tag: latest
9 11:43:03.252714 >> latest: Pulling from kernelci/qemu
10 11:43:03.284811 >> Digest: sha256:ce67b4aa6149816ab5c39a34ebc77720cac0c3651072f2c36655342e38024d42
11 11:43:03.284994 >> Status: Image is up to date for kernelci/qemu:latest
12 11:43:03.352006 >> docker.io/kernelci/qemu:latest
13 11:43:03.355145 Returned 0 in 1 seconds
14 11:43:03.492072 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 11:43:03.492520 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 11:43:06.777169 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 11:43:06.777608 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 11:43:09.074153 Returned 0 in 5 seconds
19 11:43:09.175437 validate duration: 7.76
21 11:43:09.175999 start: 1 deployimages (timeout 00:03:00) [common]
22 11:43:09.176174 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 11:43:09.176659 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q
24 11:43:09.176917 makedir: /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin
25 11:43:09.177122 makedir: /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/tests
26 11:43:09.177342 makedir: /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/results
27 11:43:09.177566 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-add-keys
28 11:43:09.177865 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-add-sources
29 11:43:09.178116 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-background-process-start
30 11:43:09.178365 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-background-process-stop
31 11:43:09.178607 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-common-functions
32 11:43:09.178844 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-echo-ipv4
33 11:43:09.179087 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-install-packages
34 11:43:09.179325 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-installed-packages
35 11:43:09.179559 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-os-build
36 11:43:09.179796 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-probe-channel
37 11:43:09.180035 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-probe-ip
38 11:43:09.180274 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-target-ip
39 11:43:09.180510 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-target-mac
40 11:43:09.180746 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-target-storage
41 11:43:09.180986 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-test-case
42 11:43:09.181225 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-test-event
43 11:43:09.181492 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-test-feedback
44 11:43:09.181752 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-test-raise
45 11:43:09.181997 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-test-reference
46 11:43:09.182233 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-test-runner
47 11:43:09.182468 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-test-set
48 11:43:09.182703 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-test-shell
49 11:43:09.182945 Updating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-install-packages (oe)
50 11:43:09.183254 Updating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/bin/lava-installed-packages (oe)
51 11:43:09.183497 Creating /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/environment
52 11:43:09.183702 LAVA metadata
53 11:43:09.183847 - LAVA_JOB_ID=615297
54 11:43:09.183979 - LAVA_DISPATCHER_IP=172.27.0.2
55 11:43:09.184187 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 11:43:09.184323 skipped lava-vland-overlay
57 11:43:09.184473 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 11:43:09.184638 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 11:43:09.184767 skipped lava-multinode-overlay
60 11:43:09.184911 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 11:43:09.185066 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 11:43:09.185219 Loading test definitions
63 11:43:09.185429 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 11:43:09.185581 Using /lava-615297 at stage 0
65 11:43:09.186222 uuid=615297_1.1.3.1 testdef=None
66 11:43:09.186406 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 11:43:09.186565 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 11:43:09.187462 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 11:43:09.187940 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 11:43:09.189025 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 11:43:09.189533 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 11:43:09.190598 runner path: /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/0/tests/0_timesync-off test_uuid 615297_1.1.3.1
75 11:43:09.190887 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 11:43:09.191359 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 11:43:09.191499 Using /lava-615297 at stage 0
79 11:43:09.191697 Fetching tests from https://github.com/kernelci/test-definitions.git
80 11:43:09.191850 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/0/tests/1_kselftest-arm64_qemu'
81 11:43:12.237468 Running '/usr/bin/git checkout kernelci.org
82 11:43:12.378417 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 11:43:12.379981 uuid=615297_1.1.3.5 testdef=None
84 11:43:12.380244 end: 1.1.3.5 git-repo-action (duration 00:00:03) [common]
86 11:43:12.380795 start: 1.1.3.6 test-overlay (timeout 00:02:57) [common]
87 11:43:12.382454 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 11:43:12.382946 start: 1.1.3.7 test-install-overlay (timeout 00:02:57) [common]
90 11:43:12.385258 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 11:43:12.385812 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:57) [common]
93 11:43:12.388649 runner path: /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/0/tests/1_kselftest-arm64_qemu test_uuid 615297_1.1.3.5
94 11:43:12.388919 BOARD='qemu_arm64-virt-gicv3'
95 11:43:12.389136 BRANCH='cip'
96 11:43:12.389341 SKIPFILE='/dev/null'
97 11:43:12.389541 SKIP_INSTALL='True'
98 11:43:12.389733 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
99 11:43:12.389893 TST_CASENAME=''
100 11:43:12.390016 TST_CMDFILES='arm64'
101 11:43:12.390304 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 11:43:12.390776 Creating lava-test-runner.conf files
104 11:43:12.390908 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/615297/lava-overlay-0__th40q/lava-615297/0 for stage 0
105 11:43:12.391091 - 0_timesync-off
106 11:43:12.391231 - 1_kselftest-arm64_qemu
107 11:43:12.391419 end: 1.1.3 test-definition (duration 00:00:03) [common]
108 11:43:12.391590 start: 1.1.4 compress-overlay (timeout 00:02:57) [common]
109 11:43:21.184614 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 11:43:21.184808 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:48) [common]
111 11:43:21.184904 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 11:43:21.185012 end: 1.1 lava-overlay (duration 00:00:12) [common]
113 11:43:21.185103 start: 1.2 apply-overlay-guest (timeout 00:02:48) [common]
114 11:43:21.185181 Overlay: /var/lib/lava/dispatcher/tmp/615297/compress-overlay-h90i3zxp/overlay-1.1.4.tar.gz
115 11:43:36.064014 end: 1.2 apply-overlay-guest (duration 00:00:15) [common]
117 11:43:36.064611 start: 1.3 deploy-device-env (timeout 00:02:33) [common]
118 11:43:36.064720 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 11:43:36.064833 start: 1.4 download-retry (timeout 00:02:33) [common]
120 11:43:36.064955 start: 1.4.1 http-download (timeout 00:02:33) [common]
121 11:43:36.065191 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
122 11:43:36.065282 saving as /var/lib/lava/dispatcher/tmp/615297/deployimages-0qs6rb_b/kernel/Image
123 11:43:36.065364 total size: 47581696 (45MB)
124 11:43:36.065446 No compression specified
125 11:43:36.406877 progress 0% (0MB)
126 11:43:37.431301 progress 5% (2MB)
127 11:43:37.776474 progress 10% (4MB)
128 11:43:37.953019 progress 15% (6MB)
129 11:43:38.297876 progress 20% (9MB)
130 11:43:38.469246 progress 25% (11MB)
131 11:43:38.800310 progress 30% (13MB)
132 11:43:38.976460 progress 35% (15MB)
133 11:43:39.154226 progress 40% (18MB)
134 11:43:39.483548 progress 45% (20MB)
135 11:43:39.659910 progress 50% (22MB)
136 11:43:39.834088 progress 55% (24MB)
137 11:43:40.161273 progress 60% (27MB)
138 11:43:40.337673 progress 65% (29MB)
139 11:43:40.512278 progress 70% (31MB)
140 11:43:40.687078 progress 75% (34MB)
141 11:43:41.012683 progress 80% (36MB)
142 11:43:41.188315 progress 85% (38MB)
143 11:43:41.362157 progress 90% (40MB)
144 11:43:41.537537 progress 95% (43MB)
145 11:43:41.997138 progress 100% (45MB)
146 11:43:41.997496 45MB downloaded in 5.93s (7.65MB/s)
147 11:43:41.997887 end: 1.4.1 http-download (duration 00:00:06) [common]
149 11:43:41.998564 end: 1.4 download-retry (duration 00:00:06) [common]
150 11:43:41.998759 start: 1.5 download-retry (timeout 00:02:27) [common]
151 11:43:41.998926 start: 1.5.1 http-download (timeout 00:02:27) [common]
152 11:43:41.999165 Not decompressing ramdisk as can be used compressed.
153 11:43:41.999336 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/rootfs.cpio.gz
154 11:43:41.999462 saving as /var/lib/lava/dispatcher/tmp/615297/deployimages-0qs6rb_b/ramdisk/rootfs.cpio.gz
155 11:43:41.999581 total size: 88950412 (84MB)
156 11:43:41.999701 No compression specified
157 11:43:42.171189 progress 0% (0MB)
158 11:43:42.683292 progress 5% (4MB)
159 11:43:43.194038 progress 10% (8MB)
160 11:43:43.703661 progress 15% (12MB)
161 11:43:44.211476 progress 20% (16MB)
162 11:43:44.577343 progress 25% (21MB)
163 11:43:45.082272 progress 30% (25MB)
164 11:43:45.586059 progress 35% (29MB)
165 11:43:46.084441 progress 40% (33MB)
166 11:43:46.587621 progress 45% (38MB)
167 11:43:46.949498 progress 50% (42MB)
168 11:43:47.452270 progress 55% (46MB)
169 11:43:47.949218 progress 60% (50MB)
170 11:43:48.310493 progress 65% (55MB)
171 11:43:48.812359 progress 70% (59MB)
172 11:43:49.308290 progress 75% (63MB)
173 11:43:49.674191 progress 80% (67MB)
174 11:43:50.172294 progress 85% (72MB)
175 11:43:50.669821 progress 90% (76MB)
176 11:43:51.033823 progress 95% (80MB)
177 11:43:51.531929 progress 100% (84MB)
178 11:43:51.532333 84MB downloaded in 9.53s (8.90MB/s)
179 11:43:51.532593 end: 1.5.1 http-download (duration 00:00:10) [common]
181 11:43:51.533072 end: 1.5 download-retry (duration 00:00:10) [common]
182 11:43:51.533234 end: 1 deployimages (duration 00:00:42) [common]
183 11:43:51.533393 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 11:43:51.533559 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 11:43:51.533726 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 11:43:51.534071 Extending command line for qcow2 test overlay
187 11:43:51.534676 Pulling docker image
188 11:43:51.534834 cmd: ['docker', 'pull', 'kernelci/qemu']
189 11:43:51.534965 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 11:43:51.694559 >> Using default tag: latest
191 11:43:52.798647 >> latest: Pulling from kernelci/qemu
192 11:43:52.830725 >> Digest: sha256:ce67b4aa6149816ab5c39a34ebc77720cac0c3651072f2c36655342e38024d42
193 11:43:52.830988 >> Status: Image is up to date for kernelci/qemu:latest
194 11:43:52.863951 >> docker.io/kernelci/qemu:latest
195 11:43:52.866641 Returned 0 in 1 seconds
196 11:43:53.004846 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-615297-2.1.1-4f2zuaprig --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/615297/deployimages-0qs6rb_b/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/615297/deployimages-0qs6rb_b/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/615297/apply-overlay-guest-dmvejwwg/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 11:43:53.140576 started a shell command
198 11:43:53.141124 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 11:43:53.141329 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 11:43:53.141515 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 11:43:53.141712 Setting prompt string to ['Linux version [0-9]']
202 11:43:53.141862 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 11:43:57.835714 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 11:43:57.836333 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
205 11:43:57.836548 [ 0.000000] random: crng init done
206 11:43:57.836792 [ 0.000000] Machine model: linux,dummy-virt
207 11:43:57.836963 [ 0.000000] efi: UEFI not found.
208 11:43:57.837102 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
209 11:43:57.837234 [ 0.000000] printk: bootconsole [pl11] enabled
210 11:43:57.837713 start: 2.2.1 login-action (timeout 00:04:54) [common]
211 11:43:57.837886 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
212 11:43:57.838057 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
213 11:43:57.838218 Using line separator: #'\n'#
214 11:43:57.838377 No login prompt set.
215 11:43:57.838589 Parsing kernel messages
216 11:43:57.838773 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
217 11:43:57.839116 [login-action] Waiting for messages, (timeout 00:04:54)
218 11:43:57.840986 [ 0.000000] NUMA: No NUMA configuration found
219 11:43:57.841198 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 11:43:57.841408 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf5a00-0x7fdf7fff]
221 11:43:57.843386 [ 0.000000] Zone ranges:
222 11:43:57.844169 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 11:43:57.844372 [ 0.000000] DMA32 empty
224 11:43:57.844554 [ 0.000000] Normal empty
225 11:43:57.844753 [ 0.000000] Movable zone start for each node
226 11:43:57.844938 [ 0.000000] Early memory node ranges
227 11:43:57.845077 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 11:43:57.845226 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 11:43:57.859673 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 11:43:57.860742 [ 0.000000] psci: probing for conduit method from DT.
231 11:43:57.860981 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 11:43:57.861155 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 11:43:57.861341 [ 0.000000] psci: Trusted OS migration not required
234 11:43:57.861495 [ 0.000000] psci: SMC Calling Convention v1.0
235 11:43:57.863845 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
236 11:43:57.864467 [ 0.000000] pcpu-alloc: s45224 r8192 d32600 u86016 alloc=21*4096
237 11:43:57.864635 [ 0.000000] pcpu-alloc: [0] 0
238 11:43:57.866097 [ 0.000000] Detected PIPT I-cache on CPU0
239 11:43:57.871365 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 11:43:57.872090 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 11:43:57.872406 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 11:43:57.872601 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 11:43:57.872756 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 11:43:57.873115 [ 0.000000] CPU features: detected: Spectre-v4
245 11:43:57.876802 [ 0.000000] alternatives: applying boot alternatives
246 11:43:57.879723 [ 0.000000] Fallback order for Node 0: 0
247 11:43:57.879875 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 11:43:57.880000 [ 0.000000] Policy zone: DMA
249 11:43:57.880572 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 11:43:57.882938 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 11:43:57.885747 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 11:43:57.886171 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 11:43:57.886574 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 11:43:57.896230 <6>[ 0.000000] Memory: 860720K/1048576K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 155088K reserved, 32768K cma-reserved)
255 11:43:57.902188 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 11:43:57.908933 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 11:43:57.909125 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 11:43:57.909314 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 11:43:57.909474 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 11:43:57.909633 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 11:43:57.909830 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 11:43:57.909997 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 11:43:57.911016 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 11:43:57.917900 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 11:43:57.918124 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 11:43:57.919457 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 11:43:57.919869 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 11:43:57.920548 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 11:43:57.925202 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 11:43:57.926046 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @43030000 (indirect, esz 8, psz 64K, shr 1)
271 11:43:57.926564 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @43040000 (flat, esz 8, psz 64K, shr 1)
272 11:43:57.927065 <6>[ 0.000000] GICv3: using LPI property table @0x0000000043050000
273 11:43:57.927973 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000043060000
274 11:43:57.929215 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 11:43:57.938093 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 11:43:57.938694 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 11:43:57.939398 <6>[ 0.000081] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 11:43:57.958272 <6>[ 0.016354] Console: colour dummy device 80x25
279 11:43:57.962119 <6>[ 0.022375] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 11:43:57.962725 <6>[ 0.023527] pid_max: default: 32768 minimum: 301
281 11:43:57.963877 <6>[ 0.024746] LSM: Security Framework initializing
282 11:43:57.968197 <6>[ 0.028934] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 11:43:57.968307 <6>[ 0.029159] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 11:43:57.999991 <4>[ 0.060900] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 11:43:58.005963 <6>[ 0.066754] cblist_init_generic: Setting adjustable number of callback queues.
286 11:43:58.006346 <6>[ 0.067094] cblist_init_generic: Setting shift to 0 and lim to 1.
287 11:43:58.006964 <6>[ 0.067774] cblist_init_generic: Setting shift to 0 and lim to 1.
288 11:43:58.008723 <6>[ 0.069541] rcu: Hierarchical SRCU implementation.
289 11:43:58.008849 <6>[ 0.069796] rcu: Max phase no-delay instances is 1000.
290 11:43:58.013731 <6>[ 0.074691] Platform MSI: its@8080000 domain created
291 11:43:58.014744 <6>[ 0.075366] PCI/MSI: /intc@8000000/its@8080000 domain created
292 11:43:58.014958 <6>[ 0.075945] fsl-mc MSI: its@8080000 domain created
293 11:43:58.018566 <6>[ 0.079429] EFI services will not be available.
294 11:43:58.019326 <6>[ 0.080313] smp: Bringing up secondary CPUs ...
295 11:43:58.019921 <6>[ 0.080536] smp: Brought up 1 node, 1 CPU
296 11:43:58.020096 <6>[ 0.080684] SMP: Total of 1 processors activated.
297 11:43:58.020289 <6>[ 0.081009] CPU features: detected: Branch Target Identification
298 11:43:58.020460 <6>[ 0.081235] CPU features: detected: 32-bit EL0 Support
299 11:43:58.020647 <6>[ 0.081415] CPU features: detected: 32-bit EL1 Support
300 11:43:58.020817 <6>[ 0.081592] CPU features: detected: ARMv8.4 Translation Table Level
301 11:43:58.020981 <6>[ 0.081796] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 11:43:58.021734 <6>[ 0.082483] CPU features: detected: Common not Private translations
303 11:43:58.021954 <6>[ 0.082650] CPU features: detected: CRC32 instructions
304 11:43:58.022179 <6>[ 0.082810] CPU features: detected: E0PD
305 11:43:58.022344 <6>[ 0.083023] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 11:43:58.022556 <6>[ 0.083227] CPU features: detected: RCpc load-acquire (LDAPR)
307 11:43:58.022724 <6>[ 0.083387] CPU features: detected: LSE atomic instructions
308 11:43:58.022910 <6>[ 0.083535] CPU features: detected: Privileged Access Never
309 11:43:58.023082 <6>[ 0.083695] CPU features: detected: RAS Extension Support
310 11:43:58.023266 <6>[ 0.083868] CPU features: detected: Random Number Generator
311 11:43:58.023472 <6>[ 0.084028] CPU features: detected: Speculation barrier (SB)
312 11:43:58.023646 <6>[ 0.084171] CPU features: detected: Stage-2 Force Write-Back
313 11:43:58.023809 <6>[ 0.084313] CPU features: detected: TLB range maintenance instructions
314 11:43:58.023981 <6>[ 0.084459] CPU features: detected: Scalable Matrix Extension
315 11:43:58.024118 <6>[ 0.084605] CPU features: detected: FA64
316 11:43:58.024239 <6>[ 0.084716] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 11:43:58.024360 <6>[ 0.084875] CPU features: detected: Scalable Vector Extension
318 11:43:58.036185 <6>[ 0.094440] SVE: maximum available vector length 256 bytes per vector
319 11:43:58.036641 <6>[ 0.097544] SVE: default vector length 64 bytes per vector
320 11:43:58.038824 <6>[ 0.099542] SME: minimum available vector length 16 bytes per vector
321 11:43:58.039005 <6>[ 0.099766] SME: maximum available vector length 256 bytes per vector
322 11:43:58.039216 <6>[ 0.099975] SME: default vector length 32 bytes per vector
323 11:43:58.039390 <6>[ 0.100414] CPU: All CPU(s) started at EL1
324 11:43:58.039844 <6>[ 0.100780] alternatives: applying system-wide alternatives
325 11:43:58.092416 <6>[ 0.153194] devtmpfs: initialized
326 11:43:58.112289 <6>[ 0.172803] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 11:43:58.112899 <6>[ 0.173638] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 11:43:58.118761 <6>[ 0.179469] pinctrl core: initialized pinctrl subsystem
329 11:43:58.129524 <6>[ 0.190541] DMI not present or invalid.
330 11:43:58.138811 <6>[ 0.199643] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 11:43:58.150531 <6>[ 0.211258] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 11:43:58.151384 <6>[ 0.212119] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 11:43:58.151840 <6>[ 0.212590] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 11:43:58.152287 <6>[ 0.213052] audit: initializing netlink subsys (disabled)
335 11:43:58.159856 <6>[ 0.220017] thermal_sys: Registered thermal governor 'step_wise'
336 11:43:58.160090 <5>[ 0.220517] audit: type=2000 audit(0.176:1): state=initialized audit_enabled=0 res=1
337 11:43:58.160908 <6>[ 0.221224] thermal_sys: Registered thermal governor 'power_allocator'
338 11:43:58.161070 <6>[ 0.221645] cpuidle: using governor menu
339 11:43:58.161831 <6>[ 0.222577] NET: Registered PF_QIPCRTR protocol family
340 11:43:58.164892 <6>[ 0.225554] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
341 11:43:58.165222 <6>[ 0.226177] ASID allocator initialised with 65536 entries
342 11:43:58.171607 <6>[ 0.232581] Serial: AMBA PL011 UART driver
343 11:43:58.221517 <6>[ 0.282239] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
344 11:43:58.223336 <6>[ 0.283966] printk: console [ttyAMA0] enabled
345 11:43:58.223534 <6>[ 0.283966] printk: console [ttyAMA0] enabled
346 11:43:58.223697 <6>[ 0.284441] printk: bootconsole [pl11] disabled
347 11:43:58.223824 <6>[ 0.284441] printk: bootconsole [pl11] disabled
348 11:43:58.234357 <6>[ 0.295325] KASLR enabled
349 11:43:58.271376 <6>[ 0.331932] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
350 11:43:58.271679 <6>[ 0.332126] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
351 11:43:58.271857 <6>[ 0.332302] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
352 11:43:58.272122 <6>[ 0.332453] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
353 11:43:58.272285 <6>[ 0.332626] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
354 11:43:58.272412 <6>[ 0.332783] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
355 11:43:58.272533 <6>[ 0.332980] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
356 11:43:58.272683 <6>[ 0.333138] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
357 11:43:58.281995 <6>[ 0.342957] ACPI: Interpreter disabled.
358 11:43:58.290406 <6>[ 0.351379] iommu: Default domain type: Translated
359 11:43:58.290881 <6>[ 0.351543] iommu: DMA domain TLB invalidation policy: strict mode
360 11:43:58.292304 <5>[ 0.353298] SCSI subsystem initialized
361 11:43:58.293413 <7>[ 0.354189] libata version 3.00 loaded.
362 11:43:58.294982 <6>[ 0.355763] usbcore: registered new interface driver usbfs
363 11:43:58.295334 <6>[ 0.356197] usbcore: registered new interface driver hub
364 11:43:58.295686 <6>[ 0.356553] usbcore: registered new device driver usb
365 11:43:58.299225 <6>[ 0.360203] pps_core: LinuxPPS API ver. 1 registered
366 11:43:58.299782 <6>[ 0.360357] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
367 11:43:58.299955 <6>[ 0.360722] PTP clock support registered
368 11:43:58.300651 <6>[ 0.361411] EDAC MC: Ver: 3.0.0
369 11:43:58.306821 <6>[ 0.367801] FPGA manager framework
370 11:43:58.307842 <6>[ 0.368602] Advanced Linux Sound Architecture Driver Initialized.
371 11:43:58.316884 <6>[ 0.377831] vgaarb: loaded
372 11:43:58.321093 <6>[ 0.381771] clocksource: Switched to clocksource arch_sys_counter
373 11:43:58.322293 <5>[ 0.383041] VFS: Disk quotas dquot_6.6.0
374 11:43:58.322481 <6>[ 0.383327] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
375 11:43:58.325758 <6>[ 0.386757] pnp: PnP ACPI: disabled
376 11:43:58.344105 <6>[ 0.405042] NET: Registered PF_INET protocol family
377 11:43:58.346697 <6>[ 0.407359] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
378 11:43:58.351383 <6>[ 0.412101] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
379 11:43:58.351564 <6>[ 0.412384] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
380 11:43:58.351879 <6>[ 0.412629] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
381 11:43:58.352197 <6>[ 0.412997] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
382 11:43:58.352740 <6>[ 0.413585] TCP: Hash tables configured (established 8192 bind 8192)
383 11:43:58.354108 <6>[ 0.414778] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
384 11:43:58.354328 <6>[ 0.415164] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
385 11:43:58.355507 <6>[ 0.416300] NET: Registered PF_UNIX/PF_LOCAL protocol family
386 11:43:58.358329 <6>[ 0.419098] RPC: Registered named UNIX socket transport module.
387 11:43:58.358460 <6>[ 0.419281] RPC: Registered udp transport module.
388 11:43:58.358614 <6>[ 0.419398] RPC: Registered tcp transport module.
389 11:43:58.358740 <6>[ 0.419508] RPC: Registered tcp NFSv4.1 backchannel transport module.
390 11:43:58.358864 <6>[ 0.419722] PCI: CLS 0 bytes, default 64
391 11:43:58.362650 <6>[ 0.423691] Unpacking initramfs...
392 11:43:58.373014 <6>[ 0.433938] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
393 11:43:58.373893 <6>[ 0.434663] kvm [1]: HYP mode not available
394 11:43:58.378713 <5>[ 0.439677] Initialise system trusted keyrings
395 11:43:58.385463 <6>[ 0.446379] workingset: timestamp_bits=42 max_order=18 bucket_order=0
396 11:43:58.424965 <6>[ 0.485812] squashfs: version 4.0 (2009/01/31) Phillip Lougher
397 11:43:58.430248 <5>[ 0.490959] NFS: Registering the id_resolver key type
398 11:43:58.430491 <5>[ 0.491374] Key type id_resolver registered
399 11:43:58.430687 <5>[ 0.491517] Key type id_legacy registered
400 11:43:58.431327 <6>[ 0.492005] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
401 11:43:58.431454 <6>[ 0.492287] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
402 11:43:58.432316 <6>[ 0.493115] 9p: Installing v9fs 9p2000 file system support
403 11:43:58.497095 <5>[ 0.557915] Key type asymmetric registered
404 11:43:58.497604 <5>[ 0.558172] Asymmetric key parser 'x509' registered
405 11:43:58.497968 <6>[ 0.558742] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
406 11:43:58.498094 <6>[ 0.559099] io scheduler mq-deadline registered
407 11:43:58.498411 <6>[ 0.559277] io scheduler kyber registered
408 11:43:58.573371 <6>[ 0.634103] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
409 11:43:58.584807 <6>[ 0.645311] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
410 11:43:58.589745 <6>[ 0.650299] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
411 11:43:58.590093 <6>[ 0.651017] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
412 11:43:58.590484 <6>[ 0.651333] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
413 11:43:58.591305 <4>[ 0.652106] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
414 11:43:58.592485 <6>[ 0.652903] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
415 11:43:58.597800 <6>[ 0.658536] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
416 11:43:58.598051 <6>[ 0.658975] pci_bus 0000:00: root bus resource [bus 00-ff]
417 11:43:58.598905 <6>[ 0.659213] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
418 11:43:58.599071 <6>[ 0.659482] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
419 11:43:58.599211 <6>[ 0.659673] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
420 11:43:58.600472 <6>[ 0.661204] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
421 11:43:58.608219 <6>[ 0.668913] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
422 11:43:58.608437 <6>[ 0.669346] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
423 11:43:58.612844 <6>[ 0.673605] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
424 11:43:58.613013 <6>[ 0.673826] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
425 11:43:58.613138 <6>[ 0.674089] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
426 11:43:58.613940 <6>[ 0.674747] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
427 11:43:58.614050 <6>[ 0.674991] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
428 11:43:58.614361 <6>[ 0.675180] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
429 11:43:58.614512 <6>[ 0.675407] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
430 11:43:58.621827 <6>[ 0.682553] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
431 11:43:58.622199 <6>[ 0.683044] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
432 11:43:58.622618 <6>[ 0.683351] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
433 11:43:58.622826 <6>[ 0.683576] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
434 11:43:58.623040 <6>[ 0.683808] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
435 11:43:58.623218 <6>[ 0.684027] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
436 11:43:58.623376 <6>[ 0.684214] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
437 11:43:58.641922 <6>[ 0.702776] EINJ: ACPI disabled.
438 11:43:58.734712 <6>[ 0.795534] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
439 11:43:58.741663 <6>[ 0.802541] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
440 11:43:58.777266 <6>[ 0.838082] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
441 11:43:58.793881 <6>[ 0.854765] SuperH (H)SCI(F) driver initialized
442 11:43:58.795249 <6>[ 0.856232] msm_serial: driver initialized
443 11:43:58.828909 <4>[ 0.889771] cacheinfo: Unable to detect cache hierarchy for CPU 0
444 11:43:58.864742 <6>[ 0.925630] loop: module loaded
445 11:43:58.865471 <6>[ 0.926448] virtio_blk virtio1: 1/0/0 default/read/poll queues
446 11:43:58.882070 <5>[ 0.942953] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
447 11:43:58.908376 <6>[ 0.969238] megasas: 07.719.03.00-rc1
448 11:43:58.930066 <5>[ 0.990874] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
449 11:43:58.931978 <6>[ 0.992473] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
450 11:43:58.932274 <6>[ 0.993202] Intel/Sharp Extended Query Table at 0x0031
451 11:43:58.936954 <6>[ 0.997888] Using buffer write method
452 11:43:58.937482 <7>[ 0.998315] erase region 0: offset=0x0,size=0x40000,blocks=256
453 11:43:58.938025 <5>[ 0.998689] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
454 11:43:58.938649 <6>[ 0.999346] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
455 11:43:58.938761 <6>[ 0.999648] Intel/Sharp Extended Query Table at 0x0031
456 11:43:58.939364 <6>[ 1.000184] Using buffer write method
457 11:43:58.939464 <7>[ 1.000317] erase region 0: offset=0x0,size=0x40000,blocks=256
458 11:43:58.939566 <5>[ 1.000542] Concatenating MTD devices:
459 11:43:58.939669 <5>[ 1.000676] (0): \"0.flash\"
460 11:43:58.939772 <5>[ 1.000768] (1): \"0.flash\"
461 11:43:58.939874 <5>[ 1.000847] into device \"0.flash\"
462 11:44:03.573929 <6>[ 5.634705] Freeing initrd memory: 86864K
463 11:44:03.694440 <6>[ 5.755250] tun: Universal TUN/TAP device driver, 1.6
464 11:44:03.704171 <6>[ 5.765071] thunder_xcv, ver 1.0
465 11:44:03.704697 <6>[ 5.765304] thunder_bgx, ver 1.0
466 11:44:03.704873 <6>[ 5.765637] nicpf, ver 1.0
467 11:44:03.708362 <6>[ 5.768994] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
468 11:44:03.708631 <6>[ 5.769200] hns3: Copyright (c) 2017 Huawei Corporation.
469 11:44:03.708815 <6>[ 5.769695] hclge is initializing
470 11:44:03.709238 <6>[ 5.769912] e1000: Intel(R) PRO/1000 Network Driver
471 11:44:03.709376 <6>[ 5.770060] e1000: Copyright (c) 1999-2006 Intel Corporation.
472 11:44:03.709520 <6>[ 5.770332] e1000e: Intel(R) PRO/1000 Network Driver
473 11:44:03.709661 <6>[ 5.770456] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
474 11:44:03.709884 <6>[ 5.770712] igb: Intel(R) Gigabit Ethernet Network Driver
475 11:44:03.710044 <6>[ 5.770862] igb: Copyright (c) 2007-2014 Intel Corporation.
476 11:44:03.710222 <6>[ 5.771110] igbvf: Intel(R) Gigabit Virtual Function Network Driver
477 11:44:03.710385 <6>[ 5.771288] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
478 11:44:03.711263 <6>[ 5.772281] sky2: driver version 1.30
479 11:44:03.715048 <6>[ 5.775813] VFIO - User Level meta-driver version: 0.3
480 11:44:03.724524 <6>[ 5.785210] usbcore: registered new interface driver usb-storage
481 11:44:03.725221 <6>[ 5.786031] usbcore: registered new device driver onboard-usb-hub
482 11:44:03.734742 <6>[ 5.795462] rtc-pl031 9010000.pl031: registered as rtc0
483 11:44:03.735825 <6>[ 5.796270] rtc-pl031 9010000.pl031: setting system clock to 2023-06-15T11:44:03 UTC (1686829443)
484 11:44:03.737760 <6>[ 5.798779] i2c_dev: i2c /dev entries driver
485 11:44:03.756350 <6>[ 5.817278] sdhci: Secure Digital Host Controller Interface driver
486 11:44:03.756948 <6>[ 5.817459] sdhci: Copyright(c) Pierre Ossman
487 11:44:03.758803 <6>[ 5.819555] Synopsys Designware Multimedia Card Interface Driver
488 11:44:03.761439 <6>[ 5.822221] sdhci-pltfm: SDHCI platform and OF driver helper
489 11:44:03.767122 <6>[ 5.827911] ledtrig-cpu: registered to indicate activity on CPUs
490 11:44:03.773153 <6>[ 5.833946] usbcore: registered new interface driver usbhid
491 11:44:03.773264 <6>[ 5.834127] usbhid: USB HID core driver
492 11:44:03.798606 <6>[ 5.859334] NET: Registered PF_PACKET protocol family
493 11:44:03.799598 <6>[ 5.860419] 9pnet: Installing 9P2000 support
494 11:44:03.799939 <5>[ 5.860767] Key type dns_resolver registered
495 11:44:03.801403 <6>[ 5.862162] registered taskstats version 1
496 11:44:03.801676 <5>[ 5.862540] Loading compiled-in X.509 certificates
497 11:44:03.823242 <6>[ 5.884074] input: gpio-keys as /devices/platform/gpio-keys/input/input0
498 11:44:03.830317 <6>[ 5.891281] ALSA device list:
499 11:44:03.830653 <6>[ 5.891489] No soundcards found.
500 11:44:03.833582 <6>[ 5.894277] uart-pl011 9000000.pl011: no DMA platform data
501 11:44:03.891405 <6>[ 5.952159] Freeing unused kernel memory: 8384K
502 11:44:03.892231 <6>[ 5.953251] Run /init as init process
503 11:44:03.892571 <7>[ 5.953371] with arguments:
504 11:44:03.892691 <7>[ 5.953613] /init
505 11:44:03.892787 <7>[ 5.953680] verbose
506 11:44:03.892894 <7>[ 5.953797] with environment:
507 11:44:03.892999 <7>[ 5.953944] HOME=/
508 11:44:03.893102 <7>[ 5.954051] TERM=linux
509 11:44:04.022107 <30>[ 6.082593] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
510 11:44:04.023106 <31>[ 6.083845] systemd[1]: No virtualization found in DMI
511 11:44:04.024064 <31>[ 6.084787] systemd[1]: UML virtualization not found in /proc/cpuinfo.
512 11:44:04.024304 <31>[ 6.085100] systemd[1]: No virtualization found in CPUID
513 11:44:04.024544 <31>[ 6.085370] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
514 11:44:04.026122 <31>[ 6.086807] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
515 11:44:04.026326 <31>[ 6.087273] systemd[1]: Found VM virtualization qemu
516 11:44:04.026782 <30>[ 6.087511] systemd[1]: Detected virtualization qemu.
517 11:44:04.026944 <30>[ 6.087858] systemd[1]: Detected architecture arm64.
518 11:44:04.027367 <31>[ 6.088203] systemd[1]: Detected initialized system, this is not the first boot.
519 11:44:04.031264
520 11:44:04.031713 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
521 11:44:04.031862
522 11:44:04.033682 <30>[ 6.094412] systemd[1]: Set hostname to <debian-bullseye-arm64>.
523 11:44:04.052143 <31>[ 6.112782] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
524 11:44:04.053445 <31>[ 6.114174] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
525 11:44:04.053954 <31>[ 6.114676] systemd[1]: Successfully brought loopback interface up
526 11:44:04.058469 <31>[ 6.119187] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
527 11:44:04.070330 <31>[ 6.130977] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
528 11:44:04.070537 <31>[ 6.131289] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
529 11:44:04.111704 <31>[ 6.172530] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
530 11:44:04.113399 <31>[ 6.174121] systemd[1]: Controller 'cpu' supported: yes
531 11:44:04.113515 <31>[ 6.174335] systemd[1]: Controller 'cpuacct' supported: no
532 11:44:04.113625 <31>[ 6.174541] systemd[1]: Controller 'cpuset' supported: yes
533 11:44:04.113972 <31>[ 6.174736] systemd[1]: Controller 'io' supported: yes
534 11:44:04.114082 <31>[ 6.174923] systemd[1]: Controller 'blkio' supported: no
535 11:44:04.114188 <31>[ 6.175125] systemd[1]: Controller 'memory' supported: yes
536 11:44:04.114590 <31>[ 6.175354] systemd[1]: Controller 'devices' supported: no
537 11:44:04.114800 <31>[ 6.175553] systemd[1]: Controller 'pids' supported: yes
538 11:44:04.114984 <31>[ 6.175721] systemd[1]: Controller 'bpf-firewall' supported: yes
539 11:44:04.115121 <31>[ 6.175919] systemd[1]: Controller 'bpf-devices' supported: yes
540 11:44:04.116279 <31>[ 6.177048] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
541 11:44:04.117124 <31>[ 6.177761] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
542 11:44:04.117595 <31>[ 6.178443] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
543 11:44:04.124595 <31>[ 6.185329] systemd[1]: Enabling (yes) showing of status (commandline).
544 11:44:04.132625 <31>[ 6.193270] systemd[1]: Successfully forked off '(sd-executor)' as PID 98.
545 11:44:04.141611 <31>[ 6.202536] systemd[98]: Successfully forked off '(direxec)' as PID 99.
546 11:44:04.144393 <31>[ 6.205137] systemd[98]: Successfully forked off '(direxec)' as PID 100.
547 11:44:04.150618 <31>[ 6.211294] systemd[98]: Successfully forked off '(direxec)' as PID 101.
548 11:44:04.153120 <31>[ 6.213272] systemd[98]: Successfully forked off '(direxec)' as PID 102.
549 11:44:04.166811 <31>[ 6.227490] systemd[98]: Successfully forked off '(direxec)' as PID 103.
550 11:44:04.320799 <31>[ 6.381663] systemd-bless-boot-generator[99]: Skipping generator, not an EFI boot.
551 11:44:04.326247 <31>[ 6.386892] systemd-fstab-generator[100]: Parsing /etc/fstab...
552 11:44:04.328278 <31>[ 6.388972] systemd-fstab-generator[100]: Found entry what=/dev/disk/by-uuid/e8944c3c-78ff-4c74-a97d-ff60ed2bed2f where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
553 11:44:04.329126 <31>[ 6.389924] systemd-getty-generator[101]: Automatically adding serial getty for /dev/ttyAMA0.
554 11:44:04.330476 <31>[ 6.391270] systemd-getty-generator[101]: SELinux enabled state cached to: disabled
555 11:44:04.346017 <31>[ 6.406650] systemd[98]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
556 11:44:04.349981 <31>[ 6.409441] systemd-fstab-generator[100]: Checking was requested for /dev/disk/by-uuid/e8944c3c-78ff-4c74-a97d-ff60ed2bed2f, but fsck.ext4 does not exist.
557 11:44:04.353495 <31>[ 6.414238] systemd[98]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
558 11:44:04.354026 <31>[ 6.414662] systemd[98]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
559 11:44:04.354768 <31>[ 6.415560] systemd-fstab-generator[100]: SELinux enabled state cached to: disabled
560 11:44:04.360068 <31>[ 6.420872] systemd[98]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
561 11:44:04.360664 <31>[ 6.421303] systemd[98]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
562 11:44:04.363675 <31>[ 6.424522] systemd[1]: (sd-executor) succeeded.
563 11:44:04.365925 <31>[ 6.426627] systemd[1]: Looking for unit files in (higher priority first):
564 11:44:04.366077 <31>[ 6.426821] systemd[1]: /etc/systemd/system.control
565 11:44:04.366194 <31>[ 6.426972] systemd[1]: /run/systemd/system.control
566 11:44:04.366310 <31>[ 6.427167] systemd[1]: /run/systemd/transient
567 11:44:04.366415 <31>[ 6.427363] systemd[1]: /run/systemd/generator.early
568 11:44:04.366806 <31>[ 6.427589] systemd[1]: /etc/systemd/system
569 11:44:04.366998 <31>[ 6.427759] systemd[1]: /etc/systemd/system.attached
570 11:44:04.367257 <31>[ 6.427912] systemd[1]: /run/systemd/system
571 11:44:04.367443 <31>[ 6.428035] systemd[1]: /run/systemd/system.attached
572 11:44:04.367601 <31>[ 6.428176] systemd[1]: /run/systemd/generator
573 11:44:04.367789 <31>[ 6.428345] systemd[1]: /usr/local/lib/systemd/system
574 11:44:04.367920 <31>[ 6.428497] systemd[1]: /lib/systemd/system
575 11:44:04.368042 <31>[ 6.428672] systemd[1]: /usr/lib/systemd/system
576 11:44:04.368182 <31>[ 6.428817] systemd[1]: /run/systemd/generator.late
577 11:44:04.403707 <31>[ 6.464301] systemd[1]: Modification times have changed, need to update cache.
578 11:44:04.405624 <31>[ 6.466339] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
579 11:44:04.406409 <31>[ 6.467117] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
580 11:44:04.407217 <31>[ 6.467783] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
581 11:44:04.408048 <31>[ 6.468693] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
582 11:44:04.409496 <31>[ 6.470235] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/autovt@.service → getty@.service
583 11:44:04.409873 <31>[ 6.470538] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
584 11:44:04.410242 <31>[ 6.470899] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub@.service
585 11:44:04.410643 <31>[ 6.471260] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
586 11:44:04.410797 <31>[ 6.471608] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
587 11:44:04.411217 <31>[ 6.471997] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
588 11:44:04.411660 <31>[ 6.472356] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
589 11:44:04.411883 <31>[ 6.472721] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
590 11:44:04.412627 <31>[ 6.473393] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
591 11:44:04.413809 <31>[ 6.474201] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
592 11:44:04.413989 <31>[ 6.474514] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
593 11:44:04.414497 <31>[ 6.474771] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sysinit.target
594 11:44:04.414697 <31>[ 6.475063] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
595 11:44:04.414861 <31>[ 6.475379] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
596 11:44:04.415421 <31>[ 6.476049] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
597 11:44:04.416034 <31>[ 6.476709] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
598 11:44:04.416261 <31>[ 6.477070] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/swap.target
599 11:44:04.416838 <31>[ 6.477392] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
600 11:44:04.417067 <31>[ 6.477733] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
601 11:44:04.417901 <31>[ 6.478441] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
602 11:44:04.418132 <31>[ 6.478854] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
603 11:44:04.418690 <31>[ 6.479240] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
604 11:44:04.419270 <31>[ 6.479836] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
605 11:44:04.419528 <31>[ 6.480182] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
606 11:44:04.419797 <31>[ 6.480484] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
607 11:44:04.420065 <31>[ 6.480813] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
608 11:44:04.420285 <31>[ 6.481137] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
609 11:44:04.420820 <31>[ 6.481430] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
610 11:44:04.421319 <31>[ 6.482080] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
611 11:44:04.422185 <31>[ 6.482794] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel6.target → reboot.target
612 11:44:04.423097 <31>[ 6.483599] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/ctrl-alt-del.target → reboot.target
613 11:44:04.423331 <31>[ 6.483948] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
614 11:44:04.423542 <31>[ 6.484349] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
615 11:44:04.424077 <31>[ 6.484708] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rc-local.service
616 11:44:04.424320 <31>[ 6.485022] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
617 11:44:04.424570 <31>[ 6.485386] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
618 11:44:04.425117 <31>[ 6.486011] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
619 11:44:04.425637 <31>[ 6.486290] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
620 11:44:04.425855 <31>[ 6.486558] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
621 11:44:04.426111 <31>[ 6.486806] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
622 11:44:04.426370 <31>[ 6.487122] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
623 11:44:04.426647 <31>[ 6.487442] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.mount
624 11:44:04.426862 <31>[ 6.487782] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs.target
625 11:44:04.427350 <31>[ 6.488036] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hostnamed.service
626 11:44:04.427588 <31>[ 6.488330] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-remount-fs.service
627 11:44:04.427823 <31>[ 6.488737] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/final.target
628 11:44:04.428387 <31>[ 6.489017] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
629 11:44:04.428585 <31>[ 6.489297] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.service
630 11:44:04.429031 <31>[ 6.489871] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
631 11:44:04.429845 <31>[ 6.490634] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
632 11:44:04.430059 <31>[ 6.490979] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
633 11:44:04.430586 <31>[ 6.491378] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
634 11:44:04.431130 <31>[ 6.491740] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
635 11:44:04.431324 <31>[ 6.492036] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs.target
636 11:44:04.431542 <31>[ 6.492306] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
637 11:44:04.431746 <31>[ 6.492654] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
638 11:44:04.432197 <31>[ 6.492929] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
639 11:44:04.433036 <31>[ 6.493805] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel0.target → poweroff.target
640 11:44:04.433246 <31>[ 6.494125] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
641 11:44:04.433725 <31>[ 6.494407] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/debug-shell.service
642 11:44:04.433903 <31>[ 6.494714] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
643 11:44:04.434389 <31>[ 6.495011] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
644 11:44:04.434851 <31>[ 6.495656] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
645 11:44:04.435043 <31>[ 6.495945] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
646 11:44:04.435254 <31>[ 6.496207] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
647 11:44:04.435761 <31>[ 6.496451] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
648 11:44:04.435969 <31>[ 6.496739] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
649 11:44:04.436213 <31>[ 6.497013] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
650 11:44:04.436761 <31>[ 6.497381] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
651 11:44:04.437252 <31>[ 6.498010] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
652 11:44:04.437517 <31>[ 6.498353] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
653 11:44:04.438088 <31>[ 6.498721] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
654 11:44:04.438622 <31>[ 6.499314] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
655 11:44:04.438866 <31>[ 6.499690] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
656 11:44:04.439151 <31>[ 6.500011] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_fail@.service
657 11:44:04.439987 <31>[ 6.500689] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
658 11:44:04.440680 <31>[ 6.501214] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
659 11:44:04.441578 <31>[ 6.502306] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
660 11:44:04.442100 <31>[ 6.502704] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-localed.service
661 11:44:04.442593 <31>[ 6.503442] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
662 11:44:04.442900 <31>[ 6.503746] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
663 11:44:04.443476 <31>[ 6.504046] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.path
664 11:44:04.443682 <31>[ 6.504397] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.service
665 11:44:04.443891 <31>[ 6.504702] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/shutdown.target
666 11:44:04.444137 <31>[ 6.504978] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
667 11:44:04.444701 <31>[ 6.505317] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-check-no-failures.service
668 11:44:04.445241 <31>[ 6.506002] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
669 11:44:04.445824 <31>[ 6.506375] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
670 11:44:04.446023 <31>[ 6.506681] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
671 11:44:04.446207 <31>[ 6.506988] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
672 11:44:04.446788 <31>[ 6.507314] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
673 11:44:04.446981 <31>[ 6.507661] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-exit.service
674 11:44:04.447212 <31>[ 6.507954] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsckd.service
675 11:44:04.447787 <31>[ 6.508402] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
676 11:44:04.447997 <31>[ 6.508749] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
677 11:44:04.448190 <31>[ 6.509064] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
678 11:44:04.448714 <31>[ 6.509352] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
679 11:44:04.449322 <31>[ 6.509948] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
680 11:44:04.449536 <31>[ 6.510273] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
681 11:44:04.449762 <31>[ 6.510613] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
682 11:44:04.450558 <31>[ 6.511199] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
683 11:44:04.450788 <31>[ 6.511558] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.service
684 11:44:04.451218 <31>[ 6.512047] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
685 11:44:04.451600 <31>[ 6.512352] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
686 11:44:04.451932 <31>[ 6.512715] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-sync.target
687 11:44:04.452392 <31>[ 6.513087] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-user-lookup.target
688 11:44:04.452636 <31>[ 6.513442] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
689 11:44:04.453165 <31>[ 6.514051] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
690 11:44:04.453711 <31>[ 6.514339] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.socket
691 11:44:04.453959 <31>[ 6.514618] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
692 11:44:04.454180 <31>[ 6.514913] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
693 11:44:04.454413 <31>[ 6.515282] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
694 11:44:04.455035 <31>[ 6.515593] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
695 11:44:04.455291 <31>[ 6.515932] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/first-boot-complete.target
696 11:44:04.455481 <31>[ 6.516260] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
697 11:44:04.456032 <31>[ 6.516600] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
698 11:44:04.456232 <31>[ 6.516925] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
699 11:44:04.456403 <31>[ 6.517199] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
700 11:44:04.456876 <31>[ 6.517617] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
701 11:44:04.457711 <31>[ 6.518293] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
702 11:44:04.457936 <31>[ 6.518634] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
703 11:44:04.458128 <31>[ 6.518922] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-mqueue.mount
704 11:44:04.458334 <31>[ 6.519202] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
705 11:44:04.458849 <31>[ 6.519464] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
706 11:44:04.459068 <31>[ 6.519772] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
707 11:44:04.459251 <31>[ 6.520052] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-config.mount
708 11:44:04.459744 <31>[ 6.520356] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
709 11:44:04.459892 <31>[ 6.520663] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
710 11:44:04.460031 <31>[ 6.520944] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
711 11:44:04.460461 <31>[ 6.521207] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/container-getty@.service
712 11:44:04.461131 <31>[ 6.521778] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
713 11:44:04.461257 <31>[ 6.522105] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
714 11:44:04.461687 <31>[ 6.522451] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-trigger.service
715 11:44:04.462219 <31>[ 6.522801] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
716 11:44:04.462404 <31>[ 6.523086] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
717 11:44:04.462568 <31>[ 6.523361] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
718 11:44:04.463287 <31>[ 6.524028] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
719 11:44:04.463733 <31>[ 6.524358] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
720 11:44:04.463899 <31>[ 6.524672] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
721 11:44:04.464426 <31>[ 6.524968] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
722 11:44:04.464852 <31>[ 6.525296] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
723 11:44:04.465256 <31>[ 6.526030] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/smartcard.target
724 11:44:04.465590 <31>[ 6.526319] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
725 11:44:04.465925 <31>[ 6.526617] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
726 11:44:04.466020 <31>[ 6.526902] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
727 11:44:04.466351 <31>[ 6.527191] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
728 11:44:04.466688 <31>[ 6.527501] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
729 11:44:04.877066 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
730 11:44:04.881476 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
731 11:44:04.884828 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
732 11:44:04.888250 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
733 11:44:04.891775 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
734 11:44:04.893446 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
735 11:44:04.895666 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
736 11:44:04.896554 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
737 11:44:04.897554 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
738 11:44:04.898061 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
739 11:44:04.898770 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
740 11:44:04.902610 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
741 11:44:04.906582 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
742 11:44:04.909160 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
743 11:44:04.911205 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
744 11:44:04.913802 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
745 11:44:04.916044 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
746 11:44:04.918263 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
747 11:44:04.946513 Mounting [0;1;39mHuge Pages File System[0m...
748 11:44:04.965756 Mounting [0;1;39mPOSIX Message Queue File System[0m...
749 11:44:05.002263 Mounting [0;1;39mKernel Debug File System[0m...
750 11:44:05.066801 Starting [0;1;39mLoad Kernel Module configfs[0m...
751 11:44:05.098213 Starting [0;1;39mLoad Kernel Module drm[0m...
752 11:44:05.158377 Starting [0;1;39mJournal Service[0m...
753 11:44:05.190664 Starting [0;1;39mLoad Kernel Modules[0m...
754 11:44:05.226983 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
755 11:44:05.290021 Starting [0;1;39mColdplug All udev Devices[0m...
756 11:44:05.374647 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
757 11:44:05.386983 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
758 11:44:05.398497 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
759 11:44:05.450013 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
760 11:44:05.501608 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
761 11:44:05.522205 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
762 11:44:05.597819 Mounting [0;1;39mKernel Configuration File System[0m...
763 11:44:05.701955 Starting [0;1;39mApply Kernel Variables[0m...
764 11:44:05.782198 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
765 11:44:05.849797 <47>[ 7.910388] systemd-journald[109]: SELinux enabled state cached to: disabled
766 11:44:05.851113 <47>[ 7.911849] systemd-journald[109]: Auditing in kernel turned off.
767 11:44:05.871794 <47>[ 7.932619] systemd-journald[109]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
768 11:44:05.910940 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
769 11:44:05.933669 <47>[ 7.994280] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
770 11:44:05.936066 <47>[ 7.996811] systemd-journald[109]: Fixed min_use=3.8M max_use=19.3M max_size=2.4M min_size=512.0K keep_free=9.6M n_max_files=100
771 11:44:05.938356 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
772 11:44:05.941217 See 'systemctl status systemd-remount-fs.service' for details.
773 11:44:05.950114 <47>[ 8.011032] systemd-journald[109]: Reserving 333 entries in field hash table.
774 11:44:05.975100 <47>[ 8.035990] systemd-journald[109]: Reserving 4394 entries in data hash table.
775 11:44:05.978680 Starting [0;1;39mLoad/Save Random Seed[0m...
776 11:44:05.993212 <47>[ 8.054116] systemd-journald[109]: Vacuuming...
777 11:44:05.994167 <47>[ 8.054863] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
778 11:44:05.994680 <47>[ 8.055629] systemd-journald[109]: Flushing /dev/kmsg...
779 11:44:06.037934 Starting [0;1;39mCreate System Users[0m...
780 11:44:06.182638 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
781 11:44:06.342635 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
782 11:44:06.386498 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
783 11:44:06.516389 <47>[ 8.577167] systemd-journald[109]: systemd-journald running as PID 109 for the system.
784 11:44:06.530463 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
785 11:44:06.544977 <47>[ 8.605826] systemd-journald[109]: Sent READY=1 notification.
786 11:44:06.545535 <47>[ 8.606274] systemd-journald[109]: Sent WATCHDOG=1 notification.
787 11:44:06.575779 <47>[ 8.636601] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
788 11:44:06.586554 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
789 11:44:06.613002 <47>[ 8.673802] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
790 11:44:06.627883 <47>[ 8.688727] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
791 11:44:06.635344 <47>[ 8.696002] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
792 11:44:06.646545 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
793 11:44:06.654957 <47>[ 8.715840] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
794 11:44:06.657525 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
795 11:44:06.662420 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
796 11:44:06.670769 <47>[ 8.731382] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
797 11:44:06.681372 <47>[ 8.742252] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
798 11:44:06.699946 <47>[ 8.760798] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
799 11:44:06.714793 <47>[ 8.775572] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
800 11:44:06.716437 <47>[ 8.777158] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
801 11:44:06.731182 <47>[ 8.791780] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
802 11:44:06.732732 <47>[ 8.793423] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
803 11:44:06.746523 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
804 11:44:06.749328 <47>[ 8.810028] systemd-journald[109]: n/a: New incoming connection.
805 11:44:06.749887 <47>[ 8.810556] systemd-journald[109]: varlink-20: varlink: setting state idle-server
806 11:44:06.770013 <47>[ 8.830582] systemd-journald[109]: varlink-20: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
807 11:44:06.771793 <47>[ 8.832431] systemd-journald[109]: varlink-20: varlink: changing state idle-server → processing-method
808 11:44:06.772008 <46>[ 8.832746] systemd-journald[109]: Received client request to flush runtime journal.
809 11:44:06.772285 <47>[ 8.833139] systemd-journald[109]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
810 11:44:06.785968 <47>[ 8.846810] systemd-journald[109]: Vacuuming...
811 11:44:06.786623 <47>[ 8.847277] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
812 11:44:06.787848 <47>[ 8.848448] systemd-journald[109]: varlink-20: Sending message: {\"parameters\":{}}
813 11:44:06.788036 <47>[ 8.848693] systemd-journald[109]: varlink-20: varlink: changing state processing-method → processed-method
814 11:44:06.788305 <47>[ 8.849117] systemd-journald[109]: varlink-20: varlink: changing state processed-method → idle-server
815 11:44:06.809573 <47>[ 8.870021] systemd-journald[109]: varlink-20: varlink: changing state idle-server → pending-disconnect
816 11:44:06.809899 <47>[ 8.870398] systemd-journald[109]: varlink-20: varlink: changing state pending-disconnect → processing-disconnect
817 11:44:06.810130 <47>[ 8.870686] systemd-journald[109]: varlink-20: varlink: changing state processing-disconnect → disconnected
818 11:44:06.811791 <47>[ 8.872482] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
819 11:44:06.821794 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
820 11:44:06.832465 <47>[ 8.892999] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
821 11:44:06.843187 <47>[ 8.903828] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
822 11:44:06.882271 Starting [0;1;39mCreate Volatile Files and Directories[0m...
823 11:44:06.895825 <47>[ 8.956662] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
824 11:44:07.345160 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
825 11:44:07.609998 Starting [0;1;39mNetwork Service[0m...
826 11:44:07.618586 <47>[ 9.679244] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
827 11:44:07.971462 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
828 11:44:08.094574 Starting [0;1;39mNetwork Time Synchronization[0m...
829 11:44:08.111234 <47>[ 10.171786] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
830 11:44:08.162863 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
831 11:44:08.179398 <47>[ 10.240203] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
832 11:44:08.661800 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
833 11:44:09.560289 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
834 11:44:09.580189 <47>[ 11.640711] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
835 11:44:09.680026 Starting [0;1;39mNetwork Name Resolution[0m...
836 11:44:09.724138 <47>[ 11.784869] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
837 11:44:09.893463 <47>[ 11.953897] systemd-journald[109]: Data hash table of /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal has a fill level at 75.1 (3299 of 4394 items, 2531328 file size, 767 bytes per hash table item), suggesting rotation.
838 11:44:09.893751 <47>[ 11.954553] systemd-journald[109]: /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal: Journal header limits reached or header out-of-date, rotating.
839 11:44:09.894115 <47>[ 11.954910] systemd-journald[109]: Rotating...
840 11:44:09.894981 <47>[ 11.955801] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
841 11:44:09.896507 <47>[ 11.957283] systemd-journald[109]: Reserving 333 entries in field hash table.
842 11:44:09.950800 <47>[ 12.011603] systemd-journald[109]: Reserving 4394 entries in data hash table.
843 11:44:09.970129 <47>[ 12.030989] systemd-journald[109]: Vacuuming...
844 11:44:09.972494 <47>[ 12.032749] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
845 11:44:10.327112 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
846 11:44:10.329460 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
847 11:44:10.337778 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
848 11:44:11.174936 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
849 11:44:11.182996 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
850 11:44:11.208928 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
851 11:44:11.224846 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
852 11:44:11.236157 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
853 11:44:11.243602 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
854 11:44:11.274969 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
855 11:44:11.275783 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
856 11:44:11.276276 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
857 11:44:11.351107 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
858 11:44:11.359605 <47>[ 13.420143] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
859 11:44:11.522304 <47>[ 13.582805] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
860 11:44:11.523178 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
861 11:44:11.747459 Starting [0;1;39mUser Login Management[0m...
862 11:44:11.763651 <47>[ 13.824240] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
863 11:44:12.413034 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
864 11:44:12.421702 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
865 11:44:12.425809 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
866 11:44:12.499216 Starting [0;1;39mPermit User Sessions[0m...
867 11:44:12.507187 <47>[ 14.567853] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
868 11:44:12.561794 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
869 11:44:12.725288 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
870 11:44:12.802173 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
871 11:44:13.080149 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
872 11:44:15.220020 [[0m[0;31m* [0m] A start job is running for /dev/ttyAMA0 (10s / 1min 30s)
873 11:44:15.578594 M[K[[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
874 11:44:15.652807 [K[[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
875 11:44:15.674791 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
876 11:44:15.690595 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
877 11:44:15.702049 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
878 11:44:15.757992 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
879 11:44:15.767868 <47>[ 17.828662] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
880 11:44:15.984134 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
881 11:44:16.043532 <47>[ 18.104071] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
882 11:44:16.053290 <47>[ 18.113800] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
883 11:44:16.136336
884 11:44:16.136546 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
885 11:44:16.136638
886 11:44:16.136711 debian-bullseye-arm64 login: root (automatic login)
887 11:44:16.136774
888 11:44:16.289550 <6>[ 18.350361] virtio_net virtio0 enp0s1: renamed from eth0
889 11:44:16.386013 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
890 11:44:16.386530
891 11:44:16.386661 The programs included with the Debian GNU/Linux system are free software;
892 11:44:16.386775 the exact distribution terms for each program are described in the
893 11:44:16.386880 individual files in /usr/share/doc/*/copyright.
894 11:44:16.386967
895 11:44:16.387074 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
896 11:44:16.387181 permitted by applicable law.
897 11:44:16.987965 <47>[ 19.048396] systemd-journald[109]: Data hash table of /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal has a fill level at 75.0 (3296 of 4394 items, 2531328 file size, 768 bytes per hash table item), suggesting rotation.
898 11:44:16.988353 <47>[ 19.049031] systemd-journald[109]: /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal: Journal header limits reached or header out-of-date, rotating.
899 11:44:16.988618 <47>[ 19.049451] systemd-journald[109]: Rotating...
900 11:44:17.004895 <47>[ 19.065392] systemd-journald[109]: Reserving 333 entries in field hash table.
901 11:44:17.024277 <47>[ 19.085060] systemd-journald[109]: Reserving 4394 entries in data hash table.
902 11:44:17.050692 <47>[ 19.111535] systemd-journald[109]: Vacuuming...
903 11:44:17.052182 <47>[ 19.112825] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
904 11:44:17.079685 <47>[ 19.140202] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
905 11:44:17.364089 <47>[ 19.424585] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
906 11:44:18.547089 <47>[ 20.607871] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
907 11:44:19.633793 Matched prompt #10: / #
909 11:44:19.634368 Setting prompt string to ['/ #']
910 11:44:19.634552 end: 2.2.1 login-action (duration 00:00:22) [common]
912 11:44:19.634967 end: 2.2 auto-login-action (duration 00:00:26) [common]
913 11:44:19.635132 start: 2.3 expect-shell-connection (timeout 00:04:32) [common]
914 11:44:19.635273 Setting prompt string to ['/ #']
915 11:44:19.635396 Forcing a shell prompt, looking for ['/ #']
917 11:44:19.685966 / #
918 11:44:19.686289 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
919 11:44:19.686495 Waiting using forced prompt support (timeout 00:02:30)
920 11:44:19.688137
921 11:44:19.695059 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
922 11:44:19.695339 start: 2.4 export-device-env (timeout 00:04:32) [common]
923 11:44:19.695515 end: 2.4 export-device-env (duration 00:00:00) [common]
924 11:44:19.695681 end: 2 boot-image-retry (duration 00:00:28) [common]
925 11:44:19.695839 start: 3 lava-test-retry (timeout 00:08:49) [common]
926 11:44:19.696002 start: 3.1 lava-test-shell (timeout 00:08:49) [common]
927 11:44:19.696139 Using namespace: common
929 11:44:19.797021 / # #
930 11:44:19.797334 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
931 11:44:19.797963 #
933 11:44:19.907554 / # mkdir /lava-615297
934 11:44:19.908662 mkdir /lava-615297
936 11:44:20.042350 / # mount /dev/disk/by-uuid/4a725230-16fa-41d0-8c89-0970f5cdc28a -t ext2 /lava-615297
937 11:44:20.043301 mount /dev/disk/by-uuid/4a725230-16fa-41d0-8c89-0970f5cdc28a -t ext2 /lava-615297
938 11:44:20.068667 <4>[ 22.129344] ext2 filesystem being mounted at /lava-615297 supports timestamps until 2038 (0x7fffffff)
940 11:44:20.202317 / # ls -la /lava-615297/bin/lava-test-runner
941 11:44:20.203159 ls -la /lava-615297/bin/lava-test-runner
942 11:44:20.231202 -rwxr-xr-x 1 root root 1039 Jun 15 11:43 /lava-615297/bin/lava-test-runner
943 11:44:20.242650 Using /lava-615297
945 11:44:20.343598 / # export SHELL=/bin/sh
946 11:44:20.344561 export SHELL=/bin/sh
948 11:44:20.453718 / # . /lava-615297/environment
949 11:44:20.454759 . /lava-615297/environment
951 11:44:20.567567 / # /lava-615297/bin/lava-test-runner /lava-615297/0
952 11:44:20.567896 Test shell timeout: 10s (minimum of the action and connection timeout)
953 11:44:20.568677 /lava-615297/bin/lava-test-runner /lava-615297/0
954 11:44:20.727855 + export TESTRUN_ID=0_timesync-off
955 11:44:20.728134 + cd /lava-615297/0/tests/0_timesync-off
956 11:44:20.730549 + cat uuid
957 11:44:20.739488 + UUID=615297_1.1.3.1
958 11:44:20.739751 + set +x
959 11:44:20.740053 <LAVA_SIGNAL_STARTRUN 0_timesync-off 615297_1.1.3.1>
960 11:44:20.740382 Received signal: <STARTRUN> 0_timesync-off 615297_1.1.3.1
961 11:44:20.740494 Starting test lava.0_timesync-off (615297_1.1.3.1)
962 11:44:20.740632 Skipping test definition patterns.
963 11:44:20.740790 + systemctl stop systemd-timesyncd
964 11:44:20.997823 + set +x
965 11:44:20.998274 <LAVA_SIGNAL_ENDRUN 0_timesync-off 615297_1.1.3.1>
966 11:44:20.998568 Received signal: <ENDRUN> 0_timesync-off 615297_1.1.3.1
967 11:44:20.998707 Ending use of test pattern.
968 11:44:20.998802 Ending test lava.0_timesync-off (615297_1.1.3.1), duration 0.26
970 11:44:21.044651 + export TESTRUN_ID=1_kselftest-arm64_qemu
971 11:44:21.044913 + cd /lava-615297/0/tests/1_kselftest-arm64_qemu
972 11:44:21.047302 + cat uuid
973 11:44:21.056058 + UUID=615297_1.1.3.5
974 11:44:21.056608 + set +x
975 11:44:21.056853 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 615297_1.1.3.5>
976 11:44:21.057310 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 615297_1.1.3.5
977 11:44:21.057487 Starting test lava.1_kselftest-arm64_qemu (615297_1.1.3.5)
978 11:44:21.057712 Skipping test definition patterns.
979 11:44:21.057939 + cd ./automated/linux/kselftest/
980 11:44:21.062549 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip -e -p /opt/kselftests/mainline/ -n 1 -i 1
981 11:44:21.163172 INFO: install_deps skipped
982 11:44:21.197091 --2023-06-15 11:44:20-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
983 11:44:21.357020 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
984 11:44:21.557959 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
985 11:44:21.745456 HTTP request sent, awaiting response... 200 OK
986 11:44:21.748816 Length: 2884276 (2.8M) [application/octet-stream]
987 11:44:21.750414 Saving to: 'kselftest.tar.xz'
988 11:44:21.751690
989 11:44:22.989362 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 151KB/s kselftest.tar.xz 7%[> ] 219.84K 323KB/s kselftest.tar.xz 31%[=====> ] 898.59K 878KB/s kselftest.tar.xz 73%[=============> ] 2.01M 1.64MB/s kselftest.tar.xz 100%[===================>] 2.75M 2.18MB/s in 1.3s
990 11:44:22.989616
991 11:44:22.992092 2023-06-15 11:44:22 (2.18 MB/s) - 'kselftest.tar.xz' saved [2884276/2884276]
992 11:44:22.992221
993 11:44:26.116830 skiplist:
994 11:44:26.117117 ========================================
995 11:44:26.118004 ========================================
996 11:44:26.175353 arm64:tags_test
997 11:44:26.175596 arm64:run_tags_test.sh
998 11:44:26.175676 arm64:fake_sigreturn_bad_magic
999 11:44:26.176013 arm64:fake_sigreturn_bad_size
1000 11:44:26.176112 arm64:fake_sigreturn_bad_size_for_magic0
1001 11:44:26.176188 arm64:fake_sigreturn_duplicated_fpsimd
1002 11:44:26.176258 arm64:fake_sigreturn_misaligned_sp
1003 11:44:26.176329 arm64:fake_sigreturn_missing_fpsimd
1004 11:44:26.176400 arm64:fake_sigreturn_sme_change_vl
1005 11:44:26.176470 arm64:fake_sigreturn_sve_change_vl
1006 11:44:26.176539 arm64:mangle_pstate_invalid_compat_toggle
1007 11:44:26.176628 arm64:mangle_pstate_invalid_daif_bits
1008 11:44:26.176702 arm64:mangle_pstate_invalid_mode_el1h
1009 11:44:26.176772 arm64:mangle_pstate_invalid_mode_el1t
1010 11:44:26.177102 arm64:mangle_pstate_invalid_mode_el2h
1011 11:44:26.177265 arm64:mangle_pstate_invalid_mode_el2t
1012 11:44:26.177401 arm64:mangle_pstate_invalid_mode_el3h
1013 11:44:26.177555 arm64:mangle_pstate_invalid_mode_el3t
1014 11:44:26.177696 arm64:sme_trap_no_sm
1015 11:44:26.177819 arm64:sme_trap_non_streaming
1016 11:44:26.177940 arm64:sme_trap_za
1017 11:44:26.178058 arm64:sme_vl
1018 11:44:26.178177 arm64:ssve_regs
1019 11:44:26.178295 arm64:sve_regs
1020 11:44:26.178440 arm64:sve_vl
1021 11:44:26.178559 arm64:za_no_regs
1022 11:44:26.178655 arm64:za_regs
1023 11:44:26.178744 arm64:pac
1024 11:44:26.178833 arm64:fp-stress
1025 11:44:26.178931 arm64:sve-ptrace
1026 11:44:26.179023 arm64:sve-probe-vls
1027 11:44:26.179112 arm64:vec-syscfg
1028 11:44:26.179201 arm64:za-fork
1029 11:44:26.179288 arm64:za-ptrace
1030 11:44:26.179376 arm64:check_buffer_fill
1031 11:44:26.179463 arm64:check_child_memory
1032 11:44:26.179560 arm64:check_gcr_el1_cswitch
1033 11:44:26.179687 arm64:check_ksm_options
1034 11:44:26.179839 arm64:check_mmap_options
1035 11:44:26.179953 arm64:check_prctl
1036 11:44:26.180045 arm64:check_tags_inclusion
1037 11:44:26.180133 arm64:check_user_mem
1038 11:44:26.180221 arm64:btitest
1039 11:44:26.180309 arm64:nobtitest
1040 11:44:26.180396 arm64:hwcap
1041 11:44:26.180483 arm64:ptrace
1042 11:44:26.180573 arm64:syscall-abi
1043 11:44:26.180661 arm64:tpidr2
1044 11:44:26.191160 ============== Tests to run ===============
1045 11:44:26.196932 arm64:tags_test
1046 11:44:26.197183 arm64:run_tags_test.sh
1047 11:44:26.197277 arm64:fake_sigreturn_bad_magic
1048 11:44:26.197568 arm64:fake_sigreturn_bad_size
1049 11:44:26.197692 arm64:fake_sigreturn_bad_size_for_magic0
1050 11:44:26.197785 arm64:fake_sigreturn_duplicated_fpsimd
1051 11:44:26.197874 arm64:fake_sigreturn_misaligned_sp
1052 11:44:26.197962 arm64:fake_sigreturn_missing_fpsimd
1053 11:44:26.198048 arm64:fake_sigreturn_sme_change_vl
1054 11:44:26.198154 arm64:fake_sigreturn_sve_change_vl
1055 11:44:26.198243 arm64:mangle_pstate_invalid_compat_toggle
1056 11:44:26.198331 arm64:mangle_pstate_invalid_daif_bits
1057 11:44:26.198415 arm64:mangle_pstate_invalid_mode_el1h
1058 11:44:26.198502 arm64:mangle_pstate_invalid_mode_el1t
1059 11:44:26.198606 arm64:mangle_pstate_invalid_mode_el2h
1060 11:44:26.198696 arm64:mangle_pstate_invalid_mode_el2t
1061 11:44:26.198783 arm64:mangle_pstate_invalid_mode_el3h
1062 11:44:26.198867 arm64:mangle_pstate_invalid_mode_el3t
1063 11:44:26.198951 arm64:sme_trap_no_sm
1064 11:44:26.199054 arm64:sme_trap_non_streaming
1065 11:44:26.199144 arm64:sme_trap_za
1066 11:44:26.199228 arm64:sme_vl
1067 11:44:26.199314 arm64:ssve_regs
1068 11:44:26.199400 arm64:sve_regs
1069 11:44:26.199487 arm64:sve_vl
1070 11:44:26.199593 arm64:za_no_regs
1071 11:44:26.199680 arm64:za_regs
1072 11:44:26.199763 arm64:pac
1073 11:44:26.199844 arm64:fp-stress
1074 11:44:26.199926 arm64:sve-ptrace
1075 11:44:26.200007 arm64:sve-probe-vls
1076 11:44:26.200088 arm64:vec-syscfg
1077 11:44:26.200169 arm64:za-fork
1078 11:44:26.200250 arm64:za-ptrace
1079 11:44:26.200350 arm64:check_buffer_fill
1080 11:44:26.200437 arm64:check_child_memory
1081 11:44:26.200520 arm64:check_gcr_el1_cswitch
1082 11:44:26.200602 arm64:check_ksm_options
1083 11:44:26.200687 arm64:check_mmap_options
1084 11:44:26.200772 arm64:check_prctl
1085 11:44:26.200854 arm64:check_tags_inclusion
1086 11:44:26.200936 arm64:check_user_mem
1087 11:44:26.201038 arm64:btitest
1088 11:44:26.201126 arm64:nobtitest
1089 11:44:26.201211 arm64:hwcap
1090 11:44:26.201292 arm64:ptrace
1091 11:44:26.201375 arm64:syscall-abi
1092 11:44:26.201458 arm64:tpidr2
1093 11:44:26.202484 ===========End Tests to run ===============
1094 11:44:27.165943 <12>[ 29.226709] kselftest: Running tests in arm64
1095 11:44:27.194890 TAP version 13
1096 11:44:27.214076 1..48
1097 11:44:27.264390 # selftests: arm64: tags_test
1098 11:44:27.319931 ok 1 selftests: arm64: tags_test
1099 11:44:27.369861 # selftests: arm64: run_tags_test.sh
1100 11:44:27.422850 # --------------------
1101 11:44:27.423094 # running tags test
1102 11:44:27.423398 # --------------------
1103 11:44:27.423500 # [PASS]
1104 11:44:27.429103 ok 2 selftests: arm64: run_tags_test.sh
1105 11:44:27.480605 # selftests: arm64: fake_sigreturn_bad_magic
1106 11:44:27.538623 # Registered handlers for all signals.
1107 11:44:27.538865 # Detected MINSTKSIGSZ:10000
1108 11:44:27.539166 # Testcase initialized.
1109 11:44:27.539264 # uc context validated.
1110 11:44:27.539348 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1111 11:44:27.539429 # Handled SIG_COPYCTX
1112 11:44:27.539507 # Available space:3536
1113 11:44:27.539579 # Using badly built context - ERR: BAD MAGIC !
1114 11:44:27.539652 # SIG_OK -- SP:0xFFFFCD7D3810 si_addr@:0xffffcd7d3810 si_code:2 token@:0xffffcd7d25b0 offset:-4704
1115 11:44:27.541019 # ==>> completed. PASS(1)
1116 11:44:27.541328 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1117 11:44:27.541421 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCD7D25B0
1118 11:44:27.549201 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1119 11:44:27.606989 # selftests: arm64: fake_sigreturn_bad_size
1120 11:44:27.674465 # Registered handlers for all signals.
1121 11:44:27.675064 # Detected MINSTKSIGSZ:10000
1122 11:44:27.675177 # Testcase initialized.
1123 11:44:27.675270 # uc context validated.
1124 11:44:27.675361 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1125 11:44:27.675449 # Handled SIG_COPYCTX
1126 11:44:27.675534 # Available space:3536
1127 11:44:27.675620 # uc context validated.
1128 11:44:27.675703 # Using badly built context - ERR: Bad size for esr_context
1129 11:44:27.675806 # SIG_OK -- SP:0xFFFFF6F6F410 si_addr@:0xfffff6f6f410 si_code:2 token@:0xfffff6f6e1b0 offset:-4704
1130 11:44:27.675897 # ==>> completed. PASS(1)
1131 11:44:27.675985 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1132 11:44:27.676073 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF6F6E1B0
1133 11:44:27.687667 ok 4 selftests: arm64: fake_sigreturn_bad_size
1134 11:44:27.741197 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1135 11:44:27.791791 # Registered handlers for all signals.
1136 11:44:27.792027 # Detected MINSTKSIGSZ:10000
1137 11:44:27.792105 # Testcase initialized.
1138 11:44:27.792383 # uc context validated.
1139 11:44:27.792465 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1140 11:44:27.792536 # Handled SIG_COPYCTX
1141 11:44:27.792608 # Available space:3536
1142 11:44:27.792684 # Using badly built context - ERR: Bad size for terminator
1143 11:44:27.794513 # SIG_OK -- SP:0xFFFFDDE62480 si_addr@:0xffffdde62480 si_code:2 token@:0xffffdde61220 offset:-4704
1144 11:44:27.794608 # ==>> completed. PASS(1)
1145 11:44:27.794675 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1146 11:44:27.794961 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDDE61220
1147 11:44:27.801671 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1148 11:44:27.850358 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1149 11:44:27.901678 # Registered handlers for all signals.
1150 11:44:27.901962 # Detected MINSTKSIGSZ:10000
1151 11:44:27.903159 # Testcase initialized.
1152 11:44:27.903374 # uc context validated.
1153 11:44:27.903778 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1154 11:44:27.903926 # Handled SIG_COPYCTX
1155 11:44:27.904067 # Available space:3536
1156 11:44:27.904190 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1157 11:44:27.904305 # SIG_OK -- SP:0xFFFFC73DE7E0 si_addr@:0xffffc73de7e0 si_code:2 token@:0xffffc73dd580 offset:-4704
1158 11:44:27.904418 # ==>> completed. PASS(1)
1159 11:44:27.904762 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1160 11:44:27.904910 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC73DD580
1161 11:44:27.911517 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1162 11:44:27.958931 # selftests: arm64: fake_sigreturn_misaligned_sp
1163 11:44:28.011655 # Registered handlers for all signals.
1164 11:44:28.011986 # Detected MINSTKSIGSZ:10000
1165 11:44:28.012368 # Testcase initialized.
1166 11:44:28.012464 # uc context validated.
1167 11:44:28.012542 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1168 11:44:28.012618 # Handled SIG_COPYCTX
1169 11:44:28.012695 # SIG_OK -- SP:0xFFFFC4A4CF93 si_addr@:0xffffc4a4cf93 si_code:2 token@:0xffffc4a4cf93 offset:0
1170 11:44:28.012771 # ==>> completed. PASS(1)
1171 11:44:28.012846 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1172 11:44:28.012936 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC4A4CF93
1173 11:44:28.019209 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1174 11:44:28.067553 # selftests: arm64: fake_sigreturn_missing_fpsimd
1175 11:44:28.118697 # Registered handlers for all signals.
1176 11:44:28.119162 # Detected MINSTKSIGSZ:10000
1177 11:44:28.119264 # Testcase initialized.
1178 11:44:28.119343 # uc context validated.
1179 11:44:28.119417 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1180 11:44:28.119490 # Handled SIG_COPYCTX
1181 11:44:28.119562 # Mangling template header. Spare space:4096
1182 11:44:28.119649 # Using badly built context - ERR: Missing FPSIMD
1183 11:44:28.119724 # SIG_OK -- SP:0xFFFFD3B85EB0 si_addr@:0xffffd3b85eb0 si_code:2 token@:0xffffd3b84c50 offset:-4704
1184 11:44:28.119797 # ==>> completed. PASS(1)
1185 11:44:28.119882 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1186 11:44:28.120147 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD3B84C50
1187 11:44:28.128137 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1188 11:44:28.178235 # selftests: arm64: fake_sigreturn_sme_change_vl
1189 11:44:28.229666 # Registered handlers for all signals.
1190 11:44:28.230160 # Detected MINSTKSIGSZ:10000
1191 11:44:28.230359 # Required Features: [ SME ] supported
1192 11:44:28.230532 # Incompatible Features: [] absent
1193 11:44:28.230693 # Testcase initialized.
1194 11:44:28.230856 # uc context validated.
1195 11:44:28.231017 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1196 11:44:28.231140 # Handled SIG_COPYCTX
1197 11:44:28.231254 # Attempting to change VL from 16 to 256
1198 11:44:28.231367 # SIG_OK -- SP:0xFFFFF06AF1B0 si_addr@:0xfffff06af1b0 si_code:2 token@:0xfffff06adf50 offset:-4704
1199 11:44:28.231485 # ==>> completed. PASS(1)
1200 11:44:28.231598 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1201 11:44:28.231734 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF06ADF50
1202 11:44:28.238934 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1203 11:44:28.285588 # selftests: arm64: fake_sigreturn_sve_change_vl
1204 11:44:28.336846 # Registered handlers for all signals.
1205 11:44:28.337154 # Detected MINSTKSIGSZ:10000
1206 11:44:28.337359 # Required Features: [ SVE ] supported
1207 11:44:28.337561 # Incompatible Features: [] absent
1208 11:44:28.337810 # Testcase initialized.
1209 11:44:28.337975 # uc context validated.
1210 11:44:28.338100 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1211 11:44:28.338218 # Handled SIG_COPYCTX
1212 11:44:28.338330 # Attempting to change VL from 16 to 256
1213 11:44:28.338442 # SIG_OK -- SP:0xFFFFCA3F1430 si_addr@:0xffffca3f1430 si_code:2 token@:0xffffca3f01d0 offset:-4704
1214 11:44:28.338557 # ==>> completed. PASS(1)
1215 11:44:28.338672 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1216 11:44:28.338809 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCA3F01D0
1217 11:44:28.345855 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1218 11:44:28.392432 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1219 11:44:28.441870 # Registered handlers for all signals.
1220 11:44:28.442110 # Detected MINSTKSIGSZ:10000
1221 11:44:28.442426 # Testcase initialized.
1222 11:44:28.442526 # uc context validated.
1223 11:44:28.442612 # Handled SIG_TRIG
1224 11:44:28.442697 # SIG_OK -- SP:0xFFFFE0080D40 si_addr@:0xffffe0080d40 si_code:2 token@:(nil) offset:-281474440367424
1225 11:44:28.442781 # ==>> completed. PASS(1)
1226 11:44:28.442876 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1227 11:44:28.450397 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1228 11:44:28.496997 # selftests: arm64: mangle_pstate_invalid_daif_bits
1229 11:44:28.550302 # Registered handlers for all signals.
1230 11:44:28.550650 # Detected MINSTKSIGSZ:10000
1231 11:44:28.550801 # Testcase initialized.
1232 11:44:28.551151 # uc context validated.
1233 11:44:28.551320 # Handled SIG_TRIG
1234 11:44:28.551457 # SIG_OK -- SP:0xFFFFD14DE430 si_addr@:0xffffd14de430 si_code:2 token@:(nil) offset:-281474193286192
1235 11:44:28.551577 # ==>> completed. PASS(1)
1236 11:44:28.551694 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1237 11:44:28.558670 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1238 11:44:28.606407 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1239 11:44:28.655627 # Registered handlers for all signals.
1240 11:44:28.655972 # Detected MINSTKSIGSZ:10000
1241 11:44:28.656180 # Testcase initialized.
1242 11:44:28.656571 # uc context validated.
1243 11:44:28.656732 # Handled SIG_TRIG
1244 11:44:28.656858 # SIG_OK -- SP:0xFFFFEB8CD6C0 si_addr@:0xffffeb8cd6c0 si_code:2 token@:(nil) offset:-281474633619136
1245 11:44:28.656979 # ==>> completed. PASS(1)
1246 11:44:28.657098 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1247 11:44:28.665606 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1248 11:44:28.712975 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1249 11:44:28.762628 # Registered handlers for all signals.
1250 11:44:28.762990 # Detected MINSTKSIGSZ:10000
1251 11:44:28.763188 # Testcase initialized.
1252 11:44:28.763553 # uc context validated.
1253 11:44:28.763689 # Handled SIG_TRIG
1254 11:44:28.763813 # SIG_OK -- SP:0xFFFFF5467EC0 si_addr@:0xfffff5467ec0 si_code:2 token@:(nil) offset:-281474796781248
1255 11:44:28.763935 # ==>> completed. PASS(1)
1256 11:44:28.764053 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1257 11:44:28.770363 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1258 11:44:28.822005 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1259 11:44:28.873582 # Registered handlers for all signals.
1260 11:44:28.873926 # Detected MINSTKSIGSZ:10000
1261 11:44:28.874085 # Testcase initialized.
1262 11:44:28.874452 # uc context validated.
1263 11:44:28.874613 # Handled SIG_TRIG
1264 11:44:28.874738 # SIG_OK -- SP:0xFFFFE49EC970 si_addr@:0xffffe49ec970 si_code:2 token@:(nil) offset:-281474517354864
1265 11:44:28.874861 # ==>> completed. PASS(1)
1266 11:44:28.874980 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1267 11:44:28.883285 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1268 11:44:28.931592 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1269 11:44:28.982748 # Registered handlers for all signals.
1270 11:44:28.983084 # Detected MINSTKSIGSZ:10000
1271 11:44:28.983494 # Testcase initialized.
1272 11:44:28.983704 # uc context validated.
1273 11:44:28.983904 # Handled SIG_TRIG
1274 11:44:28.984069 # SIG_OK -- SP:0xFFFFC32FF8C0 si_addr@:0xffffc32ff8c0 si_code:2 token@:(nil) offset:-281473956444352
1275 11:44:28.984203 # ==>> completed. PASS(1)
1276 11:44:28.984328 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1277 11:44:28.992424 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1278 11:44:29.038752 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1279 11:44:29.088683 # Registered handlers for all signals.
1280 11:44:29.088927 # Detected MINSTKSIGSZ:10000
1281 11:44:29.089209 # Testcase initialized.
1282 11:44:29.089383 # uc context validated.
1283 11:44:29.089557 # Handled SIG_TRIG
1284 11:44:29.089725 # SIG_OK -- SP:0xFFFFDFD47570 si_addr@:0xffffdfd47570 si_code:2 token@:(nil) offset:-281474436986224
1285 11:44:29.089875 # ==>> completed. PASS(1)
1286 11:44:29.090053 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1287 11:44:29.096430 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1288 11:44:29.142804 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1289 11:44:29.196648 # Registered handlers for all signals.
1290 11:44:29.197240 # Detected MINSTKSIGSZ:10000
1291 11:44:29.197416 # Testcase initialized.
1292 11:44:29.197591 # uc context validated.
1293 11:44:29.197781 # Handled SIG_TRIG
1294 11:44:29.197926 # SIG_OK -- SP:0xFFFFE59AE720 si_addr@:0xffffe59ae720 si_code:2 token@:(nil) offset:-281474533877536
1295 11:44:29.198056 # ==>> completed. PASS(1)
1296 11:44:29.198209 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1297 11:44:29.205185 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1298 11:44:29.253117 # selftests: arm64: sme_trap_no_sm
1299 11:44:29.366797 # Registered handlers for all signals.
1300 11:44:29.367362 # Detected MINSTKSIGSZ:10000
1301 11:44:29.367583 # Required Features: [ SME ] supported
1302 11:44:29.367789 # Incompatible Features: [] absent
1303 11:44:29.367996 # Testcase initialized.
1304 11:44:29.368152 # SIG_OK -- SP:0xFFFFC85756B0 si_addr@:0xaaaae03b2514 si_code:1 token@:(nil) offset:-187650883134740
1305 11:44:29.368314 # ==>> completed. PASS(1)
1306 11:44:29.368450 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1307 11:44:29.384837 ok 19 selftests: arm64: sme_trap_no_sm
1308 11:44:29.483780 # selftests: arm64: sme_trap_non_streaming
1309 11:44:29.549777 # Registered handlers for all signals.
1310 11:44:29.550025 # Detected MINSTKSIGSZ:10000
1311 11:44:29.550123 # Required Features: [] NOT supported
1312 11:44:29.550414 # Incompatible Features: [] supported
1313 11:44:29.550593 # ==>> completed. SKIP.
1314 11:44:29.550733 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1315 11:44:29.560082 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1316 11:44:29.614399 # selftests: arm64: sme_trap_za
1317 11:44:29.668867 # Registered handlers for all signals.
1318 11:44:29.669209 # Detected MINSTKSIGSZ:10000
1319 11:44:29.669398 # Testcase initialized.
1320 11:44:29.669577 # SIG_OK -- SP:0xFFFFF80863D0 si_addr@:0xaaaad1812510 si_code:1 token@:(nil) offset:-187650636064016
1321 11:44:29.669762 # ==>> completed. PASS(1)
1322 11:44:29.669916 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1323 11:44:29.678255 ok 21 selftests: arm64: sme_trap_za
1324 11:44:29.729368 # selftests: arm64: sme_vl
1325 11:44:29.787366 # Registered handlers for all signals.
1326 11:44:29.787846 # Detected MINSTKSIGSZ:10000
1327 11:44:29.787945 # Required Features: [ SME ] supported
1328 11:44:29.788022 # Incompatible Features: [] absent
1329 11:44:29.788096 # Testcase initialized.
1330 11:44:29.788168 # uc context validated.
1331 11:44:29.788239 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1332 11:44:29.788310 # Handled SIG_COPYCTX
1333 11:44:29.788380 # got expected VL 32
1334 11:44:29.788464 # ==>> completed. PASS(1)
1335 11:44:29.788540 # # SME VL :: Check that we get the right SME VL reported
1336 11:44:29.797127 ok 22 selftests: arm64: sme_vl
1337 11:44:29.848378 # selftests: arm64: ssve_regs
1338 11:44:30.041767 # Registered handlers for all signals.
1339 11:44:30.042058 # Detected MINSTKSIGSZ:10000
1340 11:44:30.042462 # Required Features: [ SME FA64 ] supported
1341 11:44:30.042635 # Incompatible Features: [] absent
1342 11:44:30.042820 # Testcase initialized.
1343 11:44:30.042970 # Testing VL 256
1344 11:44:30.043112 # Validating EXTRA...
1345 11:44:30.043254 # uc context validated.
1346 11:44:30.043949 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1347 11:44:30.044163 # Handled SIG_COPYCTX
1348 11:44:30.044660 # Got expected size 8752 and VL 256
1349 11:44:30.044871 # Testing VL 128
1350 11:44:30.045081 # Validating EXTRA...
1351 11:44:30.045311 # uc context validated.
1352 11:44:30.045529 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1353 11:44:30.045743 # Handled SIG_COPYCTX
1354 11:44:30.045900 # Got expected size 4384 and VL 128
1355 11:44:30.046024 # Testing VL 64
1356 11:44:30.046141 # uc context validated.
1357 11:44:30.046256 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1358 11:44:30.046371 # Handled SIG_COPYCTX
1359 11:44:30.046519 # Got expected size 2208 and VL 64
1360 11:44:30.046644 # Testing VL 32
1361 11:44:30.046762 # uc context validated.
1362 11:44:30.046876 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1363 11:44:30.046993 # Handled SIG_COPYCTX
1364 11:44:30.047107 # Got expected size 1120 and VL 32
1365 11:44:30.047221 # Testing VL 16
1366 11:44:30.047335 # uc context validated.
1367 11:44:30.047449 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1368 11:44:30.047563 # Handled SIG_COPYCTX
1369 11:44:30.047679 # Got expected size 576 and VL 16
1370 11:44:30.047793 # ==>> completed. PASS(1)
1371 11:44:30.047908 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1372 11:44:30.052919 ok 23 selftests: arm64: ssve_regs
1373 11:44:30.102295 # selftests: arm64: sve_regs
1374 11:44:30.669223 # Registered handlers for all signals.
1375 11:44:30.669474 # Detected MINSTKSIGSZ:10000
1376 11:44:30.669572 # Required Features: [ SVE ] supported
1377 11:44:30.671232 # Incompatible Features: [] absent
1378 11:44:30.671439 # Testcase initialized.
1379 11:44:30.671849 # Testing VL 256
1380 11:44:30.672025 # Validating EXTRA...
1381 11:44:30.672213 # uc context validated.
1382 11:44:30.672364 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1383 11:44:30.672508 # Handled SIG_COPYCTX
1384 11:44:30.672650 # Got expected size 8752 and VL 256
1385 11:44:30.672793 # Testing VL 240
1386 11:44:30.672935 # Validating EXTRA...
1387 11:44:30.673137 # uc context validated.
1388 11:44:30.673318 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1389 11:44:30.673454 # Handled SIG_COPYCTX
1390 11:44:30.673574 # Got expected size 8208 and VL 240
1391 11:44:30.673707 # Testing VL 224
1392 11:44:30.673825 # Validating EXTRA...
1393 11:44:30.673942 # uc context validated.
1394 11:44:30.674057 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1395 11:44:30.674176 # Handled SIG_COPYCTX
1396 11:44:30.674292 # Got expected size 7664 and VL 224
1397 11:44:30.674408 # Testing VL 208
1398 11:44:30.674524 # Validating EXTRA...
1399 11:44:30.674639 # uc context validated.
1400 11:44:30.674754 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1401 11:44:30.674870 # Handled SIG_COPYCTX
1402 11:44:30.674985 # Got expected size 7120 and VL 208
1403 11:44:30.675102 # Testing VL 192
1404 11:44:30.675247 # Validating EXTRA...
1405 11:44:30.675373 # uc context validated.
1406 11:44:30.675491 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1407 11:44:30.680628 # Handled SIG_COPYCTX
1408 11:44:30.680895 # Got expected size 6576 and VL 192
1409 11:44:30.681071 # Testing VL 176
1410 11:44:30.681510 # Validating EXTRA...
1411 11:44:30.681713 # uc context validated.
1412 11:44:30.681894 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1413 11:44:30.682060 # Handled SIG_COPYCTX
1414 11:44:30.682188 # Got expected size 6032 and VL 176
1415 11:44:30.682317 # Testing VL 160
1416 11:44:30.682443 # Validating EXTRA...
1417 11:44:30.682597 # uc context validated.
1418 11:44:30.682728 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1419 11:44:30.682854 # Handled SIG_COPYCTX
1420 11:44:30.682976 # Got expected size 5488 and VL 160
1421 11:44:30.683102 # Testing VL 144
1422 11:44:30.683248 # Validating EXTRA...
1423 11:44:30.683376 # uc context validated.
1424 11:44:30.683498 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1425 11:44:30.683619 # Handled SIG_COPYCTX
1426 11:44:30.683763 # Got expected size 4944 and VL 144
1427 11:44:30.683890 # Testing VL 128
1428 11:44:30.684011 # Validating EXTRA...
1429 11:44:30.684140 # uc context validated.
1430 11:44:30.684287 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1431 11:44:30.684417 # Handled SIG_COPYCTX
1432 11:44:30.684543 # Got expected size 4384 and VL 128
1433 11:44:30.684670 # Testing VL 112
1434 11:44:30.684819 # Validating EXTRA...
1435 11:44:30.684948 # uc context validated.
1436 11:44:30.685073 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1437 11:44:30.685199 # Handled SIG_COPYCTX
1438 11:44:30.685345 # Got expected size 3840 and VL 112
1439 11:44:30.685473 # Testing VL 96
1440 11:44:30.692634 # uc context validated.
1441 11:44:30.693175 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1442 11:44:30.693334 # Handled SIG_COPYCTX
1443 11:44:30.693527 # Got expected size 3296 and VL 96
1444 11:44:30.693702 # Testing VL 80
1445 11:44:30.693905 # uc context validated.
1446 11:44:30.694064 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1447 11:44:30.694238 # Handled SIG_COPYCTX
1448 11:44:30.694410 # Got expected size 2752 and VL 80
1449 11:44:30.694576 # Testing VL 64
1450 11:44:30.694743 # uc context validated.
1451 11:44:30.694904 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1452 11:44:30.695063 # Handled SIG_COPYCTX
1453 11:44:30.695238 # Got expected size 2208 and VL 64
1454 11:44:30.695432 # Testing VL 48
1455 11:44:30.695590 # uc context validated.
1456 11:44:30.695810 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1457 11:44:30.695972 # Handled SIG_COPYCTX
1458 11:44:30.696153 # Got expected size 1664 and VL 48
1459 11:44:30.696326 # Testing VL 32
1460 11:44:30.696471 # uc context validated.
1461 11:44:30.696614 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1462 11:44:30.696756 # Handled SIG_COPYCTX
1463 11:44:30.696898 # Got expected size 1120 and VL 32
1464 11:44:30.697067 # Testing VL 16
1465 11:44:30.697244 # uc context validated.
1466 11:44:30.697395 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1467 11:44:30.697523 # Handled SIG_COPYCTX
1468 11:44:30.697653 # Got expected size 576 and VL 16
1469 11:44:30.697780 # ==>> completed. PASS(1)
1470 11:44:30.697905 # # SVE registers :: Check that we get the right SVE registers reported
1471 11:44:30.698064 ok 24 selftests: arm64: sve_regs
1472 11:44:30.742697 # selftests: arm64: sve_vl
1473 11:44:30.796728 # Registered handlers for all signals.
1474 11:44:30.796983 # Detected MINSTKSIGSZ:10000
1475 11:44:30.797290 # Required Features: [ SVE ] supported
1476 11:44:30.797466 # Incompatible Features: [] absent
1477 11:44:30.797600 # Testcase initialized.
1478 11:44:30.797744 # uc context validated.
1479 11:44:30.797871 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1480 11:44:30.797998 # Handled SIG_COPYCTX
1481 11:44:30.798124 # got expected VL 64
1482 11:44:30.798248 # ==>> completed. PASS(1)
1483 11:44:30.798396 # # SVE VL :: Check that we get the right SVE VL reported
1484 11:44:30.807178 ok 25 selftests: arm64: sve_vl
1485 11:44:30.858165 # selftests: arm64: za_no_regs
1486 11:44:30.923085 # Registered handlers for all signals.
1487 11:44:30.923295 # Detected MINSTKSIGSZ:10000
1488 11:44:30.923388 # Required Features: [ SME ] supported
1489 11:44:30.923477 # Incompatible Features: [] absent
1490 11:44:30.923590 # Testcase initialized.
1491 11:44:30.925355 # Testing VL 256
1492 11:44:30.925680 # uc context validated.
1493 11:44:30.925778 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1494 11:44:30.925882 # Handled SIG_COPYCTX
1495 11:44:30.925974 # Got expected size 16 and VL 256
1496 11:44:30.926061 # Testing VL 128
1497 11:44:30.926148 # uc context validated.
1498 11:44:30.926250 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1499 11:44:30.926341 # Handled SIG_COPYCTX
1500 11:44:30.926428 # Got expected size 16 and VL 128
1501 11:44:30.926515 # Testing VL 64
1502 11:44:30.926601 # uc context validated.
1503 11:44:30.926704 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1504 11:44:30.926793 # Handled SIG_COPYCTX
1505 11:44:30.926881 # Got expected size 16 and VL 64
1506 11:44:30.926984 # Testing VL 32
1507 11:44:30.927074 # uc context validated.
1508 11:44:30.927157 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1509 11:44:30.927244 # Handled SIG_COPYCTX
1510 11:44:30.927345 # Got expected size 16 and VL 32
1511 11:44:30.927435 # Testing VL 16
1512 11:44:30.934438 # uc context validated.
1513 11:44:30.934873 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1514 11:44:30.934973 # Handled SIG_COPYCTX
1515 11:44:30.935061 # Got expected size 16 and VL 16
1516 11:44:30.935149 # ==>> completed. PASS(1)
1517 11:44:30.935234 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1518 11:44:30.935737 ok 26 selftests: arm64: za_no_regs
1519 11:44:30.986327 # selftests: arm64: za_regs
1520 11:44:31.162072 # Registered handlers for all signals.
1521 11:44:31.162323 # Detected MINSTKSIGSZ:10000
1522 11:44:31.162700 # Required Features: [ SME ] supported
1523 11:44:31.162804 # Incompatible Features: [] absent
1524 11:44:31.162892 # Testcase initialized.
1525 11:44:31.162978 # Testing VL 256
1526 11:44:31.163066 # Validating EXTRA...
1527 11:44:31.163148 # uc context validated.
1528 11:44:31.163233 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1529 11:44:31.163317 # Handled SIG_COPYCTX
1530 11:44:31.163422 # Got expected size 65552 and VL 256
1531 11:44:31.163512 # Testing VL 128
1532 11:44:31.163605 # Validating EXTRA...
1533 11:44:31.163694 # uc context validated.
1534 11:44:31.163779 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1535 11:44:31.163864 # Handled SIG_COPYCTX
1536 11:44:31.163949 # Got expected size 16400 and VL 128
1537 11:44:31.164057 # Testing VL 64
1538 11:44:31.164144 # Validating EXTRA...
1539 11:44:31.164227 # uc context validated.
1540 11:44:31.164312 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1541 11:44:31.164396 # Handled SIG_COPYCTX
1542 11:44:31.164480 # Got expected size 4112 and VL 64
1543 11:44:31.164581 # Testing VL 32
1544 11:44:31.164665 # uc context validated.
1545 11:44:31.164798 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1546 11:44:31.164895 # Handled SIG_COPYCTX
1547 11:44:31.164999 # Got expected size 1040 and VL 32
1548 11:44:31.165087 # Testing VL 16
1549 11:44:31.165170 # uc context validated.
1550 11:44:31.165253 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1551 11:44:31.165333 # Handled SIG_COPYCTX
1552 11:44:31.165431 # Got expected size 272 and VL 16
1553 11:44:31.165516 # ==>> completed. PASS(1)
1554 11:44:31.165598 # # ZA register :: Check that we get the right ZA registers reported
1555 11:44:31.175748 ok 27 selftests: arm64: za_regs
1556 11:44:31.250995 # selftests: arm64: pac
1557 11:44:31.428687 # TAP version 13
1558 11:44:31.429046 # 1..7
1559 11:44:31.429258 # # Starting 7 tests from 1 test cases.
1560 11:44:31.429729 # # RUN global.corrupt_pac ...
1561 11:44:31.429932 # # OK global.corrupt_pac
1562 11:44:31.430073 # ok 1 global.corrupt_pac
1563 11:44:31.430206 # # RUN global.pac_instructions_not_nop ...
1564 11:44:31.430356 # # OK global.pac_instructions_not_nop
1565 11:44:31.430482 # ok 2 global.pac_instructions_not_nop
1566 11:44:31.430602 # # RUN global.pac_instructions_not_nop_generic ...
1567 11:44:31.430718 # # OK global.pac_instructions_not_nop_generic
1568 11:44:31.430888 # ok 3 global.pac_instructions_not_nop_generic
1569 11:44:31.431050 # # RUN global.single_thread_different_keys ...
1570 11:44:31.431198 # # OK global.single_thread_different_keys
1571 11:44:31.431347 # ok 4 global.single_thread_different_keys
1572 11:44:31.431488 # # RUN global.exec_changed_keys ...
1573 11:44:31.431631 # # OK global.exec_changed_keys
1574 11:44:31.431773 # ok 5 global.exec_changed_keys
1575 11:44:31.431913 # # RUN global.context_switch_keep_keys ...
1576 11:44:31.432055 # # OK global.context_switch_keep_keys
1577 11:44:31.432198 # ok 6 global.context_switch_keep_keys
1578 11:44:31.432338 # # RUN global.context_switch_keep_keys_generic ...
1579 11:44:31.432480 # # OK global.context_switch_keep_keys_generic
1580 11:44:31.432663 # ok 7 global.context_switch_keep_keys_generic
1581 11:44:31.432798 # # PASSED: 7 / 7 tests passed.
1582 11:44:31.432941 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1583 11:44:31.441308 ok 28 selftests: arm64: pac
1584 11:44:31.493856 # selftests: arm64: fp-stress
1585 11:44:48.566702 # TAP version 13
1586 11:44:48.567022 # 1..27
1587 11:44:48.567485 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1588 11:44:48.567815 # # Will run for 10s
1589 11:44:48.567995 # # Started FPSIMD-0-0
1590 11:44:48.568149 # # Started SVE-VL-256-0
1591 11:44:48.568355 # # Started SVE-VL-240-0
1592 11:44:48.568518 # # Started SVE-VL-224-0
1593 11:44:48.568680 # # Started SVE-VL-208-0
1594 11:44:48.568844 # # Started SVE-VL-192-0
1595 11:44:48.569013 # # Started SVE-VL-176-0
1596 11:44:48.569172 # # Started SVE-VL-160-0
1597 11:44:48.569408 # # Started SVE-VL-144-0
1598 11:44:48.569593 # # Started SVE-VL-128-0
1599 11:44:48.569754 # # Started SVE-VL-112-0
1600 11:44:48.569914 # # Started SVE-VL-96-0
1601 11:44:48.570041 # # Started SVE-VL-80-0
1602 11:44:48.570158 # # Started SVE-VL-64-0
1603 11:44:48.570273 # # Started SVE-VL-48-0
1604 11:44:48.570387 # # Started SVE-VL-32-0
1605 11:44:48.570501 # # Started SVE-VL-16-0
1606 11:44:48.570617 # # Started SSVE-VL-256-0
1607 11:44:48.570730 # # Started ZA-VL-256-0
1608 11:44:48.570845 # # Started SSVE-VL-128-0
1609 11:44:48.570959 # # Started ZA-VL-128-0
1610 11:44:48.571072 # # Started SSVE-VL-64-0
1611 11:44:48.571185 # # Started ZA-VL-64-0
1612 11:44:48.571300 # # Started SSVE-VL-32-0
1613 11:44:48.571413 # # Started ZA-VL-32-0
1614 11:44:48.571526 # # Started SSVE-VL-16-0
1615 11:44:48.571648 # # Started ZA-VL-16-0
1616 11:44:48.571808 # # SVE-VL-256-0: Vector length: 2048 bits
1617 11:44:48.571936 # # SVE-VL-256-0: PID: 913
1618 11:44:48.572049 # # SVE-VL-240-0: Vector length: 1920 bits
1619 11:44:48.572162 # # SVE-VL-240-0: PID: 914
1620 11:44:48.572273 # # SVE-VL-224-0: Vector length: 1792 bits
1621 11:44:48.572385 # # SVE-VL-224-0: PID: 915
1622 11:44:48.572496 # # SVE-VL-192-0: Vector length: 1536 bits
1623 11:44:48.572608 # # SVE-VL-192-0: PID: 917
1624 11:44:48.575874 # # FPSIMD-0-0: Vector length: 128 bits
1625 11:44:48.575996 # # FPSIMD-0-0: PID: 912
1626 11:44:48.576080 # # SVE-VL-208-0: Vector length: 1664 bits
1627 11:44:48.576376 # # SVE-VL-208-0: PID: 916
1628 11:44:48.576497 # # SVE-VL-112-0: Vector length: 896 bits
1629 11:44:48.576585 # # SVE-VL-112-0: PID: 922
1630 11:44:48.576673 # # SVE-VL-144-0: Vector length: 1152 bits
1631 11:44:48.576757 # # SVE-VL-144-0: PID: 920
1632 11:44:48.576841 # # SVE-VL-160-0: Vector length: 1280 bits
1633 11:44:48.576946 # # SVE-VL-160-0: PID: 919
1634 11:44:48.577034 # # SVE-VL-128-0: Vector length: 1024 bits
1635 11:44:48.577115 # # SVE-VL-128-0: PID: 921
1636 11:44:48.577195 # # SVE-VL-96-0: Vector length: 768 bits
1637 11:44:48.577279 # # SVE-VL-96-0: PID: 923
1638 11:44:48.577362 # # SVE-VL-176-0: Vector length: 1408 bits
1639 11:44:48.577446 # # SVE-VL-176-0: PID: 918
1640 11:44:48.577548 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1641 11:44:48.577636 # # ZA-VL-256-0: PID: 930
1642 11:44:48.577729 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1643 11:44:48.577813 # # SVE-VL-16-0: Vector length: 128 bits
1644 11:44:48.577897 # # SVE-VL-16-0: PID: 928
1645 11:44:48.577980 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1646 11:44:48.580201 # # SSVE-VL-128-0: PID: 931
1647 11:44:48.580315 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1648 11:44:48.580419 # # SSVE-VL-256-0: PID: 929
1649 11:44:48.580521 # # SVE-VL-48-0: Vector length: 384 bits
1650 11:44:48.580609 # # SVE-VL-48-0: PID: 926
1651 11:44:48.580709 # # ZA-VL-128-0: PID: 932
1652 11:44:48.581216 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1653 11:44:48.581318 # # SSVE-VL-32-0: PID: 935
1654 11:44:48.581599 # # SVE-VL-32-0: Vector length: 256 bits
1655 11:44:48.581695 # # SVE-VL-32-0: PID: 927
1656 11:44:48.581774 # # SVE-VL-64-0: Vector length: 512 bits
1657 11:44:48.582754 # # SVE-VL-64-0: PID: 925
1658 11:44:48.583270 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1659 11:44:48.583410 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1660 11:44:48.583532 # # ZA-VL-32-0: PID: 936
1661 11:44:48.583667 # # SSVE-VL-16-0: PID: 937
1662 11:44:48.583865 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1663 11:44:48.583949 # # SVE-VL-80-0: Vector length: 640 bits
1664 11:44:48.584022 # # SVE-VL-80-0: PID: 924
1665 11:44:48.584109 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1666 11:44:48.584181 # # SSVE-VL-64-0: PID: 933
1667 11:44:48.584249 # # ZA-VL-64-0: PID: 934
1668 11:44:48.584316 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1669 11:44:48.584385 # # ZA-VL-16-0: PID: 938
1670 11:44:48.584453 # # Finishing up...
1671 11:44:48.584527 # ok 1 FPSIMD-0-0
1672 11:44:48.584605 # ok 2 SVE-VL-256-0
1673 11:44:48.584680 # ok 3 SVE-VL-240-0
1674 11:44:48.584772 # ok 4 SVE-VL-224-0
1675 11:44:48.584851 # ok 5 SVE-VL-208-0
1676 11:44:48.584922 # ok 6 SVE-VL-192-0
1677 11:44:48.584990 # ok 7 SVE-VL-176-0
1678 11:44:48.585056 # ok 8 SVE-VL-160-0
1679 11:44:48.585124 # ok 9 SVE-VL-144-0
1680 11:44:48.585192 # ok 10 SVE-VL-128-0
1681 11:44:48.585259 # ok 11 SVE-VL-112-0
1682 11:44:48.585327 # ok 12 SVE-VL-96-0
1683 11:44:48.585395 # ok 13 SVE-VL-80-0
1684 11:44:48.585462 # ok 14 SVE-VL-64-0
1685 11:44:48.585532 # ok 15 SVE-VL-48-0
1686 11:44:48.585599 # ok 16 SVE-VL-32-0
1687 11:44:48.585697 # ok 17 SVE-VL-16-0
1688 11:44:48.585774 # ok 18 SSVE-VL-256-0
1689 11:44:48.585867 # ok 19 ZA-VL-256-0
1690 11:44:48.585946 # ok 20 SSVE-VL-128-0
1691 11:44:48.586022 # ok 21 ZA-VL-128-0
1692 11:44:48.586092 # ok 22 SSVE-VL-64-0
1693 11:44:48.586163 # ok 23 ZA-VL-64-0
1694 11:44:48.586232 # ok 24 SSVE-VL-32-0
1695 11:44:48.586299 # ok 25 ZA-VL-32-0
1696 11:44:48.586374 # ok 26 SSVE-VL-16-0
1697 11:44:48.586453 # ok 27 ZA-VL-16-0
1698 11:44:48.586530 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=3071, signals=9
1699 11:44:48.589040 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=777, signals=9
1700 11:44:48.589465 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=4403, signals=9
1701 11:44:48.606658 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=7815, signals=9
1702 11:44:48.607203 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=12216, signals=9
1703 11:44:48.607316 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=11108, signals=9
1704 11:44:48.607409 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=4143, signals=9
1705 11:44:48.607515 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=2692, signals=9
1706 11:44:48.607603 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=1074, signals=9
1707 11:44:48.699726 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=3731, signals=9
1708 11:44:48.700219 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=2310, signals=9
1709 11:44:48.700332 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=2723, signals=9
1710 11:44:48.700439 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=5840, signals=9
1711 11:44:48.700543 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=1267, signals=9
1712 11:44:48.700645 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=855, signals=9
1713 11:44:48.701000 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=2916, signals=9
1714 11:44:48.701198 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=6734, signals=9
1715 11:44:48.701358 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=5721, signals=9
1716 11:44:48.740878 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=3033, signals=9
1717 11:44:48.741449 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=229, signals=9
1718 11:44:48.741612 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=4292, signals=9
1719 11:44:48.741755 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2485, signals=9
1720 11:44:48.742412 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=3936, signals=9
1721 11:44:48.742843 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=2853, signals=9
1722 11:44:48.742977 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=4907, signals=9
1723 11:44:48.743088 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=8806, signals=9
1724 11:44:48.743186 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=3406, signals=9
1725 11:44:48.743269 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1726 11:44:48.764083 ok 29 selftests: arm64: fp-stress
1727 11:44:48.971916 # selftests: arm64: sve-ptrace
1728 11:44:49.146554 # TAP version 13
1729 11:44:49.146806 # 1..4104
1730 11:44:49.147129 # # Parent is 955, child is 956
1731 11:44:49.147231 # ok 1 SVE FPSIMD set via SVE: 0
1732 11:44:49.147318 # ok 2 SVE get_fpsimd() gave same state
1733 11:44:49.147409 # ok 3 SVE SVE_PT_VL_INHERIT set
1734 11:44:49.147493 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1735 11:44:49.147577 # ok 5 Set SVE VL 16
1736 11:44:49.147662 # ok 6 Set and get SVE data for VL 16
1737 11:44:49.147763 # ok 7 Set and get FPSIMD data for SVE VL 16
1738 11:44:49.147851 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1739 11:44:49.147935 # ok 9 Set SVE VL 32
1740 11:44:49.148019 # ok 10 Set and get SVE data for VL 32
1741 11:44:49.148111 # ok 11 Set and get FPSIMD data for SVE VL 32
1742 11:44:49.148212 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1743 11:44:49.148300 # ok 13 Set SVE VL 48
1744 11:44:49.148382 # ok 14 Set and get SVE data for VL 48
1745 11:44:49.148465 # ok 15 Set and get FPSIMD data for SVE VL 48
1746 11:44:49.148566 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1747 11:44:49.148653 # ok 17 Set SVE VL 64
1748 11:44:49.148736 # ok 18 Set and get SVE data for VL 64
1749 11:44:49.148838 # ok 19 Set and get FPSIMD data for SVE VL 64
1750 11:44:49.148924 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1751 11:44:49.149010 # ok 21 Set SVE VL 80
1752 11:44:49.154085 # ok 22 Set and get SVE data for VL 80
1753 11:44:49.154533 # ok 23 Set and get FPSIMD data for SVE VL 80
1754 11:44:49.154642 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1755 11:44:49.154732 # ok 25 Set SVE VL 96
1756 11:44:49.154818 # ok 26 Set and get SVE data for VL 96
1757 11:44:49.154921 # ok 27 Set and get FPSIMD data for SVE VL 96
1758 11:44:49.155009 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1759 11:44:49.155101 # ok 29 Set SVE VL 112
1760 11:44:49.155188 # ok 30 Set and get SVE data for VL 112
1761 11:44:49.155273 # ok 31 Set and get FPSIMD data for SVE VL 112
1762 11:44:49.155375 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1763 11:44:49.155462 # ok 33 Set SVE VL 128
1764 11:44:49.155546 # ok 34 Set and get SVE data for VL 128
1765 11:44:49.155629 # ok 35 Set and get FPSIMD data for SVE VL 128
1766 11:44:49.155727 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1767 11:44:49.155817 # ok 37 Set SVE VL 144
1768 11:44:49.155920 # ok 38 Set and get SVE data for VL 144
1769 11:44:49.156011 # ok 39 Set and get FPSIMD data for SVE VL 144
1770 11:44:49.156114 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1771 11:44:49.156201 # ok 41 Set SVE VL 160
1772 11:44:49.156284 # ok 42 Set and get SVE data for VL 160
1773 11:44:49.156367 # ok 43 Set and get FPSIMD data for SVE VL 160
1774 11:44:49.156465 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1775 11:44:49.156551 # ok 45 Set SVE VL 176
1776 11:44:49.156635 # ok 46 Set and get SVE data for VL 176
1777 11:44:49.156716 # ok 47 Set and get FPSIMD data for SVE VL 176
1778 11:44:49.156817 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1779 11:44:49.156905 # ok 49 Set SVE VL 192
1780 11:44:49.156988 # ok 50 Set and get SVE data for VL 192
1781 11:44:49.157071 # ok 51 Set and get FPSIMD data for SVE VL 192
1782 11:44:49.162661 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1783 11:44:49.162855 # ok 53 Set SVE VL 208
1784 11:44:49.163013 # ok 54 Set and get SVE data for VL 208
1785 11:44:49.163198 # ok 55 Set and get FPSIMD data for SVE VL 208
1786 11:44:49.163360 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1787 11:44:49.163500 # ok 57 Set SVE VL 224
1788 11:44:49.163641 # ok 58 Set and get SVE data for VL 224
1789 11:44:49.163786 # ok 59 Set and get FPSIMD data for SVE VL 224
1790 11:44:49.163987 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1791 11:44:49.164133 # ok 61 Set SVE VL 240
1792 11:44:49.164288 # ok 62 Set and get SVE data for VL 240
1793 11:44:49.164444 # ok 63 Set and get FPSIMD data for SVE VL 240
1794 11:44:49.164596 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1795 11:44:49.164753 # ok 65 Set SVE VL 256
1796 11:44:49.164899 # ok 66 Set and get SVE data for VL 256
1797 11:44:49.165020 # ok 67 Set and get FPSIMD data for SVE VL 256
1798 11:44:49.165137 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1799 11:44:49.165278 # ok 69 Set SVE VL 272
1800 11:44:49.165397 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1801 11:44:49.165540 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1802 11:44:49.165726 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1803 11:44:49.165933 # ok 73 Set SVE VL 288
1804 11:44:49.166118 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1805 11:44:49.166303 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1806 11:44:49.166487 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1807 11:44:49.166631 # ok 77 Set SVE VL 304
1808 11:44:49.170708 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1809 11:44:49.171156 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1810 11:44:49.171267 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1811 11:44:49.171359 # ok 81 Set SVE VL 320
1812 11:44:49.171469 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1813 11:44:49.171562 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1814 11:44:49.171664 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1815 11:44:49.171752 # ok 85 Set SVE VL 336
1816 11:44:49.171853 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1817 11:44:49.171943 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1818 11:44:49.172047 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1819 11:44:49.172136 # ok 89 Set SVE VL 352
1820 11:44:49.172239 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1821 11:44:49.172343 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1822 11:44:49.172690 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1823 11:44:49.172896 # ok 93 Set SVE VL 368
1824 11:44:49.173040 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1825 11:44:49.173168 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1826 11:44:49.173317 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1827 11:44:49.173662 # ok 97 Set SVE VL 384
1828 11:44:49.173773 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1829 11:44:49.174027 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1830 11:44:49.174123 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1831 11:44:49.174202 # ok 101 Set SVE VL 400
1832 11:44:49.175302 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1833 11:44:49.175761 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1834 11:44:49.175952 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1835 11:44:49.176121 # ok 105 Set SVE VL 416
1836 11:44:49.176246 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1837 11:44:49.176393 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1838 11:44:49.176516 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1839 11:44:49.176634 # ok 109 Set SVE VL 432
1840 11:44:49.176751 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1841 11:44:49.176867 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1842 11:44:49.176983 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1843 11:44:49.177123 # ok 113 Set SVE VL 448
1844 11:44:49.177244 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1845 11:44:49.177361 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1846 11:44:49.177475 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1847 11:44:49.187755 # ok 117 Set SVE VL 464
1848 11:44:49.188202 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1849 11:44:49.188311 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1850 11:44:49.188404 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1851 11:44:49.188493 # ok 121 Set SVE VL 480
1852 11:44:49.188579 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1853 11:44:49.188681 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1854 11:44:49.188775 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1855 11:44:49.188857 # ok 125 Set SVE VL 496
1856 11:44:49.188949 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1857 11:44:49.192363 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1858 11:44:49.192837 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1859 11:44:49.193047 # ok 129 Set SVE VL 512
1860 11:44:49.193301 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1861 11:44:49.193541 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1862 11:44:49.193774 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1863 11:44:49.193930 # ok 133 Set SVE VL 528
1864 11:44:49.194098 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1865 11:44:49.194265 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1866 11:44:49.194417 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1867 11:44:49.194557 # ok 137 Set SVE VL 544
1868 11:44:49.194683 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1869 11:44:49.194814 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1870 11:44:49.194943 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1871 11:44:49.195100 # ok 141 Set SVE VL 560
1872 11:44:49.195313 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1873 11:44:49.195494 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1874 11:44:49.195668 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1875 11:44:49.195837 # ok 145 Set SVE VL 576
1876 11:44:49.196009 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1877 11:44:49.196167 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1878 11:44:49.196320 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1879 11:44:49.196456 # ok 149 Set SVE VL 592
1880 11:44:49.196582 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1881 11:44:49.196733 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1882 11:44:49.196895 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1883 11:44:49.197033 # ok 153 Set SVE VL 608
1884 11:44:49.197180 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1885 11:44:49.197320 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1886 11:44:49.197516 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1887 11:44:49.197696 # ok 157 Set SVE VL 624
1888 11:44:49.197858 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1889 11:44:49.197983 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1890 11:44:49.198101 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1891 11:44:49.198220 # ok 161 Set SVE VL 640
1892 11:44:49.198338 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1893 11:44:49.198454 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1894 11:44:49.198571 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1895 11:44:49.198688 # ok 165 Set SVE VL 656
1896 11:44:49.198804 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1897 11:44:49.198920 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1898 11:44:49.199036 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1899 11:44:49.199153 # ok 169 Set SVE VL 672
1900 11:44:49.199270 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1901 11:44:49.199416 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1902 11:44:49.199762 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1903 11:44:49.211119 # ok 173 Set SVE VL 688
1904 11:44:49.211475 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1905 11:44:49.211892 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1906 11:44:49.212000 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1907 11:44:49.212090 # ok 177 Set SVE VL 704
1908 11:44:49.212181 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1909 11:44:49.212268 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1910 11:44:49.212355 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1911 11:44:49.212441 # ok 181 Set SVE VL 720
1912 11:44:49.212547 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1913 11:44:49.212636 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1914 11:44:49.212723 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1915 11:44:49.212810 # ok 185 Set SVE VL 736
1916 11:44:49.212888 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1917 11:44:49.212979 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1918 11:44:49.213057 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1919 11:44:49.213131 # ok 189 Set SVE VL 752
1920 11:44:49.213734 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1921 11:44:49.214023 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1922 11:44:49.214126 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1923 11:44:49.214213 # ok 193 Set SVE VL 768
1924 11:44:49.214321 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1925 11:44:49.214411 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1926 11:44:49.214510 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1927 11:44:49.214610 # ok 197 Set SVE VL 784
1928 11:44:49.214915 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1929 11:44:49.215025 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1930 11:44:49.215132 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1931 11:44:49.215235 # ok 201 Set SVE VL 800
1932 11:44:49.215338 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1933 11:44:49.215639 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1934 11:44:49.215743 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1935 11:44:49.215846 # ok 205 Set SVE VL 816
1936 11:44:49.215935 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1937 11:44:49.216034 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1938 11:44:49.216135 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1939 11:44:49.216222 # ok 209 Set SVE VL 832
1940 11:44:49.216321 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1941 11:44:49.216420 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1942 11:44:49.216705 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1943 11:44:49.216809 # ok 213 Set SVE VL 848
1944 11:44:49.216912 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1945 11:44:49.226897 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1946 11:44:49.227346 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1947 11:44:49.227453 # ok 217 Set SVE VL 864
1948 11:44:49.227545 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1949 11:44:49.227630 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1950 11:44:49.227714 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1951 11:44:49.227822 # ok 221 Set SVE VL 880
1952 11:44:49.227914 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1953 11:44:49.227999 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1954 11:44:49.228085 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1955 11:44:49.228185 # ok 225 Set SVE VL 896
1956 11:44:49.228276 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1957 11:44:49.228609 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1958 11:44:49.228714 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1959 11:44:49.228799 # ok 229 Set SVE VL 912
1960 11:44:49.228882 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1961 11:44:49.228980 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1962 11:44:49.229508 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1963 11:44:49.229818 # ok 233 Set SVE VL 928
1964 11:44:49.229925 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1965 11:44:49.230014 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1966 11:44:49.230114 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1967 11:44:49.230200 # ok 237 Set SVE VL 944
1968 11:44:49.230297 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1969 11:44:49.230397 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1970 11:44:49.230483 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1971 11:44:49.230580 # ok 241 Set SVE VL 960
1972 11:44:49.230678 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1973 11:44:49.230764 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1974 11:44:49.230861 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1975 11:44:49.230947 # ok 245 Set SVE VL 976
1976 11:44:49.231040 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1977 11:44:49.231136 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1978 11:44:49.231432 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1979 11:44:49.231539 # ok 249 Set SVE VL 992
1980 11:44:49.231625 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1981 11:44:49.231727 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1982 11:44:49.231815 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1983 11:44:49.231917 # ok 253 Set SVE VL 1008
1984 11:44:49.232018 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1985 11:44:49.232121 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1986 11:44:49.232236 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1987 11:44:49.232340 # ok 257 Set SVE VL 1024
1988 11:44:49.232453 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1989 11:44:49.232763 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1990 11:44:49.232867 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1991 11:44:49.232967 # ok 261 Set SVE VL 1040
1992 11:44:49.242221 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1993 11:44:49.242542 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1994 11:44:49.242938 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1995 11:44:49.243046 # ok 265 Set SVE VL 1056
1996 11:44:49.243134 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1997 11:44:49.243219 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1998 11:44:49.243302 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1999 11:44:49.243392 # ok 269 Set SVE VL 1072
2000 11:44:49.243474 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
2001 11:44:49.243558 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
2002 11:44:49.243660 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2003 11:44:49.243746 # ok 273 Set SVE VL 1088
2004 11:44:49.243831 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2005 11:44:49.243915 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2006 11:44:49.244001 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2007 11:44:49.244086 # ok 277 Set SVE VL 1104
2008 11:44:49.244190 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2009 11:44:49.244279 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2010 11:44:49.244367 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2011 11:44:49.244470 # ok 281 Set SVE VL 1120
2012 11:44:49.244556 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2013 11:44:49.244656 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2014 11:44:49.244756 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2015 11:44:49.244842 # ok 285 Set SVE VL 1136
2016 11:44:49.253483 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2017 11:44:49.253780 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2018 11:44:49.254084 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2019 11:44:49.254183 # ok 289 Set SVE VL 1152
2020 11:44:49.254271 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2021 11:44:49.254357 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2022 11:44:49.254444 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2023 11:44:49.256487 # ok 293 Set SVE VL 1168
2024 11:44:49.256599 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2025 11:44:49.256705 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2026 11:44:49.256810 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2027 11:44:49.257503 # ok 297 Set SVE VL 1184
2028 11:44:49.257797 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2029 11:44:49.257897 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2030 11:44:49.258001 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2031 11:44:49.258089 # ok 301 Set SVE VL 1200
2032 11:44:49.258189 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2033 11:44:49.258280 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2034 11:44:49.258380 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2035 11:44:49.258707 # ok 305 Set SVE VL 1216
2036 11:44:49.258875 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2037 11:44:49.259250 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2038 11:44:49.259427 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2039 11:44:49.259577 # ok 309 Set SVE VL 1232
2040 11:44:49.259738 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2041 11:44:49.259906 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2042 11:44:49.260076 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2043 11:44:49.260268 # ok 313 Set SVE VL 1248
2044 11:44:49.260432 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2045 11:44:49.260577 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2046 11:44:49.260730 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2047 11:44:49.260868 # ok 317 Set SVE VL 1264
2048 11:44:49.260988 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2049 11:44:49.261103 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2050 11:44:49.261217 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2051 11:44:49.261332 # ok 321 Set SVE VL 1280
2052 11:44:49.261444 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2053 11:44:49.261586 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2054 11:44:49.261723 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2055 11:44:49.261838 # ok 325 Set SVE VL 1296
2056 11:44:49.261954 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2057 11:44:49.269249 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2058 11:44:49.269843 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2059 11:44:49.270066 # ok 329 Set SVE VL 1312
2060 11:44:49.270270 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2061 11:44:49.270435 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2062 11:44:49.270569 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2063 11:44:49.270695 # ok 333 Set SVE VL 1328
2064 11:44:49.270846 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2065 11:44:49.270976 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2066 11:44:49.271105 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2067 11:44:49.271223 # ok 337 Set SVE VL 1344
2068 11:44:49.271339 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2069 11:44:49.271459 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2070 11:44:49.271578 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2071 11:44:49.271721 # ok 341 Set SVE VL 1360
2072 11:44:49.271896 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2073 11:44:49.272024 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2074 11:44:49.272143 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2075 11:44:49.272258 # ok 345 Set SVE VL 1376
2076 11:44:49.272375 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2077 11:44:49.272491 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2078 11:44:49.272605 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2079 11:44:49.272721 # ok 349 Set SVE VL 1392
2080 11:44:49.272862 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2081 11:44:49.272986 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2082 11:44:49.273103 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2083 11:44:49.273219 # ok 353 Set SVE VL 1408
2084 11:44:49.273337 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2085 11:44:49.273452 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2086 11:44:49.277865 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2087 11:44:49.278324 # ok 357 Set SVE VL 1424
2088 11:44:49.278516 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2089 11:44:49.278701 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2090 11:44:49.278913 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2091 11:44:49.279054 # ok 361 Set SVE VL 1440
2092 11:44:49.279197 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2093 11:44:49.279341 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2094 11:44:49.279482 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2095 11:44:49.279663 # ok 365 Set SVE VL 1456
2096 11:44:49.279896 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2097 11:44:49.280056 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2098 11:44:49.280200 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2099 11:44:49.280345 # ok 369 Set SVE VL 1472
2100 11:44:49.280486 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2101 11:44:49.280626 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2102 11:44:49.280768 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2103 11:44:49.280945 # ok 373 Set SVE VL 1488
2104 11:44:49.281079 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2105 11:44:49.281220 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2106 11:44:49.281364 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2107 11:44:49.281504 # ok 377 Set SVE VL 1504
2108 11:44:49.281656 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2109 11:44:49.281801 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2110 11:44:49.281944 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2111 11:44:49.285771 # ok 381 Set SVE VL 1520
2112 11:44:49.286245 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2113 11:44:49.286354 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2114 11:44:49.286445 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2115 11:44:49.286534 # ok 385 Set SVE VL 1536
2116 11:44:49.286636 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2117 11:44:49.286942 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2118 11:44:49.287145 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2119 11:44:49.287347 # ok 389 Set SVE VL 1552
2120 11:44:49.287632 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2121 11:44:49.287888 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2122 11:44:49.288087 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2123 11:44:49.288253 # ok 393 Set SVE VL 1568
2124 11:44:49.288459 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2125 11:44:49.288666 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2126 11:44:49.288836 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2127 11:44:49.289032 # ok 397 Set SVE VL 1584
2128 11:44:49.289245 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2129 11:44:49.289391 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2130 11:44:49.289536 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2131 11:44:49.289693 # ok 401 Set SVE VL 1600
2132 11:44:49.289837 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2133 11:44:49.289979 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2134 11:44:49.290122 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2135 11:44:49.290264 # ok 405 Set SVE VL 1616
2136 11:44:49.293599 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2137 11:44:49.294091 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2138 11:44:49.294293 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2139 11:44:49.294494 # ok 409 Set SVE VL 1632
2140 11:44:49.294711 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2141 11:44:49.294974 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2142 11:44:49.295176 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2143 11:44:49.295395 # ok 413 Set SVE VL 1648
2144 11:44:49.295576 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2145 11:44:49.295745 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2146 11:44:49.295954 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2147 11:44:49.296176 # ok 417 Set SVE VL 1664
2148 11:44:49.296355 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2149 11:44:49.296518 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2150 11:44:49.296720 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2151 11:44:49.296879 # ok 421 Set SVE VL 1680
2152 11:44:49.297001 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2153 11:44:49.297118 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2154 11:44:49.297232 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2155 11:44:49.297351 # ok 425 Set SVE VL 1696
2156 11:44:49.297466 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2157 11:44:49.297581 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2158 11:44:49.297711 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2159 11:44:49.297826 # ok 429 Set SVE VL 1712
2160 11:44:49.297939 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2161 11:44:49.298051 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2162 11:44:49.298164 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2163 11:44:49.298277 # ok 433 Set SVE VL 1728
2164 11:44:49.298390 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2165 11:44:49.298503 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2166 11:44:49.298639 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2167 11:44:49.301535 # ok 437 Set SVE VL 1744
2168 11:44:49.301864 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2169 11:44:49.301971 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2170 11:44:49.302055 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2171 11:44:49.302147 # ok 441 Set SVE VL 1760
2172 11:44:49.302227 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2173 11:44:49.302320 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2174 11:44:49.302412 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2175 11:44:49.302492 # ok 445 Set SVE VL 1776
2176 11:44:49.302568 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2177 11:44:49.302657 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2178 11:44:49.302940 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2179 11:44:49.303042 # ok 449 Set SVE VL 1792
2180 11:44:49.303122 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2181 11:44:49.303211 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2182 11:44:49.303290 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2183 11:44:49.303504 # ok 453 Set SVE VL 1808
2184 11:44:49.303696 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2185 11:44:49.303891 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2186 11:44:49.303988 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2187 11:44:49.304067 # ok 457 Set SVE VL 1824
2188 11:44:49.304143 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2189 11:44:49.304237 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2190 11:44:49.304317 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2191 11:44:49.304393 # ok 461 Set SVE VL 1840
2192 11:44:49.304469 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2193 11:44:49.304545 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2194 11:44:49.304636 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2195 11:44:49.304715 # ok 465 Set SVE VL 1856
2196 11:44:49.304791 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2197 11:44:49.304867 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2198 11:44:49.304941 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2199 11:44:49.305014 # ok 469 Set SVE VL 1872
2200 11:44:49.305108 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2201 11:44:49.309744 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2202 11:44:49.310207 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2203 11:44:49.310312 # ok 473 Set SVE VL 1888
2204 11:44:49.310399 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2205 11:44:49.310491 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2206 11:44:49.310570 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2207 11:44:49.310647 # ok 477 Set SVE VL 1904
2208 11:44:49.310723 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2209 11:44:49.310812 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2210 11:44:49.317667 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2211 11:44:49.317868 # ok 481 Set SVE VL 1920
2212 11:44:49.318028 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2213 11:44:49.318225 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2214 11:44:49.318371 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2215 11:44:49.318495 # ok 485 Set SVE VL 1936
2216 11:44:49.318612 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2217 11:44:49.318733 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2218 11:44:49.318880 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2219 11:44:49.319007 # ok 489 Set SVE VL 1952
2220 11:44:49.319129 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2221 11:44:49.319252 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2222 11:44:49.319391 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2223 11:44:49.319596 # ok 493 Set SVE VL 1968
2224 11:44:49.319794 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2225 11:44:49.319994 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2226 11:44:49.320143 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2227 11:44:49.320285 # ok 497 Set SVE VL 1984
2228 11:44:49.320423 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2229 11:44:49.320550 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2230 11:44:49.320672 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2231 11:44:49.320793 # ok 501 Set SVE VL 2000
2232 11:44:49.320909 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2233 11:44:49.321023 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2234 11:44:49.321136 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2235 11:44:49.321278 # ok 505 Set SVE VL 2016
2236 11:44:49.321399 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2237 11:44:49.321513 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2238 11:44:49.321629 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2239 11:44:49.321757 # ok 509 Set SVE VL 2032
2240 11:44:49.321873 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2241 11:44:49.321987 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2242 11:44:49.325569 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2243 11:44:49.325958 # ok 513 Set SVE VL 2048
2244 11:44:49.326095 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2245 11:44:49.326216 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2246 11:44:49.326365 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2247 11:44:49.326515 # ok 517 Set SVE VL 2064
2248 11:44:49.326667 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2249 11:44:49.326822 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2250 11:44:49.327000 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2251 11:44:49.327132 # ok 521 Set SVE VL 2080
2252 11:44:49.327252 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2253 11:44:49.327382 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2254 11:44:49.327528 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2255 11:44:49.327707 # ok 525 Set SVE VL 2096
2256 11:44:49.327878 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2257 11:44:49.328015 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2258 11:44:49.328166 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2259 11:44:49.328296 # ok 529 Set SVE VL 2112
2260 11:44:49.328414 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2261 11:44:49.328531 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2262 11:44:49.328651 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2263 11:44:49.328795 # ok 533 Set SVE VL 2128
2264 11:44:49.328919 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2265 11:44:49.329035 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2266 11:44:49.329152 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2267 11:44:49.329269 # ok 537 Set SVE VL 2144
2268 11:44:49.332192 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2269 11:44:49.332633 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2270 11:44:49.332799 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2271 11:44:49.332931 # ok 541 Set SVE VL 2160
2272 11:44:49.333072 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2273 11:44:49.333193 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2274 11:44:49.333519 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2275 11:44:49.333680 # ok 545 Set SVE VL 2176
2276 11:44:49.333829 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2277 11:44:49.333992 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2278 11:44:49.334185 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2279 11:44:49.334351 # ok 549 Set SVE VL 2192
2280 11:44:49.334511 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2281 11:44:49.334650 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2282 11:44:49.334828 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2283 11:44:49.334976 # ok 553 Set SVE VL 2208
2284 11:44:49.335137 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2285 11:44:49.335292 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2286 11:44:49.335452 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2287 11:44:49.335651 # ok 557 Set SVE VL 2224
2288 11:44:49.336602 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2289 11:44:49.336785 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2290 11:44:49.336922 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2291 11:44:49.337071 # ok 561 Set SVE VL 2240
2292 11:44:49.337233 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2293 11:44:49.337396 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2294 11:44:49.337542 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2295 11:44:49.337691 # ok 565 Set SVE VL 2256
2296 11:44:49.337817 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2297 11:44:49.337945 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2298 11:44:49.338080 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2299 11:44:49.338238 # ok 569 Set SVE VL 2272
2300 11:44:49.338402 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2301 11:44:49.338563 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2302 11:44:49.338718 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2303 11:44:49.338887 # ok 573 Set SVE VL 2288
2304 11:44:49.339043 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2305 11:44:49.339165 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2306 11:44:49.339282 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2307 11:44:49.339428 # ok 577 Set SVE VL 2304
2308 11:44:49.339583 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2309 11:44:49.339704 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2310 11:44:49.339820 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2311 11:44:49.339936 # ok 581 Set SVE VL 2320
2312 11:44:49.340049 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2313 11:44:49.340163 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2314 11:44:49.340276 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2315 11:44:49.340391 # ok 585 Set SVE VL 2336
2316 11:44:49.340506 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2317 11:44:49.340621 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2318 11:44:49.340953 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2319 11:44:49.341063 # ok 589 Set SVE VL 2352
2320 11:44:49.341155 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2321 11:44:49.341241 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2322 11:44:49.341324 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2323 11:44:49.341406 # ok 593 Set SVE VL 2368
2324 11:44:49.341497 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2325 11:44:49.341581 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2326 11:44:49.341675 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2327 11:44:49.341759 # ok 597 Set SVE VL 2384
2328 11:44:49.341842 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2329 11:44:49.341924 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2330 11:44:49.342004 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2331 11:44:49.342086 # ok 601 Set SVE VL 2400
2332 11:44:49.342169 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2333 11:44:49.342251 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2334 11:44:49.342335 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2335 11:44:49.342418 # ok 605 Set SVE VL 2416
2336 11:44:49.342500 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2337 11:44:49.342583 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2338 11:44:49.342667 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2339 11:44:49.342751 # ok 609 Set SVE VL 2432
2340 11:44:49.342833 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2341 11:44:49.342939 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2342 11:44:49.343029 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2343 11:44:49.343113 # ok 613 Set SVE VL 2448
2344 11:44:49.343197 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2345 11:44:49.343283 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2346 11:44:49.343369 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2347 11:44:49.343453 # ok 617 Set SVE VL 2464
2348 11:44:49.343532 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2349 11:44:49.343615 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2350 11:44:49.343698 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2351 11:44:49.343781 # ok 621 Set SVE VL 2480
2352 11:44:49.343864 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2353 11:44:49.343948 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2354 11:44:49.344032 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2355 11:44:49.344115 # ok 625 Set SVE VL 2496
2356 11:44:49.344198 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2357 11:44:49.344300 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2358 11:44:49.344387 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2359 11:44:49.344469 # ok 629 Set SVE VL 2512
2360 11:44:49.344548 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2361 11:44:49.344629 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2362 11:44:49.345377 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2363 11:44:49.345479 # ok 633 Set SVE VL 2528
2364 11:44:49.345563 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2365 11:44:49.345650 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2366 11:44:49.345734 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2367 11:44:49.345813 # ok 637 Set SVE VL 2544
2368 11:44:49.345892 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2369 11:44:49.345974 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2370 11:44:49.346057 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2371 11:44:49.346139 # ok 641 Set SVE VL 2560
2372 11:44:49.346222 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2373 11:44:49.346306 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2374 11:44:49.346389 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2375 11:44:49.346473 # ok 645 Set SVE VL 2576
2376 11:44:49.346556 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2377 11:44:49.346639 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2378 11:44:49.346724 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2379 11:44:49.346808 # ok 649 Set SVE VL 2592
2380 11:44:49.346893 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2381 11:44:49.346978 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2382 11:44:49.347062 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2383 11:44:49.347146 # ok 653 Set SVE VL 2608
2384 11:44:49.347250 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2385 11:44:49.347337 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2386 11:44:49.347420 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2387 11:44:49.347501 # ok 657 Set SVE VL 2624
2388 11:44:49.347583 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2389 11:44:49.347664 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2390 11:44:49.347746 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2391 11:44:49.347830 # ok 661 Set SVE VL 2640
2392 11:44:49.347914 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2393 11:44:49.347997 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2394 11:44:49.348078 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2395 11:44:49.348158 # ok 665 Set SVE VL 2656
2396 11:44:49.348237 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2397 11:44:49.359195 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2398 11:44:49.359634 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2399 11:44:49.359744 # ok 669 Set SVE VL 2672
2400 11:44:49.359826 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2401 11:44:49.359903 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2402 11:44:49.359980 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2403 11:44:49.360076 # ok 673 Set SVE VL 2688
2404 11:44:49.360155 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2405 11:44:49.360231 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2406 11:44:49.360307 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2407 11:44:49.360382 # ok 677 Set SVE VL 2704
2408 11:44:49.360474 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2409 11:44:49.360557 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2410 11:44:49.360634 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2411 11:44:49.360710 # ok 681 Set SVE VL 2720
2412 11:44:49.360799 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2413 11:44:49.360878 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2414 11:44:49.360954 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2415 11:44:49.361374 # ok 685 Set SVE VL 2736
2416 11:44:49.361846 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2417 11:44:49.362053 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2418 11:44:49.362277 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2419 11:44:49.362463 # ok 689 Set SVE VL 2752
2420 11:44:49.362704 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2421 11:44:49.362900 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2422 11:44:49.363096 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2423 11:44:49.363316 # ok 693 Set SVE VL 2768
2424 11:44:49.363500 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2425 11:44:49.363667 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2426 11:44:49.363831 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2427 11:44:49.364038 # ok 697 Set SVE VL 2784
2428 11:44:49.364224 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2429 11:44:49.364451 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2430 11:44:49.364671 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2431 11:44:49.364884 # ok 701 Set SVE VL 2800
2432 11:44:49.365074 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2433 11:44:49.365230 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2434 11:44:49.365384 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2435 11:44:49.365546 # ok 705 Set SVE VL 2816
2436 11:44:49.366109 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2437 11:44:49.366312 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2438 11:44:49.366484 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2439 11:44:49.366690 # ok 709 Set SVE VL 2832
2440 11:44:49.366861 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2441 11:44:49.367064 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2442 11:44:49.367261 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2443 11:44:49.367466 # ok 713 Set SVE VL 2848
2444 11:44:49.367644 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2445 11:44:49.367873 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2446 11:44:49.368102 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2447 11:44:49.368273 # ok 717 Set SVE VL 2864
2448 11:44:49.368434 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2449 11:44:49.368601 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2450 11:44:49.368818 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2451 11:44:49.368989 # ok 721 Set SVE VL 2880
2452 11:44:49.369152 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2453 11:44:49.369366 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2454 11:44:49.369601 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2455 11:44:49.369837 # ok 725 Set SVE VL 2896
2456 11:44:49.370067 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2457 11:44:49.370296 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2458 11:44:49.370508 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2459 11:44:49.370706 # ok 729 Set SVE VL 2912
2460 11:44:49.371189 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2461 11:44:49.371416 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2462 11:44:49.371583 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2463 11:44:49.371721 # ok 733 Set SVE VL 2928
2464 11:44:49.371874 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2465 11:44:49.372022 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2466 11:44:49.372208 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2467 11:44:49.372462 # ok 737 Set SVE VL 2944
2468 11:44:49.372687 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2469 11:44:49.372876 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2470 11:44:49.373063 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2471 11:44:49.373232 # ok 741 Set SVE VL 2960
2472 11:44:49.373390 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2473 11:44:49.373529 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2474 11:44:49.373705 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2475 11:44:49.373886 # ok 745 Set SVE VL 2976
2476 11:44:49.374113 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2477 11:44:49.374302 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2478 11:44:49.374454 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2479 11:44:49.374615 # ok 749 Set SVE VL 2992
2480 11:44:49.374756 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2481 11:44:49.374894 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2482 11:44:49.375038 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2483 11:44:49.375189 # ok 753 Set SVE VL 3008
2484 11:44:49.375333 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2485 11:44:49.375509 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2486 11:44:49.375679 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2487 11:44:49.375812 # ok 757 Set SVE VL 3024
2488 11:44:49.375948 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2489 11:44:49.376095 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2490 11:44:49.376246 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2491 11:44:49.376437 # ok 761 Set SVE VL 3040
2492 11:44:49.376599 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2493 11:44:49.376735 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2494 11:44:49.376860 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2495 11:44:49.376975 # ok 765 Set SVE VL 3056
2496 11:44:49.377090 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2497 11:44:49.377228 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2498 11:44:49.377376 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2499 11:44:49.377526 # ok 769 Set SVE VL 3072
2500 11:44:49.378398 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2501 11:44:49.378587 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2502 11:44:49.378742 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2503 11:44:49.379133 # ok 773 Set SVE VL 3088
2504 11:44:49.379255 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2505 11:44:49.379345 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2506 11:44:49.379431 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2507 11:44:49.379520 # ok 777 Set SVE VL 3104
2508 11:44:49.379614 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2509 11:44:49.379699 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2510 11:44:49.379784 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2511 11:44:49.379868 # ok 781 Set SVE VL 3120
2512 11:44:49.379953 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2513 11:44:49.380038 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2514 11:44:49.380122 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2515 11:44:49.380204 # ok 785 Set SVE VL 3136
2516 11:44:49.380286 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2517 11:44:49.380368 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2518 11:44:49.380449 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2519 11:44:49.380531 # ok 789 Set SVE VL 3152
2520 11:44:49.380613 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2521 11:44:49.380696 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2522 11:44:49.380780 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2523 11:44:49.380863 # ok 793 Set SVE VL 3168
2524 11:44:49.380943 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2525 11:44:49.381026 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2526 11:44:49.381109 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2527 11:44:49.381189 # ok 797 Set SVE VL 3184
2528 11:44:49.381269 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2529 11:44:49.381352 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2530 11:44:49.381435 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2531 11:44:49.381520 # ok 801 Set SVE VL 3200
2532 11:44:49.381602 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2533 11:44:49.381695 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2534 11:44:49.381778 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2535 11:44:49.381861 # ok 805 Set SVE VL 3216
2536 11:44:49.381942 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2537 11:44:49.382021 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2538 11:44:49.382102 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2539 11:44:49.382183 # ok 809 Set SVE VL 3232
2540 11:44:49.382265 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2541 11:44:49.382348 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2542 11:44:49.382431 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2543 11:44:49.382519 # ok 813 Set SVE VL 3248
2544 11:44:49.382607 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2545 11:44:49.382692 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2546 11:44:49.382776 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2547 11:44:49.383073 # ok 817 Set SVE VL 3264
2548 11:44:49.383169 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2549 11:44:49.383256 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2550 11:44:49.383342 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2551 11:44:49.383428 # ok 821 Set SVE VL 3280
2552 11:44:49.383514 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2553 11:44:49.383600 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2554 11:44:49.383684 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2555 11:44:49.383769 # ok 825 Set SVE VL 3296
2556 11:44:49.383853 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2557 11:44:49.383939 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2558 11:44:49.384025 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2559 11:44:49.384109 # ok 829 Set SVE VL 3312
2560 11:44:49.384194 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2561 11:44:49.384277 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2562 11:44:49.384359 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2563 11:44:49.384442 # ok 833 Set SVE VL 3328
2564 11:44:49.384527 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2565 11:44:49.384610 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2566 11:44:49.384695 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2567 11:44:49.384780 # ok 837 Set SVE VL 3344
2568 11:44:49.384865 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2569 11:44:49.384949 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2570 11:44:49.385033 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2571 11:44:49.385118 # ok 841 Set SVE VL 3360
2572 11:44:49.385204 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2573 11:44:49.385289 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2574 11:44:49.385374 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2575 11:44:49.385460 # ok 845 Set SVE VL 3376
2576 11:44:49.385548 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2577 11:44:49.385633 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2578 11:44:49.385723 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2579 11:44:49.385808 # ok 849 Set SVE VL 3392
2580 11:44:49.385892 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2581 11:44:49.385977 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2582 11:44:49.386062 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2583 11:44:49.386147 # ok 853 Set SVE VL 3408
2584 11:44:49.386230 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2585 11:44:49.388430 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2586 11:44:49.388561 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2587 11:44:49.388650 # ok 857 Set SVE VL 3424
2588 11:44:49.388751 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2589 11:44:49.389352 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2590 11:44:49.389746 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2591 11:44:49.389894 # ok 861 Set SVE VL 3440
2592 11:44:49.390021 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2593 11:44:49.390169 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2594 11:44:49.390298 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2595 11:44:49.390423 # ok 865 Set SVE VL 3456
2596 11:44:49.390550 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2597 11:44:49.390653 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2598 11:44:49.390761 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2599 11:44:49.390885 # ok 869 Set SVE VL 3472
2600 11:44:49.390996 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2601 11:44:49.391096 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2602 11:44:49.391188 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2603 11:44:49.391288 # ok 873 Set SVE VL 3488
2604 11:44:49.391424 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2605 11:44:49.391580 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2606 11:44:49.391734 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2607 11:44:49.391895 # ok 877 Set SVE VL 3504
2608 11:44:49.392026 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2609 11:44:49.392166 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2610 11:44:49.392288 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2611 11:44:49.392387 # ok 881 Set SVE VL 3520
2612 11:44:49.392490 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2613 11:44:49.392582 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2614 11:44:49.392687 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2615 11:44:49.392781 # ok 885 Set SVE VL 3536
2616 11:44:49.392883 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2617 11:44:49.393017 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2618 11:44:49.393111 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2619 11:44:49.393199 # ok 889 Set SVE VL 3552
2620 11:44:49.393286 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2621 11:44:49.393373 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2622 11:44:49.393477 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2623 11:44:49.393574 # ok 893 Set SVE VL 3568
2624 11:44:49.393672 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2625 11:44:49.393760 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2626 11:44:49.393864 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2627 11:44:49.393956 # ok 897 Set SVE VL 3584
2628 11:44:49.394043 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2629 11:44:49.394145 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2630 11:44:49.394236 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2631 11:44:49.394323 # ok 901 Set SVE VL 3600
2632 11:44:49.394426 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2633 11:44:49.394516 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2634 11:44:49.394876 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2635 11:44:49.394980 # ok 905 Set SVE VL 3616
2636 11:44:49.395068 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2637 11:44:49.395167 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2638 11:44:49.395254 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2639 11:44:49.395337 # ok 909 Set SVE VL 3632
2640 11:44:49.395435 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2641 11:44:49.395521 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2642 11:44:49.395618 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2643 11:44:49.395719 # ok 913 Set SVE VL 3648
2644 11:44:49.396013 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2645 11:44:49.396122 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2646 11:44:49.396222 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2647 11:44:49.396307 # ok 917 Set SVE VL 3664
2648 11:44:49.396402 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2649 11:44:49.396501 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2650 11:44:49.396600 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2651 11:44:49.396699 # ok 921 Set SVE VL 3680
2652 11:44:49.396984 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2653 11:44:49.397304 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2654 11:44:49.397613 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2655 11:44:49.397728 # ok 925 Set SVE VL 3696
2656 11:44:49.398039 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2657 11:44:49.398155 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2658 11:44:49.398574 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2659 11:44:49.398670 # ok 929 Set SVE VL 3712
2660 11:44:49.398769 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2661 11:44:49.398844 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2662 11:44:49.398936 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2663 11:44:49.399021 # ok 933 Set SVE VL 3728
2664 11:44:49.399110 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2665 11:44:49.399395 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2666 11:44:49.399501 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2667 11:44:49.399597 # ok 937 Set SVE VL 3744
2668 11:44:49.399866 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2669 11:44:49.399943 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2670 11:44:49.400015 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2671 11:44:49.400087 # ok 941 Set SVE VL 3760
2672 11:44:49.400158 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2673 11:44:49.400636 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2674 11:44:49.400715 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2675 11:44:49.400778 # ok 945 Set SVE VL 3776
2676 11:44:49.401015 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2677 11:44:49.401089 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2678 11:44:49.401889 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2679 11:44:49.401972 # ok 949 Set SVE VL 3792
2680 11:44:49.402062 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2681 11:44:49.402173 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2682 11:44:49.402272 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2683 11:44:49.402370 # ok 953 Set SVE VL 3808
2684 11:44:49.402667 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2685 11:44:49.402783 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2686 11:44:49.402880 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2687 11:44:49.402987 # ok 957 Set SVE VL 3824
2688 11:44:49.403107 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2689 11:44:49.403208 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2690 11:44:49.403309 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2691 11:44:49.403396 # ok 961 Set SVE VL 3840
2692 11:44:49.403486 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2693 11:44:49.403588 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2694 11:44:49.403670 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2695 11:44:49.403756 # ok 965 Set SVE VL 3856
2696 11:44:49.403875 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2697 11:44:49.403979 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2698 11:44:49.404073 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2699 11:44:49.404154 # ok 969 Set SVE VL 3872
2700 11:44:49.404222 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2701 11:44:49.404281 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2702 11:44:49.404355 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2703 11:44:49.404421 # ok 973 Set SVE VL 3888
2704 11:44:49.404482 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2705 11:44:49.404542 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2706 11:44:49.404661 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2707 11:44:49.404757 # ok 977 Set SVE VL 3904
2708 11:44:49.404826 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2709 11:44:49.404915 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2710 11:44:49.405008 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2711 11:44:49.405086 # ok 981 Set SVE VL 3920
2712 11:44:49.405173 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2713 11:44:49.405257 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2714 11:44:49.405341 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2715 11:44:49.405434 # ok 985 Set SVE VL 3936
2716 11:44:49.405519 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2717 11:44:49.405635 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2718 11:44:49.405730 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2719 11:44:49.405824 # ok 989 Set SVE VL 3952
2720 11:44:49.406120 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2721 11:44:49.406220 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2722 11:44:49.406323 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2723 11:44:49.406413 # ok 993 Set SVE VL 3968
2724 11:44:49.406500 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2725 11:44:49.406602 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2726 11:44:49.406691 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2727 11:44:49.406790 # ok 997 Set SVE VL 3984
2728 11:44:49.406864 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2729 11:44:49.406942 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2730 11:44:49.407041 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2731 11:44:49.407119 # ok 1001 Set SVE VL 4000
2732 11:44:49.407203 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2733 11:44:49.407304 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2734 11:44:49.407599 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2735 11:44:49.407680 # ok 1005 Set SVE VL 4016
2736 11:44:49.409820 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2737 11:44:49.409926 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2738 11:44:49.410012 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2739 11:44:49.410094 # ok 1009 Set SVE VL 4032
2740 11:44:49.410176 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2741 11:44:49.410257 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2742 11:44:49.410338 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2743 11:44:49.410422 # ok 1013 Set SVE VL 4048
2744 11:44:49.410505 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2745 11:44:49.410588 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2746 11:44:49.410671 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2747 11:44:49.410755 # ok 1017 Set SVE VL 4064
2748 11:44:49.410837 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2749 11:44:49.410921 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2750 11:44:49.411006 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2751 11:44:49.411090 # ok 1021 Set SVE VL 4080
2752 11:44:49.411174 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2753 11:44:49.411258 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2754 11:44:49.411342 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2755 11:44:49.411428 # ok 1025 Set SVE VL 4096
2756 11:44:49.412628 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2757 11:44:49.412752 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2758 11:44:49.412843 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2759 11:44:49.412931 # ok 1029 Set SVE VL 4112
2760 11:44:49.413016 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2761 11:44:49.413102 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2762 11:44:49.413188 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2763 11:44:49.413274 # ok 1033 Set SVE VL 4128
2764 11:44:49.413360 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2765 11:44:49.413446 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2766 11:44:49.413531 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2767 11:44:49.413622 # ok 1037 Set SVE VL 4144
2768 11:44:49.413726 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2769 11:44:49.413812 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2770 11:44:49.413899 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2771 11:44:49.426552 # ok 1041 Set SVE VL 4160
2772 11:44:49.426710 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2773 11:44:49.426807 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2774 11:44:49.426888 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2775 11:44:49.426978 # ok 1045 Set SVE VL 4176
2776 11:44:49.427068 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2777 11:44:49.427160 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2778 11:44:49.427447 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2779 11:44:49.427539 # ok 1049 Set SVE VL 4192
2780 11:44:49.427813 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2781 11:44:49.427898 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2782 11:44:49.427989 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2783 11:44:49.428068 # ok 1053 Set SVE VL 4208
2784 11:44:49.428353 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2785 11:44:49.428438 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2786 11:44:49.428538 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2787 11:44:49.428624 # ok 1057 Set SVE VL 4224
2788 11:44:49.428710 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2789 11:44:49.429049 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2790 11:44:49.429334 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2791 11:44:49.429441 # ok 1061 Set SVE VL 4240
2792 11:44:49.429546 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2793 11:44:49.429658 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2794 11:44:49.429762 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2795 11:44:49.429848 # ok 1065 Set SVE VL 4256
2796 11:44:49.429944 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2797 11:44:49.430049 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2798 11:44:49.430342 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2799 11:44:49.430442 # ok 1069 Set SVE VL 4272
2800 11:44:49.430542 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2801 11:44:49.430649 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2802 11:44:49.430750 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2803 11:44:49.430851 # ok 1073 Set SVE VL 4288
2804 11:44:49.430958 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2805 11:44:49.431257 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2806 11:44:49.431374 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2807 11:44:49.431478 # ok 1077 Set SVE VL 4304
2808 11:44:49.431588 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2809 11:44:49.431889 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2810 11:44:49.431991 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2811 11:44:49.432078 # ok 1081 Set SVE VL 4320
2812 11:44:49.432176 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2813 11:44:49.432274 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2814 11:44:49.432578 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2815 11:44:49.432686 # ok 1085 Set SVE VL 4336
2816 11:44:49.432771 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2817 11:44:49.434457 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2818 11:44:49.434793 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2819 11:44:49.434904 # ok 1089 Set SVE VL 4352
2820 11:44:49.434986 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2821 11:44:49.435076 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2822 11:44:49.435173 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2823 11:44:49.435264 # ok 1093 Set SVE VL 4368
2824 11:44:49.435552 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2825 11:44:49.435669 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2826 11:44:49.435960 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2827 11:44:49.436190 # ok 1097 Set SVE VL 4384
2828 11:44:49.436291 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2829 11:44:49.436393 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2830 11:44:49.436495 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2831 11:44:49.436583 # ok 1101 Set SVE VL 4400
2832 11:44:49.436673 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2833 11:44:49.436772 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2834 11:44:49.436858 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2835 11:44:49.437920 # ok 1105 Set SVE VL 4416
2836 11:44:49.438219 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2837 11:44:49.438319 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2838 11:44:49.438419 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2839 11:44:49.438523 # ok 1109 Set SVE VL 4432
2840 11:44:49.438608 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2841 11:44:49.438707 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2842 11:44:49.439056 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2843 11:44:49.439156 # ok 1113 Set SVE VL 4448
2844 11:44:49.439240 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2845 11:44:49.439525 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2846 11:44:49.439637 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2847 11:44:49.439714 # ok 1117 Set SVE VL 4464
2848 11:44:49.439870 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2849 11:44:49.439963 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2850 11:44:49.440051 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2851 11:44:49.440126 # ok 1121 Set SVE VL 4480
2852 11:44:49.440208 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2853 11:44:49.440312 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2854 11:44:49.440600 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2855 11:44:49.440696 # ok 1125 Set SVE VL 4496
2856 11:44:49.440788 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2857 11:44:49.441063 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2858 11:44:49.441414 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2859 11:44:49.441694 # ok 1129 Set SVE VL 4512
2860 11:44:49.441905 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2861 11:44:49.442173 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2862 11:44:49.442365 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2863 11:44:49.442560 # ok 1133 Set SVE VL 4528
2864 11:44:49.442743 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2865 11:44:49.442930 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2866 11:44:49.443087 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2867 11:44:49.443251 # ok 1137 Set SVE VL 4544
2868 11:44:49.443416 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2869 11:44:49.443624 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2870 11:44:49.443877 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2871 11:44:49.444027 # ok 1141 Set SVE VL 4560
2872 11:44:49.444167 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2873 11:44:49.444287 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2874 11:44:49.444410 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2875 11:44:49.444531 # ok 1145 Set SVE VL 4576
2876 11:44:49.444651 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2877 11:44:49.444754 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2878 11:44:49.444867 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2879 11:44:49.444981 # ok 1149 Set SVE VL 4592
2880 11:44:49.445094 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2881 11:44:49.445202 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2882 11:44:49.445308 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2883 11:44:49.445426 # ok 1153 Set SVE VL 4608
2884 11:44:49.445541 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2885 11:44:49.445701 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2886 11:44:49.445832 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2887 11:44:49.445952 # ok 1157 Set SVE VL 4624
2888 11:44:49.446074 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2889 11:44:49.446221 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2890 11:44:49.446423 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2891 11:44:49.446616 # ok 1161 Set SVE VL 4640
2892 11:44:49.446807 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2893 11:44:49.446938 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2894 11:44:49.447070 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2895 11:44:49.447213 # ok 1165 Set SVE VL 4656
2896 11:44:49.447336 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2897 11:44:49.447491 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2898 11:44:49.447704 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2899 11:44:49.447859 # ok 1169 Set SVE VL 4672
2900 11:44:49.448059 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2901 11:44:49.448460 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2902 11:44:49.448641 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2903 11:44:49.448744 # ok 1173 Set SVE VL 4688
2904 11:44:49.448822 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2905 11:44:49.448896 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2906 11:44:49.448971 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2907 11:44:49.449045 # ok 1177 Set SVE VL 4704
2908 11:44:49.449121 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2909 11:44:49.449190 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2910 11:44:49.449266 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2911 11:44:49.449360 # ok 1181 Set SVE VL 4720
2912 11:44:49.449487 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2913 11:44:49.449575 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2914 11:44:49.449666 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2915 11:44:49.449755 # ok 1185 Set SVE VL 4736
2916 11:44:49.449835 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2917 11:44:49.449910 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2918 11:44:49.450010 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2919 11:44:49.450109 # ok 1189 Set SVE VL 4752
2920 11:44:49.450199 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2921 11:44:49.450263 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2922 11:44:49.450337 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2923 11:44:49.450400 # ok 1193 Set SVE VL 4768
2924 11:44:49.450460 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2925 11:44:49.450531 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2926 11:44:49.450601 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2927 11:44:49.450672 # ok 1197 Set SVE VL 4784
2928 11:44:49.450744 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2929 11:44:49.450995 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2930 11:44:49.451086 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2931 11:44:49.451162 # ok 1201 Set SVE VL 4800
2932 11:44:49.451238 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2933 11:44:49.451513 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2934 11:44:49.451622 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2935 11:44:49.451724 # ok 1205 Set SVE VL 4816
2936 11:44:49.451810 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2937 11:44:49.451912 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2938 11:44:49.452014 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2939 11:44:49.452114 # ok 1209 Set SVE VL 4832
2940 11:44:49.452213 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2941 11:44:49.452500 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2942 11:44:49.452604 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2943 11:44:49.452706 # ok 1213 Set SVE VL 4848
2944 11:44:49.452794 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2945 11:44:49.453082 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2946 11:44:49.453187 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2947 11:44:49.453288 # ok 1217 Set SVE VL 4864
2948 11:44:49.453567 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2949 11:44:49.453870 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2950 11:44:49.453968 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2951 11:44:49.454055 # ok 1221 Set SVE VL 4880
2952 11:44:49.454154 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2953 11:44:49.454252 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2954 11:44:49.467012 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2955 11:44:49.467211 # ok 1225 Set SVE VL 4896
2956 11:44:49.467298 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2957 11:44:49.467400 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2958 11:44:49.467483 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2959 11:44:49.467565 # ok 1229 Set SVE VL 4912
2960 11:44:49.467666 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2961 11:44:49.467761 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2962 11:44:49.467865 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2963 11:44:49.467958 # ok 1233 Set SVE VL 4928
2964 11:44:49.468055 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2965 11:44:49.468140 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2966 11:44:49.468239 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2967 11:44:49.468324 # ok 1237 Set SVE VL 4944
2968 11:44:49.468419 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2969 11:44:49.468525 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2970 11:44:49.470759 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2971 11:44:49.471082 # ok 1241 Set SVE VL 4960
2972 11:44:49.471186 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2973 11:44:49.471325 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2974 11:44:49.471420 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2975 11:44:49.471498 # ok 1245 Set SVE VL 4976
2976 11:44:49.471584 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2977 11:44:49.471671 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2978 11:44:49.471745 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2979 11:44:49.471829 # ok 1249 Set SVE VL 4992
2980 11:44:49.471914 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2981 11:44:49.472000 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2982 11:44:49.472084 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2983 11:44:49.472171 # ok 1253 Set SVE VL 5008
2984 11:44:49.472259 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2985 11:44:49.472596 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2986 11:44:49.472700 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2987 11:44:49.472782 # ok 1257 Set SVE VL 5024
2988 11:44:49.472876 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2989 11:44:49.473852 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2990 11:44:49.473965 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2991 11:44:49.474058 # ok 1261 Set SVE VL 5040
2992 11:44:49.474365 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2993 11:44:49.474467 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2994 11:44:49.474560 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2995 11:44:49.474640 # ok 1265 Set SVE VL 5056
2996 11:44:49.474729 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2997 11:44:49.474809 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2998 11:44:49.474897 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2999 11:44:49.474988 # ok 1269 Set SVE VL 5072
3000 11:44:49.475276 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
3001 11:44:49.475391 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
3002 11:44:49.475486 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3003 11:44:49.475564 # ok 1273 Set SVE VL 5088
3004 11:44:49.475861 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3005 11:44:49.475963 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3006 11:44:49.476055 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3007 11:44:49.476134 # ok 1277 Set SVE VL 5104
3008 11:44:49.476223 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3009 11:44:49.476313 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3010 11:44:49.476404 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3011 11:44:49.476483 # ok 1281 Set SVE VL 5120
3012 11:44:49.476572 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3013 11:44:49.476662 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3014 11:44:49.477693 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3015 11:44:49.477794 # ok 1285 Set SVE VL 5136
3016 11:44:49.477889 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3017 11:44:49.477990 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3018 11:44:49.478081 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3019 11:44:49.478166 # ok 1289 Set SVE VL 5152
3020 11:44:49.478258 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3021 11:44:49.478340 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3022 11:44:49.478434 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3023 11:44:49.478741 # ok 1293 Set SVE VL 5168
3024 11:44:49.478833 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3025 11:44:49.478913 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3026 11:44:49.478991 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3027 11:44:49.479085 # ok 1297 Set SVE VL 5184
3028 11:44:49.479165 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3029 11:44:49.479243 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3030 11:44:49.479333 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3031 11:44:49.479413 # ok 1301 Set SVE VL 5200
3032 11:44:49.479488 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3033 11:44:49.479596 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3034 11:44:49.479693 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3035 11:44:49.480059 # ok 1305 Set SVE VL 5216
3036 11:44:49.480168 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3037 11:44:49.480258 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3038 11:44:49.480335 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3039 11:44:49.480427 # ok 1309 Set SVE VL 5232
3040 11:44:49.480520 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3041 11:44:49.480798 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3042 11:44:49.480907 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3043 11:44:49.481027 # ok 1313 Set SVE VL 5248
3044 11:44:49.481153 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3045 11:44:49.481272 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3046 11:44:49.481371 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3047 11:44:49.481475 # ok 1317 Set SVE VL 5264
3048 11:44:49.481579 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3049 11:44:49.481685 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3050 11:44:49.481789 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3051 11:44:49.481895 # ok 1321 Set SVE VL 5280
3052 11:44:49.482020 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3053 11:44:49.482120 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3054 11:44:49.482200 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3055 11:44:49.482275 # ok 1325 Set SVE VL 5296
3056 11:44:49.482367 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3057 11:44:49.482451 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3058 11:44:49.482546 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3059 11:44:49.482628 # ok 1329 Set SVE VL 5312
3060 11:44:49.482740 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3061 11:44:49.482852 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3062 11:44:49.483205 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3063 11:44:49.483311 # ok 1333 Set SVE VL 5328
3064 11:44:49.483480 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3065 11:44:49.483615 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3066 11:44:49.483719 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3067 11:44:49.483804 # ok 1337 Set SVE VL 5344
3068 11:44:49.483880 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3069 11:44:49.483970 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3070 11:44:49.484049 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3071 11:44:49.484126 # ok 1341 Set SVE VL 5360
3072 11:44:49.484215 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3073 11:44:49.484293 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3074 11:44:49.484382 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3075 11:44:49.484472 # ok 1345 Set SVE VL 5376
3076 11:44:49.484562 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3077 11:44:49.484847 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3078 11:44:49.485161 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3079 11:44:49.485258 # ok 1349 Set SVE VL 5392
3080 11:44:49.485343 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3081 11:44:49.485436 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3082 11:44:49.485523 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3083 11:44:49.485624 # ok 1353 Set SVE VL 5408
3084 11:44:49.485726 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3085 11:44:49.485801 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3086 11:44:49.485891 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3087 11:44:49.485983 # ok 1357 Set SVE VL 5424
3088 11:44:49.486111 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3089 11:44:49.486217 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3090 11:44:49.486314 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3091 11:44:49.486442 # ok 1361 Set SVE VL 5440
3092 11:44:49.486559 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3093 11:44:49.486640 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3094 11:44:49.486727 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3095 11:44:49.486790 # ok 1365 Set SVE VL 5456
3096 11:44:49.486873 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3097 11:44:49.486982 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3098 11:44:49.487266 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3099 11:44:49.487372 # ok 1369 Set SVE VL 5472
3100 11:44:49.487474 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3101 11:44:49.487597 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3102 11:44:49.487689 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3103 11:44:49.487794 # ok 1373 Set SVE VL 5488
3104 11:44:49.487900 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3105 11:44:49.488023 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3106 11:44:49.488118 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3107 11:44:49.488215 # ok 1377 Set SVE VL 5504
3108 11:44:49.488299 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3109 11:44:49.488401 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3110 11:44:49.488689 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3111 11:44:49.488793 # ok 1381 Set SVE VL 5520
3112 11:44:49.489085 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3113 11:44:49.489183 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3114 11:44:49.489262 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3115 11:44:49.489348 # ok 1385 Set SVE VL 5536
3116 11:44:49.489434 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3117 11:44:49.489515 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3118 11:44:49.489798 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3119 11:44:49.489905 # ok 1389 Set SVE VL 5552
3120 11:44:49.490002 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3121 11:44:49.490083 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3122 11:44:49.490181 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3123 11:44:49.490267 # ok 1393 Set SVE VL 5568
3124 11:44:49.490362 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3125 11:44:49.490457 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3126 11:44:49.490551 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3127 11:44:49.490650 # ok 1397 Set SVE VL 5584
3128 11:44:49.490758 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3129 11:44:49.491088 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3130 11:44:49.491191 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3131 11:44:49.491276 # ok 1401 Set SVE VL 5600
3132 11:44:49.491374 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3133 11:44:49.491472 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3134 11:44:49.491570 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3135 11:44:49.491669 # ok 1405 Set SVE VL 5616
3136 11:44:49.491768 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3137 11:44:49.523608 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3138 11:44:49.524125 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3139 11:44:49.524236 # ok 1409 Set SVE VL 5632
3140 11:44:49.524326 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3141 11:44:49.524414 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3142 11:44:49.524707 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3143 11:44:49.524811 # ok 1413 Set SVE VL 5648
3144 11:44:49.524892 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3145 11:44:49.524970 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3146 11:44:49.525049 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3147 11:44:49.525131 # ok 1417 Set SVE VL 5664
3148 11:44:49.528625 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3149 11:44:49.529052 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3150 11:44:49.531532 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3151 11:44:49.531847 # ok 1421 Set SVE VL 5680
3152 11:44:49.531954 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3153 11:44:49.532066 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3154 11:44:49.532202 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3155 11:44:49.532305 # ok 1425 Set SVE VL 5696
3156 11:44:49.532427 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3157 11:44:49.532552 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3158 11:44:49.532646 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3159 11:44:49.532713 # ok 1429 Set SVE VL 5712
3160 11:44:49.532786 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3161 11:44:49.534200 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3162 11:44:49.534502 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3163 11:44:49.534602 # ok 1433 Set SVE VL 5728
3164 11:44:49.534695 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3165 11:44:49.534782 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3166 11:44:49.534880 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3167 11:44:49.534966 # ok 1437 Set SVE VL 5744
3168 11:44:49.535053 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3169 11:44:49.535138 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3170 11:44:49.535238 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3171 11:44:49.535317 # ok 1441 Set SVE VL 5760
3172 11:44:49.535394 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3173 11:44:49.535490 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3174 11:44:49.535572 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3175 11:44:49.535666 # ok 1445 Set SVE VL 5776
3176 11:44:49.535958 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3177 11:44:49.536073 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3178 11:44:49.536164 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3179 11:44:49.536243 # ok 1449 Set SVE VL 5792
3180 11:44:49.536342 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3181 11:44:49.536429 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3182 11:44:49.536517 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3183 11:44:49.536604 # ok 1453 Set SVE VL 5808
3184 11:44:49.537856 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3185 11:44:49.538154 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3186 11:44:49.538259 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3187 11:44:49.538341 # ok 1457 Set SVE VL 5824
3188 11:44:49.538432 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3189 11:44:49.538512 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3190 11:44:49.538602 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3191 11:44:49.538682 # ok 1461 Set SVE VL 5840
3192 11:44:49.538773 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3193 11:44:49.538864 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3194 11:44:49.539163 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3195 11:44:49.539263 # ok 1465 Set SVE VL 5856
3196 11:44:49.539439 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3197 11:44:49.539621 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3198 11:44:49.539717 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3199 11:44:49.539801 # ok 1469 Set SVE VL 5872
3200 11:44:49.539877 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3201 11:44:49.540165 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3202 11:44:49.540266 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3203 11:44:49.540345 # ok 1473 Set SVE VL 5888
3204 11:44:49.540421 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3205 11:44:49.540510 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3206 11:44:49.540589 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3207 11:44:49.540665 # ok 1477 Set SVE VL 5904
3208 11:44:49.540754 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3209 11:44:49.540836 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3210 11:44:49.542116 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3211 11:44:49.542217 # ok 1481 Set SVE VL 5920
3212 11:44:49.542307 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3213 11:44:49.542398 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3214 11:44:49.542487 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3215 11:44:49.542577 # ok 1485 Set SVE VL 5936
3216 11:44:49.542665 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3217 11:44:49.542754 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3218 11:44:49.543144 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3219 11:44:49.543450 # ok 1489 Set SVE VL 5952
3220 11:44:49.543540 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3221 11:44:49.543720 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3222 11:44:49.544048 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3223 11:44:49.544149 # ok 1493 Set SVE VL 5968
3224 11:44:49.544230 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3225 11:44:49.544310 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3226 11:44:49.544387 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3227 11:44:49.544463 # ok 1497 Set SVE VL 5984
3228 11:44:49.544538 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3229 11:44:49.544613 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3230 11:44:49.544689 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3231 11:44:49.544780 # ok 1501 Set SVE VL 6000
3232 11:44:49.544859 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3233 11:44:49.544934 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3234 11:44:49.545010 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3235 11:44:49.545086 # ok 1505 Set SVE VL 6016
3236 11:44:49.545161 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3237 11:44:49.545775 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3238 11:44:49.546355 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3239 11:44:49.546483 # ok 1509 Set SVE VL 6032
3240 11:44:49.546578 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3241 11:44:49.546662 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3242 11:44:49.546746 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3243 11:44:49.546845 # ok 1513 Set SVE VL 6048
3244 11:44:49.546935 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3245 11:44:49.547036 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3246 11:44:49.547122 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3247 11:44:49.547205 # ok 1517 Set SVE VL 6064
3248 11:44:49.547290 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3249 11:44:49.547394 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3250 11:44:49.547481 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3251 11:44:49.547580 # ok 1521 Set SVE VL 6080
3252 11:44:49.547666 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3253 11:44:49.547754 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3254 11:44:49.549799 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3255 11:44:49.550028 # ok 1525 Set SVE VL 6096
3256 11:44:49.550203 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3257 11:44:49.550368 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3258 11:44:49.550520 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3259 11:44:49.550671 # ok 1529 Set SVE VL 6112
3260 11:44:49.550819 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3261 11:44:49.550971 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3262 11:44:49.551133 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3263 11:44:49.551298 # ok 1533 Set SVE VL 6128
3264 11:44:49.551456 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3265 11:44:49.551620 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3266 11:44:49.552032 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3267 11:44:49.552140 # ok 1537 Set SVE VL 6144
3268 11:44:49.552228 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3269 11:44:49.552313 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3270 11:44:49.552399 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3271 11:44:49.552482 # ok 1541 Set SVE VL 6160
3272 11:44:49.552564 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3273 11:44:49.552646 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3274 11:44:49.552727 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3275 11:44:49.552810 # ok 1545 Set SVE VL 6176
3276 11:44:49.552891 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3277 11:44:49.552970 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3278 11:44:49.553047 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3279 11:44:49.553125 # ok 1549 Set SVE VL 6192
3280 11:44:49.553207 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3281 11:44:49.553289 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3282 11:44:49.553369 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3283 11:44:49.553449 # ok 1553 Set SVE VL 6208
3284 11:44:49.553531 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3285 11:44:49.553634 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3286 11:44:49.553728 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3287 11:44:49.553809 # ok 1557 Set SVE VL 6224
3288 11:44:49.553899 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3289 11:44:49.553980 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3290 11:44:49.554061 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3291 11:44:49.554141 # ok 1561 Set SVE VL 6240
3292 11:44:49.554223 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3293 11:44:49.554305 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3294 11:44:49.554405 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3295 11:44:49.554489 # ok 1565 Set SVE VL 6256
3296 11:44:49.554569 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3297 11:44:49.554652 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3298 11:44:49.554735 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3299 11:44:49.554820 # ok 1569 Set SVE VL 6272
3300 11:44:49.554902 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3301 11:44:49.555000 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3302 11:44:49.555087 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3303 11:44:49.555170 # ok 1573 Set SVE VL 6288
3304 11:44:49.555252 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3305 11:44:49.555336 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3306 11:44:49.555421 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3307 11:44:49.555523 # ok 1577 Set SVE VL 6304
3308 11:44:49.555609 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3309 11:44:49.556344 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3310 11:44:49.556450 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3311 11:44:49.556536 # ok 1581 Set SVE VL 6320
3312 11:44:49.556620 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3313 11:44:49.556703 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3314 11:44:49.556789 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3315 11:44:49.556875 # ok 1585 Set SVE VL 6336
3316 11:44:49.556958 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3317 11:44:49.557043 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3318 11:44:49.557127 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3319 11:44:49.557213 # ok 1589 Set SVE VL 6352
3320 11:44:49.558830 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3321 11:44:49.558940 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3322 11:44:49.559041 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3323 11:44:49.559126 # ok 1593 Set SVE VL 6368
3324 11:44:49.559210 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3325 11:44:49.559309 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3326 11:44:49.559396 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3327 11:44:49.559495 # ok 1597 Set SVE VL 6384
3328 11:44:49.559580 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3329 11:44:49.559677 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3330 11:44:49.559776 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3331 11:44:49.559868 # ok 1601 Set SVE VL 6400
3332 11:44:49.559970 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3333 11:44:49.560069 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3334 11:44:49.560434 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3335 11:44:49.560546 # ok 1605 Set SVE VL 6416
3336 11:44:49.560628 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3337 11:44:49.560720 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3338 11:44:49.561484 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3339 11:44:49.561917 # ok 1609 Set SVE VL 6432
3340 11:44:49.562024 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3341 11:44:49.562131 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3342 11:44:49.562234 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3343 11:44:49.562338 # ok 1613 Set SVE VL 6448
3344 11:44:49.562447 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3345 11:44:49.562739 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3346 11:44:49.563054 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3347 11:44:49.563162 # ok 1617 Set SVE VL 6464
3348 11:44:49.563265 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3349 11:44:49.563370 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3350 11:44:49.563662 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3351 11:44:49.563760 # ok 1621 Set SVE VL 6480
3352 11:44:49.564052 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3353 11:44:49.564159 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3354 11:44:49.564267 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3355 11:44:49.564555 # ok 1625 Set SVE VL 6496
3356 11:44:49.564666 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3357 11:44:49.564992 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3358 11:44:49.565455 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3359 11:44:49.565547 # ok 1629 Set SVE VL 6512
3360 11:44:49.565625 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3361 11:44:49.565712 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3362 11:44:49.565791 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3363 11:44:49.565884 # ok 1633 Set SVE VL 6528
3364 11:44:49.565963 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3365 11:44:49.566039 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3366 11:44:49.566128 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3367 11:44:49.566206 # ok 1637 Set SVE VL 6544
3368 11:44:49.566294 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3369 11:44:49.566385 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3370 11:44:49.566476 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3371 11:44:49.566567 # ok 1641 Set SVE VL 6560
3372 11:44:49.566656 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3373 11:44:49.566746 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3374 11:44:49.567031 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3375 11:44:49.567115 # ok 1645 Set SVE VL 6576
3376 11:44:49.567201 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3377 11:44:49.567298 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3378 11:44:49.567410 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3379 11:44:49.567518 # ok 1649 Set SVE VL 6592
3380 11:44:49.567621 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3381 11:44:49.567719 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3382 11:44:49.567832 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3383 11:44:49.567916 # ok 1653 Set SVE VL 6608
3384 11:44:49.568007 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3385 11:44:49.568289 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3386 11:44:49.568388 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3387 11:44:49.568481 # ok 1657 Set SVE VL 6624
3388 11:44:49.568560 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3389 11:44:49.568640 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3390 11:44:49.568906 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3391 11:44:49.569005 # ok 1661 Set SVE VL 6640
3392 11:44:49.569097 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3393 11:44:49.569187 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3394 11:44:49.569280 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3395 11:44:49.569376 # ok 1665 Set SVE VL 6656
3396 11:44:49.569471 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3397 11:44:49.569778 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3398 11:44:49.569904 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3399 11:44:49.569998 # ok 1669 Set SVE VL 6672
3400 11:44:49.570098 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3401 11:44:49.570184 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3402 11:44:49.570283 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3403 11:44:49.570383 # ok 1673 Set SVE VL 6688
3404 11:44:49.570483 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3405 11:44:49.570585 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3406 11:44:49.570849 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3407 11:44:49.570960 # ok 1677 Set SVE VL 6704
3408 11:44:49.571064 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3409 11:44:49.571153 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3410 11:44:49.571252 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3411 11:44:49.571335 # ok 1681 Set SVE VL 6720
3412 11:44:49.571432 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3413 11:44:49.571730 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3414 11:44:49.571841 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3415 11:44:49.571932 # ok 1685 Set SVE VL 6736
3416 11:44:49.572032 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3417 11:44:49.572118 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3418 11:44:49.572218 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3419 11:44:49.572305 # ok 1689 Set SVE VL 6752
3420 11:44:49.572402 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3421 11:44:49.572506 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3422 11:44:49.572607 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3423 11:44:49.572924 # ok 1693 Set SVE VL 6768
3424 11:44:49.573024 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3425 11:44:49.573143 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3426 11:44:49.573253 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3427 11:44:49.573379 # ok 1697 Set SVE VL 6784
3428 11:44:49.573474 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3429 11:44:49.573591 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3430 11:44:49.573719 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3431 11:44:49.573824 # ok 1701 Set SVE VL 6800
3432 11:44:49.573908 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3433 11:44:49.574196 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3434 11:44:49.574294 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3435 11:44:49.574385 # ok 1705 Set SVE VL 6816
3436 11:44:49.574466 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3437 11:44:49.574561 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3438 11:44:49.574654 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3439 11:44:49.574735 # ok 1709 Set SVE VL 6832
3440 11:44:49.574830 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3441 11:44:49.574928 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3442 11:44:49.575241 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3443 11:44:49.575343 # ok 1713 Set SVE VL 6848
3444 11:44:49.575424 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3445 11:44:49.575521 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3446 11:44:49.575619 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3447 11:44:49.575701 # ok 1717 Set SVE VL 6864
3448 11:44:49.575912 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3449 11:44:49.576021 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3450 11:44:49.576102 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3451 11:44:49.576191 # ok 1721 Set SVE VL 6880
3452 11:44:49.576269 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3453 11:44:49.576357 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3454 11:44:49.576636 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3455 11:44:49.576737 # ok 1725 Set SVE VL 6896
3456 11:44:49.576816 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3457 11:44:49.576910 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3458 11:44:49.576988 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3459 11:44:49.577078 # ok 1729 Set SVE VL 6912
3460 11:44:49.577156 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3461 11:44:49.577244 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3462 11:44:49.577334 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3463 11:44:49.577413 # ok 1733 Set SVE VL 6928
3464 11:44:49.577500 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3465 11:44:49.577590 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3466 11:44:49.577737 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3467 11:44:49.577829 # ok 1737 Set SVE VL 6944
3468 11:44:49.577923 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3469 11:44:49.578016 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3470 11:44:49.578309 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3471 11:44:49.578410 # ok 1741 Set SVE VL 6960
3472 11:44:49.578693 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3473 11:44:49.578794 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3474 11:44:49.578863 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3475 11:44:49.578933 # ok 1745 Set SVE VL 6976
3476 11:44:49.579024 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3477 11:44:49.579106 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3478 11:44:49.579199 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3479 11:44:49.579282 # ok 1749 Set SVE VL 6992
3480 11:44:49.579386 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3481 11:44:49.579493 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3482 11:44:49.579602 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3483 11:44:49.579714 # ok 1753 Set SVE VL 7008
3484 11:44:49.579801 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3485 11:44:49.579894 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3486 11:44:49.579996 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3487 11:44:49.580081 # ok 1757 Set SVE VL 7024
3488 11:44:49.580173 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3489 11:44:49.580274 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3490 11:44:49.580636 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3491 11:44:49.580718 # ok 1761 Set SVE VL 7040
3492 11:44:49.580793 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3493 11:44:49.580889 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3494 11:44:49.581173 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3495 11:44:49.581280 # ok 1765 Set SVE VL 7056
3496 11:44:49.581369 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3497 11:44:49.581475 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3498 11:44:49.581566 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3499 11:44:49.581677 # ok 1769 Set SVE VL 7072
3500 11:44:49.581779 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3501 11:44:49.581864 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3502 11:44:49.581965 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3503 11:44:49.584489 # ok 1773 Set SVE VL 7088
3504 11:44:49.584603 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3505 11:44:49.584690 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3506 11:44:49.585277 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3507 11:44:49.585607 # ok 1777 Set SVE VL 7104
3508 11:44:49.585723 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3509 11:44:49.585812 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3510 11:44:49.585912 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3511 11:44:49.586000 # ok 1781 Set SVE VL 7120
3512 11:44:49.586084 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3513 11:44:49.586182 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3514 11:44:49.586267 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3515 11:44:49.586364 # ok 1785 Set SVE VL 7136
3516 11:44:49.586462 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3517 11:44:49.586560 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3518 11:44:49.586660 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3519 11:44:49.586762 # ok 1789 Set SVE VL 7152
3520 11:44:49.586847 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3521 11:44:49.586945 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3522 11:44:49.587045 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3523 11:44:49.587153 # ok 1793 Set SVE VL 7168
3524 11:44:49.587580 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3525 11:44:49.587684 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3526 11:44:49.587788 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3527 11:44:49.587877 # ok 1797 Set SVE VL 7184
3528 11:44:49.587964 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3529 11:44:49.588068 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3530 11:44:49.588156 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3531 11:44:49.588253 # ok 1801 Set SVE VL 7200
3532 11:44:49.588352 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3533 11:44:49.588448 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3534 11:44:49.588741 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3535 11:44:49.588859 # ok 1805 Set SVE VL 7216
3536 11:44:49.588956 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3537 11:44:49.589245 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3538 11:44:49.589356 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3539 11:44:49.589457 # ok 1809 Set SVE VL 7232
3540 11:44:49.589747 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3541 11:44:49.589846 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3542 11:44:49.589948 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3543 11:44:49.590037 # ok 1813 Set SVE VL 7248
3544 11:44:49.590137 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3545 11:44:49.590439 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3546 11:44:49.590559 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3547 11:44:49.590647 # ok 1817 Set SVE VL 7264
3548 11:44:49.590745 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3549 11:44:49.590845 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3550 11:44:49.590952 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3551 11:44:49.591054 # ok 1821 Set SVE VL 7280
3552 11:44:49.591153 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3553 11:44:49.591252 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3554 11:44:49.591552 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3555 11:44:49.591656 # ok 1825 Set SVE VL 7296
3556 11:44:49.591758 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3557 11:44:49.591849 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3558 11:44:49.591963 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3559 11:44:49.592062 # ok 1829 Set SVE VL 7312
3560 11:44:49.592162 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3561 11:44:49.592279 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3562 11:44:49.592571 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3563 11:44:49.592666 # ok 1833 Set SVE VL 7328
3564 11:44:49.593569 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3565 11:44:49.593870 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3566 11:44:49.593980 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3567 11:44:49.594082 # ok 1837 Set SVE VL 7344
3568 11:44:49.594191 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3569 11:44:49.594484 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3570 11:44:49.594594 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3571 11:44:49.594697 # ok 1841 Set SVE VL 7360
3572 11:44:49.594801 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3573 11:44:49.595128 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3574 11:44:49.595233 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3575 11:44:49.595322 # ok 1845 Set SVE VL 7376
3576 11:44:49.595421 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3577 11:44:49.595506 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3578 11:44:49.595607 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3579 11:44:49.595708 # ok 1849 Set SVE VL 7392
3580 11:44:49.595807 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3581 11:44:49.595908 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3582 11:44:49.596017 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3583 11:44:49.596345 # ok 1853 Set SVE VL 7408
3584 11:44:49.596453 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3585 11:44:49.596551 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3586 11:44:49.596632 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3587 11:44:49.596709 # ok 1857 Set SVE VL 7424
3588 11:44:49.597240 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3589 11:44:49.597542 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3590 11:44:49.597660 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3591 11:44:49.597753 # ok 1861 Set SVE VL 7440
3592 11:44:49.597860 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3593 11:44:49.597980 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3594 11:44:49.598103 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3595 11:44:49.598216 # ok 1865 Set SVE VL 7456
3596 11:44:49.598347 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3597 11:44:49.598669 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3598 11:44:49.598814 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3599 11:44:49.598916 # ok 1869 Set SVE VL 7472
3600 11:44:49.599052 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3601 11:44:49.599172 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3602 11:44:49.599273 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3603 11:44:49.599378 # ok 1873 Set SVE VL 7488
3604 11:44:49.599491 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3605 11:44:49.599588 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3606 11:44:49.599688 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3607 11:44:49.599796 # ok 1877 Set SVE VL 7504
3608 11:44:49.599886 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3609 11:44:49.599973 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3610 11:44:49.600278 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3611 11:44:49.600382 # ok 1881 Set SVE VL 7520
3612 11:44:49.600486 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3613 11:44:49.600593 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3614 11:44:49.600687 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3615 11:44:49.600777 # ok 1885 Set SVE VL 7536
3616 11:44:49.600894 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3617 11:44:49.600994 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3618 11:44:49.601116 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3619 11:44:49.601217 # ok 1889 Set SVE VL 7552
3620 11:44:49.601303 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3621 11:44:49.601417 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3622 11:44:49.601697 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3623 11:44:49.601794 # ok 1893 Set SVE VL 7568
3624 11:44:49.601881 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3625 11:44:49.601963 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3626 11:44:49.602057 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3627 11:44:49.602143 # ok 1897 Set SVE VL 7584
3628 11:44:49.602218 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3629 11:44:49.602317 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3630 11:44:49.602406 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3631 11:44:49.602493 # ok 1901 Set SVE VL 7600
3632 11:44:49.602582 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3633 11:44:49.602668 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3634 11:44:49.602735 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3635 11:44:49.602834 # ok 1905 Set SVE VL 7616
3636 11:44:49.602939 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3637 11:44:49.603055 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3638 11:44:49.603166 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3639 11:44:49.603258 # ok 1909 Set SVE VL 7632
3640 11:44:49.603372 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3641 11:44:49.603461 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3642 11:44:49.603542 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3643 11:44:49.603627 # ok 1913 Set SVE VL 7648
3644 11:44:49.603737 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3645 11:44:49.603840 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3646 11:44:49.603942 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3647 11:44:49.604048 # ok 1917 Set SVE VL 7664
3648 11:44:49.604159 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3649 11:44:49.604246 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3650 11:44:49.604374 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3651 11:44:49.604464 # ok 1921 Set SVE VL 7680
3652 11:44:49.604560 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3653 11:44:49.604645 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3654 11:44:49.604721 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3655 11:44:49.604784 # ok 1925 Set SVE VL 7696
3656 11:44:49.605059 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3657 11:44:49.605160 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3658 11:44:49.605247 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3659 11:44:49.605334 # ok 1929 Set SVE VL 7712
3660 11:44:49.605429 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3661 11:44:49.605507 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3662 11:44:49.605608 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3663 11:44:49.605690 # ok 1933 Set SVE VL 7728
3664 11:44:49.605758 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3665 11:44:49.605850 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3666 11:44:49.605934 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3667 11:44:49.606014 # ok 1937 Set SVE VL 7744
3668 11:44:49.606124 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3669 11:44:49.606469 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3670 11:44:49.606594 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3671 11:44:49.606700 # ok 1941 Set SVE VL 7760
3672 11:44:49.606768 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3673 11:44:49.606857 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3674 11:44:49.606938 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3675 11:44:49.607006 # ok 1945 Set SVE VL 7776
3676 11:44:49.607067 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3677 11:44:49.607142 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3678 11:44:49.607209 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3679 11:44:49.607272 # ok 1949 Set SVE VL 7792
3680 11:44:49.607345 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3681 11:44:49.607451 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3682 11:44:49.607560 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3683 11:44:49.607668 # ok 1953 Set SVE VL 7808
3684 11:44:49.607775 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3685 11:44:49.607869 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3686 11:44:49.610813 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3687 11:44:49.610934 # ok 1957 Set SVE VL 7824
3688 11:44:49.611052 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3689 11:44:49.611522 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3690 11:44:49.611616 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3691 11:44:49.611685 # ok 1961 Set SVE VL 7840
3692 11:44:49.611745 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3693 11:44:49.611804 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3694 11:44:49.612046 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3695 11:44:49.612115 # ok 1965 Set SVE VL 7856
3696 11:44:49.612189 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3697 11:44:49.612264 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3698 11:44:49.612339 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3699 11:44:49.612403 # ok 1969 Set SVE VL 7872
3700 11:44:49.612464 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3701 11:44:49.612537 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3702 11:44:49.613214 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3703 11:44:49.613459 # ok 1973 Set SVE VL 7888
3704 11:44:49.613534 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3705 11:44:49.613607 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3706 11:44:49.613695 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3707 11:44:49.613769 # ok 1977 Set SVE VL 7904
3708 11:44:49.614023 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3709 11:44:49.614113 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3710 11:44:49.614186 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3711 11:44:49.614270 # ok 1981 Set SVE VL 7920
3712 11:44:49.614515 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3713 11:44:49.614757 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3714 11:44:49.614822 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3715 11:44:49.614882 # ok 1985 Set SVE VL 7936
3716 11:44:49.614955 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3717 11:44:49.615029 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3718 11:44:49.615274 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3719 11:44:49.615339 # ok 1989 Set SVE VL 7952
3720 11:44:49.615436 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3721 11:44:49.615692 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3722 11:44:49.615771 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3723 11:44:49.615860 # ok 1993 Set SVE VL 7968
3724 11:44:49.615940 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3725 11:44:49.616187 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3726 11:44:49.616251 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3727 11:44:49.616311 # ok 1997 Set SVE VL 7984
3728 11:44:49.616381 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3729 11:44:49.616451 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3730 11:44:49.616697 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3731 11:44:49.616773 # ok 2001 Set SVE VL 8000
3732 11:44:49.617019 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3733 11:44:49.617094 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3734 11:44:49.617339 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3735 11:44:49.617404 # ok 2005 Set SVE VL 8016
3736 11:44:49.617473 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3737 11:44:49.617544 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3738 11:44:49.617790 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3739 11:44:49.618076 # ok 2009 Set SVE VL 8032
3740 11:44:49.618143 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3741 11:44:49.618204 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3742 11:44:49.618440 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3743 11:44:49.618504 # ok 2013 Set SVE VL 8048
3744 11:44:49.618575 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3745 11:44:49.618648 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3746 11:44:49.618908 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3747 11:44:49.618975 # ok 2017 Set SVE VL 8064
3748 11:44:49.619046 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3749 11:44:49.619118 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3750 11:44:49.619383 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3751 11:44:49.619469 # ok 2021 Set SVE VL 8080
3752 11:44:49.619557 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3753 11:44:49.619665 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3754 11:44:49.619792 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3755 11:44:49.619880 # ok 2025 Set SVE VL 8096
3756 11:44:49.619973 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3757 11:44:49.620075 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3758 11:44:49.620181 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3759 11:44:49.620537 # ok 2029 Set SVE VL 8112
3760 11:44:49.620658 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3761 11:44:49.620729 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3762 11:44:49.621042 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3763 11:44:49.621151 # ok 2033 Set SVE VL 8128
3764 11:44:49.621267 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3765 11:44:49.621369 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3766 11:44:49.621489 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3767 11:44:49.621596 # ok 2037 Set SVE VL 8144
3768 11:44:49.621909 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3769 11:44:49.622013 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3770 11:44:49.622116 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3771 11:44:49.622217 # ok 2041 Set SVE VL 8160
3772 11:44:49.622317 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3773 11:44:49.622606 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3774 11:44:49.622696 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3775 11:44:49.622789 # ok 2045 Set SVE VL 8176
3776 11:44:49.622881 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3777 11:44:49.622973 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3778 11:44:49.623250 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3779 11:44:49.623345 # ok 2049 Set SVE VL 8192
3780 11:44:49.623444 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3781 11:44:49.623724 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3782 11:44:49.623818 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3783 11:44:49.623909 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3784 11:44:49.624005 # ok 2054 Streaming SVE get_fpsimd() gave same state
3785 11:44:49.624280 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3786 11:44:49.624363 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3787 11:44:49.624454 # ok 2057 Set Streaming SVE VL 16
3788 11:44:49.624544 # ok 2058 Set and get Streaming SVE data for VL 16
3789 11:44:49.625000 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3790 11:44:49.625085 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3791 11:44:49.625174 # ok 2061 Set Streaming SVE VL 32
3792 11:44:49.625446 # ok 2062 Set and get Streaming SVE data for VL 32
3793 11:44:49.625529 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3794 11:44:49.625619 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3795 11:44:49.625724 # ok 2065 Set Streaming SVE VL 48
3796 11:44:49.626002 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3797 11:44:49.626096 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3798 11:44:49.626375 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3799 11:44:49.626458 # ok 2069 Set Streaming SVE VL 64
3800 11:44:49.626547 # ok 2070 Set and get Streaming SVE data for VL 64
3801 11:44:49.626655 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3802 11:44:49.626932 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3803 11:44:49.627027 # ok 2073 Set Streaming SVE VL 80
3804 11:44:49.627300 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3805 11:44:49.627395 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3806 11:44:49.627674 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3807 11:44:49.627764 # ok 2077 Set Streaming SVE VL 96
3808 11:44:49.627860 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3809 11:44:49.628153 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3810 11:44:49.628246 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3811 11:44:49.628347 # ok 2081 Set Streaming SVE VL 112
3812 11:44:49.628451 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3813 11:44:49.628861 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3814 11:44:49.628964 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3815 11:44:49.629061 # ok 2085 Set Streaming SVE VL 128
3816 11:44:49.629153 # ok 2086 Set and get Streaming SVE data for VL 128
3817 11:44:49.629414 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3818 11:44:49.629511 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3819 11:44:49.629592 # ok 2089 Set Streaming SVE VL 144
3820 11:44:49.629877 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3821 11:44:49.630041 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3822 11:44:49.630133 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3823 11:44:49.630213 # ok 2093 Set Streaming SVE VL 160
3824 11:44:49.630285 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3825 11:44:49.630543 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3826 11:44:49.630794 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3827 11:44:49.630858 # ok 2097 Set Streaming SVE VL 176
3828 11:44:49.631103 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3829 11:44:49.631167 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3830 11:44:49.631398 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3831 11:44:49.631498 # ok 2101 Set Streaming SVE VL 192
3832 11:44:49.631595 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3833 11:44:49.631695 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3834 11:44:49.631970 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3835 11:44:49.632056 # ok 2105 Set Streaming SVE VL 208
3836 11:44:49.632146 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3837 11:44:49.632426 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3838 11:44:49.632521 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3839 11:44:49.632611 # ok 2109 Set Streaming SVE VL 224
3840 11:44:49.632884 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3841 11:44:49.633161 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3842 11:44:49.633259 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3843 11:44:49.633350 # ok 2113 Set Streaming SVE VL 240
3844 11:44:49.633441 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3845 11:44:49.633689 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3846 11:44:49.633786 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3847 11:44:49.633877 # ok 2117 Set Streaming SVE VL 256
3848 11:44:49.634158 # ok 2118 Set and get Streaming SVE data for VL 256
3849 11:44:49.634253 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3850 11:44:49.634345 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3851 11:44:49.634452 # ok 2121 Set Streaming SVE VL 272
3852 11:44:49.634728 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3853 11:44:49.634822 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3854 11:44:49.634920 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3855 11:44:49.635192 # ok 2125 Set Streaming SVE VL 288
3856 11:44:49.638438 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3857 11:44:49.638567 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3858 11:44:49.638845 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3859 11:44:49.638930 # ok 2129 Set Streaming SVE VL 304
3860 11:44:49.639020 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3861 11:44:49.639291 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3862 11:44:49.639385 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3863 11:44:49.639481 # ok 2133 Set Streaming SVE VL 320
3864 11:44:49.639779 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3865 11:44:49.639875 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3866 11:44:49.640148 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3867 11:44:49.640242 # ok 2137 Set Streaming SVE VL 336
3868 11:44:49.640507 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3869 11:44:49.640593 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3870 11:44:49.641228 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3871 11:44:49.641496 # ok 2141 Set Streaming SVE VL 352
3872 11:44:49.641579 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3873 11:44:49.641677 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3874 11:44:49.641951 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3875 11:44:49.642035 # ok 2145 Set Streaming SVE VL 368
3876 11:44:49.642124 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3877 11:44:49.642396 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3878 11:44:49.642490 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3879 11:44:49.642581 # ok 2149 Set Streaming SVE VL 384
3880 11:44:49.642853 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3881 11:44:49.642948 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3882 11:44:49.643039 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3883 11:44:49.643137 # ok 2153 Set Streaming SVE VL 400
3884 11:44:49.643427 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3885 11:44:49.643533 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3886 11:44:49.643944 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3887 11:44:49.644045 # ok 2157 Set Streaming SVE VL 416
3888 11:44:49.644140 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3889 11:44:49.644422 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3890 11:44:49.644521 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3891 11:44:49.644600 # ok 2161 Set Streaming SVE VL 432
3892 11:44:49.644676 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3893 11:44:49.644766 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3894 11:44:49.644858 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3895 11:44:49.644955 # ok 2165 Set Streaming SVE VL 448
3896 11:44:49.645253 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3897 11:44:49.645352 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3898 11:44:49.645444 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3899 11:44:49.645536 # ok 2169 Set Streaming SVE VL 464
3900 11:44:49.645826 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3901 11:44:49.645937 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3902 11:44:49.646033 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3903 11:44:49.646124 # ok 2173 Set Streaming SVE VL 480
3904 11:44:49.646214 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3905 11:44:49.646513 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3906 11:44:49.646612 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3907 11:44:49.646704 # ok 2177 Set Streaming SVE VL 496
3908 11:44:49.646783 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3909 11:44:49.646873 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3910 11:44:49.646970 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3911 11:44:49.647069 # ok 2181 Set Streaming SVE VL 512
3912 11:44:49.647357 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3913 11:44:49.647466 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3914 11:44:49.647565 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3915 11:44:49.647658 # ok 2185 Set Streaming SVE VL 528
3916 11:44:49.647953 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3917 11:44:49.648056 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3918 11:44:49.648383 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3919 11:44:49.648483 # ok 2189 Set Streaming SVE VL 544
3920 11:44:49.648575 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3921 11:44:49.648865 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3922 11:44:49.648948 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3923 11:44:49.649027 # ok 2193 Set Streaming SVE VL 560
3924 11:44:49.649121 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3925 11:44:49.649393 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3926 11:44:49.649473 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3927 11:44:49.649551 # ok 2197 Set Streaming SVE VL 576
3928 11:44:49.649800 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3929 11:44:49.650054 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3930 11:44:49.650297 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3931 11:44:49.650362 # ok 2201 Set Streaming SVE VL 592
3932 11:44:49.650431 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3933 11:44:49.650501 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3934 11:44:49.650758 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3935 11:44:49.650825 # ok 2205 Set Streaming SVE VL 608
3936 11:44:49.651071 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3937 11:44:49.651144 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3938 11:44:49.651404 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3939 11:44:49.651502 # ok 2209 Set Streaming SVE VL 624
3940 11:44:49.651603 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3941 11:44:49.651888 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3942 11:44:49.651984 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3943 11:44:49.652064 # ok 2213 Set Streaming SVE VL 640
3944 11:44:49.652154 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3945 11:44:49.652478 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3946 11:44:49.652567 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3947 11:44:49.652819 # ok 2217 Set Streaming SVE VL 656
3948 11:44:49.652895 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3949 11:44:49.653137 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3950 11:44:49.653210 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3951 11:44:49.653455 # ok 2221 Set Streaming SVE VL 672
3952 11:44:49.653519 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3953 11:44:49.653763 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3954 11:44:49.654012 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3955 11:44:49.654077 # ok 2225 Set Streaming SVE VL 688
3956 11:44:49.654146 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3957 11:44:49.654222 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3958 11:44:49.654466 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3959 11:44:49.654530 # ok 2229 Set Streaming SVE VL 704
3960 11:44:49.654774 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3961 11:44:49.654838 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3962 11:44:49.655081 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3963 11:44:49.655144 # ok 2233 Set Streaming SVE VL 720
3964 11:44:49.655213 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3965 11:44:49.655471 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3966 11:44:49.655572 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3967 11:44:49.655663 # ok 2237 Set Streaming SVE VL 736
3968 11:44:49.655942 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3969 11:44:49.656031 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3970 11:44:49.656285 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3971 11:44:49.656350 # ok 2241 Set Streaming SVE VL 752
3972 11:44:49.656592 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3973 11:44:49.656833 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3974 11:44:49.656922 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3975 11:44:49.656994 # ok 2245 Set Streaming SVE VL 768
3976 11:44:49.657242 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3977 11:44:49.657315 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3978 11:44:49.657392 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3979 11:44:49.657642 # ok 2249 Set Streaming SVE VL 784
3980 11:44:49.657728 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3981 11:44:49.657973 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3982 11:44:49.658048 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3983 11:44:49.658293 # ok 2253 Set Streaming SVE VL 800
3984 11:44:49.658369 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3985 11:44:49.658616 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3986 11:44:49.658691 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3987 11:44:49.658763 # ok 2257 Set Streaming SVE VL 816
3988 11:44:49.659012 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3989 11:44:49.659261 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3990 11:44:49.659336 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3991 11:44:49.659408 # ok 2261 Set Streaming SVE VL 832
3992 11:44:49.659671 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3993 11:44:49.659775 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3994 11:44:49.659866 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3995 11:44:49.660119 # ok 2265 Set Streaming SVE VL 848
3996 11:44:49.660184 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3997 11:44:49.660428 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3998 11:44:49.660505 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3999 11:44:49.660922 # ok 2269 Set Streaming SVE VL 864
4000 11:44:49.660989 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
4001 11:44:49.661065 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
4002 11:44:49.661312 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4003 11:44:49.661387 # ok 2273 Set Streaming SVE VL 880
4004 11:44:49.661632 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4005 11:44:49.661718 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4006 11:44:49.661965 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4007 11:44:49.662215 # ok 2277 Set Streaming SVE VL 896
4008 11:44:49.662280 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4009 11:44:49.665412 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4010 11:44:49.665675 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4011 11:44:49.665743 # ok 2281 Set Streaming SVE VL 912
4012 11:44:49.665988 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4013 11:44:49.666064 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4014 11:44:49.666309 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4015 11:44:49.666375 # ok 2285 Set Streaming SVE VL 928
4016 11:44:49.666647 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4017 11:44:49.666756 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4018 11:44:49.667106 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4019 11:44:49.667287 # ok 2289 Set Streaming SVE VL 944
4020 11:44:49.667585 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4021 11:44:49.667690 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4022 11:44:49.667780 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4023 11:44:49.667877 # ok 2293 Set Streaming SVE VL 960
4024 11:44:49.668346 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4025 11:44:49.668459 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4026 11:44:49.668557 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4027 11:44:49.668724 # ok 2297 Set Streaming SVE VL 976
4028 11:44:49.668826 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4029 11:44:49.668927 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4030 11:44:49.669056 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4031 11:44:49.669160 # ok 2301 Set Streaming SVE VL 992
4032 11:44:49.669256 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4033 11:44:49.669352 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4034 11:44:49.669467 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4035 11:44:49.669565 # ok 2305 Set Streaming SVE VL 1008
4036 11:44:49.669673 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4037 11:44:49.669788 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4038 11:44:49.669885 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4039 11:44:49.669998 # ok 2309 Set Streaming SVE VL 1024
4040 11:44:49.670117 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4041 11:44:49.670229 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4042 11:44:49.670538 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4043 11:44:49.670640 # ok 2313 Set Streaming SVE VL 1040
4044 11:44:49.670752 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4045 11:44:49.670866 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4046 11:44:49.670979 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4047 11:44:49.671096 # ok 2317 Set Streaming SVE VL 1056
4048 11:44:49.671413 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4049 11:44:49.671533 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4050 11:44:49.671636 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4051 11:44:49.671937 # ok 2321 Set Streaming SVE VL 1072
4052 11:44:49.672033 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4053 11:44:49.672138 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4054 11:44:49.672427 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4055 11:44:49.672519 # ok 2325 Set Streaming SVE VL 1088
4056 11:44:49.672809 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4057 11:44:49.672918 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4058 11:44:49.673028 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4059 11:44:49.673131 # ok 2329 Set Streaming SVE VL 1104
4060 11:44:49.673239 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4061 11:44:49.673530 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4062 11:44:49.673641 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4063 11:44:49.673753 # ok 2333 Set Streaming SVE VL 1120
4064 11:44:49.673853 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4065 11:44:49.674159 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4066 11:44:49.674268 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4067 11:44:49.674367 # ok 2337 Set Streaming SVE VL 1136
4068 11:44:49.674469 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4069 11:44:49.674761 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4070 11:44:49.674872 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4071 11:44:49.674975 # ok 2341 Set Streaming SVE VL 1152
4072 11:44:49.675080 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4073 11:44:49.675379 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4074 11:44:49.675487 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4075 11:44:49.675590 # ok 2345 Set Streaming SVE VL 1168
4076 11:44:49.675878 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4077 11:44:49.675974 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4078 11:44:49.676262 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4079 11:44:49.676356 # ok 2349 Set Streaming SVE VL 1184
4080 11:44:49.676457 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4081 11:44:49.676557 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4082 11:44:49.676844 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4083 11:44:49.676952 # ok 2353 Set Streaming SVE VL 1200
4084 11:44:49.677240 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4085 11:44:49.677347 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4086 11:44:49.677454 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4087 11:44:49.677554 # ok 2357 Set Streaming SVE VL 1216
4088 11:44:49.677857 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4089 11:44:49.677968 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4090 11:44:49.678066 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4091 11:44:49.678168 # ok 2361 Set Streaming SVE VL 1232
4092 11:44:49.678457 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4093 11:44:49.678569 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4094 11:44:49.678674 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4095 11:44:49.678784 # ok 2365 Set Streaming SVE VL 1248
4096 11:44:49.679092 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4097 11:44:49.679187 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4098 11:44:49.679475 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4099 11:44:49.679570 # ok 2369 Set Streaming SVE VL 1264
4100 11:44:49.679673 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4101 11:44:49.679779 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4102 11:44:49.680071 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4103 11:44:49.680170 # ok 2373 Set Streaming SVE VL 1280
4104 11:44:49.680274 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4105 11:44:49.680379 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4106 11:44:49.680670 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4107 11:44:49.680780 # ok 2377 Set Streaming SVE VL 1296
4108 11:44:49.680901 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4109 11:44:49.681012 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4110 11:44:49.681303 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4111 11:44:49.681408 # ok 2381 Set Streaming SVE VL 1312
4112 11:44:49.681685 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4113 11:44:49.681780 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4114 11:44:49.681879 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4115 11:44:49.681979 # ok 2385 Set Streaming SVE VL 1328
4116 11:44:49.682273 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4117 11:44:49.682384 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4118 11:44:49.682486 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4119 11:44:49.682587 # ok 2389 Set Streaming SVE VL 1344
4120 11:44:49.682874 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4121 11:44:49.682983 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4122 11:44:49.683089 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4123 11:44:49.683382 # ok 2393 Set Streaming SVE VL 1360
4124 11:44:49.683492 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4125 11:44:49.683595 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4126 11:44:49.683891 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4127 11:44:49.683989 # ok 2397 Set Streaming SVE VL 1376
4128 11:44:49.684092 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4129 11:44:49.684383 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4130 11:44:49.684493 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4131 11:44:49.684597 # ok 2401 Set Streaming SVE VL 1392
4132 11:44:49.684709 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4133 11:44:49.685010 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4134 11:44:49.685121 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4135 11:44:49.685223 # ok 2405 Set Streaming SVE VL 1408
4136 11:44:49.685514 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4137 11:44:49.685610 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4138 11:44:49.685721 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4139 11:44:49.685825 # ok 2409 Set Streaming SVE VL 1424
4140 11:44:49.685928 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4141 11:44:49.686232 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4142 11:44:49.686339 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4143 11:44:49.686441 # ok 2413 Set Streaming SVE VL 1440
4144 11:44:49.686544 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4145 11:44:49.686834 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4146 11:44:49.686943 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4147 11:44:49.687033 # ok 2417 Set Streaming SVE VL 1456
4148 11:44:49.687321 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4149 11:44:49.687430 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4150 11:44:49.687720 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4151 11:44:49.687817 # ok 2421 Set Streaming SVE VL 1472
4152 11:44:49.687922 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4153 11:44:49.688013 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4154 11:44:49.688118 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4155 11:44:49.688410 # ok 2425 Set Streaming SVE VL 1488
4156 11:44:49.688506 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4157 11:44:49.688793 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4158 11:44:49.688903 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4159 11:44:49.691264 # ok 2429 Set Streaming SVE VL 1504
4160 11:44:49.691564 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4161 11:44:49.691672 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4162 11:44:49.691774 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4163 11:44:49.691879 # ok 2433 Set Streaming SVE VL 1520
4164 11:44:49.692171 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4165 11:44:49.692281 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4166 11:44:49.692382 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4167 11:44:49.692485 # ok 2437 Set Streaming SVE VL 1536
4168 11:44:49.693320 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4169 11:44:49.693612 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4170 11:44:49.693906 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4171 11:44:49.693999 # ok 2441 Set Streaming SVE VL 1552
4172 11:44:49.694087 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4173 11:44:49.694184 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4174 11:44:49.694282 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4175 11:44:49.694381 # ok 2445 Set Streaming SVE VL 1568
4176 11:44:49.694944 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4177 11:44:49.695049 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4178 11:44:49.695134 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4179 11:44:49.695216 # ok 2449 Set Streaming SVE VL 1584
4180 11:44:49.695512 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4181 11:44:49.695617 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4182 11:44:49.695704 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4183 11:44:49.695787 # ok 2453 Set Streaming SVE VL 1600
4184 11:44:49.695871 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4185 11:44:49.695975 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4186 11:44:49.696064 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4187 11:44:49.696152 # ok 2457 Set Streaming SVE VL 1616
4188 11:44:49.696251 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4189 11:44:49.696334 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4190 11:44:49.696430 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4191 11:44:49.696515 # ok 2461 Set Streaming SVE VL 1632
4192 11:44:49.696614 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4193 11:44:49.696958 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4194 11:44:49.697064 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4195 11:44:49.697160 # ok 2465 Set Streaming SVE VL 1648
4196 11:44:49.697261 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4197 11:44:49.697349 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4198 11:44:49.697446 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4199 11:44:49.697544 # ok 2469 Set Streaming SVE VL 1664
4200 11:44:49.697643 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4201 11:44:49.697954 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4202 11:44:49.698059 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4203 11:44:49.698162 # ok 2473 Set Streaming SVE VL 1680
4204 11:44:49.698263 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4205 11:44:49.698365 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4206 11:44:49.698453 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4207 11:44:49.698553 # ok 2477 Set Streaming SVE VL 1696
4208 11:44:49.698889 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4209 11:44:49.698993 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4210 11:44:49.699076 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4211 11:44:49.699183 # ok 2481 Set Streaming SVE VL 1712
4212 11:44:49.699268 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4213 11:44:49.699365 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4214 11:44:49.699466 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4215 11:44:49.699552 # ok 2485 Set Streaming SVE VL 1728
4216 11:44:49.699647 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4217 11:44:49.699940 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4218 11:44:49.700045 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4219 11:44:49.700129 # ok 2489 Set Streaming SVE VL 1744
4220 11:44:49.700224 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4221 11:44:49.700311 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4222 11:44:49.700409 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4223 11:44:49.700498 # ok 2493 Set Streaming SVE VL 1760
4224 11:44:49.700596 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4225 11:44:49.700696 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4226 11:44:49.700797 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4227 11:44:49.700897 # ok 2497 Set Streaming SVE VL 1776
4228 11:44:49.701225 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4229 11:44:49.701331 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4230 11:44:49.701436 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4231 11:44:49.701523 # ok 2501 Set Streaming SVE VL 1792
4232 11:44:49.701624 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4233 11:44:49.701734 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4234 11:44:49.702065 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4235 11:44:49.702173 # ok 2505 Set Streaming SVE VL 1808
4236 11:44:49.702273 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4237 11:44:49.702359 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4238 11:44:49.702456 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4239 11:44:49.702554 # ok 2509 Set Streaming SVE VL 1824
4240 11:44:49.702650 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4241 11:44:49.702749 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4242 11:44:49.703065 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4243 11:44:49.703169 # ok 2513 Set Streaming SVE VL 1840
4244 11:44:49.703268 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4245 11:44:49.703366 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4246 11:44:49.703464 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4247 11:44:49.703563 # ok 2517 Set Streaming SVE VL 1856
4248 11:44:49.703875 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4249 11:44:49.703979 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4250 11:44:49.704079 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4251 11:44:49.704172 # ok 2521 Set Streaming SVE VL 1872
4252 11:44:49.704268 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4253 11:44:49.704367 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4254 11:44:49.704465 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4255 11:44:49.704564 # ok 2525 Set Streaming SVE VL 1888
4256 11:44:49.704862 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4257 11:44:49.704983 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4258 11:44:49.705295 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4259 11:44:49.705400 # ok 2529 Set Streaming SVE VL 1904
4260 11:44:49.705485 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4261 11:44:49.705764 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4262 11:44:49.705867 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4263 11:44:49.705981 # ok 2533 Set Streaming SVE VL 1920
4264 11:44:49.706062 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4265 11:44:49.706156 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4266 11:44:49.706247 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4267 11:44:49.706345 # ok 2537 Set Streaming SVE VL 1936
4268 11:44:49.706453 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4269 11:44:49.706542 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4270 11:44:49.706616 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4271 11:44:49.706716 # ok 2541 Set Streaming SVE VL 1952
4272 11:44:49.706804 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4273 11:44:49.706912 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4274 11:44:49.707193 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4275 11:44:49.707297 # ok 2545 Set Streaming SVE VL 1968
4276 11:44:49.707431 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4277 11:44:49.707545 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4278 11:44:49.707679 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4279 11:44:49.707779 # ok 2549 Set Streaming SVE VL 1984
4280 11:44:49.707891 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4281 11:44:49.707983 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4282 11:44:49.708079 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4283 11:44:49.708155 # ok 2553 Set Streaming SVE VL 2000
4284 11:44:49.708246 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4285 11:44:49.708332 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4286 11:44:49.708602 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4287 11:44:49.708811 # ok 2557 Set Streaming SVE VL 2016
4288 11:44:49.709154 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4289 11:44:49.709250 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4290 11:44:49.709360 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4291 11:44:49.709434 # ok 2561 Set Streaming SVE VL 2032
4292 11:44:49.709799 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4293 11:44:49.709905 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4294 11:44:49.709992 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4295 11:44:49.710290 # ok 2565 Set Streaming SVE VL 2048
4296 11:44:49.710394 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4297 11:44:49.710476 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4298 11:44:49.710556 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4299 11:44:49.710648 # ok 2569 Set Streaming SVE VL 2064
4300 11:44:49.710726 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4301 11:44:49.710815 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4302 11:44:49.710906 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4303 11:44:49.710985 # ok 2573 Set Streaming SVE VL 2080
4304 11:44:49.711074 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4305 11:44:49.711374 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4306 11:44:49.711476 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4307 11:44:49.711556 # ok 2577 Set Streaming SVE VL 2096
4308 11:44:49.711648 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4309 11:44:49.714880 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4310 11:44:49.715004 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4311 11:44:49.715097 # ok 2581 Set Streaming SVE VL 2112
4312 11:44:49.715394 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4313 11:44:49.715495 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4314 11:44:49.715599 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4315 11:44:49.715680 # ok 2585 Set Streaming SVE VL 2128
4316 11:44:49.715968 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4317 11:44:49.716070 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4318 11:44:49.716168 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4319 11:44:49.716248 # ok 2589 Set Streaming SVE VL 2144
4320 11:44:49.716339 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4321 11:44:49.716434 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4322 11:44:49.717134 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4323 11:44:49.717440 # ok 2593 Set Streaming SVE VL 2160
4324 11:44:49.717548 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4325 11:44:49.717658 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4326 11:44:49.717749 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4327 11:44:49.717848 # ok 2597 Set Streaming SVE VL 2176
4328 11:44:49.717951 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4329 11:44:49.718058 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4330 11:44:49.718161 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4331 11:44:49.718262 # ok 2601 Set Streaming SVE VL 2192
4332 11:44:49.718547 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4333 11:44:49.718667 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4334 11:44:49.718753 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4335 11:44:49.718837 # ok 2605 Set Streaming SVE VL 2208
4336 11:44:49.718919 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4337 11:44:49.719017 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4338 11:44:49.719103 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4339 11:44:49.719208 # ok 2609 Set Streaming SVE VL 2224
4340 11:44:49.719293 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4341 11:44:49.719393 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4342 11:44:49.719492 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4343 11:44:49.719592 # ok 2613 Set Streaming SVE VL 2240
4344 11:44:49.719953 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4345 11:44:49.720061 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4346 11:44:49.720344 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4347 11:44:49.720446 # ok 2617 Set Streaming SVE VL 2256
4348 11:44:49.720524 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4349 11:44:49.720615 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4350 11:44:49.720897 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4351 11:44:49.720992 # ok 2621 Set Streaming SVE VL 2272
4352 11:44:49.721099 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4353 11:44:49.721179 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4354 11:44:49.721272 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4355 11:44:49.721539 # ok 2625 Set Streaming SVE VL 2288
4356 11:44:49.721611 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4357 11:44:49.721712 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4358 11:44:49.721977 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4359 11:44:49.722249 # ok 2629 Set Streaming SVE VL 2304
4360 11:44:49.722335 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4361 11:44:49.722483 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4362 11:44:49.722589 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4363 11:44:49.722658 # ok 2633 Set Streaming SVE VL 2320
4364 11:44:49.722750 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4365 11:44:49.723042 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4366 11:44:49.723163 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4367 11:44:49.723255 # ok 2637 Set Streaming SVE VL 2336
4368 11:44:49.723356 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4369 11:44:49.723493 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4370 11:44:49.723609 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4371 11:44:49.723708 # ok 2641 Set Streaming SVE VL 2352
4372 11:44:49.724000 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4373 11:44:49.724114 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4374 11:44:49.724413 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4375 11:44:49.724516 # ok 2645 Set Streaming SVE VL 2368
4376 11:44:49.724610 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4377 11:44:49.724954 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4378 11:44:49.725257 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4379 11:44:49.725356 # ok 2649 Set Streaming SVE VL 2384
4380 11:44:49.725458 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4381 11:44:49.725547 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4382 11:44:49.725644 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4383 11:44:49.725939 # ok 2653 Set Streaming SVE VL 2400
4384 11:44:49.726044 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4385 11:44:49.726332 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4386 11:44:49.726435 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4387 11:44:49.726525 # ok 2657 Set Streaming SVE VL 2416
4388 11:44:49.726612 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4389 11:44:49.726716 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4390 11:44:49.726804 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4391 11:44:49.726903 # ok 2661 Set Streaming SVE VL 2432
4392 11:44:49.727003 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4393 11:44:49.727100 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4394 11:44:49.727202 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4395 11:44:49.727492 # ok 2665 Set Streaming SVE VL 2448
4396 11:44:49.727598 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4397 11:44:49.727700 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4398 11:44:49.727788 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4399 11:44:49.727873 # ok 2669 Set Streaming SVE VL 2464
4400 11:44:49.727974 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4401 11:44:49.728062 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4402 11:44:49.728162 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4403 11:44:49.728263 # ok 2673 Set Streaming SVE VL 2480
4404 11:44:49.728363 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4405 11:44:49.728667 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4406 11:44:49.728783 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4407 11:44:49.728879 # ok 2677 Set Streaming SVE VL 2496
4408 11:44:49.728973 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4409 11:44:49.729294 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4410 11:44:49.729396 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4411 11:44:49.729477 # ok 2681 Set Streaming SVE VL 2512
4412 11:44:49.729568 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4413 11:44:49.729653 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4414 11:44:49.729746 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4415 11:44:49.729838 # ok 2685 Set Streaming SVE VL 2528
4416 11:44:49.730138 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4417 11:44:49.730296 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4418 11:44:49.730397 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4419 11:44:49.730478 # ok 2689 Set Streaming SVE VL 2544
4420 11:44:49.730555 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4421 11:44:49.730843 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4422 11:44:49.730946 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4423 11:44:49.731028 # ok 2693 Set Streaming SVE VL 2560
4424 11:44:49.731122 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4425 11:44:49.731207 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4426 11:44:49.731298 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4427 11:44:49.731376 # ok 2697 Set Streaming SVE VL 2576
4428 11:44:49.731472 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4429 11:44:49.731689 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4430 11:44:49.731907 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4431 11:44:49.732002 # ok 2701 Set Streaming SVE VL 2592
4432 11:44:49.732086 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4433 11:44:49.732181 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4434 11:44:49.732281 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4435 11:44:49.732361 # ok 2705 Set Streaming SVE VL 2608
4436 11:44:49.732450 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4437 11:44:49.732747 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4438 11:44:49.732909 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4439 11:44:49.733218 # ok 2709 Set Streaming SVE VL 2624
4440 11:44:49.733310 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4441 11:44:49.733409 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4442 11:44:49.733531 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4443 11:44:49.733663 # ok 2713 Set Streaming SVE VL 2640
4444 11:44:49.733767 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4445 11:44:49.733840 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4446 11:44:49.733914 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4447 11:44:49.733995 # ok 2717 Set Streaming SVE VL 2656
4448 11:44:49.734090 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4449 11:44:49.734221 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4450 11:44:49.734357 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4451 11:44:49.734475 # ok 2721 Set Streaming SVE VL 2672
4452 11:44:49.734787 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4453 11:44:49.734896 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4454 11:44:49.735002 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4455 11:44:49.735094 # ok 2725 Set Streaming SVE VL 2688
4456 11:44:49.735200 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4457 11:44:49.735291 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4458 11:44:49.738395 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4459 11:44:49.738521 # ok 2729 Set Streaming SVE VL 2704
4460 11:44:49.738648 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4461 11:44:49.738761 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4462 11:44:49.738854 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4463 11:44:49.738979 # ok 2733 Set Streaming SVE VL 2720
4464 11:44:49.739095 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4465 11:44:49.739213 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4466 11:44:49.739318 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4467 11:44:49.739554 # ok 2737 Set Streaming SVE VL 2736
4468 11:44:49.739649 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4469 11:44:49.739747 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4470 11:44:49.739868 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4471 11:44:49.739961 # ok 2741 Set Streaming SVE VL 2752
4472 11:44:49.740077 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4473 11:44:49.740203 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4474 11:44:49.740302 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4475 11:44:49.740394 # ok 2745 Set Streaming SVE VL 2768
4476 11:44:49.741076 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4477 11:44:49.741371 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4478 11:44:49.741473 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4479 11:44:49.741573 # ok 2749 Set Streaming SVE VL 2784
4480 11:44:49.741681 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4481 11:44:49.741779 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4482 11:44:49.741881 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4483 11:44:49.741981 # ok 2753 Set Streaming SVE VL 2800
4484 11:44:49.742284 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4485 11:44:49.742380 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4486 11:44:49.742478 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4487 11:44:49.742574 # ok 2757 Set Streaming SVE VL 2816
4488 11:44:49.742671 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4489 11:44:49.742772 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4490 11:44:49.743102 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4491 11:44:49.743210 # ok 2761 Set Streaming SVE VL 2832
4492 11:44:49.743305 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4493 11:44:49.743385 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4494 11:44:49.743490 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4495 11:44:49.743589 # ok 2765 Set Streaming SVE VL 2848
4496 11:44:49.743688 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4497 11:44:49.743982 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4498 11:44:49.744097 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4499 11:44:49.744194 # ok 2769 Set Streaming SVE VL 2864
4500 11:44:49.744276 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4501 11:44:49.744365 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4502 11:44:49.744455 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4503 11:44:49.744927 # ok 2773 Set Streaming SVE VL 2880
4504 11:44:49.745039 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4505 11:44:49.745152 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4506 11:44:49.745278 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4507 11:44:49.745386 # ok 2777 Set Streaming SVE VL 2896
4508 11:44:49.745489 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4509 11:44:49.745587 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4510 11:44:49.746008 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4511 11:44:49.746138 # ok 2781 Set Streaming SVE VL 2912
4512 11:44:49.746248 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4513 11:44:49.746343 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4514 11:44:49.746445 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4515 11:44:49.746532 # ok 2785 Set Streaming SVE VL 2928
4516 11:44:49.746616 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4517 11:44:49.746728 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4518 11:44:49.746826 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4519 11:44:49.746945 # ok 2789 Set Streaming SVE VL 2944
4520 11:44:49.747053 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4521 11:44:49.747182 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4522 11:44:49.747279 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4523 11:44:49.747363 # ok 2793 Set Streaming SVE VL 2960
4524 11:44:49.747483 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4525 11:44:49.747573 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4526 11:44:49.747655 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4527 11:44:49.747747 # ok 2797 Set Streaming SVE VL 2976
4528 11:44:49.748042 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4529 11:44:49.748151 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4530 11:44:49.748257 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4531 11:44:49.748344 # ok 2801 Set Streaming SVE VL 2992
4532 11:44:49.748429 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4533 11:44:49.748529 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4534 11:44:49.748893 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4535 11:44:49.748996 # ok 2805 Set Streaming SVE VL 3008
4536 11:44:49.749083 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4537 11:44:49.749365 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4538 11:44:49.749470 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4539 11:44:49.749558 # ok 2809 Set Streaming SVE VL 3024
4540 11:44:49.749670 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4541 11:44:49.749759 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4542 11:44:49.749842 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4543 11:44:49.749926 # ok 2813 Set Streaming SVE VL 3040
4544 11:44:49.750024 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4545 11:44:49.750111 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4546 11:44:49.750196 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4547 11:44:49.750293 # ok 2817 Set Streaming SVE VL 3056
4548 11:44:49.750393 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4549 11:44:49.750480 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4550 11:44:49.750580 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4551 11:44:49.750680 # ok 2821 Set Streaming SVE VL 3072
4552 11:44:49.750781 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4553 11:44:49.751090 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4554 11:44:49.751218 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4555 11:44:49.751320 # ok 2825 Set Streaming SVE VL 3088
4556 11:44:49.751418 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4557 11:44:49.751530 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4558 11:44:49.751647 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4559 11:44:49.751747 # ok 2829 Set Streaming SVE VL 3104
4560 11:44:49.751874 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4561 11:44:49.752063 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4562 11:44:49.752170 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4563 11:44:49.752293 # ok 2833 Set Streaming SVE VL 3120
4564 11:44:49.752407 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4565 11:44:49.753362 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4566 11:44:49.753677 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4567 11:44:49.753783 # ok 2837 Set Streaming SVE VL 3136
4568 11:44:49.753891 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4569 11:44:49.753994 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4570 11:44:49.754191 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4571 11:44:49.754519 # ok 2841 Set Streaming SVE VL 3152
4572 11:44:49.754626 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4573 11:44:49.754731 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4574 11:44:49.754819 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4575 11:44:49.754917 # ok 2845 Set Streaming SVE VL 3168
4576 11:44:49.755016 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4577 11:44:49.755115 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4578 11:44:49.755445 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4579 11:44:49.755557 # ok 2849 Set Streaming SVE VL 3184
4580 11:44:49.755644 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4581 11:44:49.755743 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4582 11:44:49.755847 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4583 11:44:49.755938 # ok 2853 Set Streaming SVE VL 3200
4584 11:44:49.756041 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4585 11:44:49.756157 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4586 11:44:49.756267 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4587 11:44:49.756366 # ok 2857 Set Streaming SVE VL 3216
4588 11:44:49.757145 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4589 11:44:49.757558 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4590 11:44:49.757667 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4591 11:44:49.757749 # ok 2861 Set Streaming SVE VL 3232
4592 11:44:49.757840 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4593 11:44:49.758164 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4594 11:44:49.758263 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4595 11:44:49.758342 # ok 2865 Set Streaming SVE VL 3248
4596 11:44:49.758432 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4597 11:44:49.758524 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4598 11:44:49.758603 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4599 11:44:49.758693 # ok 2869 Set Streaming SVE VL 3264
4600 11:44:49.758772 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4601 11:44:49.758861 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4602 11:44:49.759184 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4603 11:44:49.759292 # ok 2873 Set Streaming SVE VL 3280
4604 11:44:49.759392 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4605 11:44:49.759478 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4606 11:44:49.759578 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4607 11:44:49.759664 # ok 2877 Set Streaming SVE VL 3296
4608 11:44:49.768279 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4609 11:44:49.768718 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4610 11:44:49.783313 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4611 11:44:49.783556 # ok 2881 Set Streaming SVE VL 3312
4612 11:44:49.783858 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4613 11:44:49.783959 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4614 11:44:49.784041 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4615 11:44:49.784133 # ok 2885 Set Streaming SVE VL 3328
4616 11:44:49.784216 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4617 11:44:49.784312 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4618 11:44:49.784405 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4619 11:44:49.791983 # ok 2889 Set Streaming SVE VL 3344
4620 11:44:49.792438 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4621 11:44:49.792528 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4622 11:44:49.792609 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4623 11:44:49.794015 # ok 2893 Set Streaming SVE VL 3360
4624 11:44:49.794313 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4625 11:44:49.794411 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4626 11:44:49.794696 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4627 11:44:49.794781 # ok 2897 Set Streaming SVE VL 3376
4628 11:44:49.794871 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4629 11:44:49.795161 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4630 11:44:49.795277 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4631 11:44:49.795363 # ok 2901 Set Streaming SVE VL 3392
4632 11:44:49.795448 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4633 11:44:49.795734 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4634 11:44:49.795838 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4635 11:44:49.795915 # ok 2905 Set Streaming SVE VL 3408
4636 11:44:49.796007 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4637 11:44:49.796285 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4638 11:44:49.796373 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4639 11:44:49.796463 # ok 2909 Set Streaming SVE VL 3424
4640 11:44:49.802142 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4641 11:44:49.802587 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4642 11:44:49.802674 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4643 11:44:49.802753 # ok 2913 Set Streaming SVE VL 3440
4644 11:44:49.802843 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4645 11:44:49.802936 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4646 11:44:49.803028 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4647 11:44:49.803120 # ok 2917 Set Streaming SVE VL 3456
4648 11:44:49.803441 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4649 11:44:49.803554 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4650 11:44:49.803648 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4651 11:44:49.803740 # ok 2921 Set Streaming SVE VL 3472
4652 11:44:49.803831 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4653 11:44:49.804110 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4654 11:44:49.804207 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4655 11:44:49.804307 # ok 2925 Set Streaming SVE VL 3488
4656 11:44:49.804577 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4657 11:44:49.810387 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4658 11:44:49.810613 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4659 11:44:49.810707 # ok 2929 Set Streaming SVE VL 3504
4660 11:44:49.810787 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4661 11:44:49.810878 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4662 11:44:49.811156 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4663 11:44:49.811252 # ok 2933 Set Streaming SVE VL 3520
4664 11:44:49.811348 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4665 11:44:49.811621 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4666 11:44:49.811718 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4667 11:44:49.811808 # ok 2937 Set Streaming SVE VL 3536
4668 11:44:49.811898 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4669 11:44:49.812175 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4670 11:44:49.812273 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4671 11:44:49.812365 # ok 2941 Set Streaming SVE VL 3552
4672 11:44:49.818538 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4673 11:44:49.819004 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4674 11:44:49.819111 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4675 11:44:49.819197 # ok 2945 Set Streaming SVE VL 3568
4676 11:44:49.819277 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4677 11:44:49.819373 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4678 11:44:49.819454 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4679 11:44:49.819531 # ok 2949 Set Streaming SVE VL 3584
4680 11:44:49.819632 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4681 11:44:49.819714 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4682 11:44:49.819807 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4683 11:44:49.819900 # ok 2953 Set Streaming SVE VL 3600
4684 11:44:49.820196 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4685 11:44:49.820297 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4686 11:44:49.820599 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4687 11:44:49.820701 # ok 2957 Set Streaming SVE VL 3616
4688 11:44:49.821384 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4689 11:44:49.821720 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4690 11:44:49.822065 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4691 11:44:49.822179 # ok 2961 Set Streaming SVE VL 3632
4692 11:44:49.822511 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4693 11:44:49.822629 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4694 11:44:49.822728 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4695 11:44:49.823065 # ok 2965 Set Streaming SVE VL 3648
4696 11:44:49.823178 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4697 11:44:49.830274 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4698 11:44:49.830517 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4699 11:44:49.830851 # ok 2969 Set Streaming SVE VL 3664
4700 11:44:49.830952 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4701 11:44:49.831037 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4702 11:44:49.831119 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4703 11:44:49.831201 # ok 2973 Set Streaming SVE VL 3680
4704 11:44:49.831301 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4705 11:44:49.831459 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4706 11:44:49.831591 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4707 11:44:49.831701 # ok 2977 Set Streaming SVE VL 3696
4708 11:44:49.831843 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4709 11:44:49.831932 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4710 11:44:49.832032 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4711 11:44:49.833763 # ok 2981 Set Streaming SVE VL 3712
4712 11:44:49.833872 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4713 11:44:49.833952 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4714 11:44:49.834029 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4715 11:44:49.834108 # ok 2985 Set Streaming SVE VL 3728
4716 11:44:49.838516 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4717 11:44:49.838915 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4718 11:44:49.839000 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4719 11:44:49.839078 # ok 2989 Set Streaming SVE VL 3744
4720 11:44:49.839168 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4721 11:44:49.839259 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4722 11:44:49.839545 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4723 11:44:49.839639 # ok 2993 Set Streaming SVE VL 3760
4724 11:44:49.839729 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4725 11:44:49.840008 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4726 11:44:49.840102 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4727 11:44:49.840466 # ok 2997 Set Streaming SVE VL 3776
4728 11:44:49.840582 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4729 11:44:49.841555 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4730 11:44:49.841871 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4731 11:44:49.842026 # ok 3001 Set Streaming SVE VL 3792
4732 11:44:49.842183 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4733 11:44:49.842321 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4734 11:44:49.842479 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4735 11:44:49.842612 # ok 3005 Set Streaming SVE VL 3808
4736 11:44:49.842771 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4737 11:44:49.842931 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4738 11:44:49.843056 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4739 11:44:49.843192 # ok 3009 Set Streaming SVE VL 3824
4740 11:44:49.843403 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4741 11:44:49.843572 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4742 11:44:49.843731 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4743 11:44:49.843892 # ok 3013 Set Streaming SVE VL 3840
4744 11:44:49.844046 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4745 11:44:49.844199 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4746 11:44:49.844304 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4747 11:44:49.844426 # ok 3017 Set Streaming SVE VL 3856
4748 11:44:49.844552 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4749 11:44:49.844655 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4750 11:44:49.851082 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4751 11:44:49.851449 # ok 3021 Set Streaming SVE VL 3872
4752 11:44:49.851541 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4753 11:44:49.851637 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4754 11:44:49.851716 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4755 11:44:49.851806 # ok 3025 Set Streaming SVE VL 3888
4756 11:44:49.851905 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4757 11:44:49.863905 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4758 11:44:49.864079 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4759 11:44:49.864173 # ok 3029 Set Streaming SVE VL 3904
4760 11:44:49.864268 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4761 11:44:49.864348 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4762 11:44:49.864443 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4763 11:44:49.867855 # ok 3033 Set Streaming SVE VL 3920
4764 11:44:49.868200 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4765 11:44:49.868299 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4766 11:44:49.868397 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4767 11:44:49.868489 # ok 3037 Set Streaming SVE VL 3936
4768 11:44:49.869633 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4769 11:44:49.869943 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4770 11:44:49.870043 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4771 11:44:49.870137 # ok 3041 Set Streaming SVE VL 3952
4772 11:44:49.870230 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4773 11:44:49.870543 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4774 11:44:49.870642 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4775 11:44:49.870734 # ok 3045 Set Streaming SVE VL 3968
4776 11:44:49.870825 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4777 11:44:49.870916 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4778 11:44:49.871191 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4779 11:44:49.871274 # ok 3049 Set Streaming SVE VL 3984
4780 11:44:49.871364 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4781 11:44:49.871782 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4782 11:44:49.871883 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4783 11:44:49.873723 # ok 3053 Set Streaming SVE VL 4000
4784 11:44:49.874017 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4785 11:44:49.874101 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4786 11:44:49.874180 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4787 11:44:49.874258 # ok 3057 Set Streaming SVE VL 4016
4788 11:44:49.874334 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4789 11:44:49.881992 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4790 11:44:49.882377 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4791 11:44:49.882492 # ok 3061 Set Streaming SVE VL 4032
4792 11:44:49.882582 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4793 11:44:49.882684 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4794 11:44:49.882771 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4795 11:44:49.882871 # ok 3065 Set Streaming SVE VL 4048
4796 11:44:49.882957 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4797 11:44:49.883257 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4798 11:44:49.883362 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4799 11:44:49.883469 # ok 3069 Set Streaming SVE VL 4064
4800 11:44:49.883770 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4801 11:44:49.883873 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4802 11:44:49.883955 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4803 11:44:49.884048 # ok 3073 Set Streaming SVE VL 4080
4804 11:44:49.884129 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4805 11:44:49.884220 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4806 11:44:49.884313 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4807 11:44:49.884405 # ok 3077 Set Streaming SVE VL 4096
4808 11:44:49.890338 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4809 11:44:49.890727 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4810 11:44:49.890829 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4811 11:44:49.890923 # ok 3081 Set Streaming SVE VL 4112
4812 11:44:49.891002 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4813 11:44:49.891091 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4814 11:44:49.891182 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4815 11:44:49.891403 # ok 3085 Set Streaming SVE VL 4128
4816 11:44:49.891521 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4817 11:44:49.891815 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4818 11:44:49.891917 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4819 11:44:49.892011 # ok 3089 Set Streaming SVE VL 4144
4820 11:44:49.892106 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4821 11:44:49.892189 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4822 11:44:49.892280 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4823 11:44:49.892370 # ok 3093 Set Streaming SVE VL 4160
4824 11:44:49.893280 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4825 11:44:49.893701 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4826 11:44:49.893897 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4827 11:44:49.894060 # ok 3097 Set Streaming SVE VL 4176
4828 11:44:49.894212 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4829 11:44:49.894337 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4830 11:44:49.894457 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4831 11:44:49.894595 # ok 3101 Set Streaming SVE VL 4192
4832 11:44:49.894717 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4833 11:44:49.894856 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4834 11:44:49.894996 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4835 11:44:49.895120 # ok 3105 Set Streaming SVE VL 4208
4836 11:44:49.895259 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4837 11:44:49.895402 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4838 11:44:49.895596 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4839 11:44:49.895802 # ok 3109 Set Streaming SVE VL 4224
4840 11:44:49.895963 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4841 11:44:49.896141 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4842 11:44:49.896279 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4843 11:44:49.896422 # ok 3113 Set Streaming SVE VL 4240
4844 11:44:49.896596 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4845 11:44:49.896772 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4846 11:44:49.902207 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4847 11:44:49.902686 # ok 3117 Set Streaming SVE VL 4256
4848 11:44:49.902867 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4849 11:44:49.903034 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4850 11:44:49.903233 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4851 11:44:49.903468 # ok 3121 Set Streaming SVE VL 4272
4852 11:44:49.903687 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4853 11:44:49.903870 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4854 11:44:49.904072 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4855 11:44:49.904241 # ok 3125 Set Streaming SVE VL 4288
4856 11:44:49.904417 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4857 11:44:49.904584 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4858 11:44:49.904715 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4859 11:44:49.904830 # ok 3129 Set Streaming SVE VL 4304
4860 11:44:49.904989 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4861 11:44:49.905113 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4862 11:44:49.905229 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4863 11:44:49.908375 # ok 3133 Set Streaming SVE VL 4320
4864 11:44:49.914273 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4865 11:44:49.914607 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4866 11:44:49.914712 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4867 11:44:49.914808 # ok 3137 Set Streaming SVE VL 4336
4868 11:44:49.914891 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4869 11:44:49.914983 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4870 11:44:49.915276 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4871 11:44:49.915378 # ok 3141 Set Streaming SVE VL 4352
4872 11:44:49.915476 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4873 11:44:49.915757 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4874 11:44:49.915850 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4875 11:44:49.915942 # ok 3145 Set Streaming SVE VL 4368
4876 11:44:49.916035 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4877 11:44:49.916308 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4878 11:44:49.916404 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4879 11:44:49.921938 # ok 3149 Set Streaming SVE VL 4384
4880 11:44:49.922286 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4881 11:44:49.922451 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4882 11:44:49.922783 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4883 11:44:49.922931 # ok 3153 Set Streaming SVE VL 4400
4884 11:44:49.923107 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4885 11:44:49.923244 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4886 11:44:49.923417 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4887 11:44:49.923559 # ok 3157 Set Streaming SVE VL 4416
4888 11:44:49.923734 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4889 11:44:49.923873 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4890 11:44:49.924016 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4891 11:44:49.924160 # ok 3161 Set Streaming SVE VL 4432
4892 11:44:49.924333 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4893 11:44:49.924496 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4894 11:44:49.924635 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4895 11:44:49.924777 # ok 3165 Set Streaming SVE VL 4448
4896 11:44:49.924950 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4897 11:44:49.929481 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4898 11:44:49.929969 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4899 11:44:49.930148 # ok 3169 Set Streaming SVE VL 4464
4900 11:44:49.930271 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4901 11:44:49.930411 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4902 11:44:49.930532 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4903 11:44:49.930648 # ok 3173 Set Streaming SVE VL 4480
4904 11:44:49.930764 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4905 11:44:49.930901 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4906 11:44:49.931020 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4907 11:44:49.931925 # ok 3177 Set Streaming SVE VL 4496
4908 11:44:49.932090 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4909 11:44:49.932241 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4910 11:44:49.932408 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4911 11:44:49.932554 # ok 3181 Set Streaming SVE VL 4512
4912 11:44:49.945592 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4913 11:44:49.945842 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4914 11:44:49.946260 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4915 11:44:49.946365 # ok 3185 Set Streaming SVE VL 4528
4916 11:44:49.946447 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4917 11:44:49.946526 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4918 11:44:49.946624 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4919 11:44:49.946704 # ok 3189 Set Streaming SVE VL 4544
4920 11:44:49.946793 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4921 11:44:49.946884 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4922 11:44:49.947178 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4923 11:44:49.947281 # ok 3193 Set Streaming SVE VL 4560
4924 11:44:49.947374 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4925 11:44:49.947475 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4926 11:44:49.947782 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4927 11:44:49.947880 # ok 3197 Set Streaming SVE VL 4576
4928 11:44:49.947980 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4929 11:44:49.948074 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4930 11:44:49.948358 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4931 11:44:49.948452 # ok 3201 Set Streaming SVE VL 4592
4932 11:44:49.948542 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4933 11:44:49.965955 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4934 11:44:49.966350 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4935 11:44:49.966455 # ok 3205 Set Streaming SVE VL 4608
4936 11:44:49.966538 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4937 11:44:49.966631 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4938 11:44:49.967227 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4939 11:44:49.967329 # ok 3209 Set Streaming SVE VL 4624
4940 11:44:49.967425 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4941 11:44:49.967528 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4942 11:44:49.967625 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4943 11:44:49.967706 # ok 3213 Set Streaming SVE VL 4640
4944 11:44:49.967799 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4945 11:44:49.967879 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4946 11:44:49.967955 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4947 11:44:49.968032 # ok 3217 Set Streaming SVE VL 4656
4948 11:44:49.968121 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4949 11:44:49.968200 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4950 11:44:49.968289 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4951 11:44:49.968368 # ok 3221 Set Streaming SVE VL 4672
4952 11:44:49.979640 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4953 11:44:49.979955 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4954 11:44:49.980316 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4955 11:44:49.980447 # ok 3225 Set Streaming SVE VL 4688
4956 11:44:49.980566 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4957 11:44:49.980683 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4958 11:44:49.982797 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4959 11:44:49.983138 # ok 3229 Set Streaming SVE VL 4704
4960 11:44:49.983250 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4961 11:44:49.983359 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4962 11:44:49.983443 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4963 11:44:49.983538 # ok 3233 Set Streaming SVE VL 4720
4964 11:44:49.985784 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4965 11:44:49.986013 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4966 11:44:49.986180 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4967 11:44:49.986340 # ok 3237 Set Streaming SVE VL 4736
4968 11:44:49.986488 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4969 11:44:49.986621 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4970 11:44:49.986739 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4971 11:44:49.986856 # ok 3241 Set Streaming SVE VL 4752
4972 11:44:49.986972 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4973 11:44:49.987087 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4974 11:44:49.987210 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4975 11:44:49.987583 # ok 3245 Set Streaming SVE VL 4768
4976 11:44:49.987790 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4977 11:44:49.987936 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4978 11:44:49.988079 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4979 11:44:49.988221 # ok 3249 Set Streaming SVE VL 4784
4980 11:44:49.988362 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4981 11:44:49.988504 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4982 11:44:49.988644 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4983 11:44:49.988790 # ok 3253 Set Streaming SVE VL 4800
4984 11:44:49.988932 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4985 11:44:49.989074 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4986 11:44:49.989216 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4987 11:44:49.989358 # ok 3257 Set Streaming SVE VL 4816
4988 11:44:49.989536 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4989 11:44:49.989685 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4990 11:44:49.989832 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4991 11:44:49.989975 # ok 3261 Set Streaming SVE VL 4832
4992 11:44:49.990116 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4993 11:44:50.010368 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4994 11:44:50.010908 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4995 11:44:50.011017 # ok 3265 Set Streaming SVE VL 4848
4996 11:44:50.011106 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4997 11:44:50.011192 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4998 11:44:50.011295 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4999 11:44:50.011386 # ok 3269 Set Streaming SVE VL 4864
5000 11:44:50.011471 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
5001 11:44:50.011583 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
5002 11:44:50.011673 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5003 11:44:50.011772 # ok 3273 Set Streaming SVE VL 4880
5004 11:44:50.011900 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5005 11:44:50.011996 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5006 11:44:50.012098 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5007 11:44:50.012182 # ok 3277 Set Streaming SVE VL 4896
5008 11:44:50.012291 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5009 11:44:50.012569 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5010 11:44:50.021859 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5011 11:44:50.022273 # ok 3281 Set Streaming SVE VL 4912
5012 11:44:50.022476 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5013 11:44:50.022643 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5014 11:44:50.022842 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5015 11:44:50.023042 # ok 3285 Set Streaming SVE VL 4928
5016 11:44:50.023221 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5017 11:44:50.023412 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5018 11:44:50.023582 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5019 11:44:50.023843 # ok 3289 Set Streaming SVE VL 4944
5020 11:44:50.024050 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5021 11:44:50.024241 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5022 11:44:50.024403 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5023 11:44:50.024543 # ok 3293 Set Streaming SVE VL 4960
5024 11:44:50.024662 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5025 11:44:50.024777 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5026 11:44:50.024921 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5027 11:44:50.025043 # ok 3297 Set Streaming SVE VL 4976
5028 11:44:50.025160 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5029 11:44:50.025277 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5030 11:44:50.038442 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5031 11:44:50.038668 # ok 3301 Set Streaming SVE VL 4992
5032 11:44:50.038964 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5033 11:44:50.039068 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5034 11:44:50.039148 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5035 11:44:50.039225 # ok 3305 Set Streaming SVE VL 5008
5036 11:44:50.039302 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5037 11:44:50.039400 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5038 11:44:50.039482 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5039 11:44:50.039562 # ok 3309 Set Streaming SVE VL 5024
5040 11:44:50.039656 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5041 11:44:50.039736 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5042 11:44:50.039830 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5043 11:44:50.039910 # ok 3313 Set Streaming SVE VL 5040
5044 11:44:50.040224 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5045 11:44:50.040326 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5046 11:44:50.040419 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5047 11:44:50.040499 # ok 3317 Set Streaming SVE VL 5056
5048 11:44:50.040575 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5049 11:44:50.047730 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5050 11:44:50.047962 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5051 11:44:50.048272 # ok 3321 Set Streaming SVE VL 5072
5052 11:44:50.048376 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5053 11:44:50.048466 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5054 11:44:50.048565 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5055 11:44:50.048651 # ok 3325 Set Streaming SVE VL 5088
5056 11:44:50.048740 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5057 11:44:50.051203 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5058 11:44:50.051355 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5059 11:44:50.051457 # ok 3329 Set Streaming SVE VL 5104
5060 11:44:50.051745 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5061 11:44:50.051838 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5062 11:44:50.051941 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5063 11:44:50.052046 # ok 3333 Set Streaming SVE VL 5120
5064 11:44:50.052148 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5065 11:44:50.057793 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5066 11:44:50.058378 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5067 11:44:50.058576 # ok 3337 Set Streaming SVE VL 5136
5068 11:44:50.058785 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5069 11:44:50.058983 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5070 11:44:50.059195 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5071 11:44:50.059360 # ok 3341 Set Streaming SVE VL 5152
5072 11:44:50.059508 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5073 11:44:50.059664 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5074 11:44:50.059819 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5075 11:44:50.060027 # ok 3345 Set Streaming SVE VL 5168
5076 11:44:50.060203 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5077 11:44:50.060390 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5078 11:44:50.060558 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5079 11:44:50.060684 # ok 3349 Set Streaming SVE VL 5184
5080 11:44:50.060828 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5081 11:44:50.060972 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5082 11:44:50.061091 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5083 11:44:50.061208 # ok 3353 Set Streaming SVE VL 5200
5084 11:44:50.061323 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5085 11:44:50.061440 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5086 11:44:50.061554 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5087 11:44:50.065955 # ok 3357 Set Streaming SVE VL 5216
5088 11:44:50.066404 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5089 11:44:50.066516 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5090 11:44:50.066608 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5091 11:44:50.066715 # ok 3361 Set Streaming SVE VL 5232
5092 11:44:50.066805 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5093 11:44:50.066902 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5094 11:44:50.067007 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5095 11:44:50.067095 # ok 3365 Set Streaming SVE VL 5248
5096 11:44:50.067193 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5097 11:44:50.067295 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5098 11:44:50.067398 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5099 11:44:50.067701 # ok 3369 Set Streaming SVE VL 5264
5100 11:44:50.067805 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5101 11:44:50.067893 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5102 11:44:50.067993 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5103 11:44:50.068080 # ok 3373 Set Streaming SVE VL 5280
5104 11:44:50.068178 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5105 11:44:50.068277 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5106 11:44:50.074255 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5107 11:44:50.074717 # ok 3377 Set Streaming SVE VL 5296
5108 11:44:50.074825 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5109 11:44:50.074914 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5110 11:44:50.075018 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5111 11:44:50.075108 # ok 3381 Set Streaming SVE VL 5312
5112 11:44:50.075210 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5113 11:44:50.075309 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5114 11:44:50.075610 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5115 11:44:50.075714 # ok 3385 Set Streaming SVE VL 5328
5116 11:44:50.075815 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5117 11:44:50.076121 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5118 11:44:50.076224 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5119 11:44:50.076321 # ok 3389 Set Streaming SVE VL 5344
5120 11:44:50.077281 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5121 11:44:50.077637 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5122 11:44:50.077749 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5123 11:44:50.077854 # ok 3393 Set Streaming SVE VL 5360
5124 11:44:50.077957 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5125 11:44:50.078043 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5126 11:44:50.078142 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5127 11:44:50.078243 # ok 3397 Set Streaming SVE VL 5376
5128 11:44:50.078605 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5129 11:44:50.078796 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5130 11:44:50.078896 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5131 11:44:50.078998 # ok 3401 Set Streaming SVE VL 5392
5132 11:44:50.079101 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5133 11:44:50.079404 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5134 11:44:50.079509 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5135 11:44:50.079608 # ok 3405 Set Streaming SVE VL 5408
5136 11:44:50.079705 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5137 11:44:50.079806 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5138 11:44:50.080104 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5139 11:44:50.080206 # ok 3409 Set Streaming SVE VL 5424
5140 11:44:50.080304 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5141 11:44:50.089790 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5142 11:44:50.090304 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5143 11:44:50.090550 # ok 3413 Set Streaming SVE VL 5440
5144 11:44:50.090762 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5145 11:44:50.090940 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5146 11:44:50.091131 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5147 11:44:50.091305 # ok 3417 Set Streaming SVE VL 5456
5148 11:44:50.091470 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5149 11:44:50.091635 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5150 11:44:50.091799 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5151 11:44:50.091961 # ok 3421 Set Streaming SVE VL 5472
5152 11:44:50.092120 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5153 11:44:50.092317 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5154 11:44:50.092455 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5155 11:44:50.092573 # ok 3425 Set Streaming SVE VL 5488
5156 11:44:50.092692 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5157 11:44:50.092810 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5158 11:44:50.092928 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5159 11:44:50.093046 # ok 3429 Set Streaming SVE VL 5504
5160 11:44:50.093161 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5161 11:44:50.099235 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5162 11:44:50.099697 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5163 11:44:50.099805 # ok 3433 Set Streaming SVE VL 5520
5164 11:44:50.099900 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5165 11:44:50.100002 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5166 11:44:50.100090 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5167 11:44:50.100190 # ok 3437 Set Streaming SVE VL 5536
5168 11:44:50.100297 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5169 11:44:50.100583 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5170 11:44:50.105905 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5171 11:44:50.106398 # ok 3441 Set Streaming SVE VL 5552
5172 11:44:50.106598 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5173 11:44:50.106771 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5174 11:44:50.106936 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5175 11:44:50.107104 # ok 3445 Set Streaming SVE VL 5568
5176 11:44:50.107297 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5177 11:44:50.107463 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5178 11:44:50.107623 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5179 11:44:50.107777 # ok 3449 Set Streaming SVE VL 5584
5180 11:44:50.107942 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5181 11:44:50.108109 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5182 11:44:50.108310 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5183 11:44:50.108489 # ok 3453 Set Streaming SVE VL 5600
5184 11:44:50.108616 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5185 11:44:50.108735 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5186 11:44:50.108852 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5187 11:44:50.108971 # ok 3457 Set Streaming SVE VL 5616
5188 11:44:50.109087 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5189 11:44:50.109203 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5190 11:44:50.109319 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5191 11:44:50.109435 # ok 3461 Set Streaming SVE VL 5632
5192 11:44:50.113983 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5193 11:44:50.114305 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5194 11:44:50.114703 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5195 11:44:50.114812 # ok 3465 Set Streaming SVE VL 5648
5196 11:44:50.114903 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5197 11:44:50.114985 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5198 11:44:50.115071 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5199 11:44:50.115171 # ok 3469 Set Streaming SVE VL 5664
5200 11:44:50.115258 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5201 11:44:50.115341 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5202 11:44:50.115439 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5203 11:44:50.115523 # ok 3473 Set Streaming SVE VL 5680
5204 11:44:50.115619 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5205 11:44:50.115716 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5206 11:44:50.122282 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5207 11:44:50.122507 # ok 3477 Set Streaming SVE VL 5696
5208 11:44:50.122599 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5209 11:44:50.122699 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5210 11:44:50.122785 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5211 11:44:50.122868 # ok 3481 Set Streaming SVE VL 5712
5212 11:44:50.122967 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5213 11:44:50.123067 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5214 11:44:50.123168 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5215 11:44:50.123265 # ok 3485 Set Streaming SVE VL 5728
5216 11:44:50.123362 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5217 11:44:50.123460 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5218 11:44:50.123851 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5219 11:44:50.123952 # ok 3489 Set Streaming SVE VL 5744
5220 11:44:50.124054 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5221 11:44:50.124141 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5222 11:44:50.124392 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5223 11:44:50.133223 # ok 3493 Set Streaming SVE VL 5760
5224 11:44:50.133686 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5225 11:44:50.133796 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5226 11:44:50.133889 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5227 11:44:50.133979 # ok 3497 Set Streaming SVE VL 5776
5228 11:44:50.134092 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5229 11:44:50.134181 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5230 11:44:50.134266 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5231 11:44:50.134367 # ok 3501 Set Streaming SVE VL 5792
5232 11:44:50.134454 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5233 11:44:50.134541 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5234 11:44:50.134643 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5235 11:44:50.134732 # ok 3505 Set Streaming SVE VL 5808
5236 11:44:50.134840 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5237 11:44:50.134943 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5238 11:44:50.135245 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5239 11:44:50.135365 # ok 3509 Set Streaming SVE VL 5824
5240 11:44:50.135473 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5241 11:44:50.135577 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5242 11:44:50.135869 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5243 11:44:50.135963 # ok 3513 Set Streaming SVE VL 5840
5244 11:44:50.136063 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5245 11:44:50.136166 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5246 11:44:50.144003 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5247 11:44:50.144243 # ok 3517 Set Streaming SVE VL 5856
5248 11:44:50.144544 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5249 11:44:50.144648 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5250 11:44:50.144738 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5251 11:44:50.147811 # ok 3521 Set Streaming SVE VL 5872
5252 11:44:50.148256 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5253 11:44:50.148362 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5254 11:44:50.148464 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5255 11:44:50.148550 # ok 3525 Set Streaming SVE VL 5888
5256 11:44:50.157808 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5257 11:44:50.158053 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5258 11:44:50.158358 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5259 11:44:50.158460 # ok 3529 Set Streaming SVE VL 5904
5260 11:44:50.158549 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5261 11:44:50.158639 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5262 11:44:50.158737 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5263 11:44:50.158823 # ok 3533 Set Streaming SVE VL 5920
5264 11:44:50.158920 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5265 11:44:50.159019 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5266 11:44:50.159255 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5267 11:44:50.159376 # ok 3537 Set Streaming SVE VL 5936
5268 11:44:50.159683 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5269 11:44:50.159790 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5270 11:44:50.159905 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5271 11:44:50.160013 # ok 3541 Set Streaming SVE VL 5952
5272 11:44:50.160314 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5273 11:44:50.165792 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5274 11:44:50.166257 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5275 11:44:50.166358 # ok 3545 Set Streaming SVE VL 5968
5276 11:44:50.166448 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5277 11:44:50.166535 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5278 11:44:50.166640 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5279 11:44:50.166725 # ok 3549 Set Streaming SVE VL 5984
5280 11:44:50.166811 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5281 11:44:50.166914 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5282 11:44:50.167216 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5283 11:44:50.167323 # ok 3553 Set Streaming SVE VL 6000
5284 11:44:50.167424 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5285 11:44:50.167724 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5286 11:44:50.167845 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5287 11:44:50.167951 # ok 3557 Set Streaming SVE VL 6016
5288 11:44:50.168259 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5289 11:44:50.168354 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5290 11:44:50.177905 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5291 11:44:50.178368 # ok 3561 Set Streaming SVE VL 6032
5292 11:44:50.178473 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5293 11:44:50.178564 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5294 11:44:50.178668 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5295 11:44:50.178758 # ok 3565 Set Streaming SVE VL 6048
5296 11:44:50.178863 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5297 11:44:50.178957 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5298 11:44:50.179058 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5299 11:44:50.179160 # ok 3569 Set Streaming SVE VL 6064
5300 11:44:50.179460 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5301 11:44:50.179818 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5302 11:44:50.180024 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5303 11:44:50.180236 # ok 3573 Set Streaming SVE VL 6080
5304 11:44:50.180412 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5305 11:44:50.180537 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5306 11:44:50.180656 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5307 11:44:50.180769 # ok 3577 Set Streaming SVE VL 6096
5308 11:44:50.193888 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5309 11:44:50.194356 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5310 11:44:50.194462 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5311 11:44:50.194549 # ok 3581 Set Streaming SVE VL 6112
5312 11:44:50.194650 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5313 11:44:50.194737 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5314 11:44:50.194820 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5315 11:44:50.194918 # ok 3585 Set Streaming SVE VL 6128
5316 11:44:50.195001 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5317 11:44:50.195097 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5318 11:44:50.195203 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5319 11:44:50.195303 # ok 3589 Set Streaming SVE VL 6144
5320 11:44:50.195402 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5321 11:44:50.195737 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5322 11:44:50.195858 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5323 11:44:50.195943 # ok 3593 Set Streaming SVE VL 6160
5324 11:44:50.196043 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5325 11:44:50.196139 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5326 11:44:50.196355 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5327 11:44:50.196477 # ok 3597 Set Streaming SVE VL 6176
5328 11:44:50.204353 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5329 11:44:50.209760 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5330 11:44:50.210374 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5331 11:44:50.210481 # ok 3601 Set Streaming SVE VL 6192
5332 11:44:50.210566 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5333 11:44:50.210646 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5334 11:44:50.210725 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5335 11:44:50.210804 # ok 3605 Set Streaming SVE VL 6208
5336 11:44:50.210898 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5337 11:44:50.210980 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5338 11:44:50.211060 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5339 11:44:50.211153 # ok 3609 Set Streaming SVE VL 6224
5340 11:44:50.211235 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5341 11:44:50.211327 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5342 11:44:50.211636 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5343 11:44:50.211816 # ok 3613 Set Streaming SVE VL 6240
5344 11:44:50.211985 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5345 11:44:50.212120 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5346 11:44:50.212324 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5347 11:44:50.212460 # ok 3617 Set Streaming SVE VL 6256
5348 11:44:50.221758 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5349 11:44:50.221951 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5350 11:44:50.222146 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5351 11:44:50.222387 # ok 3621 Set Streaming SVE VL 6272
5352 11:44:50.222582 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5353 11:44:50.222785 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5354 11:44:50.222922 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5355 11:44:50.223045 # ok 3625 Set Streaming SVE VL 6288
5356 11:44:50.223689 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5357 11:44:50.224131 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5358 11:44:50.224242 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5359 11:44:50.224334 # ok 3629 Set Streaming SVE VL 6304
5360 11:44:50.224436 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5361 11:44:50.230634 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5362 11:44:50.230987 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5363 11:44:50.231093 # ok 3633 Set Streaming SVE VL 6320
5364 11:44:50.231207 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5365 11:44:50.231505 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5366 11:44:50.231613 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5367 11:44:50.231703 # ok 3637 Set Streaming SVE VL 6336
5368 11:44:50.231811 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5369 11:44:50.231904 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5370 11:44:50.232010 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5371 11:44:50.232102 # ok 3641 Set Streaming SVE VL 6352
5372 11:44:50.232203 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5373 11:44:50.238239 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5374 11:44:50.238569 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5375 11:44:50.238677 # ok 3645 Set Streaming SVE VL 6368
5376 11:44:50.238764 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5377 11:44:50.238868 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5378 11:44:50.238973 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5379 11:44:50.239060 # ok 3649 Set Streaming SVE VL 6384
5380 11:44:50.239165 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5381 11:44:50.239264 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5382 11:44:50.239368 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5383 11:44:50.239699 # ok 3653 Set Streaming SVE VL 6400
5384 11:44:50.239807 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5385 11:44:50.239907 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5386 11:44:50.240042 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5387 11:44:50.240151 # ok 3657 Set Streaming SVE VL 6416
5388 11:44:50.240257 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5389 11:44:50.240352 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5390 11:44:50.241266 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5391 11:44:50.241667 # ok 3661 Set Streaming SVE VL 6432
5392 11:44:50.241889 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5393 11:44:50.242097 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5394 11:44:50.242236 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5395 11:44:50.242381 # ok 3665 Set Streaming SVE VL 6448
5396 11:44:50.242506 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5397 11:44:50.242649 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5398 11:44:50.242774 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5399 11:44:50.242918 # ok 3669 Set Streaming SVE VL 6464
5400 11:44:50.243044 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5401 11:44:50.243192 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5402 11:44:50.243317 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5403 11:44:50.243459 # ok 3673 Set Streaming SVE VL 6480
5404 11:44:50.243583 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5405 11:44:50.243725 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5406 11:44:50.243871 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5407 11:44:50.244573 # ok 3677 Set Streaming SVE VL 6496
5408 11:44:50.244728 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5409 11:44:50.244856 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5410 11:44:50.244982 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5411 11:44:50.258411 # ok 3681 Set Streaming SVE VL 6512
5412 11:44:50.259251 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5413 11:44:50.259482 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5414 11:44:50.259649 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5415 11:44:50.259804 # ok 3685 Set Streaming SVE VL 6528
5416 11:44:50.260022 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5417 11:44:50.260212 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5418 11:44:50.260388 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5419 11:44:50.260515 # ok 3689 Set Streaming SVE VL 6544
5420 11:44:50.260709 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5421 11:44:50.260849 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5422 11:44:50.260992 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5423 11:44:50.261115 # ok 3693 Set Streaming SVE VL 6560
5424 11:44:50.261255 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5425 11:44:50.261375 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5426 11:44:50.261513 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5427 11:44:50.261681 # ok 3697 Set Streaming SVE VL 6576
5428 11:44:50.261861 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5429 11:44:50.262006 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5430 11:44:50.262706 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5431 11:44:50.263113 # ok 3701 Set Streaming SVE VL 6592
5432 11:44:50.263216 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5433 11:44:50.263297 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5434 11:44:50.263576 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5435 11:44:50.263683 # ok 3705 Set Streaming SVE VL 6608
5436 11:44:50.263764 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5437 11:44:50.263857 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5438 11:44:50.263937 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5439 11:44:50.264013 # ok 3709 Set Streaming SVE VL 6624
5440 11:44:50.264102 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5441 11:44:50.264185 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5442 11:44:50.273401 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5443 11:44:50.273942 # ok 3713 Set Streaming SVE VL 6640
5444 11:44:50.274420 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5445 11:44:50.274626 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5446 11:44:50.274804 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5447 11:44:50.274992 # ok 3717 Set Streaming SVE VL 6656
5448 11:44:50.275206 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5449 11:44:50.275349 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5450 11:44:50.275495 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5451 11:44:50.275676 # ok 3721 Set Streaming SVE VL 6672
5452 11:44:50.275849 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5453 11:44:50.275995 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5454 11:44:50.276178 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5455 11:44:50.276317 # ok 3725 Set Streaming SVE VL 6688
5456 11:44:50.276461 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5457 11:44:50.276602 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5458 11:44:50.276744 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5459 11:44:50.276888 # ok 3729 Set Streaming SVE VL 6704
5460 11:44:50.277029 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5461 11:44:50.281450 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5462 11:44:50.282220 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5463 11:44:50.282407 # ok 3733 Set Streaming SVE VL 6720
5464 11:44:50.282596 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5465 11:44:50.282767 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5466 11:44:50.282926 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5467 11:44:50.283049 # ok 3737 Set Streaming SVE VL 6736
5468 11:44:50.283405 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5469 11:44:50.283606 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5470 11:44:50.283797 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5471 11:44:50.283954 # ok 3741 Set Streaming SVE VL 6752
5472 11:44:50.284127 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5473 11:44:50.284260 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5474 11:44:50.289981 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5475 11:44:50.290895 # ok 3745 Set Streaming SVE VL 6768
5476 11:44:50.290995 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5477 11:44:50.291096 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5478 11:44:50.291294 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5479 11:44:50.291417 # ok 3749 Set Streaming SVE VL 6784
5480 11:44:50.291521 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5481 11:44:50.291784 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5482 11:44:50.292103 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5483 11:44:50.292209 # ok 3753 Set Streaming SVE VL 6800
5484 11:44:50.292302 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5485 11:44:50.300224 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5486 11:44:50.301620 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5487 11:44:50.301731 # ok 3757 Set Streaming SVE VL 6816
5488 11:44:50.301825 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5489 11:44:50.302107 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5490 11:44:50.302211 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5491 11:44:50.302292 # ok 3761 Set Streaming SVE VL 6832
5492 11:44:50.302382 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5493 11:44:50.302462 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5494 11:44:50.302556 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5495 11:44:50.302647 # ok 3765 Set Streaming SVE VL 6848
5496 11:44:50.302926 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5497 11:44:50.303027 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5498 11:44:50.303120 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5499 11:44:50.303204 # ok 3769 Set Streaming SVE VL 6864
5500 11:44:50.303297 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5501 11:44:50.303518 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5502 11:44:50.303633 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5503 11:44:50.303713 # ok 3773 Set Streaming SVE VL 6880
5504 11:44:50.303802 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5505 11:44:50.312269 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5506 11:44:50.313584 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5507 11:44:50.313916 # ok 3777 Set Streaming SVE VL 6896
5508 11:44:50.314018 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5509 11:44:50.314118 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5510 11:44:50.314204 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5511 11:44:50.314306 # ok 3781 Set Streaming SVE VL 6912
5512 11:44:50.314390 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5513 11:44:50.314485 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5514 11:44:50.314778 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5515 11:44:50.314871 # ok 3785 Set Streaming SVE VL 6928
5516 11:44:50.314954 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5517 11:44:50.315038 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5518 11:44:50.315300 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5519 11:44:50.315394 # ok 3789 Set Streaming SVE VL 6944
5520 11:44:50.315500 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5521 11:44:50.315796 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5522 11:44:50.316072 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5523 11:44:50.316163 # ok 3793 Set Streaming SVE VL 6960
5524 11:44:50.316249 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5525 11:44:50.326835 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5526 11:44:50.326945 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5527 11:44:50.327019 # ok 3797 Set Streaming SVE VL 6976
5528 11:44:50.327270 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5529 11:44:50.327345 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5530 11:44:50.327449 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5531 11:44:50.327751 # ok 3801 Set Streaming SVE VL 6992
5532 11:44:50.327862 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5533 11:44:50.327972 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5534 11:44:50.328258 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5535 11:44:50.335255 # ok 3805 Set Streaming SVE VL 7008
5536 11:44:50.335728 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5537 11:44:50.335846 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5538 11:44:50.335936 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5539 11:44:50.336026 # ok 3809 Set Streaming SVE VL 7024
5540 11:44:50.336126 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5541 11:44:50.336215 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5542 11:44:50.337073 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5543 11:44:50.337374 # ok 3813 Set Streaming SVE VL 7040
5544 11:44:50.337490 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5545 11:44:50.337611 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5546 11:44:50.337933 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5547 11:44:50.338035 # ok 3817 Set Streaming SVE VL 7056
5548 11:44:50.338135 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5549 11:44:50.338438 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5550 11:44:50.338548 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5551 11:44:50.338655 # ok 3821 Set Streaming SVE VL 7072
5552 11:44:50.338761 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5553 11:44:50.338863 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5554 11:44:50.338971 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5555 11:44:50.339080 # ok 3825 Set Streaming SVE VL 7088
5556 11:44:50.339298 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5557 11:44:50.339419 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5558 11:44:50.339533 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5559 11:44:50.339639 # ok 3829 Set Streaming SVE VL 7104
5560 11:44:50.339743 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5561 11:44:50.339844 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5562 11:44:50.340151 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5563 11:44:50.340256 # ok 3833 Set Streaming SVE VL 7120
5564 11:44:50.344608 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5565 11:44:50.345021 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5566 11:44:50.345121 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5567 11:44:50.345210 # ok 3837 Set Streaming SVE VL 7136
5568 11:44:50.345317 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5569 11:44:50.345406 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5570 11:44:50.345504 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5571 11:44:50.345592 # ok 3841 Set Streaming SVE VL 7152
5572 11:44:50.345700 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5573 11:44:50.345800 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5574 11:44:50.345903 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5575 11:44:50.346200 # ok 3845 Set Streaming SVE VL 7168
5576 11:44:50.346303 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5577 11:44:50.346411 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5578 11:44:50.346511 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5579 11:44:50.346815 # ok 3849 Set Streaming SVE VL 7184
5580 11:44:50.346918 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5581 11:44:50.347019 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5582 11:44:50.347116 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5583 11:44:50.347420 # ok 3853 Set Streaming SVE VL 7200
5584 11:44:50.347523 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5585 11:44:50.347621 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5586 11:44:50.347719 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5587 11:44:50.347817 # ok 3857 Set Streaming SVE VL 7216
5588 11:44:50.352651 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5589 11:44:50.352807 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5590 11:44:50.352894 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5591 11:44:50.352993 # ok 3861 Set Streaming SVE VL 7232
5592 11:44:50.353079 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5593 11:44:50.353176 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5594 11:44:50.353293 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5595 11:44:50.353404 # ok 3865 Set Streaming SVE VL 7248
5596 11:44:50.353516 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5597 11:44:50.353631 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5598 11:44:50.353777 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5599 11:44:50.353903 # ok 3869 Set Streaming SVE VL 7264
5600 11:44:50.354029 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5601 11:44:50.354366 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5602 11:44:50.354462 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5603 11:44:50.354713 # ok 3873 Set Streaming SVE VL 7280
5604 11:44:50.354858 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5605 11:44:50.354974 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5606 11:44:50.355283 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5607 11:44:50.355390 # ok 3877 Set Streaming SVE VL 7296
5608 11:44:50.355654 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5609 11:44:50.355760 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5610 11:44:50.355862 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5611 11:44:50.355961 # ok 3881 Set Streaming SVE VL 7312
5612 11:44:50.356261 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5613 11:44:50.356988 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5614 11:44:50.357290 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5615 11:44:50.357395 # ok 3885 Set Streaming SVE VL 7328
5616 11:44:50.357488 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5617 11:44:50.357790 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5618 11:44:50.357890 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5619 11:44:50.357986 # ok 3889 Set Streaming SVE VL 7344
5620 11:44:50.358094 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5621 11:44:50.358449 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5622 11:44:50.358551 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5623 11:44:50.358639 # ok 3893 Set Streaming SVE VL 7360
5624 11:44:50.358885 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5625 11:44:50.359002 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5626 11:44:50.359122 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5627 11:44:50.359232 # ok 3897 Set Streaming SVE VL 7376
5628 11:44:50.359356 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5629 11:44:50.359465 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5630 11:44:50.359589 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5631 11:44:50.359683 # ok 3901 Set Streaming SVE VL 7392
5632 11:44:50.359811 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5633 11:44:50.360366 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5634 11:44:50.360446 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5635 11:44:50.362635 # ok 3905 Set Streaming SVE VL 7408
5636 11:44:50.362989 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5637 11:44:50.363091 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5638 11:44:50.363195 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5639 11:44:50.363282 # ok 3909 Set Streaming SVE VL 7424
5640 11:44:50.363387 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5641 11:44:50.363724 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5642 11:44:50.363831 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5643 11:44:50.363929 # ok 3913 Set Streaming SVE VL 7440
5644 11:44:50.364064 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5645 11:44:50.364536 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5646 11:44:50.364840 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5647 11:44:50.364950 # ok 3917 Set Streaming SVE VL 7456
5648 11:44:50.365061 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5649 11:44:50.365155 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5650 11:44:50.365261 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5651 11:44:50.365353 # ok 3921 Set Streaming SVE VL 7472
5652 11:44:50.365463 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5653 11:44:50.365552 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5654 11:44:50.365669 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5655 11:44:50.366130 # ok 3925 Set Streaming SVE VL 7488
5656 11:44:50.366400 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5657 11:44:50.366472 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5658 11:44:50.366549 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5659 11:44:50.366615 # ok 3929 Set Streaming SVE VL 7504
5660 11:44:50.366860 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5661 11:44:50.366929 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5662 11:44:50.367005 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5663 11:44:50.367070 # ok 3933 Set Streaming SVE VL 7520
5664 11:44:50.367143 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5665 11:44:50.367391 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5666 11:44:50.367459 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5667 11:44:50.367535 # ok 3937 Set Streaming SVE VL 7536
5668 11:44:50.367611 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5669 11:44:50.367677 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5670 11:44:50.367928 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5671 11:44:50.367999 # ok 3941 Set Streaming SVE VL 7552
5672 11:44:50.368072 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5673 11:44:50.368148 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5674 11:44:50.372684 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5675 11:44:50.372869 # ok 3945 Set Streaming SVE VL 7568
5676 11:44:50.373133 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5677 11:44:50.373215 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5678 11:44:50.376421 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5679 11:44:50.376601 # ok 3949 Set Streaming SVE VL 7584
5680 11:44:50.376669 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5681 11:44:50.376731 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5682 11:44:50.376793 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5683 11:44:50.376865 # ok 3953 Set Streaming SVE VL 7600
5684 11:44:50.376925 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5685 11:44:50.376986 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5686 11:44:50.377046 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5687 11:44:50.377106 # ok 3957 Set Streaming SVE VL 7616
5688 11:44:50.377165 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5689 11:44:50.377224 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5690 11:44:50.377284 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5691 11:44:50.377376 # ok 3961 Set Streaming SVE VL 7632
5692 11:44:50.377463 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5693 11:44:50.377552 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5694 11:44:50.377635 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5695 11:44:50.377729 # ok 3965 Set Streaming SVE VL 7648
5696 11:44:50.377813 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5697 11:44:50.377898 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5698 11:44:50.377984 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5699 11:44:50.378072 # ok 3969 Set Streaming SVE VL 7664
5700 11:44:50.378158 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5701 11:44:50.378240 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5702 11:44:50.378326 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5703 11:44:50.378411 # ok 3973 Set Streaming SVE VL 7680
5704 11:44:50.378498 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5705 11:44:50.378587 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5706 11:44:50.378677 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5707 11:44:50.378767 # ok 3977 Set Streaming SVE VL 7696
5708 11:44:50.378854 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5709 11:44:50.378942 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5710 11:44:50.379021 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5711 11:44:50.382192 # ok 3981 Set Streaming SVE VL 7712
5712 11:44:50.382613 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5713 11:44:50.382725 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5714 11:44:50.382840 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5715 11:44:50.382945 # ok 3985 Set Streaming SVE VL 7728
5716 11:44:50.383084 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5717 11:44:50.383193 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5718 11:44:50.383286 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5719 11:44:50.383355 # ok 3989 Set Streaming SVE VL 7744
5720 11:44:50.383419 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5721 11:44:50.383673 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5722 11:44:50.383754 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5723 11:44:50.383824 # ok 3993 Set Streaming SVE VL 7760
5724 11:44:50.383903 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5725 11:44:50.383983 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5726 11:44:50.384076 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5727 11:44:50.384152 # ok 3997 Set Streaming SVE VL 7776
5728 11:44:50.384229 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5729 11:44:50.386597 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5730 11:44:50.386918 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5731 11:44:50.387025 # ok 4001 Set Streaming SVE VL 7792
5732 11:44:50.387099 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5733 11:44:50.387174 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5734 11:44:50.387237 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5735 11:44:50.387487 # ok 4005 Set Streaming SVE VL 7808
5736 11:44:50.387597 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5737 11:44:50.387727 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5738 11:44:50.388134 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5739 11:44:50.388233 # ok 4009 Set Streaming SVE VL 7824
5740 11:44:50.388303 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5741 11:44:50.388694 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5742 11:44:50.389015 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5743 11:44:50.389139 # ok 4013 Set Streaming SVE VL 7840
5744 11:44:50.389227 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5745 11:44:50.389673 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5746 11:44:50.389774 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5747 11:44:50.389856 # ok 4017 Set Streaming SVE VL 7856
5748 11:44:50.389935 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5749 11:44:50.390216 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5750 11:44:50.390319 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5751 11:44:50.390392 # ok 4021 Set Streaming SVE VL 7872
5752 11:44:50.390468 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5753 11:44:50.390543 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5754 11:44:50.390623 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5755 11:44:50.390685 # ok 4025 Set Streaming SVE VL 7888
5756 11:44:50.390745 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5757 11:44:50.391113 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5758 11:44:50.391201 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5759 11:44:50.391304 # ok 4029 Set Streaming SVE VL 7904
5760 11:44:50.391405 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5761 11:44:50.391514 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5762 11:44:50.391812 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5763 11:44:50.391903 # ok 4033 Set Streaming SVE VL 7920
5764 11:44:50.392007 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5765 11:44:50.392108 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5766 11:44:50.392200 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5767 11:44:50.392276 # ok 4037 Set Streaming SVE VL 7936
5768 11:44:50.392352 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5769 11:44:50.392422 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5770 11:44:50.392483 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5771 11:44:50.392543 # ok 4041 Set Streaming SVE VL 7952
5772 11:44:50.396956 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5773 11:44:50.397179 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5774 11:44:50.397289 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5775 11:44:50.397392 # ok 4045 Set Streaming SVE VL 7968
5776 11:44:50.397518 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5777 11:44:50.397639 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5778 11:44:50.397768 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5779 11:44:50.397892 # ok 4049 Set Streaming SVE VL 7984
5780 11:44:50.398019 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5781 11:44:50.398154 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5782 11:44:50.398504 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5783 11:44:50.398606 # ok 4053 Set Streaming SVE VL 8000
5784 11:44:50.398699 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5785 11:44:50.399015 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5786 11:44:50.399124 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5787 11:44:50.399240 # ok 4057 Set Streaming SVE VL 8016
5788 11:44:50.399359 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5789 11:44:50.399480 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5790 11:44:50.399798 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5791 11:44:50.399920 # ok 4061 Set Streaming SVE VL 8032
5792 11:44:50.400036 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5793 11:44:50.417042 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5794 11:44:50.417469 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5795 11:44:50.417573 # ok 4065 Set Streaming SVE VL 8048
5796 11:44:50.417670 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5797 11:44:50.417775 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5798 11:44:50.417863 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5799 11:44:50.417950 # ok 4069 Set Streaming SVE VL 8064
5800 11:44:50.418048 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5801 11:44:50.418387 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5802 11:44:50.418509 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5803 11:44:50.418599 # ok 4073 Set Streaming SVE VL 8080
5804 11:44:50.418696 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5805 11:44:50.421218 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5806 11:44:50.421404 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5807 11:44:50.421501 # ok 4077 Set Streaming SVE VL 8096
5808 11:44:50.421590 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5809 11:44:50.421689 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5810 11:44:50.429398 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5811 11:44:50.429632 # ok 4081 Set Streaming SVE VL 8112
5812 11:44:50.429977 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5813 11:44:50.430215 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5814 11:44:50.430399 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5815 11:44:50.430576 # ok 4085 Set Streaming SVE VL 8128
5816 11:44:50.430781 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5817 11:44:50.430952 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5818 11:44:50.431155 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5819 11:44:50.431354 # ok 4089 Set Streaming SVE VL 8144
5820 11:44:50.431488 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5821 11:44:50.431632 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5822 11:44:50.431827 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5823 11:44:50.431991 # ok 4093 Set Streaming SVE VL 8160
5824 11:44:50.432152 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5825 11:44:50.432281 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5826 11:44:50.432399 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5827 11:44:50.432514 # ok 4097 Set Streaming SVE VL 8176
5828 11:44:50.432629 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5829 11:44:50.432770 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5830 11:44:50.432892 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5831 11:44:50.433008 # ok 4101 Set Streaming SVE VL 8192
5832 11:44:50.435319 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5833 11:44:50.435754 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5834 11:44:50.435862 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5835 11:44:50.435951 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5836 11:44:50.436036 ok 30 selftests: arm64: sve-ptrace
5837 11:44:50.436136 # selftests: arm64: sve-probe-vls
5838 11:44:50.436222 # TAP version 13
5839 11:44:50.436307 # 1..2
5840 11:44:50.436392 # ok 1 Enumerated 16 vector lengths
5841 11:44:50.440733 # ok 2 All vector lengths valid
5842 11:44:50.440939 # # 16
5843 11:44:50.441029 # # 32
5844 11:44:50.441114 # # 48
5845 11:44:50.441195 # # 64
5846 11:44:50.441488 # # 80
5847 11:44:50.441590 # # 96
5848 11:44:50.441684 # # 112
5849 11:44:50.441767 # # 128
5850 11:44:50.441851 # # 144
5851 11:44:50.441936 # # 160
5852 11:44:50.442021 # # 176
5853 11:44:50.442103 # # 192
5854 11:44:50.442188 # # 208
5855 11:44:50.442274 # # 224
5856 11:44:50.442363 # # 240
5857 11:44:50.442451 # # 256
5858 11:44:50.442543 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5859 11:44:50.442629 ok 31 selftests: arm64: sve-probe-vls
5860 11:44:50.442734 # selftests: arm64: vec-syscfg
5861 11:44:51.285656 # TAP version 13
5862 11:44:51.285934 # 1..20
5863 11:44:51.286248 # ok 1 SVE default vector length 64
5864 11:44:51.286362 # ok 2 SVE minimum vector length 16
5865 11:44:51.286455 # ok 3 SVE maximum vector length 256
5866 11:44:51.286543 # ok 4 SVE current VL is 64
5867 11:44:51.286629 # ok 5 SVE set VL 64 and have VL 64
5868 11:44:51.286730 # ok 6 SVE prctl() set min/max
5869 11:44:51.287069 # ok 7 SVE vector length used default
5870 11:44:51.287177 # ok 8 SVE vector length was inherited
5871 11:44:51.287265 # ok 9 SVE vector length set on exec
5872 11:44:51.287349 # ok 10 SVE prctl() set all VLs, 0 errors
5873 11:44:51.287432 # ok 11 SME default vector length 32
5874 11:44:51.287515 # ok 12 SME minimum vector length 16
5875 11:44:51.287596 # ok 13 SME maximum vector length 256
5876 11:44:51.287678 # ok 14 SME current VL is 32
5877 11:44:51.287763 # ok 15 SME set VL 32 and have VL 32
5878 11:44:51.287844 # ok 16 SME prctl() set min/max
5879 11:44:51.287944 # ok 17 SME vector length used default
5880 11:44:51.288030 # ok 18 SME vector length was inherited
5881 11:44:51.288111 # ok 19 SME vector length set on exec
5882 11:44:51.288193 # ok 20 SME prctl() set all VLs, 0 errors
5883 11:44:51.288275 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5884 11:44:51.300887 ok 32 selftests: arm64: vec-syscfg
5885 11:44:51.397439 # selftests: arm64: za-fork
5886 11:44:51.562141 # TAP version 13
5887 11:44:51.562342 # 1..1
5888 11:44:51.562626 # # PID: 1019
5889 11:44:51.562724 # ok 1 fork_test
5890 11:44:51.562814 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5891 11:44:51.595613 ok 33 selftests: arm64: za-fork
5892 11:44:51.734545 # selftests: arm64: za-ptrace
5893 11:44:51.879245 # TAP version 13
5894 11:44:51.879482 # 1..1536
5895 11:44:51.879787 # # Parent is 1037, child is 1038
5896 11:44:51.879889 # ok 1 Set VL 16
5897 11:44:51.879979 # ok 2 Disabled ZA for VL 16
5898 11:44:51.880067 # ok 3 Data match for VL 16
5899 11:44:51.880688 # ok 4 Set VL 32
5900 11:44:51.881156 # ok 5 Disabled ZA for VL 32
5901 11:44:51.881369 # ok 6 Data match for VL 32
5902 11:44:51.881558 # ok 7 Set VL 48
5903 11:44:51.881748 # ok 8 # SKIP Disabled ZA for VL 48
5904 11:44:51.881942 # ok 9 # SKIP Get and set data for VL 48
5905 11:44:51.882110 # ok 10 Set VL 64
5906 11:44:51.882285 # ok 11 Disabled ZA for VL 64
5907 11:44:51.882500 # ok 12 Data match for VL 64
5908 11:44:51.882710 # ok 13 Set VL 80
5909 11:44:51.882883 # ok 14 # SKIP Disabled ZA for VL 80
5910 11:44:51.883050 # ok 15 # SKIP Get and set data for VL 80
5911 11:44:51.883212 # ok 16 Set VL 96
5912 11:44:51.883417 # ok 17 # SKIP Disabled ZA for VL 96
5913 11:44:51.883561 # ok 18 # SKIP Get and set data for VL 96
5914 11:44:51.883682 # ok 19 Set VL 112
5915 11:44:51.883796 # ok 20 # SKIP Disabled ZA for VL 112
5916 11:44:51.883910 # ok 21 # SKIP Get and set data for VL 112
5917 11:44:51.884047 # ok 22 Set VL 128
5918 11:44:51.884222 # ok 23 Disabled ZA for VL 128
5919 11:44:51.884369 # ok 24 Data match for VL 128
5920 11:44:51.884531 # ok 25 Set VL 144
5921 11:44:51.884706 # ok 26 # SKIP Disabled ZA for VL 144
5922 11:44:51.884878 # ok 27 # SKIP Get and set data for VL 144
5923 11:44:51.885066 # ok 28 Set VL 160
5924 11:44:51.885203 # ok 29 # SKIP Disabled ZA for VL 160
5925 11:44:51.885319 # ok 30 # SKIP Get and set data for VL 160
5926 11:44:51.885432 # ok 31 Set VL 176
5927 11:44:51.885545 # ok 32 # SKIP Disabled ZA for VL 176
5928 11:44:51.885710 # ok 33 # SKIP Get and set data for VL 176
5929 11:44:51.888067 # ok 34 Set VL 192
5930 11:44:51.888544 # ok 35 # SKIP Disabled ZA for VL 192
5931 11:44:51.888735 # ok 36 # SKIP Get and set data for VL 192
5932 11:44:51.888898 # ok 37 Set VL 208
5933 11:44:51.889058 # ok 38 # SKIP Disabled ZA for VL 208
5934 11:44:51.889206 # ok 39 # SKIP Get and set data for VL 208
5935 11:44:51.889416 # ok 40 Set VL 224
5936 11:44:51.889626 # ok 41 # SKIP Disabled ZA for VL 224
5937 11:44:51.889820 # ok 42 # SKIP Get and set data for VL 224
5938 11:44:51.889990 # ok 43 Set VL 240
5939 11:44:51.890153 # ok 44 # SKIP Disabled ZA for VL 240
5940 11:44:51.890318 # ok 45 # SKIP Get and set data for VL 240
5941 11:44:51.890479 # ok 46 Set VL 256
5942 11:44:51.890613 # ok 47 Disabled ZA for VL 256
5943 11:44:51.890772 # ok 48 Data match for VL 256
5944 11:44:51.890928 # ok 49 Set VL 272
5945 11:44:51.891088 # ok 50 # SKIP Disabled ZA for VL 272
5946 11:44:51.891290 # ok 51 # SKIP Get and set data for VL 272
5947 11:44:51.891444 # ok 52 Set VL 288
5948 11:44:51.891561 # ok 53 # SKIP Disabled ZA for VL 288
5949 11:44:51.891675 # ok 54 # SKIP Get and set data for VL 288
5950 11:44:51.891789 # ok 55 Set VL 304
5951 11:44:51.891901 # ok 56 # SKIP Disabled ZA for VL 304
5952 11:44:51.892014 # ok 57 # SKIP Get and set data for VL 304
5953 11:44:51.892127 # ok 58 Set VL 320
5954 11:44:51.892241 # ok 59 # SKIP Disabled ZA for VL 320
5955 11:44:51.892353 # ok 60 # SKIP Get and set data for VL 320
5956 11:44:51.892465 # ok 61 Set VL 336
5957 11:44:51.892576 # ok 62 # SKIP Disabled ZA for VL 336
5958 11:44:51.892688 # ok 63 # SKIP Get and set data for VL 336
5959 11:44:51.892801 # ok 64 Set VL 352
5960 11:44:51.892913 # ok 65 # SKIP Disabled ZA for VL 352
5961 11:44:51.893026 # ok 66 # SKIP Get and set data for VL 352
5962 11:44:51.893138 # ok 67 Set VL 368
5963 11:44:51.893252 # ok 68 # SKIP Disabled ZA for VL 368
5964 11:44:51.893366 # ok 69 # SKIP Get and set data for VL 368
5965 11:44:51.893478 # ok 70 Set VL 384
5966 11:44:51.893616 # ok 71 # SKIP Disabled ZA for VL 384
5967 11:44:51.898436 # ok 72 # SKIP Get and set data for VL 384
5968 11:44:51.898708 # ok 73 Set VL 400
5969 11:44:51.899100 # ok 74 # SKIP Disabled ZA for VL 400
5970 11:44:51.899209 # ok 75 # SKIP Get and set data for VL 400
5971 11:44:51.899300 # ok 76 Set VL 416
5972 11:44:51.899386 # ok 77 # SKIP Disabled ZA for VL 416
5973 11:44:51.899473 # ok 78 # SKIP Get and set data for VL 416
5974 11:44:51.899558 # ok 79 Set VL 432
5975 11:44:51.899642 # ok 80 # SKIP Disabled ZA for VL 432
5976 11:44:51.899725 # ok 81 # SKIP Get and set data for VL 432
5977 11:44:51.899810 # ok 82 Set VL 448
5978 11:44:51.899892 # ok 83 # SKIP Disabled ZA for VL 448
5979 11:44:51.899977 # ok 84 # SKIP Get and set data for VL 448
5980 11:44:51.900080 # ok 85 Set VL 464
5981 11:44:51.900167 # ok 86 # SKIP Disabled ZA for VL 464
5982 11:44:51.900256 # ok 87 # SKIP Get and set data for VL 464
5983 11:44:51.900340 # ok 88 Set VL 480
5984 11:44:51.900423 # ok 89 # SKIP Disabled ZA for VL 480
5985 11:44:51.900506 # ok 90 # SKIP Get and set data for VL 480
5986 11:44:51.900608 # ok 91 Set VL 496
5987 11:44:51.900694 # ok 92 # SKIP Disabled ZA for VL 496
5988 11:44:51.900778 # ok 93 # SKIP Get and set data for VL 496
5989 11:44:51.900862 # ok 94 Set VL 512
5990 11:44:51.900945 # ok 95 # SKIP Disabled ZA for VL 512
5991 11:44:51.901046 # ok 96 # SKIP Get and set data for VL 512
5992 11:44:51.901128 # ok 97 Set VL 528
5993 11:44:51.901211 # ok 98 # SKIP Disabled ZA for VL 528
5994 11:44:51.901294 # ok 99 # SKIP Get and set data for VL 528
5995 11:44:51.901376 # ok 100 Set VL 544
5996 11:44:51.901457 # ok 101 # SKIP Disabled ZA for VL 544
5997 11:44:51.901540 # ok 102 # SKIP Get and set data for VL 544
5998 11:44:51.901644 # ok 103 Set VL 560
5999 11:44:51.901739 # ok 104 # SKIP Disabled ZA for VL 560
6000 11:44:51.901821 # ok 105 # SKIP Get and set data for VL 560
6001 11:44:51.901902 # ok 106 Set VL 576
6002 11:44:51.901984 # ok 107 # SKIP Disabled ZA for VL 576
6003 11:44:51.902067 # ok 108 # SKIP Get and set data for VL 576
6004 11:44:51.902149 # ok 109 Set VL 592
6005 11:44:51.902250 # ok 110 # SKIP Disabled ZA for VL 592
6006 11:44:51.902336 # ok 111 # SKIP Get and set data for VL 592
6007 11:44:51.902417 # ok 112 Set VL 608
6008 11:44:51.902498 # ok 113 # SKIP Disabled ZA for VL 608
6009 11:44:51.902580 # ok 114 # SKIP Get and set data for VL 608
6010 11:44:51.902664 # ok 115 Set VL 624
6011 11:44:51.902746 # ok 116 # SKIP Disabled ZA for VL 624
6012 11:44:51.902848 # ok 117 # SKIP Get and set data for VL 624
6013 11:44:51.902935 # ok 118 Set VL 640
6014 11:44:51.903015 # ok 119 # SKIP Disabled ZA for VL 640
6015 11:44:51.903095 # ok 120 # SKIP Get and set data for VL 640
6016 11:44:51.903179 # ok 121 Set VL 656
6017 11:44:51.903266 # ok 122 # SKIP Disabled ZA for VL 656
6018 11:44:51.903364 # ok 123 # SKIP Get and set data for VL 656
6019 11:44:51.903453 # ok 124 Set VL 672
6020 11:44:51.914769 # ok 125 # SKIP Disabled ZA for VL 672
6021 11:44:51.915238 # ok 126 # SKIP Get and set data for VL 672
6022 11:44:51.915357 # ok 127 Set VL 688
6023 11:44:51.915455 # ok 128 # SKIP Disabled ZA for VL 688
6024 11:44:51.915528 # ok 129 # SKIP Get and set data for VL 688
6025 11:44:51.915592 # ok 130 Set VL 704
6026 11:44:51.915655 # ok 131 # SKIP Disabled ZA for VL 704
6027 11:44:51.915732 # ok 132 # SKIP Get and set data for VL 704
6028 11:44:51.915798 # ok 133 Set VL 720
6029 11:44:51.923291 # ok 134 # SKIP Disabled ZA for VL 720
6030 11:44:51.923791 # ok 135 # SKIP Get and set data for VL 720
6031 11:44:51.923941 # ok 136 Set VL 736
6032 11:44:51.924134 # ok 137 # SKIP Disabled ZA for VL 736
6033 11:44:51.924295 # ok 138 # SKIP Get and set data for VL 736
6034 11:44:51.924459 # ok 139 Set VL 752
6035 11:44:51.924671 # ok 140 # SKIP Disabled ZA for VL 752
6036 11:44:51.924873 # ok 141 # SKIP Get and set data for VL 752
6037 11:44:51.925053 # ok 142 Set VL 768
6038 11:44:51.925244 # ok 143 # SKIP Disabled ZA for VL 768
6039 11:44:51.925403 # ok 144 # SKIP Get and set data for VL 768
6040 11:44:51.925603 # ok 145 Set VL 784
6041 11:44:51.925785 # ok 146 # SKIP Disabled ZA for VL 784
6042 11:44:51.925938 # ok 147 # SKIP Get and set data for VL 784
6043 11:44:51.926060 # ok 148 Set VL 800
6044 11:44:51.926175 # ok 149 # SKIP Disabled ZA for VL 800
6045 11:44:51.926301 # ok 150 # SKIP Get and set data for VL 800
6046 11:44:51.926428 # ok 151 Set VL 816
6047 11:44:51.926550 # ok 152 # SKIP Disabled ZA for VL 816
6048 11:44:51.926674 # ok 153 # SKIP Get and set data for VL 816
6049 11:44:51.926797 # ok 154 Set VL 832
6050 11:44:51.926916 # ok 155 # SKIP Disabled ZA for VL 832
6051 11:44:51.927074 # ok 156 # SKIP Get and set data for VL 832
6052 11:44:51.927226 # ok 157 Set VL 848
6053 11:44:51.927369 # ok 158 # SKIP Disabled ZA for VL 848
6054 11:44:51.927500 # ok 159 # SKIP Get and set data for VL 848
6055 11:44:51.927618 # ok 160 Set VL 864
6056 11:44:51.927733 # ok 161 # SKIP Disabled ZA for VL 864
6057 11:44:51.927847 # ok 162 # SKIP Get and set data for VL 864
6058 11:44:51.927963 # ok 163 Set VL 880
6059 11:44:51.928078 # ok 164 # SKIP Disabled ZA for VL 880
6060 11:44:51.928202 # ok 165 # SKIP Get and set data for VL 880
6061 11:44:51.928330 # ok 166 Set VL 896
6062 11:44:51.928454 # ok 167 # SKIP Disabled ZA for VL 896
6063 11:44:51.928605 # ok 168 # SKIP Get and set data for VL 896
6064 11:44:51.928739 # ok 169 Set VL 912
6065 11:44:51.928863 # ok 170 # SKIP Disabled ZA for VL 912
6066 11:44:51.928985 # ok 171 # SKIP Get and set data for VL 912
6067 11:44:51.929108 # ok 172 Set VL 928
6068 11:44:51.929231 # ok 173 # SKIP Disabled ZA for VL 928
6069 11:44:51.934832 # ok 174 # SKIP Get and set data for VL 928
6070 11:44:51.935123 # ok 175 Set VL 944
6071 11:44:51.935569 # ok 176 # SKIP Disabled ZA for VL 944
6072 11:44:51.935732 # ok 177 # SKIP Get and set data for VL 944
6073 11:44:51.935947 # ok 178 Set VL 960
6074 11:44:51.936124 # ok 179 # SKIP Disabled ZA for VL 960
6075 11:44:51.936285 # ok 180 # SKIP Get and set data for VL 960
6076 11:44:51.936450 # ok 181 Set VL 976
6077 11:44:51.936640 # ok 182 # SKIP Disabled ZA for VL 976
6078 11:44:51.936809 # ok 183 # SKIP Get and set data for VL 976
6079 11:44:51.936971 # ok 184 Set VL 992
6080 11:44:51.937135 # ok 185 # SKIP Disabled ZA for VL 992
6081 11:44:51.937292 # ok 186 # SKIP Get and set data for VL 992
6082 11:44:51.937453 # ok 187 Set VL 1008
6083 11:44:51.937618 # ok 188 # SKIP Disabled ZA for VL 1008
6084 11:44:51.937881 # ok 189 # SKIP Get and set data for VL 1008
6085 11:44:51.938059 # ok 190 Set VL 1024
6086 11:44:51.938221 # ok 191 # SKIP Disabled ZA for VL 1024
6087 11:44:51.938382 # ok 192 # SKIP Get and set data for VL 1024
6088 11:44:51.938541 # ok 193 Set VL 1040
6089 11:44:51.938696 # ok 194 # SKIP Disabled ZA for VL 1040
6090 11:44:51.938850 # ok 195 # SKIP Get and set data for VL 1040
6091 11:44:51.939007 # ok 196 Set VL 1056
6092 11:44:51.939160 # ok 197 # SKIP Disabled ZA for VL 1056
6093 11:44:51.939302 # ok 198 # SKIP Get and set data for VL 1056
6094 11:44:51.939434 # ok 199 Set VL 1072
6095 11:44:51.939551 # ok 200 # SKIP Disabled ZA for VL 1072
6096 11:44:51.939666 # ok 201 # SKIP Get and set data for VL 1072
6097 11:44:51.939780 # ok 202 Set VL 1088
6098 11:44:51.939927 # ok 203 # SKIP Disabled ZA for VL 1088
6099 11:44:51.940049 # ok 204 # SKIP Get and set data for VL 1088
6100 11:44:51.940165 # ok 205 Set VL 1104
6101 11:44:51.940279 # ok 206 # SKIP Disabled ZA for VL 1104
6102 11:44:51.940395 # ok 207 # SKIP Get and set data for VL 1104
6103 11:44:51.940511 # ok 208 Set VL 1120
6104 11:44:51.940625 # ok 209 # SKIP Disabled ZA for VL 1120
6105 11:44:51.940739 # ok 210 # SKIP Get and set data for VL 1120
6106 11:44:51.940852 # ok 211 Set VL 1136
6107 11:44:51.940965 # ok 212 # SKIP Disabled ZA for VL 1136
6108 11:44:51.941079 # ok 213 # SKIP Get and set data for VL 1136
6109 11:44:51.941192 # ok 214 Set VL 1152
6110 11:44:51.941305 # ok 215 # SKIP Disabled ZA for VL 1152
6111 11:44:51.941420 # ok 216 # SKIP Get and set data for VL 1152
6112 11:44:51.941534 # ok 217 Set VL 1168
6113 11:44:51.942403 # ok 218 # SKIP Disabled ZA for VL 1168
6114 11:44:51.942577 # ok 219 # SKIP Get and set data for VL 1168
6115 11:44:51.946774 # ok 220 Set VL 1184
6116 11:44:51.947259 # ok 221 # SKIP Disabled ZA for VL 1184
6117 11:44:51.947374 # ok 222 # SKIP Get and set data for VL 1184
6118 11:44:51.947466 # ok 223 Set VL 1200
6119 11:44:51.947553 # ok 224 # SKIP Disabled ZA for VL 1200
6120 11:44:51.947637 # ok 225 # SKIP Get and set data for VL 1200
6121 11:44:51.947722 # ok 226 Set VL 1216
6122 11:44:51.947822 # ok 227 # SKIP Disabled ZA for VL 1216
6123 11:44:51.947912 # ok 228 # SKIP Get and set data for VL 1216
6124 11:44:51.948012 # ok 229 Set VL 1232
6125 11:44:51.948112 # ok 230 # SKIP Disabled ZA for VL 1232
6126 11:44:51.948195 # ok 231 # SKIP Get and set data for VL 1232
6127 11:44:51.948293 # ok 232 Set VL 1248
6128 11:44:51.948386 # ok 233 # SKIP Disabled ZA for VL 1248
6129 11:44:51.948484 # ok 234 # SKIP Get and set data for VL 1248
6130 11:44:51.948568 # ok 235 Set VL 1264
6131 11:44:51.948664 # ok 236 # SKIP Disabled ZA for VL 1264
6132 11:44:51.948751 # ok 237 # SKIP Get and set data for VL 1264
6133 11:44:51.948833 # ok 238 Set VL 1280
6134 11:44:51.948931 # ok 239 # SKIP Disabled ZA for VL 1280
6135 11:44:51.949016 # ok 240 # SKIP Get and set data for VL 1280
6136 11:44:51.949097 # ok 241 Set VL 1296
6137 11:44:51.949180 # ok 242 # SKIP Disabled ZA for VL 1296
6138 11:44:51.949280 # ok 243 # SKIP Get and set data for VL 1296
6139 11:44:51.949371 # ok 244 Set VL 1312
6140 11:44:51.949453 # ok 245 # SKIP Disabled ZA for VL 1312
6141 11:44:51.949550 # ok 246 # SKIP Get and set data for VL 1312
6142 11:44:51.949637 # ok 247 Set VL 1328
6143 11:44:51.949728 # ok 248 # SKIP Disabled ZA for VL 1328
6144 11:44:51.949811 # ok 249 # SKIP Get and set data for VL 1328
6145 11:44:51.949894 # ok 250 Set VL 1344
6146 11:44:51.949996 # ok 251 # SKIP Disabled ZA for VL 1344
6147 11:44:51.950082 # ok 252 # SKIP Get and set data for VL 1344
6148 11:44:51.950162 # ok 253 Set VL 1360
6149 11:44:51.950245 # ok 254 # SKIP Disabled ZA for VL 1360
6150 11:44:51.950331 # ok 255 # SKIP Get and set data for VL 1360
6151 11:44:51.950417 # ok 256 Set VL 1376
6152 11:44:51.950501 # ok 257 # SKIP Disabled ZA for VL 1376
6153 11:44:51.950606 # ok 258 # SKIP Get and set data for VL 1376
6154 11:44:51.950693 # ok 259 Set VL 1392
6155 11:44:51.950778 # ok 260 # SKIP Disabled ZA for VL 1392
6156 11:44:51.950862 # ok 261 # SKIP Get and set data for VL 1392
6157 11:44:51.950946 # ok 262 Set VL 1408
6158 11:44:51.951029 # ok 263 # SKIP Disabled ZA for VL 1408
6159 11:44:51.951115 # ok 264 # SKIP Get and set data for VL 1408
6160 11:44:51.951200 # ok 265 Set VL 1424
6161 11:44:51.951300 # ok 266 # SKIP Disabled ZA for VL 1424
6162 11:44:51.951383 # ok 267 # SKIP Get and set data for VL 1424
6163 11:44:51.951466 # ok 268 Set VL 1440
6164 11:44:51.951549 # ok 269 # SKIP Disabled ZA for VL 1440
6165 11:44:51.951633 # ok 270 # SKIP Get and set data for VL 1440
6166 11:44:51.951718 # ok 271 Set VL 1456
6167 11:44:51.951802 # ok 272 # SKIP Disabled ZA for VL 1456
6168 11:44:51.951883 # ok 273 # SKIP Get and set data for VL 1456
6169 11:44:51.951965 # ok 274 Set VL 1472
6170 11:44:51.952251 # ok 275 # SKIP Disabled ZA for VL 1472
6171 11:44:51.952344 # ok 276 # SKIP Get and set data for VL 1472
6172 11:44:51.952429 # ok 277 Set VL 1488
6173 11:44:51.952515 # ok 278 # SKIP Disabled ZA for VL 1488
6174 11:44:51.956571 # ok 279 # SKIP Get and set data for VL 1488
6175 11:44:51.956754 # ok 280 Set VL 1504
6176 11:44:51.957047 # ok 281 # SKIP Disabled ZA for VL 1504
6177 11:44:51.957142 # ok 282 # SKIP Get and set data for VL 1504
6178 11:44:51.957229 # ok 283 Set VL 1520
6179 11:44:51.957315 # ok 284 # SKIP Disabled ZA for VL 1520
6180 11:44:51.957401 # ok 285 # SKIP Get and set data for VL 1520
6181 11:44:51.957486 # ok 286 Set VL 1536
6182 11:44:51.957589 # ok 287 # SKIP Disabled ZA for VL 1536
6183 11:44:51.957687 # ok 288 # SKIP Get and set data for VL 1536
6184 11:44:51.957773 # ok 289 Set VL 1552
6185 11:44:51.957858 # ok 290 # SKIP Disabled ZA for VL 1552
6186 11:44:51.957944 # ok 291 # SKIP Get and set data for VL 1552
6187 11:44:51.958030 # ok 292 Set VL 1568
6188 11:44:51.958115 # ok 293 # SKIP Disabled ZA for VL 1568
6189 11:44:51.958200 # ok 294 # SKIP Get and set data for VL 1568
6190 11:44:51.958283 # ok 295 Set VL 1584
6191 11:44:51.958368 # ok 296 # SKIP Disabled ZA for VL 1584
6192 11:44:51.958474 # ok 297 # SKIP Get and set data for VL 1584
6193 11:44:51.958562 # ok 298 Set VL 1600
6194 11:44:51.958647 # ok 299 # SKIP Disabled ZA for VL 1600
6195 11:44:51.958732 # ok 300 # SKIP Get and set data for VL 1600
6196 11:44:51.958817 # ok 301 Set VL 1616
6197 11:44:51.958902 # ok 302 # SKIP Disabled ZA for VL 1616
6198 11:44:51.958986 # ok 303 # SKIP Get and set data for VL 1616
6199 11:44:51.959071 # ok 304 Set VL 1632
6200 11:44:51.959156 # ok 305 # SKIP Disabled ZA for VL 1632
6201 11:44:51.959241 # ok 306 # SKIP Get and set data for VL 1632
6202 11:44:51.959327 # ok 307 Set VL 1648
6203 11:44:51.959416 # ok 308 # SKIP Disabled ZA for VL 1648
6204 11:44:51.959522 # ok 309 # SKIP Get and set data for VL 1648
6205 11:44:51.959610 # ok 310 Set VL 1664
6206 11:44:51.959697 # ok 311 # SKIP Disabled ZA for VL 1664
6207 11:44:51.959783 # ok 312 # SKIP Get and set data for VL 1664
6208 11:44:51.959865 # ok 313 Set VL 1680
6209 11:44:51.959949 # ok 314 # SKIP Disabled ZA for VL 1680
6210 11:44:51.960034 # ok 315 # SKIP Get and set data for VL 1680
6211 11:44:51.960119 # ok 316 Set VL 1696
6212 11:44:51.960202 # ok 317 # SKIP Disabled ZA for VL 1696
6213 11:44:51.960284 # ok 318 # SKIP Get and set data for VL 1696
6214 11:44:51.960366 # ok 319 Set VL 1712
6215 11:44:51.960447 # ok 320 # SKIP Disabled ZA for VL 1712
6216 11:44:51.960531 # ok 321 # SKIP Get and set data for VL 1712
6217 11:44:51.960614 # ok 322 Set VL 1728
6218 11:44:51.963180 # ok 323 # SKIP Disabled ZA for VL 1728
6219 11:44:51.963518 # ok 324 # SKIP Get and set data for VL 1728
6220 11:44:51.963618 # ok 325 Set VL 1744
6221 11:44:51.963702 # ok 326 # SKIP Disabled ZA for VL 1744
6222 11:44:51.963784 # ok 327 # SKIP Get and set data for VL 1744
6223 11:44:51.963866 # ok 328 Set VL 1760
6224 11:44:52.011465 # ok 329 # SKIP Disabled ZA for VL 1760
6225 11:44:52.012776 # ok 330 # SKIP Get and set data for VL 1760
6226 11:44:52.012980 # ok 331 Set VL 1776
6227 11:44:52.013180 # ok 332 # SKIP Disabled ZA for VL 1776
6228 11:44:52.013378 # ok 333 # SKIP Get and set data for VL 1776
6229 11:44:52.013548 # ok 334 Set VL 1792
6230 11:44:52.013731 # ok 335 # SKIP Disabled ZA for VL 1792
6231 11:44:52.013923 # ok 336 # SKIP Get and set data for VL 1792
6232 11:44:52.014077 # ok 337 Set VL 1808
6233 11:44:52.014238 # ok 338 # SKIP Disabled ZA for VL 1808
6234 11:44:52.014380 # ok 339 # SKIP Get and set data for VL 1808
6235 11:44:52.014526 # ok 340 Set VL 1824
6236 11:44:52.014707 # ok 341 # SKIP Disabled ZA for VL 1824
6237 11:44:52.014850 # ok 342 # SKIP Get and set data for VL 1824
6238 11:44:52.014972 # ok 343 Set VL 1840
6239 11:44:52.015090 # ok 344 # SKIP Disabled ZA for VL 1840
6240 11:44:52.015209 # ok 345 # SKIP Get and set data for VL 1840
6241 11:44:52.015328 # ok 346 Set VL 1856
6242 11:44:52.015445 # ok 347 # SKIP Disabled ZA for VL 1856
6243 11:44:52.015563 # ok 348 # SKIP Get and set data for VL 1856
6244 11:44:52.015682 # ok 349 Set VL 1872
6245 11:44:52.015799 # ok 350 # SKIP Disabled ZA for VL 1872
6246 11:44:52.015916 # ok 351 # SKIP Get and set data for VL 1872
6247 11:44:52.016034 # ok 352 Set VL 1888
6248 11:44:52.016194 # ok 353 # SKIP Disabled ZA for VL 1888
6249 11:44:52.016329 # ok 354 # SKIP Get and set data for VL 1888
6250 11:44:52.016446 # ok 355 Set VL 1904
6251 11:44:52.016560 # ok 356 # SKIP Disabled ZA for VL 1904
6252 11:44:52.016746 # ok 357 # SKIP Get and set data for VL 1904
6253 11:44:52.016894 # ok 358 Set VL 1920
6254 11:44:52.050160 # ok 359 # SKIP Disabled ZA for VL 1920
6255 11:44:52.050481 # ok 360 # SKIP Get and set data for VL 1920
6256 11:44:52.050873 # ok 361 Set VL 1936
6257 11:44:52.051058 # ok 362 # SKIP Disabled ZA for VL 1936
6258 11:44:52.051209 # ok 363 # SKIP Get and set data for VL 1936
6259 11:44:52.051403 # ok 364 Set VL 1952
6260 11:44:52.051564 # ok 365 # SKIP Disabled ZA for VL 1952
6261 11:44:52.051708 # ok 366 # SKIP Get and set data for VL 1952
6262 11:44:52.051851 # ok 367 Set VL 1968
6263 11:44:52.051993 # ok 368 # SKIP Disabled ZA for VL 1968
6264 11:44:52.052135 # ok 369 # SKIP Get and set data for VL 1968
6265 11:44:52.052313 # ok 370 Set VL 1984
6266 11:44:52.052451 # ok 371 # SKIP Disabled ZA for VL 1984
6267 11:44:52.052593 # ok 372 # SKIP Get and set data for VL 1984
6268 11:44:52.052736 # ok 373 Set VL 2000
6269 11:44:52.052877 # ok 374 # SKIP Disabled ZA for VL 2000
6270 11:44:52.053019 # ok 375 # SKIP Get and set data for VL 2000
6271 11:44:52.053159 # ok 376 Set VL 2016
6272 11:44:52.056624 # ok 377 # SKIP Disabled ZA for VL 2016
6273 11:44:52.057134 # ok 378 # SKIP Get and set data for VL 2016
6274 11:44:52.057323 # ok 379 Set VL 2032
6275 11:44:52.057530 # ok 380 # SKIP Disabled ZA for VL 2032
6276 11:44:52.057750 # ok 381 # SKIP Get and set data for VL 2032
6277 11:44:52.057924 # ok 382 Set VL 2048
6278 11:44:52.058087 # ok 383 # SKIP Disabled ZA for VL 2048
6279 11:44:52.058244 # ok 384 # SKIP Get and set data for VL 2048
6280 11:44:52.058459 # ok 385 Set VL 2064
6281 11:44:52.058658 # ok 386 # SKIP Disabled ZA for VL 2064
6282 11:44:52.058874 # ok 387 # SKIP Get and set data for VL 2064
6283 11:44:52.059062 # ok 388 Set VL 2080
6284 11:44:52.059228 # ok 389 # SKIP Disabled ZA for VL 2080
6285 11:44:52.059378 # ok 390 # SKIP Get and set data for VL 2080
6286 11:44:52.059500 # ok 391 Set VL 2096
6287 11:44:52.059616 # ok 392 # SKIP Disabled ZA for VL 2096
6288 11:44:52.059731 # ok 393 # SKIP Get and set data for VL 2096
6289 11:44:52.059845 # ok 394 Set VL 2112
6290 11:44:52.059961 # ok 395 # SKIP Disabled ZA for VL 2112
6291 11:44:52.060142 # ok 396 # SKIP Get and set data for VL 2112
6292 11:44:52.060282 # ok 397 Set VL 2128
6293 11:44:52.060409 # ok 398 # SKIP Disabled ZA for VL 2128
6294 11:44:52.060572 # ok 399 # SKIP Get and set data for VL 2128
6295 11:44:52.060703 # ok 400 Set VL 2144
6296 11:44:52.060828 # ok 401 # SKIP Disabled ZA for VL 2144
6297 11:44:52.060952 # ok 402 # SKIP Get and set data for VL 2144
6298 11:44:52.061075 # ok 403 Set VL 2160
6299 11:44:52.061196 # ok 404 # SKIP Disabled ZA for VL 2160
6300 11:44:52.061320 # ok 405 # SKIP Get and set data for VL 2160
6301 11:44:52.061441 # ok 406 Set VL 2176
6302 11:44:52.064736 # ok 407 # SKIP Disabled ZA for VL 2176
6303 11:44:52.065137 # ok 408 # SKIP Get and set data for VL 2176
6304 11:44:52.065245 # ok 409 Set VL 2192
6305 11:44:52.065333 # ok 410 # SKIP Disabled ZA for VL 2192
6306 11:44:52.065418 # ok 411 # SKIP Get and set data for VL 2192
6307 11:44:52.065503 # ok 412 Set VL 2208
6308 11:44:52.065611 # ok 413 # SKIP Disabled ZA for VL 2208
6309 11:44:52.065710 # ok 414 # SKIP Get and set data for VL 2208
6310 11:44:52.065796 # ok 415 Set VL 2224
6311 11:44:52.065880 # ok 416 # SKIP Disabled ZA for VL 2224
6312 11:44:52.065982 # ok 417 # SKIP Get and set data for VL 2224
6313 11:44:52.066069 # ok 418 Set VL 2240
6314 11:44:52.066154 # ok 419 # SKIP Disabled ZA for VL 2240
6315 11:44:52.066241 # ok 420 # SKIP Get and set data for VL 2240
6316 11:44:52.066330 # ok 421 Set VL 2256
6317 11:44:52.066431 # ok 422 # SKIP Disabled ZA for VL 2256
6318 11:44:52.066520 # ok 423 # SKIP Get and set data for VL 2256
6319 11:44:52.066608 # ok 424 Set VL 2272
6320 11:44:52.066693 # ok 425 # SKIP Disabled ZA for VL 2272
6321 11:44:52.066797 # ok 426 # SKIP Get and set data for VL 2272
6322 11:44:52.066885 # ok 427 Set VL 2288
6323 11:44:52.066971 # ok 428 # SKIP Disabled ZA for VL 2288
6324 11:44:52.067058 # ok 429 # SKIP Get and set data for VL 2288
6325 11:44:52.067144 # ok 430 Set VL 2304
6326 11:44:52.067247 # ok 431 # SKIP Disabled ZA for VL 2304
6327 11:44:52.067336 # ok 432 # SKIP Get and set data for VL 2304
6328 11:44:52.067420 # ok 433 Set VL 2320
6329 11:44:52.067503 # ok 434 # SKIP Disabled ZA for VL 2320
6330 11:44:52.067591 # ok 435 # SKIP Get and set data for VL 2320
6331 11:44:52.067690 # ok 436 Set VL 2336
6332 11:44:52.067774 # ok 437 # SKIP Disabled ZA for VL 2336
6333 11:44:52.073077 # ok 438 # SKIP Get and set data for VL 2336
6334 11:44:52.073316 # ok 439 Set VL 2352
6335 11:44:52.073413 # ok 440 # SKIP Disabled ZA for VL 2352
6336 11:44:52.073715 # ok 441 # SKIP Get and set data for VL 2352
6337 11:44:52.073824 # ok 442 Set VL 2368
6338 11:44:52.073914 # ok 443 # SKIP Disabled ZA for VL 2368
6339 11:44:52.074001 # ok 444 # SKIP Get and set data for VL 2368
6340 11:44:52.074087 # ok 445 Set VL 2384
6341 11:44:52.074172 # ok 446 # SKIP Disabled ZA for VL 2384
6342 11:44:52.074275 # ok 447 # SKIP Get and set data for VL 2384
6343 11:44:52.074362 # ok 448 Set VL 2400
6344 11:44:52.074447 # ok 449 # SKIP Disabled ZA for VL 2400
6345 11:44:52.074531 # ok 450 # SKIP Get and set data for VL 2400
6346 11:44:52.074617 # ok 451 Set VL 2416
6347 11:44:52.074717 # ok 452 # SKIP Disabled ZA for VL 2416
6348 11:44:52.074803 # ok 453 # SKIP Get and set data for VL 2416
6349 11:44:52.074888 # ok 454 Set VL 2432
6350 11:44:52.074969 # ok 455 # SKIP Disabled ZA for VL 2432
6351 11:44:52.075068 # ok 456 # SKIP Get and set data for VL 2432
6352 11:44:52.075152 # ok 457 Set VL 2448
6353 11:44:52.075232 # ok 458 # SKIP Disabled ZA for VL 2448
6354 11:44:52.075326 # ok 459 # SKIP Get and set data for VL 2448
6355 11:44:52.075416 # ok 460 Set VL 2464
6356 11:44:52.081112 # ok 461 # SKIP Disabled ZA for VL 2464
6357 11:44:52.081490 # ok 462 # SKIP Get and set data for VL 2464
6358 11:44:52.081714 # ok 463 Set VL 2480
6359 11:44:52.081886 # ok 464 # SKIP Disabled ZA for VL 2480
6360 11:44:52.082062 # ok 465 # SKIP Get and set data for VL 2480
6361 11:44:52.082231 # ok 466 Set VL 2496
6362 11:44:52.082402 # ok 467 # SKIP Disabled ZA for VL 2496
6363 11:44:52.082571 # ok 468 # SKIP Get and set data for VL 2496
6364 11:44:52.082744 # ok 469 Set VL 2512
6365 11:44:52.082944 # ok 470 # SKIP Disabled ZA for VL 2512
6366 11:44:52.083109 # ok 471 # SKIP Get and set data for VL 2512
6367 11:44:52.083258 # ok 472 Set VL 2528
6368 11:44:52.083385 # ok 473 # SKIP Disabled ZA for VL 2528
6369 11:44:52.083502 # ok 474 # SKIP Get and set data for VL 2528
6370 11:44:52.083619 # ok 475 Set VL 2544
6371 11:44:52.083766 # ok 476 # SKIP Disabled ZA for VL 2544
6372 11:44:52.083889 # ok 477 # SKIP Get and set data for VL 2544
6373 11:44:52.084007 # ok 478 Set VL 2560
6374 11:44:52.084122 # ok 479 # SKIP Disabled ZA for VL 2560
6375 11:44:52.084238 # ok 480 # SKIP Get and set data for VL 2560
6376 11:44:52.084353 # ok 481 Set VL 2576
6377 11:44:52.084467 # ok 482 # SKIP Disabled ZA for VL 2576
6378 11:44:52.084581 # ok 483 # SKIP Get and set data for VL 2576
6379 11:44:52.084695 # ok 484 Set VL 2592
6380 11:44:52.084810 # ok 485 # SKIP Disabled ZA for VL 2592
6381 11:44:52.084924 # ok 486 # SKIP Get and set data for VL 2592
6382 11:44:52.087015 # ok 487 Set VL 2608
6383 11:44:52.087377 # ok 488 # SKIP Disabled ZA for VL 2608
6384 11:44:52.087482 # ok 489 # SKIP Get and set data for VL 2608
6385 11:44:52.087574 # ok 490 Set VL 2624
6386 11:44:52.093043 # ok 491 # SKIP Disabled ZA for VL 2624
6387 11:44:52.093502 # ok 492 # SKIP Get and set data for VL 2624
6388 11:44:52.093708 # ok 493 Set VL 2640
6389 11:44:52.093873 # ok 494 # SKIP Disabled ZA for VL 2640
6390 11:44:52.094024 # ok 495 # SKIP Get and set data for VL 2640
6391 11:44:52.094171 # ok 496 Set VL 2656
6392 11:44:52.094354 # ok 497 # SKIP Disabled ZA for VL 2656
6393 11:44:52.094520 # ok 498 # SKIP Get and set data for VL 2656
6394 11:44:52.094747 # ok 499 Set VL 2672
6395 11:44:52.094962 # ok 500 # SKIP Disabled ZA for VL 2672
6396 11:44:52.095190 # ok 501 # SKIP Get and set data for VL 2672
6397 11:44:52.095389 # ok 502 Set VL 2688
6398 11:44:52.095535 # ok 503 # SKIP Disabled ZA for VL 2688
6399 11:44:52.095658 # ok 504 # SKIP Get and set data for VL 2688
6400 11:44:52.095775 # ok 505 Set VL 2704
6401 11:44:52.095893 # ok 506 # SKIP Disabled ZA for VL 2704
6402 11:44:52.096041 # ok 507 # SKIP Get and set data for VL 2704
6403 11:44:52.096168 # ok 508 Set VL 2720
6404 11:44:52.096286 # ok 509 # SKIP Disabled ZA for VL 2720
6405 11:44:52.096404 # ok 510 # SKIP Get and set data for VL 2720
6406 11:44:52.096522 # ok 511 Set VL 2736
6407 11:44:52.096638 # ok 512 # SKIP Disabled ZA for VL 2736
6408 11:44:52.096752 # ok 513 # SKIP Get and set data for VL 2736
6409 11:44:52.096864 # ok 514 Set VL 2752
6410 11:44:52.096976 # ok 515 # SKIP Disabled ZA for VL 2752
6411 11:44:52.097089 # ok 516 # SKIP Get and set data for VL 2752
6412 11:44:52.097202 # ok 517 Set VL 2768
6413 11:44:52.097314 # ok 518 # SKIP Disabled ZA for VL 2768
6414 11:44:52.100697 # ok 519 # SKIP Get and set data for VL 2768
6415 11:44:52.100969 # ok 520 Set VL 2784
6416 11:44:52.101421 # ok 521 # SKIP Disabled ZA for VL 2784
6417 11:44:52.101624 # ok 522 # SKIP Get and set data for VL 2784
6418 11:44:52.101855 # ok 523 Set VL 2800
6419 11:44:52.102056 # ok 524 # SKIP Disabled ZA for VL 2800
6420 11:44:52.102264 # ok 525 # SKIP Get and set data for VL 2800
6421 11:44:52.102489 # ok 526 Set VL 2816
6422 11:44:52.102721 # ok 527 # SKIP Disabled ZA for VL 2816
6423 11:44:52.102978 # ok 528 # SKIP Get and set data for VL 2816
6424 11:44:52.103193 # ok 529 Set VL 2832
6425 11:44:52.103409 # ok 530 # SKIP Disabled ZA for VL 2832
6426 11:44:52.103576 # ok 531 # SKIP Get and set data for VL 2832
6427 11:44:52.103713 # ok 532 Set VL 2848
6428 11:44:52.103833 # ok 533 # SKIP Disabled ZA for VL 2848
6429 11:44:52.103951 # ok 534 # SKIP Get and set data for VL 2848
6430 11:44:52.104069 # ok 535 Set VL 2864
6431 11:44:52.104185 # ok 536 # SKIP Disabled ZA for VL 2864
6432 11:44:52.104302 # ok 537 # SKIP Get and set data for VL 2864
6433 11:44:52.104421 # ok 538 Set VL 2880
6434 11:44:52.104538 # ok 539 # SKIP Disabled ZA for VL 2880
6435 11:44:52.104656 # ok 540 # SKIP Get and set data for VL 2880
6436 11:44:52.104773 # ok 541 Set VL 2896
6437 11:44:52.104889 # ok 542 # SKIP Disabled ZA for VL 2896
6438 11:44:52.105006 # ok 543 # SKIP Get and set data for VL 2896
6439 11:44:52.105123 # ok 544 Set VL 2912
6440 11:44:52.105238 # ok 545 # SKIP Disabled ZA for VL 2912
6441 11:44:52.105356 # ok 546 # SKIP Get and set data for VL 2912
6442 11:44:52.105472 # ok 547 Set VL 2928
6443 11:44:52.105626 # ok 548 # SKIP Disabled ZA for VL 2928
6444 11:44:52.105769 # ok 549 # SKIP Get and set data for VL 2928
6445 11:44:52.105890 # ok 550 Set VL 2944
6446 11:44:52.106007 # ok 551 # SKIP Disabled ZA for VL 2944
6447 11:44:52.106125 # ok 552 # SKIP Get and set data for VL 2944
6448 11:44:52.106243 # ok 553 Set VL 2960
6449 11:44:52.108678 # ok 554 # SKIP Disabled ZA for VL 2960
6450 11:44:52.109087 # ok 555 # SKIP Get and set data for VL 2960
6451 11:44:52.109192 # ok 556 Set VL 2976
6452 11:44:52.109282 # ok 557 # SKIP Disabled ZA for VL 2976
6453 11:44:52.109382 # ok 558 # SKIP Get and set data for VL 2976
6454 11:44:52.109682 # ok 559 Set VL 2992
6455 11:44:52.109785 # ok 560 # SKIP Disabled ZA for VL 2992
6456 11:44:52.109871 # ok 561 # SKIP Get and set data for VL 2992
6457 11:44:52.109955 # ok 562 Set VL 3008
6458 11:44:52.110054 # ok 563 # SKIP Disabled ZA for VL 3008
6459 11:44:52.110142 # ok 564 # SKIP Get and set data for VL 3008
6460 11:44:52.110369 # ok 565 Set VL 3024
6461 11:44:52.110466 # ok 566 # SKIP Disabled ZA for VL 3024
6462 11:44:52.110569 # ok 567 # SKIP Get and set data for VL 3024
6463 11:44:52.110655 # ok 568 Set VL 3040
6464 11:44:52.110742 # ok 569 # SKIP Disabled ZA for VL 3040
6465 11:44:52.110824 # ok 570 # SKIP Get and set data for VL 3040
6466 11:44:52.110906 # ok 571 Set VL 3056
6467 11:44:52.111004 # ok 572 # SKIP Disabled ZA for VL 3056
6468 11:44:52.111089 # ok 573 # SKIP Get and set data for VL 3056
6469 11:44:52.111175 # ok 574 Set VL 3072
6470 11:44:52.111257 # ok 575 # SKIP Disabled ZA for VL 3072
6471 11:44:52.111354 # ok 576 # SKIP Get and set data for VL 3072
6472 11:44:52.111430 # ok 577 Set VL 3088
6473 11:44:52.116768 # ok 578 # SKIP Disabled ZA for VL 3088
6474 11:44:52.117350 # ok 579 # SKIP Get and set data for VL 3088
6475 11:44:52.117545 # ok 580 Set VL 3104
6476 11:44:52.117727 # ok 581 # SKIP Disabled ZA for VL 3104
6477 11:44:52.117863 # ok 582 # SKIP Get and set data for VL 3104
6478 11:44:52.117983 # ok 583 Set VL 3120
6479 11:44:52.118128 # ok 584 # SKIP Disabled ZA for VL 3120
6480 11:44:52.118252 # ok 585 # SKIP Get and set data for VL 3120
6481 11:44:52.118370 # ok 586 Set VL 3136
6482 11:44:52.118487 # ok 587 # SKIP Disabled ZA for VL 3136
6483 11:44:52.118627 # ok 588 # SKIP Get and set data for VL 3136
6484 11:44:52.118816 # ok 589 Set VL 3152
6485 11:44:52.119064 # ok 590 # SKIP Disabled ZA for VL 3152
6486 11:44:52.119259 # ok 591 # SKIP Get and set data for VL 3152
6487 11:44:52.119463 # ok 592 Set VL 3168
6488 11:44:52.119608 # ok 593 # SKIP Disabled ZA for VL 3168
6489 11:44:52.119728 # ok 594 # SKIP Get and set data for VL 3168
6490 11:44:52.119847 # ok 595 Set VL 3184
6491 11:44:52.119990 # ok 596 # SKIP Disabled ZA for VL 3184
6492 11:44:52.120114 # ok 597 # SKIP Get and set data for VL 3184
6493 11:44:52.120231 # ok 598 Set VL 3200
6494 11:44:52.120348 # ok 599 # SKIP Disabled ZA for VL 3200
6495 11:44:52.124935 # ok 600 # SKIP Get and set data for VL 3200
6496 11:44:52.125506 # ok 601 Set VL 3216
6497 11:44:52.125614 # ok 602 # SKIP Disabled ZA for VL 3216
6498 11:44:52.125712 # ok 603 # SKIP Get and set data for VL 3216
6499 11:44:52.125798 # ok 604 Set VL 3232
6500 11:44:52.125883 # ok 605 # SKIP Disabled ZA for VL 3232
6501 11:44:52.125966 # ok 606 # SKIP Get and set data for VL 3232
6502 11:44:52.126050 # ok 607 Set VL 3248
6503 11:44:52.126151 # ok 608 # SKIP Disabled ZA for VL 3248
6504 11:44:52.126237 # ok 609 # SKIP Get and set data for VL 3248
6505 11:44:52.126321 # ok 610 Set VL 3264
6506 11:44:52.126404 # ok 611 # SKIP Disabled ZA for VL 3264
6507 11:44:52.126945 # ok 612 # SKIP Get and set data for VL 3264
6508 11:44:52.127077 # ok 613 Set VL 3280
6509 11:44:52.127171 # ok 614 # SKIP Disabled ZA for VL 3280
6510 11:44:52.127255 # ok 615 # SKIP Get and set data for VL 3280
6511 11:44:52.127338 # ok 616 Set VL 3296
6512 11:44:52.127420 # ok 617 # SKIP Disabled ZA for VL 3296
6513 11:44:52.127503 # ok 618 # SKIP Get and set data for VL 3296
6514 11:44:52.127584 # ok 619 Set VL 3312
6515 11:44:52.127666 # ok 620 # SKIP Disabled ZA for VL 3312
6516 11:44:52.127748 # ok 621 # SKIP Get and set data for VL 3312
6517 11:44:52.127827 # ok 622 Set VL 3328
6518 11:44:52.128131 # ok 623 # SKIP Disabled ZA for VL 3328
6519 11:44:52.128291 # ok 624 # SKIP Get and set data for VL 3328
6520 11:44:52.128415 # ok 625 Set VL 3344
6521 11:44:52.130870 # ok 626 # SKIP Disabled ZA for VL 3344
6522 11:44:52.131236 # ok 627 # SKIP Get and set data for VL 3344
6523 11:44:52.131339 # ok 628 Set VL 3360
6524 11:44:52.131417 # ok 629 # SKIP Disabled ZA for VL 3360
6525 11:44:52.131491 # ok 630 # SKIP Get and set data for VL 3360
6526 11:44:52.131577 # ok 631 Set VL 3376
6527 11:44:52.137068 # ok 632 # SKIP Disabled ZA for VL 3376
6528 11:44:52.137311 # ok 633 # SKIP Get and set data for VL 3376
6529 11:44:52.137582 # ok 634 Set VL 3392
6530 11:44:52.137697 # ok 635 # SKIP Disabled ZA for VL 3392
6531 11:44:52.137791 # ok 636 # SKIP Get and set data for VL 3392
6532 11:44:52.137879 # ok 637 Set VL 3408
6533 11:44:52.137965 # ok 638 # SKIP Disabled ZA for VL 3408
6534 11:44:52.138065 # ok 639 # SKIP Get and set data for VL 3408
6535 11:44:52.138151 # ok 640 Set VL 3424
6536 11:44:52.138235 # ok 641 # SKIP Disabled ZA for VL 3424
6537 11:44:52.138321 # ok 642 # SKIP Get and set data for VL 3424
6538 11:44:52.138406 # ok 643 Set VL 3440
6539 11:44:52.138509 # ok 644 # SKIP Disabled ZA for VL 3440
6540 11:44:52.138593 # ok 645 # SKIP Get and set data for VL 3440
6541 11:44:52.138678 # ok 646 Set VL 3456
6542 11:44:52.138763 # ok 647 # SKIP Disabled ZA for VL 3456
6543 11:44:52.138860 # ok 648 # SKIP Get and set data for VL 3456
6544 11:44:52.138946 # ok 649 Set VL 3472
6545 11:44:52.139045 # ok 650 # SKIP Disabled ZA for VL 3472
6546 11:44:52.139370 # ok 651 # SKIP Get and set data for VL 3472
6547 11:44:52.139466 # ok 652 Set VL 3488
6548 11:44:52.139542 # ok 653 # SKIP Disabled ZA for VL 3488
6549 11:44:52.144789 # ok 654 # SKIP Get and set data for VL 3488
6550 11:44:52.145013 # ok 655 Set VL 3504
6551 11:44:52.145103 # ok 656 # SKIP Disabled ZA for VL 3504
6552 11:44:52.145208 # ok 657 # SKIP Get and set data for VL 3504
6553 11:44:52.145300 # ok 658 Set VL 3520
6554 11:44:52.145385 # ok 659 # SKIP Disabled ZA for VL 3520
6555 11:44:52.145470 # ok 660 # SKIP Get and set data for VL 3520
6556 11:44:52.145571 # ok 661 Set VL 3536
6557 11:44:52.145665 # ok 662 # SKIP Disabled ZA for VL 3536
6558 11:44:52.145750 # ok 663 # SKIP Get and set data for VL 3536
6559 11:44:52.145833 # ok 664 Set VL 3552
6560 11:44:52.145933 # ok 665 # SKIP Disabled ZA for VL 3552
6561 11:44:52.146018 # ok 666 # SKIP Get and set data for VL 3552
6562 11:44:52.146117 # ok 667 Set VL 3568
6563 11:44:52.146202 # ok 668 # SKIP Disabled ZA for VL 3568
6564 11:44:52.146301 # ok 669 # SKIP Get and set data for VL 3568
6565 11:44:52.146652 # ok 670 Set VL 3584
6566 11:44:52.146755 # ok 671 # SKIP Disabled ZA for VL 3584
6567 11:44:52.146841 # ok 672 # SKIP Get and set data for VL 3584
6568 11:44:52.146927 # ok 673 Set VL 3600
6569 11:44:52.147027 # ok 674 # SKIP Disabled ZA for VL 3600
6570 11:44:52.147115 # ok 675 # SKIP Get and set data for VL 3600
6571 11:44:52.147214 # ok 676 Set VL 3616
6572 11:44:52.147299 # ok 677 # SKIP Disabled ZA for VL 3616
6573 11:44:52.147390 # ok 678 # SKIP Get and set data for VL 3616
6574 11:44:52.154869 # ok 679 Set VL 3632
6575 11:44:52.155395 # ok 680 # SKIP Disabled ZA for VL 3632
6576 11:44:52.155557 # ok 681 # SKIP Get and set data for VL 3632
6577 11:44:52.155689 # ok 682 Set VL 3648
6578 11:44:52.155812 # ok 683 # SKIP Disabled ZA for VL 3648
6579 11:44:52.155930 # ok 684 # SKIP Get and set data for VL 3648
6580 11:44:52.156046 # ok 685 Set VL 3664
6581 11:44:52.156163 # ok 686 # SKIP Disabled ZA for VL 3664
6582 11:44:52.156282 # ok 687 # SKIP Get and set data for VL 3664
6583 11:44:52.156400 # ok 688 Set VL 3680
6584 11:44:52.156541 # ok 689 # SKIP Disabled ZA for VL 3680
6585 11:44:52.156665 # ok 690 # SKIP Get and set data for VL 3680
6586 11:44:52.156784 # ok 691 Set VL 3696
6587 11:44:52.161183 # ok 692 # SKIP Disabled ZA for VL 3696
6588 11:44:52.161532 # ok 693 # SKIP Get and set data for VL 3696
6589 11:44:52.161728 # ok 694 Set VL 3712
6590 11:44:52.161973 # ok 695 # SKIP Disabled ZA for VL 3712
6591 11:44:52.162178 # ok 696 # SKIP Get and set data for VL 3712
6592 11:44:52.162370 # ok 697 Set VL 3728
6593 11:44:52.162574 # ok 698 # SKIP Disabled ZA for VL 3728
6594 11:44:52.162754 # ok 699 # SKIP Get and set data for VL 3728
6595 11:44:52.162969 # ok 700 Set VL 3744
6596 11:44:52.163160 # ok 701 # SKIP Disabled ZA for VL 3744
6597 11:44:52.163399 # ok 702 # SKIP Get and set data for VL 3744
6598 11:44:52.163544 # ok 703 Set VL 3760
6599 11:44:52.163664 # ok 704 # SKIP Disabled ZA for VL 3760
6600 11:44:52.163781 # ok 705 # SKIP Get and set data for VL 3760
6601 11:44:52.163899 # ok 706 Set VL 3776
6602 11:44:52.164013 # ok 707 # SKIP Disabled ZA for VL 3776
6603 11:44:52.164191 # ok 708 # SKIP Get and set data for VL 3776
6604 11:44:52.164354 # ok 709 Set VL 3792
6605 11:44:52.164482 # ok 710 # SKIP Disabled ZA for VL 3792
6606 11:44:52.164605 # ok 711 # SKIP Get and set data for VL 3792
6607 11:44:52.164745 # ok 712 Set VL 3808
6608 11:44:52.164939 # ok 713 # SKIP Disabled ZA for VL 3808
6609 11:44:52.165103 # ok 714 # SKIP Get and set data for VL 3808
6610 11:44:52.178643 # ok 715 Set VL 3824
6611 11:44:52.178887 # ok 716 # SKIP Disabled ZA for VL 3824
6612 11:44:52.178978 # ok 717 # SKIP Get and set data for VL 3824
6613 11:44:52.179065 # ok 718 Set VL 3840
6614 11:44:52.179151 # ok 719 # SKIP Disabled ZA for VL 3840
6615 11:44:52.179440 # ok 720 # SKIP Get and set data for VL 3840
6616 11:44:52.179524 # ok 721 Set VL 3856
6617 11:44:52.179596 # ok 722 # SKIP Disabled ZA for VL 3856
6618 11:44:52.179668 # ok 723 # SKIP Get and set data for VL 3856
6619 11:44:52.179740 # ok 724 Set VL 3872
6620 11:44:52.179810 # ok 725 # SKIP Disabled ZA for VL 3872
6621 11:44:52.184362 # ok 726 # SKIP Get and set data for VL 3872
6622 11:44:52.184597 # ok 727 Set VL 3888
6623 11:44:52.184687 # ok 728 # SKIP Disabled ZA for VL 3888
6624 11:44:52.185007 # ok 729 # SKIP Get and set data for VL 3888
6625 11:44:52.185108 # ok 730 Set VL 3904
6626 11:44:52.185195 # ok 731 # SKIP Disabled ZA for VL 3904
6627 11:44:52.185283 # ok 732 # SKIP Get and set data for VL 3904
6628 11:44:52.185368 # ok 733 Set VL 3920
6629 11:44:52.185450 # ok 734 # SKIP Disabled ZA for VL 3920
6630 11:44:52.185554 # ok 735 # SKIP Get and set data for VL 3920
6631 11:44:52.185643 # ok 736 Set VL 3936
6632 11:44:52.185736 # ok 737 # SKIP Disabled ZA for VL 3936
6633 11:44:52.185822 # ok 738 # SKIP Get and set data for VL 3936
6634 11:44:52.185909 # ok 739 Set VL 3952
6635 11:44:52.185994 # ok 740 # SKIP Disabled ZA for VL 3952
6636 11:44:52.186097 # ok 741 # SKIP Get and set data for VL 3952
6637 11:44:52.186185 # ok 742 Set VL 3968
6638 11:44:52.186270 # ok 743 # SKIP Disabled ZA for VL 3968
6639 11:44:52.186354 # ok 744 # SKIP Get and set data for VL 3968
6640 11:44:52.186455 # ok 745 Set VL 3984
6641 11:44:52.186541 # ok 746 # SKIP Disabled ZA for VL 3984
6642 11:44:52.186627 # ok 747 # SKIP Get and set data for VL 3984
6643 11:44:52.186729 # ok 748 Set VL 4000
6644 11:44:52.186817 # ok 749 # SKIP Disabled ZA for VL 4000
6645 11:44:52.186919 # ok 750 # SKIP Get and set data for VL 4000
6646 11:44:52.187008 # ok 751 Set VL 4016
6647 11:44:52.187110 # ok 752 # SKIP Disabled ZA for VL 4016
6648 11:44:52.187200 # ok 753 # SKIP Get and set data for VL 4016
6649 11:44:52.187315 # ok 754 Set VL 4032
6650 11:44:52.200813 # ok 755 # SKIP Disabled ZA for VL 4032
6651 11:44:52.201260 # ok 756 # SKIP Get and set data for VL 4032
6652 11:44:52.201365 # ok 757 Set VL 4048
6653 11:44:52.201454 # ok 758 # SKIP Disabled ZA for VL 4048
6654 11:44:52.201538 # ok 759 # SKIP Get and set data for VL 4048
6655 11:44:52.201626 # ok 760 Set VL 4064
6656 11:44:52.201722 # ok 761 # SKIP Disabled ZA for VL 4064
6657 11:44:52.201828 # ok 762 # SKIP Get and set data for VL 4064
6658 11:44:52.201917 # ok 763 Set VL 4080
6659 11:44:52.202003 # ok 764 # SKIP Disabled ZA for VL 4080
6660 11:44:52.202088 # ok 765 # SKIP Get and set data for VL 4080
6661 11:44:52.202173 # ok 766 Set VL 4096
6662 11:44:52.202274 # ok 767 # SKIP Disabled ZA for VL 4096
6663 11:44:52.202361 # ok 768 # SKIP Get and set data for VL 4096
6664 11:44:52.202446 # ok 769 Set VL 4112
6665 11:44:52.202530 # ok 770 # SKIP Disabled ZA for VL 4112
6666 11:44:52.202634 # ok 771 # SKIP Get and set data for VL 4112
6667 11:44:52.202722 # ok 772 Set VL 4128
6668 11:44:52.202807 # ok 773 # SKIP Disabled ZA for VL 4128
6669 11:44:52.202910 # ok 774 # SKIP Get and set data for VL 4128
6670 11:44:52.202994 # ok 775 Set VL 4144
6671 11:44:52.203093 # ok 776 # SKIP Disabled ZA for VL 4144
6672 11:44:52.203178 # ok 777 # SKIP Get and set data for VL 4144
6673 11:44:52.203276 # ok 778 Set VL 4160
6674 11:44:52.203356 # ok 779 # SKIP Disabled ZA for VL 4160
6675 11:44:52.216372 # ok 780 # SKIP Get and set data for VL 4160
6676 11:44:52.216609 # ok 781 Set VL 4176
6677 11:44:52.216708 # ok 782 # SKIP Disabled ZA for VL 4176
6678 11:44:52.217027 # ok 783 # SKIP Get and set data for VL 4176
6679 11:44:52.217136 # ok 784 Set VL 4192
6680 11:44:52.217227 # ok 785 # SKIP Disabled ZA for VL 4192
6681 11:44:52.217314 # ok 786 # SKIP Get and set data for VL 4192
6682 11:44:52.217398 # ok 787 Set VL 4208
6683 11:44:52.217472 # ok 788 # SKIP Disabled ZA for VL 4208
6684 11:44:52.217550 # ok 789 # SKIP Get and set data for VL 4208
6685 11:44:52.217632 # ok 790 Set VL 4224
6686 11:44:52.217745 # ok 791 # SKIP Disabled ZA for VL 4224
6687 11:44:52.217828 # ok 792 # SKIP Get and set data for VL 4224
6688 11:44:52.217914 # ok 793 Set VL 4240
6689 11:44:52.217997 # ok 794 # SKIP Disabled ZA for VL 4240
6690 11:44:52.218077 # ok 795 # SKIP Get and set data for VL 4240
6691 11:44:52.218156 # ok 796 Set VL 4256
6692 11:44:52.218271 # ok 797 # SKIP Disabled ZA for VL 4256
6693 11:44:52.218370 # ok 798 # SKIP Get and set data for VL 4256
6694 11:44:52.218462 # ok 799 Set VL 4272
6695 11:44:52.218562 # ok 800 # SKIP Disabled ZA for VL 4272
6696 11:44:52.218692 # ok 801 # SKIP Get and set data for VL 4272
6697 11:44:52.218793 # ok 802 Set VL 4288
6698 11:44:52.218911 # ok 803 # SKIP Disabled ZA for VL 4288
6699 11:44:52.219012 # ok 804 # SKIP Get and set data for VL 4288
6700 11:44:52.219102 # ok 805 Set VL 4304
6701 11:44:52.219190 # ok 806 # SKIP Disabled ZA for VL 4304
6702 11:44:52.219304 # ok 807 # SKIP Get and set data for VL 4304
6703 11:44:52.219384 # ok 808 Set VL 4320
6704 11:44:52.219457 # ok 809 # SKIP Disabled ZA for VL 4320
6705 11:44:52.219532 # ok 810 # SKIP Get and set data for VL 4320
6706 11:44:52.219606 # ok 811 Set VL 4336
6707 11:44:52.236385 # ok 812 # SKIP Disabled ZA for VL 4336
6708 11:44:52.236625 # ok 813 # SKIP Get and set data for VL 4336
6709 11:44:52.236959 # ok 814 Set VL 4352
6710 11:44:52.237071 # ok 815 # SKIP Disabled ZA for VL 4352
6711 11:44:52.237161 # ok 816 # SKIP Get and set data for VL 4352
6712 11:44:52.237245 # ok 817 Set VL 4368
6713 11:44:52.237336 # ok 818 # SKIP Disabled ZA for VL 4368
6714 11:44:52.237416 # ok 819 # SKIP Get and set data for VL 4368
6715 11:44:52.237493 # ok 820 Set VL 4384
6716 11:44:52.237568 # ok 821 # SKIP Disabled ZA for VL 4384
6717 11:44:52.238506 # ok 822 # SKIP Get and set data for VL 4384
6718 11:44:52.238615 # ok 823 Set VL 4400
6719 11:44:52.238716 # ok 824 # SKIP Disabled ZA for VL 4400
6720 11:44:52.238803 # ok 825 # SKIP Get and set data for VL 4400
6721 11:44:52.238904 # ok 826 Set VL 4416
6722 11:44:52.238993 # ok 827 # SKIP Disabled ZA for VL 4416
6723 11:44:52.239092 # ok 828 # SKIP Get and set data for VL 4416
6724 11:44:52.239178 # ok 829 Set VL 4432
6725 11:44:52.239274 # ok 830 # SKIP Disabled ZA for VL 4432
6726 11:44:52.245561 # ok 831 # SKIP Get and set data for VL 4432
6727 11:44:52.245812 # ok 832 Set VL 4448
6728 11:44:52.246164 # ok 833 # SKIP Disabled ZA for VL 4448
6729 11:44:52.246269 # ok 834 # SKIP Get and set data for VL 4448
6730 11:44:52.246357 # ok 835 Set VL 4464
6731 11:44:52.246444 # ok 836 # SKIP Disabled ZA for VL 4464
6732 11:44:52.246550 # ok 837 # SKIP Get and set data for VL 4464
6733 11:44:52.246639 # ok 838 Set VL 4480
6734 11:44:52.246723 # ok 839 # SKIP Disabled ZA for VL 4480
6735 11:44:52.246808 # ok 840 # SKIP Get and set data for VL 4480
6736 11:44:52.246910 # ok 841 Set VL 4496
6737 11:44:52.247002 # ok 842 # SKIP Disabled ZA for VL 4496
6738 11:44:52.247102 # ok 843 # SKIP Get and set data for VL 4496
6739 11:44:52.247189 # ok 844 Set VL 4512
6740 11:44:52.247288 # ok 845 # SKIP Disabled ZA for VL 4512
6741 11:44:52.247391 # ok 846 # SKIP Get and set data for VL 4512
6742 11:44:52.247468 # ok 847 Set VL 4528
6743 11:44:52.250819 # ok 848 # SKIP Disabled ZA for VL 4528
6744 11:44:52.251300 # ok 849 # SKIP Get and set data for VL 4528
6745 11:44:52.251399 # ok 850 Set VL 4544
6746 11:44:52.251476 # ok 851 # SKIP Disabled ZA for VL 4544
6747 11:44:52.251549 # ok 852 # SKIP Get and set data for VL 4544
6748 11:44:52.251624 # ok 853 Set VL 4560
6749 11:44:52.257275 # ok 854 # SKIP Disabled ZA for VL 4560
6750 11:44:52.257831 # ok 855 # SKIP Get and set data for VL 4560
6751 11:44:52.258066 # ok 856 Set VL 4576
6752 11:44:52.258269 # ok 857 # SKIP Disabled ZA for VL 4576
6753 11:44:52.258513 # ok 858 # SKIP Get and set data for VL 4576
6754 11:44:52.258716 # ok 859 Set VL 4592
6755 11:44:52.258937 # ok 860 # SKIP Disabled ZA for VL 4592
6756 11:44:52.259156 # ok 861 # SKIP Get and set data for VL 4592
6757 11:44:52.259367 # ok 862 Set VL 4608
6758 11:44:52.259556 # ok 863 # SKIP Disabled ZA for VL 4608
6759 11:44:52.259693 # ok 864 # SKIP Get and set data for VL 4608
6760 11:44:52.259827 # ok 865 Set VL 4624
6761 11:44:52.260023 # ok 866 # SKIP Disabled ZA for VL 4624
6762 11:44:52.260214 # ok 867 # SKIP Get and set data for VL 4624
6763 11:44:52.260403 # ok 868 Set VL 4640
6764 11:44:52.260589 # ok 869 # SKIP Disabled ZA for VL 4640
6765 11:44:52.260776 # ok 870 # SKIP Get and set data for VL 4640
6766 11:44:52.260969 # ok 871 Set VL 4656
6767 11:44:52.261143 # ok 872 # SKIP Disabled ZA for VL 4656
6768 11:44:52.266137 # ok 873 # SKIP Get and set data for VL 4656
6769 11:44:52.266381 # ok 874 Set VL 4672
6770 11:44:52.266685 # ok 875 # SKIP Disabled ZA for VL 4672
6771 11:44:52.266783 # ok 876 # SKIP Get and set data for VL 4672
6772 11:44:52.266872 # ok 877 Set VL 4688
6773 11:44:52.266956 # ok 878 # SKIP Disabled ZA for VL 4688
6774 11:44:52.267041 # ok 879 # SKIP Get and set data for VL 4688
6775 11:44:52.267145 # ok 880 Set VL 4704
6776 11:44:52.267232 # ok 881 # SKIP Disabled ZA for VL 4704
6777 11:44:52.267318 # ok 882 # SKIP Get and set data for VL 4704
6778 11:44:52.267405 # ok 883 Set VL 4720
6779 11:44:52.267488 # ok 884 # SKIP Disabled ZA for VL 4720
6780 11:44:52.267590 # ok 885 # SKIP Get and set data for VL 4720
6781 11:44:52.267678 # ok 886 Set VL 4736
6782 11:44:52.268839 # ok 887 # SKIP Disabled ZA for VL 4736
6783 11:44:52.268945 # ok 888 # SKIP Get and set data for VL 4736
6784 11:44:52.269033 # ok 889 Set VL 4752
6785 11:44:52.269118 # ok 890 # SKIP Disabled ZA for VL 4752
6786 11:44:52.269394 # ok 891 # SKIP Get and set data for VL 4752
6787 11:44:52.269487 # ok 892 Set VL 4768
6788 11:44:52.269572 # ok 893 # SKIP Disabled ZA for VL 4768
6789 11:44:52.269665 # ok 894 # SKIP Get and set data for VL 4768
6790 11:44:52.269750 # ok 895 Set VL 4784
6791 11:44:52.269835 # ok 896 # SKIP Disabled ZA for VL 4784
6792 11:44:52.269936 # ok 897 # SKIP Get and set data for VL 4784
6793 11:44:52.270024 # ok 898 Set VL 4800
6794 11:44:52.270110 # ok 899 # SKIP Disabled ZA for VL 4800
6795 11:44:52.270195 # ok 900 # SKIP Get and set data for VL 4800
6796 11:44:52.270280 # ok 901 Set VL 4816
6797 11:44:52.270382 # ok 902 # SKIP Disabled ZA for VL 4816
6798 11:44:52.270486 # ok 903 # SKIP Get and set data for VL 4816
6799 11:44:52.270573 # ok 904 Set VL 4832
6800 11:44:52.270659 # ok 905 # SKIP Disabled ZA for VL 4832
6801 11:44:52.270745 # ok 906 # SKIP Get and set data for VL 4832
6802 11:44:52.270831 # ok 907 Set VL 4848
6803 11:44:52.270915 # ok 908 # SKIP Disabled ZA for VL 4848
6804 11:44:52.271005 # ok 909 # SKIP Get and set data for VL 4848
6805 11:44:52.271092 # ok 910 Set VL 4864
6806 11:44:52.271197 # ok 911 # SKIP Disabled ZA for VL 4864
6807 11:44:52.271284 # ok 912 # SKIP Get and set data for VL 4864
6808 11:44:52.271371 # ok 913 Set VL 4880
6809 11:44:52.271455 # ok 914 # SKIP Disabled ZA for VL 4880
6810 11:44:52.271540 # ok 915 # SKIP Get and set data for VL 4880
6811 11:44:52.271624 # ok 916 Set VL 4896
6812 11:44:52.271706 # ok 917 # SKIP Disabled ZA for VL 4896
6813 11:44:52.271791 # ok 918 # SKIP Get and set data for VL 4896
6814 11:44:52.271877 # ok 919 Set VL 4912
6815 11:44:52.280501 # ok 920 # SKIP Disabled ZA for VL 4912
6816 11:44:52.280904 # ok 921 # SKIP Get and set data for VL 4912
6817 11:44:52.281107 # ok 922 Set VL 4928
6818 11:44:52.281276 # ok 923 # SKIP Disabled ZA for VL 4928
6819 11:44:52.281410 # ok 924 # SKIP Get and set data for VL 4928
6820 11:44:52.281573 # ok 925 Set VL 4944
6821 11:44:52.281752 # ok 926 # SKIP Disabled ZA for VL 4944
6822 11:44:52.281905 # ok 927 # SKIP Get and set data for VL 4944
6823 11:44:52.282067 # ok 928 Set VL 4960
6824 11:44:52.282224 # ok 929 # SKIP Disabled ZA for VL 4960
6825 11:44:52.282445 # ok 930 # SKIP Get and set data for VL 4960
6826 11:44:52.282610 # ok 931 Set VL 4976
6827 11:44:52.282775 # ok 932 # SKIP Disabled ZA for VL 4976
6828 11:44:52.282910 # ok 933 # SKIP Get and set data for VL 4976
6829 11:44:52.283040 # ok 934 Set VL 4992
6830 11:44:52.283178 # ok 935 # SKIP Disabled ZA for VL 4992
6831 11:44:52.283305 # ok 936 # SKIP Get and set data for VL 4992
6832 11:44:52.283427 # ok 937 Set VL 5008
6833 11:44:52.283544 # ok 938 # SKIP Disabled ZA for VL 5008
6834 11:44:52.283715 # ok 939 # SKIP Get and set data for VL 5008
6835 11:44:52.283893 # ok 940 Set VL 5024
6836 11:44:52.284054 # ok 941 # SKIP Disabled ZA for VL 5024
6837 11:44:52.284190 # ok 942 # SKIP Get and set data for VL 5024
6838 11:44:52.284383 # ok 943 Set VL 5040
6839 11:44:52.284532 # ok 944 # SKIP Disabled ZA for VL 5040
6840 11:44:52.284652 # ok 945 # SKIP Get and set data for VL 5040
6841 11:44:52.284771 # ok 946 Set VL 5056
6842 11:44:52.284917 # ok 947 # SKIP Disabled ZA for VL 5056
6843 11:44:52.285044 # ok 948 # SKIP Get and set data for VL 5056
6844 11:44:52.285164 # ok 949 Set VL 5072
6845 11:44:52.285282 # ok 950 # SKIP Disabled ZA for VL 5072
6846 11:44:52.285399 # ok 951 # SKIP Get and set data for VL 5072
6847 11:44:52.285518 # ok 952 Set VL 5088
6848 11:44:52.285636 # ok 953 # SKIP Disabled ZA for VL 5088
6849 11:44:52.289029 # ok 954 # SKIP Get and set data for VL 5088
6850 11:44:52.289241 # ok 955 Set VL 5104
6851 11:44:52.289388 # ok 956 # SKIP Disabled ZA for VL 5104
6852 11:44:52.289740 # ok 957 # SKIP Get and set data for VL 5104
6853 11:44:52.289887 # ok 958 Set VL 5120
6854 11:44:52.290019 # ok 959 # SKIP Disabled ZA for VL 5120
6855 11:44:52.290151 # ok 960 # SKIP Get and set data for VL 5120
6856 11:44:52.290280 # ok 961 Set VL 5136
6857 11:44:52.290406 # ok 962 # SKIP Disabled ZA for VL 5136
6858 11:44:52.290608 # ok 963 # SKIP Get and set data for VL 5136
6859 11:44:52.290788 # ok 964 Set VL 5152
6860 11:44:52.290988 # ok 965 # SKIP Disabled ZA for VL 5152
6861 11:44:52.291163 # ok 966 # SKIP Get and set data for VL 5152
6862 11:44:52.291303 # ok 967 Set VL 5168
6863 11:44:52.291419 # ok 968 # SKIP Disabled ZA for VL 5168
6864 11:44:52.291533 # ok 969 # SKIP Get and set data for VL 5168
6865 11:44:52.291655 # ok 970 Set VL 5184
6866 11:44:52.291785 # ok 971 # SKIP Disabled ZA for VL 5184
6867 11:44:52.291972 # ok 972 # SKIP Get and set data for VL 5184
6868 11:44:52.292108 # ok 973 Set VL 5200
6869 11:44:52.292311 # ok 974 # SKIP Disabled ZA for VL 5200
6870 11:44:52.292492 # ok 975 # SKIP Get and set data for VL 5200
6871 11:44:52.292648 # ok 976 Set VL 5216
6872 11:44:52.292809 # ok 977 # SKIP Disabled ZA for VL 5216
6873 11:44:52.292963 # ok 978 # SKIP Get and set data for VL 5216
6874 11:44:52.293122 # ok 979 Set VL 5232
6875 11:44:52.293353 # ok 980 # SKIP Disabled ZA for VL 5232
6876 11:44:52.293554 # ok 981 # SKIP Get and set data for VL 5232
6877 11:44:52.294313 # ok 982 Set VL 5248
6878 11:44:52.294508 # ok 983 # SKIP Disabled ZA for VL 5248
6879 11:44:52.294679 # ok 984 # SKIP Get and set data for VL 5248
6880 11:44:52.294840 # ok 985 Set VL 5264
6881 11:44:52.295029 # ok 986 # SKIP Disabled ZA for VL 5264
6882 11:44:52.295233 # ok 987 # SKIP Get and set data for VL 5264
6883 11:44:52.295403 # ok 988 Set VL 5280
6884 11:44:52.295533 # ok 989 # SKIP Disabled ZA for VL 5280
6885 11:44:52.295652 # ok 990 # SKIP Get and set data for VL 5280
6886 11:44:52.295767 # ok 991 Set VL 5296
6887 11:44:52.295881 # ok 992 # SKIP Disabled ZA for VL 5296
6888 11:44:52.295993 # ok 993 # SKIP Get and set data for VL 5296
6889 11:44:52.296107 # ok 994 Set VL 5312
6890 11:44:52.296221 # ok 995 # SKIP Disabled ZA for VL 5312
6891 11:44:52.296366 # ok 996 # SKIP Get and set data for VL 5312
6892 11:44:52.296488 # ok 997 Set VL 5328
6893 11:44:52.296602 # ok 998 # SKIP Disabled ZA for VL 5328
6894 11:44:52.296717 # ok 999 # SKIP Get and set data for VL 5328
6895 11:44:52.296831 # ok 1000 Set VL 5344
6896 11:44:52.296944 # ok 1001 # SKIP Disabled ZA for VL 5344
6897 11:44:52.297058 # ok 1002 # SKIP Get and set data for VL 5344
6898 11:44:52.297171 # ok 1003 Set VL 5360
6899 11:44:52.297294 # ok 1004 # SKIP Disabled ZA for VL 5360
6900 11:44:52.297409 # ok 1005 # SKIP Get and set data for VL 5360
6901 11:44:52.297522 # ok 1006 Set VL 5376
6902 11:44:52.297635 # ok 1007 # SKIP Disabled ZA for VL 5376
6903 11:44:52.297872 # ok 1008 # SKIP Get and set data for VL 5376
6904 11:44:52.298066 # ok 1009 Set VL 5392
6905 11:44:52.298496 # ok 1010 # SKIP Disabled ZA for VL 5392
6906 11:44:52.298657 # ok 1011 # SKIP Get and set data for VL 5392
6907 11:44:52.298802 # ok 1012 Set VL 5408
6908 11:44:52.298945 # ok 1013 # SKIP Disabled ZA for VL 5408
6909 11:44:52.299092 # ok 1014 # SKIP Get and set data for VL 5408
6910 11:44:52.299239 # ok 1015 Set VL 5424
6911 11:44:52.299381 # ok 1016 # SKIP Disabled ZA for VL 5424
6912 11:44:52.299524 # ok 1017 # SKIP Get and set data for VL 5424
6913 11:44:52.300223 # ok 1018 Set VL 5440
6914 11:44:52.300332 # ok 1019 # SKIP Disabled ZA for VL 5440
6915 11:44:52.300709 # ok 1020 # SKIP Get and set data for VL 5440
6916 11:44:52.300951 # ok 1021 Set VL 5456
6917 11:44:52.301151 # ok 1022 # SKIP Disabled ZA for VL 5456
6918 11:44:52.301358 # ok 1023 # SKIP Get and set data for VL 5456
6919 11:44:52.301540 # ok 1024 Set VL 5472
6920 11:44:52.301755 # ok 1025 # SKIP Disabled ZA for VL 5472
6921 11:44:52.301972 # ok 1026 # SKIP Get and set data for VL 5472
6922 11:44:52.302135 # ok 1027 Set VL 5488
6923 11:44:52.302313 # ok 1028 # SKIP Disabled ZA for VL 5488
6924 11:44:52.302497 # ok 1029 # SKIP Get and set data for VL 5488
6925 11:44:52.302685 # ok 1030 Set VL 5504
6926 11:44:52.302855 # ok 1031 # SKIP Disabled ZA for VL 5504
6927 11:44:52.303018 # ok 1032 # SKIP Get and set data for VL 5504
6928 11:44:52.303198 # ok 1033 Set VL 5520
6929 11:44:52.303336 # ok 1034 # SKIP Disabled ZA for VL 5520
6930 11:44:52.303454 # ok 1035 # SKIP Get and set data for VL 5520
6931 11:44:52.303569 # ok 1036 Set VL 5536
6932 11:44:52.303714 # ok 1037 # SKIP Disabled ZA for VL 5536
6933 11:44:52.303834 # ok 1038 # SKIP Get and set data for VL 5536
6934 11:44:52.303950 # ok 1039 Set VL 5552
6935 11:44:52.304064 # ok 1040 # SKIP Disabled ZA for VL 5552
6936 11:44:52.304178 # ok 1041 # SKIP Get and set data for VL 5552
6937 11:44:52.304292 # ok 1042 Set VL 5568
6938 11:44:52.304404 # ok 1043 # SKIP Disabled ZA for VL 5568
6939 11:44:52.304517 # ok 1044 # SKIP Get and set data for VL 5568
6940 11:44:52.304631 # ok 1045 Set VL 5584
6941 11:44:52.304744 # ok 1046 # SKIP Disabled ZA for VL 5584
6942 11:44:52.304856 # ok 1047 # SKIP Get and set data for VL 5584
6943 11:44:52.304969 # ok 1048 Set VL 5600
6944 11:44:52.305081 # ok 1049 # SKIP Disabled ZA for VL 5600
6945 11:44:52.305194 # ok 1050 # SKIP Get and set data for VL 5600
6946 11:44:52.305577 # ok 1051 Set VL 5616
6947 11:44:52.305886 # ok 1052 # SKIP Disabled ZA for VL 5616
6948 11:44:52.306957 # ok 1053 # SKIP Get and set data for VL 5616
6949 11:44:52.307263 # ok 1054 Set VL 5632
6950 11:44:52.307370 # ok 1055 # SKIP Disabled ZA for VL 5632
6951 11:44:52.313212 # ok 1056 # SKIP Get and set data for VL 5632
6952 11:44:52.313582 # ok 1057 Set VL 5648
6953 11:44:52.313692 # ok 1058 # SKIP Disabled ZA for VL 5648
6954 11:44:52.313777 # ok 1059 # SKIP Get and set data for VL 5648
6955 11:44:52.313872 # ok 1060 Set VL 5664
6956 11:44:52.313953 # ok 1061 # SKIP Disabled ZA for VL 5664
6957 11:44:52.314031 # ok 1062 # SKIP Get and set data for VL 5664
6958 11:44:52.314110 # ok 1063 Set VL 5680
6959 11:44:52.314201 # ok 1064 # SKIP Disabled ZA for VL 5680
6960 11:44:52.314281 # ok 1065 # SKIP Get and set data for VL 5680
6961 11:44:52.314359 # ok 1066 Set VL 5696
6962 11:44:52.314435 # ok 1067 # SKIP Disabled ZA for VL 5696
6963 11:44:52.314527 # ok 1068 # SKIP Get and set data for VL 5696
6964 11:44:52.314612 # ok 1069 Set VL 5712
6965 11:44:52.314690 # ok 1070 # SKIP Disabled ZA for VL 5712
6966 11:44:52.314781 # ok 1071 # SKIP Get and set data for VL 5712
6967 11:44:52.314860 # ok 1072 Set VL 5728
6968 11:44:52.314938 # ok 1073 # SKIP Disabled ZA for VL 5728
6969 11:44:52.315013 # ok 1074 # SKIP Get and set data for VL 5728
6970 11:44:52.315093 # ok 1075 Set VL 5744
6971 11:44:52.315182 # ok 1076 # SKIP Disabled ZA for VL 5744
6972 11:44:52.315259 # ok 1077 # SKIP Get and set data for VL 5744
6973 11:44:52.315335 # ok 1078 Set VL 5760
6974 11:44:52.315416 # ok 1079 # SKIP Disabled ZA for VL 5760
6975 11:44:52.315516 # ok 1080 # SKIP Get and set data for VL 5760
6976 11:44:52.320693 # ok 1081 Set VL 5776
6977 11:44:52.320815 # ok 1082 # SKIP Disabled ZA for VL 5776
6978 11:44:52.320897 # ok 1083 # SKIP Get and set data for VL 5776
6979 11:44:52.320988 # ok 1084 Set VL 5792
6980 11:44:52.321086 # ok 1085 # SKIP Disabled ZA for VL 5792
6981 11:44:52.321167 # ok 1086 # SKIP Get and set data for VL 5792
6982 11:44:52.321244 # ok 1087 Set VL 5808
6983 11:44:52.321334 # ok 1088 # SKIP Disabled ZA for VL 5808
6984 11:44:52.321414 # ok 1089 # SKIP Get and set data for VL 5808
6985 11:44:52.321491 # ok 1090 Set VL 5824
6986 11:44:52.321582 # ok 1091 # SKIP Disabled ZA for VL 5824
6987 11:44:52.321687 # ok 1092 # SKIP Get and set data for VL 5824
6988 11:44:52.321768 # ok 1093 Set VL 5840
6989 11:44:52.321860 # ok 1094 # SKIP Disabled ZA for VL 5840
6990 11:44:52.321939 # ok 1095 # SKIP Get and set data for VL 5840
6991 11:44:52.322029 # ok 1096 Set VL 5856
6992 11:44:52.330462 # ok 1097 # SKIP Disabled ZA for VL 5856
6993 11:44:52.330844 # ok 1098 # SKIP Get and set data for VL 5856
6994 11:44:52.330946 # ok 1099 Set VL 5872
6995 11:44:52.331025 # ok 1100 # SKIP Disabled ZA for VL 5872
6996 11:44:52.331120 # ok 1101 # SKIP Get and set data for VL 5872
6997 11:44:52.331199 # ok 1102 Set VL 5888
6998 11:44:52.331275 # ok 1103 # SKIP Disabled ZA for VL 5888
6999 11:44:52.331350 # ok 1104 # SKIP Get and set data for VL 5888
7000 11:44:52.331431 # ok 1105 Set VL 5904
7001 11:44:52.331531 # ok 1106 # SKIP Disabled ZA for VL 5904
7002 11:44:52.331610 # ok 1107 # SKIP Get and set data for VL 5904
7003 11:44:52.331892 # ok 1108 Set VL 5920
7004 11:44:52.331996 # ok 1109 # SKIP Disabled ZA for VL 5920
7005 11:44:52.332093 # ok 1110 # SKIP Get and set data for VL 5920
7006 11:44:52.332187 # ok 1111 Set VL 5936
7007 11:44:52.332433 # ok 1112 # SKIP Disabled ZA for VL 5936
7008 11:44:52.332557 # ok 1113 # SKIP Get and set data for VL 5936
7009 11:44:52.332650 # ok 1114 Set VL 5952
7010 11:44:52.332735 # ok 1115 # SKIP Disabled ZA for VL 5952
7011 11:44:52.333106 # ok 1116 # SKIP Get and set data for VL 5952
7012 11:44:52.333217 # ok 1117 Set VL 5968
7013 11:44:52.333302 # ok 1118 # SKIP Disabled ZA for VL 5968
7014 11:44:52.333385 # ok 1119 # SKIP Get and set data for VL 5968
7015 11:44:52.333467 # ok 1120 Set VL 5984
7016 11:44:52.333549 # ok 1121 # SKIP Disabled ZA for VL 5984
7017 11:44:52.333631 # ok 1122 # SKIP Get and set data for VL 5984
7018 11:44:52.333722 # ok 1123 Set VL 6000
7019 11:44:52.333803 # ok 1124 # SKIP Disabled ZA for VL 6000
7020 11:44:52.334106 # ok 1125 # SKIP Get and set data for VL 6000
7021 11:44:52.334211 # ok 1126 Set VL 6016
7022 11:44:52.334296 # ok 1127 # SKIP Disabled ZA for VL 6016
7023 11:44:52.334380 # ok 1128 # SKIP Get and set data for VL 6016
7024 11:44:52.334463 # ok 1129 Set VL 6032
7025 11:44:52.334545 # ok 1130 # SKIP Disabled ZA for VL 6032
7026 11:44:52.334626 # ok 1131 # SKIP Get and set data for VL 6032
7027 11:44:52.334709 # ok 1132 Set VL 6048
7028 11:44:52.334792 # ok 1133 # SKIP Disabled ZA for VL 6048
7029 11:44:52.334875 # ok 1134 # SKIP Get and set data for VL 6048
7030 11:44:52.334977 # ok 1135 Set VL 6064
7031 11:44:52.335063 # ok 1136 # SKIP Disabled ZA for VL 6064
7032 11:44:52.335148 # ok 1137 # SKIP Get and set data for VL 6064
7033 11:44:52.335233 # ok 1138 Set VL 6080
7034 11:44:52.335315 # ok 1139 # SKIP Disabled ZA for VL 6080
7035 11:44:52.335404 # ok 1140 # SKIP Get and set data for VL 6080
7036 11:44:52.335486 # ok 1141 Set VL 6096
7037 11:44:52.335572 # ok 1142 # SKIP Disabled ZA for VL 6096
7038 11:44:52.335654 # ok 1143 # SKIP Get and set data for VL 6096
7039 11:44:52.335735 # ok 1144 Set VL 6112
7040 11:44:52.335817 # ok 1145 # SKIP Disabled ZA for VL 6112
7041 11:44:52.335918 # ok 1146 # SKIP Get and set data for VL 6112
7042 11:44:52.336004 # ok 1147 Set VL 6128
7043 11:44:52.336084 # ok 1148 # SKIP Disabled ZA for VL 6128
7044 11:44:52.341044 # ok 1149 # SKIP Get and set data for VL 6128
7045 11:44:52.341524 # ok 1150 Set VL 6144
7046 11:44:52.341756 # ok 1151 # SKIP Disabled ZA for VL 6144
7047 11:44:52.341939 # ok 1152 # SKIP Get and set data for VL 6144
7048 11:44:52.342102 # ok 1153 Set VL 6160
7049 11:44:52.342258 # ok 1154 # SKIP Disabled ZA for VL 6160
7050 11:44:52.342403 # ok 1155 # SKIP Get and set data for VL 6160
7051 11:44:52.342590 # ok 1156 Set VL 6176
7052 11:44:52.342740 # ok 1157 # SKIP Disabled ZA for VL 6176
7053 11:44:52.342888 # ok 1158 # SKIP Get and set data for VL 6176
7054 11:44:52.343025 # ok 1159 Set VL 6192
7055 11:44:52.343197 # ok 1160 # SKIP Disabled ZA for VL 6192
7056 11:44:52.343329 # ok 1161 # SKIP Get and set data for VL 6192
7057 11:44:52.343455 # ok 1162 Set VL 6208
7058 11:44:52.343655 # ok 1163 # SKIP Disabled ZA for VL 6208
7059 11:44:52.343834 # ok 1164 # SKIP Get and set data for VL 6208
7060 11:44:52.343981 # ok 1165 Set VL 6224
7061 11:44:52.344123 # ok 1166 # SKIP Disabled ZA for VL 6224
7062 11:44:52.344303 # ok 1167 # SKIP Get and set data for VL 6224
7063 11:44:52.344441 # ok 1168 Set VL 6240
7064 11:44:52.344583 # ok 1169 # SKIP Disabled ZA for VL 6240
7065 11:44:52.344725 # ok 1170 # SKIP Get and set data for VL 6240
7066 11:44:52.344867 # ok 1171 Set VL 6256
7067 11:44:52.347969 # ok 1172 # SKIP Disabled ZA for VL 6256
7068 11:44:52.348284 # ok 1173 # SKIP Get and set data for VL 6256
7069 11:44:52.348385 # ok 1174 Set VL 6272
7070 11:44:52.348465 # ok 1175 # SKIP Disabled ZA for VL 6272
7071 11:44:52.348555 # ok 1176 # SKIP Get and set data for VL 6272
7072 11:44:52.348633 # ok 1177 Set VL 6288
7073 11:44:52.348722 # ok 1178 # SKIP Disabled ZA for VL 6288
7074 11:44:52.348801 # ok 1179 # SKIP Get and set data for VL 6288
7075 11:44:52.348878 # ok 1180 Set VL 6304
7076 11:44:52.348966 # ok 1181 # SKIP Disabled ZA for VL 6304
7077 11:44:52.349044 # ok 1182 # SKIP Get and set data for VL 6304
7078 11:44:52.349125 # ok 1183 Set VL 6320
7079 11:44:52.349200 # ok 1184 # SKIP Disabled ZA for VL 6320
7080 11:44:52.349491 # ok 1185 # SKIP Get and set data for VL 6320
7081 11:44:52.349594 # ok 1186 Set VL 6336
7082 11:44:52.349685 # ok 1187 # SKIP Disabled ZA for VL 6336
7083 11:44:52.349763 # ok 1188 # SKIP Get and set data for VL 6336
7084 11:44:52.349838 # ok 1189 Set VL 6352
7085 11:44:52.349929 # ok 1190 # SKIP Disabled ZA for VL 6352
7086 11:44:52.350008 # ok 1191 # SKIP Get and set data for VL 6352
7087 11:44:52.350086 # ok 1192 Set VL 6368
7088 11:44:52.350163 # ok 1193 # SKIP Disabled ZA for VL 6368
7089 11:44:52.350238 # ok 1194 # SKIP Get and set data for VL 6368
7090 11:44:52.350328 # ok 1195 Set VL 6384
7091 11:44:52.350406 # ok 1196 # SKIP Disabled ZA for VL 6384
7092 11:44:52.350481 # ok 1197 # SKIP Get and set data for VL 6384
7093 11:44:52.350556 # ok 1198 Set VL 6400
7094 11:44:52.350631 # ok 1199 # SKIP Disabled ZA for VL 6400
7095 11:44:52.350705 # ok 1200 # SKIP Get and set data for VL 6400
7096 11:44:52.350781 # ok 1201 Set VL 6416
7097 11:44:52.350870 # ok 1202 # SKIP Disabled ZA for VL 6416
7098 11:44:52.350948 # ok 1203 # SKIP Get and set data for VL 6416
7099 11:44:52.351023 # ok 1204 Set VL 6432
7100 11:44:52.351391 # ok 1205 # SKIP Disabled ZA for VL 6432
7101 11:44:52.351497 # ok 1206 # SKIP Get and set data for VL 6432
7102 11:44:52.351581 # ok 1207 Set VL 6448
7103 11:44:52.351675 # ok 1208 # SKIP Disabled ZA for VL 6448
7104 11:44:52.351760 # ok 1209 # SKIP Get and set data for VL 6448
7105 11:44:52.351838 # ok 1210 Set VL 6464
7106 11:44:52.351915 # ok 1211 # SKIP Disabled ZA for VL 6464
7107 11:44:52.361573 # ok 1212 # SKIP Get and set data for VL 6464
7108 11:44:52.361760 # ok 1213 Set VL 6480
7109 11:44:52.362035 # ok 1214 # SKIP Disabled ZA for VL 6480
7110 11:44:52.362138 # ok 1215 # SKIP Get and set data for VL 6480
7111 11:44:52.362218 # ok 1216 Set VL 6496
7112 11:44:52.362297 # ok 1217 # SKIP Disabled ZA for VL 6496
7113 11:44:52.362387 # ok 1218 # SKIP Get and set data for VL 6496
7114 11:44:52.362468 # ok 1219 Set VL 6512
7115 11:44:52.362545 # ok 1220 # SKIP Disabled ZA for VL 6512
7116 11:44:52.362623 # ok 1221 # SKIP Get and set data for VL 6512
7117 11:44:52.362702 # ok 1222 Set VL 6528
7118 11:44:52.362793 # ok 1223 # SKIP Disabled ZA for VL 6528
7119 11:44:52.362872 # ok 1224 # SKIP Get and set data for VL 6528
7120 11:44:52.362950 # ok 1225 Set VL 6544
7121 11:44:52.363027 # ok 1226 # SKIP Disabled ZA for VL 6544
7122 11:44:52.363122 # ok 1227 # SKIP Get and set data for VL 6544
7123 11:44:52.363202 # ok 1228 Set VL 6560
7124 11:44:52.363279 # ok 1229 # SKIP Disabled ZA for VL 6560
7125 11:44:52.363369 # ok 1230 # SKIP Get and set data for VL 6560
7126 11:44:52.370691 # ok 1231 Set VL 6576
7127 11:44:52.370833 # ok 1232 # SKIP Disabled ZA for VL 6576
7128 11:44:52.370928 # ok 1233 # SKIP Get and set data for VL 6576
7129 11:44:52.371011 # ok 1234 Set VL 6592
7130 11:44:52.371199 # ok 1235 # SKIP Disabled ZA for VL 6592
7131 11:44:52.371301 # ok 1236 # SKIP Get and set data for VL 6592
7132 11:44:52.371381 # ok 1237 Set VL 6608
7133 11:44:52.371479 # ok 1238 # SKIP Disabled ZA for VL 6608
7134 11:44:52.371954 # ok 1239 # SKIP Get and set data for VL 6608
7135 11:44:52.372065 # ok 1240 Set VL 6624
7136 11:44:52.372359 # ok 1241 # SKIP Disabled ZA for VL 6624
7137 11:44:52.372467 # ok 1242 # SKIP Get and set data for VL 6624
7138 11:44:52.372555 # ok 1243 Set VL 6640
7139 11:44:52.372639 # ok 1244 # SKIP Disabled ZA for VL 6640
7140 11:44:52.372739 # ok 1245 # SKIP Get and set data for VL 6640
7141 11:44:52.372825 # ok 1246 Set VL 6656
7142 11:44:52.372909 # ok 1247 # SKIP Disabled ZA for VL 6656
7143 11:44:52.372990 # ok 1248 # SKIP Get and set data for VL 6656
7144 11:44:52.373088 # ok 1249 Set VL 6672
7145 11:44:52.373172 # ok 1250 # SKIP Disabled ZA for VL 6672
7146 11:44:52.373255 # ok 1251 # SKIP Get and set data for VL 6672
7147 11:44:52.373339 # ok 1252 Set VL 6688
7148 11:44:52.373437 # ok 1253 # SKIP Disabled ZA for VL 6688
7149 11:44:52.373523 # ok 1254 # SKIP Get and set data for VL 6688
7150 11:44:52.373606 # ok 1255 Set VL 6704
7151 11:44:52.373697 # ok 1256 # SKIP Disabled ZA for VL 6704
7152 11:44:52.373798 # ok 1257 # SKIP Get and set data for VL 6704
7153 11:44:52.373883 # ok 1258 Set VL 6720
7154 11:44:52.373964 # ok 1259 # SKIP Disabled ZA for VL 6720
7155 11:44:52.374047 # ok 1260 # SKIP Get and set data for VL 6720
7156 11:44:52.374147 # ok 1261 Set VL 6736
7157 11:44:52.374233 # ok 1262 # SKIP Disabled ZA for VL 6736
7158 11:44:52.374314 # ok 1263 # SKIP Get and set data for VL 6736
7159 11:44:52.374397 # ok 1264 Set VL 6752
7160 11:44:52.374495 # ok 1265 # SKIP Disabled ZA for VL 6752
7161 11:44:52.374579 # ok 1266 # SKIP Get and set data for VL 6752
7162 11:44:52.374662 # ok 1267 Set VL 6768
7163 11:44:52.374744 # ok 1268 # SKIP Disabled ZA for VL 6768
7164 11:44:52.374842 # ok 1269 # SKIP Get and set data for VL 6768
7165 11:44:52.374929 # ok 1270 Set VL 6784
7166 11:44:52.375011 # ok 1271 # SKIP Disabled ZA for VL 6784
7167 11:44:52.375093 # ok 1272 # SKIP Get and set data for VL 6784
7168 11:44:52.375180 # ok 1273 Set VL 6800
7169 11:44:52.375277 # ok 1274 # SKIP Disabled ZA for VL 6800
7170 11:44:52.375363 # ok 1275 # SKIP Get and set data for VL 6800
7171 11:44:52.375445 # ok 1276 Set VL 6816
7172 11:44:52.384542 # ok 1277 # SKIP Disabled ZA for VL 6816
7173 11:44:52.385407 # ok 1278 # SKIP Get and set data for VL 6816
7174 11:44:52.385748 # ok 1279 Set VL 6832
7175 11:44:52.385955 # ok 1280 # SKIP Disabled ZA for VL 6832
7176 11:44:52.386158 # ok 1281 # SKIP Get and set data for VL 6832
7177 11:44:52.386337 # ok 1282 Set VL 6848
7178 11:44:52.386507 # ok 1283 # SKIP Disabled ZA for VL 6848
7179 11:44:52.386672 # ok 1284 # SKIP Get and set data for VL 6848
7180 11:44:52.386832 # ok 1285 Set VL 6864
7181 11:44:52.386991 # ok 1286 # SKIP Disabled ZA for VL 6864
7182 11:44:52.387186 # ok 1287 # SKIP Get and set data for VL 6864
7183 11:44:52.387324 # ok 1288 Set VL 6880
7184 11:44:52.387490 # ok 1289 # SKIP Disabled ZA for VL 6880
7185 11:44:52.387660 # ok 1290 # SKIP Get and set data for VL 6880
7186 11:44:52.387846 # ok 1291 Set VL 6896
7187 11:44:52.388012 # ok 1292 # SKIP Disabled ZA for VL 6896
7188 11:44:52.388137 # ok 1293 # SKIP Get and set data for VL 6896
7189 11:44:52.388279 # ok 1294 Set VL 6912
7190 11:44:52.388463 # ok 1295 # SKIP Disabled ZA for VL 6912
7191 11:44:52.388631 # ok 1296 # SKIP Get and set data for VL 6912
7192 11:44:52.388796 # ok 1297 Set VL 6928
7193 11:44:52.388959 # ok 1298 # SKIP Disabled ZA for VL 6928
7194 11:44:52.389138 # ok 1299 # SKIP Get and set data for VL 6928
7195 11:44:52.389310 # ok 1300 Set VL 6944
7196 11:44:52.389463 # ok 1301 # SKIP Disabled ZA for VL 6944
7197 11:44:52.396488 # ok 1302 # SKIP Get and set data for VL 6944
7198 11:44:52.396744 # ok 1303 Set VL 6960
7199 11:44:52.397095 # ok 1304 # SKIP Disabled ZA for VL 6960
7200 11:44:52.397202 # ok 1305 # SKIP Get and set data for VL 6960
7201 11:44:52.397292 # ok 1306 Set VL 6976
7202 11:44:52.397371 # ok 1307 # SKIP Disabled ZA for VL 6976
7203 11:44:52.397453 # ok 1308 # SKIP Get and set data for VL 6976
7204 11:44:52.397554 # ok 1309 Set VL 6992
7205 11:44:52.397638 # ok 1310 # SKIP Disabled ZA for VL 6992
7206 11:44:52.397869 # ok 1311 # SKIP Get and set data for VL 6992
7207 11:44:52.397958 # ok 1312 Set VL 7008
7208 11:44:52.398040 # ok 1313 # SKIP Disabled ZA for VL 7008
7209 11:44:52.398140 # ok 1314 # SKIP Get and set data for VL 7008
7210 11:44:52.398229 # ok 1315 Set VL 7024
7211 11:44:52.398310 # ok 1316 # SKIP Disabled ZA for VL 7024
7212 11:44:52.398391 # ok 1317 # SKIP Get and set data for VL 7024
7213 11:44:52.398474 # ok 1318 Set VL 7040
7214 11:44:52.398558 # ok 1319 # SKIP Disabled ZA for VL 7040
7215 11:44:52.398657 # ok 1320 # SKIP Get and set data for VL 7040
7216 11:44:52.398740 # ok 1321 Set VL 7056
7217 11:44:52.398822 # ok 1322 # SKIP Disabled ZA for VL 7056
7218 11:44:52.398905 # ok 1323 # SKIP Get and set data for VL 7056
7219 11:44:52.399003 # ok 1324 Set VL 7072
7220 11:44:52.399088 # ok 1325 # SKIP Disabled ZA for VL 7072
7221 11:44:52.399175 # ok 1326 # SKIP Get and set data for VL 7072
7222 11:44:52.399260 # ok 1327 Set VL 7088
7223 11:44:52.399356 # ok 1328 # SKIP Disabled ZA for VL 7088
7224 11:44:52.408769 # ok 1329 # SKIP Get and set data for VL 7088
7225 11:44:52.409135 # ok 1330 Set VL 7104
7226 11:44:52.409581 # ok 1331 # SKIP Disabled ZA for VL 7104
7227 11:44:52.409702 # ok 1332 # SKIP Get and set data for VL 7104
7228 11:44:52.409793 # ok 1333 Set VL 7120
7229 11:44:52.409879 # ok 1334 # SKIP Disabled ZA for VL 7120
7230 11:44:52.409965 # ok 1335 # SKIP Get and set data for VL 7120
7231 11:44:52.410048 # ok 1336 Set VL 7136
7232 11:44:52.410131 # ok 1337 # SKIP Disabled ZA for VL 7136
7233 11:44:52.410231 # ok 1338 # SKIP Get and set data for VL 7136
7234 11:44:52.410320 # ok 1339 Set VL 7152
7235 11:44:52.410401 # ok 1340 # SKIP Disabled ZA for VL 7152
7236 11:44:52.410483 # ok 1341 # SKIP Get and set data for VL 7152
7237 11:44:52.410562 # ok 1342 Set VL 7168
7238 11:44:52.410640 # ok 1343 # SKIP Disabled ZA for VL 7168
7239 11:44:52.410720 # ok 1344 # SKIP Get and set data for VL 7168
7240 11:44:52.410801 # ok 1345 Set VL 7184
7241 11:44:52.410882 # ok 1346 # SKIP Disabled ZA for VL 7184
7242 11:44:52.410983 # ok 1347 # SKIP Get and set data for VL 7184
7243 11:44:52.411068 # ok 1348 Set VL 7200
7244 11:44:52.411149 # ok 1349 # SKIP Disabled ZA for VL 7200
7245 11:44:52.411230 # ok 1350 # SKIP Get and set data for VL 7200
7246 11:44:52.411311 # ok 1351 Set VL 7216
7247 11:44:52.411393 # ok 1352 # SKIP Disabled ZA for VL 7216
7248 11:44:52.411492 # ok 1353 # SKIP Get and set data for VL 7216
7249 11:44:52.411575 # ok 1354 Set VL 7232
7250 11:44:52.411656 # ok 1355 # SKIP Disabled ZA for VL 7232
7251 11:44:52.421070 # ok 1356 # SKIP Get and set data for VL 7232
7252 11:44:52.421535 # ok 1357 Set VL 7248
7253 11:44:52.421643 # ok 1358 # SKIP Disabled ZA for VL 7248
7254 11:44:52.421752 # ok 1359 # SKIP Get and set data for VL 7248
7255 11:44:52.421842 # ok 1360 Set VL 7264
7256 11:44:52.421927 # ok 1361 # SKIP Disabled ZA for VL 7264
7257 11:44:52.422014 # ok 1362 # SKIP Get and set data for VL 7264
7258 11:44:52.422099 # ok 1363 Set VL 7280
7259 11:44:52.422182 # ok 1364 # SKIP Disabled ZA for VL 7280
7260 11:44:52.422472 # ok 1365 # SKIP Get and set data for VL 7280
7261 11:44:52.422578 # ok 1366 Set VL 7296
7262 11:44:52.422671 # ok 1367 # SKIP Disabled ZA for VL 7296
7263 11:44:52.422758 # ok 1368 # SKIP Get and set data for VL 7296
7264 11:44:52.422844 # ok 1369 Set VL 7312
7265 11:44:52.422929 # ok 1370 # SKIP Disabled ZA for VL 7312
7266 11:44:52.423014 # ok 1371 # SKIP Get and set data for VL 7312
7267 11:44:52.423100 # ok 1372 Set VL 7328
7268 11:44:52.423190 # ok 1373 # SKIP Disabled ZA for VL 7328
7269 11:44:52.423271 # ok 1374 # SKIP Get and set data for VL 7328
7270 11:44:52.423346 # ok 1375 Set VL 7344
7271 11:44:52.423416 # ok 1376 # SKIP Disabled ZA for VL 7344
7272 11:44:52.423487 # ok 1377 # SKIP Get and set data for VL 7344
7273 11:44:52.423557 # ok 1378 Set VL 7360
7274 11:44:52.432392 # ok 1379 # SKIP Disabled ZA for VL 7360
7275 11:44:52.432900 # ok 1380 # SKIP Get and set data for VL 7360
7276 11:44:52.433096 # ok 1381 Set VL 7376
7277 11:44:52.433525 # ok 1382 # SKIP Disabled ZA for VL 7376
7278 11:44:52.433752 # ok 1383 # SKIP Get and set data for VL 7376
7279 11:44:52.433919 # ok 1384 Set VL 7392
7280 11:44:52.434061 # ok 1385 # SKIP Disabled ZA for VL 7392
7281 11:44:52.434199 # ok 1386 # SKIP Get and set data for VL 7392
7282 11:44:52.434377 # ok 1387 Set VL 7408
7283 11:44:52.434524 # ok 1388 # SKIP Disabled ZA for VL 7408
7284 11:44:52.434668 # ok 1389 # SKIP Get and set data for VL 7408
7285 11:44:52.434810 # ok 1390 Set VL 7424
7286 11:44:52.434996 # ok 1391 # SKIP Disabled ZA for VL 7424
7287 11:44:52.435134 # ok 1392 # SKIP Get and set data for VL 7424
7288 11:44:52.435279 # ok 1393 Set VL 7440
7289 11:44:52.435423 # ok 1394 # SKIP Disabled ZA for VL 7440
7290 11:44:52.435566 # ok 1395 # SKIP Get and set data for VL 7440
7291 11:44:52.435709 # ok 1396 Set VL 7456
7292 11:44:52.435851 # ok 1397 # SKIP Disabled ZA for VL 7456
7293 11:44:52.435992 # ok 1398 # SKIP Get and set data for VL 7456
7294 11:44:52.436133 # ok 1399 Set VL 7472
7295 11:44:52.436278 # ok 1400 # SKIP Disabled ZA for VL 7472
7296 11:44:52.436420 # ok 1401 # SKIP Get and set data for VL 7472
7297 11:44:52.436562 # ok 1402 Set VL 7488
7298 11:44:52.436702 # ok 1403 # SKIP Disabled ZA for VL 7488
7299 11:44:52.436844 # ok 1404 # SKIP Get and set data for VL 7488
7300 11:44:52.436986 # ok 1405 Set VL 7504
7301 11:44:52.437128 # ok 1406 # SKIP Disabled ZA for VL 7504
7302 11:44:52.437319 # ok 1407 # SKIP Get and set data for VL 7504
7303 11:44:52.437456 # ok 1408 Set VL 7520
7304 11:44:52.437598 # ok 1409 # SKIP Disabled ZA for VL 7520
7305 11:44:52.444552 # ok 1410 # SKIP Get and set data for VL 7520
7306 11:44:52.444880 # ok 1411 Set VL 7536
7307 11:44:52.445052 # ok 1412 # SKIP Disabled ZA for VL 7536
7308 11:44:52.445410 # ok 1413 # SKIP Get and set data for VL 7536
7309 11:44:52.445519 # ok 1414 Set VL 7552
7310 11:44:52.445609 # ok 1415 # SKIP Disabled ZA for VL 7552
7311 11:44:52.445704 # ok 1416 # SKIP Get and set data for VL 7552
7312 11:44:52.445791 # ok 1417 Set VL 7568
7313 11:44:52.445880 # ok 1418 # SKIP Disabled ZA for VL 7568
7314 11:44:52.445967 # ok 1419 # SKIP Get and set data for VL 7568
7315 11:44:52.446051 # ok 1420 Set VL 7584
7316 11:44:52.446151 # ok 1421 # SKIP Disabled ZA for VL 7584
7317 11:44:52.446238 # ok 1422 # SKIP Get and set data for VL 7584
7318 11:44:52.446328 # ok 1423 Set VL 7600
7319 11:44:52.446415 # ok 1424 # SKIP Disabled ZA for VL 7600
7320 11:44:52.446499 # ok 1425 # SKIP Get and set data for VL 7600
7321 11:44:52.446584 # ok 1426 Set VL 7616
7322 11:44:52.446667 # ok 1427 # SKIP Disabled ZA for VL 7616
7323 11:44:52.446769 # ok 1428 # SKIP Get and set data for VL 7616
7324 11:44:52.446853 # ok 1429 Set VL 7632
7325 11:44:52.446935 # ok 1430 # SKIP Disabled ZA for VL 7632
7326 11:44:52.447018 # ok 1431 # SKIP Get and set data for VL 7632
7327 11:44:52.447101 # ok 1432 Set VL 7648
7328 11:44:52.447198 # ok 1433 # SKIP Disabled ZA for VL 7648
7329 11:44:52.447281 # ok 1434 # SKIP Get and set data for VL 7648
7330 11:44:52.447361 # ok 1435 Set VL 7664
7331 11:44:52.447434 # ok 1436 # SKIP Disabled ZA for VL 7664
7332 11:44:52.465992 # ok 1437 # SKIP Get and set data for VL 7664
7333 11:44:52.466467 # ok 1438 Set VL 7680
7334 11:44:52.466573 # ok 1439 # SKIP Disabled ZA for VL 7680
7335 11:44:52.466663 # ok 1440 # SKIP Get and set data for VL 7680
7336 11:44:52.466747 # ok 1441 Set VL 7696
7337 11:44:52.466828 # ok 1442 # SKIP Disabled ZA for VL 7696
7338 11:44:52.466930 # ok 1443 # SKIP Get and set data for VL 7696
7339 11:44:52.467018 # ok 1444 Set VL 7712
7340 11:44:52.467102 # ok 1445 # SKIP Disabled ZA for VL 7712
7341 11:44:52.467184 # ok 1446 # SKIP Get and set data for VL 7712
7342 11:44:52.467273 # ok 1447 Set VL 7728
7343 11:44:52.467350 # ok 1448 # SKIP Disabled ZA for VL 7728
7344 11:44:52.468054 # ok 1449 # SKIP Get and set data for VL 7728
7345 11:44:52.468162 # ok 1450 Set VL 7744
7346 11:44:52.468453 # ok 1451 # SKIP Disabled ZA for VL 7744
7347 11:44:52.468559 # ok 1452 # SKIP Get and set data for VL 7744
7348 11:44:52.468649 # ok 1453 Set VL 7760
7349 11:44:52.468736 # ok 1454 # SKIP Disabled ZA for VL 7760
7350 11:44:52.468839 # ok 1455 # SKIP Get and set data for VL 7760
7351 11:44:52.468928 # ok 1456 Set VL 7776
7352 11:44:52.469028 # ok 1457 # SKIP Disabled ZA for VL 7776
7353 11:44:52.469115 # ok 1458 # SKIP Get and set data for VL 7776
7354 11:44:52.469200 # ok 1459 Set VL 7792
7355 11:44:52.469303 # ok 1460 # SKIP Disabled ZA for VL 7792
7356 11:44:52.469391 # ok 1461 # SKIP Get and set data for VL 7792
7357 11:44:52.469491 # ok 1462 Set VL 7808
7358 11:44:52.469580 # ok 1463 # SKIP Disabled ZA for VL 7808
7359 11:44:52.469905 # ok 1464 # SKIP Get and set data for VL 7808
7360 11:44:52.470005 # ok 1465 Set VL 7824
7361 11:44:52.470107 # ok 1466 # SKIP Disabled ZA for VL 7824
7362 11:44:52.470194 # ok 1467 # SKIP Get and set data for VL 7824
7363 11:44:52.470293 # ok 1468 Set VL 7840
7364 11:44:52.470381 # ok 1469 # SKIP Disabled ZA for VL 7840
7365 11:44:52.470489 # ok 1470 # SKIP Get and set data for VL 7840
7366 11:44:52.470575 # ok 1471 Set VL 7856
7367 11:44:52.470673 # ok 1472 # SKIP Disabled ZA for VL 7856
7368 11:44:52.470773 # ok 1473 # SKIP Get and set data for VL 7856
7369 11:44:52.470874 # ok 1474 Set VL 7872
7370 11:44:52.470975 # ok 1475 # SKIP Disabled ZA for VL 7872
7371 11:44:52.471075 # ok 1476 # SKIP Get and set data for VL 7872
7372 11:44:52.471396 # ok 1477 Set VL 7888
7373 11:44:52.472079 # ok 1478 # SKIP Disabled ZA for VL 7888
7374 11:44:52.472592 # ok 1479 # SKIP Get and set data for VL 7888
7375 11:44:52.472809 # ok 1480 Set VL 7904
7376 11:44:52.472973 # ok 1481 # SKIP Disabled ZA for VL 7904
7377 11:44:52.473181 # ok 1482 # SKIP Get and set data for VL 7904
7378 11:44:52.473357 # ok 1483 Set VL 7920
7379 11:44:52.473509 # ok 1484 # SKIP Disabled ZA for VL 7920
7380 11:44:52.473663 # ok 1485 # SKIP Get and set data for VL 7920
7381 11:44:52.473853 # ok 1486 Set VL 7936
7382 11:44:52.473994 # ok 1487 # SKIP Disabled ZA for VL 7936
7383 11:44:52.474139 # ok 1488 # SKIP Get and set data for VL 7936
7384 11:44:52.474283 # ok 1489 Set VL 7952
7385 11:44:52.474426 # ok 1490 # SKIP Disabled ZA for VL 7952
7386 11:44:52.474569 # ok 1491 # SKIP Get and set data for VL 7952
7387 11:44:52.474712 # ok 1492 Set VL 7968
7388 11:44:52.474854 # ok 1493 # SKIP Disabled ZA for VL 7968
7389 11:44:52.474998 # ok 1494 # SKIP Get and set data for VL 7968
7390 11:44:52.475178 # ok 1495 Set VL 7984
7391 11:44:52.475316 # ok 1496 # SKIP Disabled ZA for VL 7984
7392 11:44:52.475461 # ok 1497 # SKIP Get and set data for VL 7984
7393 11:44:52.475604 # ok 1498 Set VL 8000
7394 11:44:52.475745 # ok 1499 # SKIP Disabled ZA for VL 8000
7395 11:44:52.475887 # ok 1500 # SKIP Get and set data for VL 8000
7396 11:44:52.476029 # ok 1501 Set VL 8016
7397 11:44:52.476180 # ok 1502 # SKIP Disabled ZA for VL 8016
7398 11:44:52.476427 # ok 1503 # SKIP Get and set data for VL 8016
7399 11:44:52.476610 # ok 1504 Set VL 8032
7400 11:44:52.476761 # ok 1505 # SKIP Disabled ZA for VL 8032
7401 11:44:52.477030 # ok 1506 # SKIP Get and set data for VL 8032
7402 11:44:52.477223 # ok 1507 Set VL 8048
7403 11:44:52.477372 # ok 1508 # SKIP Disabled ZA for VL 8048
7404 11:44:52.477551 # ok 1509 # SKIP Get and set data for VL 8048
7405 11:44:52.477993 # ok 1510 Set VL 8064
7406 11:44:52.478232 # ok 1511 # SKIP Disabled ZA for VL 8064
7407 11:44:52.478442 # ok 1512 # SKIP Get and set data for VL 8064
7408 11:44:52.478649 # ok 1513 Set VL 8080
7409 11:44:52.478866 # ok 1514 # SKIP Disabled ZA for VL 8080
7410 11:44:52.479060 # ok 1515 # SKIP Get and set data for VL 8080
7411 11:44:52.479213 # ok 1516 Set VL 8096
7412 11:44:52.479335 # ok 1517 # SKIP Disabled ZA for VL 8096
7413 11:44:52.479484 # ok 1518 # SKIP Get and set data for VL 8096
7414 11:44:52.479606 # ok 1519 Set VL 8112
7415 11:44:52.479721 # ok 1520 # SKIP Disabled ZA for VL 8112
7416 11:44:52.479837 # ok 1521 # SKIP Get and set data for VL 8112
7417 11:44:52.479952 # ok 1522 Set VL 8128
7418 11:44:52.480095 # ok 1523 # SKIP Disabled ZA for VL 8128
7419 11:44:52.480217 # ok 1524 # SKIP Get and set data for VL 8128
7420 11:44:52.480335 # ok 1525 Set VL 8144
7421 11:44:52.480449 # ok 1526 # SKIP Disabled ZA for VL 8144
7422 11:44:52.480564 # ok 1527 # SKIP Get and set data for VL 8144
7423 11:44:52.480679 # ok 1528 Set VL 8160
7424 11:44:52.480794 # ok 1529 # SKIP Disabled ZA for VL 8160
7425 11:44:52.480909 # ok 1530 # SKIP Get and set data for VL 8160
7426 11:44:52.481024 # ok 1531 Set VL 8176
7427 11:44:52.481398 # ok 1532 # SKIP Disabled ZA for VL 8176
7428 11:44:52.481618 # ok 1533 # SKIP Get and set data for VL 8176
7429 11:44:52.481830 # ok 1534 Set VL 8192
7430 11:44:52.482019 # ok 1535 # SKIP Disabled ZA for VL 8192
7431 11:44:52.482164 # ok 1536 # SKIP Get and set data for VL 8192
7432 11:44:52.482307 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7433 11:44:52.482450 ok 34 selftests: arm64: za-ptrace
7434 11:44:52.482594 # selftests: arm64: check_buffer_fill
7435 11:44:52.872445 # 1..20
7436 11:44:52.872923 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7437 11:44:52.873037 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7438 11:44:52.873124 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7439 11:44:52.873226 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7440 11:44:52.873326 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7441 11:44:52.873426 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7442 11:44:52.873695 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 11:44:52.873815 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7444 11:44:52.874124 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7445 11:44:52.874434 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7446 11:44:52.874537 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7447 11:44:52.874630 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7448 11:44:52.874916 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7449 11:44:52.875028 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7450 11:44:52.883021 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7451 11:44:52.883550 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7452 11:44:52.898298 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7453 11:44:52.898902 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7454 11:44:52.899068 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7455 11:44:52.899198 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7456 11:44:52.899319 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7457 11:44:52.904027 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7458 11:44:53.032579 # selftests: arm64: check_child_memory
7459 11:44:53.516545 # 1..12
7460 11:44:53.517138 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7461 11:44:53.517326 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7462 11:44:53.517478 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7463 11:44:53.517683 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7464 11:44:53.517872 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7465 11:44:53.518036 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7466 11:44:53.518202 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7467 11:44:53.518365 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7468 11:44:53.518543 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7469 11:44:53.518670 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7470 11:44:53.518787 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7471 11:44:53.518904 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7472 11:44:53.519041 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7473 11:44:53.542092 not ok 36 selftests: arm64: check_child_memory # exit=1
7474 11:44:53.665512 # selftests: arm64: check_gcr_el1_cswitch
7475 11:45:38.862229 <47>[ 100.916649] systemd-journald[109]: Sent WATCHDOG=1 notification.
7476 11:45:39.378198 <47>[ 101.438512] systemd-journald[109]: Data hash table of /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal has a fill level at 75.0 (3296 of 4394 items, 2531328 file size, 768 bytes per hash table item), suggesting rotation.
7477 11:45:39.378643 <47>[ 101.439251] systemd-journald[109]: /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal: Journal header limits reached or header out-of-date, rotating.
7478 11:45:39.378765 <47>[ 101.439758] systemd-journald[109]: Rotating...
7479 11:45:39.404032 <47>[ 101.464839] systemd-journald[109]: Reserving 333 entries in field hash table.
7480 11:45:39.452232 <47>[ 101.512871] systemd-journald[109]: Reserving 4394 entries in data hash table.
7481 11:45:39.474295 <47>[ 101.535110] systemd-journald[109]: Vacuuming...
7482 11:45:39.487252 <47>[ 101.547824] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
7483 11:45:39.949370 # 1..1
7484 11:45:39.949618 # 1..1
7485 11:45:39.949716 # 1..1
7486 11:45:39.949803 # 1..1
7487 11:45:39.950148 # 1..1
7488 11:45:39.950351 # 1..1
7489 11:45:39.950520 # 1..1
7490 11:45:39.950678 # 1..1
7491 11:45:39.950830 # 1..1
7492 11:45:39.950984 # 1..1
7493 11:45:39.951139 # 1..1
7494 11:45:39.951295 # 1..1
7495 11:45:39.951448 # 1..1
7496 11:45:39.951615 # 1..1
7497 11:45:39.951770 # 1..1
7498 11:45:39.951895 # 1..1
7499 11:45:39.952018 # 1..1
7500 11:45:39.952139 # 1..1
7501 11:45:39.952259 # 1..1
7502 11:45:39.952381 # 1..1
7503 11:45:39.952500 # 1..1
7504 11:45:39.952620 # 1..1
7505 11:45:39.952739 # 1..1
7506 11:45:39.952860 # 1..1
7507 11:45:39.952979 # 1..1
7508 11:45:39.953100 # 1..1
7509 11:45:39.953220 # 1..1
7510 11:45:39.953338 # 1..1
7511 11:45:39.953458 # 1..1
7512 11:45:39.953570 # 1..1
7513 11:45:39.953707 # 1..1
7514 11:45:39.953823 # 1..1
7515 11:45:39.953936 # 1..1
7516 11:45:39.954059 # 1..1
7517 11:45:39.954221 # 1..1
7518 11:45:39.954346 # 1..1
7519 11:45:39.954464 # 1..1
7520 11:45:39.954579 # 1..1
7521 11:45:39.954698 # 1..1
7522 11:45:39.954815 # 1..1
7523 11:45:39.954932 # 1..1
7524 11:45:39.955047 # 1..1
7525 11:45:39.955160 # 1..1
7526 11:45:39.955274 # 1..1
7527 11:45:39.955388 # 1..1
7528 11:45:39.955554 # 1..1
7529 11:45:39.955696 # 1..1
7530 11:45:39.955815 # 1..1
7531 11:45:39.955930 # 1..1
7532 11:45:39.956066 # 1..1
7533 11:45:39.956208 # 1..1
7534 11:45:39.956326 # 1..1
7535 11:45:39.956440 # 1..1
7536 11:45:39.956556 # 1..1
7537 11:45:39.956670 # 1..1
7538 11:45:39.956784 # 1..1
7539 11:45:39.956897 # 1..1
7540 11:45:39.957013 # 1..1
7541 11:45:39.957128 # 1..1
7542 11:45:39.957243 # 1..1
7543 11:45:39.957356 # 1..1
7544 11:45:39.957472 # 1..1
7545 11:45:39.957586 # 1..1
7546 11:45:39.957715 # 1..1
7547 11:45:39.957830 # 1..1
7548 11:45:39.957944 # 1..1
7549 11:45:39.958059 # 1..1
7550 11:45:39.958173 # 1..1
7551 11:45:39.958287 # 1..1
7552 11:45:39.958401 # 1..1
7553 11:45:39.958514 # 1..1
7554 11:45:39.958629 # 1..1
7555 11:45:39.958751 # 1..1
7556 11:45:39.958866 # 1..1
7557 11:45:39.958981 # 1..1
7558 11:45:39.959094 # 1..1
7559 11:45:39.959210 # 1..1
7560 11:45:39.959323 # 1..1
7561 11:45:39.959452 # 1..1
7562 11:45:39.959614 # 1..1
7563 11:45:39.959736 # 1..1
7564 11:45:39.959853 # 1..1
7565 11:45:39.959968 # 1..1
7566 11:45:39.960082 # 1..1
7567 11:45:39.960196 # 1..1
7568 11:45:39.960310 # 1..1
7569 11:45:39.960423 # 1..1
7570 11:45:39.960536 # 1..1
7571 11:45:39.960650 # 1..1
7572 11:45:39.960763 # 1..1
7573 11:45:39.960876 # 1..1
7574 11:45:40.001317 # 1..1
7575 11:45:40.001643 # 1..1
7576 11:45:40.001822 # 1..1
7577 11:45:40.001968 # 1..1
7578 11:45:40.002101 # 1..1
7579 11:45:40.002252 # 1..1
7580 11:45:40.002402 # 1..1
7581 11:45:40.002857 # 1..1
7582 11:45:40.003055 # 1..1
7583 11:45:40.003219 # 1..1
7584 11:45:40.003351 # 1..1
7585 11:45:40.003530 # 1..1
7586 11:45:40.003705 # 1..1
7587 11:45:40.003849 # 1..1
7588 11:45:40.003990 # 1..1
7589 11:45:40.004131 # 1..1
7590 11:45:40.004271 # 1..1
7591 11:45:40.004411 # 1..1
7592 11:45:40.004551 # 1..1
7593 11:45:40.004691 # 1..1
7594 11:45:40.004830 # 1..1
7595 11:45:40.004970 # 1..1
7596 11:45:40.005110 # 1..1
7597 11:45:40.005248 # 1..1
7598 11:45:40.005388 # 1..1
7599 11:45:40.005531 # 1..1
7600 11:45:40.005684 # 1..1
7601 11:45:40.005828 # 1..1
7602 11:45:40.005968 # 1..1
7603 11:45:40.006107 # 1..1
7604 11:45:40.006266 # 1..1
7605 11:45:40.006454 # 1..1
7606 11:45:40.006628 # 1..1
7607 11:45:40.006771 # 1..1
7608 11:45:40.006912 # 1..1
7609 11:45:40.007071 # 1..1
7610 11:45:40.007259 # 1..1
7611 11:45:40.007437 # 1..1
7612 11:45:40.007592 # 1..1
7613 11:45:40.007716 # 1..1
7614 11:45:40.007841 # 1..1
7615 11:45:40.007968 # 1..1
7616 11:45:40.008147 # 1..1
7617 11:45:40.008287 # 1..1
7618 11:45:40.008438 # 1..1
7619 11:45:40.008596 # 1..1
7620 11:45:40.008721 # 1..1
7621 11:45:40.008843 # 1..1
7622 11:45:40.008966 # 1..1
7623 11:45:40.009090 # 1..1
7624 11:45:40.009213 # 1..1
7625 11:45:40.009335 # 1..1
7626 11:45:40.009458 # 1..1
7627 11:45:40.009581 # 1..1
7628 11:45:40.009714 # 1..1
7629 11:45:40.009838 # 1..1
7630 11:45:40.009960 # 1..1
7631 11:45:40.010083 # 1..1
7632 11:45:40.010204 # 1..1
7633 11:45:40.010324 # 1..1
7634 11:45:40.010445 # 1..1
7635 11:45:40.010609 # 1..1
7636 11:45:40.010734 # 1..1
7637 11:45:40.010851 # 1..1
7638 11:45:40.010970 # 1..1
7639 11:45:40.011087 # 1..1
7640 11:45:40.011202 # 1..1
7641 11:45:40.011315 # 1..1
7642 11:45:40.011429 # 1..1
7643 11:45:40.011545 # 1..1
7644 11:45:40.011661 # 1..1
7645 11:45:40.011777 # 1..1
7646 11:45:40.011891 # 1..1
7647 11:45:40.012032 # 1..1
7648 11:45:40.012176 # 1..1
7649 11:45:40.012294 # 1..1
7650 11:45:40.012418 # 1..1
7651 11:45:40.012540 # 1..1
7652 11:45:40.012656 # 1..1
7653 11:45:40.012772 # 1..1
7654 11:45:40.012887 # 1..1
7655 11:45:40.013016 # 1..1
7656 11:45:40.013162 # 1..1
7657 11:45:40.013279 # 1..1
7658 11:45:40.013394 # 1..1
7659 11:45:40.013511 # 1..1
7660 11:45:40.013625 # 1..1
7661 11:45:40.013753 # 1..1
7662 11:45:40.013868 # 1..1
7663 11:45:40.013982 # 1..1
7664 11:45:40.014096 # 1..1
7665 11:45:40.014211 # 1..1
7666 11:45:40.014324 # 1..1
7667 11:45:40.014438 # 1..1
7668 11:45:40.014557 # 1..1
7669 11:45:40.014673 # 1..1
7670 11:45:40.014787 # 1..1
7671 11:45:40.014901 # 1..1
7672 11:45:40.015014 # 1..1
7673 11:45:40.015128 # 1..1
7674 11:45:40.015244 # 1..1
7675 11:45:40.015357 # 1..1
7676 11:45:40.015472 # 1..1
7677 11:45:40.020115 # 1..1
7678 11:45:40.020358 # 1..1
7679 11:45:40.020480 # 1..1
7680 11:45:40.020600 # 1..1
7681 11:45:40.020717 # 1..1
7682 11:45:40.020867 # 1..1
7683 11:45:40.021043 # 1..1
7684 11:45:40.021184 # 1..1
7685 11:45:40.021302 # 1..1
7686 11:45:40.021744 # 1..1
7687 11:45:40.033238 # 1..1
7688 11:45:40.033484 # 1..1
7689 11:45:40.033583 # 1..1
7690 11:45:40.033686 # 1..1
7691 11:45:40.033992 # 1..1
7692 11:45:40.034097 # 1..1
7693 11:45:40.034187 # 1..1
7694 11:45:40.034273 # 1..1
7695 11:45:40.034360 # 1..1
7696 11:45:40.034451 # 1..1
7697 11:45:40.034539 # 1..1
7698 11:45:40.034625 # 1..1
7699 11:45:40.034711 # 1..1
7700 11:45:40.034799 # 1..1
7701 11:45:40.034886 # 1..1
7702 11:45:40.034973 # 1..1
7703 11:45:40.035061 # 1..1
7704 11:45:40.035147 # 1..1
7705 11:45:40.035234 # 1..1
7706 11:45:40.035317 # 1..1
7707 11:45:40.035403 # 1..1
7708 11:45:40.035494 # 1..1
7709 11:45:40.035579 # 1..1
7710 11:45:40.035658 # 1..1
7711 11:45:40.035737 # 1..1
7712 11:45:40.035818 # 1..1
7713 11:45:40.035900 # 1..1
7714 11:45:40.035990 # 1..1
7715 11:45:40.036074 # 1..1
7716 11:45:40.036156 # 1..1
7717 11:45:40.036238 # 1..1
7718 11:45:40.036354 # 1..1
7719 11:45:40.036444 # 1..1
7720 11:45:40.036533 # 1..1
7721 11:45:40.036619 # 1..1
7722 11:45:40.036703 # 1..1
7723 11:45:40.036787 # 1..1
7724 11:45:40.036871 # 1..1
7725 11:45:40.036957 # 1..1
7726 11:45:40.037044 # 1..1
7727 11:45:40.037131 # 1..1
7728 11:45:40.037218 # 1..1
7729 11:45:40.037305 # 1..1
7730 11:45:40.037392 # 1..1
7731 11:45:40.037479 # 1..1
7732 11:45:40.037565 # 1..1
7733 11:45:40.038347 # 1..1
7734 11:45:40.038465 # 1..1
7735 11:45:40.038552 # 1..1
7736 11:45:40.038635 # 1..1
7737 11:45:40.038721 # 1..1
7738 11:45:40.038809 # 1..1
7739 11:45:40.038898 # 1..1
7740 11:45:40.038987 # 1..1
7741 11:45:40.039070 # 1..1
7742 11:45:40.039151 # 1..1
7743 11:45:40.039234 # 1..1
7744 11:45:40.039320 # 1..1
7745 11:45:40.039408 # 1..1
7746 11:45:40.039504 # 1..1
7747 11:45:40.039587 # 1..1
7748 11:45:40.039667 # 1..1
7749 11:45:40.039749 # 1..1
7750 11:45:40.039832 # 1..1
7751 11:45:40.039915 # 1..1
7752 11:45:40.040001 # 1..1
7753 11:45:40.040087 # 1..1
7754 11:45:40.040173 # 1..1
7755 11:45:40.040254 # 1..1
7756 11:45:40.040338 # 1..1
7757 11:45:40.040421 # 1..1
7758 11:45:40.040506 # 1..1
7759 11:45:40.040589 # 1..1
7760 11:45:40.040671 # 1..1
7761 11:45:40.040756 # 1..1
7762 11:45:40.040841 # 1..1
7763 11:45:40.040927 # 1..1
7764 11:45:40.041015 # 1..1
7765 11:45:40.041101 # 1..1
7766 11:45:40.041188 # 1..1
7767 11:45:40.041274 # 1..1
7768 11:45:40.041360 # 1..1
7769 11:45:40.041448 # 1..1
7770 11:45:40.041532 # 1..1
7771 11:45:40.041614 # 1..1
7772 11:45:40.041707 # 1..1
7773 11:45:40.041791 # 1..1
7774 11:45:40.041869 # 1..1
7775 11:45:40.041953 # 1..1
7776 11:45:40.042039 # 1..1
7777 11:45:40.042124 # 1..1
7778 11:45:40.042208 # 1..1
7779 11:45:40.042290 # 1..1
7780 11:45:40.042371 # 1..1
7781 11:45:40.042455 # 1..1
7782 11:45:40.042536 # 1..1
7783 11:45:40.042620 # 1..1
7784 11:45:40.042704 # 1..1
7785 11:45:40.042789 # 1..1
7786 11:45:40.042874 # 1..1
7787 11:45:40.042959 # 1..1
7788 11:45:40.043044 # 1..1
7789 11:45:40.059423 # 1..1
7790 11:45:40.059893 # 1..1
7791 11:45:40.059995 # 1..1
7792 11:45:40.060082 # 1..1
7793 11:45:40.060169 # 1..1
7794 11:45:40.060252 # 1..1
7795 11:45:40.060333 # 1..1
7796 11:45:40.060415 # 1..1
7797 11:45:40.060498 # 1..1
7798 11:45:40.060584 # 1..1
7799 11:45:40.060669 # 1..1
7800 11:45:40.060751 # 1..1
7801 11:45:40.060837 # 1..1
7802 11:45:40.060918 # 1..1
7803 11:45:40.061006 # 1..1
7804 11:45:40.061092 # 1..1
7805 11:45:40.061175 # 1..1
7806 11:45:40.061258 # 1..1
7807 11:45:40.061342 # 1..1
7808 11:45:40.061447 # 1..1
7809 11:45:40.061536 # 1..1
7810 11:45:40.061624 # 1..1
7811 11:45:40.061722 # 1..1
7812 11:45:40.077609 # 1..1
7813 11:45:40.078102 # 1..1
7814 11:45:40.078266 # 1..1
7815 11:45:40.078417 # 1..1
7816 11:45:40.078561 # 1..1
7817 11:45:40.078703 # 1..1
7818 11:45:40.078842 # 1..1
7819 11:45:40.078982 # 1..1
7820 11:45:40.079121 # 1..1
7821 11:45:40.079261 # 1..1
7822 11:45:40.079400 # 1..1
7823 11:45:40.079547 # 1..1
7824 11:45:40.079689 # 1..1
7825 11:45:40.079828 # 1..1
7826 11:45:40.080014 # 1..1
7827 11:45:40.080148 # 1..1
7828 11:45:40.080290 # 1..1
7829 11:45:40.080431 # 1..1
7830 11:45:40.080576 # 1..1
7831 11:45:40.080718 # 1..1
7832 11:45:40.080857 # 1..1
7833 11:45:40.080996 # 1..1
7834 11:45:40.081135 # 1..1
7835 11:45:40.081274 # 1..1
7836 11:45:40.081413 # 1..1
7837 11:45:40.081555 # 1..1
7838 11:45:40.081718 # 1..1
7839 11:45:40.081862 # 1..1
7840 11:45:40.082004 # 1..1
7841 11:45:40.082147 # 1..1
7842 11:45:40.082286 # 1..1
7843 11:45:40.082428 # 1..1
7844 11:45:40.082568 # 1..1
7845 11:45:40.082709 # 1..1
7846 11:45:40.082851 # 1..1
7847 11:45:40.082992 # 1..1
7848 11:45:40.083134 # 1..1
7849 11:45:40.083274 # 1..1
7850 11:45:40.083415 # 1..1
7851 11:45:40.083555 # 1..1
7852 11:45:40.083696 # 1..1
7853 11:45:40.083837 # 1..1
7854 11:45:40.083978 # 1..1
7855 11:45:40.084119 # 1..1
7856 11:45:40.084260 # 1..1
7857 11:45:40.084403 # 1..1
7858 11:45:40.084545 # 1..1
7859 11:45:40.084687 # 1..1
7860 11:45:40.084826 # 1..1
7861 11:45:40.084967 # 1..1
7862 11:45:40.085107 # 1..1
7863 11:45:40.085247 # 1..1
7864 11:45:40.085388 # 1..1
7865 11:45:40.085527 # 1..1
7866 11:45:40.085682 # 1..1
7867 11:45:40.085826 # 1..1
7868 11:45:40.085965 # 1..1
7869 11:45:40.086106 # 1..1
7870 11:45:40.086247 # 1..1
7871 11:45:40.086434 # 1..1
7872 11:45:40.086626 # 1..1
7873 11:45:40.086797 # 1..1
7874 11:45:40.086942 # 1..1
7875 11:45:40.087083 # 1..1
7876 11:45:40.087225 # 1..1
7877 11:45:40.087365 # 1..1
7878 11:45:40.087506 # 1..1
7879 11:45:40.087647 # 1..1
7880 11:45:40.087785 # 1..1
7881 11:45:40.087924 # 1..1
7882 11:45:40.088062 # 1..1
7883 11:45:40.088202 # 1..1
7884 11:45:40.088341 # 1..1
7885 11:45:40.088480 # 1..1
7886 11:45:40.088622 # 1..1
7887 11:45:40.088761 # 1..1
7888 11:45:40.088948 # 1..1
7889 11:45:40.089082 # 1..1
7890 11:45:40.089224 # 1..1
7891 11:45:40.102174 # 1..1
7892 11:45:40.102774 # 1..1
7893 11:45:40.102942 # 1..1
7894 11:45:40.103073 # 1..1
7895 11:45:40.103197 # 1..1
7896 11:45:40.103317 # 1..1
7897 11:45:40.103446 # 1..1
7898 11:45:40.103621 # 1..1
7899 11:45:40.103766 # 1..1
7900 11:45:40.103909 # 1..1
7901 11:45:40.104051 # 1..1
7902 11:45:40.104191 # 1..1
7903 11:45:40.104331 # 1..1
7904 11:45:40.104472 # 1..1
7905 11:45:40.104613 # 1..1
7906 11:45:40.104754 # 1..1
7907 11:45:40.104894 # 1..1
7908 11:45:40.105080 # 1..1
7909 11:45:40.105213 # 1..1
7910 11:45:40.105354 # 1..1
7911 11:45:40.105495 # 1..1
7912 11:45:40.105638 # 1..1
7913 11:45:40.105794 # 1..1
7914 11:45:40.105935 # 1..1
7915 11:45:40.106075 # 1..1
7916 11:45:40.106215 # 1..1
7917 11:45:40.106354 # 1..1
7918 11:45:40.106494 # 1..1
7919 11:45:40.106636 # 1..1
7920 11:45:40.106777 # 1..1
7921 11:45:40.106917 # 1..1
7922 11:45:40.107057 # 1..1
7923 11:45:40.107198 # 1..1
7924 11:45:40.107337 # 1..1
7925 11:45:40.107476 # 1..1
7926 11:45:40.107615 # 1..1
7927 11:45:40.107755 # 1..1
7928 11:45:40.107896 # 1..1
7929 11:45:40.108036 # 1..1
7930 11:45:40.108176 # 1..1
7931 11:45:40.108315 # 1..1
7932 11:45:40.108455 # 1..1
7933 11:45:40.108594 # 1..1
7934 11:45:40.108734 # 1..1
7935 11:45:40.108875 # 1..1
7936 11:45:40.109016 # 1..1
7937 11:45:40.109156 # 1..1
7938 11:45:40.109297 # 1..1
7939 11:45:40.109437 # 1..1
7940 11:45:40.109576 # 1..1
7941 11:45:40.109733 # 1..1
7942 11:45:40.109875 # 1..1
7943 11:45:40.110015 # 1..1
7944 11:45:40.110155 # 1..1
7945 11:45:40.110296 # 1..1
7946 11:45:40.110435 # 1..1
7947 11:45:40.110573 # 1..1
7948 11:45:40.110716 # 1..1
7949 11:45:40.110857 # 1..1
7950 11:45:40.110998 # 1..1
7951 11:45:40.111137 # 1..1
7952 11:45:40.126861 # 1..1
7953 11:45:40.127249 # 1..1
7954 11:45:40.127355 # 1..1
7955 11:45:40.127446 # 1..1
7956 11:45:40.127531 # 1..1
7957 11:45:40.127616 # 1..1
7958 11:45:40.127699 # 1..1
7959 11:45:40.127782 # 1..1
7960 11:45:40.127866 # 1..1
7961 11:45:40.127942 # 1..1
7962 11:45:40.128024 # 1..1
7963 11:45:40.128126 # 1..1
7964 11:45:40.128212 # 1..1
7965 11:45:40.128286 # 1..1
7966 11:45:40.128360 # 1..1
7967 11:45:40.128433 # 1..1
7968 11:45:40.128505 # 1..1
7969 11:45:40.128578 # 1..1
7970 11:45:40.128656 # 1..1
7971 11:45:40.128751 # 1..1
7972 11:45:40.128821 # 1..1
7973 11:45:40.128893 # 1..1
7974 11:45:40.128965 # 1..1
7975 11:45:40.129037 # 1..1
7976 11:45:40.129109 # 1..1
7977 11:45:40.129181 # 1..1
7978 11:45:40.129253 # 1..1
7979 11:45:40.129326 # 1..1
7980 11:45:40.129397 # 1..1
7981 11:45:40.129469 # 1..1
7982 11:45:40.129539 # 1..1
7983 11:45:40.129613 # 1..1
7984 11:45:40.129767 # 1..1
7985 11:45:40.129906 # 1..1
7986 11:45:40.130043 # 1..1
7987 11:45:40.130182 # 1..1
7988 11:45:40.130321 # 1..1
7989 11:45:40.130458 # 1..1
7990 11:45:40.130597 # 1..1
7991 11:45:40.143691 #
7992 11:45:40.143963 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
7993 11:45:40.454947 # selftests: arm64: check_ksm_options
7994 11:45:40.811341 # 1..4
7995 11:45:40.811588 # # Invalid MTE synchronous exception caught!
7996 11:45:40.861414 not ok 38 selftests: arm64: check_ksm_options # exit=1
7997 11:45:41.174064 # selftests: arm64: check_mmap_options
7998 11:45:42.036142 # 1..22
7999 11:45:42.036606 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
8000 11:45:42.049540 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
8001 11:45:42.049781 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
8002 11:45:42.049894 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
8003 11:45:42.049999 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
8004 11:45:42.050102 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8005 11:45:42.050410 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
8006 11:45:42.050529 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8007 11:45:42.050862 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
8008 11:45:42.050987 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8009 11:45:42.051343 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
8010 11:45:42.051553 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8011 11:45:42.051766 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
8012 11:45:42.051948 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8013 11:45:42.052186 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
8014 11:45:42.063323 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8015 11:45:42.063829 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
8016 11:45:42.063936 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8017 11:45:42.064033 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
8018 11:45:42.064321 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8019 11:45:42.064427 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
8020 11:45:42.099215 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
8021 11:45:42.099513 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
8022 11:45:42.108798 not ok 39 selftests: arm64: check_mmap_options # exit=1
8023 11:45:42.411297 # selftests: arm64: check_prctl
8024 11:45:42.713289 # TAP version 13
8025 11:45:42.713541 # 1..5
8026 11:45:42.713847 # ok 1 check_basic_read
8027 11:45:42.713945 # ok 2 NONE
8028 11:45:42.714030 # ok 3 SYNC
8029 11:45:42.714113 # ok 4 ASYNC
8030 11:45:42.714194 # ok 5 SYNC+ASYNC
8031 11:45:42.714275 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8032 11:45:42.749586 ok 40 selftests: arm64: check_prctl
8033 11:45:43.053504 # selftests: arm64: check_tags_inclusion
8034 11:45:43.421591 # 1..4
8035 11:45:43.421862 # # Unexpected fault recorded for 0x700ffffaecc0000-0x700ffffaecc0050 in mode 1
8036 11:45:43.422176 # not ok 1 Check an included tag value with sync mode
8037 11:45:43.422284 # # Unexpected fault recorded for 0x100ffffaecc0000-0x100ffffaecc0050 in mode 1
8038 11:45:43.422375 # not ok 2 Check different included tags value with sync mode
8039 11:45:43.422468 # ok 3 Check none included tags value with sync mode
8040 11:45:43.422555 # # Unexpected fault recorded for 0x100ffffaecc0000-0x100ffffaecc0050 in mode 1
8041 11:45:43.422640 # not ok 4 Check all included tags value with sync mode
8042 11:45:43.422745 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
8043 11:45:43.482850 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
8044 11:45:43.782130 # selftests: arm64: check_user_mem
8045 11:45:52.694598 # 1..64
8046 11:45:52.695265 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8047 11:45:52.695378 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8048 11:45:52.695473 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8049 11:45:52.695560 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8050 11:45:52.695667 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8051 11:45:52.695755 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8052 11:45:52.695936 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8053 11:45:52.696111 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8054 11:45:52.697765 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8055 11:45:52.698170 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8056 11:45:52.698281 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8057 11:45:52.698374 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8058 11:45:52.698480 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8059 11:45:52.698587 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8060 11:45:52.698876 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8061 11:45:52.698996 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8062 11:45:52.699101 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8063 11:45:52.699414 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8064 11:45:52.699535 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8065 11:45:52.699826 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8066 11:45:52.699936 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8067 11:45:52.700041 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8068 11:45:52.700852 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8069 11:45:52.701284 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8070 11:45:52.701453 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8071 11:45:52.701629 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8072 11:45:52.701822 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8073 11:45:52.702046 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8074 11:45:52.702269 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8075 11:45:52.702450 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8076 11:45:52.702607 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8077 11:45:52.702843 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8078 11:45:52.703039 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8079 11:45:52.703251 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8080 11:45:52.703433 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8081 11:45:52.703667 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8082 11:45:52.703862 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8083 11:45:52.704070 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8084 11:45:52.704268 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8085 11:45:52.704444 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8086 11:45:52.712843 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8087 11:45:52.713360 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8088 11:45:52.713468 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8089 11:45:52.713574 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8090 11:45:52.713680 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8091 11:45:52.713782 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8092 11:45:52.714126 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8093 11:45:52.714245 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8094 11:45:52.714557 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8095 11:45:52.714674 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8096 11:45:52.714970 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8097 11:45:54.374471 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8098 11:45:54.374712 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8099 11:45:54.374823 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8100 11:45:54.374916 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8101 11:45:54.375018 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8102 11:45:54.375320 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8103 11:45:54.375440 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8104 11:45:54.375544 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8105 11:45:54.375828 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8106 11:45:54.375931 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8107 11:45:54.376214 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8108 11:45:54.381945 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8109 11:45:54.382166 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8110 11:45:54.382246 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
8111 11:45:54.407423 ok 42 selftests: arm64: check_user_mem
8112 11:45:54.533698 # selftests: arm64: btitest
8113 11:45:54.721955 # TAP version 13
8114 11:45:54.722260 # 1..18
8115 11:45:54.722426 # # HWCAP_PACA present
8116 11:45:54.722586 # # HWCAP2_BTI present
8117 11:45:54.722755 # # Test binary built for BTI
8118 11:45:54.722950 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
8119 11:45:54.723096 # ok 1 nohint_func/call_using_br_x0
8120 11:45:54.723257 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
8121 11:45:54.723420 # ok 2 nohint_func/call_using_br_x16
8122 11:45:54.723586 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
8123 11:45:54.723798 # ok 3 nohint_func/call_using_blr
8124 11:45:54.724038 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
8125 11:45:54.724202 # ok 4 bti_none_func/call_using_br_x0
8126 11:45:54.724349 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
8127 11:45:54.724493 # ok 5 bti_none_func/call_using_br_x16
8128 11:45:54.724634 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
8129 11:45:54.724774 # ok 6 bti_none_func/call_using_blr
8130 11:45:54.724914 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
8131 11:45:54.725055 # ok 7 bti_c_func/call_using_br_x0
8132 11:45:54.725228 # ok 8 bti_c_func/call_using_br_x16
8133 11:45:54.731742 # ok 9 bti_c_func/call_using_blr
8134 11:45:54.732253 # ok 10 bti_j_func/call_using_br_x0
8135 11:45:54.732416 # ok 11 bti_j_func/call_using_br_x16
8136 11:45:54.732537 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
8137 11:45:54.732654 # ok 12 bti_j_func/call_using_blr
8138 11:45:54.732769 # ok 13 bti_jc_func/call_using_br_x0
8139 11:45:54.732883 # ok 14 bti_jc_func/call_using_br_x16
8140 11:45:54.750251 # ok 15 bti_jc_func/call_using_blr
8141 11:45:54.750718 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
8142 11:45:54.750848 # ok 16 paciasp_func/call_using_br_x0
8143 11:45:54.750966 # ok 17 paciasp_func/call_using_br_x16
8144 11:45:54.751081 # ok 18 paciasp_func/call_using_blr
8145 11:45:54.751196 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8146 11:45:54.751335 ok 43 selftests: arm64: btitest
8147 11:45:54.877471 # selftests: arm64: nobtitest
8148 11:45:54.998483 # TAP version 13
8149 11:45:54.998773 # 1..18
8150 11:45:54.998956 # # HWCAP_PACA present
8151 11:45:54.999404 # # HWCAP2_BTI present
8152 11:45:54.999612 # # Test binary not built for BTI
8153 11:45:54.999830 # ok 1 nohint_func/call_using_br_x0
8154 11:45:55.000042 # ok 2 nohint_func/call_using_br_x16
8155 11:45:55.000194 # ok 3 nohint_func/call_using_blr
8156 11:45:55.000316 # ok 4 bti_none_func/call_using_br_x0
8157 11:45:55.000430 # ok 5 bti_none_func/call_using_br_x16
8158 11:45:55.000541 # ok 6 bti_none_func/call_using_blr
8159 11:45:55.000652 # ok 7 bti_c_func/call_using_br_x0
8160 11:45:55.000762 # ok 8 bti_c_func/call_using_br_x16
8161 11:45:55.000873 # ok 9 bti_c_func/call_using_blr
8162 11:45:55.001016 # ok 10 bti_j_func/call_using_br_x0
8163 11:45:55.001135 # ok 11 bti_j_func/call_using_br_x16
8164 11:45:55.001247 # ok 12 bti_j_func/call_using_blr
8165 11:45:55.001360 # ok 13 bti_jc_func/call_using_br_x0
8166 11:45:55.001470 # ok 14 bti_jc_func/call_using_br_x16
8167 11:45:55.001581 # ok 15 bti_jc_func/call_using_blr
8168 11:45:55.001747 # ok 16 paciasp_func/call_using_br_x0
8169 11:45:55.001950 # ok 17 paciasp_func/call_using_br_x16
8170 11:45:55.002173 # ok 18 paciasp_func/call_using_blr
8171 11:45:55.002349 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8172 11:45:55.021871 ok 44 selftests: arm64: nobtitest
8173 11:45:55.151230 # selftests: arm64: hwcap
8174 11:45:55.302037 # TAP version 13
8175 11:45:55.302286 # 1..28
8176 11:45:55.302378 # # RNG present
8177 11:45:55.302715 # ok 1 cpuinfo_match_RNG
8178 11:45:55.302918 # ok 2 sigill_RNG
8179 11:45:55.303123 # # SME present
8180 11:45:55.303323 # ok 3 cpuinfo_match_SME
8181 11:45:55.303521 # ok 4 sigill_SME
8182 11:45:55.303710 # # SVE present
8183 11:45:55.303899 # ok 5 cpuinfo_match_SVE
8184 11:45:55.304110 # ok 6 sigill_SVE
8185 11:45:55.304317 # # SVE 2 present
8186 11:45:55.304562 # ok 7 cpuinfo_match_SVE 2
8187 11:45:55.304736 # ok 8 sigill_SVE 2
8188 11:45:55.304926 # # SVE AES present
8189 11:45:55.305114 # ok 9 cpuinfo_match_SVE AES
8190 11:45:55.305303 # ok 10 sigill_SVE AES
8191 11:45:55.305492 # # SVE2 PMULL present
8192 11:45:55.305693 # ok 11 cpuinfo_match_SVE2 PMULL
8193 11:45:55.305881 # ok 12 sigill_SVE2 PMULL
8194 11:45:55.306068 # # SVE2 BITPERM present
8195 11:45:55.306255 # ok 13 cpuinfo_match_SVE2 BITPERM
8196 11:45:55.306442 # ok 14 sigill_SVE2 BITPERM
8197 11:45:55.306651 # # SVE2 SHA3 present
8198 11:45:55.306849 # ok 15 cpuinfo_match_SVE2 SHA3
8199 11:45:55.307040 # ok 16 sigill_SVE2 SHA3
8200 11:45:55.307223 # # SVE2 SM4 present
8201 11:45:55.307397 # ok 17 cpuinfo_match_SVE2 SM4
8202 11:45:55.307563 # ok 18 sigill_SVE2 SM4
8203 11:45:55.307736 # # SVE2 I8MM present
8204 11:45:55.307881 # ok 19 cpuinfo_match_SVE2 I8MM
8205 11:45:55.308044 # ok 20 sigill_SVE2 I8MM
8206 11:45:55.308199 # # SVE2 F32MM present
8207 11:45:55.308359 # ok 21 cpuinfo_match_SVE2 F32MM
8208 11:45:55.308482 # ok 22 sigill_SVE2 F32MM
8209 11:45:55.308600 # # SVE2 F64MM present
8210 11:45:55.308715 # ok 23 cpuinfo_match_SVE2 F64MM
8211 11:45:55.308831 # ok 24 sigill_SVE2 F64MM
8212 11:45:55.311064 # # SVE2 BF16 present
8213 11:45:55.311472 # ok 25 cpuinfo_match_SVE2 BF16
8214 11:45:55.311604 # ok 26 sigill_SVE2 BF16
8215 11:45:55.311726 # ok 27 cpuinfo_match_SVE2 EBF16
8216 11:45:55.311844 # ok 28 # SKIP sigill_SVE2 EBF16
8217 11:45:55.311962 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8218 11:45:55.336267 ok 45 selftests: arm64: hwcap
8219 11:45:55.494706 # selftests: arm64: ptrace
8220 11:45:55.709792 # TAP version 13
8221 11:45:55.710122 # 1..7
8222 11:45:55.710534 # # Parent is 4321, child is 4322
8223 11:45:55.710674 # ok 1 read_tpidr_one
8224 11:45:55.710796 # ok 2 write_tpidr_one
8225 11:45:55.710916 # ok 3 verify_tpidr_one
8226 11:45:55.711033 # ok 4 count_tpidrs
8227 11:45:55.711150 # ok 5 tpidr2_write
8228 11:45:55.711268 # ok 6 tpidr2_read
8229 11:45:55.711385 # ok 7 write_tpidr_only
8230 11:45:55.711502 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8231 11:45:55.733896 ok 46 selftests: arm64: ptrace
8232 11:45:55.882017 # selftests: arm64: syscall-abi
8233 11:45:58.543228 # TAP version 13
8234 11:45:58.543680 # 1..514
8235 11:45:58.543794 # # SME with FA64
8236 11:45:58.543890 # ok 1 getpid() FPSIMD
8237 11:45:58.543979 # ok 2 getpid() SVE VL 256
8238 11:45:58.544271 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8239 11:45:58.544368 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8240 11:45:58.544449 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8241 11:45:58.552498 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8242 11:45:58.553036 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8243 11:45:58.553149 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8244 11:45:58.553244 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8245 11:45:58.553338 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8246 11:45:58.553445 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8247 11:45:58.553781 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8248 11:45:58.553889 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8249 11:45:58.553976 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8250 11:45:58.554065 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8251 11:45:58.554156 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8252 11:45:58.554240 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8253 11:45:58.554524 # ok 18 getpid() SVE VL 240
8254 11:45:58.554633 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8255 11:45:58.554724 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8256 11:45:58.554810 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8257 11:45:58.554893 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8258 11:45:58.555026 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8259 11:45:58.555116 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8260 11:45:58.555206 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8261 11:45:58.555292 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8262 11:45:58.555395 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8263 11:45:58.555486 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8264 11:45:58.555572 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8265 11:45:58.555680 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8266 11:45:58.555767 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8267 11:45:58.555868 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8268 11:45:58.555970 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8269 11:45:58.556071 # ok 34 getpid() SVE VL 224
8270 11:45:58.556710 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8271 11:45:58.556996 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8272 11:45:58.557121 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8273 11:45:58.557232 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8274 11:45:58.557322 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8275 11:45:58.557422 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8276 11:45:58.557524 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8277 11:45:58.557855 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8278 11:45:58.557959 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8279 11:45:58.558062 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8280 11:45:58.558164 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8281 11:45:58.558265 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8282 11:45:58.558559 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8283 11:45:58.558661 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8284 11:45:58.559040 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8285 11:45:58.559493 # ok 50 getpid() SVE VL 208
8286 11:45:58.559702 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8287 11:45:58.559884 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8288 11:45:58.560054 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8289 11:45:58.560240 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8290 11:45:58.560372 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8291 11:45:58.560493 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8292 11:45:58.560609 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8293 11:45:58.560727 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8294 11:45:58.560844 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8295 11:45:58.564597 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8296 11:45:58.565063 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8297 11:45:58.565262 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8298 11:45:58.565432 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8299 11:45:58.565813 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8300 11:45:58.565918 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8301 11:45:58.566006 # ok 66 getpid() SVE VL 192
8302 11:45:58.566092 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8303 11:45:58.566178 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8304 11:45:58.566265 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8305 11:45:58.566348 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8306 11:45:58.566432 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8307 11:45:58.566514 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8308 11:45:58.566601 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8309 11:45:58.566702 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8310 11:45:58.566787 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8311 11:45:58.566871 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8312 11:45:58.566955 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8313 11:45:58.567039 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8314 11:45:58.567122 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8315 11:45:58.567223 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8316 11:45:58.567310 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8317 11:45:58.567395 # ok 82 getpid() SVE VL 176
8318 11:45:58.567480 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8319 11:45:58.567564 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8320 11:45:58.567670 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8321 11:45:58.567756 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8322 11:45:58.567843 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8323 11:45:58.567944 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8324 11:45:58.568027 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8325 11:45:58.568123 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8326 11:45:58.572500 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8327 11:45:58.573002 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8328 11:45:58.573179 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8329 11:45:58.573307 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8330 11:45:58.573424 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8331 11:45:58.573541 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8332 11:45:58.573704 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8333 11:45:58.573875 # ok 98 getpid() SVE VL 160
8334 11:46:01.069405 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8335 11:46:01.069670 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8336 11:46:01.069978 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8337 11:46:01.070080 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8338 11:46:01.070167 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8339 11:46:01.070252 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8340 11:46:01.070337 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8341 11:46:01.070439 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8342 11:46:01.070524 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8343 11:46:01.070608 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8344 11:46:01.070690 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8345 11:46:01.070771 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8346 11:46:01.070870 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8347 11:46:01.070957 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8348 11:46:01.071057 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8349 11:46:01.071142 # ok 114 getpid() SVE VL 144
8350 11:46:01.071241 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8351 11:46:01.071340 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8352 11:46:01.071425 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8353 11:46:01.071524 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8354 11:46:01.071622 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8355 11:46:01.071722 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8356 11:46:01.071820 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8357 11:46:01.072085 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8358 11:46:01.077562 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8359 11:46:01.078129 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8360 11:46:01.078325 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8361 11:46:01.078477 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8362 11:46:01.078612 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8363 11:46:01.078731 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8364 11:46:01.078850 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8365 11:46:01.079026 # ok 130 getpid() SVE VL 128
8366 11:46:01.079154 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8367 11:46:01.079279 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8368 11:46:01.079418 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8369 11:46:01.079551 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8370 11:46:01.079689 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8371 11:46:01.079829 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8372 11:46:01.079956 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8373 11:46:01.080086 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8374 11:46:01.080232 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8375 11:46:01.080352 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8376 11:46:01.080467 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8377 11:46:01.080581 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8378 11:46:01.080694 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8379 11:46:01.080807 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8380 11:46:01.080920 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8381 11:46:01.081033 # ok 146 getpid() SVE VL 112
8382 11:46:01.081147 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8383 11:46:01.081260 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8384 11:46:01.081373 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8385 11:46:01.081486 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8386 11:46:01.085069 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8387 11:46:01.085565 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8388 11:46:01.085745 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8389 11:46:01.085898 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8390 11:46:01.086063 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8391 11:46:01.086228 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8392 11:46:01.086427 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8393 11:46:01.086601 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8394 11:46:01.086769 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8395 11:46:01.086936 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8396 11:46:01.087101 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8397 11:46:01.087268 # ok 162 getpid() SVE VL 96
8398 11:46:01.087435 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8399 11:46:01.087638 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8400 11:46:01.087789 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8401 11:46:01.087906 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8402 11:46:01.088072 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8403 11:46:01.088202 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8404 11:46:01.088315 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8405 11:46:01.088429 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8406 11:46:01.088556 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8407 11:46:01.088671 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8408 11:46:01.088784 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8409 11:46:01.088897 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8410 11:46:01.089015 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8411 11:46:01.089809 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8412 11:46:01.089916 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8413 11:46:01.089998 # ok 178 getpid() SVE VL 80
8414 11:46:01.090075 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8415 11:46:01.090152 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8416 11:46:01.092854 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8417 11:46:01.093170 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8418 11:46:01.093273 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8419 11:46:01.093375 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8420 11:46:01.093463 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8421 11:46:01.093563 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8422 11:46:01.093671 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8423 11:46:01.093772 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8424 11:46:01.093881 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8425 11:46:01.094155 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8426 11:46:01.094280 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8427 11:46:01.094395 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8428 11:46:01.094488 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8429 11:46:01.094577 # ok 194 getpid() SVE VL 64
8430 11:46:01.094683 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8431 11:46:03.353675 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8432 11:46:03.354233 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8433 11:46:03.354429 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8434 11:46:03.354605 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8435 11:46:03.354756 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8436 11:46:03.354901 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8437 11:46:03.355044 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8438 11:46:03.355228 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8439 11:46:03.355368 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8440 11:46:03.355512 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8441 11:46:03.355662 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8442 11:46:03.355804 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8443 11:46:03.355948 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8444 11:46:03.356090 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8445 11:46:03.356234 # ok 210 getpid() SVE VL 48
8446 11:46:03.356376 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8447 11:46:03.356517 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8448 11:46:03.356658 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8449 11:46:03.356799 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8450 11:46:03.356941 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8451 11:46:03.357126 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8452 11:46:03.357261 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8453 11:46:03.357403 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8454 11:46:03.357546 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8455 11:46:03.357708 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8456 11:46:03.357854 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8457 11:46:03.357997 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8458 11:46:03.358138 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8459 11:46:03.358281 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8460 11:46:03.358423 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8461 11:46:03.358564 # ok 226 getpid() SVE VL 32
8462 11:46:03.358709 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8463 11:46:03.364753 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8464 11:46:03.365199 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8465 11:46:03.365341 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8466 11:46:03.365490 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8467 11:46:03.365637 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8468 11:46:03.365797 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8469 11:46:03.365983 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8470 11:46:03.366120 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8471 11:46:03.366262 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8472 11:46:03.366405 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8473 11:46:03.366549 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8474 11:46:03.366692 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8475 11:46:03.366838 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8476 11:46:03.366980 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8477 11:46:03.367123 # ok 242 getpid() SVE VL 16
8478 11:46:03.367265 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8479 11:46:03.367409 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8480 11:46:03.367551 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8481 11:46:03.367741 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8482 11:46:03.367879 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8483 11:46:03.368021 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8484 11:46:03.368164 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8485 11:46:03.368307 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8486 11:46:03.368449 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8487 11:46:03.368591 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8488 11:46:03.368732 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8489 11:46:03.368873 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8490 11:46:03.369015 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8491 11:46:03.369156 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8492 11:46:03.369297 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8493 11:46:03.369439 # ok 258 sched_yield() FPSIMD
8494 11:46:03.369582 # ok 259 sched_yield() SVE VL 256
8495 11:46:03.369740 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8496 11:46:03.369885 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8497 11:46:03.370028 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8498 11:46:03.370211 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8499 11:46:03.370348 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8500 11:46:03.370491 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8501 11:46:03.370633 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8502 11:46:03.370775 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8503 11:46:03.376688 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8504 11:46:03.377156 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8505 11:46:03.377363 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8506 11:46:03.377537 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8507 11:46:03.377699 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8508 11:46:03.377871 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8509 11:46:03.378053 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8510 11:46:03.378189 # ok 275 sched_yield() SVE VL 240
8511 11:46:03.378317 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8512 11:46:03.378443 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8513 11:46:03.378568 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8514 11:46:03.378692 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8515 11:46:03.378818 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8516 11:46:03.378942 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8517 11:46:03.379067 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8518 11:46:03.379219 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8519 11:46:03.379351 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8520 11:46:03.379475 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8521 11:46:03.379601 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8522 11:46:03.379730 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8523 11:46:03.379852 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8524 11:46:03.379978 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8525 11:46:05.396937 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8526 11:46:05.397510 # ok 291 sched_yield() SVE VL 224
8527 11:46:05.397712 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8528 11:46:05.397890 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8529 11:46:05.398066 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8530 11:46:05.398239 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8531 11:46:05.398379 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8532 11:46:05.398513 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8533 11:46:05.398643 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8534 11:46:05.398772 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8535 11:46:05.398899 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8536 11:46:05.399028 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8537 11:46:05.399150 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8538 11:46:05.399307 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8539 11:46:05.399443 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8540 11:46:05.399572 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8541 11:46:05.399700 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8542 11:46:05.399827 # ok 307 sched_yield() SVE VL 208
8543 11:46:05.399957 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8544 11:46:05.400086 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8545 11:46:05.400212 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8546 11:46:05.400330 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8547 11:46:05.400448 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8548 11:46:05.400564 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8549 11:46:05.400682 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8550 11:46:05.400829 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8551 11:46:05.400954 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8552 11:46:05.401072 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8553 11:46:05.401191 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8554 11:46:05.401307 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8555 11:46:05.401425 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8556 11:46:05.401544 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8557 11:46:05.405328 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8558 11:46:05.405439 # ok 323 sched_yield() SVE VL 192
8559 11:46:05.405545 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8560 11:46:05.405857 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8561 11:46:05.405977 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8562 11:46:05.406080 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8563 11:46:05.406210 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8564 11:46:05.406314 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8565 11:46:05.406387 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8566 11:46:05.406483 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8567 11:46:05.406643 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8568 11:46:05.407117 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8569 11:46:05.407339 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8570 11:46:05.407792 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8571 11:46:05.408015 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8572 11:46:05.408210 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8573 11:46:05.408383 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8574 11:46:05.408532 # ok 339 sched_yield() SVE VL 176
8575 11:46:05.408676 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8576 11:46:05.408853 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8577 11:46:05.408992 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8578 11:46:05.412724 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8579 11:46:05.413289 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8580 11:46:05.413491 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8581 11:46:05.413673 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8582 11:46:05.413831 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8583 11:46:05.414019 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8584 11:46:05.414184 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8585 11:46:05.414351 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8586 11:46:05.414536 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8587 11:46:05.414684 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8588 11:46:05.414828 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8589 11:46:05.415007 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8590 11:46:05.415146 # ok 355 sched_yield() SVE VL 160
8591 11:46:05.415290 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8592 11:46:05.416734 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8593 11:46:05.416906 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8594 11:46:05.417028 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8595 11:46:05.417147 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8596 11:46:05.417264 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8597 11:46:05.417383 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8598 11:46:05.417500 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8599 11:46:05.417617 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8600 11:46:05.417753 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8601 11:46:05.417871 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8602 11:46:05.417989 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8603 11:46:05.418106 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8604 11:46:05.418224 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8605 11:46:05.418341 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8606 11:46:05.420714 # ok 371 sched_yield() SVE VL 144
8607 11:46:05.421318 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8608 11:46:05.421478 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8609 11:46:05.421601 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8610 11:46:05.421746 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8611 11:46:05.421889 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8612 11:46:07.498919 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8613 11:46:07.499402 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8614 11:46:07.499555 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8615 11:46:07.499684 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8616 11:46:07.499832 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8617 11:46:07.499971 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8618 11:46:07.500143 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8619 11:46:07.500277 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8620 11:46:07.500422 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8621 11:46:07.500566 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8622 11:46:07.500975 # ok 387 sched_yield() SVE VL 128
8623 11:46:07.501132 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8624 11:46:07.501254 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8625 11:46:07.501418 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8626 11:46:07.501561 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8627 11:46:07.501698 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8628 11:46:07.501843 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8629 11:46:07.501964 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8630 11:46:07.502080 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8631 11:46:07.502194 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8632 11:46:07.502332 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8633 11:46:07.502471 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8634 11:46:07.502618 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8635 11:46:07.502742 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8636 11:46:07.502883 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8637 11:46:07.503002 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8638 11:46:07.503116 # ok 403 sched_yield() SVE VL 112
8639 11:46:07.503254 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8640 11:46:07.503380 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8641 11:46:07.503580 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8642 11:46:07.503746 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8643 11:46:07.503872 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8644 11:46:07.504045 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8645 11:46:07.504199 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8646 11:46:07.504321 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8647 11:46:07.504436 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8648 11:46:07.504549 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8649 11:46:07.504666 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8650 11:46:07.504779 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8651 11:46:07.512624 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8652 11:46:07.513107 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8653 11:46:07.513237 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8654 11:46:07.513353 # ok 419 sched_yield() SVE VL 96
8655 11:46:07.513488 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8656 11:46:07.513626 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8657 11:46:07.513841 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8658 11:46:07.514013 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8659 11:46:07.514204 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8660 11:46:07.514422 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8661 11:46:07.514592 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8662 11:46:07.514755 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8663 11:46:07.514917 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8664 11:46:07.515107 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8665 11:46:07.515269 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8666 11:46:07.515441 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8667 11:46:07.515646 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8668 11:46:07.515882 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8669 11:46:07.516086 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8670 11:46:07.516248 # ok 435 sched_yield() SVE VL 80
8671 11:46:07.516367 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8672 11:46:07.516481 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8673 11:46:07.516593 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8674 11:46:07.516778 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8675 11:46:07.516913 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8676 11:46:07.517029 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8677 11:46:07.517142 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8678 11:46:07.517254 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8679 11:46:07.517365 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8680 11:46:07.517477 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8681 11:46:07.517591 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8682 11:46:07.520891 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8683 11:46:07.521386 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8684 11:46:07.521567 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8685 11:46:07.521725 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8686 11:46:07.521850 # ok 451 sched_yield() SVE VL 64
8687 11:46:07.522000 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8688 11:46:07.522128 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8689 11:46:07.522251 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8690 11:46:07.522372 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8691 11:46:07.522493 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8692 11:46:07.522642 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8693 11:46:07.522770 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8694 11:46:07.522887 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8695 11:46:07.523002 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8696 11:46:07.523116 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8697 11:46:07.523230 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8698 11:46:07.523343 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8699 11:46:08.211798 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8700 11:46:08.212041 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8701 11:46:08.212135 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8702 11:46:08.212222 # ok 467 sched_yield() SVE VL 48
8703 11:46:08.212524 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8704 11:46:08.212633 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8705 11:46:08.214357 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8706 11:46:08.214905 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8707 11:46:08.215107 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8708 11:46:08.215288 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8709 11:46:08.215470 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8710 11:46:08.215626 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8711 11:46:08.215779 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8712 11:46:08.215961 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8713 11:46:08.216132 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8714 11:46:08.216289 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8715 11:46:08.216412 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8716 11:46:08.216530 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8717 11:46:08.216646 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8718 11:46:08.216764 # ok 483 sched_yield() SVE VL 32
8719 11:46:08.216884 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8720 11:46:08.217073 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8721 11:46:08.217205 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8722 11:46:08.222946 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8723 11:46:08.223426 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8724 11:46:08.223624 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8725 11:46:08.223839 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8726 11:46:08.224075 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8727 11:46:08.224259 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8728 11:46:08.224436 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8729 11:46:08.224593 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8730 11:46:08.224736 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8731 11:46:08.224896 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8732 11:46:08.225092 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8733 11:46:08.225349 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8734 11:46:08.225535 # ok 499 sched_yield() SVE VL 16
8735 11:46:08.225717 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8736 11:46:08.225910 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8737 11:46:08.226073 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8738 11:46:08.226225 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8739 11:46:08.226383 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8740 11:46:08.226593 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8741 11:46:08.226739 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8742 11:46:08.226873 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8743 11:46:08.227037 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8744 11:46:08.227156 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8745 11:46:08.227269 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8746 11:46:08.227380 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8747 11:46:08.227492 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8748 11:46:08.227611 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8749 11:46:08.227727 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8750 11:46:08.227840 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8751 11:46:08.227979 ok 47 selftests: arm64: syscall-abi
8752 11:46:08.276705 # selftests: arm64: tpidr2
8753 11:46:08.433256 # TAP version 13
8754 11:46:08.433726 # 1..5
8755 11:46:08.433905 # # PID: 4356
8756 11:46:08.434082 # ok 1 default_value
8757 11:46:08.434231 # ok 2 write_read
8758 11:46:08.434410 # ok 3 write_sleep_read
8759 11:46:08.434549 # ok 4 write_fork_read
8760 11:46:08.434691 # ok 5 write_clone_read
8761 11:46:08.434832 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8762 11:46:08.455605 ok 48 selftests: arm64: tpidr2
8763 11:46:08.962813 arm64_tags_test pass
8764 11:46:08.963073 arm64_run_tags_test_sh pass
8765 11:46:08.963463 arm64_fake_sigreturn_bad_magic pass
8766 11:46:08.963644 arm64_fake_sigreturn_bad_size pass
8767 11:46:08.963790 arm64_fake_sigreturn_bad_size_for_magic0 pass
8768 11:46:08.963920 arm64_fake_sigreturn_duplicated_fpsimd pass
8769 11:46:08.964102 arm64_fake_sigreturn_misaligned_sp pass
8770 11:46:08.964293 arm64_fake_sigreturn_missing_fpsimd pass
8771 11:46:08.964505 arm64_fake_sigreturn_sme_change_vl pass
8772 11:46:08.964662 arm64_fake_sigreturn_sve_change_vl pass
8773 11:46:08.964837 arm64_mangle_pstate_invalid_compat_toggle pass
8774 11:46:08.964983 arm64_mangle_pstate_invalid_daif_bits pass
8775 11:46:08.965125 arm64_mangle_pstate_invalid_mode_el1h pass
8776 11:46:08.965862 arm64_mangle_pstate_invalid_mode_el1t pass
8777 11:46:08.966056 arm64_mangle_pstate_invalid_mode_el2h pass
8778 11:46:08.966238 arm64_mangle_pstate_invalid_mode_el2t pass
8779 11:46:08.966391 arm64_mangle_pstate_invalid_mode_el3h pass
8780 11:46:08.966534 arm64_mangle_pstate_invalid_mode_el3t pass
8781 11:46:08.966673 arm64_sme_trap_no_sm pass
8782 11:46:08.966814 arm64_sme_trap_non_streaming skip
8783 11:46:08.966968 arm64_sme_trap_za pass
8784 11:46:08.967114 arm64_sme_vl pass
8785 11:46:08.967270 arm64_ssve_regs pass
8786 11:46:08.967449 arm64_sve_regs pass
8787 11:46:08.967609 arm64_sve_vl pass
8788 11:46:08.967757 arm64_za_no_regs pass
8789 11:46:08.967912 arm64_za_regs pass
8790 11:46:08.968063 arm64_pac_global_corrupt_pac pass
8791 11:46:08.968200 arm64_pac_global_pac_instructions_not_nop pass
8792 11:46:08.968557 arm64_pac_global_pac_instructions_not_nop_generic pass
8793 11:46:08.968723 arm64_pac_global_single_thread_different_keys pass
8794 11:46:08.968859 arm64_pac_global_exec_changed_keys pass
8795 11:46:08.968986 arm64_pac_global_context_switch_keep_keys pass
8796 11:46:08.969113 arm64_pac_global_context_switch_keep_keys_generic pass
8797 11:46:08.969238 arm64_pac pass
8798 11:46:08.969363 arm64_fp-stress_FPSIMD-0-0 pass
8799 11:46:08.969481 arm64_fp-stress_SVE-VL-256-0 pass
8800 11:46:08.969604 arm64_fp-stress_SVE-VL-240-0 pass
8801 11:46:08.969741 arm64_fp-stress_SVE-VL-224-0 pass
8802 11:46:08.969861 arm64_fp-stress_SVE-VL-208-0 pass
8803 11:46:08.969984 arm64_fp-stress_SVE-VL-192-0 pass
8804 11:46:08.970102 arm64_fp-stress_SVE-VL-176-0 pass
8805 11:46:08.970220 arm64_fp-stress_SVE-VL-160-0 pass
8806 11:46:08.970338 arm64_fp-stress_SVE-VL-144-0 pass
8807 11:46:08.970456 arm64_fp-stress_SVE-VL-128-0 pass
8808 11:46:08.970573 arm64_fp-stress_SVE-VL-112-0 pass
8809 11:46:08.970697 arm64_fp-stress_SVE-VL-96-0 pass
8810 11:46:08.970815 arm64_fp-stress_SVE-VL-80-0 pass
8811 11:46:08.970933 arm64_fp-stress_SVE-VL-64-0 pass
8812 11:46:08.971050 arm64_fp-stress_SVE-VL-48-0 pass
8813 11:46:08.971168 arm64_fp-stress_SVE-VL-32-0 pass
8814 11:46:08.972394 arm64_fp-stress_SVE-VL-16-0 pass
8815 11:46:08.972839 arm64_fp-stress_SSVE-VL-256-0 pass
8816 11:46:08.973031 arm64_fp-stress_ZA-VL-256-0 pass
8817 11:46:08.973176 arm64_fp-stress_SSVE-VL-128-0 pass
8818 11:46:08.973333 arm64_fp-stress_ZA-VL-128-0 pass
8819 11:46:08.973497 arm64_fp-stress_SSVE-VL-64-0 pass
8820 11:46:08.973704 arm64_fp-stress_ZA-VL-64-0 pass
8821 11:46:08.973874 arm64_fp-stress_SSVE-VL-32-0 pass
8822 11:46:08.974032 arm64_fp-stress_ZA-VL-32-0 pass
8823 11:46:08.974188 arm64_fp-stress_SSVE-VL-16-0 pass
8824 11:46:08.974339 arm64_fp-stress_ZA-VL-16-0 pass
8825 11:46:08.974471 arm64_fp-stress pass
8826 11:46:08.974633 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8827 11:46:08.974794 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8828 11:46:08.974990 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8829 11:46:08.975161 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8830 11:46:08.975384 arm64_sve-ptrace_Set_SVE_VL_16 pass
8831 11:46:08.975605 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8832 11:46:08.975810 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8833 11:46:08.976009 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8834 11:46:08.976221 arm64_sve-ptrace_Set_SVE_VL_32 pass
8835 11:46:08.976372 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8836 11:46:08.976522 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8837 11:46:08.976646 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8838 11:46:08.976762 arm64_sve-ptrace_Set_SVE_VL_48 pass
8839 11:46:08.976876 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8840 11:46:08.976991 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8841 11:46:08.977107 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8842 11:46:08.977221 arm64_sve-ptrace_Set_SVE_VL_64 pass
8843 11:46:08.977334 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8844 11:46:08.977448 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8845 11:46:08.980347 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8846 11:46:08.980834 arm64_sve-ptrace_Set_SVE_VL_80 pass
8847 11:46:08.981038 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8848 11:46:08.981207 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8849 11:46:08.981369 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8850 11:46:08.981576 arm64_sve-ptrace_Set_SVE_VL_96 pass
8851 11:46:08.981755 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8852 11:46:08.981903 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8853 11:46:08.982062 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8854 11:46:08.982221 arm64_sve-ptrace_Set_SVE_VL_112 pass
8855 11:46:08.982429 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8856 11:46:08.982590 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8857 11:46:08.982759 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8858 11:46:08.982907 arm64_sve-ptrace_Set_SVE_VL_128 pass
8859 11:46:08.983047 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8860 11:46:08.983204 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8861 11:46:08.984101 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8862 11:46:08.984297 arm64_sve-ptrace_Set_SVE_VL_144 pass
8863 11:46:08.984472 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8864 11:46:08.984616 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8865 11:46:08.984759 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8866 11:46:08.984901 arm64_sve-ptrace_Set_SVE_VL_160 pass
8867 11:46:08.985043 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8868 11:46:08.985223 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8869 11:46:08.985362 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8870 11:46:08.985505 arm64_sve-ptrace_Set_SVE_VL_176 pass
8871 11:46:08.985655 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8872 11:46:08.988324 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8873 11:46:08.988756 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8874 11:46:08.988955 arm64_sve-ptrace_Set_SVE_VL_192 pass
8875 11:46:08.989178 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8876 11:46:08.989421 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8877 11:46:08.989609 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8878 11:46:08.989797 arm64_sve-ptrace_Set_SVE_VL_208 pass
8879 11:46:08.990013 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8880 11:46:08.990215 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8881 11:46:08.990375 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8882 11:46:08.990581 arm64_sve-ptrace_Set_SVE_VL_224 pass
8883 11:46:08.990756 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8884 11:46:08.990897 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8885 11:46:08.991086 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8886 11:46:08.991297 arm64_sve-ptrace_Set_SVE_VL_240 pass
8887 11:46:08.991495 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8888 11:46:08.991708 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8889 11:46:08.991890 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8890 11:46:08.992053 arm64_sve-ptrace_Set_SVE_VL_256 pass
8891 11:46:08.992177 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8892 11:46:08.992293 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8893 11:46:08.992439 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8894 11:46:08.992562 arm64_sve-ptrace_Set_SVE_VL_272 pass
8895 11:46:08.992678 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8896 11:46:08.992792 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8897 11:46:08.992947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8898 11:46:08.993078 arm64_sve-ptrace_Set_SVE_VL_288 pass
8899 11:46:08.996271 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8900 11:46:08.996740 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8901 11:46:08.996949 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8902 11:46:08.997124 arm64_sve-ptrace_Set_SVE_VL_304 pass
8903 11:46:08.997270 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8904 11:46:08.997495 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8905 11:46:08.997735 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8906 11:46:08.997952 arm64_sve-ptrace_Set_SVE_VL_320 pass
8907 11:46:08.998164 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8908 11:46:08.998372 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8909 11:46:08.998588 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8910 11:46:08.998738 arm64_sve-ptrace_Set_SVE_VL_336 pass
8911 11:46:08.998874 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8912 11:46:08.999097 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8913 11:46:08.999294 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8914 11:46:08.999493 arm64_sve-ptrace_Set_SVE_VL_352 pass
8915 11:46:08.999698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8916 11:46:08.999924 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8917 11:46:09.000091 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8918 11:46:09.000256 arm64_sve-ptrace_Set_SVE_VL_368 pass
8919 11:46:09.000381 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8920 11:46:09.000498 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8921 11:46:09.000612 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8922 11:46:09.000729 arm64_sve-ptrace_Set_SVE_VL_384 pass
8923 11:46:09.000844 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8924 11:46:09.000960 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8925 11:46:09.001075 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8926 11:46:09.001190 arm64_sve-ptrace_Set_SVE_VL_400 pass
8927 11:46:09.001304 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8928 11:46:09.001448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8929 11:46:09.004297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8930 11:46:09.004732 arm64_sve-ptrace_Set_SVE_VL_416 pass
8931 11:46:09.004940 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8932 11:46:09.005140 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8933 11:46:09.005383 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8934 11:46:09.005586 arm64_sve-ptrace_Set_SVE_VL_432 pass
8935 11:46:09.005740 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
8936 11:46:09.005863 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
8937 11:46:09.006005 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
8938 11:46:09.006165 arm64_sve-ptrace_Set_SVE_VL_448 pass
8939 11:46:09.006314 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
8940 11:46:09.006441 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
8941 11:46:09.019385 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
8942 11:46:09.019691 arm64_sve-ptrace_Set_SVE_VL_464 pass
8943 11:46:09.020103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
8944 11:46:09.020310 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
8945 11:46:09.020491 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
8946 11:46:09.020668 arm64_sve-ptrace_Set_SVE_VL_480 pass
8947 11:46:09.020814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
8948 11:46:09.020957 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
8949 11:46:09.021137 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
8950 11:46:09.021276 arm64_sve-ptrace_Set_SVE_VL_496 pass
8951 11:46:09.021436 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
8952 11:46:09.021608 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
8953 11:46:09.021806 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
8954 11:46:09.021985 arm64_sve-ptrace_Set_SVE_VL_512 pass
8955 11:46:09.022242 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
8956 11:46:09.022441 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
8957 11:46:09.022616 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
8958 11:46:09.022785 arm64_sve-ptrace_Set_SVE_VL_528 pass
8959 11:46:09.022921 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
8960 11:46:09.023070 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
8961 11:46:09.023266 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
8962 11:46:09.023466 arm64_sve-ptrace_Set_SVE_VL_544 pass
8963 11:46:09.023683 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
8964 11:46:09.023879 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
8965 11:46:09.024089 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
8966 11:46:09.024247 arm64_sve-ptrace_Set_SVE_VL_560 pass
8967 11:46:09.024368 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
8968 11:46:09.024485 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
8969 11:46:09.024602 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
8970 11:46:09.024718 arm64_sve-ptrace_Set_SVE_VL_576 pass
8971 11:46:09.024834 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
8972 11:46:09.024951 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
8973 11:46:09.025094 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
8974 11:46:09.025218 arm64_sve-ptrace_Set_SVE_VL_592 pass
8975 11:46:09.025335 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
8976 11:46:09.028299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
8977 11:46:09.028758 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
8978 11:46:09.028942 arm64_sve-ptrace_Set_SVE_VL_608 pass
8979 11:46:09.029115 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
8980 11:46:09.029284 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
8981 11:46:09.029489 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
8982 11:46:09.029684 arm64_sve-ptrace_Set_SVE_VL_624 pass
8983 11:46:09.029895 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
8984 11:46:09.030099 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
8985 11:46:09.030279 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
8986 11:46:09.030505 arm64_sve-ptrace_Set_SVE_VL_640 pass
8987 11:46:09.030768 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
8988 11:46:09.030956 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
8989 11:46:09.031148 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
8990 11:46:09.031313 arm64_sve-ptrace_Set_SVE_VL_656 pass
8991 11:46:09.031462 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
8992 11:46:09.031637 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
8993 11:46:09.031817 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
8994 11:46:09.031969 arm64_sve-ptrace_Set_SVE_VL_672 pass
8995 11:46:09.032410 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
8996 11:46:09.032544 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
8997 11:46:09.032695 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
8998 11:46:09.032819 arm64_sve-ptrace_Set_SVE_VL_688 pass
8999 11:46:09.032937 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
9000 11:46:09.033053 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
9001 11:46:09.033240 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
9002 11:46:09.033418 arm64_sve-ptrace_Set_SVE_VL_704 pass
9003 11:46:09.033620 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
9004 11:46:09.033810 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
9005 11:46:09.033947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
9006 11:46:09.034106 arm64_sve-ptrace_Set_SVE_VL_720 pass
9007 11:46:09.034287 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
9008 11:46:09.036328 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
9009 11:46:09.036812 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
9010 11:46:09.037017 arm64_sve-ptrace_Set_SVE_VL_736 pass
9011 11:46:09.037221 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
9012 11:46:09.037417 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
9013 11:46:09.037630 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
9014 11:46:09.037809 arm64_sve-ptrace_Set_SVE_VL_752 pass
9015 11:46:09.037956 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
9016 11:46:09.038166 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
9017 11:46:09.038339 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
9018 11:46:09.038496 arm64_sve-ptrace_Set_SVE_VL_768 pass
9019 11:46:09.038641 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
9020 11:46:09.038809 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
9021 11:46:09.039019 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
9022 11:46:09.039173 arm64_sve-ptrace_Set_SVE_VL_784 pass
9023 11:46:09.039329 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
9024 11:46:09.039523 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
9025 11:46:09.039724 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
9026 11:46:09.039889 arm64_sve-ptrace_Set_SVE_VL_800 pass
9027 11:46:09.040051 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
9028 11:46:09.040248 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
9029 11:46:09.040384 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
9030 11:46:09.040503 arm64_sve-ptrace_Set_SVE_VL_816 pass
9031 11:46:09.040618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
9032 11:46:09.040731 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
9033 11:46:09.040878 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
9034 11:46:09.041001 arm64_sve-ptrace_Set_SVE_VL_832 pass
9035 11:46:09.041115 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
9036 11:46:09.041229 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
9037 11:46:09.041343 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
9038 11:46:09.041455 arm64_sve-ptrace_Set_SVE_VL_848 pass
9039 11:46:09.041568 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
9040 11:46:09.041746 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
9041 11:46:09.044318 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
9042 11:46:09.044724 arm64_sve-ptrace_Set_SVE_VL_864 pass
9043 11:46:09.044843 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
9044 11:46:09.044938 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
9045 11:46:09.045046 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
9046 11:46:09.045139 arm64_sve-ptrace_Set_SVE_VL_880 pass
9047 11:46:09.045229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
9048 11:46:09.045342 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
9049 11:46:09.045433 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
9050 11:46:09.045524 arm64_sve-ptrace_Set_SVE_VL_896 pass
9051 11:46:09.045633 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
9052 11:46:09.045734 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
9053 11:46:09.045836 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
9054 11:46:09.045927 arm64_sve-ptrace_Set_SVE_VL_912 pass
9055 11:46:09.046034 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
9056 11:46:09.046129 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
9057 11:46:09.046233 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
9058 11:46:09.046342 arm64_sve-ptrace_Set_SVE_VL_928 pass
9059 11:46:09.046445 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
9060 11:46:09.046530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
9061 11:46:09.046824 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
9062 11:46:09.046930 arm64_sve-ptrace_Set_SVE_VL_944 pass
9063 11:46:09.047020 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
9064 11:46:09.047124 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
9065 11:46:09.047218 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
9066 11:46:09.047306 arm64_sve-ptrace_Set_SVE_VL_960 pass
9067 11:46:09.047408 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
9068 11:46:09.047506 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
9069 11:46:09.047609 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
9070 11:46:09.047699 arm64_sve-ptrace_Set_SVE_VL_976 pass
9071 11:46:09.047801 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
9072 11:46:09.047902 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
9073 11:46:09.048011 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
9074 11:46:09.052297 arm64_sve-ptrace_Set_SVE_VL_992 pass
9075 11:46:09.052618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
9076 11:46:09.052725 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
9077 11:46:09.052830 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
9078 11:46:09.052918 arm64_sve-ptrace_Set_SVE_VL_1008 pass
9079 11:46:09.053002 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
9080 11:46:09.053104 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
9081 11:46:09.053211 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
9082 11:46:09.053298 arm64_sve-ptrace_Set_SVE_VL_1024 pass
9083 11:46:09.053396 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
9084 11:46:09.053499 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
9085 11:46:09.053601 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
9086 11:46:09.053713 arm64_sve-ptrace_Set_SVE_VL_1040 pass
9087 11:46:09.053814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
9088 11:46:09.054157 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
9089 11:46:09.054402 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
9090 11:46:09.054577 arm64_sve-ptrace_Set_SVE_VL_1056 pass
9091 11:46:09.054721 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
9092 11:46:09.054876 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
9093 11:46:09.055029 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
9094 11:46:09.055195 arm64_sve-ptrace_Set_SVE_VL_1072 pass
9095 11:46:09.055387 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
9096 11:46:09.055555 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
9097 11:46:09.055715 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
9098 11:46:09.055873 arm64_sve-ptrace_Set_SVE_VL_1088 pass
9099 11:46:09.056052 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
9100 11:46:09.056178 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
9101 11:46:09.056292 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
9102 11:46:09.056406 arm64_sve-ptrace_Set_SVE_VL_1104 pass
9103 11:46:09.069349 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
9104 11:46:09.069884 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
9105 11:46:09.070114 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
9106 11:46:09.070325 arm64_sve-ptrace_Set_SVE_VL_1120 pass
9107 11:46:09.070526 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
9108 11:46:09.070702 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
9109 11:46:09.070896 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
9110 11:46:09.071067 arm64_sve-ptrace_Set_SVE_VL_1136 pass
9111 11:46:09.071221 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
9112 11:46:09.071370 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
9113 11:46:09.071507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
9114 11:46:09.071669 arm64_sve-ptrace_Set_SVE_VL_1152 pass
9115 11:46:09.071881 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
9116 11:46:09.072097 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
9117 11:46:09.072292 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
9118 11:46:09.072426 arm64_sve-ptrace_Set_SVE_VL_1168 pass
9119 11:46:09.072547 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
9120 11:46:09.072663 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
9121 11:46:09.072779 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
9122 11:46:09.072894 arm64_sve-ptrace_Set_SVE_VL_1184 pass
9123 11:46:09.073007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
9124 11:46:09.073120 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
9125 11:46:09.076339 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
9126 11:46:09.076843 arm64_sve-ptrace_Set_SVE_VL_1200 pass
9127 11:46:09.077044 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
9128 11:46:09.077234 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
9129 11:46:09.077398 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
9130 11:46:09.077557 arm64_sve-ptrace_Set_SVE_VL_1216 pass
9131 11:46:09.077763 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
9132 11:46:09.077928 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
9133 11:46:09.078078 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
9134 11:46:09.078242 arm64_sve-ptrace_Set_SVE_VL_1232 pass
9135 11:46:09.078401 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
9136 11:46:09.078536 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
9137 11:46:09.078676 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
9138 11:46:09.078829 arm64_sve-ptrace_Set_SVE_VL_1248 pass
9139 11:46:09.079023 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
9140 11:46:09.079178 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
9141 11:46:09.079326 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
9142 11:46:09.079494 arm64_sve-ptrace_Set_SVE_VL_1264 pass
9143 11:46:09.079656 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
9144 11:46:09.079806 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
9145 11:46:09.079968 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
9146 11:46:09.080128 arm64_sve-ptrace_Set_SVE_VL_1280 pass
9147 11:46:09.080289 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
9148 11:46:09.080420 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
9149 11:46:09.080566 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
9150 11:46:09.080689 arm64_sve-ptrace_Set_SVE_VL_1296 pass
9151 11:46:09.080805 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
9152 11:46:09.080921 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
9153 11:46:09.081033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
9154 11:46:09.081146 arm64_sve-ptrace_Set_SVE_VL_1312 pass
9155 11:46:09.081261 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
9156 11:46:09.081374 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
9157 11:46:09.081488 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
9158 11:46:09.084298 arm64_sve-ptrace_Set_SVE_VL_1328 pass
9159 11:46:09.084718 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
9160 11:46:09.084921 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
9161 11:46:09.085125 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
9162 11:46:09.085352 arm64_sve-ptrace_Set_SVE_VL_1344 pass
9163 11:46:09.085577 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
9164 11:46:09.085810 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
9165 11:46:09.086031 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
9166 11:46:09.086254 arm64_sve-ptrace_Set_SVE_VL_1360 pass
9167 11:46:09.086461 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
9168 11:46:09.086727 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
9169 11:46:09.086917 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
9170 11:46:09.087088 arm64_sve-ptrace_Set_SVE_VL_1376 pass
9171 11:46:09.087276 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
9172 11:46:09.087468 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
9173 11:46:09.087686 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
9174 11:46:09.087900 arm64_sve-ptrace_Set_SVE_VL_1392 pass
9175 11:46:09.088090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
9176 11:46:09.088221 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
9177 11:46:09.088338 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
9178 11:46:09.088452 arm64_sve-ptrace_Set_SVE_VL_1408 pass
9179 11:46:09.088570 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
9180 11:46:09.088716 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9181 11:46:09.088839 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9182 11:46:09.088956 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9183 11:46:09.089069 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9184 11:46:09.089183 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9185 11:46:09.089297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9186 11:46:09.089410 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9187 11:46:09.089524 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9188 11:46:09.089639 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9189 11:46:09.089833 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9190 11:46:09.089958 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9191 11:46:09.092292 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9192 11:46:09.092745 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9193 11:46:09.092914 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9194 11:46:09.093045 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9195 11:46:09.093171 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9196 11:46:09.093325 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9197 11:46:09.093461 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9198 11:46:09.093591 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9199 11:46:09.093815 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9200 11:46:09.094024 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9201 11:46:09.094191 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9202 11:46:09.094345 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9203 11:46:09.094493 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9204 11:46:09.094649 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9205 11:46:09.094805 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9206 11:46:09.094988 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9207 11:46:09.095155 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9208 11:46:09.095313 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9209 11:46:09.095476 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9210 11:46:09.095636 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9211 11:46:09.095794 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9212 11:46:09.095954 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9213 11:46:09.096135 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9214 11:46:09.096260 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9215 11:46:09.096374 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9216 11:46:09.096488 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9217 11:46:09.096601 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9218 11:46:09.096715 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9219 11:46:09.096828 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9220 11:46:09.096941 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9221 11:46:09.097053 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9222 11:46:09.100335 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9223 11:46:09.100810 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9224 11:46:09.100993 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9225 11:46:09.101143 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9226 11:46:09.101300 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9227 11:46:09.101487 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9228 11:46:09.101659 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9229 11:46:09.101840 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9230 11:46:09.102053 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9231 11:46:09.102229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9232 11:46:09.102437 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9233 11:46:09.102684 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9234 11:46:09.102873 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9235 11:46:09.103022 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9236 11:46:09.103158 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9237 11:46:09.103302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9238 11:46:09.103438 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9239 11:46:09.103570 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9240 11:46:09.103733 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9241 11:46:09.103881 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9242 11:46:09.104058 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9243 11:46:09.104203 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9244 11:46:09.104358 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9245 11:46:09.104483 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9246 11:46:09.104602 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9247 11:46:09.104718 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9248 11:46:09.104833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9249 11:46:09.104948 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9250 11:46:09.105062 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9251 11:46:09.105175 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9252 11:46:09.105290 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9253 11:46:09.105403 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9254 11:46:09.105518 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9255 11:46:09.105635 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9256 11:46:09.105886 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9257 11:46:09.106083 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9258 11:46:09.106268 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9259 11:46:09.108373 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9260 11:46:09.108563 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9261 11:46:09.108999 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9262 11:46:09.109162 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9263 11:46:09.121822 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9264 11:46:09.122279 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9265 11:46:09.122466 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9266 11:46:09.122629 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9267 11:46:09.122787 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9268 11:46:09.122951 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9269 11:46:09.123144 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9270 11:46:09.123290 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9271 11:46:09.123441 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9272 11:46:09.123583 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9273 11:46:09.123731 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9274 11:46:09.123906 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9275 11:46:09.124053 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9276 11:46:09.124234 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9277 11:46:09.124372 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9278 11:46:09.124515 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9279 11:46:09.124657 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9280 11:46:09.124800 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9281 11:46:09.124944 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9282 11:46:09.125086 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9283 11:46:09.125265 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9284 11:46:09.125402 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9285 11:46:09.125544 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9286 11:46:09.125703 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9287 11:46:09.125847 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9288 11:46:09.125990 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9289 11:46:09.126131 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9290 11:46:09.126312 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9291 11:46:09.126446 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9292 11:46:09.126589 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9293 11:46:09.126731 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9294 11:46:09.126872 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9295 11:46:09.127012 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9296 11:46:09.127152 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9297 11:46:09.127293 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9298 11:46:09.127433 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9299 11:46:09.127575 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9300 11:46:09.127718 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9301 11:46:09.127889 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9302 11:46:09.128248 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9303 11:46:09.128385 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9304 11:46:09.128530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9305 11:46:09.128675 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9306 11:46:09.128819 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9307 11:46:09.128962 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9308 11:46:09.129104 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9309 11:46:09.129244 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9310 11:46:09.129384 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9311 11:46:09.129525 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9312 11:46:09.129683 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9313 11:46:09.129829 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9314 11:46:09.129972 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9315 11:46:09.130113 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9316 11:46:09.132380 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9317 11:46:09.132605 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9318 11:46:09.133053 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9319 11:46:09.133243 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9320 11:46:09.133445 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9321 11:46:09.133666 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9322 11:46:09.133931 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9323 11:46:09.134163 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9324 11:46:09.134389 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9325 11:46:09.134612 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9326 11:46:09.134824 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9327 11:46:09.135019 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9328 11:46:09.135202 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9329 11:46:09.135427 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9330 11:46:09.135651 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9331 11:46:09.135910 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9332 11:46:09.136117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9333 11:46:09.136290 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9334 11:46:09.136421 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9335 11:46:09.136538 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9336 11:46:09.136654 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9337 11:46:09.136771 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9338 11:46:09.136883 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9339 11:46:09.136996 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9340 11:46:09.137112 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9341 11:46:09.137226 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9342 11:46:09.137340 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9343 11:46:09.137453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9344 11:46:09.137596 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9345 11:46:09.137811 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9346 11:46:09.138009 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9347 11:46:09.140303 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9348 11:46:09.140833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9349 11:46:09.140946 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9350 11:46:09.141036 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9351 11:46:09.141122 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9352 11:46:09.141225 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9353 11:46:09.141312 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9354 11:46:09.141397 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9355 11:46:09.141495 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9356 11:46:09.141597 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9357 11:46:09.141942 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9358 11:46:09.142120 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9359 11:46:09.142330 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9360 11:46:09.142472 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9361 11:46:09.142648 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9362 11:46:09.142787 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9363 11:46:09.142928 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9364 11:46:09.143101 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9365 11:46:09.143238 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9366 11:46:09.143412 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9367 11:46:09.143548 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9368 11:46:09.143689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9369 11:46:09.143862 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9370 11:46:09.143999 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9371 11:46:09.144141 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9372 11:46:09.144313 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9373 11:46:09.148379 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9374 11:46:09.148879 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9375 11:46:09.149121 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9376 11:46:09.149352 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9377 11:46:09.149575 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9378 11:46:09.149845 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9379 11:46:09.150076 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9380 11:46:09.150289 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9381 11:46:09.150470 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9382 11:46:09.150640 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9383 11:46:09.150840 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9384 11:46:09.151008 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9385 11:46:09.151168 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9386 11:46:09.151327 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9387 11:46:09.151484 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9388 11:46:09.151639 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9389 11:46:09.151797 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9390 11:46:09.151951 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9391 11:46:09.152098 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9392 11:46:09.152230 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9393 11:46:09.152411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9394 11:46:09.152546 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9395 11:46:09.152667 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9396 11:46:09.152783 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9397 11:46:09.152898 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9398 11:46:09.153012 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9399 11:46:09.153126 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9400 11:46:09.153241 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9401 11:46:09.153353 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9402 11:46:09.160293 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9403 11:46:09.160682 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9404 11:46:09.160796 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9405 11:46:09.160895 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9406 11:46:09.161007 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9407 11:46:09.161097 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9408 11:46:09.161185 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9409 11:46:09.161291 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9410 11:46:09.161382 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9411 11:46:09.161486 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9412 11:46:09.161589 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9413 11:46:09.161961 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9414 11:46:09.162160 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9415 11:46:09.162295 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9416 11:46:09.162456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9417 11:46:09.162644 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9418 11:46:09.162793 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9419 11:46:09.162914 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9420 11:46:09.163059 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9421 11:46:09.163208 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9422 11:46:09.163371 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9423 11:46:09.175290 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9424 11:46:09.175498 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9425 11:46:09.175788 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9426 11:46:09.175880 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9427 11:46:09.175969 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9428 11:46:09.176054 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9429 11:46:09.176156 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9430 11:46:09.176243 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9431 11:46:09.176326 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9432 11:46:09.176427 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9433 11:46:09.176840 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9434 11:46:09.176948 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9435 11:46:09.177037 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9436 11:46:09.177140 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9437 11:46:09.177228 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9438 11:46:09.177324 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9439 11:46:09.177424 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9440 11:46:09.177510 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9441 11:46:09.177807 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9442 11:46:09.177911 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9443 11:46:09.178009 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9444 11:46:09.178093 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9445 11:46:09.178380 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9446 11:46:09.178484 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9447 11:46:09.178569 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9448 11:46:09.178667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9449 11:46:09.178758 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9450 11:46:09.178856 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9451 11:46:09.178942 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9452 11:46:09.179357 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9453 11:46:09.179463 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9454 11:46:09.179564 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9455 11:46:09.179651 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9456 11:46:09.179738 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9457 11:46:09.179839 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9458 11:46:09.179923 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9459 11:46:09.180005 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9460 11:46:09.180102 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9461 11:46:09.184417 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9462 11:46:09.184682 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9463 11:46:09.185078 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9464 11:46:09.185187 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9465 11:46:09.185279 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9466 11:46:09.185368 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9467 11:46:09.185458 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9468 11:46:09.185562 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9469 11:46:09.185658 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9470 11:46:09.185750 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9471 11:46:09.185836 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9472 11:46:09.185936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9473 11:46:09.186023 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9474 11:46:09.186123 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9475 11:46:09.186222 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9476 11:46:09.186538 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9477 11:46:09.186659 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9478 11:46:09.186763 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9479 11:46:09.186867 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9480 11:46:09.186988 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9481 11:46:09.187287 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9482 11:46:09.187390 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9483 11:46:09.187492 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9484 11:46:09.187595 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9485 11:46:09.187697 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9486 11:46:09.187802 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9487 11:46:09.187966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9488 11:46:09.192282 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9489 11:46:09.192617 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9490 11:46:09.192724 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9491 11:46:09.192816 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9492 11:46:09.192918 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9493 11:46:09.193005 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9494 11:46:09.193105 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9495 11:46:09.193393 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9496 11:46:09.193499 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9497 11:46:09.193600 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9498 11:46:09.193698 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9499 11:46:09.193804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9500 11:46:09.193907 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9501 11:46:09.194101 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9502 11:46:09.194222 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9503 11:46:09.194337 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9504 11:46:09.194637 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9505 11:46:09.194760 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9506 11:46:09.194848 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9507 11:46:09.194966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9508 11:46:09.195310 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9509 11:46:09.195511 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9510 11:46:09.195708 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9511 11:46:09.195884 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9512 11:46:09.196062 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9513 11:46:09.196194 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9514 11:46:09.196312 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9515 11:46:09.196428 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9516 11:46:09.200306 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9517 11:46:09.200642 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9518 11:46:09.200748 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9519 11:46:09.200847 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9520 11:46:09.200950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9521 11:46:09.201038 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9522 11:46:09.201123 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9523 11:46:09.201223 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9524 11:46:09.201308 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9525 11:46:09.201407 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9526 11:46:09.201509 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9527 11:46:09.201610 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9528 11:46:09.201722 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9529 11:46:09.201827 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9530 11:46:09.201930 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9531 11:46:09.202030 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9532 11:46:09.202130 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9533 11:46:09.202231 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9534 11:46:09.202331 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9535 11:46:09.202630 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9536 11:46:09.202788 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9537 11:46:09.202883 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9538 11:46:09.202981 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9539 11:46:09.203079 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9540 11:46:09.203180 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9541 11:46:09.203487 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9542 11:46:09.203590 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9543 11:46:09.203689 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9544 11:46:09.203984 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9545 11:46:09.204087 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9546 11:46:09.208302 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9547 11:46:09.208778 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9548 11:46:09.208974 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9549 11:46:09.209147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9550 11:46:09.209407 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9551 11:46:09.209612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9552 11:46:09.209805 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9553 11:46:09.209982 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9554 11:46:09.210185 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9555 11:46:09.210408 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9556 11:46:09.210599 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9557 11:46:09.210778 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9558 11:46:09.210943 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9559 11:46:09.211123 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9560 11:46:09.211341 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9561 11:46:09.211557 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9562 11:46:09.211772 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9563 11:46:09.212010 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9564 11:46:09.212165 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9565 11:46:09.212285 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9566 11:46:09.212399 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9567 11:46:09.212512 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9568 11:46:09.212623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9569 11:46:09.212734 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9570 11:46:09.212848 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9571 11:46:09.212958 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9572 11:46:09.213069 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9573 11:46:09.213180 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9574 11:46:09.213290 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9575 11:46:09.213401 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9576 11:46:09.216353 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9577 11:46:09.216758 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9578 11:46:09.216891 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9579 11:46:09.216994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9580 11:46:09.217100 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9581 11:46:09.217190 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9582 11:46:09.217276 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9583 11:46:09.229918 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9584 11:46:09.230353 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9585 11:46:09.230458 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9586 11:46:09.230546 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9587 11:46:09.230631 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9588 11:46:09.230716 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9589 11:46:09.230817 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9590 11:46:09.230904 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9591 11:46:09.230987 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9592 11:46:09.231086 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9593 11:46:09.231172 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9594 11:46:09.231274 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9595 11:46:09.231377 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9596 11:46:09.231693 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9597 11:46:09.231829 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9598 11:46:09.231931 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9599 11:46:09.232023 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9600 11:46:09.232408 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9601 11:46:09.232635 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9602 11:46:09.232795 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9603 11:46:09.232977 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9604 11:46:09.233146 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9605 11:46:09.233311 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9606 11:46:09.233509 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9607 11:46:09.233660 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9608 11:46:09.233857 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9609 11:46:09.234050 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9610 11:46:09.234229 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9611 11:46:09.234421 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9612 11:46:09.234565 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9613 11:46:09.234700 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9614 11:46:09.234925 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9615 11:46:09.235168 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9616 11:46:09.235364 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9617 11:46:09.235589 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9618 11:46:09.235771 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9619 11:46:09.235950 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9620 11:46:09.236109 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9621 11:46:09.236265 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9622 11:46:09.236421 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9623 11:46:09.236576 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9624 11:46:09.236733 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9625 11:46:09.236889 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9626 11:46:09.237046 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9627 11:46:09.237235 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9628 11:46:09.237396 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9629 11:46:09.237550 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9630 11:46:09.237721 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9631 11:46:09.237878 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9632 11:46:09.240315 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9633 11:46:09.240634 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9634 11:46:09.240834 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9635 11:46:09.241021 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9636 11:46:09.241183 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9637 11:46:09.241338 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9638 11:46:09.241493 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9639 11:46:09.241689 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9640 11:46:09.241853 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9641 11:46:09.242007 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9642 11:46:09.242160 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9643 11:46:09.242313 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9644 11:46:09.242498 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9645 11:46:09.242656 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9646 11:46:09.242813 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9647 11:46:09.242966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9648 11:46:09.243123 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9649 11:46:09.243278 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9650 11:46:09.243432 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9651 11:46:09.243618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9652 11:46:09.243778 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9653 11:46:09.243935 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9654 11:46:09.244091 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9655 11:46:09.244245 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9656 11:46:09.244398 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9657 11:46:09.244552 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9658 11:46:09.244706 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9659 11:46:09.244862 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9660 11:46:09.245050 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9661 11:46:09.245209 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9662 11:46:09.245364 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9663 11:46:09.245518 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9664 11:46:09.248309 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9665 11:46:09.248774 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9666 11:46:09.248976 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9667 11:46:09.249134 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9668 11:46:09.249289 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9669 11:46:09.249468 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9670 11:46:09.249618 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9671 11:46:09.249776 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9672 11:46:09.249920 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9673 11:46:09.250062 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9674 11:46:09.250230 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9675 11:46:09.250374 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9676 11:46:09.250515 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9677 11:46:09.250654 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9678 11:46:09.250793 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9679 11:46:09.250960 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9680 11:46:09.251109 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9681 11:46:09.251280 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9682 11:46:09.251454 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9683 11:46:09.251606 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9684 11:46:09.251738 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9685 11:46:09.251891 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9686 11:46:09.252098 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9687 11:46:09.252277 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9688 11:46:09.252450 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9689 11:46:09.252625 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9690 11:46:09.252806 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9691 11:46:09.252972 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9692 11:46:09.253121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9693 11:46:09.253242 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9694 11:46:09.253357 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9695 11:46:09.253471 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9696 11:46:09.256336 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9697 11:46:09.256783 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9698 11:46:09.256925 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9699 11:46:09.257021 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9700 11:46:09.257108 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9701 11:46:09.257211 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9702 11:46:09.257297 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9703 11:46:09.257382 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9704 11:46:09.257481 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9705 11:46:09.257584 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9706 11:46:09.257694 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9707 11:46:09.257992 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9708 11:46:09.258107 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9709 11:46:09.258210 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9710 11:46:09.258501 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9711 11:46:09.258594 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9712 11:46:09.258679 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9713 11:46:09.258778 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9714 11:46:09.258867 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9715 11:46:09.258971 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9716 11:46:09.259318 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9717 11:46:09.259508 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9718 11:46:09.259701 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9719 11:46:09.259871 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9720 11:46:09.260040 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9721 11:46:09.260172 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9722 11:46:09.260313 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9723 11:46:09.260433 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9724 11:46:09.260548 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9725 11:46:09.264466 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9726 11:46:09.264627 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9727 11:46:09.264721 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9728 11:46:09.264823 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9729 11:46:09.264912 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9730 11:46:09.265011 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9731 11:46:09.265111 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9732 11:46:09.265214 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9733 11:46:09.265317 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9734 11:46:09.265430 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9735 11:46:09.265695 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9736 11:46:09.265810 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9737 11:46:09.265904 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9738 11:46:09.266002 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9739 11:46:09.266102 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9740 11:46:09.266384 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9741 11:46:09.266499 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9742 11:46:09.266599 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9743 11:46:09.283630 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9744 11:46:09.283939 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9745 11:46:09.284402 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9746 11:46:09.284595 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9747 11:46:09.284798 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9748 11:46:09.284986 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9749 11:46:09.285157 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9750 11:46:09.285366 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9751 11:46:09.285546 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9752 11:46:09.285727 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9753 11:46:09.285899 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9754 11:46:09.286067 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9755 11:46:09.286228 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9756 11:46:09.286414 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9757 11:46:09.286708 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9758 11:46:09.286928 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9759 11:46:09.287153 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9760 11:46:09.287365 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9761 11:46:09.287582 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9762 11:46:09.287751 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9763 11:46:09.287965 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9764 11:46:09.288158 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9765 11:46:09.288296 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9766 11:46:09.288446 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9767 11:46:09.288610 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9768 11:46:09.288735 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9769 11:46:09.288852 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9770 11:46:09.288970 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9771 11:46:09.289090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9772 11:46:09.289205 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9773 11:46:09.289321 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9774 11:46:09.289436 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9775 11:46:09.289549 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9776 11:46:09.289677 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9777 11:46:09.292303 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9778 11:46:09.292767 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9779 11:46:09.292975 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9780 11:46:09.293154 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9781 11:46:09.293365 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9782 11:46:09.293639 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9783 11:46:09.293854 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9784 11:46:09.294048 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9785 11:46:09.294242 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9786 11:46:09.294404 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9787 11:46:09.294563 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9788 11:46:09.294811 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9789 11:46:09.295021 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9790 11:46:09.295228 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9791 11:46:09.295420 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9792 11:46:09.295582 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9793 11:46:09.295775 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9794 11:46:09.295961 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9795 11:46:09.296154 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9796 11:46:09.296330 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9797 11:46:09.296455 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9798 11:46:09.296573 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9799 11:46:09.296687 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9800 11:46:09.296802 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9801 11:46:09.296916 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9802 11:46:09.297033 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9803 11:46:09.297147 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9804 11:46:09.297261 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9805 11:46:09.300336 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9806 11:46:09.300823 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9807 11:46:09.301008 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9808 11:46:09.301169 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9809 11:46:09.301335 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9810 11:46:09.301537 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9811 11:46:09.301712 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9812 11:46:09.301873 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9813 11:46:09.302033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9814 11:46:09.302189 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9815 11:46:09.302350 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9816 11:46:09.302538 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9817 11:46:09.302698 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9818 11:46:09.302864 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9819 11:46:09.303007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9820 11:46:09.303171 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9821 11:46:09.303335 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9822 11:46:09.303495 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9823 11:46:09.303686 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9824 11:46:09.303840 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9825 11:46:09.304003 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9826 11:46:09.304157 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9827 11:46:09.304278 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9828 11:46:09.304393 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9829 11:46:09.304508 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9830 11:46:09.304624 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9831 11:46:09.304737 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9832 11:46:09.304879 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9833 11:46:09.305002 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9834 11:46:09.305117 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9835 11:46:09.305256 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9836 11:46:09.305396 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9837 11:46:09.308400 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9838 11:46:09.308812 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9839 11:46:09.308924 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9840 11:46:09.309098 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9841 11:46:09.309269 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9842 11:46:09.309511 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9843 11:46:09.309740 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9844 11:46:09.309944 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9845 11:46:09.310117 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9846 11:46:09.310286 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9847 11:46:09.310498 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9848 11:46:09.310719 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9849 11:46:09.310931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9850 11:46:09.311148 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9851 11:46:09.311387 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9852 11:46:09.311655 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9853 11:46:09.311861 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9854 11:46:09.312077 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9855 11:46:09.312238 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9856 11:46:09.312360 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9857 11:46:09.312475 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9858 11:46:09.312590 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9859 11:46:09.312703 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9860 11:46:09.312843 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9861 11:46:09.312964 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9862 11:46:09.313082 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9863 11:46:09.316458 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9864 11:46:09.316967 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9865 11:46:09.317162 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9866 11:46:09.317332 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9867 11:46:09.317485 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9868 11:46:09.317692 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9869 11:46:09.317859 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9870 11:46:09.318018 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9871 11:46:09.318176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9872 11:46:09.318338 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9873 11:46:09.318523 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9874 11:46:09.318751 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9875 11:46:09.318935 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9876 11:46:09.319127 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9877 11:46:09.319293 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9878 11:46:09.319477 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9879 11:46:09.319745 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9880 11:46:09.319954 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9881 11:46:09.320156 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9882 11:46:09.320302 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9883 11:46:09.320421 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9884 11:46:09.320535 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9885 11:46:09.320648 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9886 11:46:09.320766 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9887 11:46:09.320906 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9888 11:46:09.321030 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9889 11:46:09.324437 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9890 11:46:09.324654 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9891 11:46:09.325102 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9892 11:46:09.325303 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9893 11:46:09.325533 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9894 11:46:09.325775 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9895 11:46:09.326043 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9896 11:46:09.326258 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9897 11:46:09.326418 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9898 11:46:09.326539 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9899 11:46:09.326654 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9900 11:46:09.326794 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9901 11:46:09.326972 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9902 11:46:09.327119 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9903 11:46:09.348767 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9904 11:46:09.349239 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9905 11:46:09.349396 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9906 11:46:09.349543 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9907 11:46:09.349685 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9908 11:46:09.349842 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9909 11:46:09.349982 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9910 11:46:09.350108 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9911 11:46:09.350260 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9912 11:46:09.350394 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9913 11:46:09.350498 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9914 11:46:09.350604 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9915 11:46:09.350693 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9916 11:46:09.351007 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9917 11:46:09.351118 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9918 11:46:09.351205 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9919 11:46:09.351306 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9920 11:46:09.351412 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9921 11:46:09.351513 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9922 11:46:09.351814 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9923 11:46:09.351915 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9924 11:46:09.352017 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9925 11:46:09.356328 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9926 11:46:09.356739 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9927 11:46:09.356843 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9928 11:46:09.356932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9929 11:46:09.357033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9930 11:46:09.357121 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9931 11:46:09.357220 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9932 11:46:09.357321 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9933 11:46:09.357624 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9934 11:46:09.357768 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9935 11:46:09.357889 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
9936 11:46:09.357977 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
9937 11:46:09.358077 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
9938 11:46:09.358179 arm64_sve-ptrace_Set_SVE_VL_4448 pass
9939 11:46:09.358541 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
9940 11:46:09.358697 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
9941 11:46:09.358841 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
9942 11:46:09.358962 arm64_sve-ptrace_Set_SVE_VL_4464 pass
9943 11:46:09.359100 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
9944 11:46:09.359239 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
9945 11:46:09.359357 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
9946 11:46:09.359492 arm64_sve-ptrace_Set_SVE_VL_4480 pass
9947 11:46:09.359629 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
9948 11:46:09.359748 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
9949 11:46:09.359882 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
9950 11:46:09.360019 arm64_sve-ptrace_Set_SVE_VL_4496 pass
9951 11:46:09.360239 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
9952 11:46:09.364312 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
9953 11:46:09.364673 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
9954 11:46:09.364783 arm64_sve-ptrace_Set_SVE_VL_4512 pass
9955 11:46:09.364870 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
9956 11:46:09.364969 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
9957 11:46:09.365058 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
9958 11:46:09.365156 arm64_sve-ptrace_Set_SVE_VL_4528 pass
9959 11:46:09.365256 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
9960 11:46:09.365559 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
9961 11:46:09.365670 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
9962 11:46:09.365770 arm64_sve-ptrace_Set_SVE_VL_4544 pass
9963 11:46:09.365870 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
9964 11:46:09.366210 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
9965 11:46:09.366404 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
9966 11:46:09.366567 arm64_sve-ptrace_Set_SVE_VL_4560 pass
9967 11:46:09.366762 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
9968 11:46:09.366959 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
9969 11:46:09.367128 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
9970 11:46:09.367278 arm64_sve-ptrace_Set_SVE_VL_4576 pass
9971 11:46:09.367442 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
9972 11:46:09.367597 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
9973 11:46:09.367756 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
9974 11:46:09.367905 arm64_sve-ptrace_Set_SVE_VL_4592 pass
9975 11:46:09.368040 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
9976 11:46:09.368163 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
9977 11:46:09.368307 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
9978 11:46:09.368429 arm64_sve-ptrace_Set_SVE_VL_4608 pass
9979 11:46:09.368544 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
9980 11:46:09.368661 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
9981 11:46:09.368776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
9982 11:46:09.372980 arm64_sve-ptrace_Set_SVE_VL_4624 pass
9983 11:46:09.373224 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
9984 11:46:09.373440 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
9985 11:46:09.373624 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
9986 11:46:09.373805 arm64_sve-ptrace_Set_SVE_VL_4640 pass
9987 11:46:09.373974 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
9988 11:46:09.374432 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
9989 11:46:09.374635 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
9990 11:46:09.374809 arm64_sve-ptrace_Set_SVE_VL_4656 pass
9991 11:46:09.374975 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
9992 11:46:09.375146 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
9993 11:46:09.375313 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
9994 11:46:09.375479 arm64_sve-ptrace_Set_SVE_VL_4672 pass
9995 11:46:09.375645 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
9996 11:46:09.375814 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
9997 11:46:09.375981 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
9998 11:46:09.376169 arm64_sve-ptrace_Set_SVE_VL_4688 pass
9999 11:46:09.376296 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
10000 11:46:09.376414 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
10001 11:46:09.376531 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
10002 11:46:09.376648 arm64_sve-ptrace_Set_SVE_VL_4704 pass
10003 11:46:09.376763 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
10004 11:46:09.376879 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
10005 11:46:09.376996 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
10006 11:46:09.377113 arm64_sve-ptrace_Set_SVE_VL_4720 pass
10007 11:46:09.377229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
10008 11:46:09.377344 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
10009 11:46:09.377460 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
10010 11:46:09.380282 arm64_sve-ptrace_Set_SVE_VL_4736 pass
10011 11:46:09.380717 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
10012 11:46:09.380826 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
10013 11:46:09.380923 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
10014 11:46:09.381031 arm64_sve-ptrace_Set_SVE_VL_4752 pass
10015 11:46:09.381123 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
10016 11:46:09.381226 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
10017 11:46:09.381311 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
10018 11:46:09.381410 arm64_sve-ptrace_Set_SVE_VL_4768 pass
10019 11:46:09.381509 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
10020 11:46:09.381607 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
10021 11:46:09.381924 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
10022 11:46:09.382041 arm64_sve-ptrace_Set_SVE_VL_4784 pass
10023 11:46:09.382149 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
10024 11:46:09.382250 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
10025 11:46:09.382576 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
10026 11:46:09.382696 arm64_sve-ptrace_Set_SVE_VL_4800 pass
10027 11:46:09.382797 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
10028 11:46:09.383115 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
10029 11:46:09.383235 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
10030 11:46:09.383341 arm64_sve-ptrace_Set_SVE_VL_4816 pass
10031 11:46:09.383427 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
10032 11:46:09.383527 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
10033 11:46:09.383820 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
10034 11:46:09.383925 arm64_sve-ptrace_Set_SVE_VL_4832 pass
10035 11:46:09.384011 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
10036 11:46:09.384119 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
10037 11:46:09.388491 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
10038 11:46:09.388635 arm64_sve-ptrace_Set_SVE_VL_4848 pass
10039 11:46:09.388738 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
10040 11:46:09.388828 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
10041 11:46:09.388928 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
10042 11:46:09.389027 arm64_sve-ptrace_Set_SVE_VL_4864 pass
10043 11:46:09.389313 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
10044 11:46:09.389404 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
10045 11:46:09.389506 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
10046 11:46:09.389605 arm64_sve-ptrace_Set_SVE_VL_4880 pass
10047 11:46:09.389715 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
10048 11:46:09.390000 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
10049 11:46:09.390092 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
10050 11:46:09.390192 arm64_sve-ptrace_Set_SVE_VL_4896 pass
10051 11:46:09.390291 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
10052 11:46:09.390394 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
10053 11:46:09.390711 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
10054 11:46:09.390815 arm64_sve-ptrace_Set_SVE_VL_4912 pass
10055 11:46:09.390916 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
10056 11:46:09.391021 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
10057 11:46:09.391123 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
10058 11:46:09.391422 arm64_sve-ptrace_Set_SVE_VL_4928 pass
10059 11:46:09.391527 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
10060 11:46:09.391629 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
10061 11:46:09.391731 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
10062 11:46:09.391832 arm64_sve-ptrace_Set_SVE_VL_4944 pass
10063 11:46:09.406888 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
10064 11:46:09.407428 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
10065 11:46:09.407619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
10066 11:46:09.407798 arm64_sve-ptrace_Set_SVE_VL_4960 pass
10067 11:46:09.407961 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
10068 11:46:09.408132 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
10069 11:46:09.408261 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
10070 11:46:09.408392 arm64_sve-ptrace_Set_SVE_VL_4976 pass
10071 11:46:09.408521 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
10072 11:46:09.408647 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
10073 11:46:09.408790 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
10074 11:46:09.408966 arm64_sve-ptrace_Set_SVE_VL_4992 pass
10075 11:46:09.409092 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
10076 11:46:09.409210 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
10077 11:46:09.409336 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
10078 11:46:09.409463 arm64_sve-ptrace_Set_SVE_VL_5008 pass
10079 11:46:09.409588 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
10080 11:46:09.409761 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
10081 11:46:09.409895 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
10082 11:46:09.410042 arm64_sve-ptrace_Set_SVE_VL_5024 pass
10083 11:46:09.410175 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
10084 11:46:09.410314 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
10085 11:46:09.410506 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
10086 11:46:09.410667 arm64_sve-ptrace_Set_SVE_VL_5040 pass
10087 11:46:09.410846 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
10088 11:46:09.411000 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
10089 11:46:09.411158 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
10090 11:46:09.411319 arm64_sve-ptrace_Set_SVE_VL_5056 pass
10091 11:46:09.411471 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
10092 11:46:09.411614 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
10093 11:46:09.411774 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
10094 11:46:09.411933 arm64_sve-ptrace_Set_SVE_VL_5072 pass
10095 11:46:09.412076 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
10096 11:46:09.412215 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
10097 11:46:09.412361 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
10098 11:46:09.412486 arm64_sve-ptrace_Set_SVE_VL_5088 pass
10099 11:46:09.412603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
10100 11:46:09.412721 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
10101 11:46:09.413052 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
10102 11:46:09.413180 arm64_sve-ptrace_Set_SVE_VL_5104 pass
10103 11:46:09.413298 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
10104 11:46:09.413415 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
10105 11:46:09.413533 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
10106 11:46:09.413667 arm64_sve-ptrace_Set_SVE_VL_5120 pass
10107 11:46:09.413788 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
10108 11:46:09.416307 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
10109 11:46:09.416642 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
10110 11:46:09.416751 arm64_sve-ptrace_Set_SVE_VL_5136 pass
10111 11:46:09.416844 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
10112 11:46:09.416947 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
10113 11:46:09.417130 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
10114 11:46:09.417246 arm64_sve-ptrace_Set_SVE_VL_5152 pass
10115 11:46:09.417333 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
10116 11:46:09.417432 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
10117 11:46:09.417517 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
10118 11:46:09.417613 arm64_sve-ptrace_Set_SVE_VL_5168 pass
10119 11:46:09.417720 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
10120 11:46:09.417820 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
10121 11:46:09.418117 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
10122 11:46:09.418227 arm64_sve-ptrace_Set_SVE_VL_5184 pass
10123 11:46:09.418327 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
10124 11:46:09.418428 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
10125 11:46:09.418528 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
10126 11:46:09.418627 arm64_sve-ptrace_Set_SVE_VL_5200 pass
10127 11:46:09.418920 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
10128 11:46:09.419027 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
10129 11:46:09.419127 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
10130 11:46:09.419217 arm64_sve-ptrace_Set_SVE_VL_5216 pass
10131 11:46:09.419313 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
10132 11:46:09.419409 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
10133 11:46:09.419508 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
10134 11:46:09.419607 arm64_sve-ptrace_Set_SVE_VL_5232 pass
10135 11:46:09.419714 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
10136 11:46:09.420025 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
10137 11:46:09.420128 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
10138 11:46:09.424296 arm64_sve-ptrace_Set_SVE_VL_5248 pass
10139 11:46:09.424650 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
10140 11:46:09.424753 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
10141 11:46:09.424855 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
10142 11:46:09.424943 arm64_sve-ptrace_Set_SVE_VL_5264 pass
10143 11:46:09.425040 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
10144 11:46:09.425140 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
10145 11:46:09.425241 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
10146 11:46:09.425340 arm64_sve-ptrace_Set_SVE_VL_5280 pass
10147 11:46:09.425639 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
10148 11:46:09.425749 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
10149 11:46:09.425853 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
10150 11:46:09.425959 arm64_sve-ptrace_Set_SVE_VL_5296 pass
10151 11:46:09.426074 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
10152 11:46:09.426390 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
10153 11:46:09.426494 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
10154 11:46:09.426598 arm64_sve-ptrace_Set_SVE_VL_5312 pass
10155 11:46:09.426687 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
10156 11:46:09.426785 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
10157 11:46:09.426883 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
10158 11:46:09.426981 arm64_sve-ptrace_Set_SVE_VL_5328 pass
10159 11:46:09.427080 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
10160 11:46:09.427348 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
10161 11:46:09.427471 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
10162 11:46:09.427746 arm64_sve-ptrace_Set_SVE_VL_5344 pass
10163 11:46:09.427851 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
10164 11:46:09.427958 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
10165 11:46:09.428062 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
10166 11:46:09.432339 arm64_sve-ptrace_Set_SVE_VL_5360 pass
10167 11:46:09.432745 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
10168 11:46:09.432855 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
10169 11:46:09.432944 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
10170 11:46:09.433045 arm64_sve-ptrace_Set_SVE_VL_5376 pass
10171 11:46:09.433134 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
10172 11:46:09.433236 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
10173 11:46:09.433338 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
10174 11:46:09.433448 arm64_sve-ptrace_Set_SVE_VL_5392 pass
10175 11:46:09.433776 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
10176 11:46:09.433895 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
10177 11:46:09.434000 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
10178 11:46:09.434101 arm64_sve-ptrace_Set_SVE_VL_5408 pass
10179 11:46:09.434409 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
10180 11:46:09.434530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10181 11:46:09.434640 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10182 11:46:09.434751 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10183 11:46:09.435047 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10184 11:46:09.435166 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10185 11:46:09.435267 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10186 11:46:09.435365 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10187 11:46:09.435662 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10188 11:46:09.435763 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10189 11:46:09.435861 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10190 11:46:09.435990 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10191 11:46:09.440284 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10192 11:46:09.440653 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10193 11:46:09.440803 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10194 11:46:09.440924 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10195 11:46:09.441055 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10196 11:46:09.441180 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10197 11:46:09.441291 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10198 11:46:09.441400 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10199 11:46:09.441493 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10200 11:46:09.441592 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10201 11:46:09.441699 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10202 11:46:09.441809 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10203 11:46:09.441913 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10204 11:46:09.442037 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10205 11:46:09.442139 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10206 11:46:09.442245 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10207 11:46:09.442317 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10208 11:46:09.442596 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10209 11:46:09.442721 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10210 11:46:09.442814 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10211 11:46:09.442914 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10212 11:46:09.443019 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10213 11:46:09.443320 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10214 11:46:09.443429 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10215 11:46:09.443530 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10216 11:46:09.443615 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10217 11:46:09.443711 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10218 11:46:09.443809 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10219 11:46:09.443907 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10220 11:46:09.448283 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10221 11:46:09.448613 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10222 11:46:09.448713 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10223 11:46:09.462269 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10224 11:46:09.462706 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10225 11:46:09.462808 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10226 11:46:09.462904 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10227 11:46:09.462995 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10228 11:46:09.463105 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10229 11:46:09.463200 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10230 11:46:09.463292 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10231 11:46:09.463395 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10232 11:46:09.463483 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10233 11:46:09.463568 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10234 11:46:09.463668 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10235 11:46:09.463753 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10236 11:46:09.463840 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10237 11:46:09.463945 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10238 11:46:09.464034 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10239 11:46:09.464130 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10240 11:46:09.464420 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10241 11:46:09.464547 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10242 11:46:09.464638 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10243 11:46:09.464733 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10244 11:46:09.464830 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10245 11:46:09.465140 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10246 11:46:09.465260 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10247 11:46:09.465366 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10248 11:46:09.465466 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10249 11:46:09.465756 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10250 11:46:09.465849 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10251 11:46:09.465949 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10252 11:46:09.466051 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10253 11:46:09.466154 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10254 11:46:09.466259 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10255 11:46:09.466368 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10256 11:46:09.466684 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10257 11:46:09.466888 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10258 11:46:09.467097 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10259 11:46:09.467265 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10260 11:46:09.467421 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10261 11:46:09.467610 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10262 11:46:09.467788 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10263 11:46:09.467956 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10264 11:46:09.468128 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10265 11:46:09.468266 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10266 11:46:09.468469 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10267 11:46:09.468651 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10268 11:46:09.468830 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10269 11:46:09.468979 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10270 11:46:09.469111 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10271 11:46:09.472313 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10272 11:46:09.472709 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10273 11:46:09.472854 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10274 11:46:09.472981 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10275 11:46:09.473131 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10276 11:46:09.473260 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10277 11:46:09.473388 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10278 11:46:09.473512 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10279 11:46:09.473677 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10280 11:46:09.473816 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10281 11:46:09.473946 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10282 11:46:09.474065 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10283 11:46:09.474208 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10284 11:46:09.474341 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10285 11:46:09.474466 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10286 11:46:09.474589 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10287 11:46:09.474715 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10288 11:46:09.474867 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10289 11:46:09.475000 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10290 11:46:09.475126 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10291 11:46:09.475251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10292 11:46:09.475378 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10293 11:46:09.475501 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10294 11:46:09.475652 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10295 11:46:09.475785 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10296 11:46:09.475911 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10297 11:46:09.476035 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10298 11:46:09.476158 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10299 11:46:09.476277 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10300 11:46:09.476418 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10301 11:46:09.476539 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10302 11:46:09.476656 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10303 11:46:09.476773 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10304 11:46:09.476890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10305 11:46:09.480492 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10306 11:46:09.480703 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10307 11:46:09.480874 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10308 11:46:09.481064 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10309 11:46:09.481242 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10310 11:46:09.481438 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10311 11:46:09.481609 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10312 11:46:09.481779 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10313 11:46:09.481941 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10314 11:46:09.482105 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10315 11:46:09.482295 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10316 11:46:09.482464 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10317 11:46:09.482631 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10318 11:46:09.482791 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10319 11:46:09.482955 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10320 11:46:09.483118 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10321 11:46:09.483269 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10322 11:46:09.483406 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10323 11:46:09.483587 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10324 11:46:09.483740 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10325 11:46:09.483871 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10326 11:46:09.484004 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10327 11:46:09.484133 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10328 11:46:09.484251 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10329 11:46:09.484364 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10330 11:46:09.484479 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10331 11:46:09.484592 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10332 11:46:09.484704 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10333 11:46:09.484847 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10334 11:46:09.484967 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10335 11:46:09.485081 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10336 11:46:09.485195 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10337 11:46:09.485310 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10338 11:46:09.488307 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10339 11:46:09.488632 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10340 11:46:09.488727 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10341 11:46:09.488815 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10342 11:46:09.488915 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10343 11:46:09.489018 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10344 11:46:09.489119 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10345 11:46:09.489219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10346 11:46:09.489325 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10347 11:46:09.489693 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10348 11:46:09.489854 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10349 11:46:09.490033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10350 11:46:09.490172 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10351 11:46:09.490315 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10352 11:46:09.490491 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10353 11:46:09.490648 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10354 11:46:09.490823 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10355 11:46:09.490967 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10356 11:46:09.491109 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10357 11:46:09.491252 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10358 11:46:09.491432 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10359 11:46:09.491570 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10360 11:46:09.491713 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10361 11:46:09.491857 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10362 11:46:09.491999 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10363 11:46:09.492140 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10364 11:46:09.492282 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10365 11:46:09.492428 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10366 11:46:09.492570 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10367 11:46:09.492711 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10368 11:46:09.492890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10369 11:46:09.493026 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10370 11:46:09.493168 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10371 11:46:09.493309 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10372 11:46:09.493454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10373 11:46:09.493596 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10374 11:46:09.493749 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10375 11:46:09.496349 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10376 11:46:09.496662 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10377 11:46:09.496762 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10378 11:46:09.496852 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10379 11:46:09.496942 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10380 11:46:09.497045 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10381 11:46:09.497132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10382 11:46:09.497217 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10383 11:46:09.513847 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10384 11:46:09.514078 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10385 11:46:09.514398 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10386 11:46:09.514529 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10387 11:46:09.514628 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10388 11:46:09.514712 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10389 11:46:09.514813 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10390 11:46:09.514898 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10391 11:46:09.514980 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10392 11:46:09.515064 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10393 11:46:09.515162 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10394 11:46:09.515248 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10395 11:46:09.515332 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10396 11:46:09.515432 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10397 11:46:09.515519 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10398 11:46:09.515620 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10399 11:46:09.515706 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10400 11:46:09.515805 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10401 11:46:09.515889 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10402 11:46:09.515988 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10403 11:46:09.516102 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10404 11:46:09.516562 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10405 11:46:09.516668 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10406 11:46:09.516755 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10407 11:46:09.516855 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10408 11:46:09.516942 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10409 11:46:09.517043 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10410 11:46:09.517132 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10411 11:46:09.517232 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10412 11:46:09.517339 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10413 11:46:09.517439 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10414 11:46:09.517587 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10415 11:46:09.517833 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10416 11:46:09.518009 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10417 11:46:09.518204 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10418 11:46:09.518375 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10419 11:46:09.518568 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10420 11:46:09.518730 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10421 11:46:09.518891 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10422 11:46:09.519073 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10423 11:46:09.519221 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10424 11:46:09.519382 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10425 11:46:09.519512 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10426 11:46:09.519653 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10427 11:46:09.519838 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10428 11:46:09.520001 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10429 11:46:09.520142 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10430 11:46:09.520261 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10431 11:46:09.520379 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10432 11:46:09.520518 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10433 11:46:09.520639 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10434 11:46:09.520755 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10435 11:46:09.524325 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10436 11:46:09.524891 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10437 11:46:09.525047 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10438 11:46:09.525195 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10439 11:46:09.525338 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10440 11:46:09.525482 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10441 11:46:09.525670 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10442 11:46:09.525809 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10443 11:46:09.525952 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10444 11:46:09.526095 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10445 11:46:09.526238 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10446 11:46:09.526418 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10447 11:46:09.526587 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10448 11:46:09.526785 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10449 11:46:09.526920 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10450 11:46:09.527046 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10451 11:46:09.527171 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10452 11:46:09.527295 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10453 11:46:09.527426 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10454 11:46:09.527550 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10455 11:46:09.527677 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10456 11:46:09.527834 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10457 11:46:09.528028 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10458 11:46:09.528184 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10459 11:46:09.528306 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10460 11:46:09.528425 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10461 11:46:09.528541 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10462 11:46:09.528657 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10463 11:46:09.528773 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10464 11:46:09.528897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10465 11:46:09.529087 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10466 11:46:09.529278 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10467 11:46:09.536346 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10468 11:46:09.536808 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10469 11:46:09.536974 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10470 11:46:09.537135 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10471 11:46:09.537298 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10472 11:46:09.537454 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10473 11:46:09.537661 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10474 11:46:09.537815 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10475 11:46:09.537946 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10476 11:46:09.538077 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10477 11:46:09.538204 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10478 11:46:09.538333 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10479 11:46:09.538465 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10480 11:46:09.538607 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10481 11:46:09.538798 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10482 11:46:09.538956 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10483 11:46:09.539102 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10484 11:46:09.539252 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10485 11:46:09.539408 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10486 11:46:09.539557 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10487 11:46:09.539695 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10488 11:46:09.539824 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10489 11:46:09.539947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10490 11:46:09.540101 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10491 11:46:09.540229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10492 11:46:09.540347 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10493 11:46:09.540466 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10494 11:46:09.540582 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10495 11:46:09.540698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10496 11:46:09.540814 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10497 11:46:09.540928 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10498 11:46:09.541043 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10499 11:46:09.541158 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10500 11:46:09.541295 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10501 11:46:09.544443 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10502 11:46:09.544581 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10503 11:46:09.544686 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10504 11:46:09.544788 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10505 11:46:09.544890 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10506 11:46:09.545001 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10507 11:46:09.545103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10508 11:46:09.545200 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10509 11:46:09.545519 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10510 11:46:09.545643 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10511 11:46:09.545762 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10512 11:46:09.545850 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10513 11:46:09.545947 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10514 11:46:09.546047 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10515 11:46:09.546146 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10516 11:46:09.546448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10517 11:46:09.546636 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10518 11:46:09.546733 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10519 11:46:09.546832 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10520 11:46:09.546930 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10521 11:46:09.547028 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10522 11:46:09.547249 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10523 11:46:09.547366 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10524 11:46:09.547647 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10525 11:46:09.547804 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10526 11:46:09.547905 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10527 11:46:09.548009 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10528 11:46:09.552319 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10529 11:46:09.552748 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10530 11:46:09.552937 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10531 11:46:09.553156 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10532 11:46:09.553412 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10533 11:46:09.553604 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10534 11:46:09.553790 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10535 11:46:09.553953 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10536 11:46:09.554153 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10537 11:46:09.554310 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10538 11:46:09.554443 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10539 11:46:09.554560 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10540 11:46:09.554675 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10541 11:46:09.554812 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10542 11:46:09.554954 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10543 11:46:09.576565 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10544 11:46:09.577193 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10545 11:46:09.577392 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10546 11:46:09.577554 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10547 11:46:09.577723 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10548 11:46:09.577877 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10549 11:46:09.578068 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10550 11:46:09.578241 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10551 11:46:09.578408 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10552 11:46:09.578564 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10553 11:46:09.578723 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10554 11:46:09.578880 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10555 11:46:09.579040 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10556 11:46:09.579221 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10557 11:46:09.579387 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10558 11:46:09.579546 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10559 11:46:09.579698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10560 11:46:09.579858 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10561 11:46:09.579994 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10562 11:46:09.580132 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10563 11:46:09.580278 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10564 11:46:09.580398 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10565 11:46:09.580519 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10566 11:46:09.580634 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10567 11:46:09.580750 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10568 11:46:09.580866 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10569 11:46:09.584472 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10570 11:46:09.584796 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10571 11:46:09.585192 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10572 11:46:09.585302 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10573 11:46:09.585391 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10574 11:46:09.585475 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10575 11:46:09.585555 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10576 11:46:09.585666 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10577 11:46:09.585760 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10578 11:46:09.586042 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10579 11:46:09.586145 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10580 11:46:09.586233 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10581 11:46:09.586319 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10582 11:46:09.586686 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10583 11:46:09.586906 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10584 11:46:09.587120 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10585 11:46:09.587332 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10586 11:46:09.587776 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10587 11:46:09.587984 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10588 11:46:09.588205 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10589 11:46:09.588362 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10590 11:46:09.588486 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10591 11:46:09.588603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10592 11:46:09.588719 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10593 11:46:09.588837 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10594 11:46:09.588981 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10595 11:46:09.589107 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10596 11:46:09.592305 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10597 11:46:09.592714 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10598 11:46:09.592820 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10599 11:46:09.592909 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10600 11:46:09.593013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10601 11:46:09.593099 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10602 11:46:09.593186 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10603 11:46:09.593289 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10604 11:46:09.593377 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10605 11:46:09.593477 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10606 11:46:09.593581 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10607 11:46:09.593691 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10608 11:46:09.593794 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10609 11:46:09.593900 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10610 11:46:09.594005 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10611 11:46:09.594104 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10612 11:46:09.594206 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10613 11:46:09.594311 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10614 11:46:09.594398 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10615 11:46:09.594500 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10616 11:46:09.594602 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10617 11:46:09.601767 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10618 11:46:09.601900 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10619 11:46:09.601991 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10620 11:46:09.602079 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10621 11:46:09.602166 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10622 11:46:09.602250 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10623 11:46:09.602337 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10624 11:46:09.602422 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10625 11:46:09.602505 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10626 11:46:09.602591 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10627 11:46:09.602671 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10628 11:46:09.602751 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10629 11:46:09.602837 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10630 11:46:09.602922 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10631 11:46:09.603007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10632 11:46:09.603090 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10633 11:46:09.603173 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10634 11:46:09.603253 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10635 11:46:09.603337 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10636 11:46:09.603424 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10637 11:46:09.603515 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10638 11:46:09.603601 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10639 11:46:09.603687 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10640 11:46:09.603775 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10641 11:46:09.603861 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10642 11:46:09.603948 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10643 11:46:09.604030 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10644 11:46:09.604115 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10645 11:46:09.604201 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10646 11:46:09.604286 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10647 11:46:09.604374 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10648 11:46:09.604461 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10649 11:46:09.604549 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10650 11:46:09.604634 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10651 11:46:09.604722 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10652 11:46:09.604808 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10653 11:46:09.604891 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10654 11:46:09.604970 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10655 11:46:09.605289 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10656 11:46:09.605449 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10657 11:46:09.605575 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10658 11:46:09.605718 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10659 11:46:09.605834 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10660 11:46:09.605949 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10661 11:46:09.606063 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10662 11:46:09.606177 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10663 11:46:09.606289 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10664 11:46:09.606404 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10665 11:46:09.606520 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10666 11:46:09.606634 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10667 11:46:09.606748 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10668 11:46:09.606860 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10669 11:46:09.606973 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10670 11:46:09.607087 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10671 11:46:09.607200 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10672 11:46:09.607313 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10673 11:46:09.607429 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10674 11:46:09.607555 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10675 11:46:09.607679 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10676 11:46:09.607841 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10677 11:46:09.608001 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10678 11:46:09.612310 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10679 11:46:09.612723 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10680 11:46:09.612833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10681 11:46:09.612926 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10682 11:46:09.613013 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10683 11:46:09.613116 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10684 11:46:09.613205 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10685 11:46:09.613292 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10686 11:46:09.613395 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10687 11:46:09.613694 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10688 11:46:09.613794 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10689 11:46:09.613898 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10690 11:46:09.614001 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10691 11:46:09.614101 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10692 11:46:09.614395 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10693 11:46:09.614507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10694 11:46:09.614599 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10695 11:46:09.614889 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10696 11:46:09.614983 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10697 11:46:09.615284 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10698 11:46:09.615388 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10699 11:46:09.615473 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10700 11:46:09.615578 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10701 11:46:09.615661 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10702 11:46:09.615758 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10703 11:46:09.631071 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10704 11:46:09.631560 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10705 11:46:09.631687 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10706 11:46:09.631781 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10707 11:46:09.631866 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10708 11:46:09.632023 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10709 11:46:09.632127 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10710 11:46:09.632212 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10711 11:46:09.632299 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10712 11:46:09.632401 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10713 11:46:09.632698 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10714 11:46:09.632807 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10715 11:46:09.633101 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10716 11:46:09.633308 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10717 11:46:09.633700 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10718 11:46:09.633842 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10719 11:46:09.633992 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10720 11:46:09.634148 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10721 11:46:09.634280 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10722 11:46:09.634429 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10723 11:46:09.634582 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10724 11:46:09.634733 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10725 11:46:09.634883 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10726 11:46:09.635081 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10727 11:46:09.635216 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10728 11:46:09.635352 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10729 11:46:09.635549 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10730 11:46:09.635739 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10731 11:46:09.635950 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10732 11:46:09.636104 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10733 11:46:09.636248 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10734 11:46:09.640388 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10735 11:46:09.640823 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10736 11:46:09.640998 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10737 11:46:09.641159 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10738 11:46:09.641346 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10739 11:46:09.641488 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10740 11:46:09.641609 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10741 11:46:09.641752 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10742 11:46:09.641902 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10743 11:46:09.642044 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10744 11:46:09.642190 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10745 11:46:09.642381 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10746 11:46:09.642600 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10747 11:46:09.642773 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10748 11:46:09.642931 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10749 11:46:09.643094 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10750 11:46:09.643257 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10751 11:46:09.643456 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10752 11:46:09.643623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10753 11:46:09.643780 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10754 11:46:09.643907 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10755 11:46:09.644036 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10756 11:46:09.644207 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10757 11:46:09.644350 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10758 11:46:09.644468 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10759 11:46:09.644582 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10760 11:46:09.648332 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10761 11:46:09.648809 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10762 11:46:09.649035 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10763 11:46:09.649223 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10764 11:46:09.649431 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10765 11:46:09.649617 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10766 11:46:09.649864 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10767 11:46:09.650041 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10768 11:46:09.650249 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10769 11:46:09.650431 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10770 11:46:09.650609 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10771 11:46:09.650785 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10772 11:46:09.650956 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10773 11:46:09.651165 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10774 11:46:09.651346 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10775 11:46:09.651521 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10776 11:46:09.651689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10777 11:46:09.651862 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10778 11:46:09.652049 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10779 11:46:09.652223 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10780 11:46:09.652395 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10781 11:46:09.652603 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10782 11:46:09.652785 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10783 11:46:09.652942 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10784 11:46:09.653114 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10785 11:46:09.653285 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10786 11:46:09.656309 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10787 11:46:09.656699 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10788 11:46:09.656899 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10789 11:46:09.657109 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10790 11:46:09.657293 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10791 11:46:09.657469 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10792 11:46:09.657689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10793 11:46:09.657872 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10794 11:46:09.658050 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10795 11:46:09.658226 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10796 11:46:09.658433 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10797 11:46:09.658611 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10798 11:46:09.658788 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10799 11:46:09.658964 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10800 11:46:09.659139 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10801 11:46:09.659343 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10802 11:46:09.659523 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10803 11:46:09.659698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10804 11:46:09.659873 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10805 11:46:09.660042 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10806 11:46:09.660215 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10807 11:46:09.660423 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10808 11:46:09.660604 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10809 11:46:09.660776 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10810 11:46:09.660951 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10811 11:46:09.661125 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10812 11:46:09.664394 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10813 11:46:09.664874 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10814 11:46:09.665085 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10815 11:46:09.665298 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10816 11:46:09.665482 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10817 11:46:09.665714 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10818 11:46:09.665899 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10819 11:46:09.666108 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10820 11:46:09.666321 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10821 11:46:09.666533 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10822 11:46:09.666750 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10823 11:46:09.666962 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10824 11:46:09.667171 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10825 11:46:09.667384 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10826 11:46:09.667597 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10827 11:46:09.667808 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10828 11:46:09.668021 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10829 11:46:09.668233 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10830 11:46:09.672359 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10831 11:46:09.672840 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10832 11:46:09.673053 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10833 11:46:09.673236 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10834 11:46:09.673415 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10835 11:46:09.673629 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10836 11:46:09.673828 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10837 11:46:09.674007 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10838 11:46:09.674185 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10839 11:46:09.674361 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10840 11:46:09.674541 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10841 11:46:09.674757 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10842 11:46:09.674940 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10843 11:46:09.675118 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10844 11:46:09.675296 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10845 11:46:09.675473 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10846 11:46:09.675650 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10847 11:46:09.675827 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10848 11:46:09.676004 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10849 11:46:09.676223 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10850 11:46:09.676408 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10851 11:46:09.676590 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10852 11:46:09.676773 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10853 11:46:09.676953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10854 11:46:09.677132 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10855 11:46:09.677310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10856 11:46:09.677489 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10857 11:46:09.677679 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10858 11:46:09.677860 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10859 11:46:09.678038 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10860 11:46:09.680492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10861 11:46:09.680711 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10862 11:46:09.680924 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10863 11:46:09.692616 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10864 11:46:09.692854 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10865 11:46:09.693168 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10866 11:46:09.693275 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10867 11:46:09.693365 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10868 11:46:09.693453 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10869 11:46:09.693538 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10870 11:46:09.693639 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10871 11:46:09.693731 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10872 11:46:09.693813 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10873 11:46:09.693894 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10874 11:46:09.693975 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10875 11:46:09.694078 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10876 11:46:09.694167 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10877 11:46:09.694250 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10878 11:46:09.694354 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10879 11:46:09.694441 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10880 11:46:09.694541 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10881 11:46:09.694839 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10882 11:46:09.694936 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10883 11:46:09.695042 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10884 11:46:09.695149 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10885 11:46:09.695274 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10886 11:46:09.695583 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10887 11:46:09.695690 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10888 11:46:09.695980 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10889 11:46:09.696096 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10890 11:46:09.700293 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10891 11:46:09.700595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10892 11:46:09.700697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10893 11:46:09.700970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10894 11:46:09.701062 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10895 11:46:09.701163 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10896 11:46:09.701263 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10897 11:46:09.701563 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10898 11:46:09.701664 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10899 11:46:09.701769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10900 11:46:09.702059 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10901 11:46:09.702172 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10902 11:46:09.702279 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10903 11:46:09.702580 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10904 11:46:09.702688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10905 11:46:09.702967 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10906 11:46:09.703056 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10907 11:46:09.703339 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10908 11:46:09.703429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10909 11:46:09.703555 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10910 11:46:09.703678 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10911 11:46:09.703996 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10912 11:46:09.704118 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10913 11:46:09.708314 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10914 11:46:09.708657 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10915 11:46:09.708767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10916 11:46:09.708852 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10917 11:46:09.708942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10918 11:46:09.709015 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10919 11:46:09.709107 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10920 11:46:09.709390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10921 11:46:09.709499 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10922 11:46:09.709602 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10923 11:46:09.709723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10924 11:46:09.709812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10925 11:46:09.710087 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10926 11:46:09.710181 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10927 11:46:09.710281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10928 11:46:09.710568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10929 11:46:09.710687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10930 11:46:09.710782 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10931 11:46:09.710869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10932 11:46:09.711152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10933 11:46:09.711256 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10934 11:46:09.711351 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10935 11:46:09.711679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
10936 11:46:09.711769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
10937 11:46:09.711883 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
10938 11:46:09.711990 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
10939 11:46:09.716248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
10940 11:46:09.716615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
10941 11:46:09.716755 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
10942 11:46:09.716900 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
10943 11:46:09.717059 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
10944 11:46:09.717222 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
10945 11:46:09.717378 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
10946 11:46:09.717525 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
10947 11:46:09.717703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
10948 11:46:09.717858 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
10949 11:46:09.717998 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
10950 11:46:09.718157 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
10951 11:46:09.718282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
10952 11:46:09.718377 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
10953 11:46:09.718510 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
10954 11:46:09.718612 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
10955 11:46:09.718704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
10956 11:46:09.718828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
10957 11:46:09.718951 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
10958 11:46:09.719085 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
10959 11:46:09.719217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
10960 11:46:09.719375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
10961 11:46:09.719557 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
10962 11:46:09.719692 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
10963 11:46:09.719839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
10964 11:46:09.719967 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
10965 11:46:09.720113 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
10966 11:46:09.724243 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
10967 11:46:09.724562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
10968 11:46:09.724687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
10969 11:46:09.724808 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
10970 11:46:09.724914 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
10971 11:46:09.725010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
10972 11:46:09.725309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
10973 11:46:09.725416 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
10974 11:46:09.725522 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
10975 11:46:09.725624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
10976 11:46:09.725738 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
10977 11:46:09.726031 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
10978 11:46:09.726327 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
10979 11:46:09.726427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
10980 11:46:09.726534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
10981 11:46:09.726641 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
10982 11:46:09.726746 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
10983 11:46:09.726855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
10984 11:46:09.727146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
10985 11:46:09.727255 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
10986 11:46:09.727567 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
10987 11:46:09.727687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
10988 11:46:09.727800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
10989 11:46:09.727944 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
10990 11:46:09.728065 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
10991 11:46:09.732308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
10992 11:46:09.732630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
10993 11:46:09.732737 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
10994 11:46:09.732850 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
10995 11:46:09.732949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
10996 11:46:09.733061 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
10997 11:46:09.733365 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
10998 11:46:09.733469 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
10999 11:46:09.733579 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
11000 11:46:09.744563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
11001 11:46:09.745049 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
11002 11:46:09.745185 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
11003 11:46:09.745301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
11004 11:46:09.745415 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
11005 11:46:09.745548 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
11006 11:46:09.745677 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
11007 11:46:09.745795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
11008 11:46:09.745927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
11009 11:46:09.746061 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
11010 11:46:09.746197 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
11011 11:46:09.746334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
11012 11:46:09.746471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
11013 11:46:09.746819 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
11014 11:46:09.746910 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
11015 11:46:09.747173 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
11016 11:46:09.747295 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
11017 11:46:09.747397 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
11018 11:46:09.747469 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
11019 11:46:09.747769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
11020 11:46:09.747875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
11021 11:46:09.748065 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
11022 11:46:09.748164 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
11023 11:46:09.752244 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
11024 11:46:09.752576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
11025 11:46:09.752672 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
11026 11:46:09.752786 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
11027 11:46:09.752883 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
11028 11:46:09.753144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
11029 11:46:09.753225 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
11030 11:46:09.753323 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
11031 11:46:09.753573 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
11032 11:46:09.753831 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
11033 11:46:09.753904 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
11034 11:46:09.753985 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
11035 11:46:09.754241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
11036 11:46:09.754323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
11037 11:46:09.754576 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
11038 11:46:09.754649 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
11039 11:46:09.754904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
11040 11:46:09.754988 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
11041 11:46:09.755069 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
11042 11:46:09.755323 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
11043 11:46:09.755404 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
11044 11:46:09.755657 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
11045 11:46:09.755740 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
11046 11:46:09.755822 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
11047 11:46:09.756082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
11048 11:46:09.760257 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
11049 11:46:09.760527 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
11050 11:46:09.760599 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
11051 11:46:09.760697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
11052 11:46:09.760991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
11053 11:46:09.761273 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
11054 11:46:09.761369 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
11055 11:46:09.761448 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
11056 11:46:09.761675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
11057 11:46:09.761942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
11058 11:46:09.762021 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
11059 11:46:09.762102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
11060 11:46:09.762358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
11061 11:46:09.762438 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
11062 11:46:09.762522 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
11063 11:46:09.762780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
11064 11:46:09.763038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
11065 11:46:09.763119 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
11066 11:46:09.763197 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
11067 11:46:09.763483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
11068 11:46:09.763572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
11069 11:46:09.763828 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
11070 11:46:09.763909 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
11071 11:46:09.768297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
11072 11:46:09.768572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
11073 11:46:09.768671 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
11074 11:46:09.768741 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
11075 11:46:09.768841 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
11076 11:46:09.769147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
11077 11:46:09.769267 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
11078 11:46:09.769366 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
11079 11:46:09.769479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
11080 11:46:09.769784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
11081 11:46:09.769908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
11082 11:46:09.770027 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
11083 11:46:09.770145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
11084 11:46:09.770448 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
11085 11:46:09.770579 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
11086 11:46:09.770693 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
11087 11:46:09.771014 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
11088 11:46:09.771118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
11089 11:46:09.771237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
11090 11:46:09.771343 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
11091 11:46:09.771501 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
11092 11:46:09.771650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
11093 11:46:09.771780 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
11094 11:46:09.771928 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
11095 11:46:09.776241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
11096 11:46:09.776618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
11097 11:46:09.776778 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
11098 11:46:09.776960 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
11099 11:46:09.777089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
11100 11:46:09.777231 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
11101 11:46:09.777361 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
11102 11:46:09.777522 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
11103 11:46:09.777720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
11104 11:46:09.777964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
11105 11:46:09.778162 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
11106 11:46:09.778346 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
11107 11:46:09.778555 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
11108 11:46:09.778737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
11109 11:46:09.778919 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
11110 11:46:09.779092 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
11111 11:46:09.779288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
11112 11:46:09.779472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
11113 11:46:09.779654 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
11114 11:46:09.779815 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
11115 11:46:09.780012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
11116 11:46:09.780235 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
11117 11:46:09.780382 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
11118 11:46:09.780502 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
11119 11:46:09.780620 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
11120 11:46:09.780740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
11121 11:46:09.780860 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
11122 11:46:09.784255 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
11123 11:46:09.784717 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
11124 11:46:09.784915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
11125 11:46:09.785072 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
11126 11:46:09.785303 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
11127 11:46:09.785489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
11128 11:46:09.785680 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
11129 11:46:09.785890 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
11130 11:46:09.786079 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
11131 11:46:09.786252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
11132 11:46:09.786380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
11133 11:46:09.786515 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
11134 11:46:09.786644 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
11135 11:46:09.786764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
11136 11:46:09.796535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
11137 11:46:09.796741 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
11138 11:46:09.797099 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
11139 11:46:09.797251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
11140 11:46:09.797408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
11141 11:46:09.797591 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
11142 11:46:09.797759 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
11143 11:46:09.797909 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
11144 11:46:09.798070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
11145 11:46:09.798209 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
11146 11:46:09.798373 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
11147 11:46:09.798528 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
11148 11:46:09.798656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
11149 11:46:09.798770 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
11150 11:46:09.798909 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
11151 11:46:09.799056 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
11152 11:46:09.799214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
11153 11:46:09.799341 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
11154 11:46:09.799460 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
11155 11:46:09.799578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
11156 11:46:09.799697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
11157 11:46:09.799817 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
11158 11:46:09.799970 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
11159 11:46:09.800080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
11160 11:46:09.800171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
11161 11:46:09.800256 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
11162 11:46:09.800341 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
11163 11:46:09.800427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
11164 11:46:09.804411 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
11165 11:46:09.804590 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
11166 11:46:09.804973 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
11167 11:46:09.805138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
11168 11:46:09.805272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
11169 11:46:09.805393 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
11170 11:46:09.805541 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
11171 11:46:09.805667 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
11172 11:46:09.805785 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
11173 11:46:09.805908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
11174 11:46:09.806049 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
11175 11:46:09.806184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
11176 11:46:09.806312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
11177 11:46:09.806436 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
11178 11:46:09.806586 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
11179 11:46:09.806728 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
11180 11:46:09.806854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11181 11:46:09.806975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11182 11:46:09.807121 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11183 11:46:09.807257 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11184 11:46:09.807374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11185 11:46:09.807493 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11186 11:46:09.807612 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11187 11:46:09.807760 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11188 11:46:09.807895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11189 11:46:09.808040 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11190 11:46:09.808168 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11191 11:46:09.808284 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11192 11:46:09.808422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11193 11:46:09.808541 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11194 11:46:09.812599 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11195 11:46:09.812802 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11196 11:46:09.813031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11197 11:46:09.813227 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11198 11:46:09.813440 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11199 11:46:09.813680 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11200 11:46:09.813884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11201 11:46:09.814057 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11202 11:46:09.814214 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11203 11:46:09.814362 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11204 11:46:09.814614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11205 11:46:09.814811 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11206 11:46:09.814946 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11207 11:46:09.815093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11208 11:46:09.815256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11209 11:46:09.815461 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11210 11:46:09.815651 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11211 11:46:09.815855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11212 11:46:09.816017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11213 11:46:09.816144 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11214 11:46:09.816266 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11215 11:46:09.816381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11216 11:46:09.816494 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11217 11:46:09.816609 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11218 11:46:09.816724 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11219 11:46:09.816862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11220 11:46:09.820277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11221 11:46:09.820724 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11222 11:46:09.820934 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11223 11:46:09.821107 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11224 11:46:09.821301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11225 11:46:09.821463 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11226 11:46:09.821662 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11227 11:46:09.821875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11228 11:46:09.822063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11229 11:46:09.822201 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11230 11:46:09.822345 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11231 11:46:09.822550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11232 11:46:09.822678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11233 11:46:09.822821 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11234 11:46:09.822976 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11235 11:46:09.823124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11236 11:46:09.823275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11237 11:46:09.823443 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11238 11:46:09.823609 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11239 11:46:09.823758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11240 11:46:09.823897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11241 11:46:09.824029 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11242 11:46:09.824134 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11243 11:46:09.824244 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11244 11:46:09.824336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11245 11:46:09.824423 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11246 11:46:09.824510 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11247 11:46:09.824596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11248 11:46:09.828291 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11249 11:46:09.828652 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11250 11:46:09.828798 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11251 11:46:09.828990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11252 11:46:09.829138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11253 11:46:09.829234 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11254 11:46:09.829316 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11255 11:46:09.829401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11256 11:46:09.829506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11257 11:46:09.829594 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11258 11:46:09.829687 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11259 11:46:09.829789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11260 11:46:09.829875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11261 11:46:09.829974 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11262 11:46:09.830303 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11263 11:46:09.830479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11264 11:46:09.830648 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11265 11:46:09.830785 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11266 11:46:09.831006 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11267 11:46:09.831199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11268 11:46:09.831405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11269 11:46:09.831547 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11270 11:46:09.844953 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11271 11:46:09.845513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11272 11:46:09.845630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11273 11:46:09.845731 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11274 11:46:09.845822 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11275 11:46:09.845910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11276 11:46:09.846018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11277 11:46:09.846107 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11278 11:46:09.846193 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11279 11:46:09.846298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11280 11:46:09.846387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11281 11:46:09.846491 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11282 11:46:09.846580 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11283 11:46:09.846683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11284 11:46:09.846772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11285 11:46:09.846875 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11286 11:46:09.846978 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11287 11:46:09.847078 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11288 11:46:09.847421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11289 11:46:09.847670 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11290 11:46:09.847857 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11291 11:46:09.848069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11292 11:46:09.848277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11293 11:46:09.848418 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11294 11:46:09.848561 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11295 11:46:09.852326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11296 11:46:09.852764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11297 11:46:09.852969 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11298 11:46:09.853142 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11299 11:46:09.853373 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11300 11:46:09.853570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11301 11:46:09.853808 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11302 11:46:09.854002 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11303 11:46:09.854211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11304 11:46:09.854388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11305 11:46:09.854606 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11306 11:46:09.854828 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11307 11:46:09.855031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11308 11:46:09.855216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11309 11:46:09.855475 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11310 11:46:09.855680 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11311 11:46:09.855935 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11312 11:46:09.856170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11313 11:46:09.856301 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11314 11:46:09.856418 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11315 11:46:09.856534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11316 11:46:09.856650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11317 11:46:09.856767 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11318 11:46:09.856914 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11319 11:46:09.857040 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11320 11:46:09.857158 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11321 11:46:09.857275 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11322 11:46:09.860253 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11323 11:46:09.860563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11324 11:46:09.860769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11325 11:46:09.861018 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11326 11:46:09.861241 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11327 11:46:09.861506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11328 11:46:09.861743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11329 11:46:09.861971 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11330 11:46:09.862237 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11331 11:46:09.862455 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11332 11:46:09.862638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11333 11:46:09.862866 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11334 11:46:09.863085 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11335 11:46:09.863301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11336 11:46:09.863555 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11337 11:46:09.863762 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11338 11:46:09.863972 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11339 11:46:09.864173 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11340 11:46:09.864308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11341 11:46:09.864427 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11342 11:46:09.864544 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11343 11:46:09.864658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11344 11:46:09.864771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11345 11:46:09.864886 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11346 11:46:09.865000 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11347 11:46:09.865144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11348 11:46:09.865266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11349 11:46:09.865380 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11350 11:46:09.865494 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11351 11:46:09.868288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11352 11:46:09.868776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11353 11:46:09.868963 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11354 11:46:09.869145 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11355 11:46:09.869395 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11356 11:46:09.869593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11357 11:46:09.869807 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11358 11:46:09.870031 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11359 11:46:09.870244 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11360 11:46:09.870499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11361 11:46:09.870722 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11362 11:46:09.870914 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11363 11:46:09.871096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11364 11:46:09.871301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11365 11:46:09.871506 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11366 11:46:09.871719 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11367 11:46:09.871900 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11368 11:46:09.872074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11369 11:46:09.872216 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11370 11:46:09.872370 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11371 11:46:09.872510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11372 11:46:09.872671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11373 11:46:09.872795 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11374 11:46:09.872911 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11375 11:46:09.873026 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11376 11:46:09.873146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11377 11:46:09.873261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11378 11:46:09.873375 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11379 11:46:09.873490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11380 11:46:09.873607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11381 11:46:09.876359 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11382 11:46:09.876808 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11383 11:46:09.877012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11384 11:46:09.877146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11385 11:46:09.877287 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11386 11:46:09.877432 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11387 11:46:09.877575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11388 11:46:09.877731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11389 11:46:09.877900 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11390 11:46:09.878052 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11391 11:46:09.878210 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11392 11:46:09.878354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11393 11:46:09.878491 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11394 11:46:09.878627 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11395 11:46:09.878752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11396 11:46:09.878862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11397 11:46:09.878969 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11398 11:46:09.879085 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11399 11:46:09.879227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11400 11:46:09.879327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11401 11:46:09.879416 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11402 11:46:09.879504 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11403 11:46:09.879605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11404 11:46:09.893453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11405 11:46:09.893692 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11406 11:46:09.894043 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11407 11:46:09.894236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11408 11:46:09.894444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11409 11:46:09.894640 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11410 11:46:09.894827 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11411 11:46:09.895034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11412 11:46:09.895218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11413 11:46:09.895419 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11414 11:46:09.895640 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11415 11:46:09.895794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11416 11:46:09.895989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11417 11:46:09.896176 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11418 11:46:09.896359 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11419 11:46:09.896487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11420 11:46:09.896605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11421 11:46:09.896723 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11422 11:46:09.896839 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11423 11:46:09.896954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11424 11:46:09.897070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11425 11:46:09.897185 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11426 11:46:09.900289 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11427 11:46:09.900730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11428 11:46:09.900910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11429 11:46:09.901141 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11430 11:46:09.901312 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11431 11:46:09.901507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11432 11:46:09.901713 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11433 11:46:09.901925 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11434 11:46:09.902103 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11435 11:46:09.902256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11436 11:46:09.902410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11437 11:46:09.902596 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11438 11:46:09.902780 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11439 11:46:09.902964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11440 11:46:09.903137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11441 11:46:09.903293 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11442 11:46:09.903464 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11443 11:46:09.903653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11444 11:46:09.903817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11445 11:46:09.904024 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11446 11:46:09.904193 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11447 11:46:09.904323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11448 11:46:09.904440 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11449 11:46:09.904556 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11450 11:46:09.904670 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11451 11:46:09.904784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11452 11:46:09.904899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11453 11:46:09.905012 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11454 11:46:09.905126 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11455 11:46:09.908390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11456 11:46:09.908609 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11457 11:46:09.909101 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11458 11:46:09.909315 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11459 11:46:09.909483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11460 11:46:09.909674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11461 11:46:09.909868 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11462 11:46:09.910035 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11463 11:46:09.910236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11464 11:46:09.910402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11465 11:46:09.910551 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11466 11:46:09.910708 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11467 11:46:09.910887 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11468 11:46:09.911058 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11469 11:46:09.911254 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11470 11:46:09.911421 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11471 11:46:09.911612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11472 11:46:09.911782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11473 11:46:09.911945 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11474 11:46:09.912106 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11475 11:46:09.912229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11476 11:46:09.912345 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11477 11:46:09.912459 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11478 11:46:09.912572 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11479 11:46:09.912687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11480 11:46:09.912802 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11481 11:46:09.912915 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11482 11:46:09.913057 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11483 11:46:09.913179 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11484 11:46:09.913293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11485 11:46:09.916274 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11486 11:46:09.916721 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11487 11:46:09.916920 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11488 11:46:09.917110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11489 11:46:09.917348 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11490 11:46:09.917549 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11491 11:46:09.917741 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11492 11:46:09.917914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11493 11:46:09.918080 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11494 11:46:09.918274 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11495 11:46:09.918435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11496 11:46:09.918608 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11497 11:46:09.918814 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11498 11:46:09.919037 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11499 11:46:09.919287 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11500 11:46:09.919503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11501 11:46:09.919714 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11502 11:46:09.919883 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11503 11:46:09.920038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11504 11:46:09.920167 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11505 11:46:09.920283 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11506 11:46:09.920398 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11507 11:46:09.920512 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11508 11:46:09.920627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11509 11:46:09.920742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11510 11:46:09.920855 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11511 11:46:09.920968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11512 11:46:09.921108 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11513 11:46:09.921232 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11514 11:46:09.924302 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11515 11:46:09.924758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11516 11:46:09.924924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11517 11:46:09.925095 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11518 11:46:09.925305 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11519 11:46:09.925487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11520 11:46:09.925701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11521 11:46:09.925919 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11522 11:46:09.926076 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11523 11:46:09.926236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11524 11:46:09.926412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11525 11:46:09.926587 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11526 11:46:09.926816 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11527 11:46:09.926998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11528 11:46:09.927212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11529 11:46:09.927464 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11530 11:46:09.927679 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11531 11:46:09.927832 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11532 11:46:09.928054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11533 11:46:09.928214 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11534 11:46:09.928338 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11535 11:46:09.928456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11536 11:46:09.928573 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11537 11:46:09.928687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11538 11:46:09.941703 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11539 11:46:09.941944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11540 11:46:09.942243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11541 11:46:09.942341 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11542 11:46:09.942429 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11543 11:46:09.942516 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11544 11:46:09.942618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11545 11:46:09.942707 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11546 11:46:09.942791 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11547 11:46:09.942894 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11548 11:46:09.942982 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11549 11:46:09.943084 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11550 11:46:09.943192 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11551 11:46:09.943297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11552 11:46:09.943400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11553 11:46:09.943502 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11554 11:46:09.943611 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11555 11:46:09.943913 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11556 11:46:09.944015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11557 11:46:09.944116 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11558 11:46:09.944209 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11559 11:46:09.944501 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11560 11:46:09.944617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11561 11:46:09.944709 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11562 11:46:09.944811 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11563 11:46:09.944901 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11564 11:46:09.945001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11565 11:46:09.945089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11566 11:46:09.945187 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11567 11:46:09.945292 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11568 11:46:09.945394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11569 11:46:09.945690 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11570 11:46:09.945792 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11571 11:46:09.945903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11572 11:46:09.946000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11573 11:46:09.946099 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11574 11:46:09.946198 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11575 11:46:09.946521 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11576 11:46:09.946637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11577 11:46:09.946739 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11578 11:46:09.946844 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11579 11:46:09.946945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11580 11:46:09.947046 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11581 11:46:09.947163 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11582 11:46:09.947268 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11583 11:46:09.947569 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11584 11:46:09.947674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11585 11:46:09.947780 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11586 11:46:09.947872 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11587 11:46:09.947975 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11588 11:46:09.948277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11589 11:46:09.952599 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11590 11:46:09.952833 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11591 11:46:09.953001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11592 11:46:09.953156 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11593 11:46:09.953313 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11594 11:46:09.953502 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11595 11:46:09.953659 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11596 11:46:09.953811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11597 11:46:09.953953 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11598 11:46:09.954104 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11599 11:46:09.954225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11600 11:46:09.954346 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11601 11:46:09.954463 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11602 11:46:09.954579 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11603 11:46:09.954730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11604 11:46:09.954875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11605 11:46:09.955037 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11606 11:46:09.955237 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11607 11:46:09.955402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11608 11:46:09.955559 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11609 11:46:09.955761 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11610 11:46:09.955937 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11611 11:46:09.956085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11612 11:46:09.956207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11613 11:46:09.956323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11614 11:46:09.956438 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11615 11:46:09.956551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11616 11:46:09.956665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11617 11:46:09.956777 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11618 11:46:09.956917 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11619 11:46:09.957038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11620 11:46:09.960414 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11621 11:46:09.960869 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11622 11:46:09.961038 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11623 11:46:09.961434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11624 11:46:09.961587 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11625 11:46:09.961739 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11626 11:46:09.961862 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11627 11:46:09.962001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11628 11:46:09.962121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11629 11:46:09.965834 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11630 11:46:09.965978 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11631 11:46:09.966065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11632 11:46:09.966148 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11633 11:46:09.966227 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11634 11:46:09.966308 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11635 11:46:09.966392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11636 11:46:09.966475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11637 11:46:09.966555 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11638 11:46:09.966636 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11639 11:46:09.966718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11640 11:46:09.966800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11641 11:46:09.966881 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11642 11:46:09.966966 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11643 11:46:09.967049 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11644 11:46:09.967132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11645 11:46:09.967217 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11646 11:46:09.968607 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11647 11:46:09.968712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11648 11:46:09.968800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11649 11:46:09.969116 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11650 11:46:09.969280 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11651 11:46:09.969413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11652 11:46:09.969578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11653 11:46:09.969773 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11654 11:46:09.969959 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11655 11:46:09.970125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11656 11:46:09.970280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11657 11:46:09.970471 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11658 11:46:09.970638 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11659 11:46:09.970774 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11660 11:46:09.970891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11661 11:46:09.971007 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11662 11:46:09.971173 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11663 11:46:09.971334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11664 11:46:09.971485 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11665 11:46:09.971607 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11666 11:46:09.971720 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11667 11:46:09.971834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11668 11:46:09.971955 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11669 11:46:09.972069 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11670 11:46:09.972183 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11671 11:46:09.972298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11672 11:46:09.992825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11673 11:46:09.993080 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11674 11:46:09.993420 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11675 11:46:09.993510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11676 11:46:09.993631 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11677 11:46:09.993728 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11678 11:46:09.993814 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11679 11:46:09.993918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11680 11:46:09.994007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11681 11:46:09.994300 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11682 11:46:09.994435 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11683 11:46:09.994572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11684 11:46:09.994696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11685 11:46:09.994793 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11686 11:46:09.994898 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11687 11:46:09.994987 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11688 11:46:09.995074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11689 11:46:09.995180 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11690 11:46:09.995302 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11691 11:46:09.995390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11692 11:46:09.995487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11693 11:46:09.997810 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11694 11:46:09.997908 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11695 11:46:09.997973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11696 11:46:09.998036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11697 11:46:09.998096 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11698 11:46:10.000363 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11699 11:46:10.000725 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11700 11:46:10.000827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11701 11:46:10.001146 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11702 11:46:10.001248 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11703 11:46:10.001333 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11704 11:46:10.001422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11705 11:46:10.001524 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11706 11:46:10.001904 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11707 11:46:10.002008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11708 11:46:10.002085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11709 11:46:10.002365 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11710 11:46:10.002453 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11711 11:46:10.002537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11712 11:46:10.002615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11713 11:46:10.002922 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11714 11:46:10.003024 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11715 11:46:10.003112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11716 11:46:10.003201 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11717 11:46:10.003310 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11718 11:46:10.003401 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11719 11:46:10.003491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11720 11:46:10.003596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11721 11:46:10.003703 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11722 11:46:10.003811 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11723 11:46:10.004107 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11724 11:46:10.008342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11725 11:46:10.008787 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11726 11:46:10.008887 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11727 11:46:10.008983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11728 11:46:10.009320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11729 11:46:10.009634 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11730 11:46:10.009740 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11731 11:46:10.010026 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11732 11:46:10.010135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11733 11:46:10.010245 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11734 11:46:10.010337 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11735 11:46:10.010439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11736 11:46:10.010542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11737 11:46:10.010645 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11738 11:46:10.010975 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11739 11:46:10.011086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11740 11:46:10.011375 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11741 11:46:10.011478 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11742 11:46:10.011581 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11743 11:46:10.011681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11744 11:46:10.011784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11745 11:46:10.012080 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11746 11:46:10.016324 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11747 11:46:10.016678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11748 11:46:10.017295 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11749 11:46:10.017405 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11750 11:46:10.017494 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11751 11:46:10.017579 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11752 11:46:10.017671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11753 11:46:10.017958 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11754 11:46:10.018062 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11755 11:46:10.018166 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11756 11:46:10.018251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11757 11:46:10.018334 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11758 11:46:10.018417 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11759 11:46:10.018516 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11760 11:46:10.018601 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11761 11:46:10.018684 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11762 11:46:10.018968 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11763 11:46:10.019085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11764 11:46:10.019173 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11765 11:46:10.019452 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11766 11:46:10.019545 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11767 11:46:10.019628 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11768 11:46:10.019712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11769 11:46:10.019817 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11770 11:46:10.019903 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11771 11:46:10.019986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11772 11:46:10.020084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11773 11:46:10.020170 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11774 11:46:10.020255 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11775 11:46:10.024617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11776 11:46:10.024782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11777 11:46:10.024884 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11778 11:46:10.024971 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11779 11:46:10.025069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11780 11:46:10.025185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11781 11:46:10.025530 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11782 11:46:10.025631 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11783 11:46:10.025737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11784 11:46:10.026036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11785 11:46:10.026142 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11786 11:46:10.026437 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11787 11:46:10.026537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11788 11:46:10.026834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11789 11:46:10.026936 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11790 11:46:10.027025 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11791 11:46:10.027112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11792 11:46:10.027215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11793 11:46:10.027303 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11794 11:46:10.027391 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11795 11:46:10.027676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11796 11:46:10.027771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11797 11:46:10.028046 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11798 11:46:10.028138 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11799 11:46:10.028240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11800 11:46:10.028335 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11801 11:46:10.028421 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11802 11:46:10.032442 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11803 11:46:10.032572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11804 11:46:10.032860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11805 11:46:10.032960 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11806 11:46:10.044776 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11807 11:46:10.045290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11808 11:46:10.045393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11809 11:46:10.045482 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11810 11:46:10.045568 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11811 11:46:10.045665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11812 11:46:10.045771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11813 11:46:10.045862 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11814 11:46:10.045946 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11815 11:46:10.046048 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11816 11:46:10.046134 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11817 11:46:10.046236 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11818 11:46:10.046544 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11819 11:46:10.046642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11820 11:46:10.046727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11821 11:46:10.046825 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11822 11:46:10.046910 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11823 11:46:10.047008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11824 11:46:10.047106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11825 11:46:10.047207 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11826 11:46:10.047538 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11827 11:46:10.047640 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11828 11:46:10.048108 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11829 11:46:10.048451 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11830 11:46:10.048553 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11831 11:46:10.048638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11832 11:46:10.052526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11833 11:46:10.052986 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11834 11:46:10.053519 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11835 11:46:10.053711 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11836 11:46:10.053916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11837 11:46:10.054063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11838 11:46:10.054193 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11839 11:46:10.054317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11840 11:46:10.054467 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11841 11:46:10.054598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11842 11:46:10.055123 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11843 11:46:10.055328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11844 11:46:10.055509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11845 11:46:10.055687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11846 11:46:10.055852 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11847 11:46:10.055990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11848 11:46:10.056113 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11849 11:46:10.056229 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11850 11:46:10.056344 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11851 11:46:10.056459 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11852 11:46:10.056599 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11853 11:46:10.060292 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11854 11:46:10.060772 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11855 11:46:10.060957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11856 11:46:10.061172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11857 11:46:10.061400 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11858 11:46:10.061543 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11859 11:46:10.061677 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11860 11:46:10.061769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11861 11:46:10.062097 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11862 11:46:10.062198 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11863 11:46:10.062297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11864 11:46:10.062398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11865 11:46:10.062690 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11866 11:46:10.063047 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11867 11:46:10.063151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11868 11:46:10.063252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11869 11:46:10.063572 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11870 11:46:10.063689 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11871 11:46:10.063790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11872 11:46:10.063875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11873 11:46:10.064169 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11874 11:46:10.068315 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11875 11:46:10.068884 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11876 11:46:10.069125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11877 11:46:10.069302 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11878 11:46:10.069505 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11879 11:46:10.069845 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11880 11:46:10.070016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11881 11:46:10.070180 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11882 11:46:10.070348 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11883 11:46:10.070550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11884 11:46:10.070721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11885 11:46:10.070876 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11886 11:46:10.071044 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11887 11:46:10.071211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11888 11:46:10.071349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11889 11:46:10.071507 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11890 11:46:10.071655 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11891 11:46:10.071819 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11892 11:46:10.071987 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11893 11:46:10.072128 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11894 11:46:10.072272 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11895 11:46:10.072392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11896 11:46:10.072511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11897 11:46:10.076300 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11898 11:46:10.076751 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11899 11:46:10.076898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11900 11:46:10.077016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11901 11:46:10.077111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11902 11:46:10.077219 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11903 11:46:10.077311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11904 11:46:10.077620 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11905 11:46:10.077749 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11906 11:46:10.078079 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11907 11:46:10.078351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11908 11:46:10.078472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11909 11:46:10.078561 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11910 11:46:10.078662 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11911 11:46:10.078952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11912 11:46:10.079123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11913 11:46:10.079229 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11914 11:46:10.079330 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11915 11:46:10.079433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11916 11:46:10.079518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11917 11:46:10.079617 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11918 11:46:10.079903 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11919 11:46:10.080011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11920 11:46:10.084372 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11921 11:46:10.084789 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11922 11:46:10.084903 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11923 11:46:10.085013 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11924 11:46:10.085117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11925 11:46:10.085223 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11926 11:46:10.085328 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11927 11:46:10.085632 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11928 11:46:10.085759 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11929 11:46:10.085873 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11930 11:46:10.086175 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11931 11:46:10.086295 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11932 11:46:10.086591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11933 11:46:10.086698 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11934 11:46:10.086805 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11935 11:46:10.086911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
11936 11:46:10.087205 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
11937 11:46:10.087582 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
11938 11:46:10.087686 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
11939 11:46:10.087787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
11940 11:46:10.099221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
11941 11:46:10.099766 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
11942 11:46:10.099950 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
11943 11:46:10.100123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
11944 11:46:10.100306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
11945 11:46:10.100545 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
11946 11:46:10.100718 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
11947 11:46:10.100844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
11948 11:46:10.100988 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
11949 11:46:10.101111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
11950 11:46:10.101248 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
11951 11:46:10.101389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
11952 11:46:10.101753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
11953 11:46:10.102010 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
11954 11:46:10.102202 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
11955 11:46:10.102464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
11956 11:46:10.102686 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
11957 11:46:10.102860 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
11958 11:46:10.103086 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
11959 11:46:10.103272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
11960 11:46:10.103443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
11961 11:46:10.103607 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
11962 11:46:10.103770 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
11963 11:46:10.103972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
11964 11:46:10.104121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
11965 11:46:10.104241 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
11966 11:46:10.104355 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
11967 11:46:10.104493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
11968 11:46:10.108679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
11969 11:46:10.108844 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
11970 11:46:10.108960 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
11971 11:46:10.109058 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
11972 11:46:10.109167 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
11973 11:46:10.109274 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
11974 11:46:10.109574 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
11975 11:46:10.109701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
11976 11:46:10.109947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
11977 11:46:10.110070 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
11978 11:46:10.110159 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
11979 11:46:10.110256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
11980 11:46:10.110555 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
11981 11:46:10.110659 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
11982 11:46:10.110760 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
11983 11:46:10.110865 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
11984 11:46:10.111167 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
11985 11:46:10.111287 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
11986 11:46:10.111390 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
11987 11:46:10.111724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
11988 11:46:10.111952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
11989 11:46:10.112193 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
11990 11:46:10.112379 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
11991 11:46:10.116564 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
11992 11:46:10.116825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
11993 11:46:10.117068 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
11994 11:46:10.117254 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
11995 11:46:10.117426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
11996 11:46:10.117614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
11997 11:46:10.117852 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
11998 11:46:10.118061 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
11999 11:46:10.118285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
12000 11:46:10.118467 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
12001 11:46:10.118668 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
12002 11:46:10.118871 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
12003 11:46:10.119126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
12004 11:46:10.119320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
12005 11:46:10.119511 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
12006 11:46:10.119667 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
12007 11:46:10.119861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
12008 11:46:10.120031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
12009 11:46:10.120158 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
12010 11:46:10.120275 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
12011 11:46:10.120415 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
12012 11:46:10.124298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
12013 11:46:10.124644 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
12014 11:46:10.124745 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
12015 11:46:10.124856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
12016 11:46:10.124954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
12017 11:46:10.125064 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
12018 11:46:10.125175 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
12019 11:46:10.125282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
12020 11:46:10.125403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
12021 11:46:10.125515 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
12022 11:46:10.125709 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
12023 11:46:10.125831 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
12024 11:46:10.126163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
12025 11:46:10.126362 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
12026 11:46:10.126564 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
12027 11:46:10.126756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
12028 11:46:10.126949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
12029 11:46:10.127176 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
12030 11:46:10.127378 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
12031 11:46:10.127557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
12032 11:46:10.127748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
12033 11:46:10.127912 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
12034 11:46:10.128070 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
12035 11:46:10.128198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
12036 11:46:10.128312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
12037 11:46:10.128448 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
12038 11:46:10.128564 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
12039 11:46:10.132355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
12040 11:46:10.132725 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
12041 11:46:10.132834 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
12042 11:46:10.132939 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
12043 11:46:10.133027 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
12044 11:46:10.133130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
12045 11:46:10.133443 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
12046 11:46:10.133554 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
12047 11:46:10.133663 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
12048 11:46:10.133765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
12049 11:46:10.134091 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
12050 11:46:10.134207 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
12051 11:46:10.134514 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
12052 11:46:10.134618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
12053 11:46:10.134718 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
12054 11:46:10.134819 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
12055 11:46:10.135128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
12056 11:46:10.135243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
12057 11:46:10.135351 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
12058 11:46:10.135646 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
12059 11:46:10.135749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
12060 11:46:10.135851 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
12061 11:46:10.136164 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
12062 11:46:10.140314 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
12063 11:46:10.140690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
12064 11:46:10.140799 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
12065 11:46:10.140904 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
12066 11:46:10.140999 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
12067 11:46:10.141112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
12068 11:46:10.141427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
12069 11:46:10.141631 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
12070 11:46:10.141864 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
12071 11:46:10.142001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
12072 11:46:10.142118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
12073 11:46:10.142241 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
12074 11:46:10.154478 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
12075 11:46:10.154783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
12076 11:46:10.155220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
12077 11:46:10.155409 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
12078 11:46:10.155586 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
12079 11:46:10.155765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
12080 11:46:10.155935 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
12081 11:46:10.156124 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
12082 11:46:10.156275 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
12083 11:46:10.156444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
12084 11:46:10.156683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
12085 11:46:10.156876 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
12086 11:46:10.157085 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
12087 11:46:10.157259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
12088 11:46:10.157445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
12089 11:46:10.157617 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
12090 11:46:10.157796 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
12091 11:46:10.157970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
12092 11:46:10.158169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
12093 11:46:10.158325 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
12094 11:46:10.158457 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
12095 11:46:10.158616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
12096 11:46:10.158778 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
12097 11:46:10.158930 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
12098 11:46:10.159081 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
12099 11:46:10.159271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
12100 11:46:10.159436 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
12101 11:46:10.159602 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
12102 11:46:10.159766 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
12103 11:46:10.159927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
12104 11:46:10.160079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
12105 11:46:10.160199 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
12106 11:46:10.160315 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
12107 11:46:10.160647 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
12108 11:46:10.160756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
12109 11:46:10.160850 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
12110 11:46:10.160943 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
12111 11:46:10.161037 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
12112 11:46:10.161129 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
12113 11:46:10.164344 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
12114 11:46:10.164732 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
12115 11:46:10.164839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
12116 11:46:10.164925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
12117 11:46:10.165023 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
12118 11:46:10.165109 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
12119 11:46:10.165206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
12120 11:46:10.165505 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
12121 11:46:10.165627 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
12122 11:46:10.165721 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
12123 11:46:10.166027 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
12124 11:46:10.166340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
12125 11:46:10.166442 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
12126 11:46:10.166541 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
12127 11:46:10.166628 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
12128 11:46:10.166927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
12129 11:46:10.167030 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
12130 11:46:10.167325 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
12131 11:46:10.167427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
12132 11:46:10.167528 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
12133 11:46:10.167630 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
12134 11:46:10.169782 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
12135 11:46:10.169906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
12136 11:46:10.170004 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
12137 11:46:10.172322 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
12138 11:46:10.172776 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
12139 11:46:10.172973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
12140 11:46:10.173164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
12141 11:46:10.173371 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
12142 11:46:10.173535 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
12143 11:46:10.173685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
12144 11:46:10.173853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
12145 11:46:10.174047 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
12146 11:46:10.174210 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
12147 11:46:10.174374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
12148 11:46:10.174535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
12149 11:46:10.174751 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
12150 11:46:10.174951 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
12151 11:46:10.175118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
12152 11:46:10.175274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
12153 11:46:10.175404 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
12154 11:46:10.175535 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
12155 11:46:10.175694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
12156 11:46:10.175893 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
12157 11:46:10.176055 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
12158 11:46:10.176178 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
12159 11:46:10.176296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
12160 11:46:10.176418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
12161 11:46:10.176544 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
12162 11:46:10.176667 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
12163 11:46:10.176791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
12164 11:46:10.176942 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
12165 11:46:10.180322 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
12166 11:46:10.180702 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
12167 11:46:10.180806 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
12168 11:46:10.180898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
12169 11:46:10.180998 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
12170 11:46:10.181096 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
12171 11:46:10.181198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
12172 11:46:10.181697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
12173 11:46:10.181802 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
12174 11:46:10.181905 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
12175 11:46:10.182009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
12176 11:46:10.182307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
12177 11:46:10.182412 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
12178 11:46:10.182513 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
12179 11:46:10.182614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
12180 11:46:10.182911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12181 11:46:10.183028 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12182 11:46:10.183131 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12183 11:46:10.183334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12184 11:46:10.183685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12185 11:46:10.183806 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12186 11:46:10.183894 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12187 11:46:10.183994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12188 11:46:10.188342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12189 11:46:10.188709 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12190 11:46:10.188813 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12191 11:46:10.188914 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12192 11:46:10.189000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12193 11:46:10.189098 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12194 11:46:10.189393 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12195 11:46:10.189512 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12196 11:46:10.189615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12197 11:46:10.189727 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12198 11:46:10.190013 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12199 11:46:10.190121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12200 11:46:10.190227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12201 11:46:10.190406 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12202 11:46:10.190527 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12203 11:46:10.190869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12204 11:46:10.191097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12205 11:46:10.191271 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12206 11:46:10.191422 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12207 11:46:10.191547 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12208 11:46:10.206707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12209 11:46:10.207243 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12210 11:46:10.207441 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12211 11:46:10.207611 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12212 11:46:10.207766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12213 11:46:10.207945 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12214 11:46:10.208084 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12215 11:46:10.208225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12216 11:46:10.208388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12217 11:46:10.208608 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12218 11:46:10.208829 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12219 11:46:10.209011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12220 11:46:10.209228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12221 11:46:10.209390 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12222 11:46:10.209575 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12223 11:46:10.209838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12224 11:46:10.210038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12225 11:46:10.210230 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12226 11:46:10.210374 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12227 11:46:10.210532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12228 11:46:10.210707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12229 11:46:10.210891 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12230 11:46:10.211029 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12231 11:46:10.211171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12232 11:46:10.211314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12233 11:46:10.211458 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12234 11:46:10.211601 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12235 11:46:10.211747 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12236 11:46:10.211924 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12237 11:46:10.212082 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12238 11:46:10.212254 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12239 11:46:10.212397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12240 11:46:10.212541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12241 11:46:10.212906 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12242 11:46:10.213047 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12243 11:46:10.213192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12244 11:46:10.216418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12245 11:46:10.217024 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12246 11:46:10.217300 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12247 11:46:10.217507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12248 11:46:10.217727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12249 11:46:10.217986 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12250 11:46:10.218190 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12251 11:46:10.218376 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12252 11:46:10.218544 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12253 11:46:10.218704 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12254 11:46:10.218865 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12255 11:46:10.219068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12256 11:46:10.219241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12257 11:46:10.219405 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12258 11:46:10.219565 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12259 11:46:10.219720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12260 11:46:10.219883 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12261 11:46:10.220038 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12262 11:46:10.220159 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12263 11:46:10.220303 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12264 11:46:10.220425 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12265 11:46:10.220541 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12266 11:46:10.220665 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12267 11:46:10.220781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12268 11:46:10.224320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12269 11:46:10.224685 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12270 11:46:10.224788 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12271 11:46:10.224892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12272 11:46:10.225190 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12273 11:46:10.225294 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12274 11:46:10.225396 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12275 11:46:10.225702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12276 11:46:10.225822 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12277 11:46:10.226110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12278 11:46:10.226212 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12279 11:46:10.226312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12280 11:46:10.226526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12281 11:46:10.226785 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12282 11:46:10.226971 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12283 11:46:10.227165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12284 11:46:10.227396 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12285 11:46:10.227679 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12286 11:46:10.227907 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12287 11:46:10.228109 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12288 11:46:10.228246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12289 11:46:10.228415 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12290 11:46:10.228567 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12291 11:46:10.228702 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12292 11:46:10.232581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12293 11:46:10.232855 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12294 11:46:10.233054 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12295 11:46:10.233263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12296 11:46:10.233481 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12297 11:46:10.233659 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12298 11:46:10.233867 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12299 11:46:10.234057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12300 11:46:10.234218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12301 11:46:10.234369 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12302 11:46:10.234528 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12303 11:46:10.234696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12304 11:46:10.234910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12305 11:46:10.235076 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12306 11:46:10.235236 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12307 11:46:10.235385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12308 11:46:10.235533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12309 11:46:10.235710 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12310 11:46:10.235872 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12311 11:46:10.236031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12312 11:46:10.236163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12313 11:46:10.236282 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12314 11:46:10.236419 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12315 11:46:10.236572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12316 11:46:10.236720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12317 11:46:10.236846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12318 11:46:10.240334 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12319 11:46:10.240716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12320 11:46:10.240820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12321 11:46:10.240924 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12322 11:46:10.241011 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12323 11:46:10.241116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12324 11:46:10.241415 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12325 11:46:10.241533 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12326 11:46:10.241634 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12327 11:46:10.241931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12328 11:46:10.242023 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12329 11:46:10.242123 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12330 11:46:10.242223 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12331 11:46:10.242507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12332 11:46:10.242614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12333 11:46:10.242716 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12334 11:46:10.242816 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12335 11:46:10.243112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12336 11:46:10.243229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12337 11:46:10.243331 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12338 11:46:10.243617 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12339 11:46:10.243715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12340 11:46:10.243817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12341 11:46:10.244114 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12342 11:46:10.259729 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12343 11:46:10.260041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12344 11:46:10.260376 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12345 11:46:10.260486 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12346 11:46:10.260577 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12347 11:46:10.260681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12348 11:46:10.260770 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12349 11:46:10.260873 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12350 11:46:10.260964 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12351 11:46:10.261270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12352 11:46:10.261381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12353 11:46:10.261644 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12354 11:46:10.261759 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12355 11:46:10.261859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12356 11:46:10.262219 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12357 11:46:10.262465 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12358 11:46:10.262644 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12359 11:46:10.262844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12360 11:46:10.263014 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12361 11:46:10.263217 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12362 11:46:10.263456 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12363 11:46:10.263678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12364 11:46:10.263861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12365 11:46:10.264030 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12366 11:46:10.264207 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12367 11:46:10.264331 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12368 11:46:10.268413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12369 11:46:10.268789 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12370 11:46:10.268897 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12371 11:46:10.268982 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12372 11:46:10.269080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12373 11:46:10.269180 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12374 11:46:10.269278 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12375 11:46:10.269614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12376 11:46:10.269723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12377 11:46:10.270023 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12378 11:46:10.270126 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12379 11:46:10.270412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12380 11:46:10.270518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12381 11:46:10.270617 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12382 11:46:10.270930 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12383 11:46:10.271033 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12384 11:46:10.271132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12385 11:46:10.271461 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12386 11:46:10.271579 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12387 11:46:10.271757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12388 11:46:10.271875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12389 11:46:10.276274 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12390 11:46:10.276617 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12391 11:46:10.276767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12392 11:46:10.276925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12393 11:46:10.277089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12394 11:46:10.277199 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12395 11:46:10.277304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12396 11:46:10.277586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12397 11:46:10.277702 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12398 11:46:10.277807 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12399 11:46:10.278161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12400 11:46:10.278438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12401 11:46:10.278645 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12402 11:46:10.278850 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12403 11:46:10.279064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12404 11:46:10.279282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12405 11:46:10.279549 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12406 11:46:10.279767 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12407 11:46:10.279986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12408 11:46:10.280208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12409 11:46:10.280348 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12410 11:46:10.280522 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12411 11:46:10.284308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12412 11:46:10.284691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12413 11:46:10.284902 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12414 11:46:10.285113 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12415 11:46:10.285262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12416 11:46:10.285394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12417 11:46:10.285551 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12418 11:46:10.285705 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12419 11:46:10.285838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12420 11:46:10.285994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12421 11:46:10.286128 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12422 11:46:10.286257 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12423 11:46:10.286413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12424 11:46:10.286546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12425 11:46:10.286674 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12426 11:46:10.286804 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12427 11:46:10.286956 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12428 11:46:10.287089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12429 11:46:10.287220 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12430 11:46:10.287372 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12431 11:46:10.287507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12432 11:46:10.287634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12433 11:46:10.287784 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12434 11:46:10.287909 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12435 11:46:10.289800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12436 11:46:10.289972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12437 11:46:10.290092 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12438 11:46:10.292497 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12439 11:46:10.292940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12440 11:46:10.293049 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12441 11:46:10.293146 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12442 11:46:10.293254 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12443 11:46:10.293360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12444 11:46:10.293666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12445 11:46:10.293771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12446 11:46:10.293872 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12447 11:46:10.294171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12448 11:46:10.294276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12449 11:46:10.294377 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12450 11:46:10.294484 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12451 11:46:10.294792 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12452 11:46:10.295128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12453 11:46:10.295228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12454 11:46:10.295315 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12455 11:46:10.295612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12456 11:46:10.295716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12457 11:46:10.295801 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12458 11:46:10.295897 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12459 11:46:10.295993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12460 11:46:10.296092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12461 11:46:10.300301 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12462 11:46:10.300733 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12463 11:46:10.300915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12464 11:46:10.301099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12465 11:46:10.301313 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12466 11:46:10.301545 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12467 11:46:10.301794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12468 11:46:10.301950 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12469 11:46:10.302145 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12470 11:46:10.302326 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12471 11:46:10.302514 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12472 11:46:10.302647 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12473 11:46:10.302766 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12474 11:46:10.302880 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12475 11:46:10.303025 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12476 11:46:10.314431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12477 11:46:10.314832 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12478 11:46:10.314930 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12479 11:46:10.315019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12480 11:46:10.315123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12481 11:46:10.315211 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12482 11:46:10.315310 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12483 11:46:10.315411 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12484 11:46:10.315715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12485 11:46:10.315838 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12486 11:46:10.315941 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12487 11:46:10.316397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12488 11:46:10.316513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12489 11:46:10.316856 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12490 11:46:10.317058 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12491 11:46:10.317242 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12492 11:46:10.317413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12493 11:46:10.317615 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12494 11:46:10.317800 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12495 11:46:10.317964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12496 11:46:10.318169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12497 11:46:10.318339 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12498 11:46:10.318505 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12499 11:46:10.318705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12500 11:46:10.318878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12501 11:46:10.319048 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12502 11:46:10.319245 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12503 11:46:10.319418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12504 11:46:10.319612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12505 11:46:10.319782 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12506 11:46:10.319976 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12507 11:46:10.320147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12508 11:46:10.320285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12509 11:46:10.324345 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12510 11:46:10.324808 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12511 11:46:10.324922 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12512 11:46:10.325015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12513 11:46:10.325120 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12514 11:46:10.325211 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12515 11:46:10.325299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12516 11:46:10.325405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12517 11:46:10.325497 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12518 11:46:10.325596 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12519 11:46:10.325708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12520 11:46:10.325982 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12521 11:46:10.326101 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12522 11:46:10.326190 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12523 11:46:10.326490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12524 11:46:10.326593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12525 11:46:10.326692 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12526 11:46:10.326792 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12527 11:46:10.327130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12528 11:46:10.327233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12529 11:46:10.327332 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12530 11:46:10.327436 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12531 11:46:10.327844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12532 11:46:10.327960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12533 11:46:10.328255 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12534 11:46:10.332563 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12535 11:46:10.332793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12536 11:46:10.332990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12537 11:46:10.333148 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12538 11:46:10.333294 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12539 11:46:10.333465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12540 11:46:10.333602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12541 11:46:10.333775 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12542 11:46:10.334024 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12543 11:46:10.334197 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12544 11:46:10.334368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12545 11:46:10.334562 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12546 11:46:10.334775 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12547 11:46:10.334954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12548 11:46:10.335137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12549 11:46:10.335278 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12550 11:46:10.335401 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12551 11:46:10.335522 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12552 11:46:10.335666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12553 11:46:10.335796 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12554 11:46:10.335924 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12555 11:46:10.336084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12556 11:46:10.336219 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12557 11:46:10.340300 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12558 11:46:10.340648 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12559 11:46:10.340757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12560 11:46:10.340857 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12561 11:46:10.340962 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12562 11:46:10.341062 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12563 11:46:10.341336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12564 11:46:10.341465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12565 11:46:10.341580 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12566 11:46:10.341896 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12567 11:46:10.342003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12568 11:46:10.342101 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12569 11:46:10.342201 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12570 11:46:10.342514 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12571 11:46:10.342632 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12572 11:46:10.342719 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12573 11:46:10.343014 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12574 11:46:10.343133 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12575 11:46:10.343237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12576 11:46:10.343534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12577 11:46:10.343651 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12578 11:46:10.343744 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12579 11:46:10.343846 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12580 11:46:10.344138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12581 11:46:10.352398 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12582 11:46:10.352717 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12583 11:46:10.353132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12584 11:46:10.353236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12585 11:46:10.353323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12586 11:46:10.353408 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12587 11:46:10.353492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12588 11:46:10.353590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12589 11:46:10.353687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12590 11:46:10.353770 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12591 11:46:10.353868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12592 11:46:10.353968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12593 11:46:10.354282 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12594 11:46:10.354399 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12595 11:46:10.354500 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12596 11:46:10.354997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12597 11:46:10.355128 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12598 11:46:10.355221 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12599 11:46:10.355322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12600 11:46:10.355424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12601 11:46:10.355526 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12602 11:46:10.355744 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12603 11:46:10.355863 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12604 11:46:10.356170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12605 11:46:10.360323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12606 11:46:10.360845 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12607 11:46:10.361014 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12608 11:46:10.361140 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12609 11:46:10.361260 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12610 11:46:10.369897 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12611 11:46:10.370449 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12612 11:46:10.370653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12613 11:46:10.370839 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12614 11:46:10.371055 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12615 11:46:10.371305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12616 11:46:10.371487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12617 11:46:10.371673 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12618 11:46:10.371864 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12619 11:46:10.372005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12620 11:46:10.372129 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12621 11:46:10.372282 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12622 11:46:10.372443 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12623 11:46:10.372615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12624 11:46:10.372767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12625 11:46:10.372984 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12626 11:46:10.373172 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12627 11:46:10.373380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12628 11:46:10.373558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12629 11:46:10.377838 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12630 11:46:10.378034 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12631 11:46:10.378192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12632 11:46:10.378348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12633 11:46:10.378503 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12634 11:46:10.378659 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12635 11:46:10.378862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12636 11:46:10.379026 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12637 11:46:10.379182 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12638 11:46:10.379337 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12639 11:46:10.379492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12640 11:46:10.379646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12641 11:46:10.379800 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12642 11:46:10.379954 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12643 11:46:10.380439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12644 11:46:10.380639 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12645 11:46:10.380802 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12646 11:46:10.380959 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12647 11:46:10.381115 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12648 11:46:10.381270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12649 11:46:10.381424 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12650 11:46:10.381662 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12651 11:46:10.381847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12652 11:46:10.382043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12653 11:46:10.382205 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12654 11:46:10.382361 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12655 11:46:10.382514 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12656 11:46:10.382668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12657 11:46:10.382820 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12658 11:46:10.382972 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12659 11:46:10.383128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12660 11:46:10.383282 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12661 11:46:10.383468 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12662 11:46:10.383628 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12663 11:46:10.383782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12664 11:46:10.383936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12665 11:46:10.384090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12666 11:46:10.384244 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12667 11:46:10.384397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12668 11:46:10.384583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12669 11:46:10.384742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12670 11:46:10.384896 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12671 11:46:10.385049 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12672 11:46:10.385203 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12673 11:46:10.388345 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12674 11:46:10.388560 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12675 11:46:10.388976 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12676 11:46:10.389174 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12677 11:46:10.389334 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12678 11:46:10.389520 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12679 11:46:10.389688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12680 11:46:10.389836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12681 11:46:10.389982 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12682 11:46:10.390127 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12683 11:46:10.390299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12684 11:46:10.390444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12685 11:46:10.390588 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12686 11:46:10.390730 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12687 11:46:10.390874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12688 11:46:10.391017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12689 11:46:10.391160 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12690 11:46:10.391303 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12691 11:46:10.391484 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12692 11:46:10.391673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12693 11:46:10.391848 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12694 11:46:10.392010 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12695 11:46:10.392146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12696 11:46:10.392306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12697 11:46:10.392480 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12698 11:46:10.392653 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12699 11:46:10.392825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12700 11:46:10.392998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12701 11:46:10.393215 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12702 11:46:10.393391 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12703 11:46:10.393542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12704 11:46:10.393676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12705 11:46:10.393797 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12706 11:46:10.394130 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12707 11:46:10.396637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12708 11:46:10.396761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12709 11:46:10.396848 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12710 11:46:10.397125 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12711 11:46:10.397405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12712 11:46:10.397495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12713 11:46:10.397579 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12714 11:46:10.397669 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12715 11:46:10.397769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12716 11:46:10.397854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12717 11:46:10.397937 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12718 11:46:10.398035 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12719 11:46:10.398133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12720 11:46:10.398475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12721 11:46:10.398587 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12722 11:46:10.398673 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12723 11:46:10.398769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12724 11:46:10.399068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12725 11:46:10.399168 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12726 11:46:10.399266 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12727 11:46:10.399550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12728 11:46:10.399639 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12729 11:46:10.399735 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12730 11:46:10.399834 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12731 11:46:10.400121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12732 11:46:10.408469 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12733 11:46:10.408894 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12734 11:46:10.408985 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12735 11:46:10.409068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12736 11:46:10.409156 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12737 11:46:10.409256 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12738 11:46:10.409342 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12739 11:46:10.409424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12740 11:46:10.409523 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12741 11:46:10.409622 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12742 11:46:10.409729 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12743 11:46:10.409839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12744 11:46:10.421091 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12745 11:46:10.421300 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12746 11:46:10.421589 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12747 11:46:10.421689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12748 11:46:10.421793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12749 11:46:10.421879 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12750 11:46:10.421978 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12751 11:46:10.422253 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12752 11:46:10.422533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12753 11:46:10.422622 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12754 11:46:10.422707 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12755 11:46:10.422791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12756 11:46:10.422892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12757 11:46:10.422996 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12758 11:46:10.423095 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12759 11:46:10.423379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12760 11:46:10.423484 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12761 11:46:10.423591 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12762 11:46:10.423690 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12763 11:46:10.423974 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12764 11:46:10.424065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12765 11:46:10.428543 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12766 11:46:10.428717 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12767 11:46:10.429017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12768 11:46:10.429118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12769 11:46:10.429203 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12770 11:46:10.429285 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12771 11:46:10.429382 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12772 11:46:10.429466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12773 11:46:10.429563 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12774 11:46:10.429849 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12775 11:46:10.429960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12776 11:46:10.430048 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12777 11:46:10.430153 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12778 11:46:10.430269 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12779 11:46:10.430553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12780 11:46:10.430936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12781 11:46:10.431027 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12782 11:46:10.431110 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12783 11:46:10.431193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12784 11:46:10.431462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12785 11:46:10.431575 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12786 11:46:10.431663 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12787 11:46:10.431746 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12788 11:46:10.431844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12789 11:46:10.431941 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12790 11:46:10.432227 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12791 11:46:10.436562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12792 11:46:10.436738 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12793 11:46:10.436833 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12794 11:46:10.437107 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12795 11:46:10.437208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12796 11:46:10.437294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12797 11:46:10.437401 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12798 11:46:10.437491 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12799 11:46:10.437579 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12800 11:46:10.437676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12801 11:46:10.437746 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12802 11:46:10.438037 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12803 11:46:10.438135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12804 11:46:10.438208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12805 11:46:10.438468 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12806 11:46:10.438554 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12807 11:46:10.438618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12808 11:46:10.438680 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12809 11:46:10.438933 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12810 11:46:10.439003 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12811 11:46:10.439082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12812 11:46:10.439147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12813 11:46:10.439212 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12814 11:46:10.439301 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12815 11:46:10.439378 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12816 11:46:10.439464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12817 11:46:10.439748 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12818 11:46:10.439853 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12819 11:46:10.439962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12820 11:46:10.440072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12821 11:46:10.444362 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12822 11:46:10.444735 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12823 11:46:10.444830 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12824 11:46:10.444923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12825 11:46:10.445039 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12826 11:46:10.445128 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12827 11:46:10.445208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12828 11:46:10.445300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12829 11:46:10.445382 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12830 11:46:10.445478 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12831 11:46:10.445769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12832 11:46:10.445863 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12833 11:46:10.445948 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12834 11:46:10.446040 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12835 11:46:10.446332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12836 11:46:10.446438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12837 11:46:10.446526 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12838 11:46:10.446619 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12839 11:46:10.446718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12840 11:46:10.446992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12841 11:46:10.447112 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12842 11:46:10.447218 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12843 11:46:10.447318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12844 11:46:10.447613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12845 11:46:10.447916 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12846 11:46:10.448017 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12847 11:46:10.448102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12848 11:46:10.452388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12849 11:46:10.452727 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12850 11:46:10.452820 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12851 11:46:10.452906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12852 11:46:10.453008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12853 11:46:10.453289 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12854 11:46:10.453382 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12855 11:46:10.453483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12856 11:46:10.453582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12857 11:46:10.453706 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12858 11:46:10.454040 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12859 11:46:10.454132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12860 11:46:10.454234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12861 11:46:10.454520 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12862 11:46:10.454635 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12863 11:46:10.454736 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12864 11:46:10.455032 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12865 11:46:10.455149 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12866 11:46:10.455251 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12867 11:46:10.455522 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12868 11:46:10.455636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12869 11:46:10.455739 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12870 11:46:10.456032 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12871 11:46:10.456151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12872 11:46:10.460336 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12873 11:46:10.460670 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12874 11:46:10.460772 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12875 11:46:10.460874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12876 11:46:10.461164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12877 11:46:10.461263 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12878 11:46:10.477040 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12879 11:46:10.477264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12880 11:46:10.477353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12881 11:46:10.477692 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12882 11:46:10.477830 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12883 11:46:10.477955 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12884 11:46:10.478054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12885 11:46:10.478161 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12886 11:46:10.478249 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12887 11:46:10.478349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12888 11:46:10.478450 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12889 11:46:10.478792 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12890 11:46:10.478968 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12891 11:46:10.479131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12892 11:46:10.479266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12893 11:46:10.479418 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12894 11:46:10.479550 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12895 11:46:10.479676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12896 11:46:10.479826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12897 11:46:10.479956 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12898 11:46:10.480084 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12899 11:46:10.480231 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12900 11:46:10.480356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12901 11:46:10.484360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12902 11:46:10.484791 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12903 11:46:10.484985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12904 11:46:10.485147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12905 11:46:10.485291 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12906 11:46:10.485453 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12907 11:46:10.485610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12908 11:46:10.485783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12909 11:46:10.485948 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12910 11:46:10.486111 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12911 11:46:10.486305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12912 11:46:10.486471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12913 11:46:10.486635 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12914 11:46:10.486802 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12915 11:46:10.486966 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12916 11:46:10.487165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12917 11:46:10.487336 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12918 11:46:10.487503 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12919 11:46:10.487672 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12920 11:46:10.487835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12921 11:46:10.487999 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12922 11:46:10.488159 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12923 11:46:10.488280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12924 11:46:10.488426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12925 11:46:10.488549 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12926 11:46:10.488664 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12927 11:46:10.488780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12928 11:46:10.488895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12929 11:46:10.489009 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12930 11:46:10.489124 arm64_sve-ptrace pass
12931 11:46:10.489237 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12932 11:46:10.492314 arm64_sve-probe-vls_All_vector_lengths_valid pass
12933 11:46:10.492670 arm64_sve-probe-vls pass
12934 11:46:10.492814 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12935 11:46:10.492943 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
12936 11:46:10.493091 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
12937 11:46:10.493186 arm64_vec-syscfg_SVE_current_VL_is_64 pass
12938 11:46:10.493273 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
12939 11:46:10.493360 arm64_vec-syscfg_SVE_prctl_set_min_max pass
12940 11:46:10.493460 arm64_vec-syscfg_SVE_vector_length_used_default pass
12941 11:46:10.493543 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
12942 11:46:10.493626 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
12943 11:46:10.493732 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
12944 11:46:10.493818 arm64_vec-syscfg_SME_default_vector_length_32 pass
12945 11:46:10.493917 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
12946 11:46:10.494015 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
12947 11:46:10.494352 arm64_vec-syscfg_SME_current_VL_is_32 pass
12948 11:46:10.494471 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
12949 11:46:10.494560 arm64_vec-syscfg_SME_prctl_set_min_max pass
12950 11:46:10.494657 arm64_vec-syscfg_SME_vector_length_used_default pass
12951 11:46:10.494756 arm64_vec-syscfg_SME_vector_length_was_inherited pass
12952 11:46:10.494893 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
12953 11:46:10.495256 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
12954 11:46:10.495357 arm64_vec-syscfg pass
12955 11:46:10.495439 arm64_za-fork_fork_test pass
12956 11:46:10.495541 arm64_za-fork pass
12957 11:46:10.495626 arm64_za-ptrace_Set_VL_16 pass
12958 11:46:10.495723 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
12959 11:46:10.495822 arm64_za-ptrace_Data_match_for_VL_16 pass
12960 11:46:10.495908 arm64_za-ptrace_Set_VL_32 pass
12961 11:46:10.496004 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
12962 11:46:10.496088 arm64_za-ptrace_Data_match_for_VL_32 pass
12963 11:46:10.496170 arm64_za-ptrace_Set_VL_48 pass
12964 11:46:10.500342 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
12965 11:46:10.500698 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
12966 11:46:10.500805 arm64_za-ptrace_Set_VL_64 pass
12967 11:46:10.500896 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
12968 11:46:10.500998 arm64_za-ptrace_Data_match_for_VL_64 pass
12969 11:46:10.501085 arm64_za-ptrace_Set_VL_80 pass
12970 11:46:10.501170 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
12971 11:46:10.501312 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
12972 11:46:10.501404 arm64_za-ptrace_Set_VL_96 pass
12973 11:46:10.501488 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
12974 11:46:10.501586 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
12975 11:46:10.501680 arm64_za-ptrace_Set_VL_112 pass
12976 11:46:10.501764 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
12977 11:46:10.501861 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
12978 11:46:10.501948 arm64_za-ptrace_Set_VL_128 pass
12979 11:46:10.502031 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
12980 11:46:10.502130 arm64_za-ptrace_Data_match_for_VL_128 pass
12981 11:46:10.502219 arm64_za-ptrace_Set_VL_144 pass
12982 11:46:10.502315 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
12983 11:46:10.502414 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
12984 11:46:10.502512 arm64_za-ptrace_Set_VL_160 pass
12985 11:46:10.502595 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
12986 11:46:10.502691 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
12987 11:46:10.502786 arm64_za-ptrace_Set_VL_176 pass
12988 11:46:10.502884 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
12989 11:46:10.502984 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
12990 11:46:10.512317 arm64_za-ptrace_Set_VL_192 pass
12991 11:46:10.512739 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
12992 11:46:10.512846 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
12993 11:46:10.512933 arm64_za-ptrace_Set_VL_208 pass
12994 11:46:10.513017 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
12995 11:46:10.513117 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
12996 11:46:10.513204 arm64_za-ptrace_Set_VL_224 pass
12997 11:46:10.513291 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
12998 11:46:10.513375 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
12999 11:46:10.513474 arm64_za-ptrace_Set_VL_240 pass
13000 11:46:10.513561 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
13001 11:46:10.513829 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
13002 11:46:10.513939 arm64_za-ptrace_Set_VL_256 pass
13003 11:46:10.514046 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
13004 11:46:10.514134 arm64_za-ptrace_Data_match_for_VL_256 pass
13005 11:46:10.514220 arm64_za-ptrace_Set_VL_272 pass
13006 11:46:10.514310 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
13007 11:46:10.514396 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
13008 11:46:10.514498 arm64_za-ptrace_Set_VL_288 pass
13009 11:46:10.514588 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
13010 11:46:10.514675 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
13011 11:46:10.514757 arm64_za-ptrace_Set_VL_304 pass
13012 11:46:10.514839 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
13013 11:46:10.514937 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
13014 11:46:10.515023 arm64_za-ptrace_Set_VL_320 pass
13015 11:46:10.515106 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
13016 11:46:10.515204 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
13017 11:46:10.515289 arm64_za-ptrace_Set_VL_336 pass
13018 11:46:10.515372 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
13019 11:46:10.515470 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
13020 11:46:10.515556 arm64_za-ptrace_Set_VL_352 pass
13021 11:46:10.515638 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
13022 11:46:10.515736 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
13023 11:46:10.515822 arm64_za-ptrace_Set_VL_368 pass
13024 11:46:10.515903 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
13025 11:46:10.516000 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
13026 11:46:10.516084 arm64_za-ptrace_Set_VL_384 pass
13027 11:46:10.520267 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
13028 11:46:10.520612 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
13029 11:46:10.520740 arm64_za-ptrace_Set_VL_400 pass
13030 11:46:10.520849 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
13031 11:46:10.520955 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
13032 11:46:10.521046 arm64_za-ptrace_Set_VL_416 pass
13033 11:46:10.521133 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
13034 11:46:10.521235 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
13035 11:46:10.521324 arm64_za-ptrace_Set_VL_432 pass
13036 11:46:10.521427 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
13037 11:46:10.521515 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
13038 11:46:10.521613 arm64_za-ptrace_Set_VL_448 pass
13039 11:46:10.521721 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
13040 11:46:10.522126 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
13041 11:46:10.522238 arm64_za-ptrace_Set_VL_464 pass
13042 11:46:10.522325 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
13043 11:46:10.522423 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
13044 11:46:10.522510 arm64_za-ptrace_Set_VL_480 pass
13045 11:46:10.522591 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
13046 11:46:10.522687 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
13047 11:46:10.522772 arm64_za-ptrace_Set_VL_496 pass
13048 11:46:10.522871 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
13049 11:46:10.537896 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
13050 11:46:10.538130 arm64_za-ptrace_Set_VL_512 pass
13051 11:46:10.538435 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
13052 11:46:10.538540 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
13053 11:46:10.538628 arm64_za-ptrace_Set_VL_528 pass
13054 11:46:10.538715 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
13055 11:46:10.538801 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
13056 11:46:10.538884 arm64_za-ptrace_Set_VL_544 pass
13057 11:46:10.538982 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
13058 11:46:10.539066 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
13059 11:46:10.539148 arm64_za-ptrace_Set_VL_560 pass
13060 11:46:10.539228 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
13061 11:46:10.539311 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
13062 11:46:10.539411 arm64_za-ptrace_Set_VL_576 pass
13063 11:46:10.539497 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
13064 11:46:10.539579 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
13065 11:46:10.539663 arm64_za-ptrace_Set_VL_592 pass
13066 11:46:10.539762 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
13067 11:46:10.539848 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
13068 11:46:10.539932 arm64_za-ptrace_Set_VL_608 pass
13069 11:46:10.540032 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
13070 11:46:10.540117 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
13071 11:46:10.540202 arm64_za-ptrace_Set_VL_624 pass
13072 11:46:10.540287 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
13073 11:46:10.540387 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
13074 11:46:10.540474 arm64_za-ptrace_Set_VL_640 pass
13075 11:46:10.540576 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
13076 11:46:10.540682 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
13077 11:46:10.540771 arm64_za-ptrace_Set_VL_656 pass
13078 11:46:10.540867 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
13079 11:46:10.540967 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
13080 11:46:10.541068 arm64_za-ptrace_Set_VL_672 pass
13081 11:46:10.541165 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
13082 11:46:10.541266 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
13083 11:46:10.541365 arm64_za-ptrace_Set_VL_688 pass
13084 11:46:10.541926 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
13085 11:46:10.542028 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
13086 11:46:10.542116 arm64_za-ptrace_Set_VL_704 pass
13087 11:46:10.542203 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
13088 11:46:10.542286 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
13089 11:46:10.542384 arm64_za-ptrace_Set_VL_720 pass
13090 11:46:10.542468 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
13091 11:46:10.542548 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
13092 11:46:10.542628 arm64_za-ptrace_Set_VL_736 pass
13093 11:46:10.542725 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
13094 11:46:10.542811 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
13095 11:46:10.542890 arm64_za-ptrace_Set_VL_752 pass
13096 11:46:10.542982 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
13097 11:46:10.543304 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
13098 11:46:10.543410 arm64_za-ptrace_Set_VL_768 pass
13099 11:46:10.543495 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
13100 11:46:10.543578 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
13101 11:46:10.543677 arm64_za-ptrace_Set_VL_784 pass
13102 11:46:10.543762 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
13103 11:46:10.543845 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
13104 11:46:10.543929 arm64_za-ptrace_Set_VL_800 pass
13105 11:46:10.544028 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
13106 11:46:10.544115 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
13107 11:46:10.544201 arm64_za-ptrace_Set_VL_816 pass
13108 11:46:10.548318 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
13109 11:46:10.548807 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
13110 11:46:10.548970 arm64_za-ptrace_Set_VL_832 pass
13111 11:46:10.549101 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
13112 11:46:10.549264 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
13113 11:46:10.549389 arm64_za-ptrace_Set_VL_848 pass
13114 11:46:10.549508 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
13115 11:46:10.549869 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
13116 11:46:10.550032 arm64_za-ptrace_Set_VL_864 pass
13117 11:46:10.550195 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
13118 11:46:10.550334 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
13119 11:46:10.550471 arm64_za-ptrace_Set_VL_880 pass
13120 11:46:10.550612 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
13121 11:46:10.550751 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
13122 11:46:10.550881 arm64_za-ptrace_Set_VL_896 pass
13123 11:46:10.551023 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
13124 11:46:10.551160 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
13125 11:46:10.551299 arm64_za-ptrace_Set_VL_912 pass
13126 11:46:10.551436 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
13127 11:46:10.551585 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
13128 11:46:10.551971 arm64_za-ptrace_Set_VL_928 pass
13129 11:46:10.552127 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
13130 11:46:10.552250 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
13131 11:46:10.552370 arm64_za-ptrace_Set_VL_944 pass
13132 11:46:10.552489 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
13133 11:46:10.552606 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
13134 11:46:10.552725 arm64_za-ptrace_Set_VL_960 pass
13135 11:46:10.552890 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
13136 11:46:10.553049 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
13137 11:46:10.553180 arm64_za-ptrace_Set_VL_976 pass
13138 11:46:10.553301 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
13139 11:46:10.553418 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
13140 11:46:10.553535 arm64_za-ptrace_Set_VL_992 pass
13141 11:46:10.553666 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
13142 11:46:10.553837 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
13143 11:46:10.553965 arm64_za-ptrace_Set_VL_1008 pass
13144 11:46:10.554082 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
13145 11:46:10.554198 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
13146 11:46:10.554316 arm64_za-ptrace_Set_VL_1024 pass
13147 11:46:10.554434 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
13148 11:46:10.554552 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
13149 11:46:10.554668 arm64_za-ptrace_Set_VL_1040 pass
13150 11:46:10.554786 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
13151 11:46:10.554904 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
13152 11:46:10.555021 arm64_za-ptrace_Set_VL_1056 pass
13153 11:46:10.555136 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
13154 11:46:10.555252 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
13155 11:46:10.555372 arm64_za-ptrace_Set_VL_1072 pass
13156 11:46:10.555519 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
13157 11:46:10.556337 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
13158 11:46:10.556745 arm64_za-ptrace_Set_VL_1088 pass
13159 11:46:10.556850 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
13160 11:46:10.556939 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
13161 11:46:10.557024 arm64_za-ptrace_Set_VL_1104 pass
13162 11:46:10.557108 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
13163 11:46:10.557208 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
13164 11:46:10.557298 arm64_za-ptrace_Set_VL_1120 pass
13165 11:46:10.557387 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
13166 11:46:10.557486 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
13167 11:46:10.557573 arm64_za-ptrace_Set_VL_1136 pass
13168 11:46:10.557681 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
13169 11:46:10.557782 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
13170 11:46:10.557882 arm64_za-ptrace_Set_VL_1152 pass
13171 11:46:10.557982 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
13172 11:46:10.558081 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
13173 11:46:10.558389 arm64_za-ptrace_Set_VL_1168 pass
13174 11:46:10.558492 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
13175 11:46:10.558592 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
13176 11:46:10.558690 arm64_za-ptrace_Set_VL_1184 pass
13177 11:46:10.558787 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
13178 11:46:10.558887 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
13179 11:46:10.559193 arm64_za-ptrace_Set_VL_1200 pass
13180 11:46:10.559298 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13181 11:46:10.559400 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13182 11:46:10.559488 arm64_za-ptrace_Set_VL_1216 pass
13183 11:46:10.559583 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13184 11:46:10.559681 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13185 11:46:10.559975 arm64_za-ptrace_Set_VL_1232 pass
13186 11:46:10.560078 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13187 11:46:10.564296 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13188 11:46:10.564794 arm64_za-ptrace_Set_VL_1248 pass
13189 11:46:10.565001 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13190 11:46:10.565198 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13191 11:46:10.565428 arm64_za-ptrace_Set_VL_1264 pass
13192 11:46:10.565642 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13193 11:46:10.565875 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13194 11:46:10.566049 arm64_za-ptrace_Set_VL_1280 pass
13195 11:46:10.566204 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13196 11:46:10.566370 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13197 11:46:10.566532 arm64_za-ptrace_Set_VL_1296 pass
13198 11:46:10.566697 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13199 11:46:10.566860 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13200 11:46:10.567024 arm64_za-ptrace_Set_VL_1312 pass
13201 11:46:10.567188 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13202 11:46:10.567351 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13203 11:46:10.567553 arm64_za-ptrace_Set_VL_1328 pass
13204 11:46:10.567729 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13205 11:46:10.567894 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13206 11:46:10.568049 arm64_za-ptrace_Set_VL_1344 pass
13207 11:46:10.568171 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13208 11:46:10.568287 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13209 11:46:10.568404 arm64_za-ptrace_Set_VL_1360 pass
13210 11:46:10.568518 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13211 11:46:10.568632 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13212 11:46:10.568747 arm64_za-ptrace_Set_VL_1376 pass
13213 11:46:10.568862 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13214 11:46:10.568976 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13215 11:46:10.569120 arm64_za-ptrace_Set_VL_1392 pass
13216 11:46:10.569242 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13217 11:46:10.569363 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13218 11:46:10.569479 arm64_za-ptrace_Set_VL_1408 pass
13219 11:46:10.572454 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13220 11:46:10.572588 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13221 11:46:10.572880 arm64_za-ptrace_Set_VL_1424 pass
13222 11:46:10.573025 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13223 11:46:10.573249 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13224 11:46:10.573559 arm64_za-ptrace_Set_VL_1440 pass
13225 11:46:10.573706 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13226 11:46:10.573973 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13227 11:46:10.574098 arm64_za-ptrace_Set_VL_1456 pass
13228 11:46:10.574191 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13229 11:46:10.574276 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13230 11:46:10.574395 arm64_za-ptrace_Set_VL_1472 pass
13231 11:46:10.574585 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13232 11:46:10.574791 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13233 11:46:10.574931 arm64_za-ptrace_Set_VL_1488 pass
13234 11:46:10.575021 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13235 11:46:10.575105 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13236 11:46:10.575189 arm64_za-ptrace_Set_VL_1504 pass
13237 11:46:10.575273 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13238 11:46:10.575357 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13239 11:46:10.575439 arm64_za-ptrace_Set_VL_1520 pass
13240 11:46:10.575521 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13241 11:46:10.575599 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13242 11:46:10.575699 arm64_za-ptrace_Set_VL_1536 pass
13243 11:46:10.575785 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13244 11:46:10.595318 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13245 11:46:10.595576 arm64_za-ptrace_Set_VL_1552 pass
13246 11:46:10.595886 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13247 11:46:10.595992 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13248 11:46:10.596082 arm64_za-ptrace_Set_VL_1568 pass
13249 11:46:10.596167 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13250 11:46:10.597996 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13251 11:46:10.598280 arm64_za-ptrace_Set_VL_1584 pass
13252 11:46:10.598488 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13253 11:46:10.598683 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13254 11:46:10.598861 arm64_za-ptrace_Set_VL_1600 pass
13255 11:46:10.599008 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13256 11:46:10.599152 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13257 11:46:10.599294 arm64_za-ptrace_Set_VL_1616 pass
13258 11:46:10.599437 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13259 11:46:10.599578 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13260 11:46:10.599719 arm64_za-ptrace_Set_VL_1632 pass
13261 11:46:10.599861 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13262 11:46:10.600004 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13263 11:46:10.600157 arm64_za-ptrace_Set_VL_1648 pass
13264 11:46:10.600351 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13265 11:46:10.600474 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13266 11:46:10.600593 arm64_za-ptrace_Set_VL_1664 pass
13267 11:46:10.600713 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13268 11:46:10.600842 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13269 11:46:10.600971 arm64_za-ptrace_Set_VL_1680 pass
13270 11:46:10.601102 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13271 11:46:10.601234 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13272 11:46:10.601369 arm64_za-ptrace_Set_VL_1696 pass
13273 11:46:10.601505 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13274 11:46:10.601639 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13275 11:46:10.602017 arm64_za-ptrace_Set_VL_1712 pass
13276 11:46:10.602168 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13277 11:46:10.602307 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13278 11:46:10.602431 arm64_za-ptrace_Set_VL_1728 pass
13279 11:46:10.602523 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13280 11:46:10.602614 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13281 11:46:10.602705 arm64_za-ptrace_Set_VL_1744 pass
13282 11:46:10.602797 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13283 11:46:10.602887 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13284 11:46:10.602979 arm64_za-ptrace_Set_VL_1760 pass
13285 11:46:10.603072 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13286 11:46:10.603163 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13287 11:46:10.603255 arm64_za-ptrace_Set_VL_1776 pass
13288 11:46:10.603346 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13289 11:46:10.603437 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13290 11:46:10.603529 arm64_za-ptrace_Set_VL_1792 pass
13291 11:46:10.603619 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13292 11:46:10.603710 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13293 11:46:10.603802 arm64_za-ptrace_Set_VL_1808 pass
13294 11:46:10.603893 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13295 11:46:10.603983 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13296 11:46:10.604384 arm64_za-ptrace_Set_VL_1824 pass
13297 11:46:10.604686 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13298 11:46:10.604792 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13299 11:46:10.604881 arm64_za-ptrace_Set_VL_1840 pass
13300 11:46:10.604984 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13301 11:46:10.605075 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13302 11:46:10.605162 arm64_za-ptrace_Set_VL_1856 pass
13303 11:46:10.605262 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13304 11:46:10.605349 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13305 11:46:10.605432 arm64_za-ptrace_Set_VL_1872 pass
13306 11:46:10.605529 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13307 11:46:10.605618 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13308 11:46:10.605712 arm64_za-ptrace_Set_VL_1888 pass
13309 11:46:10.605814 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13310 11:46:10.605903 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13311 11:46:10.605991 arm64_za-ptrace_Set_VL_1904 pass
13312 11:46:10.606097 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13313 11:46:10.606204 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13314 11:46:10.606312 arm64_za-ptrace_Set_VL_1920 pass
13315 11:46:10.606402 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13316 11:46:10.606501 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13317 11:46:10.606911 arm64_za-ptrace_Set_VL_1936 pass
13318 11:46:10.607017 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13319 11:46:10.607107 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13320 11:46:10.607193 arm64_za-ptrace_Set_VL_1952 pass
13321 11:46:10.607295 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13322 11:46:10.607382 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13323 11:46:10.607475 arm64_za-ptrace_Set_VL_1968 pass
13324 11:46:10.607563 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13325 11:46:10.607667 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13326 11:46:10.607755 arm64_za-ptrace_Set_VL_1984 pass
13327 11:46:10.607842 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13328 11:46:10.607928 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13329 11:46:10.608032 arm64_za-ptrace_Set_VL_2000 pass
13330 11:46:10.608120 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13331 11:46:10.608205 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13332 11:46:10.608292 arm64_za-ptrace_Set_VL_2016 pass
13333 11:46:10.612296 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13334 11:46:10.612686 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13335 11:46:10.612883 arm64_za-ptrace_Set_VL_2032 pass
13336 11:46:10.613057 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13337 11:46:10.613237 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13338 11:46:10.613370 arm64_za-ptrace_Set_VL_2048 pass
13339 11:46:10.613496 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13340 11:46:10.613619 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13341 11:46:10.613830 arm64_za-ptrace_Set_VL_2064 pass
13342 11:46:10.614004 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13343 11:46:10.614148 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13344 11:46:10.614329 arm64_za-ptrace_Set_VL_2080 pass
13345 11:46:10.614470 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13346 11:46:10.614614 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13347 11:46:10.614757 arm64_za-ptrace_Set_VL_2096 pass
13348 11:46:10.614900 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13349 11:46:10.615042 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13350 11:46:10.615185 arm64_za-ptrace_Set_VL_2112 pass
13351 11:46:10.615326 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13352 11:46:10.615469 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13353 11:46:10.615612 arm64_za-ptrace_Set_VL_2128 pass
13354 11:46:10.615755 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13355 11:46:10.615937 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13356 11:46:10.616072 arm64_za-ptrace_Set_VL_2144 pass
13357 11:46:10.616213 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13358 11:46:10.616356 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13359 11:46:10.616498 arm64_za-ptrace_Set_VL_2160 pass
13360 11:46:10.616640 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13361 11:46:10.616783 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13362 11:46:10.616925 arm64_za-ptrace_Set_VL_2176 pass
13363 11:46:10.617066 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13364 11:46:10.617208 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13365 11:46:10.617350 arm64_za-ptrace_Set_VL_2192 pass
13366 11:46:10.617491 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13367 11:46:10.617633 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13368 11:46:10.617787 arm64_za-ptrace_Set_VL_2208 pass
13369 11:46:10.617927 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13370 11:46:10.618103 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13371 11:46:10.620378 arm64_za-ptrace_Set_VL_2224 pass
13372 11:46:10.620813 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13373 11:46:10.620996 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13374 11:46:10.621170 arm64_za-ptrace_Set_VL_2240 pass
13375 11:46:10.621333 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13376 11:46:10.621501 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13377 11:46:10.621712 arm64_za-ptrace_Set_VL_2256 pass
13378 11:46:10.621886 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13379 11:46:10.622056 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13380 11:46:10.622226 arm64_za-ptrace_Set_VL_2272 pass
13381 11:46:10.622390 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13382 11:46:10.622548 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13383 11:46:10.622717 arm64_za-ptrace_Set_VL_2288 pass
13384 11:46:10.622884 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13385 11:46:10.623087 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13386 11:46:10.623256 arm64_za-ptrace_Set_VL_2304 pass
13387 11:46:10.623423 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13388 11:46:10.623585 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13389 11:46:10.623747 arm64_za-ptrace_Set_VL_2320 pass
13390 11:46:10.623909 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13391 11:46:10.624071 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13392 11:46:10.624214 arm64_za-ptrace_Set_VL_2336 pass
13393 11:46:10.624334 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13394 11:46:10.624450 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13395 11:46:10.624565 arm64_za-ptrace_Set_VL_2352 pass
13396 11:46:10.624712 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13397 11:46:10.624838 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13398 11:46:10.624955 arm64_za-ptrace_Set_VL_2368 pass
13399 11:46:10.625073 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13400 11:46:10.625190 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13401 11:46:10.625307 arm64_za-ptrace_Set_VL_2384 pass
13402 11:46:10.625423 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13403 11:46:10.625540 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13404 11:46:10.625668 arm64_za-ptrace_Set_VL_2400 pass
13405 11:46:10.625788 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13406 11:46:10.625905 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13407 11:46:10.626022 arm64_za-ptrace_Set_VL_2416 pass
13408 11:46:10.628303 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13409 11:46:10.628740 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13410 11:46:10.628946 arm64_za-ptrace_Set_VL_2432 pass
13411 11:46:10.629127 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13412 11:46:10.629305 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13413 11:46:10.629528 arm64_za-ptrace_Set_VL_2448 pass
13414 11:46:10.629741 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13415 11:46:10.629920 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13416 11:46:10.630131 arm64_za-ptrace_Set_VL_2464 pass
13417 11:46:10.630362 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13418 11:46:10.630570 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13419 11:46:10.630790 arm64_za-ptrace_Set_VL_2480 pass
13420 11:46:10.631062 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13421 11:46:10.631284 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13422 11:46:10.631452 arm64_za-ptrace_Set_VL_2496 pass
13423 11:46:10.631577 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13424 11:46:10.631714 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13425 11:46:10.631922 arm64_za-ptrace_Set_VL_2512 pass
13426 11:46:10.632058 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13427 11:46:10.632176 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13428 11:46:10.632293 arm64_za-ptrace_Set_VL_2528 pass
13429 11:46:10.632408 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13430 11:46:10.632527 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13431 11:46:10.632643 arm64_za-ptrace_Set_VL_2544 pass
13432 11:46:10.632758 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13433 11:46:10.632874 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13434 11:46:10.632990 arm64_za-ptrace_Set_VL_2560 pass
13435 11:46:10.633161 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13436 11:46:10.633322 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13437 11:46:10.652451 arm64_za-ptrace_Set_VL_2576 pass
13438 11:46:10.652974 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13439 11:46:10.653082 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13440 11:46:10.653172 arm64_za-ptrace_Set_VL_2592 pass
13441 11:46:10.653261 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13442 11:46:10.653365 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13443 11:46:10.653456 arm64_za-ptrace_Set_VL_2608 pass
13444 11:46:10.653541 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13445 11:46:10.653626 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13446 11:46:10.653718 arm64_za-ptrace_Set_VL_2624 pass
13447 11:46:10.653819 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13448 11:46:10.653906 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13449 11:46:10.653986 arm64_za-ptrace_Set_VL_2640 pass
13450 11:46:10.654086 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13451 11:46:10.654172 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13452 11:46:10.654255 arm64_za-ptrace_Set_VL_2656 pass
13453 11:46:10.654337 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13454 11:46:10.654418 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13455 11:46:10.654523 arm64_za-ptrace_Set_VL_2672 pass
13456 11:46:10.654609 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13457 11:46:10.654691 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13458 11:46:10.654773 arm64_za-ptrace_Set_VL_2688 pass
13459 11:46:10.654854 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13460 11:46:10.654951 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13461 11:46:10.655037 arm64_za-ptrace_Set_VL_2704 pass
13462 11:46:10.655119 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13463 11:46:10.655215 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13464 11:46:10.655298 arm64_za-ptrace_Set_VL_2720 pass
13465 11:46:10.655379 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13466 11:46:10.655478 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13467 11:46:10.655562 arm64_za-ptrace_Set_VL_2736 pass
13468 11:46:10.655643 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13469 11:46:10.655728 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13470 11:46:10.655810 arm64_za-ptrace_Set_VL_2752 pass
13471 11:46:10.655909 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13472 11:46:10.655998 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13473 11:46:10.656085 arm64_za-ptrace_Set_VL_2768 pass
13474 11:46:10.656170 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13475 11:46:10.656255 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13476 11:46:10.656356 arm64_za-ptrace_Set_VL_2784 pass
13477 11:46:10.660295 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13478 11:46:10.660726 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13479 11:46:10.660904 arm64_za-ptrace_Set_VL_2800 pass
13480 11:46:10.661100 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13481 11:46:10.661286 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13482 11:46:10.661533 arm64_za-ptrace_Set_VL_2816 pass
13483 11:46:10.661710 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13484 11:46:10.661860 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13485 11:46:10.662004 arm64_za-ptrace_Set_VL_2832 pass
13486 11:46:10.662145 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13487 11:46:10.662288 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13488 11:46:10.662432 arm64_za-ptrace_Set_VL_2848 pass
13489 11:46:10.662613 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13490 11:46:10.662750 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13491 11:46:10.662892 arm64_za-ptrace_Set_VL_2864 pass
13492 11:46:10.663034 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13493 11:46:10.663176 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13494 11:46:10.663317 arm64_za-ptrace_Set_VL_2880 pass
13495 11:46:10.663459 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13496 11:46:10.663600 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13497 11:46:10.663743 arm64_za-ptrace_Set_VL_2896 pass
13498 11:46:10.663884 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13499 11:46:10.664066 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13500 11:46:10.664203 arm64_za-ptrace_Set_VL_2912 pass
13501 11:46:10.664346 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13502 11:46:10.664487 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13503 11:46:10.664628 arm64_za-ptrace_Set_VL_2928 pass
13504 11:46:10.664770 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13505 11:46:10.664912 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13506 11:46:10.665054 arm64_za-ptrace_Set_VL_2944 pass
13507 11:46:10.665195 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13508 11:46:10.665335 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13509 11:46:10.665478 arm64_za-ptrace_Set_VL_2960 pass
13510 11:46:10.665620 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13511 11:46:10.665772 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13512 11:46:10.665915 arm64_za-ptrace_Set_VL_2976 pass
13513 11:46:10.666058 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13514 11:46:10.668297 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13515 11:46:10.668732 arm64_za-ptrace_Set_VL_2992 pass
13516 11:46:10.668925 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13517 11:46:10.669054 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13518 11:46:10.669172 arm64_za-ptrace_Set_VL_3008 pass
13519 11:46:10.669316 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13520 11:46:10.669440 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13521 11:46:10.669560 arm64_za-ptrace_Set_VL_3024 pass
13522 11:46:10.669690 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13523 11:46:10.669809 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13524 11:46:10.669924 arm64_za-ptrace_Set_VL_3040 pass
13525 11:46:10.670037 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13526 11:46:10.670150 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13527 11:46:10.670290 arm64_za-ptrace_Set_VL_3056 pass
13528 11:46:10.670409 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13529 11:46:10.670527 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13530 11:46:10.670642 arm64_za-ptrace_Set_VL_3072 pass
13531 11:46:10.670756 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13532 11:46:10.670869 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13533 11:46:10.670982 arm64_za-ptrace_Set_VL_3088 pass
13534 11:46:10.671095 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13535 11:46:10.671208 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13536 11:46:10.671321 arm64_za-ptrace_Set_VL_3104 pass
13537 11:46:10.671436 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13538 11:46:10.671551 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13539 11:46:10.671695 arm64_za-ptrace_Set_VL_3120 pass
13540 11:46:10.671815 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13541 11:46:10.671931 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13542 11:46:10.672045 arm64_za-ptrace_Set_VL_3136 pass
13543 11:46:10.672159 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13544 11:46:10.672272 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13545 11:46:10.672386 arm64_za-ptrace_Set_VL_3152 pass
13546 11:46:10.672499 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13547 11:46:10.672614 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13548 11:46:10.672727 arm64_za-ptrace_Set_VL_3168 pass
13549 11:46:10.672840 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13550 11:46:10.672954 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13551 11:46:10.673067 arm64_za-ptrace_Set_VL_3184 pass
13552 11:46:10.673180 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13553 11:46:10.673293 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13554 11:46:10.673406 arm64_za-ptrace_Set_VL_3200 pass
13555 11:46:10.673521 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13556 11:46:10.673635 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13557 11:46:10.673784 arm64_za-ptrace_Set_VL_3216 pass
13558 11:46:10.673903 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13559 11:46:10.674018 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13560 11:46:10.674339 arm64_za-ptrace_Set_VL_3232 pass
13561 11:46:10.674465 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13562 11:46:10.676240 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13563 11:46:10.676568 arm64_za-ptrace_Set_VL_3248 pass
13564 11:46:10.676691 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13565 11:46:10.676808 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13566 11:46:10.676923 arm64_za-ptrace_Set_VL_3264 pass
13567 11:46:10.677060 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13568 11:46:10.677179 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13569 11:46:10.677296 arm64_za-ptrace_Set_VL_3280 pass
13570 11:46:10.677410 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13571 11:46:10.677525 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13572 11:46:10.677641 arm64_za-ptrace_Set_VL_3296 pass
13573 11:46:10.677795 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13574 11:46:10.677920 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13575 11:46:10.678037 arm64_za-ptrace_Set_VL_3312 pass
13576 11:46:10.678153 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13577 11:46:10.678324 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13578 11:46:10.678451 arm64_za-ptrace_Set_VL_3328 pass
13579 11:46:10.678567 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13580 11:46:10.678682 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13581 11:46:10.678796 arm64_za-ptrace_Set_VL_3344 pass
13582 11:46:10.678942 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13583 11:46:10.679065 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13584 11:46:10.679181 arm64_za-ptrace_Set_VL_3360 pass
13585 11:46:10.679296 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13586 11:46:10.679410 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13587 11:46:10.679524 arm64_za-ptrace_Set_VL_3376 pass
13588 11:46:10.679638 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13589 11:46:10.679752 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13590 11:46:10.679865 arm64_za-ptrace_Set_VL_3392 pass
13591 11:46:10.679979 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13592 11:46:10.680094 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13593 11:46:10.680208 arm64_za-ptrace_Set_VL_3408 pass
13594 11:46:10.680323 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13595 11:46:10.680463 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13596 11:46:10.680586 arm64_za-ptrace_Set_VL_3424 pass
13597 11:46:10.680700 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13598 11:46:10.680814 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13599 11:46:10.680928 arm64_za-ptrace_Set_VL_3440 pass
13600 11:46:10.681041 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13601 11:46:10.681155 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13602 11:46:10.681268 arm64_za-ptrace_Set_VL_3456 pass
13603 11:46:10.681381 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13604 11:46:10.681494 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13605 11:46:10.681609 arm64_za-ptrace_Set_VL_3472 pass
13606 11:46:10.681738 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13607 11:46:10.682062 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13608 11:46:10.682185 arm64_za-ptrace_Set_VL_3488 pass
13609 11:46:10.682301 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13610 11:46:10.684311 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13611 11:46:10.684448 arm64_za-ptrace_Set_VL_3504 pass
13612 11:46:10.684764 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13613 11:46:10.684888 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13614 11:46:10.685002 arm64_za-ptrace_Set_VL_3520 pass
13615 11:46:10.685114 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13616 11:46:10.685226 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13617 11:46:10.685360 arm64_za-ptrace_Set_VL_3536 pass
13618 11:46:10.685476 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13619 11:46:10.685588 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13620 11:46:10.685722 arm64_za-ptrace_Set_VL_3552 pass
13621 11:46:10.685839 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13622 11:46:10.685953 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13623 11:46:10.686090 arm64_za-ptrace_Set_VL_3568 pass
13624 11:46:10.686209 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13625 11:46:10.686326 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13626 11:46:10.686440 arm64_za-ptrace_Set_VL_3584 pass
13627 11:46:10.686556 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13628 11:46:10.686670 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13629 11:46:10.708561 arm64_za-ptrace_Set_VL_3600 pass
13630 11:46:10.708764 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13631 11:46:10.708828 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13632 11:46:10.708888 arm64_za-ptrace_Set_VL_3616 pass
13633 11:46:10.709140 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13634 11:46:10.709204 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13635 11:46:10.709264 arm64_za-ptrace_Set_VL_3632 pass
13636 11:46:10.709322 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13637 11:46:10.709380 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13638 11:46:10.709438 arm64_za-ptrace_Set_VL_3648 pass
13639 11:46:10.709496 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13640 11:46:10.709554 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13641 11:46:10.709794 arm64_za-ptrace_Set_VL_3664 pass
13642 11:46:10.709860 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13643 11:46:10.710099 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13644 11:46:10.710163 arm64_za-ptrace_Set_VL_3680 pass
13645 11:46:10.710222 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13646 11:46:10.710282 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13647 11:46:10.710340 arm64_za-ptrace_Set_VL_3696 pass
13648 11:46:10.710399 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13649 11:46:10.710457 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13650 11:46:10.710528 arm64_za-ptrace_Set_VL_3712 pass
13651 11:46:10.710592 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13652 11:46:10.710651 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13653 11:46:10.710710 arm64_za-ptrace_Set_VL_3728 pass
13654 11:46:10.710768 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13655 11:46:10.710826 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13656 11:46:10.710884 arm64_za-ptrace_Set_VL_3744 pass
13657 11:46:10.710941 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13658 11:46:10.711012 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13659 11:46:10.711073 arm64_za-ptrace_Set_VL_3760 pass
13660 11:46:10.711131 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13661 11:46:10.711189 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13662 11:46:10.711247 arm64_za-ptrace_Set_VL_3776 pass
13663 11:46:10.711304 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13664 11:46:10.711362 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13665 11:46:10.711433 arm64_za-ptrace_Set_VL_3792 pass
13666 11:46:10.711495 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13667 11:46:10.711553 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13668 11:46:10.711612 arm64_za-ptrace_Set_VL_3808 pass
13669 11:46:10.711674 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13670 11:46:10.711744 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13671 11:46:10.711805 arm64_za-ptrace_Set_VL_3824 pass
13672 11:46:10.711863 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13673 11:46:10.711921 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13674 11:46:10.711991 arm64_za-ptrace_Set_VL_3840 pass
13675 11:46:10.712052 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13676 11:46:10.712110 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13677 11:46:10.712169 arm64_za-ptrace_Set_VL_3856 pass
13678 11:46:10.712238 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13679 11:46:10.712299 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13680 11:46:10.716440 arm64_za-ptrace_Set_VL_3872 pass
13681 11:46:10.716566 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13682 11:46:10.716841 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13683 11:46:10.716924 arm64_za-ptrace_Set_VL_3888 pass
13684 11:46:10.716986 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13685 11:46:10.717045 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13686 11:46:10.717104 arm64_za-ptrace_Set_VL_3904 pass
13687 11:46:10.717162 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13688 11:46:10.717235 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13689 11:46:10.717296 arm64_za-ptrace_Set_VL_3920 pass
13690 11:46:10.717355 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13691 11:46:10.717413 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13692 11:46:10.717483 arm64_za-ptrace_Set_VL_3936 pass
13693 11:46:10.717544 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13694 11:46:10.717603 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13695 11:46:10.717674 arm64_za-ptrace_Set_VL_3952 pass
13696 11:46:10.718278 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13697 11:46:10.718344 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13698 11:46:10.718403 arm64_za-ptrace_Set_VL_3968 pass
13699 11:46:10.718461 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13700 11:46:10.718519 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13701 11:46:10.718577 arm64_za-ptrace_Set_VL_3984 pass
13702 11:46:10.718635 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13703 11:46:10.718698 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13704 11:46:10.718756 arm64_za-ptrace_Set_VL_4000 pass
13705 11:46:10.718814 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13706 11:46:10.719063 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13707 11:46:10.719142 arm64_za-ptrace_Set_VL_4016 pass
13708 11:46:10.719203 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13709 11:46:10.719262 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13710 11:46:10.719320 arm64_za-ptrace_Set_VL_4032 pass
13711 11:46:10.719378 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13712 11:46:10.719436 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13713 11:46:10.719493 arm64_za-ptrace_Set_VL_4048 pass
13714 11:46:10.719551 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13715 11:46:10.719609 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13716 11:46:10.719667 arm64_za-ptrace_Set_VL_4064 pass
13717 11:46:10.719762 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13718 11:46:10.719847 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13719 11:46:10.719924 arm64_za-ptrace_Set_VL_4080 pass
13720 11:46:10.719998 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13721 11:46:10.720060 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13722 11:46:10.720120 arm64_za-ptrace_Set_VL_4096 pass
13723 11:46:10.720179 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13724 11:46:10.720239 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13725 11:46:10.720314 arm64_za-ptrace_Set_VL_4112 pass
13726 11:46:10.720377 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13727 11:46:10.724460 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13728 11:46:10.724873 arm64_za-ptrace_Set_VL_4128 pass
13729 11:46:10.724970 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13730 11:46:10.725039 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13731 11:46:10.725111 arm64_za-ptrace_Set_VL_4144 pass
13732 11:46:10.725215 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13733 11:46:10.725305 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13734 11:46:10.725393 arm64_za-ptrace_Set_VL_4160 pass
13735 11:46:10.725477 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13736 11:46:10.725574 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13737 11:46:10.725667 arm64_za-ptrace_Set_VL_4176 pass
13738 11:46:10.725753 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13739 11:46:10.725854 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13740 11:46:10.725940 arm64_za-ptrace_Set_VL_4192 pass
13741 11:46:10.726040 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13742 11:46:10.726141 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13743 11:46:10.726431 arm64_za-ptrace_Set_VL_4208 pass
13744 11:46:10.726510 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13745 11:46:10.726586 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13746 11:46:10.726659 arm64_za-ptrace_Set_VL_4224 pass
13747 11:46:10.726769 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13748 11:46:10.726894 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13749 11:46:10.727016 arm64_za-ptrace_Set_VL_4240 pass
13750 11:46:10.727133 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13751 11:46:10.727253 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13752 11:46:10.727365 arm64_za-ptrace_Set_VL_4256 pass
13753 11:46:10.727693 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13754 11:46:10.727792 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13755 11:46:10.727878 arm64_za-ptrace_Set_VL_4272 pass
13756 11:46:10.727970 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13757 11:46:10.728043 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13758 11:46:10.728116 arm64_za-ptrace_Set_VL_4288 pass
13759 11:46:10.732433 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13760 11:46:10.732842 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13761 11:46:10.732925 arm64_za-ptrace_Set_VL_4304 pass
13762 11:46:10.732998 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13763 11:46:10.733079 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13764 11:46:10.733153 arm64_za-ptrace_Set_VL_4320 pass
13765 11:46:10.733228 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13766 11:46:10.733318 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13767 11:46:10.733399 arm64_za-ptrace_Set_VL_4336 pass
13768 11:46:10.733493 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13769 11:46:10.733586 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13770 11:46:10.733702 arm64_za-ptrace_Set_VL_4352 pass
13771 11:46:10.733793 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13772 11:46:10.734070 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13773 11:46:10.734185 arm64_za-ptrace_Set_VL_4368 pass
13774 11:46:10.734261 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13775 11:46:10.734348 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13776 11:46:10.734434 arm64_za-ptrace_Set_VL_4384 pass
13777 11:46:10.734521 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13778 11:46:10.734773 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13779 11:46:10.734891 arm64_za-ptrace_Set_VL_4400 pass
13780 11:46:10.734980 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13781 11:46:10.735077 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13782 11:46:10.735175 arm64_za-ptrace_Set_VL_4416 pass
13783 11:46:10.735273 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13784 11:46:10.735374 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13785 11:46:10.735481 arm64_za-ptrace_Set_VL_4432 pass
13786 11:46:10.735730 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13787 11:46:10.735819 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13788 11:46:10.735892 arm64_za-ptrace_Set_VL_4448 pass
13789 11:46:10.735979 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13790 11:46:10.740472 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13791 11:46:10.740904 arm64_za-ptrace_Set_VL_4464 pass
13792 11:46:10.740996 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13793 11:46:10.741099 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13794 11:46:10.741200 arm64_za-ptrace_Set_VL_4480 pass
13795 11:46:10.741283 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13796 11:46:10.741369 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13797 11:46:10.741467 arm64_za-ptrace_Set_VL_4496 pass
13798 11:46:10.741544 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13799 11:46:10.741638 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13800 11:46:10.741732 arm64_za-ptrace_Set_VL_4512 pass
13801 11:46:10.741828 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13802 11:46:10.741925 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13803 11:46:10.742009 arm64_za-ptrace_Set_VL_4528 pass
13804 11:46:10.742309 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13805 11:46:10.742393 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13806 11:46:10.742459 arm64_za-ptrace_Set_VL_4544 pass
13807 11:46:10.742543 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13808 11:46:10.742614 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13809 11:46:10.742854 arm64_za-ptrace_Set_VL_4560 pass
13810 11:46:10.742936 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13811 11:46:10.743212 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13812 11:46:10.743330 arm64_za-ptrace_Set_VL_4576 pass
13813 11:46:10.743397 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13814 11:46:10.743495 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13815 11:46:10.743565 arm64_za-ptrace_Set_VL_4592 pass
13816 11:46:10.743649 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13817 11:46:10.743715 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13818 11:46:10.743963 arm64_za-ptrace_Set_VL_4608 pass
13819 11:46:10.744028 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13820 11:46:10.744089 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13821 11:46:10.748978 arm64_za-ptrace_Set_VL_4624 pass
13822 11:46:10.779905 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13823 11:46:10.780172 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13824 11:46:10.780374 arm64_za-ptrace_Set_VL_4640 pass
13825 11:46:10.780626 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13826 11:46:10.780812 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13827 11:46:10.780968 arm64_za-ptrace_Set_VL_4656 pass
13828 11:46:10.781115 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13829 11:46:10.781294 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13830 11:46:10.781435 arm64_za-ptrace_Set_VL_4672 pass
13831 11:46:10.781579 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13832 11:46:10.781744 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13833 11:46:10.781922 arm64_za-ptrace_Set_VL_4688 pass
13834 11:46:10.782060 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13835 11:46:10.782204 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13836 11:46:10.782434 arm64_za-ptrace_Set_VL_4704 pass
13837 11:46:10.782605 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13838 11:46:10.782731 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13839 11:46:10.782850 arm64_za-ptrace_Set_VL_4720 pass
13840 11:46:10.782964 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13841 11:46:10.783344 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13842 11:46:10.783546 arm64_za-ptrace_Set_VL_4736 pass
13843 11:46:10.783711 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13844 11:46:10.783876 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13845 11:46:10.784039 arm64_za-ptrace_Set_VL_4752 pass
13846 11:46:10.784176 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13847 11:46:10.784297 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13848 11:46:10.784448 arm64_za-ptrace_Set_VL_4768 pass
13849 11:46:10.784572 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13850 11:46:10.784692 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13851 11:46:10.784807 arm64_za-ptrace_Set_VL_4784 pass
13852 11:46:10.784921 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13853 11:46:10.785041 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13854 11:46:10.785156 arm64_za-ptrace_Set_VL_4800 pass
13855 11:46:10.785269 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13856 11:46:10.788411 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13857 11:46:10.788810 arm64_za-ptrace_Set_VL_4816 pass
13858 11:46:10.788987 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13859 11:46:10.789192 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13860 11:46:10.789434 arm64_za-ptrace_Set_VL_4832 pass
13861 11:46:10.789631 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13862 11:46:10.789793 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13863 11:46:10.789922 arm64_za-ptrace_Set_VL_4848 pass
13864 11:46:10.790044 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13865 11:46:10.790196 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13866 11:46:10.790328 arm64_za-ptrace_Set_VL_4864 pass
13867 11:46:10.790454 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13868 11:46:10.790580 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13869 11:46:10.790704 arm64_za-ptrace_Set_VL_4880 pass
13870 11:46:10.790832 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13871 11:46:10.790956 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13872 11:46:10.791108 arm64_za-ptrace_Set_VL_4896 pass
13873 11:46:10.791237 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13874 11:46:10.791360 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13875 11:46:10.791481 arm64_za-ptrace_Set_VL_4912 pass
13876 11:46:10.791604 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13877 11:46:10.791728 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13878 11:46:10.791854 arm64_za-ptrace_Set_VL_4928 pass
13879 11:46:10.792003 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13880 11:46:10.792133 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13881 11:46:10.792255 arm64_za-ptrace_Set_VL_4944 pass
13882 11:46:10.792370 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13883 11:46:10.792486 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13884 11:46:10.792600 arm64_za-ptrace_Set_VL_4960 pass
13885 11:46:10.792713 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13886 11:46:10.792853 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13887 11:46:10.792973 arm64_za-ptrace_Set_VL_4976 pass
13888 11:46:10.796425 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13889 11:46:10.796877 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13890 11:46:10.797019 arm64_za-ptrace_Set_VL_4992 pass
13891 11:46:10.797166 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13892 11:46:10.797343 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13893 11:46:10.797481 arm64_za-ptrace_Set_VL_5008 pass
13894 11:46:10.797625 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13895 11:46:10.797784 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13896 11:46:10.797929 arm64_za-ptrace_Set_VL_5024 pass
13897 11:46:10.798107 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13898 11:46:10.798246 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13899 11:46:10.798390 arm64_za-ptrace_Set_VL_5040 pass
13900 11:46:10.798534 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13901 11:46:10.798676 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13902 11:46:10.798819 arm64_za-ptrace_Set_VL_5056 pass
13903 11:46:10.798996 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13904 11:46:10.799135 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13905 11:46:10.799280 arm64_za-ptrace_Set_VL_5072 pass
13906 11:46:10.799423 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13907 11:46:10.799567 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13908 11:46:10.799709 arm64_za-ptrace_Set_VL_5088 pass
13909 11:46:10.799851 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13910 11:46:10.800032 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13911 11:46:10.800169 arm64_za-ptrace_Set_VL_5104 pass
13912 11:46:10.800312 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13913 11:46:10.800455 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13914 11:46:10.800599 arm64_za-ptrace_Set_VL_5120 pass
13915 11:46:10.800743 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13916 11:46:10.800885 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13917 11:46:10.801027 arm64_za-ptrace_Set_VL_5136 pass
13918 11:46:10.801202 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13919 11:46:10.804563 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13920 11:46:10.805052 arm64_za-ptrace_Set_VL_5152 pass
13921 11:46:10.805167 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13922 11:46:10.805256 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13923 11:46:10.805338 arm64_za-ptrace_Set_VL_5168 pass
13924 11:46:10.805439 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13925 11:46:10.805525 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13926 11:46:10.805609 arm64_za-ptrace_Set_VL_5184 pass
13927 11:46:10.805718 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13928 11:46:10.805810 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13929 11:46:10.805893 arm64_za-ptrace_Set_VL_5200 pass
13930 11:46:10.805993 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13931 11:46:10.806080 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13932 11:46:10.806179 arm64_za-ptrace_Set_VL_5216 pass
13933 11:46:10.806265 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13934 11:46:10.806556 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13935 11:46:10.806648 arm64_za-ptrace_Set_VL_5232 pass
13936 11:46:10.806748 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
13937 11:46:10.806839 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
13938 11:46:10.806938 arm64_za-ptrace_Set_VL_5248 pass
13939 11:46:10.807038 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
13940 11:46:10.807326 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
13941 11:46:10.807425 arm64_za-ptrace_Set_VL_5264 pass
13942 11:46:10.807525 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
13943 11:46:10.807810 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
13944 11:46:10.807979 arm64_za-ptrace_Set_VL_5280 pass
13945 11:46:10.808154 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
13946 11:46:10.808332 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
13947 11:46:10.808472 arm64_za-ptrace_Set_VL_5296 pass
13948 11:46:10.808617 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
13949 11:46:10.812496 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
13950 11:46:10.813033 arm64_za-ptrace_Set_VL_5312 pass
13951 11:46:10.813362 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
13952 11:46:10.813815 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
13953 11:46:10.814204 arm64_za-ptrace_Set_VL_5328 pass
13954 11:46:10.814396 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
13955 11:46:10.814598 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
13956 11:46:10.814769 arm64_za-ptrace_Set_VL_5344 pass
13957 11:46:10.815122 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
13958 11:46:10.815318 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
13959 11:46:10.815720 arm64_za-ptrace_Set_VL_5360 pass
13960 11:46:10.815908 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
13961 11:46:10.816074 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
13962 11:46:10.816209 arm64_za-ptrace_Set_VL_5376 pass
13963 11:46:10.816328 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
13964 11:46:10.816445 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
13965 11:46:10.816560 arm64_za-ptrace_Set_VL_5392 pass
13966 11:46:10.816711 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
13967 11:46:10.816835 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
13968 11:46:10.816953 arm64_za-ptrace_Set_VL_5408 pass
13969 11:46:10.817068 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
13970 11:46:10.817184 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
13971 11:46:10.817299 arm64_za-ptrace_Set_VL_5424 pass
13972 11:46:10.817414 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
13973 11:46:10.817529 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
13974 11:46:10.817643 arm64_za-ptrace_Set_VL_5440 pass
13975 11:46:10.817855 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
13976 11:46:10.818050 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
13977 11:46:10.818235 arm64_za-ptrace_Set_VL_5456 pass
13978 11:46:10.818595 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
13979 11:46:10.821959 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
13980 11:46:10.822256 arm64_za-ptrace_Set_VL_5472 pass
13981 11:46:10.822424 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
13982 11:46:10.822591 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
13983 11:46:10.822746 arm64_za-ptrace_Set_VL_5488 pass
13984 11:46:10.822904 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
13985 11:46:10.823036 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
13986 11:46:10.823181 arm64_za-ptrace_Set_VL_5504 pass
13987 11:46:10.823368 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
13988 11:46:10.824039 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
13989 11:46:10.824223 arm64_za-ptrace_Set_VL_5520 pass
13990 11:46:10.824417 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
13991 11:46:10.824599 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
13992 11:46:10.824970 arm64_za-ptrace_Set_VL_5536 pass
13993 11:46:10.825112 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
13994 11:46:10.825237 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
13995 11:46:10.825357 arm64_za-ptrace_Set_VL_5552 pass
13996 11:46:10.825475 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
13997 11:46:10.825593 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
13998 11:46:10.825731 arm64_za-ptrace_Set_VL_5568 pass
13999 11:46:10.825852 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
14000 11:46:10.825969 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
14001 11:46:10.826087 arm64_za-ptrace_Set_VL_5584 pass
14002 11:46:10.826203 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
14003 11:46:10.826320 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
14004 11:46:10.826438 arm64_za-ptrace_Set_VL_5600 pass
14005 11:46:10.826556 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
14006 11:46:10.826679 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
14007 11:46:10.826797 arm64_za-ptrace_Set_VL_5616 pass
14008 11:46:10.826914 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
14009 11:46:10.827031 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
14010 11:46:10.828477 arm64_za-ptrace_Set_VL_5632 pass
14011 11:46:10.828881 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
14012 11:46:10.829016 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
14013 11:46:10.829136 arm64_za-ptrace_Set_VL_5648 pass
14014 11:46:10.859125 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
14015 11:46:10.859502 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
14016 11:46:10.859978 arm64_za-ptrace_Set_VL_5664 pass
14017 11:46:10.860180 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
14018 11:46:10.860370 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
14019 11:46:10.860586 arm64_za-ptrace_Set_VL_5680 pass
14020 11:46:10.860774 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
14021 11:46:10.860987 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
14022 11:46:10.861209 arm64_za-ptrace_Set_VL_5696 pass
14023 11:46:10.861446 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
14024 11:46:10.861632 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
14025 11:46:10.861824 arm64_za-ptrace_Set_VL_5712 pass
14026 11:46:10.862002 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
14027 11:46:10.862177 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
14028 11:46:10.862351 arm64_za-ptrace_Set_VL_5728 pass
14029 11:46:10.862524 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
14030 11:46:10.863230 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
14031 11:46:10.863392 arm64_za-ptrace_Set_VL_5744 pass
14032 11:46:10.863642 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
14033 11:46:10.863798 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
14034 11:46:10.863944 arm64_za-ptrace_Set_VL_5760 pass
14035 11:46:10.864043 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
14036 11:46:10.864214 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
14037 11:46:10.864308 arm64_za-ptrace_Set_VL_5776 pass
14038 11:46:10.864394 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
14039 11:46:10.864479 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
14040 11:46:10.864569 arm64_za-ptrace_Set_VL_5792 pass
14041 11:46:10.864659 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
14042 11:46:10.864747 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
14043 11:46:10.864837 arm64_za-ptrace_Set_VL_5808 pass
14044 11:46:10.864933 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
14045 11:46:10.865020 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
14046 11:46:10.865101 arm64_za-ptrace_Set_VL_5824 pass
14047 11:46:10.865184 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
14048 11:46:10.865475 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
14049 11:46:10.865637 arm64_za-ptrace_Set_VL_5840 pass
14050 11:46:10.865800 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
14051 11:46:10.865947 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
14052 11:46:10.866089 arm64_za-ptrace_Set_VL_5856 pass
14053 11:46:10.866233 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
14054 11:46:10.868520 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
14055 11:46:10.868783 arm64_za-ptrace_Set_VL_5872 pass
14056 11:46:10.869333 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
14057 11:46:10.869561 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
14058 11:46:10.869807 arm64_za-ptrace_Set_VL_5888 pass
14059 11:46:10.870036 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
14060 11:46:10.870245 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
14061 11:46:10.870460 arm64_za-ptrace_Set_VL_5904 pass
14062 11:46:10.870683 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
14063 11:46:10.870924 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
14064 11:46:10.871164 arm64_za-ptrace_Set_VL_5920 pass
14065 11:46:10.871385 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
14066 11:46:10.872243 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
14067 11:46:10.872422 arm64_za-ptrace_Set_VL_5936 pass
14068 11:46:10.872570 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
14069 11:46:10.872714 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
14070 11:46:10.872856 arm64_za-ptrace_Set_VL_5952 pass
14071 11:46:10.873001 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
14072 11:46:10.873144 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
14073 11:46:10.873334 arm64_za-ptrace_Set_VL_5968 pass
14074 11:46:10.873469 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
14075 11:46:10.873614 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
14076 11:46:10.873771 arm64_za-ptrace_Set_VL_5984 pass
14077 11:46:10.873915 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
14078 11:46:10.874057 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
14079 11:46:10.874199 arm64_za-ptrace_Set_VL_6000 pass
14080 11:46:10.874341 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
14081 11:46:10.874484 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
14082 11:46:10.874625 arm64_za-ptrace_Set_VL_6016 pass
14083 11:46:10.874766 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
14084 11:46:10.876531 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
14085 11:46:10.877401 arm64_za-ptrace_Set_VL_6032 pass
14086 11:46:10.877913 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
14087 11:46:10.878006 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
14088 11:46:10.878090 arm64_za-ptrace_Set_VL_6048 pass
14089 11:46:10.878176 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
14090 11:46:10.878260 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
14091 11:46:10.878345 arm64_za-ptrace_Set_VL_6064 pass
14092 11:46:10.878454 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
14093 11:46:10.878541 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
14094 11:46:10.878621 arm64_za-ptrace_Set_VL_6080 pass
14095 11:46:10.878699 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
14096 11:46:10.878780 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
14097 11:46:10.878862 arm64_za-ptrace_Set_VL_6096 pass
14098 11:46:10.878950 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
14099 11:46:10.879032 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
14100 11:46:10.879113 arm64_za-ptrace_Set_VL_6112 pass
14101 11:46:10.879212 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
14102 11:46:10.879298 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
14103 11:46:10.879382 arm64_za-ptrace_Set_VL_6128 pass
14104 11:46:10.879461 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
14105 11:46:10.879543 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
14106 11:46:10.879626 arm64_za-ptrace_Set_VL_6144 pass
14107 11:46:10.880102 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
14108 11:46:10.880206 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
14109 11:46:10.880291 arm64_za-ptrace_Set_VL_6160 pass
14110 11:46:10.880376 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
14111 11:46:10.880461 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
14112 11:46:10.880547 arm64_za-ptrace_Set_VL_6176 pass
14113 11:46:10.884462 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
14114 11:46:10.884909 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
14115 11:46:10.885109 arm64_za-ptrace_Set_VL_6192 pass
14116 11:46:10.885282 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
14117 11:46:10.885484 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
14118 11:46:10.885769 arm64_za-ptrace_Set_VL_6208 pass
14119 11:46:10.885980 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
14120 11:46:10.886200 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
14121 11:46:10.886399 arm64_za-ptrace_Set_VL_6224 pass
14122 11:46:10.886584 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
14123 11:46:10.886782 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
14124 11:46:10.887007 arm64_za-ptrace_Set_VL_6240 pass
14125 11:46:10.887291 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
14126 11:46:10.888167 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
14127 11:46:10.888344 arm64_za-ptrace_Set_VL_6256 pass
14128 11:46:10.888492 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
14129 11:46:10.888635 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
14130 11:46:10.888777 arm64_za-ptrace_Set_VL_6272 pass
14131 11:46:10.888919 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
14132 11:46:10.889061 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
14133 11:46:10.889203 arm64_za-ptrace_Set_VL_6288 pass
14134 11:46:10.889345 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
14135 11:46:10.889534 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
14136 11:46:10.889684 arm64_za-ptrace_Set_VL_6304 pass
14137 11:46:10.889831 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
14138 11:46:10.889975 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
14139 11:46:10.890118 arm64_za-ptrace_Set_VL_6320 pass
14140 11:46:10.890261 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
14141 11:46:10.890405 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
14142 11:46:10.892592 arm64_za-ptrace_Set_VL_6336 pass
14143 11:46:10.892902 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
14144 11:46:10.893358 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
14145 11:46:10.893567 arm64_za-ptrace_Set_VL_6352 pass
14146 11:46:10.893881 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
14147 11:46:10.894069 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
14148 11:46:10.894271 arm64_za-ptrace_Set_VL_6368 pass
14149 11:46:10.894464 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
14150 11:46:10.894669 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
14151 11:46:10.894837 arm64_za-ptrace_Set_VL_6384 pass
14152 11:46:10.895002 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
14153 11:46:10.895165 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
14154 11:46:10.895333 arm64_za-ptrace_Set_VL_6400 pass
14155 11:46:10.896082 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
14156 11:46:10.896281 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
14157 11:46:10.896456 arm64_za-ptrace_Set_VL_6416 pass
14158 11:46:10.896602 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
14159 11:46:10.896745 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
14160 11:46:10.896889 arm64_za-ptrace_Set_VL_6432 pass
14161 11:46:10.897082 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
14162 11:46:10.897218 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
14163 11:46:10.897363 arm64_za-ptrace_Set_VL_6448 pass
14164 11:46:10.897506 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
14165 11:46:10.897656 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
14166 11:46:10.897804 arm64_za-ptrace_Set_VL_6464 pass
14167 11:46:10.897949 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
14168 11:46:10.898092 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
14169 11:46:10.898232 arm64_za-ptrace_Set_VL_6480 pass
14170 11:46:10.898374 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
14171 11:46:10.898515 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
14172 11:46:10.900785 arm64_za-ptrace_Set_VL_6496 pass
14173 11:46:10.901033 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
14174 11:46:10.901276 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
14175 11:46:10.901485 arm64_za-ptrace_Set_VL_6512 pass
14176 11:46:10.901685 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
14177 11:46:10.901854 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
14178 11:46:10.902030 arm64_za-ptrace_Set_VL_6528 pass
14179 11:46:10.902236 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
14180 11:46:10.902415 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14181 11:46:10.902592 arm64_za-ptrace_Set_VL_6544 pass
14182 11:46:10.902765 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14183 11:46:10.902938 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14184 11:46:10.903110 arm64_za-ptrace_Set_VL_6560 pass
14185 11:46:10.903284 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14186 11:46:10.904020 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14187 11:46:10.904226 arm64_za-ptrace_Set_VL_6576 pass
14188 11:46:10.904380 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14189 11:46:10.904523 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14190 11:46:10.904666 arm64_za-ptrace_Set_VL_6592 pass
14191 11:46:10.904808 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14192 11:46:10.904949 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14193 11:46:10.905092 arm64_za-ptrace_Set_VL_6608 pass
14194 11:46:10.905232 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14195 11:46:10.905374 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14196 11:46:10.905517 arm64_za-ptrace_Set_VL_6624 pass
14197 11:46:10.905669 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14198 11:46:10.905813 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14199 11:46:10.905956 arm64_za-ptrace_Set_VL_6640 pass
14200 11:46:10.906139 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14201 11:46:10.906277 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14202 11:46:10.908456 arm64_za-ptrace_Set_VL_6656 pass
14203 11:46:10.908951 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14204 11:46:10.909118 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14205 11:46:10.909293 arm64_za-ptrace_Set_VL_6672 pass
14206 11:46:10.909697 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14207 11:46:10.939814 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14208 11:46:10.940345 arm64_za-ptrace_Set_VL_6688 pass
14209 11:46:10.940521 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14210 11:46:10.940740 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14211 11:46:10.940962 arm64_za-ptrace_Set_VL_6704 pass
14212 11:46:10.941147 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14213 11:46:10.941357 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14214 11:46:10.941548 arm64_za-ptrace_Set_VL_6720 pass
14215 11:46:10.941753 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14216 11:46:10.942006 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14217 11:46:10.942197 arm64_za-ptrace_Set_VL_6736 pass
14218 11:46:10.942371 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14219 11:46:10.942541 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14220 11:46:10.942727 arm64_za-ptrace_Set_VL_6752 pass
14221 11:46:10.942936 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14222 11:46:10.943150 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14223 11:46:10.943313 arm64_za-ptrace_Set_VL_6768 pass
14224 11:46:10.943523 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14225 11:46:10.943750 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14226 11:46:10.943974 arm64_za-ptrace_Set_VL_6784 pass
14227 11:46:10.944175 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14228 11:46:10.944310 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14229 11:46:10.944429 arm64_za-ptrace_Set_VL_6800 pass
14230 11:46:10.944544 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14231 11:46:10.944658 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14232 11:46:10.944788 arm64_za-ptrace_Set_VL_6816 pass
14233 11:46:10.944965 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14234 11:46:10.945125 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14235 11:46:10.945247 arm64_za-ptrace_Set_VL_6832 pass
14236 11:46:10.945362 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14237 11:46:10.945507 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14238 11:46:10.945630 arm64_za-ptrace_Set_VL_6848 pass
14239 11:46:10.945868 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14240 11:46:10.946063 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14241 11:46:10.946247 arm64_za-ptrace_Set_VL_6864 pass
14242 11:46:10.948443 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14243 11:46:10.948931 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14244 11:46:10.949129 arm64_za-ptrace_Set_VL_6880 pass
14245 11:46:10.949293 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14246 11:46:10.949489 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14247 11:46:10.949672 arm64_za-ptrace_Set_VL_6896 pass
14248 11:46:10.949848 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14249 11:46:10.950057 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14250 11:46:10.950295 arm64_za-ptrace_Set_VL_6912 pass
14251 11:46:10.950514 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14252 11:46:10.950738 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14253 11:46:10.950905 arm64_za-ptrace_Set_VL_6928 pass
14254 11:46:10.951070 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14255 11:46:10.951261 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14256 11:46:10.951423 arm64_za-ptrace_Set_VL_6944 pass
14257 11:46:10.951640 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14258 11:46:10.951836 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14259 11:46:10.952018 arm64_za-ptrace_Set_VL_6960 pass
14260 11:46:10.952199 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14261 11:46:10.952362 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14262 11:46:10.952486 arm64_za-ptrace_Set_VL_6976 pass
14263 11:46:10.952604 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14264 11:46:10.952719 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14265 11:46:10.952834 arm64_za-ptrace_Set_VL_6992 pass
14266 11:46:10.952949 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14267 11:46:10.953067 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14268 11:46:10.953181 arm64_za-ptrace_Set_VL_7008 pass
14269 11:46:10.953296 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14270 11:46:10.953410 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14271 11:46:10.953526 arm64_za-ptrace_Set_VL_7024 pass
14272 11:46:10.953640 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14273 11:46:10.956684 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14274 11:46:10.956958 arm64_za-ptrace_Set_VL_7040 pass
14275 11:46:10.957166 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14276 11:46:10.957912 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14277 11:46:10.958075 arm64_za-ptrace_Set_VL_7056 pass
14278 11:46:10.958239 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14279 11:46:10.958393 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14280 11:46:10.958552 arm64_za-ptrace_Set_VL_7072 pass
14281 11:46:10.958737 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14282 11:46:10.958849 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14283 11:46:10.958934 arm64_za-ptrace_Set_VL_7088 pass
14284 11:46:10.959021 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14285 11:46:10.959335 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14286 11:46:10.959492 arm64_za-ptrace_Set_VL_7104 pass
14287 11:46:10.959659 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14288 11:46:10.959831 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14289 11:46:10.959934 arm64_za-ptrace_Set_VL_7120 pass
14290 11:46:10.960097 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14291 11:46:10.960201 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14292 11:46:10.960287 arm64_za-ptrace_Set_VL_7136 pass
14293 11:46:10.960368 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14294 11:46:10.960452 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14295 11:46:10.960537 arm64_za-ptrace_Set_VL_7152 pass
14296 11:46:10.960638 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14297 11:46:10.960721 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14298 11:46:10.960803 arm64_za-ptrace_Set_VL_7168 pass
14299 11:46:10.960884 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14300 11:46:10.960966 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14301 11:46:10.961048 arm64_za-ptrace_Set_VL_7184 pass
14302 11:46:10.961129 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14303 11:46:10.964444 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14304 11:46:10.965327 arm64_za-ptrace_Set_VL_7200 pass
14305 11:46:10.965554 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14306 11:46:10.965764 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14307 11:46:10.965968 arm64_za-ptrace_Set_VL_7216 pass
14308 11:46:10.966179 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14309 11:46:10.966384 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14310 11:46:10.966635 arm64_za-ptrace_Set_VL_7232 pass
14311 11:46:10.966869 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14312 11:46:10.967141 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14313 11:46:10.967371 arm64_za-ptrace_Set_VL_7248 pass
14314 11:46:10.968055 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14315 11:46:10.968248 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14316 11:46:10.968418 arm64_za-ptrace_Set_VL_7264 pass
14317 11:46:10.968582 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14318 11:46:10.968740 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14319 11:46:10.968899 arm64_za-ptrace_Set_VL_7280 pass
14320 11:46:10.969066 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14321 11:46:10.969209 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14322 11:46:10.969336 arm64_za-ptrace_Set_VL_7296 pass
14323 11:46:10.969466 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14324 11:46:10.969599 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14325 11:46:10.969747 arm64_za-ptrace_Set_VL_7312 pass
14326 11:46:10.969882 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14327 11:46:10.970019 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14328 11:46:10.970158 arm64_za-ptrace_Set_VL_7328 pass
14329 11:46:10.970256 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14330 11:46:10.970349 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14331 11:46:10.970441 arm64_za-ptrace_Set_VL_7344 pass
14332 11:46:10.970531 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14333 11:46:10.970624 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14334 11:46:10.970715 arm64_za-ptrace_Set_VL_7360 pass
14335 11:46:10.970808 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14336 11:46:10.972569 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14337 11:46:10.972723 arm64_za-ptrace_Set_VL_7376 pass
14338 11:46:10.972831 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14339 11:46:10.972918 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14340 11:46:10.973004 arm64_za-ptrace_Set_VL_7392 pass
14341 11:46:10.973108 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14342 11:46:10.973196 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14343 11:46:10.973296 arm64_za-ptrace_Set_VL_7408 pass
14344 11:46:10.973386 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14345 11:46:10.973486 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14346 11:46:10.973575 arm64_za-ptrace_Set_VL_7424 pass
14347 11:46:10.973684 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14348 11:46:10.973790 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14349 11:46:10.973879 arm64_za-ptrace_Set_VL_7440 pass
14350 11:46:10.973978 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14351 11:46:10.974066 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14352 11:46:10.974172 arm64_za-ptrace_Set_VL_7456 pass
14353 11:46:10.974262 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14354 11:46:10.974363 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14355 11:46:10.974451 arm64_za-ptrace_Set_VL_7472 pass
14356 11:46:10.974554 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14357 11:46:10.974642 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14358 11:46:10.974746 arm64_za-ptrace_Set_VL_7488 pass
14359 11:46:10.974839 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14360 11:46:10.974944 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14361 11:46:10.975036 arm64_za-ptrace_Set_VL_7504 pass
14362 11:46:10.975142 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14363 11:46:10.975231 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14364 11:46:10.975337 arm64_za-ptrace_Set_VL_7520 pass
14365 11:46:10.975426 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14366 11:46:10.975527 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14367 11:46:10.975613 arm64_za-ptrace_Set_VL_7536 pass
14368 11:46:10.975714 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14369 11:46:10.975804 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14370 11:46:10.975906 arm64_za-ptrace_Set_VL_7552 pass
14371 11:46:10.975996 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14372 11:46:10.976101 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14373 11:46:10.976191 arm64_za-ptrace_Set_VL_7568 pass
14374 11:46:10.980589 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14375 11:46:10.980800 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14376 11:46:10.980896 arm64_za-ptrace_Set_VL_7584 pass
14377 11:46:10.981005 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14378 11:46:10.981099 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14379 11:46:10.981194 arm64_za-ptrace_Set_VL_7600 pass
14380 11:46:10.981279 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14381 11:46:10.981380 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14382 11:46:10.981467 arm64_za-ptrace_Set_VL_7616 pass
14383 11:46:10.981549 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14384 11:46:10.981631 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14385 11:46:10.981737 arm64_za-ptrace_Set_VL_7632 pass
14386 11:46:10.981823 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14387 11:46:10.981907 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14388 11:46:10.982005 arm64_za-ptrace_Set_VL_7648 pass
14389 11:46:10.982091 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14390 11:46:10.982188 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14391 11:46:10.982270 arm64_za-ptrace_Set_VL_7664 pass
14392 11:46:10.982353 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14393 11:46:10.982450 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14394 11:46:10.982537 arm64_za-ptrace_Set_VL_7680 pass
14395 11:46:10.982635 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14396 11:46:10.982719 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14397 11:46:10.982814 arm64_za-ptrace_Set_VL_7696 pass
14398 11:46:10.982900 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14399 11:46:11.015271 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14400 11:46:11.015507 arm64_za-ptrace_Set_VL_7712 pass
14401 11:46:11.015816 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14402 11:46:11.015925 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14403 11:46:11.016021 arm64_za-ptrace_Set_VL_7728 pass
14404 11:46:11.016110 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14405 11:46:11.016199 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14406 11:46:11.016305 arm64_za-ptrace_Set_VL_7744 pass
14407 11:46:11.016398 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14408 11:46:11.016505 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14409 11:46:11.016596 arm64_za-ptrace_Set_VL_7760 pass
14410 11:46:11.016698 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14411 11:46:11.016790 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14412 11:46:11.016891 arm64_za-ptrace_Set_VL_7776 pass
14413 11:46:11.016992 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14414 11:46:11.017329 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14415 11:46:11.017503 arm64_za-ptrace_Set_VL_7792 pass
14416 11:46:11.017635 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14417 11:46:11.017842 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14418 11:46:11.017996 arm64_za-ptrace_Set_VL_7808 pass
14419 11:46:11.018144 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14420 11:46:11.018302 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14421 11:46:11.018460 arm64_za-ptrace_Set_VL_7824 pass
14422 11:46:11.018647 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14423 11:46:11.018811 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14424 11:46:11.018969 arm64_za-ptrace_Set_VL_7840 pass
14425 11:46:11.019128 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14426 11:46:11.019289 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14427 11:46:11.019449 arm64_za-ptrace_Set_VL_7856 pass
14428 11:46:11.019626 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14429 11:46:11.019789 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14430 11:46:11.019946 arm64_za-ptrace_Set_VL_7872 pass
14431 11:46:11.020131 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14432 11:46:11.020285 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14433 11:46:11.020406 arm64_za-ptrace_Set_VL_7888 pass
14434 11:46:11.020522 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14435 11:46:11.020638 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14436 11:46:11.020753 arm64_za-ptrace_Set_VL_7904 pass
14437 11:46:11.020899 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14438 11:46:11.021025 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14439 11:46:11.021144 arm64_za-ptrace_Set_VL_7920 pass
14440 11:46:11.021263 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14441 11:46:11.024380 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14442 11:46:11.024690 arm64_za-ptrace_Set_VL_7936 pass
14443 11:46:11.024795 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14444 11:46:11.024903 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14445 11:46:11.024994 arm64_za-ptrace_Set_VL_7952 pass
14446 11:46:11.025096 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14447 11:46:11.025204 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14448 11:46:11.025607 arm64_za-ptrace_Set_VL_7968 pass
14449 11:46:11.025793 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14450 11:46:11.026199 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14451 11:46:11.026363 arm64_za-ptrace_Set_VL_7984 pass
14452 11:46:11.026494 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14453 11:46:11.026623 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14454 11:46:11.026759 arm64_za-ptrace_Set_VL_8000 pass
14455 11:46:11.026954 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14456 11:46:11.027114 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14457 11:46:11.027321 arm64_za-ptrace_Set_VL_8016 pass
14458 11:46:11.027523 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14459 11:46:11.027765 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14460 11:46:11.028022 arm64_za-ptrace_Set_VL_8032 pass
14461 11:46:11.028210 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14462 11:46:11.028340 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14463 11:46:11.028457 arm64_za-ptrace_Set_VL_8048 pass
14464 11:46:11.028573 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14465 11:46:11.028689 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14466 11:46:11.028804 arm64_za-ptrace_Set_VL_8064 pass
14467 11:46:11.028919 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14468 11:46:11.029034 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14469 11:46:11.029150 arm64_za-ptrace_Set_VL_8080 pass
14470 11:46:11.029268 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14471 11:46:11.029384 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14472 11:46:11.029499 arm64_za-ptrace_Set_VL_8096 pass
14473 11:46:11.029614 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14474 11:46:11.029821 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14475 11:46:11.030015 arm64_za-ptrace_Set_VL_8112 pass
14476 11:46:11.030233 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14477 11:46:11.032416 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14478 11:46:11.032855 arm64_za-ptrace_Set_VL_8128 pass
14479 11:46:11.033033 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14480 11:46:11.033194 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14481 11:46:11.033360 arm64_za-ptrace_Set_VL_8144 pass
14482 11:46:11.033556 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14483 11:46:11.033738 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14484 11:46:11.033884 arm64_za-ptrace_Set_VL_8160 pass
14485 11:46:11.034046 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14486 11:46:11.034191 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14487 11:46:11.034351 arm64_za-ptrace_Set_VL_8176 pass
14488 11:46:11.034539 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14489 11:46:11.034712 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14490 11:46:11.034869 arm64_za-ptrace_Set_VL_8192 pass
14491 11:46:11.035026 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14492 11:46:11.035179 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14493 11:46:11.035336 arm64_za-ptrace pass
14494 11:46:11.035491 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14495 11:46:11.035683 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14496 11:46:11.035821 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14497 11:46:11.035943 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14498 11:46:11.036132 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14499 11:46:11.036341 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14500 11:46:11.040522 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14501 11:46:11.040954 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14502 11:46:11.041158 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14503 11:46:11.041363 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14504 11:46:11.041561 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14505 11:46:11.041975 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14506 11:46:11.042099 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14507 11:46:11.042394 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14508 11:46:11.042704 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14509 11:46:11.043003 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14510 11:46:11.043116 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14511 11:46:11.043413 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14512 11:46:11.043890 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14513 11:46:11.044006 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14514 11:46:11.044110 arm64_check_buffer_fill fail
14515 11:46:11.048844 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14516 11:46:11.049081 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14517 11:46:11.049314 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14518 11:46:11.049507 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14519 11:46:11.049738 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14520 11:46:11.050286 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14521 11:46:11.050507 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14522 11:46:11.050734 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14523 11:46:11.050969 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14524 11:46:11.051167 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14525 11:46:11.051365 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14526 11:46:11.051769 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14527 11:46:11.052012 arm64_check_child_memory fail
14528 11:46:11.052193 arm64_check_gcr_el1_cswitch fail
14529 11:46:11.052379 arm64_check_ksm_options fail
14530 11:46:11.056452 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14531 11:46:11.056866 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14532 11:46:11.057081 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14533 11:46:11.057255 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14534 11:46:11.057685 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14535 11:46:11.066365 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14536 11:46:11.066814 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14537 11:46:11.067028 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14538 11:46:11.067230 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14539 11:46:11.067435 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14540 11:46:11.067876 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14541 11:46:11.068118 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14542 11:46:11.068582 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14543 11:46:11.068813 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14544 11:46:11.069018 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14545 11:46:11.069214 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14546 11:46:11.069682 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14547 11:46:11.070133 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14548 11:46:11.070344 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14549 11:46:11.070540 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14550 11:46:11.070712 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14551 11:46:11.070865 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14552 11:46:11.071015 arm64_check_mmap_options fail
14553 11:46:11.071204 arm64_check_prctl_check_basic_read pass
14554 11:46:11.071363 arm64_check_prctl_NONE pass
14555 11:46:11.071485 arm64_check_prctl_SYNC pass
14556 11:46:11.071624 arm64_check_prctl_ASYNC pass
14557 11:46:11.071757 arm64_check_prctl_SYNC_ASYNC pass
14558 11:46:11.071909 arm64_check_prctl pass
14559 11:46:11.072407 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14560 11:46:11.072583 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14561 11:46:11.072710 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14562 11:46:11.076297 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14563 11:46:11.076716 arm64_check_tags_inclusion fail
14564 11:46:11.076904 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14565 11:46:11.077140 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14566 11:46:11.077334 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14567 11:46:11.077547 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14568 11:46:11.077752 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14569 11:46:11.077954 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14570 11:46:11.078178 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14571 11:46:11.078358 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14572 11:46:11.078580 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14573 11:46:11.078771 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14574 11:46:11.078963 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14575 11:46:11.079390 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14576 11:46:11.079559 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14577 11:46:11.079707 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14578 11:46:11.080155 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14579 11:46:11.080341 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14580 11:46:11.080514 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14581 11:46:11.080660 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14582 11:46:11.084366 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14583 11:46:11.084859 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14584 11:46:11.085081 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14585 11:46:11.085357 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14586 11:46:11.085535 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14587 11:46:11.085693 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14588 11:46:11.085845 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14589 11:46:11.085971 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14590 11:46:11.086147 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14591 11:46:11.086309 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14592 11:46:11.086723 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14593 11:46:11.086907 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14594 11:46:11.087100 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14595 11:46:11.087262 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14596 11:46:11.087465 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14597 11:46:11.087634 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14598 11:46:11.087819 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14599 11:46:11.088047 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14600 11:46:11.096367 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14601 11:46:11.096903 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14602 11:46:11.097098 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14603 11:46:11.097276 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14604 11:46:11.097540 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14605 11:46:11.097799 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14606 11:46:11.098053 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14607 11:46:11.098251 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14608 11:46:11.098478 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14609 11:46:11.098729 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14610 11:46:11.098923 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14611 11:46:11.099109 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14612 11:46:11.099357 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14613 11:46:11.099544 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14614 11:46:11.099776 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14615 11:46:11.100092 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14616 11:46:11.100295 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14617 11:46:11.100477 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14618 11:46:11.104327 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14619 11:46:11.104832 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14620 11:46:11.105035 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14621 11:46:11.105226 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14622 11:46:11.105388 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14623 11:46:11.105572 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14624 11:46:11.105750 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14625 11:46:11.105934 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14626 11:46:11.121031 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14627 11:46:11.121354 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14628 11:46:11.121749 arm64_check_user_mem pass
14629 11:46:11.122206 arm64_btitest_nohint_func_call_using_br_x0 pass
14630 11:46:11.122403 arm64_btitest_nohint_func_call_using_br_x16 pass
14631 11:46:11.122534 arm64_btitest_nohint_func_call_using_blr pass
14632 11:46:11.122651 arm64_btitest_bti_none_func_call_using_br_x0 pass
14633 11:46:11.122778 arm64_btitest_bti_none_func_call_using_br_x16 pass
14634 11:46:11.122929 arm64_btitest_bti_none_func_call_using_blr pass
14635 11:46:11.123091 arm64_btitest_bti_c_func_call_using_br_x0 pass
14636 11:46:11.123258 arm64_btitest_bti_c_func_call_using_br_x16 pass
14637 11:46:11.123414 arm64_btitest_bti_c_func_call_using_blr pass
14638 11:46:11.123551 arm64_btitest_bti_j_func_call_using_br_x0 pass
14639 11:46:11.123671 arm64_btitest_bti_j_func_call_using_br_x16 pass
14640 11:46:11.123828 arm64_btitest_bti_j_func_call_using_blr pass
14641 11:46:11.123991 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14642 11:46:11.124160 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14643 11:46:11.124325 arm64_btitest_bti_jc_func_call_using_blr pass
14644 11:46:11.124500 arm64_btitest_paciasp_func_call_using_br_x0 pass
14645 11:46:11.124682 arm64_btitest_paciasp_func_call_using_br_x16 pass
14646 11:46:11.124842 arm64_btitest_paciasp_func_call_using_blr pass
14647 11:46:11.125007 arm64_btitest pass
14648 11:46:11.125175 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14649 11:46:11.125339 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14650 11:46:11.125505 arm64_nobtitest_nohint_func_call_using_blr pass
14651 11:46:11.125694 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14652 11:46:11.125877 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14653 11:46:11.126099 arm64_nobtitest_bti_none_func_call_using_blr pass
14654 11:46:11.126278 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14655 11:46:11.126431 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14656 11:46:11.126561 arm64_nobtitest_bti_c_func_call_using_blr pass
14657 11:46:11.128348 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14658 11:46:11.128737 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14659 11:46:11.128859 arm64_nobtitest_bti_j_func_call_using_blr pass
14660 11:46:11.128976 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14661 11:46:11.129099 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14662 11:46:11.129194 arm64_nobtitest_bti_jc_func_call_using_blr pass
14663 11:46:11.129282 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14664 11:46:11.129378 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14665 11:46:11.129439 arm64_nobtitest_paciasp_func_call_using_blr pass
14666 11:46:11.129510 arm64_nobtitest pass
14667 11:46:11.129571 arm64_hwcap_cpuinfo_match_RNG pass
14668 11:46:11.129662 arm64_hwcap_sigill_RNG pass
14669 11:46:11.129923 arm64_hwcap_cpuinfo_match_SME pass
14670 11:46:11.129999 arm64_hwcap_sigill_SME pass
14671 11:46:11.130080 arm64_hwcap_cpuinfo_match_SVE pass
14672 11:46:11.130158 arm64_hwcap_sigill_SVE pass
14673 11:46:11.130245 arm64_hwcap_cpuinfo_match_SVE_2 pass
14674 11:46:11.130330 arm64_hwcap_sigill_SVE_2 pass
14675 11:46:11.130408 arm64_hwcap_cpuinfo_match_SVE_AES pass
14676 11:46:11.130498 arm64_hwcap_sigill_SVE_AES pass
14677 11:46:11.130586 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14678 11:46:11.130678 arm64_hwcap_sigill_SVE2_PMULL pass
14679 11:46:11.130964 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14680 11:46:11.131058 arm64_hwcap_sigill_SVE2_BITPERM pass
14681 11:46:11.131151 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14682 11:46:11.131230 arm64_hwcap_sigill_SVE2_SHA3 pass
14683 11:46:11.131318 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14684 11:46:11.131398 arm64_hwcap_sigill_SVE2_SM4 pass
14685 11:46:11.131672 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14686 11:46:11.131752 arm64_hwcap_sigill_SVE2_I8MM pass
14687 11:46:11.131841 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14688 11:46:11.131916 arm64_hwcap_sigill_SVE2_F32MM pass
14689 11:46:11.131997 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14690 11:46:11.132087 arm64_hwcap_sigill_SVE2_F64MM pass
14691 11:46:11.132165 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14692 11:46:11.132240 arm64_hwcap_sigill_SVE2_BF16 pass
14693 11:46:11.132329 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14694 11:46:11.132407 arm64_hwcap_sigill_SVE2_EBF16 skip
14695 11:46:11.132482 arm64_hwcap pass
14696 11:46:11.132577 arm64_ptrace_read_tpidr_one pass
14697 11:46:11.132685 arm64_ptrace_write_tpidr_one pass
14698 11:46:11.132772 arm64_ptrace_verify_tpidr_one pass
14699 11:46:11.132858 arm64_ptrace_count_tpidrs pass
14700 11:46:11.132987 arm64_ptrace_tpidr2_write pass
14701 11:46:11.133101 arm64_ptrace_tpidr2_read pass
14702 11:46:11.133204 arm64_ptrace_write_tpidr_only pass
14703 11:46:11.133314 arm64_ptrace pass
14704 11:46:11.133433 arm64_syscall-abi_getpid_FPSIMD pass
14705 11:46:11.133520 arm64_syscall-abi_getpid_SVE_VL_256 pass
14706 11:46:11.133622 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14707 11:46:11.133729 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14708 11:46:11.133842 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14709 11:46:11.133938 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14710 11:46:11.134040 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14711 11:46:11.140350 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14712 11:46:11.140753 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14713 11:46:11.140844 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14714 11:46:11.140921 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14715 11:46:11.141009 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14716 11:46:11.141087 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14717 11:46:11.141178 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14718 11:46:11.141472 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14719 11:46:11.141554 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14720 11:46:11.141805 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14721 11:46:11.141875 arm64_syscall-abi_getpid_SVE_VL_240 pass
14722 11:46:11.141948 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14723 11:46:11.142216 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14724 11:46:11.142323 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14725 11:46:11.142421 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14726 11:46:11.142692 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14727 11:46:11.142787 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14728 11:46:11.143053 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14729 11:46:11.143143 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14730 11:46:11.143406 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14731 11:46:11.143493 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14732 11:46:11.143583 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14733 11:46:11.143858 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14734 11:46:11.143958 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14735 11:46:11.144041 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14736 11:46:11.148370 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14737 11:46:11.148730 arm64_syscall-abi_getpid_SVE_VL_224 pass
14738 11:46:11.148826 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14739 11:46:11.148905 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14740 11:46:11.148997 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14741 11:46:11.149072 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14742 11:46:11.149162 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14743 11:46:11.149251 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14744 11:46:11.149327 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14745 11:46:11.149585 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14746 11:46:11.149668 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14747 11:46:11.149744 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14748 11:46:11.150121 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14749 11:46:11.150198 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14750 11:46:11.150445 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14751 11:46:11.150535 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14752 11:46:11.150616 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14753 11:46:11.150890 arm64_syscall-abi_getpid_SVE_VL_208 pass
14754 11:46:11.150975 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14755 11:46:11.151052 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14756 11:46:11.151144 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14757 11:46:11.151228 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14758 11:46:11.151319 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14759 11:46:11.152557 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14760 11:46:11.152784 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14761 11:46:11.152972 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14762 11:46:11.153148 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14763 11:46:11.153324 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14764 11:46:11.156436 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14765 11:46:11.156662 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14766 11:46:11.157092 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14767 11:46:11.157364 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14768 11:46:11.157546 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14769 11:46:11.157743 arm64_syscall-abi_getpid_SVE_VL_192 pass
14770 11:46:11.157921 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14771 11:46:11.158122 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14772 11:46:11.158288 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14773 11:46:11.158444 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14774 11:46:11.158604 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14775 11:46:11.158760 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14776 11:46:11.158901 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14777 11:46:11.159071 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14778 11:46:11.159247 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14779 11:46:11.159461 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14780 11:46:11.159650 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14781 11:46:11.159823 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14782 11:46:11.160001 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14783 11:46:11.160178 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14784 11:46:11.160358 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14785 11:46:11.160534 arm64_syscall-abi_getpid_SVE_VL_176 pass
14786 11:46:11.160709 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14787 11:46:11.160885 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14788 11:46:11.161061 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14789 11:46:11.161272 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14790 11:46:11.161450 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14791 11:46:11.161632 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14792 11:46:11.161820 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14793 11:46:11.164443 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14794 11:46:11.164891 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14795 11:46:11.165335 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14796 11:46:11.175906 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14797 11:46:11.176494 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14798 11:46:11.176604 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14799 11:46:11.176691 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14800 11:46:11.176792 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14801 11:46:11.177139 arm64_syscall-abi_getpid_SVE_VL_160 pass
14802 11:46:11.177393 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14803 11:46:11.177502 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14804 11:46:11.177605 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14805 11:46:11.177731 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14806 11:46:11.177834 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14807 11:46:11.177942 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14808 11:46:11.178033 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14809 11:46:11.178352 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14810 11:46:11.178459 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14811 11:46:11.178550 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14812 11:46:11.178633 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14813 11:46:11.178731 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14814 11:46:11.178817 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14815 11:46:11.178897 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14816 11:46:11.179014 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14817 11:46:11.179178 arm64_syscall-abi_getpid_SVE_VL_144 pass
14818 11:46:11.179264 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14819 11:46:11.179347 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14820 11:46:11.179432 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14821 11:46:11.179746 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14822 11:46:11.179843 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14823 11:46:11.179927 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14824 11:46:11.181884 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14825 11:46:11.182086 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14826 11:46:11.182172 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14827 11:46:11.182255 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14828 11:46:11.184638 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14829 11:46:11.184830 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14830 11:46:11.184919 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14831 11:46:11.185234 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14832 11:46:11.185326 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14833 11:46:11.185411 arm64_syscall-abi_getpid_SVE_VL_128 pass
14834 11:46:11.185502 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14835 11:46:11.185604 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14836 11:46:11.185702 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14837 11:46:11.185781 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14838 11:46:11.185863 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14839 11:46:11.185962 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14840 11:46:11.186047 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14841 11:46:11.186154 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14842 11:46:11.186244 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14843 11:46:11.186349 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14844 11:46:11.186438 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14845 11:46:11.186752 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14846 11:46:11.186860 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14847 11:46:11.186950 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14848 11:46:11.187053 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14849 11:46:11.187142 arm64_syscall-abi_getpid_SVE_VL_112 pass
14850 11:46:11.187245 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14851 11:46:11.187333 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14852 11:46:11.187431 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14853 11:46:11.187532 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14854 11:46:11.187633 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14855 11:46:11.187926 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14856 11:46:11.188034 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14857 11:46:11.188137 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14858 11:46:11.192556 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14859 11:46:11.192799 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14860 11:46:11.192908 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14861 11:46:11.192994 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14862 11:46:11.193091 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14863 11:46:11.193177 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14864 11:46:11.193280 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14865 11:46:11.193368 arm64_syscall-abi_getpid_SVE_VL_96 pass
14866 11:46:11.193677 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14867 11:46:11.193778 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14868 11:46:11.193864 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14869 11:46:11.193964 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14870 11:46:11.194050 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14871 11:46:11.194146 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14872 11:46:11.194245 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14873 11:46:11.194341 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14874 11:46:11.194664 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14875 11:46:11.194769 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14876 11:46:11.194870 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14877 11:46:11.194957 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14878 11:46:11.195055 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14879 11:46:11.195139 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14880 11:46:11.195235 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14881 11:46:11.195334 arm64_syscall-abi_getpid_SVE_VL_80 pass
14882 11:46:11.195626 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14883 11:46:11.195722 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14884 11:46:11.195822 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14885 11:46:11.195925 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14886 11:46:11.200338 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14887 11:46:11.200848 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14888 11:46:11.200953 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14889 11:46:11.201042 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14890 11:46:11.201128 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14891 11:46:11.201228 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14892 11:46:11.201314 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14893 11:46:11.201399 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14894 11:46:11.201482 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14895 11:46:11.201580 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14896 11:46:11.201673 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14897 11:46:11.201773 arm64_syscall-abi_getpid_SVE_VL_64 pass
14898 11:46:11.201874 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14899 11:46:11.201977 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14900 11:46:11.202076 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14901 11:46:11.202391 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14902 11:46:11.202495 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14903 11:46:11.202598 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14904 11:46:11.202697 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14905 11:46:11.202796 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14906 11:46:11.202896 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14907 11:46:11.203005 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14908 11:46:11.203316 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14909 11:46:11.203410 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14910 11:46:11.203512 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14911 11:46:11.203618 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14912 11:46:11.203908 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14913 11:46:11.204001 arm64_syscall-abi_getpid_SVE_VL_48 pass
14914 11:46:11.204102 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14915 11:46:11.204196 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14916 11:46:11.208365 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14917 11:46:11.208907 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14918 11:46:11.209014 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14919 11:46:11.209104 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14920 11:46:11.209188 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14921 11:46:11.209275 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14922 11:46:11.209378 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14923 11:46:11.209467 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14924 11:46:11.209556 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14925 11:46:11.209666 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14926 11:46:11.209753 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14927 11:46:11.209851 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14928 11:46:11.209941 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14929 11:46:11.210042 arm64_syscall-abi_getpid_SVE_VL_32 pass
14930 11:46:11.210130 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14931 11:46:11.210230 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14932 11:46:11.210316 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14933 11:46:11.210416 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14934 11:46:11.210500 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14935 11:46:11.210596 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
14936 11:46:11.210693 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
14937 11:46:11.210779 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
14938 11:46:11.210876 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
14939 11:46:11.211198 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
14940 11:46:11.211301 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
14941 11:46:11.211401 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
14942 11:46:11.211489 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
14943 11:46:11.211589 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
14944 11:46:11.211678 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
14945 11:46:11.211774 arm64_syscall-abi_getpid_SVE_VL_16 pass
14946 11:46:11.211858 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
14947 11:46:11.211953 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
14948 11:46:11.224616 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
14949 11:46:11.225083 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
14950 11:46:11.225185 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
14951 11:46:11.225269 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
14952 11:46:11.225351 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
14953 11:46:11.225431 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
14954 11:46:11.225513 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
14955 11:46:11.225612 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
14956 11:46:11.225704 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
14957 11:46:11.225785 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
14958 11:46:11.225868 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
14959 11:46:11.225952 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
14960 11:46:11.226050 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
14961 11:46:11.226134 arm64_syscall-abi_sched_yield_FPSIMD pass
14962 11:46:11.226218 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
14963 11:46:11.226299 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
14964 11:46:11.226399 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
14965 11:46:11.226500 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
14966 11:46:11.226600 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
14967 11:46:11.226893 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
14968 11:46:11.227002 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
14969 11:46:11.227148 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
14970 11:46:11.227265 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
14971 11:46:11.227586 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
14972 11:46:11.227690 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
14973 11:46:11.227789 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
14974 11:46:11.227895 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
14975 11:46:11.232349 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
14976 11:46:11.232541 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
14977 11:46:11.232836 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
14978 11:46:11.232938 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
14979 11:46:11.233026 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
14980 11:46:11.233126 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
14981 11:46:11.233433 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
14982 11:46:11.233531 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
14983 11:46:11.233614 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
14984 11:46:11.233703 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
14985 11:46:11.233807 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
14986 11:46:11.233893 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
14987 11:46:11.234221 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
14988 11:46:11.234322 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
14989 11:46:11.234410 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
14990 11:46:11.234510 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
14991 11:46:11.234598 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
14992 11:46:11.234697 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
14993 11:46:11.234808 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
14994 11:46:11.235101 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
14995 11:46:11.235218 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
14996 11:46:11.235333 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
14997 11:46:11.235446 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
14998 11:46:11.235558 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
14999 11:46:11.235669 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
15000 11:46:11.235978 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
15001 11:46:11.236105 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
15002 11:46:11.240410 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
15003 11:46:11.240587 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
15004 11:46:11.240904 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
15005 11:46:11.241019 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
15006 11:46:11.241115 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
15007 11:46:11.241226 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
15008 11:46:11.241321 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
15009 11:46:11.241414 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
15010 11:46:11.241523 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
15011 11:46:11.241619 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
15012 11:46:11.241738 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
15013 11:46:11.241850 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
15014 11:46:11.241964 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
15015 11:46:11.242074 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
15016 11:46:11.242185 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
15017 11:46:11.242514 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
15018 11:46:11.242621 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
15019 11:46:11.242722 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
15020 11:46:11.242820 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
15021 11:46:11.243146 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
15022 11:46:11.243249 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
15023 11:46:11.243352 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
15024 11:46:11.243440 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
15025 11:46:11.243549 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
15026 11:46:11.243650 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
15027 11:46:11.243940 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
15028 11:46:11.244225 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
15029 11:46:11.248224 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
15030 11:46:11.248567 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
15031 11:46:11.248686 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
15032 11:46:11.248791 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
15033 11:46:11.248894 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
15034 11:46:11.249193 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
15035 11:46:11.249308 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
15036 11:46:11.249412 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
15037 11:46:11.249514 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
15038 11:46:11.249624 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
15039 11:46:11.249752 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
15040 11:46:11.250066 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
15041 11:46:11.250244 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
15042 11:46:11.250347 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
15043 11:46:11.250436 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
15044 11:46:11.250534 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
15045 11:46:11.250639 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
15046 11:46:11.250729 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
15047 11:46:11.250830 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
15048 11:46:11.250930 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
15049 11:46:11.251031 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
15050 11:46:11.251140 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
15051 11:46:11.251242 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
15052 11:46:11.251591 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
15053 11:46:11.251693 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
15054 11:46:11.251794 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
15055 11:46:11.251881 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
15056 11:46:11.251981 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
15057 11:46:11.252270 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
15058 11:46:11.256394 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
15059 11:46:11.256591 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
15060 11:46:11.256891 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
15061 11:46:11.256987 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
15062 11:46:11.257073 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
15063 11:46:11.257353 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
15064 11:46:11.257445 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
15065 11:46:11.257532 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
15066 11:46:11.257619 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
15067 11:46:11.257718 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
15068 11:46:11.257821 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
15069 11:46:11.257911 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
15070 11:46:11.257999 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
15071 11:46:11.258832 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
15072 11:46:11.258929 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
15073 11:46:11.259016 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
15074 11:46:11.259097 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
15075 11:46:11.259179 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
15076 11:46:11.259260 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
15077 11:46:11.259344 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
15078 11:46:11.259427 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
15079 11:46:11.259710 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
15080 11:46:11.259804 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
15081 11:46:11.259890 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
15082 11:46:11.259971 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
15083 11:46:11.260055 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
15084 11:46:11.260137 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
15085 11:46:11.260243 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
15086 11:46:11.260332 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
15087 11:46:11.260419 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
15088 11:46:11.272704 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
15089 11:46:11.273163 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
15090 11:46:11.273270 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
15091 11:46:11.273365 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
15092 11:46:11.273471 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
15093 11:46:11.273562 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
15094 11:46:11.273680 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
15095 11:46:11.273772 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
15096 11:46:11.273877 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
15097 11:46:11.273984 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
15098 11:46:11.274089 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
15099 11:46:11.274395 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
15100 11:46:11.274517 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
15101 11:46:11.274622 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
15102 11:46:11.274722 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
15103 11:46:11.274821 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
15104 11:46:11.274920 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
15105 11:46:11.275210 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
15106 11:46:11.275317 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
15107 11:46:11.275425 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
15108 11:46:11.275545 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
15109 11:46:11.275638 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
15110 11:46:11.275743 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
15111 11:46:11.275855 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
15112 11:46:11.276149 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
15113 11:46:11.280346 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
15114 11:46:11.280710 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
15115 11:46:11.280806 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
15116 11:46:11.280905 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
15117 11:46:11.280994 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
15118 11:46:11.281092 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
15119 11:46:11.281192 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
15120 11:46:11.281291 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
15121 11:46:11.281399 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
15122 11:46:11.281691 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
15123 11:46:11.281801 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
15124 11:46:11.281903 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
15125 11:46:11.282253 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
15126 11:46:11.282348 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
15127 11:46:11.282636 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
15128 11:46:11.282750 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
15129 11:46:11.282858 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
15130 11:46:11.282947 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
15131 11:46:11.283046 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
15132 11:46:11.283146 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
15133 11:46:11.283447 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
15134 11:46:11.283550 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
15135 11:46:11.283652 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
15136 11:46:11.283828 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
15137 11:46:11.283918 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
15138 11:46:11.284024 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
15139 11:46:11.288552 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
15140 11:46:11.288957 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
15141 11:46:11.289057 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
15142 11:46:11.289353 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
15143 11:46:11.289451 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
15144 11:46:11.289554 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
15145 11:46:11.289867 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
15146 11:46:11.289982 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
15147 11:46:11.290278 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
15148 11:46:11.290387 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
15149 11:46:11.290492 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
15150 11:46:11.290598 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
15151 11:46:11.290703 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
15152 11:46:11.291005 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
15153 11:46:11.291122 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
15154 11:46:11.291217 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
15155 11:46:11.291330 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
15156 11:46:11.291636 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
15157 11:46:11.291750 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
15158 11:46:11.292048 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
15159 11:46:11.296371 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
15160 11:46:11.296822 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
15161 11:46:11.296922 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
15162 11:46:11.297017 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
15163 11:46:11.297123 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
15164 11:46:11.297217 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
15165 11:46:11.297320 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
15166 11:46:11.297612 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
15167 11:46:11.297731 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
15168 11:46:11.298028 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
15169 11:46:11.298127 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
15170 11:46:11.298235 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
15171 11:46:11.298325 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
15172 11:46:11.298428 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
15173 11:46:11.298724 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
15174 11:46:11.298820 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
15175 11:46:11.298924 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
15176 11:46:11.299031 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
15177 11:46:11.299329 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
15178 11:46:11.299429 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
15179 11:46:11.299530 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
15180 11:46:11.299822 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15181 11:46:11.299919 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15182 11:46:11.300026 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15183 11:46:11.300319 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15184 11:46:11.304320 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15185 11:46:11.304743 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15186 11:46:11.304842 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15187 11:46:11.304947 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15188 11:46:11.305063 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15189 11:46:11.305157 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15190 11:46:11.305268 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15191 11:46:11.305553 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15192 11:46:11.305642 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15193 11:46:11.305923 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15194 11:46:11.306010 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15195 11:46:11.306278 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15196 11:46:11.306543 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15197 11:46:11.306629 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15198 11:46:11.306722 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15199 11:46:11.306979 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15200 11:46:11.307066 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15201 11:46:11.307331 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15202 11:46:11.307404 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15203 11:46:11.307499 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15204 11:46:11.307766 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15205 11:46:11.307838 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15206 11:46:11.308106 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15207 11:46:11.308209 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15208 11:46:11.308494 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15209 11:46:11.308580 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15210 11:46:11.312827 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15211 11:46:11.312980 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15212 11:46:11.313046 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15213 11:46:11.313323 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15214 11:46:11.313421 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15215 11:46:11.313519 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15216 11:46:11.313822 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15217 11:46:11.313911 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15218 11:46:11.314017 arm64_syscall-abi pass
15219 11:46:11.314140 arm64_tpidr2_default_value pass
15220 11:46:11.314228 arm64_tpidr2_write_read pass
15221 11:46:11.314318 arm64_tpidr2_write_sleep_read pass
15222 11:46:11.314403 arm64_tpidr2_write_fork_read pass
15223 11:46:11.314492 arm64_tpidr2_write_clone_read pass
15224 11:46:11.314583 arm64_tpidr2 pass
15225 11:46:11.330097 + ../../utils/send-to-lava.sh ./output/result.txt
15226 11:46:11.378031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15227 11:46:11.378956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15229 11:46:11.414020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15231 11:46:11.414428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15232 11:46:11.450257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15234 11:46:11.450717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15235 11:46:11.486579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15236 11:46:11.486977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15238 11:46:11.521892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15240 11:46:11.522309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15241 11:46:11.556438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15243 11:46:11.556866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15244 11:46:11.590971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15245 11:46:11.591472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15247 11:46:11.624750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15248 11:46:11.625223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15250 11:46:11.658854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15252 11:46:11.659419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15253 11:46:11.693386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15254 11:46:11.693875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15256 11:46:11.729627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15258 11:46:11.730106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15259 11:46:11.765138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15260 11:46:11.765632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15262 11:46:11.800041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15263 11:46:11.800536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15265 11:46:11.835703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15266 11:46:11.836189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15268 11:46:11.870617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15269 11:46:11.871060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15271 11:46:11.906451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15272 11:46:11.906882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15274 11:46:11.941613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15275 11:46:11.942114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15277 11:46:11.977419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15278 11:46:11.977912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15280 11:46:12.013458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15281 11:46:12.013901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15283 11:46:12.049511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15284 11:46:12.049958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15286 11:46:12.085791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15288 11:46:12.086253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15289 11:46:12.121912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15290 11:46:12.122316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15292 11:46:12.157717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15294 11:46:12.158189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15295 11:46:12.193793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15297 11:46:12.194201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15298 11:46:12.228942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15299 11:46:12.229349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15301 11:46:12.264468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15303 11:46:12.264902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15304 11:46:12.300092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15305 11:46:12.300503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15307 11:46:12.335462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15308 11:46:12.335935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15310 11:46:12.370389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15311 11:46:12.370846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15313 11:46:12.404960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15315 11:46:12.405517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15316 11:46:12.439484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15318 11:46:12.439951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15319 11:46:12.474012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15321 11:46:12.474481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15322 11:46:12.509128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15324 11:46:12.509836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15325 11:46:12.543912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15326 11:46:12.544463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15328 11:46:12.579768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15330 11:46:12.580224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15331 11:46:12.616376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15333 11:46:12.616844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15334 11:46:12.651071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15336 11:46:12.651548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15337 11:46:12.686132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15339 11:46:12.686603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15340 11:46:12.721716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15342 11:46:12.722191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15343 11:46:12.756856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15344 11:46:12.757334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15346 11:46:12.792037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15347 11:46:12.792521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15349 11:46:12.827842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15350 11:46:12.828304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15352 11:46:12.863713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15353 11:46:12.864188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15355 11:46:12.900386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15357 11:46:12.900856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15358 11:46:12.935849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15359 11:46:12.936294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15361 11:46:12.971269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15362 11:46:12.971713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15364 11:46:13.005443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15365 11:46:13.005954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15367 11:46:13.041162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15368 11:46:13.041687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15370 11:46:13.076702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15371 11:46:13.077193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15373 11:46:13.111588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15375 11:46:13.112196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15376 11:46:13.146635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15377 11:46:13.147077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15379 11:46:13.181907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15380 11:46:13.182334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15382 11:46:13.217619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15384 11:46:13.218255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15385 11:46:13.253377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15386 11:46:13.253786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15388 11:46:13.293606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15390 11:46:13.294091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15391 11:46:13.328563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15393 11:46:13.329135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15394 11:46:13.363520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15395 11:46:13.364077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15397 11:46:13.398282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15399 11:46:13.398752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15400 11:46:13.433757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15401 11:46:13.434190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15403 11:46:13.469041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15404 11:46:13.469484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15406 11:46:13.505562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15408 11:46:13.506053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15409 11:46:13.540312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15411 11:46:13.540772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15412 11:46:13.577061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15413 11:46:13.577507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15415 11:46:13.612647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15416 11:46:13.613089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15418 11:46:13.649280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15419 11:46:13.649784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15421 11:46:13.683604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15422 11:46:13.684106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15424 11:46:13.719524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15426 11:46:13.720192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15427 11:46:13.754248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15428 11:46:13.754733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15430 11:46:13.790076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15431 11:46:13.790557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15433 11:46:13.825794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15434 11:46:13.826207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15436 11:46:13.861655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15437 11:46:13.862044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15439 11:46:13.897866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15440 11:46:13.898253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15442 11:46:13.933122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15443 11:46:13.933587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15445 11:46:13.968516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15447 11:46:13.969100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15448 11:46:14.004017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15449 11:46:14.004440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15451 11:46:14.039293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15452 11:46:14.039738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15454 11:46:14.074892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15456 11:46:14.075489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15457 11:46:14.110637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15458 11:46:14.111049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15460 11:46:14.146361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15462 11:46:14.146805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15463 11:46:14.182154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15465 11:46:14.182705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15466 11:46:14.217584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15467 11:46:14.218034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15469 11:46:14.253242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15470 11:46:14.253693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15472 11:46:14.289446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15474 11:46:14.290009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15475 11:46:14.324531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15477 11:46:14.325099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15478 11:46:14.360210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15479 11:46:14.360655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15481 11:46:14.397041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15482 11:46:14.397590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15484 11:46:14.432810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15485 11:46:14.433282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15487 11:46:14.467849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15488 11:46:14.468241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15490 11:46:14.503942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15492 11:46:14.504488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15493 11:46:14.539955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15494 11:46:14.540389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15496 11:46:14.576984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15498 11:46:14.577434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15499 11:46:14.611106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15501 11:46:14.611716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15502 11:46:14.645855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15504 11:46:14.646332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15505 11:46:14.683147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15506 11:46:14.683574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15508 11:46:14.718758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15510 11:46:14.719232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15511 11:46:14.754682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15512 11:46:14.755120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15514 11:46:14.789901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15515 11:46:14.790318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15517 11:46:14.825582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15518 11:46:14.826002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15520 11:46:14.861782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15521 11:46:14.862201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15523 11:46:14.897538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15524 11:46:14.897961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15526 11:46:14.932845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15528 11:46:14.933305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15529 11:46:14.968164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15530 11:46:14.968620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15532 11:46:15.003096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15534 11:46:15.003564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15535 11:46:15.038141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15536 11:46:15.038626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15538 11:46:15.073747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15539 11:46:15.074235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15541 11:46:15.109300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15542 11:46:15.109765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15544 11:46:15.145484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15545 11:46:15.145958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15547 11:46:15.180633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15549 11:46:15.181201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15550 11:46:15.215763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15551 11:46:15.216245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15553 11:46:15.251247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15554 11:46:15.251706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15556 11:46:15.286775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15557 11:46:15.287239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15559 11:46:15.321995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15561 11:46:15.322460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15562 11:46:15.357633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15564 11:46:15.358206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15565 11:46:15.393740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15566 11:46:15.394197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15568 11:46:15.430038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15569 11:46:15.430461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15571 11:46:15.465848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15573 11:46:15.466410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15574 11:46:15.501346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15575 11:46:15.501807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15577 11:46:15.536689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15579 11:46:15.537243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15580 11:46:15.572430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15582 11:46:15.573001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15583 11:46:15.607349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15585 11:46:15.607925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15586 11:46:15.641660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15587 11:46:15.642132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15589 11:46:15.676732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15591 11:46:15.677279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15592 11:46:15.713731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15593 11:46:15.714190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15595 11:46:15.749703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15597 11:46:15.750066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15598 11:46:15.785353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15600 11:46:15.785719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15601 11:46:15.820989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15602 11:46:15.821405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15604 11:46:15.856612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15606 11:46:15.857080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15607 11:46:15.891317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15608 11:46:15.891794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15610 11:46:15.926241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15612 11:46:15.926813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15613 11:46:15.966609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15614 11:46:15.966993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15616 11:46:16.006338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15617 11:46:16.006756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15619 11:46:16.043276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15620 11:46:16.043711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15622 11:46:16.083271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15623 11:46:16.083689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15625 11:46:16.121793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15627 11:46:16.122250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15628 11:46:16.160041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15629 11:46:16.160511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15631 11:46:16.195588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15632 11:46:16.196064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15634 11:46:16.229959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15636 11:46:16.230566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15637 11:46:16.264213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15638 11:46:16.264632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15640 11:46:16.299822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15641 11:46:16.300319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15643 11:46:16.350788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15644 11:46:16.351327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15646 11:46:16.390489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15647 11:46:16.390927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15649 11:46:16.429722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15650 11:46:16.430132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15652 11:46:16.468083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15653 11:46:16.468505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15655 11:46:16.504034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15656 11:46:16.504456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15658 11:46:16.539382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15659 11:46:16.539796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15661 11:46:16.574233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15663 11:46:16.574883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15664 11:46:16.609737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15666 11:46:16.610372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15667 11:46:16.644859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15669 11:46:16.645496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15670 11:46:16.679298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15671 11:46:16.679726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15673 11:46:16.714404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15674 11:46:16.714894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15676 11:46:16.749675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15677 11:46:16.750159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15679 11:46:16.785410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15680 11:46:16.785931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15682 11:46:16.821210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15683 11:46:16.821690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15685 11:46:16.857097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15686 11:46:16.857512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15688 11:46:16.893638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15690 11:46:16.894091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15691 11:46:16.929558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15692 11:46:16.929974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15694 11:46:16.965299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15695 11:46:16.965780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15697 11:46:17.001205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15698 11:46:17.001700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15700 11:46:17.035412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15702 11:46:17.036064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15703 11:46:17.070529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15704 11:46:17.071016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15706 11:46:17.105797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15707 11:46:17.106211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15709 11:46:17.141500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15710 11:46:17.141953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15712 11:46:17.177665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15713 11:46:17.178093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15715 11:46:17.213092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15717 11:46:17.213630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15718 11:46:17.248479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15720 11:46:17.248992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15721 11:46:17.284320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15723 11:46:17.284842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15724 11:46:17.319930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15725 11:46:17.320309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15727 11:46:17.354951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15728 11:46:17.355384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15730 11:46:17.390493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15731 11:46:17.390928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15733 11:46:17.426003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15734 11:46:17.426444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15736 11:46:17.462495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15737 11:46:17.463044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15739 11:46:17.497452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15740 11:46:17.497938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15742 11:46:17.533150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15744 11:46:17.533873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15745 11:46:17.568172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15746 11:46:17.568583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15748 11:46:17.603462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15749 11:46:17.603901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15751 11:46:17.638980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15752 11:46:17.639427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15754 11:46:17.673726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15755 11:46:17.674141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15757 11:46:17.707797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15758 11:46:17.708204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15760 11:46:17.743120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15761 11:46:17.743574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15763 11:46:17.777656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15764 11:46:17.778085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15766 11:46:17.811632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15767 11:46:17.812032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15769 11:46:17.847397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15771 11:46:17.847835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15772 11:46:17.882417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15774 11:46:17.882842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15775 11:46:17.916539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15777 11:46:17.917060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15778 11:46:17.951584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15779 11:46:17.952017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15781 11:46:17.986310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15782 11:46:17.986743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15784 11:46:18.022713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15786 11:46:18.023183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15787 11:46:18.057705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15789 11:46:18.058165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15790 11:46:18.094689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15792 11:46:18.095148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15793 11:46:18.130225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15794 11:46:18.130641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15796 11:46:18.166004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15798 11:46:18.166457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15799 11:46:18.201890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15800 11:46:18.202309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15802 11:46:18.237707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15804 11:46:18.238170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15805 11:46:18.273267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15806 11:46:18.273684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15808 11:46:18.309682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15809 11:46:18.310101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15811 11:46:18.345404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15813 11:46:18.345872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15814 11:46:18.381620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15816 11:46:18.382274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15817 11:46:18.417037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15818 11:46:18.417452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15820 11:46:18.452534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15822 11:46:18.452983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15823 11:46:18.487095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15824 11:46:18.487527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15826 11:46:18.521593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15827 11:46:18.522030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15829 11:46:18.555886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15830 11:46:18.556257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15832 11:46:18.591767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15833 11:46:18.592232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15835 11:46:18.626235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15836 11:46:18.626665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15838 11:46:18.661605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15839 11:46:18.662033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15841 11:46:18.696484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15843 11:46:18.696939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15844 11:46:18.733064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15845 11:46:18.733478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15847 11:46:18.767184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15848 11:46:18.767628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15850 11:46:18.801450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15852 11:46:18.801929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15853 11:46:18.836236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15854 11:46:18.836715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15856 11:46:18.871850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15857 11:46:18.872329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15859 11:46:18.907384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15861 11:46:18.907955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15862 11:46:18.942204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15864 11:46:18.942842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15865 11:46:18.977645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15866 11:46:18.978092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15868 11:46:19.013319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15869 11:46:19.013774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15871 11:46:19.048295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15873 11:46:19.048763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15874 11:46:19.083088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15876 11:46:19.083541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15877 11:46:19.117399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15878 11:46:19.117832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15880 11:46:19.154061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15882 11:46:19.154634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15883 11:46:19.189470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15884 11:46:19.189912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15886 11:46:19.224860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15887 11:46:19.225270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15889 11:46:19.259747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15890 11:46:19.260159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15892 11:46:19.295030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15893 11:46:19.295483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15895 11:46:19.329940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15896 11:46:19.330410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15898 11:46:19.364088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15899 11:46:19.364528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15901 11:46:19.398585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15903 11:46:19.399167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15904 11:46:19.433707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15906 11:46:19.434137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15907 11:46:19.468495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15909 11:46:19.468912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15910 11:46:19.503377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15911 11:46:19.503764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15913 11:46:19.538542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15914 11:46:19.538933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15916 11:46:19.573716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15917 11:46:19.574103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15919 11:46:19.608931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15920 11:46:19.609321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15922 11:46:19.643984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15923 11:46:19.644373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15925 11:46:19.679284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15926 11:46:19.679699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15928 11:46:19.715074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15929 11:46:19.715495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15931 11:46:19.751156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15932 11:46:19.751545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15934 11:46:19.786355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15935 11:46:19.786774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
15937 11:46:19.821209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
15939 11:46:19.821677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
15940 11:46:19.855343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
15941 11:46:19.855822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
15943 11:46:19.889717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
15945 11:46:19.890166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
15946 11:46:19.924090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
15948 11:46:19.924563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
15949 11:46:19.958343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
15950 11:46:19.958791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
15952 11:46:19.993624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
15953 11:46:19.994099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
15955 11:46:20.027849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
15957 11:46:20.028466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
15958 11:46:20.062324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
15960 11:46:20.062899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
15961 11:46:20.096665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
15963 11:46:20.097310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
15964 11:46:20.132063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
15966 11:46:20.132743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
15967 11:46:20.167140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
15968 11:46:20.167547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
15970 11:46:20.202052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
15971 11:46:20.202536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
15973 11:46:20.237466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
15974 11:46:20.237859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
15976 11:46:20.273454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
15977 11:46:20.273841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
15979 11:46:20.308729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
15980 11:46:20.309124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
15982 11:46:20.343941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
15983 11:46:20.344329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
15985 11:46:20.379634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
15987 11:46:20.380063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
15988 11:46:20.414671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
15989 11:46:20.415103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
15991 11:46:20.449210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
15993 11:46:20.449761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
15994 11:46:20.483335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
15996 11:46:20.483888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
15997 11:46:20.517344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
15998 11:46:20.517776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
16000 11:46:20.552422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
16002 11:46:20.553003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
16003 11:46:20.586677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
16005 11:46:20.587206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
16006 11:46:20.621403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
16007 11:46:20.621818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
16009 11:46:20.656136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
16010 11:46:20.656564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
16012 11:46:20.690877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
16014 11:46:20.691479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
16015 11:46:20.725717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
16017 11:46:20.726177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
16018 11:46:20.760229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
16020 11:46:20.760697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
16021 11:46:20.795521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
16022 11:46:20.796031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
16024 11:46:20.830279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
16025 11:46:20.830758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
16027 11:46:20.864633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
16029 11:46:20.865198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
16030 11:46:20.899100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
16032 11:46:20.899641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
16033 11:46:20.933710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
16034 11:46:20.934130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
16036 11:46:20.969065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
16037 11:46:20.969477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
16039 11:46:21.004057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
16040 11:46:21.004550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
16042 11:46:21.039046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
16043 11:46:21.039597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
16045 11:46:21.073928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
16046 11:46:21.074330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
16048 11:46:21.109837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
16049 11:46:21.110243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
16051 11:46:21.144829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
16053 11:46:21.145163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
16054 11:46:21.179251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
16055 11:46:21.179618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
16057 11:46:21.213848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
16058 11:46:21.214281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
16060 11:46:21.249392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
16061 11:46:21.249887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
16063 11:46:21.285232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
16064 11:46:21.285682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
16066 11:46:21.321169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
16068 11:46:21.321829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
16069 11:46:21.356435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
16071 11:46:21.356902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
16072 11:46:21.391705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
16074 11:46:21.392183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
16075 11:46:21.426679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
16077 11:46:21.427330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
16078 11:46:21.464964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
16080 11:46:21.465613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
16081 11:46:21.499772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
16083 11:46:21.500364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
16084 11:46:21.534812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
16085 11:46:21.535276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
16087 11:46:21.569204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
16089 11:46:21.578648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
16090 11:46:21.613611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
16091 11:46:21.614031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
16093 11:46:21.648270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
16095 11:46:21.648727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
16096 11:46:21.683373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
16098 11:46:21.684032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
16099 11:46:21.718246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
16101 11:46:21.718697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
16102 11:46:21.753114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
16103 11:46:21.753524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
16105 11:46:21.787669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
16106 11:46:21.788084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
16108 11:46:21.822992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
16109 11:46:21.823384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
16111 11:46:21.857536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
16112 11:46:21.857943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
16114 11:46:21.891497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
16115 11:46:21.891881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
16117 11:46:21.925713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
16118 11:46:21.926155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
16120 11:46:21.960980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
16121 11:46:21.961351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
16123 11:46:21.995058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
16124 11:46:21.995450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
16126 11:46:22.029501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
16127 11:46:22.029984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
16129 11:46:22.063792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
16131 11:46:22.064502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
16132 11:46:22.098292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
16133 11:46:22.098781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
16135 11:46:22.133940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
16137 11:46:22.134362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
16138 11:46:22.168035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
16140 11:46:22.168499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
16141 11:46:22.202274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
16142 11:46:22.202741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
16144 11:46:22.236847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
16145 11:46:22.237269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
16147 11:46:22.271860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
16148 11:46:22.272342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
16150 11:46:22.306897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
16151 11:46:22.307366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
16153 11:46:22.342186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
16154 11:46:22.342652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
16156 11:46:22.377461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
16158 11:46:22.378046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
16159 11:46:22.411699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
16160 11:46:22.412197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
16162 11:46:22.447250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
16163 11:46:22.447703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
16165 11:46:22.481908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
16167 11:46:22.482438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
16168 11:46:22.516946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
16169 11:46:22.517366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
16171 11:46:22.552244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
16173 11:46:22.552775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
16174 11:46:22.587198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
16175 11:46:22.587657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
16177 11:46:22.621689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
16179 11:46:22.622263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
16180 11:46:22.656075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16182 11:46:22.656545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16183 11:46:22.690364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16185 11:46:22.690894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16186 11:46:22.725043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16188 11:46:22.725664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16189 11:46:22.759928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16191 11:46:22.760376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16192 11:46:22.795151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16194 11:46:22.795782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16195 11:46:22.829722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16197 11:46:22.830260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16198 11:46:22.863749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16199 11:46:22.864170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16201 11:46:22.899153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16202 11:46:22.899622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16204 11:46:22.933909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16205 11:46:22.934350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16207 11:46:22.969980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16208 11:46:22.970434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16210 11:46:23.005710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16211 11:46:23.006124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16213 11:46:23.040156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16214 11:46:23.040482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16216 11:46:23.074970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16218 11:46:23.075454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16219 11:46:23.110271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16220 11:46:23.110674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16222 11:46:23.182021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16224 11:46:23.182591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16225 11:46:23.229863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16226 11:46:23.230310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16228 11:46:23.264165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16229 11:46:23.264589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16231 11:46:23.298829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16233 11:46:23.299352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16234 11:46:23.333859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16236 11:46:23.334390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16237 11:46:23.368608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16239 11:46:23.369061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16240 11:46:23.404402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16242 11:46:23.404858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16243 11:46:23.440396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16245 11:46:23.440855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16246 11:46:23.474872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16247 11:46:23.475353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16249 11:46:23.509685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16250 11:46:23.510152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16252 11:46:23.544158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16254 11:46:23.544785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16255 11:46:23.578742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16256 11:46:23.579224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16258 11:46:23.613412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16260 11:46:23.613873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16261 11:46:23.647840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16263 11:46:23.648489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16264 11:46:23.682664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16265 11:46:23.683083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16267 11:46:23.717909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16268 11:46:23.718388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16270 11:46:23.752899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16272 11:46:23.753423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16273 11:46:23.786945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16274 11:46:23.787356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16276 11:46:23.822178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16277 11:46:23.822597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16279 11:46:23.857057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16280 11:46:23.857543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16282 11:46:23.891494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16283 11:46:23.891938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16285 11:46:23.927307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16287 11:46:23.927770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16288 11:46:23.962403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16290 11:46:23.963147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16291 11:46:23.997572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16292 11:46:23.998040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16294 11:46:24.032616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16296 11:46:24.033169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16297 11:46:24.067523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16298 11:46:24.067901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16300 11:46:24.102595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16302 11:46:24.103148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16303 11:46:24.137717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16305 11:46:24.138259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16306 11:46:24.172892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16307 11:46:24.173349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16309 11:46:24.207379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16311 11:46:24.207954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16312 11:46:24.241914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16314 11:46:24.242387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16315 11:46:24.278287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16316 11:46:24.278740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16318 11:46:24.314233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16320 11:46:24.314770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16321 11:46:24.349249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16322 11:46:24.349679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16324 11:46:24.384535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16326 11:46:24.385075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16327 11:46:24.418991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16329 11:46:24.419411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16330 11:46:24.453245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16331 11:46:24.453625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16333 11:46:24.487775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16334 11:46:24.488155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16336 11:46:24.522179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16337 11:46:24.522549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16339 11:46:24.557311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16341 11:46:24.557907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16342 11:46:24.591459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16343 11:46:24.591881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16345 11:46:24.626426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16346 11:46:24.626876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16348 11:46:24.661614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16350 11:46:24.662277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16351 11:46:24.696167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16352 11:46:24.696607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16354 11:46:24.730561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16355 11:46:24.731000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16357 11:46:24.765228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16358 11:46:24.765701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16360 11:46:24.799743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16361 11:46:24.800180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16363 11:46:24.835552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16365 11:46:24.836025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16366 11:46:24.869973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16367 11:46:24.870408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16369 11:46:24.904987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16370 11:46:24.905400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16372 11:46:24.939873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16373 11:46:24.940315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16375 11:46:24.974713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16376 11:46:24.975174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16378 11:46:25.009525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16379 11:46:25.009939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16381 11:46:25.044446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16383 11:46:25.044877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16384 11:46:25.078984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16386 11:46:25.079440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16387 11:46:25.113510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16389 11:46:25.113981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16390 11:46:25.148590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16392 11:46:25.149148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16393 11:46:25.183565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16395 11:46:25.184049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16396 11:46:25.218463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16398 11:46:25.219038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16399 11:46:25.253554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16401 11:46:25.254114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16402 11:46:25.295989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16404 11:46:25.296458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16405 11:46:25.330798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16406 11:46:25.331260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16408 11:46:25.365494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16410 11:46:25.366072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16411 11:46:25.399897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16412 11:46:25.400340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16414 11:46:25.434205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16415 11:46:25.434677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16417 11:46:25.468914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16419 11:46:25.469480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16420 11:46:25.502848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16421 11:46:25.503307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16423 11:46:25.536975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16425 11:46:25.537499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16426 11:46:25.570916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16427 11:46:25.571391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16429 11:46:25.605545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16431 11:46:25.606095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16432 11:46:25.639662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16434 11:46:25.640279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16435 11:46:25.674934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16437 11:46:25.675463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16438 11:46:25.713211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16439 11:46:25.713691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16441 11:46:25.748637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16443 11:46:25.749268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16444 11:46:25.783898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16445 11:46:25.784380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16447 11:46:25.818643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16449 11:46:25.819273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16450 11:46:25.853509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16451 11:46:25.853960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16453 11:46:25.887787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16455 11:46:25.888265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16456 11:46:25.922997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16457 11:46:25.923412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16459 11:46:25.958674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16461 11:46:25.959144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16462 11:46:25.994344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16463 11:46:25.994800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16465 11:46:26.031079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16466 11:46:26.031500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16468 11:46:26.068636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16470 11:46:26.069222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16471 11:46:26.104971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16472 11:46:26.105427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16474 11:46:26.141260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16475 11:46:26.141678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16477 11:46:26.177744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16478 11:46:26.178162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16480 11:46:26.213375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16482 11:46:26.213968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16483 11:46:26.248157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16484 11:46:26.248580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16486 11:46:26.282904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16488 11:46:26.283374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16489 11:46:26.317349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16490 11:46:26.317774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16492 11:46:26.352665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16494 11:46:26.353246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16495 11:46:26.387679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16497 11:46:26.388301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16498 11:46:26.421710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16499 11:46:26.422149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16501 11:46:26.457142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16502 11:46:26.457568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16504 11:46:26.491782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16505 11:46:26.492203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16507 11:46:26.527045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16508 11:46:26.527480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16510 11:46:26.562175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16512 11:46:26.562735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16513 11:46:26.596917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16514 11:46:26.597374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16516 11:46:26.631043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16517 11:46:26.631430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16519 11:46:26.665532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16521 11:46:26.665910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16522 11:46:26.700438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16524 11:46:26.700891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16525 11:46:26.735707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16526 11:46:26.736112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16528 11:46:26.770419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16529 11:46:26.770831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16531 11:46:26.805593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16532 11:46:26.806013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16534 11:46:26.840260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16536 11:46:26.840842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16537 11:46:26.875101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16539 11:46:26.875680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16540 11:46:26.909730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16541 11:46:26.910185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16543 11:46:26.944051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16544 11:46:26.944478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16546 11:46:26.978413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16547 11:46:26.978886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16549 11:46:27.013049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16550 11:46:27.013484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16552 11:46:27.047525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16554 11:46:27.048103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16555 11:46:27.082272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16557 11:46:27.082807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16558 11:46:27.116574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16560 11:46:27.116998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16561 11:46:27.150823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16562 11:46:27.151215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16564 11:46:27.185262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16565 11:46:27.185688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16567 11:46:27.219622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16569 11:46:27.220235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16570 11:46:27.254355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16572 11:46:27.254945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16573 11:46:27.289445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16575 11:46:27.289994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16576 11:46:27.324062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16577 11:46:27.324494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16579 11:46:27.358905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16581 11:46:27.359464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16582 11:46:27.393564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16583 11:46:27.393985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16585 11:46:27.428083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16586 11:46:27.428540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16588 11:46:27.462908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16590 11:46:27.463513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16591 11:46:27.497322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16592 11:46:27.497776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16594 11:46:27.532246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16595 11:46:27.532705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16597 11:46:27.567119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16598 11:46:27.567583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16600 11:46:27.603847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16601 11:46:27.604291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16603 11:46:27.642209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16605 11:46:27.642765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16606 11:46:27.679267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16607 11:46:27.679713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16609 11:46:27.716932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16611 11:46:27.717469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16612 11:46:27.758766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16614 11:46:27.759314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16615 11:46:27.802269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16617 11:46:27.802806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16618 11:46:27.837380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16620 11:46:27.837988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16621 11:46:27.872254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16623 11:46:27.872887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16624 11:46:27.907381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16625 11:46:27.907844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16627 11:46:27.942341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16629 11:46:27.942890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16630 11:46:27.977966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16631 11:46:27.978448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16633 11:46:28.013842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16634 11:46:28.014233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16636 11:46:28.049887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16637 11:46:28.050310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16639 11:46:28.088667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16640 11:46:28.089130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16642 11:46:28.124508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16644 11:46:28.124976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16645 11:46:28.159679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16646 11:46:28.160094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16648 11:46:28.194330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16649 11:46:28.194755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16651 11:46:28.229322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16652 11:46:28.229746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16654 11:46:28.265377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16655 11:46:28.265876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16657 11:46:28.300015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16658 11:46:28.300489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16660 11:46:28.334624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16661 11:46:28.335111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16663 11:46:28.368800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16665 11:46:28.369231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16666 11:46:28.402732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16668 11:46:28.403293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16669 11:46:28.439650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16670 11:46:28.440131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16672 11:46:28.475437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16673 11:46:28.475877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16675 11:46:28.510510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16677 11:46:28.511141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16678 11:46:28.544853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16680 11:46:28.545493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16681 11:46:28.579011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16683 11:46:28.579643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16684 11:46:28.613357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16685 11:46:28.613774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16687 11:46:28.647755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16688 11:46:28.648171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16690 11:46:28.682238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16691 11:46:28.682676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16693 11:46:28.717336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16695 11:46:28.718004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16696 11:46:28.751701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16697 11:46:28.752180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16699 11:46:28.786382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16701 11:46:28.786832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16702 11:46:28.820638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16704 11:46:28.821098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16705 11:46:28.855016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16707 11:46:28.855467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16708 11:46:28.889683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16709 11:46:28.890097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16711 11:46:28.924882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16713 11:46:28.925346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16714 11:46:28.959096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16715 11:46:28.959523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16717 11:46:28.994425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16718 11:46:28.994895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16720 11:46:29.027948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16721 11:46:29.028424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16723 11:46:29.062193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16724 11:46:29.062657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16726 11:46:29.097004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16728 11:46:29.097556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16729 11:46:29.131060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16731 11:46:29.131659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16732 11:46:29.166934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16734 11:46:29.167502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16735 11:46:29.201694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16737 11:46:29.202170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16738 11:46:29.235935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16740 11:46:29.236404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16741 11:46:29.270482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16742 11:46:29.270879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16744 11:46:29.304868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16746 11:46:29.305436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16747 11:46:29.339775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16749 11:46:29.340360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16750 11:46:29.373909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16751 11:46:29.374349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16753 11:46:29.408281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16755 11:46:29.408865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16756 11:46:29.444019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16757 11:46:29.444422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16759 11:46:29.478778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16761 11:46:29.479321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16762 11:46:29.512839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16763 11:46:29.513279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16765 11:46:29.548240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16766 11:46:29.548695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16768 11:46:29.584920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16769 11:46:29.585401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16771 11:46:29.618881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16773 11:46:29.619421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16774 11:46:29.653207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16776 11:46:29.653802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16777 11:46:29.686985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16778 11:46:29.687409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16780 11:46:29.721134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16781 11:46:29.721567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16783 11:46:29.755474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16785 11:46:29.756055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16786 11:46:29.790511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16788 11:46:29.790980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16789 11:46:29.824882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16790 11:46:29.825249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16792 11:46:29.859798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16793 11:46:29.860231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16795 11:46:29.894542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16796 11:46:29.894956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16798 11:46:29.928885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16799 11:46:29.929375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16801 11:46:29.965060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16802 11:46:29.965551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16804 11:46:29.999464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16805 11:46:29.999957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16807 11:46:30.034247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16809 11:46:30.034877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16810 11:46:30.068669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16812 11:46:30.069318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16813 11:46:30.103478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16814 11:46:30.103899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16816 11:46:30.137714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16817 11:46:30.138138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16819 11:46:30.173374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16820 11:46:30.173796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16822 11:46:30.208076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16824 11:46:30.208540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16825 11:46:30.243767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16826 11:46:30.244190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16828 11:46:30.277922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16829 11:46:30.278373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16831 11:46:30.312057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16832 11:46:30.312545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16834 11:46:30.346502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16835 11:46:30.346985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16837 11:46:30.381805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16838 11:46:30.382251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16840 11:46:30.417043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16841 11:46:30.417495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16843 11:46:30.452441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16845 11:46:30.452906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16846 11:46:30.487560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16847 11:46:30.487970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16849 11:46:30.521982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16850 11:46:30.522429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16852 11:46:30.557074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16853 11:46:30.557526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16855 11:46:30.591786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16857 11:46:30.592326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16858 11:46:30.626302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16859 11:46:30.626691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16861 11:46:30.662545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16863 11:46:30.663154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16864 11:46:30.697526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16865 11:46:30.698012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16867 11:46:30.731592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16869 11:46:30.732246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16870 11:46:30.765763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16872 11:46:30.766379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16873 11:46:30.800041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16875 11:46:30.800633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16876 11:46:30.834330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16877 11:46:30.834795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16879 11:46:30.868370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16881 11:46:30.868981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16882 11:46:30.902435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16883 11:46:30.902866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16885 11:46:30.937495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16886 11:46:30.937941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16888 11:46:30.973192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16889 11:46:30.973631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16891 11:46:31.009026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16893 11:46:31.009437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16894 11:46:31.043956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16895 11:46:31.044408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16897 11:46:31.079398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16898 11:46:31.079818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16900 11:46:31.114358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16901 11:46:31.114829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16903 11:46:31.149710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16904 11:46:31.150117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16906 11:46:31.185208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16908 11:46:31.185789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16909 11:46:31.218897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16911 11:46:31.219351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16912 11:46:31.253785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16913 11:46:31.254201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16915 11:46:31.288630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16916 11:46:31.289068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16918 11:46:31.322702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16919 11:46:31.323189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16921 11:46:31.357935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16923 11:46:31.358494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16924 11:46:31.392261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16926 11:46:31.392880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16927 11:46:31.430409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16929 11:46:31.430880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16930 11:46:31.465930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16932 11:46:31.466572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16933 11:46:31.501975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
16935 11:46:31.502609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16936 11:46:31.537581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
16937 11:46:31.538006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
16939 11:46:31.573213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
16940 11:46:31.573698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
16942 11:46:31.607825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
16944 11:46:31.608253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
16945 11:46:31.642588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
16947 11:46:31.643132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
16948 11:46:31.676962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
16950 11:46:31.677507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
16951 11:46:31.711340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
16952 11:46:31.711793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
16954 11:46:31.746168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
16956 11:46:31.746686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
16957 11:46:31.781692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
16959 11:46:31.782223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
16960 11:46:31.817792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
16962 11:46:31.818363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
16963 11:46:31.853111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
16965 11:46:31.853695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
16966 11:46:31.887405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
16968 11:46:31.887998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
16969 11:46:31.922614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
16971 11:46:31.923039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
16972 11:46:31.957455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
16973 11:46:31.957930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
16975 11:46:31.991828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
16977 11:46:31.992345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
16978 11:46:32.026154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
16979 11:46:32.026594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
16981 11:46:32.060202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
16982 11:46:32.060635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
16984 11:46:32.095297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
16985 11:46:32.095769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
16987 11:46:32.130685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
16988 11:46:32.131164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
16990 11:46:32.165729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
16991 11:46:32.166221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
16993 11:46:32.200134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
16995 11:46:32.200770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
16996 11:46:32.235188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
16997 11:46:32.235604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
16999 11:46:32.269680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
17001 11:46:32.270130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
17002 11:46:32.304299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
17004 11:46:32.304771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
17005 11:46:32.339489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
17007 11:46:32.339941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
17008 11:46:32.374175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
17009 11:46:32.374625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
17011 11:46:32.409085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
17013 11:46:32.409604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
17014 11:46:32.443973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
17015 11:46:32.444416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
17017 11:46:32.478071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
17018 11:46:32.478528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
17020 11:46:32.513509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
17021 11:46:32.513989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
17023 11:46:32.547682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
17024 11:46:32.548153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
17026 11:46:32.581950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
17028 11:46:32.582509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
17029 11:46:32.616013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
17031 11:46:32.616559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
17032 11:46:32.650754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
17034 11:46:32.651290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
17035 11:46:32.685550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
17037 11:46:32.686094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
17038 11:46:32.719329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
17040 11:46:32.719886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
17041 11:46:32.753737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
17042 11:46:32.754191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
17044 11:46:32.788033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
17046 11:46:32.788584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
17047 11:46:32.822399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
17049 11:46:32.822907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
17050 11:46:32.857447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
17052 11:46:32.858052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
17053 11:46:32.892547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
17055 11:46:32.892988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
17056 11:46:32.926616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
17057 11:46:32.927045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
17059 11:46:32.961601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
17060 11:46:32.962045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
17062 11:46:32.996487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
17064 11:46:32.996944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
17065 11:46:33.031135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
17067 11:46:33.031723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
17068 11:46:33.065828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
17070 11:46:33.066281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
17071 11:46:33.100835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
17072 11:46:33.101281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
17074 11:46:33.136117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
17075 11:46:33.136542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
17077 11:46:33.171547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
17078 11:46:33.171900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
17080 11:46:33.206594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
17082 11:46:33.206959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
17083 11:46:33.242094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
17084 11:46:33.242405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
17086 11:46:33.277113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
17087 11:46:33.277595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
17089 11:46:33.311680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
17091 11:46:33.312135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
17092 11:46:33.345612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
17093 11:46:33.346033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
17095 11:46:33.381050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
17096 11:46:33.381534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
17098 11:46:33.415621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
17100 11:46:33.416070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
17101 11:46:33.450525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
17103 11:46:33.450977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
17104 11:46:33.485453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
17105 11:46:33.485869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
17107 11:46:33.521049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
17108 11:46:33.521482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
17110 11:46:33.556716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
17111 11:46:33.557154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
17113 11:46:33.591814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
17114 11:46:33.592361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
17116 11:46:33.627661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
17117 11:46:33.628150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
17119 11:46:33.662823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
17121 11:46:33.663420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
17122 11:46:33.697971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
17124 11:46:33.698591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
17125 11:46:33.733570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
17126 11:46:33.734036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
17128 11:46:33.769155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
17130 11:46:33.769690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
17131 11:46:33.805091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
17133 11:46:33.805607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
17134 11:46:33.840051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
17135 11:46:33.840532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
17137 11:46:33.875082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
17138 11:46:33.875528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
17140 11:46:33.909979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
17141 11:46:33.910425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
17143 11:46:33.945207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
17145 11:46:33.945741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
17146 11:46:33.980249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
17147 11:46:33.980676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
17149 11:46:34.016872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
17150 11:46:34.017313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
17152 11:46:34.055931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
17153 11:46:34.056420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
17155 11:46:34.090596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
17156 11:46:34.091061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
17158 11:46:34.129977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
17160 11:46:34.130542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
17161 11:46:34.167313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
17163 11:46:34.167887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
17164 11:46:34.201334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
17165 11:46:34.201751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
17167 11:46:34.235760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
17169 11:46:34.236224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
17170 11:46:34.270084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
17172 11:46:34.270555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
17173 11:46:34.304825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
17175 11:46:34.305280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
17176 11:46:34.339314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
17178 11:46:34.339963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
17179 11:46:34.374734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
17180 11:46:34.375195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17182 11:46:34.413381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17183 11:46:34.413874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17185 11:46:34.450409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17187 11:46:34.450971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17188 11:46:34.484629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17190 11:46:34.485070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17191 11:46:34.519401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17193 11:46:34.519934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17194 11:46:34.554318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17195 11:46:34.554765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17197 11:46:34.589588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17198 11:46:34.590037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17200 11:46:34.624928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17201 11:46:34.625386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17203 11:46:34.660833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17205 11:46:34.661371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17206 11:46:34.695675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17207 11:46:34.696114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17209 11:46:34.731049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17210 11:46:34.731494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17212 11:46:34.765734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17213 11:46:34.766166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17215 11:46:34.800439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17217 11:46:34.801005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17218 11:46:34.835684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17220 11:46:34.836138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17221 11:46:34.870697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17223 11:46:34.871151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17224 11:46:34.906815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17225 11:46:34.907284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17227 11:46:34.943472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17228 11:46:34.943945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17230 11:46:34.978350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17231 11:46:34.978775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17233 11:46:35.013005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17234 11:46:35.013429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17236 11:46:35.047506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17237 11:46:35.047943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17239 11:46:35.081533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17240 11:46:35.081993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17242 11:46:35.115766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17243 11:46:35.116170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17245 11:46:35.150772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17246 11:46:35.151180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17248 11:46:35.185354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17249 11:46:35.185743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17251 11:46:35.219666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17253 11:46:35.220105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17254 11:46:35.254273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17255 11:46:35.254706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17257 11:46:35.289570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17258 11:46:35.290010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17260 11:46:35.323741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17261 11:46:35.324192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17263 11:46:35.358021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17264 11:46:35.358467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17266 11:46:35.392585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17268 11:46:35.393017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17269 11:46:35.426808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17270 11:46:35.427181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17272 11:46:35.461676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17274 11:46:35.462302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17275 11:46:35.496423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17277 11:46:35.496985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17278 11:46:35.530903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17280 11:46:35.531425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17281 11:46:35.565488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17283 11:46:35.566061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17284 11:46:35.599802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17285 11:46:35.600253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17287 11:46:35.633923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17288 11:46:35.634372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17290 11:46:35.668891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17291 11:46:35.669318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17293 11:46:35.703276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17294 11:46:35.703701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17296 11:46:35.737930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17297 11:46:35.738362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17299 11:46:35.773117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17300 11:46:35.773542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17302 11:46:35.807402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17303 11:46:35.807790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17305 11:46:35.842833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17306 11:46:35.843226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17308 11:46:35.879068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17310 11:46:35.879553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17311 11:46:35.914191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17313 11:46:35.914654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17314 11:46:35.948469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17316 11:46:35.949143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17317 11:46:35.983301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17319 11:46:35.983897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17320 11:46:36.017569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17321 11:46:36.018050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17323 11:46:36.051055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17324 11:46:36.051589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17326 11:46:36.085353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17328 11:46:36.086115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17329 11:46:36.119146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17331 11:46:36.119618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17332 11:46:36.157515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17333 11:46:36.157905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17335 11:46:36.190617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17336 11:46:36.191085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17338 11:46:36.222168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17340 11:46:36.222628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17341 11:46:36.253856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17343 11:46:36.254401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17344 11:46:36.284916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17345 11:46:36.285311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17347 11:46:36.315959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17348 11:46:36.316405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17350 11:46:36.346752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17352 11:46:36.347283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17353 11:46:36.379938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17354 11:46:36.380388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17356 11:46:36.416214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17357 11:46:36.416675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17359 11:46:36.452767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17361 11:46:36.453221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17362 11:46:36.486884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17363 11:46:36.487318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17365 11:46:36.521429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17366 11:46:36.521851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17368 11:46:36.558787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17369 11:46:36.559166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17371 11:46:36.591387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17372 11:46:36.591786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17374 11:46:36.622402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17375 11:46:36.622800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17377 11:46:36.655897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17378 11:46:36.656380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17380 11:46:36.688191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17382 11:46:36.688742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17383 11:46:36.720049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17385 11:46:36.720595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17386 11:46:36.751536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17387 11:46:36.751957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17389 11:46:36.782872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17390 11:46:36.783413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17392 11:46:36.814696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17394 11:46:36.815240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17395 11:46:36.846733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17397 11:46:36.847282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17398 11:46:36.878322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17399 11:46:36.878790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17401 11:46:36.909939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17403 11:46:36.910543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17404 11:46:36.943303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17406 11:46:36.943895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17407 11:46:36.974679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17409 11:46:36.975245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17410 11:46:37.005810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17411 11:46:37.006269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17413 11:46:37.037245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17414 11:46:37.037756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17416 11:46:37.068851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17417 11:46:37.069321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17419 11:46:37.102786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17420 11:46:37.103407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17422 11:46:37.135758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17423 11:46:37.136185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17425 11:46:37.169412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17426 11:46:37.169890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17428 11:46:37.214044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17429 11:46:37.214530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17431 11:46:37.251089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17433 11:46:37.251658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17434 11:46:37.284528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17436 11:46:37.285012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17437 11:46:37.316966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17438 11:46:37.317443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17440 11:46:37.347949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17441 11:46:37.348468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17443 11:46:37.379227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17445 11:46:37.379860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17446 11:46:37.410281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17447 11:46:37.410722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17449 11:46:37.441717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17450 11:46:37.442129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17452 11:46:37.473427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17453 11:46:37.473824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17455 11:46:37.504374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17457 11:46:37.504844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17458 11:46:37.535977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17459 11:46:37.536407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17461 11:46:37.567535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17462 11:46:37.567958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17464 11:46:37.598792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17466 11:46:37.599429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17467 11:46:37.630114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17469 11:46:37.630745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17470 11:46:37.660997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17472 11:46:37.661633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17473 11:46:37.693690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17474 11:46:37.694106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17476 11:46:37.724932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17477 11:46:37.725416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17479 11:46:37.756173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17481 11:46:37.756793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17482 11:46:37.787310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17483 11:46:37.787778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17485 11:46:37.818737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17486 11:46:37.819198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17488 11:46:37.850145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17489 11:46:37.850548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17491 11:46:37.883338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17492 11:46:37.883891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17494 11:46:37.915231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17495 11:46:37.915680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17497 11:46:37.946398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17499 11:46:37.946943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17500 11:46:37.977420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17502 11:46:37.977976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17503 11:46:38.007882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17504 11:46:38.008343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17506 11:46:38.038809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17508 11:46:38.039441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17509 11:46:38.070205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17510 11:46:38.070646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17512 11:46:38.101659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17514 11:46:38.102201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17515 11:46:38.133533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17517 11:46:38.134130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17518 11:46:38.165249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17519 11:46:38.165691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17521 11:46:38.198392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17522 11:46:38.198849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17524 11:46:38.229346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17525 11:46:38.229807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17527 11:46:38.262844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17528 11:46:38.263325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17530 11:46:38.294718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17531 11:46:38.295211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17533 11:46:38.327842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17535 11:46:38.328304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17536 11:46:38.359903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17537 11:46:38.360402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17539 11:46:38.391123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17541 11:46:38.391699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17542 11:46:38.423554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17543 11:46:38.423980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17545 11:46:38.455532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17547 11:46:38.456146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17548 11:46:38.486555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17550 11:46:38.487127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17551 11:46:38.519156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17552 11:46:38.519614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17554 11:46:38.550603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17556 11:46:38.551155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17557 11:46:38.585292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17559 11:46:38.586062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17560 11:46:38.617820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17561 11:46:38.618306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17563 11:46:38.649602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17564 11:46:38.650061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17566 11:46:38.680525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17568 11:46:38.681069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17569 11:46:38.711873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17571 11:46:38.712411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17572 11:46:38.743694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17573 11:46:38.744154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17575 11:46:38.774392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17577 11:46:38.774832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17578 11:46:38.806078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17580 11:46:38.806624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17581 11:46:38.837440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17582 11:46:38.837844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17584 11:46:38.868997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17586 11:46:38.869537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17587 11:46:38.900823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17589 11:46:38.901353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17590 11:46:38.931633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17592 11:46:38.932159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17593 11:46:38.962637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17594 11:46:38.963060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17596 11:46:38.993539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17598 11:46:38.994159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17599 11:46:39.025125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17601 11:46:39.025751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17602 11:46:39.055683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17603 11:46:39.056131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17605 11:46:39.086400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17606 11:46:39.086862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17608 11:46:39.117404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17609 11:46:39.117874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17611 11:46:39.148836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17612 11:46:39.149300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17614 11:46:39.179658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17615 11:46:39.180120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17617 11:46:39.210988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17618 11:46:39.211456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17620 11:46:39.241726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17622 11:46:39.242274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17623 11:46:39.272299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17625 11:46:39.272847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17626 11:46:39.303727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17627 11:46:39.304173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17629 11:46:39.335180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17631 11:46:39.335810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17632 11:46:39.366857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17634 11:46:39.367470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17635 11:46:39.397769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17637 11:46:39.398325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17638 11:46:39.428574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17640 11:46:39.429127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17641 11:46:39.459572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17642 11:46:39.460010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17644 11:46:39.490570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17646 11:46:39.491148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17647 11:46:39.521557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17648 11:46:39.522027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17650 11:46:39.553341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17652 11:46:39.553924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17653 11:46:39.584408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17655 11:46:39.584993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17656 11:46:39.616932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17657 11:46:39.617389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17659 11:46:39.649463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17661 11:46:39.650038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17662 11:46:39.681393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17663 11:46:39.681787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17665 11:46:39.713445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17666 11:46:39.713847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17668 11:46:39.745432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17669 11:46:39.745890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17671 11:46:39.776981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17672 11:46:39.777425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17674 11:46:39.808980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17675 11:46:39.809375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17677 11:46:39.840298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17679 11:46:39.840755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17680 11:46:39.872306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17682 11:46:39.872763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17683 11:46:39.904714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17684 11:46:39.905147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17686 11:46:39.936763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17687 11:46:39.937202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17689 11:46:39.968216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17691 11:46:39.968665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17692 11:46:39.999772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17694 11:46:40.000230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17695 11:46:40.030827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17696 11:46:40.031310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17698 11:46:40.062287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17700 11:46:40.062749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17701 11:46:40.094624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17703 11:46:40.095107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17704 11:46:40.125103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17706 11:46:40.125571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17707 11:46:40.156068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17709 11:46:40.156657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17710 11:46:40.187397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17711 11:46:40.187884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17713 11:46:40.218384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17715 11:46:40.218958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17716 11:46:40.249152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17717 11:46:40.249568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17719 11:46:40.279751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17721 11:46:40.280221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17722 11:46:40.310706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17723 11:46:40.311191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17725 11:46:40.345194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17727 11:46:40.345841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17728 11:46:40.376167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17730 11:46:40.376730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17731 11:46:40.409040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17732 11:46:40.409529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17734 11:46:40.440932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17736 11:46:40.441400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17737 11:46:40.472202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17738 11:46:40.472683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17740 11:46:40.503948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17741 11:46:40.504418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17743 11:46:40.534673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17744 11:46:40.535065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17746 11:46:40.565300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17747 11:46:40.565776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17749 11:46:40.596635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17751 11:46:40.597110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17752 11:46:40.627671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17754 11:46:40.628289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17755 11:46:40.659383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17757 11:46:40.659845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17758 11:46:40.690856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17759 11:46:40.691269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17761 11:46:40.721995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17763 11:46:40.722458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17764 11:46:40.753174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17765 11:46:40.753579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17767 11:46:40.783489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17769 11:46:40.783963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17770 11:46:40.814635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17772 11:46:40.815111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17773 11:46:40.845686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17774 11:46:40.846109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17776 11:46:40.876593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17778 11:46:40.877061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17779 11:46:40.907846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17780 11:46:40.908331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17782 11:46:40.940812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17784 11:46:40.941259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17785 11:46:40.972882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17786 11:46:40.973266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17788 11:46:41.005227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17789 11:46:41.005670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17791 11:46:41.038118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17793 11:46:41.038714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17794 11:46:41.070104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17795 11:46:41.070580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17797 11:46:41.102439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17799 11:46:41.103004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17800 11:46:41.134718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17801 11:46:41.135143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17803 11:46:41.167462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17805 11:46:41.167930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17806 11:46:41.200258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17808 11:46:41.200731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17809 11:46:41.231915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17810 11:46:41.232319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17812 11:46:41.263164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17814 11:46:41.263608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17815 11:46:41.299695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17816 11:46:41.300117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17818 11:46:41.331907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17819 11:46:41.332336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17821 11:46:41.364521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17823 11:46:41.365128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17824 11:46:41.398987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17825 11:46:41.399467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17827 11:46:41.432906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17829 11:46:41.433493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17830 11:46:41.467107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17831 11:46:41.467553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17833 11:46:41.501845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17834 11:46:41.502322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17836 11:46:41.537099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17837 11:46:41.537540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17839 11:46:41.570207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17840 11:46:41.570689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17842 11:46:41.601644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17843 11:46:41.602073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17845 11:46:41.633072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17847 11:46:41.633718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17848 11:46:41.664190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17849 11:46:41.664662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17851 11:46:41.696361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17853 11:46:41.697007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17854 11:46:41.728545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17856 11:46:41.729031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17857 11:46:41.775739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17858 11:46:41.776165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17860 11:46:41.813566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17862 11:46:41.814041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17863 11:46:41.850072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17864 11:46:41.850495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17866 11:46:41.885362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17867 11:46:41.885770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17869 11:46:41.919540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17870 11:46:41.919934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17872 11:46:41.953802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17873 11:46:41.954238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17875 11:46:41.988133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17876 11:46:41.988643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17878 11:46:42.022496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17879 11:46:42.022971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17881 11:46:42.058133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17883 11:46:42.058702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17884 11:46:42.093939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17886 11:46:42.094493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17887 11:46:42.129315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17888 11:46:42.129783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17890 11:46:42.164184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17891 11:46:42.164613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17893 11:46:42.198972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17894 11:46:42.199396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17896 11:46:42.233715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17897 11:46:42.234121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17899 11:46:42.268485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17901 11:46:42.268906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17902 11:46:42.303277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17904 11:46:42.303875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17905 11:46:42.337979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17906 11:46:42.338417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17908 11:46:42.372104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17910 11:46:42.372646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17911 11:46:42.406715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17912 11:46:42.407128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17914 11:46:42.441425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17916 11:46:42.442045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17917 11:46:42.476412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17919 11:46:42.477008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17920 11:46:42.511080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17921 11:46:42.511581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17923 11:46:42.547168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17924 11:46:42.547623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17926 11:46:42.582602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17928 11:46:42.583079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17929 11:46:42.617713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17931 11:46:42.618176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17932 11:46:42.652507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17934 11:46:42.652981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17935 11:46:42.688795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
17936 11:46:42.689252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
17938 11:46:42.723332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
17939 11:46:42.723797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
17941 11:46:42.758310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
17942 11:46:42.758693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
17944 11:46:42.793464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
17945 11:46:42.793964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
17947 11:46:42.828885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
17949 11:46:42.829358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
17950 11:46:42.863459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
17952 11:46:42.864075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
17953 11:46:42.898752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
17955 11:46:42.899218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
17956 11:46:42.933791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
17958 11:46:42.934247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
17959 11:46:42.968303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
17961 11:46:42.968755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
17962 11:46:43.003833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
17964 11:46:43.004302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
17965 11:46:43.039192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
17967 11:46:43.039645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
17968 11:46:43.074423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
17970 11:46:43.074876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
17971 11:46:43.109936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
17972 11:46:43.110377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
17974 11:46:43.145399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
17975 11:46:43.145896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
17977 11:46:43.179991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
17978 11:46:43.180508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
17980 11:46:43.215737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
17982 11:46:43.216308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
17983 11:46:43.250568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
17984 11:46:43.251042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
17986 11:46:43.285895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
17987 11:46:43.286355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
17989 11:46:43.321091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
17990 11:46:43.321526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
17992 11:46:43.355798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
17993 11:46:43.356250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
17995 11:46:43.390884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
17996 11:46:43.391376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
17998 11:46:43.425839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
17999 11:46:43.426316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
18001 11:46:43.461716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
18002 11:46:43.462193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
18004 11:46:43.496862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
18005 11:46:43.497334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
18007 11:46:43.532022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
18008 11:46:43.532461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
18010 11:46:43.567490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
18011 11:46:43.567946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
18013 11:46:43.604060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
18014 11:46:43.604503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
18016 11:46:43.640169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
18018 11:46:43.640702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
18019 11:46:43.675941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
18021 11:46:43.676518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
18022 11:46:43.711322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
18023 11:46:43.711727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
18025 11:46:43.746336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
18026 11:46:43.746729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
18028 11:46:43.780943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
18029 11:46:43.781378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
18031 11:46:43.817523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
18033 11:46:43.818317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
18034 11:46:43.852927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
18035 11:46:43.853413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
18037 11:46:43.888393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
18039 11:46:43.888861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
18040 11:46:43.924858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
18041 11:46:43.925281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
18043 11:46:43.961118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
18045 11:46:43.961571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
18046 11:46:43.996648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
18048 11:46:43.997103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
18049 11:46:44.033314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
18051 11:46:44.033787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
18052 11:46:44.069978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
18053 11:46:44.070459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
18055 11:46:44.105810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
18056 11:46:44.106303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
18058 11:46:44.141303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
18060 11:46:44.141930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
18061 11:46:44.176546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
18063 11:46:44.177157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
18064 11:46:44.212426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
18066 11:46:44.212886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
18067 11:46:44.247666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
18068 11:46:44.248077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
18070 11:46:44.282601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
18072 11:46:44.283166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
18073 11:46:44.317639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
18074 11:46:44.318061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
18076 11:46:44.353661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
18077 11:46:44.354114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
18079 11:46:44.388797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
18080 11:46:44.389283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
18082 11:46:44.423783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
18083 11:46:44.424231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
18085 11:46:44.458319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
18086 11:46:44.458754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
18088 11:46:44.492327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
18090 11:46:44.492945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
18091 11:46:44.527515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
18093 11:46:44.527962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
18094 11:46:44.562075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
18096 11:46:44.562531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
18097 11:46:44.596368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
18098 11:46:44.596788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
18100 11:46:44.631125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
18101 11:46:44.631603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
18103 11:46:44.665710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
18105 11:46:44.666285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
18106 11:46:44.700066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
18108 11:46:44.700637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
18109 11:46:44.735501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
18110 11:46:44.735972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
18112 11:46:44.770224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
18113 11:46:44.770682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
18115 11:46:44.805258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
18116 11:46:44.805700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
18118 11:46:44.839822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
18119 11:46:44.840238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
18121 11:46:44.875307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
18122 11:46:44.875813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
18124 11:46:44.909983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
18125 11:46:44.910453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
18127 11:46:44.944726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
18128 11:46:44.945176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
18130 11:46:44.979541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
18132 11:46:44.980017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
18133 11:46:45.015163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
18134 11:46:45.015634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
18136 11:46:45.050655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
18137 11:46:45.051122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
18139 11:46:45.086798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
18141 11:46:45.087335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
18142 11:46:45.122295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
18143 11:46:45.122713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
18145 11:46:45.157848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
18146 11:46:45.158309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
18148 11:46:45.193137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
18149 11:46:45.193591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
18151 11:46:45.230142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
18153 11:46:45.230778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
18154 11:46:45.268547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
18156 11:46:45.269010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
18157 11:46:45.304344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
18159 11:46:45.304766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
18160 11:46:45.341248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
18161 11:46:45.341644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
18163 11:46:45.377553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
18164 11:46:45.377952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
18166 11:46:45.413175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
18167 11:46:45.413537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
18169 11:46:45.447843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
18170 11:46:45.448258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
18172 11:46:45.482649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
18174 11:46:45.483103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
18175 11:46:45.517158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
18177 11:46:45.517616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
18178 11:46:45.551484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18179 11:46:45.551915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
18181 11:46:45.586385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18183 11:46:45.586970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18184 11:46:45.620427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18186 11:46:45.620904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18187 11:46:45.655596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18189 11:46:45.656045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18190 11:46:45.690225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18191 11:46:45.690637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18193 11:46:45.724793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18194 11:46:45.725239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18196 11:46:45.758774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18198 11:46:45.759207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18199 11:46:45.793224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18201 11:46:45.793779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18202 11:46:45.827309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18204 11:46:45.827862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18205 11:46:45.863097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18206 11:46:45.863545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18208 11:46:45.898036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18209 11:46:45.898502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18211 11:46:45.933745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18212 11:46:45.934309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18214 11:46:45.969725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18216 11:46:45.970357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18217 11:46:46.004664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18219 11:46:46.005255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18220 11:46:46.039866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18221 11:46:46.040282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18223 11:46:46.076183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18224 11:46:46.076757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18226 11:46:46.114841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18227 11:46:46.115267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18229 11:46:46.152498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18231 11:46:46.153114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18232 11:46:46.189970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18233 11:46:46.190393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18235 11:46:46.226985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18237 11:46:46.227567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18238 11:46:46.262389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18240 11:46:46.262943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18241 11:46:46.297175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18242 11:46:46.297616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18244 11:46:46.331382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18245 11:46:46.331819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18247 11:46:46.365362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18248 11:46:46.365811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18250 11:46:46.399583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18251 11:46:46.400011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18253 11:46:46.436299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18255 11:46:46.436899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18256 11:46:46.472699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18258 11:46:46.473268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18259 11:46:46.509026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18260 11:46:46.509500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18262 11:46:46.544860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18263 11:46:46.545348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18265 11:46:46.579934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18266 11:46:46.580417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18268 11:46:46.614878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18269 11:46:46.615312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18271 11:46:46.649426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18272 11:46:46.649902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18274 11:46:46.683721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18275 11:46:46.684181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18277 11:46:46.718033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18278 11:46:46.718469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18280 11:46:46.752669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18282 11:46:46.753196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18283 11:46:46.787340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18285 11:46:46.787780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18286 11:46:46.821681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18288 11:46:46.822238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18289 11:46:46.855784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18290 11:46:46.856235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18292 11:46:46.890030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18294 11:46:46.890593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18295 11:46:46.924048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18296 11:46:46.924523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18298 11:46:46.958476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18300 11:46:46.959039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18301 11:46:46.993732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18302 11:46:46.994178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18304 11:46:47.028511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18306 11:46:47.029116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18307 11:46:47.062748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18309 11:46:47.063382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18310 11:46:47.097058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18311 11:46:47.097477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18313 11:46:47.130951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18314 11:46:47.131379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18316 11:46:47.165306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18317 11:46:47.165684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18319 11:46:47.200982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18321 11:46:47.201435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18322 11:46:47.235543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18324 11:46:47.235978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18325 11:46:47.269953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18326 11:46:47.270392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18328 11:46:47.305122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18329 11:46:47.305582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18331 11:46:47.339382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18332 11:46:47.339860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18334 11:46:47.373668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18335 11:46:47.374095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18337 11:46:47.407872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18339 11:46:47.408503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18340 11:46:47.442099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18342 11:46:47.442564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18343 11:46:47.476314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18345 11:46:47.476782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18346 11:46:47.511137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18348 11:46:47.511609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18349 11:46:47.545403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18351 11:46:47.545971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18352 11:46:47.579858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18354 11:46:47.580291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18355 11:46:47.614637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18356 11:46:47.615074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18358 11:46:47.649126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18359 11:46:47.649611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18361 11:46:47.683345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18363 11:46:47.683992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18364 11:46:47.717815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18365 11:46:47.718289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18367 11:46:47.751896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18368 11:46:47.752391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18370 11:46:47.786510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18371 11:46:47.786989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18373 11:46:47.820964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18374 11:46:47.821525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18376 11:46:47.855960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18377 11:46:47.856462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18379 11:46:47.894801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18380 11:46:47.895315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18382 11:46:47.930915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18383 11:46:47.931411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18385 11:46:47.966185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18386 11:46:47.966670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18388 11:46:48.002164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18390 11:46:48.002632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18391 11:46:48.037610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18392 11:46:48.038031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18394 11:46:48.070206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18395 11:46:48.070659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18397 11:46:48.103258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18398 11:46:48.103698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18400 11:46:48.133823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18401 11:46:48.134292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18403 11:46:48.165157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18404 11:46:48.165581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18406 11:46:48.196982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18407 11:46:48.197383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18409 11:46:48.230834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18410 11:46:48.231251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18412 11:46:48.264878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18413 11:46:48.265325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18415 11:46:48.296938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18416 11:46:48.297363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18418 11:46:48.327991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18419 11:46:48.328470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18421 11:46:48.358723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18423 11:46:48.359182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18424 11:46:48.390075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18425 11:46:48.390493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18427 11:46:48.421569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18428 11:46:48.421996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18430 11:46:48.452944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18431 11:46:48.453394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18433 11:46:48.483713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18434 11:46:48.484165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18436 11:46:48.514818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18438 11:46:48.515369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18439 11:46:48.545488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18440 11:46:48.545975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18442 11:46:48.577198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18443 11:46:48.577680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18445 11:46:48.608535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18447 11:46:48.609169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18448 11:46:48.639159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18450 11:46:48.639771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18451 11:46:48.670431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18453 11:46:48.671033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18454 11:46:48.701766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18455 11:46:48.702227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18457 11:46:48.732442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18459 11:46:48.733045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18460 11:46:48.763220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18461 11:46:48.763688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18463 11:46:48.794043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18465 11:46:48.794663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18466 11:46:48.825496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18468 11:46:48.826046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18469 11:46:48.857038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18470 11:46:48.857479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18472 11:46:48.887908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18473 11:46:48.888350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18475 11:46:48.919255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18477 11:46:48.919783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18478 11:46:48.950711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18480 11:46:48.951346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18481 11:46:48.982054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18482 11:46:48.982533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18484 11:46:49.013311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18486 11:46:49.013943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18487 11:46:49.044885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18488 11:46:49.045353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18490 11:46:49.076920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18491 11:46:49.077335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18493 11:46:49.108944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18494 11:46:49.109372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18496 11:46:49.139972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18497 11:46:49.140397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18499 11:46:49.171315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18500 11:46:49.171734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18502 11:46:49.202170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18503 11:46:49.202587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18505 11:46:49.234382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18506 11:46:49.234808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18508 11:46:49.265597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18509 11:46:49.266080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18511 11:46:49.298025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18513 11:46:49.298674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18514 11:46:49.328355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18516 11:46:49.328840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18517 11:46:49.358909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18519 11:46:49.359367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18520 11:46:49.389766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18522 11:46:49.390233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18523 11:46:49.421213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18524 11:46:49.421676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18526 11:46:49.451906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18527 11:46:49.452454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18529 11:46:49.483138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18530 11:46:49.483631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18532 11:46:49.513711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18534 11:46:49.514293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18535 11:46:49.545033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18536 11:46:49.545509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18538 11:46:49.576152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18539 11:46:49.576565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18541 11:46:49.607956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18543 11:46:49.608421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18544 11:46:49.639129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18546 11:46:49.639577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18547 11:46:49.670640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18548 11:46:49.671054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18550 11:46:49.702704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18551 11:46:49.703103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18553 11:46:49.734261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18554 11:46:49.734657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18556 11:46:49.765588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18558 11:46:49.766020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18559 11:46:49.797000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18560 11:46:49.797443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18562 11:46:49.827664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18563 11:46:49.828136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18565 11:46:49.858872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18566 11:46:49.859364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18568 11:46:49.890040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18569 11:46:49.890504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18571 11:46:49.921779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18572 11:46:49.922256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18574 11:46:49.953216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18575 11:46:49.953694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18577 11:46:49.985043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18578 11:46:49.985502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18580 11:46:50.016579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18582 11:46:50.017106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18583 11:46:50.047085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18584 11:46:50.047514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18586 11:46:50.078542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18588 11:46:50.079112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18589 11:46:50.110364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18590 11:46:50.110815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18592 11:46:50.141668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18594 11:46:50.142287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18595 11:46:50.172964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18596 11:46:50.173424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18598 11:46:50.204939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18600 11:46:50.205375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18601 11:46:50.236846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18603 11:46:50.237454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18604 11:46:50.268783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18605 11:46:50.269218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18607 11:46:50.300101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18608 11:46:50.300539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18610 11:46:50.331028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18612 11:46:50.331681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18613 11:46:50.361696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18615 11:46:50.362157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18616 11:46:50.393523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18617 11:46:50.393950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18619 11:46:50.425263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18620 11:46:50.425689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18622 11:46:50.457798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18624 11:46:50.458269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18625 11:46:50.489453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18626 11:46:50.489889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18628 11:46:50.522612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18629 11:46:50.523102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18631 11:46:50.554408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18632 11:46:50.554827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18634 11:46:50.586800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18635 11:46:50.587237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18637 11:46:50.617913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18638 11:46:50.618362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18640 11:46:50.648829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18641 11:46:50.649263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18643 11:46:50.680343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18645 11:46:50.680893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18646 11:46:50.713251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18647 11:46:50.713746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18649 11:46:50.744037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18651 11:46:50.744684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18652 11:46:50.775141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18653 11:46:50.775621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18655 11:46:50.806053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18657 11:46:50.806632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18658 11:46:50.837294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18659 11:46:50.837682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18661 11:46:50.868258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18663 11:46:50.868731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18664 11:46:50.902732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18665 11:46:50.903162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18667 11:46:50.934254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18668 11:46:50.934682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18670 11:46:50.965655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18671 11:46:50.966082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18673 11:46:50.996575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18675 11:46:50.997164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18676 11:46:51.027343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18677 11:46:51.027815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18679 11:46:51.058995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18680 11:46:51.059485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18682 11:46:51.103392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18684 11:46:51.103968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18685 11:46:51.145671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18687 11:46:51.146137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18688 11:46:51.187583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18689 11:46:51.187991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18691 11:46:51.237059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18692 11:46:51.237485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18694 11:46:51.269447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18695 11:46:51.269886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18697 11:46:51.300824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18698 11:46:51.301254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18700 11:46:51.331206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18701 11:46:51.331632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18703 11:46:51.362476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18705 11:46:51.363042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18706 11:46:51.393440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18707 11:46:51.393838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18709 11:46:51.424953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18710 11:46:51.425441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18712 11:46:51.458677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18713 11:46:51.459107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18715 11:46:51.497324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18716 11:46:51.497766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18718 11:46:51.530836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18720 11:46:51.531286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18721 11:46:51.566131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18722 11:46:51.566597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18724 11:46:51.601890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18725 11:46:51.602280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18727 11:46:51.635349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18728 11:46:51.635786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18730 11:46:51.667312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18732 11:46:51.667782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18733 11:46:51.698452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18734 11:46:51.698874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18736 11:46:51.729722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18738 11:46:51.730192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18739 11:46:51.761263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18740 11:46:51.761690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18742 11:46:51.792837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18744 11:46:51.793495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18745 11:46:51.823494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18747 11:46:51.823956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18748 11:46:51.854231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18750 11:46:51.854697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18751 11:46:51.885620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18753 11:46:51.886081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18754 11:46:51.917135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18755 11:46:51.917602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18757 11:46:51.949071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18758 11:46:51.949547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18760 11:46:51.980429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18762 11:46:51.980998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18763 11:46:52.011561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18764 11:46:52.012046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18766 11:46:52.044402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18768 11:46:52.045002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18769 11:46:52.077224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18770 11:46:52.077689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18772 11:46:52.107984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18774 11:46:52.108577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18775 11:46:52.138174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18776 11:46:52.138716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18778 11:46:52.169284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18779 11:46:52.169761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18781 11:46:52.202173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18782 11:46:52.202618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18784 11:46:52.234261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18786 11:46:52.234825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18787 11:46:52.266242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18788 11:46:52.266692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18790 11:46:52.297069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18791 11:46:52.297513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18793 11:46:52.327759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18795 11:46:52.328223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18796 11:46:52.358343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18797 11:46:52.358755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18799 11:46:52.388759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18801 11:46:52.389225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18802 11:46:52.419144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18803 11:46:52.419584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18805 11:46:52.449702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18807 11:46:52.450156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18808 11:46:52.479771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18809 11:46:52.480217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18811 11:46:52.511514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18812 11:46:52.511938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18814 11:46:52.542443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18815 11:46:52.542866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18817 11:46:52.573634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18819 11:46:52.574080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18820 11:46:52.604600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18822 11:46:52.605194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18823 11:46:52.643855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18824 11:46:52.644144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18826 11:46:52.682168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18828 11:46:52.682595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18829 11:46:52.718307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18830 11:46:52.718759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18832 11:46:52.754408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18833 11:46:52.754831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18835 11:46:52.790840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18836 11:46:52.791254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18838 11:46:52.826577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18840 11:46:52.827160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18841 11:46:52.862207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18842 11:46:52.862675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18844 11:46:52.897487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18846 11:46:52.898074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18847 11:46:52.932855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18848 11:46:52.933286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18850 11:46:52.968286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18852 11:46:52.968747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18853 11:46:53.003867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18854 11:46:53.004286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18856 11:46:53.039833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18857 11:46:53.040251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18859 11:46:53.075486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18861 11:46:53.075936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18862 11:46:53.110562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18864 11:46:53.111108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18865 11:46:53.145606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18866 11:46:53.146036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18868 11:46:53.181681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18869 11:46:53.182100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18871 11:46:53.216840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18872 11:46:53.217269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18874 11:46:53.252124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18875 11:46:53.252598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18877 11:46:53.287802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18878 11:46:53.288246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18880 11:46:53.323170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18882 11:46:53.323615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18883 11:46:53.358100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18884 11:46:53.358534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18886 11:46:53.393176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18888 11:46:53.393620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18889 11:46:53.428392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18891 11:46:53.429029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18892 11:46:53.463507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18893 11:46:53.464000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18895 11:46:53.498682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18896 11:46:53.499165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18898 11:46:53.534208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18899 11:46:53.534668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18901 11:46:53.569814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18902 11:46:53.570228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18904 11:46:53.605412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18905 11:46:53.605825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18907 11:46:53.641559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18909 11:46:53.642019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18910 11:46:53.676813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18911 11:46:53.677219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18913 11:46:53.712481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18915 11:46:53.712927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18916 11:46:53.748413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18918 11:46:53.748878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18919 11:46:53.784323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18921 11:46:53.784789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18922 11:46:53.820069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18923 11:46:53.820510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18925 11:46:53.868487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18927 11:46:53.868849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18928 11:46:53.905673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18929 11:46:53.906160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18931 11:46:53.940772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18932 11:46:53.941245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18934 11:46:53.975354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
18936 11:46:53.975980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18937 11:46:54.009725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
18938 11:46:54.010191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
18940 11:46:54.045600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
18941 11:46:54.046180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
18943 11:46:54.081305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
18944 11:46:54.081791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
18946 11:46:54.117226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
18947 11:46:54.117700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
18949 11:46:54.153323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
18951 11:46:54.153875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
18952 11:46:54.188957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
18953 11:46:54.189430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
18955 11:46:54.225094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
18957 11:46:54.225738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
18958 11:46:54.260375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
18960 11:46:54.261018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
18961 11:46:54.295876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
18963 11:46:54.296513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
18964 11:46:54.330849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
18965 11:46:54.331276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
18967 11:46:54.365827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
18969 11:46:54.366294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
18970 11:46:54.401716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
18972 11:46:54.402295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
18973 11:46:54.437994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
18975 11:46:54.438576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
18976 11:46:54.473641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
18977 11:46:54.474117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
18979 11:46:54.509567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
18980 11:46:54.510013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
18982 11:46:54.549129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
18983 11:46:54.549610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
18985 11:46:54.585197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
18987 11:46:54.585677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
18988 11:46:54.621457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
18990 11:46:54.621933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
18991 11:46:54.656611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
18993 11:46:54.657177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
18994 11:46:54.691640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
18995 11:46:54.692073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
18997 11:46:54.727649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
18999 11:46:54.728418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
19000 11:46:54.764313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
19001 11:46:54.764771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
19003 11:46:54.801592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
19005 11:46:54.802161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
19006 11:46:54.837210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
19007 11:46:54.837699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
19009 11:46:54.873046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
19010 11:46:54.873517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
19012 11:46:54.907827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
19014 11:46:54.908258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
19015 11:46:54.942624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
19016 11:46:54.943023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
19018 11:46:54.977608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
19019 11:46:54.978070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
19021 11:46:55.013627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
19022 11:46:55.014086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
19024 11:46:55.049482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
19026 11:46:55.050037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
19027 11:46:55.086094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
19029 11:46:55.086641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
19030 11:46:55.121401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
19032 11:46:55.121995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
19033 11:46:55.157031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
19034 11:46:55.157491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
19036 11:46:55.191919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
19037 11:46:55.192390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
19039 11:46:55.227465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
19040 11:46:55.227884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
19042 11:46:55.262632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
19043 11:46:55.263053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
19045 11:46:55.298254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
19047 11:46:55.298683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
19048 11:46:55.333953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
19049 11:46:55.334418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
19051 11:46:55.369500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
19053 11:46:55.370083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
19054 11:46:55.403783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
19056 11:46:55.404419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
19057 11:46:55.438362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
19058 11:46:55.438847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
19060 11:46:55.473582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
19061 11:46:55.473994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
19063 11:46:55.508057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
19065 11:46:55.508519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
19066 11:46:55.542925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
19067 11:46:55.543326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
19069 11:46:55.578543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
19070 11:46:55.579020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
19072 11:46:55.613800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
19073 11:46:55.614284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
19075 11:46:55.649155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
19076 11:46:55.649642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
19078 11:46:55.684937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
19079 11:46:55.685325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
19081 11:46:55.720134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
19082 11:46:55.720535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
19084 11:46:55.755904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
19085 11:46:55.756303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
19087 11:46:55.790841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
19088 11:46:55.791294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
19090 11:46:55.826310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
19091 11:46:55.826758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
19093 11:46:55.861718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
19095 11:46:55.862260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
19096 11:46:55.897525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
19097 11:46:55.897990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
19099 11:46:55.933484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
19100 11:46:55.933969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
19102 11:46:55.968907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
19104 11:46:55.969594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
19105 11:46:56.003745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
19106 11:46:56.004192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
19108 11:46:56.038432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
19109 11:46:56.038871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
19111 11:46:56.073522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
19113 11:46:56.074063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
19114 11:46:56.109745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
19116 11:46:56.110518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
19117 11:46:56.145987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
19118 11:46:56.146456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
19120 11:46:56.181471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
19121 11:46:56.181920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
19123 11:46:56.217632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
19124 11:46:56.218077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
19126 11:46:56.253529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
19128 11:46:56.254010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
19129 11:46:56.288587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
19131 11:46:56.289038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
19132 11:46:56.324901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
19134 11:46:56.325369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
19135 11:46:56.360118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
19137 11:46:56.360582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
19138 11:46:56.395811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
19139 11:46:56.396229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
19141 11:46:56.431491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
19142 11:46:56.431913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
19144 11:46:56.476129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
19145 11:46:56.476559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
19147 11:46:56.522510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
19148 11:46:56.522990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
19150 11:46:56.559969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
19151 11:46:56.560480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
19153 11:46:56.598126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
19154 11:46:56.598646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
19156 11:46:56.634927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
19157 11:46:56.635367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
19159 11:46:56.670031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
19160 11:46:56.670482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
19162 11:46:56.705719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
19163 11:46:56.706157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
19165 11:46:56.741759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
19166 11:46:56.742199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
19168 11:46:56.777601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
19169 11:46:56.778066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
19171 11:46:56.813833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
19173 11:46:56.814412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
19174 11:46:56.849734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
19176 11:46:56.850375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
19177 11:46:56.885302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
19178 11:46:56.885765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
19180 11:46:56.921210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19181 11:46:56.921707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19183 11:46:56.956117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19185 11:46:56.956657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19186 11:46:56.991642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19187 11:46:56.992036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19189 11:46:57.026651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19191 11:46:57.027090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19192 11:46:57.061811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19194 11:46:57.062349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19195 11:46:57.097629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19197 11:46:57.098185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19198 11:46:57.133702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19200 11:46:57.134244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19201 11:46:57.169900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19202 11:46:57.170320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19204 11:46:57.206061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19206 11:46:57.206518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19207 11:46:57.241999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19209 11:46:57.242429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19210 11:46:57.278205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19211 11:46:57.278674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19213 11:46:57.314691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19215 11:46:57.315322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19216 11:46:57.351393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19218 11:46:57.351857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19219 11:46:57.389128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19220 11:46:57.389562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19222 11:46:57.425264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19223 11:46:57.425690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19225 11:46:57.461829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19226 11:46:57.462251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19228 11:46:57.497790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19230 11:46:57.498259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19231 11:46:57.533259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19232 11:46:57.533696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19234 11:46:57.568928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19235 11:46:57.569395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19237 11:46:57.604721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19239 11:46:57.605275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19240 11:46:57.641008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19241 11:46:57.641462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19243 11:46:57.677124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19244 11:46:57.677604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19246 11:46:57.713308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19248 11:46:57.713890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19249 11:46:57.749730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19251 11:46:57.750331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19252 11:46:57.785410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19253 11:46:57.785899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19255 11:46:57.821498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19256 11:46:57.821991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19258 11:46:57.857653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19259 11:46:57.858065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19261 11:46:57.894320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19263 11:46:57.894769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19264 11:46:57.930231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19265 11:46:57.930643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19267 11:46:57.966374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19269 11:46:57.966826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19270 11:46:58.002002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19272 11:46:58.002451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19273 11:46:58.037733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19274 11:46:58.038183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19276 11:46:58.073669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19277 11:46:58.074052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19279 11:46:58.109333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19280 11:46:58.109747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19282 11:46:58.145438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19283 11:46:58.145866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19285 11:46:58.181686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19287 11:46:58.182259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19288 11:46:58.217599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19289 11:46:58.218073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19291 11:46:58.254245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19293 11:46:58.254934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19294 11:46:58.289958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19296 11:46:58.290527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19297 11:46:58.325556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19298 11:46:58.326030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19300 11:46:58.361657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19301 11:46:58.362063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19303 11:46:58.398134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19304 11:46:58.398554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19306 11:46:58.433741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19307 11:46:58.434167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19309 11:46:58.469831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19310 11:46:58.470256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19312 11:46:58.505782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19314 11:46:58.506257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19315 11:46:58.542157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19316 11:46:58.542599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19318 11:46:58.577718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19319 11:46:58.578135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19321 11:46:58.613722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19323 11:46:58.614204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19324 11:46:58.649029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19325 11:46:58.649622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19327 11:46:58.683980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19329 11:46:58.684447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19330 11:46:58.719564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19331 11:46:58.719949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19333 11:46:58.754703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19334 11:46:58.755103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19336 11:46:58.789810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19337 11:46:58.790283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19339 11:46:58.825531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19341 11:46:58.826006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19342 11:46:58.860573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19344 11:46:58.861220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19345 11:46:58.895480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19347 11:46:58.896039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19348 11:46:58.931084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19349 11:46:58.931562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19351 11:46:58.982210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19352 11:46:58.982592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19354 11:46:59.026702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19355 11:46:59.027162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19357 11:46:59.061933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19358 11:46:59.062398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19360 11:46:59.097266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19361 11:46:59.097695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19363 11:46:59.131431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19364 11:46:59.131869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19366 11:46:59.166795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19368 11:46:59.167246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19369 11:46:59.202528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19371 11:46:59.202976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19372 11:46:59.238642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19373 11:46:59.239030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19375 11:46:59.274716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19377 11:46:59.275152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19378 11:46:59.310156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19380 11:46:59.310602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19381 11:46:59.346539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19382 11:46:59.347004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19384 11:46:59.382279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19385 11:46:59.382764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19387 11:46:59.419127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19389 11:46:59.419588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19390 11:46:59.454505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19391 11:46:59.454980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19393 11:46:59.489718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19394 11:46:59.490142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19396 11:46:59.524557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19398 11:46:59.525200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19399 11:46:59.559495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19401 11:46:59.560074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19402 11:46:59.594808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19404 11:46:59.595380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19405 11:46:59.629991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19406 11:46:59.630459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19408 11:46:59.665425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19409 11:46:59.665898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19411 11:46:59.701750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19412 11:46:59.702193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19414 11:46:59.738161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19416 11:46:59.738767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19417 11:46:59.773260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19418 11:46:59.773693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19420 11:46:59.808158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19421 11:46:59.808573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19423 11:46:59.843582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19425 11:46:59.844037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19426 11:46:59.878584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19427 11:46:59.879017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19429 11:46:59.913795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19430 11:46:59.914211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19432 11:46:59.949585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19434 11:46:59.950185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19435 11:46:59.984982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19436 11:46:59.985547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19438 11:47:00.020516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19440 11:47:00.021120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19441 11:47:00.055365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19442 11:47:00.055778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19444 11:47:00.090194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19446 11:47:00.090656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19447 11:47:00.125230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19449 11:47:00.125705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19450 11:47:00.160136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19452 11:47:00.160601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19453 11:47:00.196046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19455 11:47:00.196508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19456 11:47:00.231834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19457 11:47:00.232254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19459 11:47:00.266992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19460 11:47:00.267458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19462 11:47:00.302850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19463 11:47:00.303306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19465 11:47:00.338268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19467 11:47:00.338798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19468 11:47:00.373791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19469 11:47:00.374215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19471 11:47:00.409284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19473 11:47:00.409819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19474 11:47:00.444345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19476 11:47:00.444887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19477 11:47:00.479953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19478 11:47:00.480389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19480 11:47:00.515958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19481 11:47:00.516450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19483 11:47:00.551596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19485 11:47:00.552136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19486 11:47:00.586770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19487 11:47:00.587229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19489 11:47:00.622418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19491 11:47:00.622969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19492 11:47:00.657708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19493 11:47:00.658159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19495 11:47:00.693453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19497 11:47:00.693996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19498 11:47:00.729484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19500 11:47:00.730087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19501 11:47:00.765699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19503 11:47:00.766242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19504 11:47:00.801258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19506 11:47:00.801821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19507 11:47:00.837119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19508 11:47:00.837588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19510 11:47:00.873127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19512 11:47:00.873679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19513 11:47:00.908623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19515 11:47:00.909238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19516 11:47:00.944229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19518 11:47:00.944749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19519 11:47:00.979848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19521 11:47:00.980444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19522 11:47:01.015417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19523 11:47:01.015880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19525 11:47:01.050894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19526 11:47:01.051317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19528 11:47:01.086551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19529 11:47:01.087111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19531 11:47:01.123664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19533 11:47:01.124033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19534 11:47:01.160696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19536 11:47:01.161266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19537 11:47:01.198991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19538 11:47:01.199453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19540 11:47:01.237462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19541 11:47:01.237892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19543 11:47:01.276250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19545 11:47:01.276712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19546 11:47:01.315603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19547 11:47:01.316063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19549 11:47:01.355265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19550 11:47:01.355744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19552 11:47:01.395593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19553 11:47:01.396052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19555 11:47:01.433128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19556 11:47:01.433582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19558 11:47:01.469480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19560 11:47:01.470047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19561 11:47:01.505640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19563 11:47:01.506278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19564 11:47:01.541338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19565 11:47:01.541836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19567 11:47:01.577126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19569 11:47:01.577693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19570 11:47:01.613053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19572 11:47:01.613510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19573 11:47:01.648970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19575 11:47:01.649443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19576 11:47:01.685354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19577 11:47:01.685755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19579 11:47:01.722113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19580 11:47:01.722533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19582 11:47:01.758200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19584 11:47:01.758665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19585 11:47:01.793821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19586 11:47:01.794232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19588 11:47:01.829689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19589 11:47:01.830152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19591 11:47:01.865289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19592 11:47:01.865769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19594 11:47:01.900916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19595 11:47:01.901391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19597 11:47:01.936433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19599 11:47:01.937030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19600 11:47:01.972926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19601 11:47:01.973398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19603 11:47:02.009898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19604 11:47:02.010335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19606 11:47:02.046187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19608 11:47:02.046637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19609 11:47:02.081630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19610 11:47:02.082057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19612 11:47:02.117220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19613 11:47:02.117639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19615 11:47:02.151238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19617 11:47:02.151673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19618 11:47:02.185872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19620 11:47:02.186317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19621 11:47:02.220477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19623 11:47:02.220950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19624 11:47:02.256547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19626 11:47:02.257002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19627 11:47:02.293427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19628 11:47:02.293870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19630 11:47:02.329346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19632 11:47:02.329809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19633 11:47:02.365460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19634 11:47:02.365890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19636 11:47:02.401426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19637 11:47:02.401818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19639 11:47:02.437379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19640 11:47:02.437800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19642 11:47:02.472796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19643 11:47:02.473234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19645 11:47:02.508160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19647 11:47:02.508630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19648 11:47:02.544104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19650 11:47:02.544574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19651 11:47:02.579844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19652 11:47:02.580341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19654 11:47:02.615887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19656 11:47:02.616375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19657 11:47:02.651331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19659 11:47:02.651792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19660 11:47:02.686978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19662 11:47:02.687598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19663 11:47:02.723084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19664 11:47:02.723522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19666 11:47:02.759348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19667 11:47:02.759797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19669 11:47:02.795167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19670 11:47:02.795588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19672 11:47:02.831998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19674 11:47:02.832591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19675 11:47:02.869335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19676 11:47:02.869803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19678 11:47:02.908045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19680 11:47:02.908675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19681 11:47:02.947709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19682 11:47:02.948165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19684 11:47:02.983224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19685 11:47:02.983678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19687 11:47:03.017033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19688 11:47:03.017464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19690 11:47:03.051084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19692 11:47:03.051654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19693 11:47:03.084983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19694 11:47:03.085458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19696 11:47:03.119297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19697 11:47:03.119808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19699 11:47:03.155240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19701 11:47:03.155836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19702 11:47:03.190435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19703 11:47:03.190892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19705 11:47:03.225951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19707 11:47:03.226512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19708 11:47:03.261837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19710 11:47:03.262391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19711 11:47:03.297152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19712 11:47:03.297614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19714 11:47:03.333241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19716 11:47:03.333982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19717 11:47:03.369969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19718 11:47:03.370434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19720 11:47:03.405728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19721 11:47:03.406210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19723 11:47:03.441997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19724 11:47:03.442481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19726 11:47:03.477739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19727 11:47:03.478199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19729 11:47:03.513242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19731 11:47:03.513712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19732 11:47:03.548133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19734 11:47:03.548685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19735 11:47:03.582960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19737 11:47:03.583540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19738 11:47:03.617212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19740 11:47:03.617677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19741 11:47:03.652399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19743 11:47:03.653016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19744 11:47:03.687744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19746 11:47:03.688433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19747 11:47:03.723213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19748 11:47:03.723665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19750 11:47:03.758287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19751 11:47:03.758748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19753 11:47:03.794156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19755 11:47:03.794724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19756 11:47:03.829817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19758 11:47:03.830375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19759 11:47:03.865069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19760 11:47:03.865542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19762 11:47:03.900421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19764 11:47:03.900886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19765 11:47:03.935896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19766 11:47:03.936357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19768 11:47:03.972308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19769 11:47:03.972749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19771 11:47:04.010513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19773 11:47:04.011039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19774 11:47:04.045724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19775 11:47:04.046142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19777 11:47:04.081896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19778 11:47:04.082308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19780 11:47:04.145841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19781 11:47:04.146324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19783 11:47:04.181511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19785 11:47:04.182156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19786 11:47:04.215938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19787 11:47:04.216424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19789 11:47:04.251046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19791 11:47:04.251602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19792 11:47:04.285834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19793 11:47:04.286310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19795 11:47:04.321672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19797 11:47:04.322267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19798 11:47:04.362744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19800 11:47:04.363312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19801 11:47:04.397888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19802 11:47:04.398346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19804 11:47:04.433279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19806 11:47:04.433843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19807 11:47:04.468022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19808 11:47:04.468506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19810 11:47:04.504407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19812 11:47:04.504874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19813 11:47:04.539957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19815 11:47:04.540429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19816 11:47:04.575692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19818 11:47:04.576275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19819 11:47:04.611493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19820 11:47:04.611905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19822 11:47:04.646842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19823 11:47:04.647281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19825 11:47:04.681959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19826 11:47:04.682459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19828 11:47:04.717259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19829 11:47:04.717654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19831 11:47:04.751979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19832 11:47:04.752414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19834 11:47:04.787063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19836 11:47:04.787520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19837 11:47:04.822695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19838 11:47:04.823124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19840 11:47:04.857796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19842 11:47:04.858251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19843 11:47:04.892489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19845 11:47:04.892949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19846 11:47:04.927302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19847 11:47:04.927745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19849 11:47:04.962674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19850 11:47:04.963143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19852 11:47:04.997629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19854 11:47:04.998204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19855 11:47:05.032050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19856 11:47:05.032469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19858 11:47:05.066599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19859 11:47:05.067075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19861 11:47:05.101155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19862 11:47:05.101627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19864 11:47:05.136234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19866 11:47:05.136785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19867 11:47:05.172190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19869 11:47:05.172656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19870 11:47:05.207377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19872 11:47:05.207836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19873 11:47:05.241907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19874 11:47:05.242327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19876 11:47:05.276942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19877 11:47:05.277372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19879 11:47:05.311809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19880 11:47:05.312161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19882 11:47:05.346993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19883 11:47:05.347410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19885 11:47:05.381794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19886 11:47:05.382195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19888 11:47:05.416111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19889 11:47:05.416545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19891 11:47:05.451152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19893 11:47:05.451684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19894 11:47:05.485690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19895 11:47:05.486093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19897 11:47:05.520848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19899 11:47:05.521487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19900 11:47:05.555292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19901 11:47:05.555732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19903 11:47:05.589855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19904 11:47:05.590347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19906 11:47:05.624508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19908 11:47:05.624982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19909 11:47:05.661936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19910 11:47:05.662352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19912 11:47:05.696978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19913 11:47:05.697419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19915 11:47:05.731986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19916 11:47:05.732527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19918 11:47:05.767173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19920 11:47:05.767702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19921 11:47:05.801871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19922 11:47:05.802321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19924 11:47:05.837147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19926 11:47:05.837759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19927 11:47:05.871479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19928 11:47:05.871932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19930 11:47:05.905714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19931 11:47:05.906182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19933 11:47:05.940966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19934 11:47:05.941444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
19936 11:47:05.975574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
19937 11:47:05.976017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
19939 11:47:06.009432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
19940 11:47:06.009912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
19942 11:47:06.043250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
19944 11:47:06.043704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
19945 11:47:06.077874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
19947 11:47:06.078319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
19948 11:47:06.113145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
19950 11:47:06.113592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
19951 11:47:06.148854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
19952 11:47:06.149286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
19954 11:47:06.184084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
19955 11:47:06.184562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
19957 11:47:06.218621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
19958 11:47:06.219190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
19960 11:47:06.253717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
19962 11:47:06.254284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
19963 11:47:06.289526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
19965 11:47:06.290087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
19966 11:47:06.325533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
19968 11:47:06.326006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
19969 11:47:06.361762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
19970 11:47:06.362209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
19972 11:47:06.397069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
19973 11:47:06.397513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
19975 11:47:06.431301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
19976 11:47:06.431787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
19978 11:47:06.466625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
19979 11:47:06.467053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
19981 11:47:06.502263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
19982 11:47:06.502742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
19984 11:47:06.538007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
19986 11:47:06.538644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
19987 11:47:06.574141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
19988 11:47:06.574566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
19990 11:47:06.609713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
19992 11:47:06.610177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
19993 11:47:06.645283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
19995 11:47:06.645761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
19996 11:47:06.681419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
19998 11:47:06.681909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
19999 11:47:06.717263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
20000 11:47:06.717682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
20002 11:47:06.751999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
20003 11:47:06.752436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
20005 11:47:06.787691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
20006 11:47:06.788172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
20008 11:47:06.822931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
20009 11:47:06.823389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
20011 11:47:06.858408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
20012 11:47:06.858894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
20014 11:47:06.893660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
20016 11:47:06.894289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
20017 11:47:06.929335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
20018 11:47:06.929785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
20020 11:47:06.965102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
20022 11:47:06.965732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
20023 11:47:06.999898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
20024 11:47:07.000376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
20026 11:47:07.033128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
20028 11:47:07.033584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
20029 11:47:07.065624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
20030 11:47:07.066054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
20032 11:47:07.097301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
20034 11:47:07.097747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
20035 11:47:07.128043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
20036 11:47:07.128536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
20038 11:47:07.160825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
20040 11:47:07.161268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
20041 11:47:07.193431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
20042 11:47:07.193855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
20044 11:47:07.225500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
20046 11:47:07.225977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
20047 11:47:07.257701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
20049 11:47:07.258173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
20050 11:47:07.289712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
20052 11:47:07.290171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
20053 11:47:07.321525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
20054 11:47:07.321951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
20056 11:47:07.354208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
20057 11:47:07.354621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
20059 11:47:07.386176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
20060 11:47:07.386580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
20062 11:47:07.417703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
20063 11:47:07.418089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
20065 11:47:07.449194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
20067 11:47:07.449655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
20068 11:47:07.480189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
20069 11:47:07.480655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
20071 11:47:07.511217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
20072 11:47:07.511689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
20074 11:47:07.542575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
20076 11:47:07.543025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
20077 11:47:07.573716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
20078 11:47:07.574131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
20080 11:47:07.605352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
20081 11:47:07.605760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
20083 11:47:07.639288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
20084 11:47:07.639777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
20086 11:47:07.673309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
20087 11:47:07.673829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
20089 11:47:07.713834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
20090 11:47:07.714332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
20092 11:47:07.748364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
20094 11:47:07.748953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
20095 11:47:07.787317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
20096 11:47:07.787791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
20098 11:47:07.830026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
20100 11:47:07.830834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
20101 11:47:07.866456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
20102 11:47:07.866943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
20104 11:47:07.905397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
20105 11:47:07.905895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
20107 11:47:07.943842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
20108 11:47:07.944333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
20110 11:47:07.975383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
20111 11:47:07.975861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
20113 11:47:08.007213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
20114 11:47:08.007680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
20116 11:47:08.038771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
20118 11:47:08.039325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
20119 11:47:08.070202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
20120 11:47:08.070674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
20122 11:47:08.102302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
20123 11:47:08.102760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
20125 11:47:08.134766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
20126 11:47:08.135228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
20128 11:47:08.166995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
20129 11:47:08.167452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
20131 11:47:08.198677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
20133 11:47:08.199268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
20134 11:47:08.229793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
20135 11:47:08.230264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
20137 11:47:08.261935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
20138 11:47:08.262341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
20140 11:47:08.294520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
20141 11:47:08.294921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
20143 11:47:08.326453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
20144 11:47:08.326862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
20146 11:47:08.358476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
20148 11:47:08.358928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
20149 11:47:08.390565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
20150 11:47:08.390974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
20152 11:47:08.422644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
20154 11:47:08.423109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
20155 11:47:08.454364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
20157 11:47:08.454829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
20158 11:47:08.485821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
20159 11:47:08.486246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
20161 11:47:08.517289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
20162 11:47:08.517682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
20164 11:47:08.548854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
20165 11:47:08.549276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
20167 11:47:08.579563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
20169 11:47:08.580024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
20170 11:47:08.610383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
20171 11:47:08.610795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
20173 11:47:08.641344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
20174 11:47:08.641751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
20176 11:47:08.672161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
20178 11:47:08.672641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
20179 11:47:08.705173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
20180 11:47:08.705594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20182 11:47:08.735519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20183 11:47:08.735958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20185 11:47:08.766317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20187 11:47:08.766902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20188 11:47:08.797419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20189 11:47:08.797855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20191 11:47:08.827805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20192 11:47:08.828226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20194 11:47:08.859058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20195 11:47:08.859465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20197 11:47:08.889746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20198 11:47:08.890191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20200 11:47:08.921543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20202 11:47:08.922202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20203 11:47:08.953219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20204 11:47:08.953661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20206 11:47:08.985266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20208 11:47:08.985733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20209 11:47:09.016662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20211 11:47:09.017132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20212 11:47:09.047816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20213 11:47:09.048259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20215 11:47:09.078994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20216 11:47:09.079495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20218 11:47:09.110076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20219 11:47:09.110551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20221 11:47:09.142291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20222 11:47:09.142718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20224 11:47:09.173640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20225 11:47:09.174063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20227 11:47:09.210893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20228 11:47:09.211318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20230 11:47:09.258540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20232 11:47:09.259110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20233 11:47:09.289881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20235 11:47:09.290338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20236 11:47:09.321709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20237 11:47:09.322142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20239 11:47:09.353178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20240 11:47:09.353611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20242 11:47:09.385586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20244 11:47:09.386069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20245 11:47:09.417740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20247 11:47:09.418312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20248 11:47:09.450421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20249 11:47:09.450970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20251 11:47:09.482694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20253 11:47:09.483298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20254 11:47:09.514868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20255 11:47:09.515313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20257 11:47:09.546641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20258 11:47:09.547081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20260 11:47:09.578513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20261 11:47:09.578988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20263 11:47:09.610345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20264 11:47:09.610835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20266 11:47:09.642433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20267 11:47:09.642928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20269 11:47:09.676147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20270 11:47:09.676648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20272 11:47:09.709991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20273 11:47:09.710462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20275 11:47:09.742429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20277 11:47:09.743054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20278 11:47:09.773858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20279 11:47:09.774332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20281 11:47:09.806106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20282 11:47:09.806494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20284 11:47:09.838174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20286 11:47:09.838787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20287 11:47:09.869526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20289 11:47:09.870149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20290 11:47:09.901615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20292 11:47:09.902263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20293 11:47:09.933726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20295 11:47:09.934280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20296 11:47:09.965537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20298 11:47:09.966094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20299 11:47:09.997830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20300 11:47:09.998271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20302 11:47:10.029265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20304 11:47:10.029928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20305 11:47:10.060025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20306 11:47:10.060512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20308 11:47:10.092093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20310 11:47:10.092703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20311 11:47:10.123909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20313 11:47:10.124505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20314 11:47:10.155544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20315 11:47:10.155962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20317 11:47:10.187949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20318 11:47:10.188404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20320 11:47:10.219357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20322 11:47:10.219820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20323 11:47:10.250640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20325 11:47:10.251111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20326 11:47:10.282165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20327 11:47:10.282604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20329 11:47:10.314012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20330 11:47:10.314479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20332 11:47:10.346443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20333 11:47:10.346921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20335 11:47:10.377812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20337 11:47:10.378365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20338 11:47:10.409388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20339 11:47:10.409873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20341 11:47:10.441583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20342 11:47:10.442014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20344 11:47:10.473443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20345 11:47:10.473869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20347 11:47:10.504156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20348 11:47:10.504582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20350 11:47:10.535453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20352 11:47:10.535899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20353 11:47:10.566584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20355 11:47:10.567148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20356 11:47:10.597619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20357 11:47:10.598078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20359 11:47:10.628539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20361 11:47:10.629066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20362 11:47:10.659557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20364 11:47:10.660161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20365 11:47:10.690351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20367 11:47:10.690818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20368 11:47:10.722584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20369 11:47:10.723062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20371 11:47:10.754573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20373 11:47:10.755130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20374 11:47:10.785509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20376 11:47:10.786076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20377 11:47:10.816629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20379 11:47:10.817171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20380 11:47:10.848688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20382 11:47:10.849249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20383 11:47:10.880821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20385 11:47:10.881352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20386 11:47:10.911683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20387 11:47:10.912137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20389 11:47:10.943377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20391 11:47:10.943962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20392 11:47:10.975007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20393 11:47:10.975493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20395 11:47:11.006999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20397 11:47:11.007541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20398 11:47:11.038897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20399 11:47:11.039346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20401 11:47:11.071102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20403 11:47:11.071645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20404 11:47:11.102318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20405 11:47:11.102765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20407 11:47:11.133861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20408 11:47:11.134313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20410 11:47:11.167072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20412 11:47:11.167604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20413 11:47:11.198932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20415 11:47:11.199494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20416 11:47:11.233556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20418 11:47:11.234216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20419 11:47:11.269831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20421 11:47:11.270431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20422 11:47:11.306627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20424 11:47:11.307081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20425 11:47:11.343087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20427 11:47:11.343653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20428 11:47:11.378826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20429 11:47:11.379266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20431 11:47:11.414332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20433 11:47:11.414708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20434 11:47:11.449789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20436 11:47:11.450351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20437 11:47:11.485431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20438 11:47:11.485868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20440 11:47:11.521529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20441 11:47:11.522005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20443 11:47:11.557830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20444 11:47:11.558323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20446 11:47:11.593637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20448 11:47:11.594153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20449 11:47:11.629016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20450 11:47:11.629528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20452 11:47:11.664240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20453 11:47:11.664674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20455 11:47:11.699741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20456 11:47:11.700096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20458 11:47:11.734987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20459 11:47:11.735452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20461 11:47:11.769939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20462 11:47:11.770402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20464 11:47:11.806895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20465 11:47:11.807360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20467 11:47:11.843051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20468 11:47:11.843477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20470 11:47:11.878913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20471 11:47:11.879386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20473 11:47:11.914115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20474 11:47:11.914590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20476 11:47:11.948941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20478 11:47:11.949547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20479 11:47:11.983060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20481 11:47:11.983531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20482 11:47:12.017771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20483 11:47:12.018189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20485 11:47:12.051612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20487 11:47:12.052086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20488 11:47:12.085711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20490 11:47:12.086173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20491 11:47:12.121026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20492 11:47:12.121527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20494 11:47:12.156044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20496 11:47:12.156590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20497 11:47:12.191590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20498 11:47:12.192044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20500 11:47:12.226044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20501 11:47:12.226489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20503 11:47:12.261145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20505 11:47:12.261584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20506 11:47:12.296608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20508 11:47:12.297171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20509 11:47:12.332647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20511 11:47:12.333254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20512 11:47:12.367712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20514 11:47:12.368180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20515 11:47:12.402386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20516 11:47:12.402828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20518 11:47:12.437455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20520 11:47:12.437920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20521 11:47:12.472014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20522 11:47:12.472442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20524 11:47:12.507449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20525 11:47:12.507895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20527 11:47:12.543116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20528 11:47:12.543580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20530 11:47:12.578423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20531 11:47:12.578863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20533 11:47:12.613857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20534 11:47:12.614316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20536 11:47:12.650018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20537 11:47:12.650473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20539 11:47:12.685117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20540 11:47:12.685560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20542 11:47:12.720158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20543 11:47:12.720572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20545 11:47:12.755683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20547 11:47:12.756140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20548 11:47:12.790676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20549 11:47:12.791084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20551 11:47:12.825929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20553 11:47:12.826393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20554 11:47:12.861351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20555 11:47:12.861816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20557 11:47:12.897145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20558 11:47:12.897630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20560 11:47:12.933250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20562 11:47:12.933851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20563 11:47:12.969509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20565 11:47:12.970074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20566 11:47:13.004415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20568 11:47:13.004974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20569 11:47:13.040475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20571 11:47:13.041038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20572 11:47:13.075883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20573 11:47:13.076304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20575 11:47:13.111213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20576 11:47:13.111685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20578 11:47:13.146295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20580 11:47:13.146848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20581 11:47:13.181770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20583 11:47:13.182337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20584 11:47:13.217664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20585 11:47:13.218047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20587 11:47:13.254239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20588 11:47:13.254694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20590 11:47:13.289782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20592 11:47:13.290332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20593 11:47:13.325413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20595 11:47:13.325887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20596 11:47:13.360519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20598 11:47:13.360972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20599 11:47:13.395630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20600 11:47:13.396072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20602 11:47:13.430631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20603 11:47:13.431073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20605 11:47:13.466216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20606 11:47:13.466655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20608 11:47:13.501975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20610 11:47:13.502519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20611 11:47:13.537795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20612 11:47:13.538249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20614 11:47:13.573427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20615 11:47:13.573891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20617 11:47:13.609151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20618 11:47:13.609600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20620 11:47:13.645029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20621 11:47:13.645510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20623 11:47:13.680288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20625 11:47:13.680750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20626 11:47:13.715592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20627 11:47:13.716029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20629 11:47:13.751703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20631 11:47:13.752147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20632 11:47:13.786884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20634 11:47:13.787341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20635 11:47:13.822231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20637 11:47:13.822675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20638 11:47:13.857592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20639 11:47:13.858040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20641 11:47:13.892869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20643 11:47:13.893422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20644 11:47:13.927758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20645 11:47:13.928142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20647 11:47:13.963364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20648 11:47:13.963783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20650 11:47:14.000286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20651 11:47:14.000710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20653 11:47:14.033707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20654 11:47:14.034112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20656 11:47:14.067287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20658 11:47:14.067754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20659 11:47:14.100993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20661 11:47:14.101434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20662 11:47:14.133904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20663 11:47:14.134293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20665 11:47:14.167289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20667 11:47:14.167761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20668 11:47:14.200050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20670 11:47:14.200514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20671 11:47:14.233573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20673 11:47:14.234043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20674 11:47:14.267291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20676 11:47:14.267863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20677 11:47:14.301192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20678 11:47:14.301681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20680 11:47:14.355105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20681 11:47:14.355572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20683 11:47:14.390507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20684 11:47:14.390985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20686 11:47:14.422198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20687 11:47:14.422644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20689 11:47:14.455975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20691 11:47:14.456558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20692 11:47:14.487909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20694 11:47:14.488474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20695 11:47:14.520421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20697 11:47:14.521195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20698 11:47:14.553508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20699 11:47:14.554011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20701 11:47:14.586504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20703 11:47:14.587063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20704 11:47:14.619443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20705 11:47:14.619923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20707 11:47:14.651549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20708 11:47:14.652030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20710 11:47:14.685148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20712 11:47:14.685730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20713 11:47:14.717771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20714 11:47:14.718222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20716 11:47:14.751087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20718 11:47:14.751545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20719 11:47:14.782663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20721 11:47:14.783119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20722 11:47:14.813691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20723 11:47:14.814116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20725 11:47:14.845139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20726 11:47:14.845563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20728 11:47:14.875929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20729 11:47:14.876424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20731 11:47:14.906775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20732 11:47:14.907207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20734 11:47:14.937888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20736 11:47:14.938346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20737 11:47:14.968896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20738 11:47:14.969279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20740 11:47:14.999739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20741 11:47:15.000204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20743 11:47:15.030711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20745 11:47:15.031166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20746 11:47:15.062264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20747 11:47:15.062676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20749 11:47:15.093968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20750 11:47:15.094421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20752 11:47:15.125336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20754 11:47:15.125929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20755 11:47:15.157263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20757 11:47:15.157836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20758 11:47:15.188265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20760 11:47:15.188823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20761 11:47:15.220575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20763 11:47:15.221121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20764 11:47:15.251837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20765 11:47:15.252309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20767 11:47:15.289199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20769 11:47:15.289761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20770 11:47:15.326152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20772 11:47:15.326701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20773 11:47:15.358955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20775 11:47:15.359504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20776 11:47:15.391593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20777 11:47:15.392092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20779 11:47:15.423646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20780 11:47:15.424094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20782 11:47:15.455424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20783 11:47:15.455850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20785 11:47:15.487282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20786 11:47:15.487758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20788 11:47:15.519148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20789 11:47:15.519611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20791 11:47:15.551314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20793 11:47:15.551868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20794 11:47:15.583429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20795 11:47:15.583878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20797 11:47:15.615830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20799 11:47:15.616364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20800 11:47:15.647531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20801 11:47:15.647962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20803 11:47:15.679575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20804 11:47:15.680010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20806 11:47:15.711361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20807 11:47:15.711871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20809 11:47:15.743770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20811 11:47:15.744234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20812 11:47:15.776013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20814 11:47:15.776480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20815 11:47:15.808082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20817 11:47:15.808547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20818 11:47:15.839774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20820 11:47:15.840418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20821 11:47:15.871432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20822 11:47:15.871912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20824 11:47:15.903496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20825 11:47:15.903963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20827 11:47:15.935097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20828 11:47:15.935585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20830 11:47:15.967120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20832 11:47:15.967742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20833 11:47:15.998666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20834 11:47:15.999147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20836 11:47:16.030565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20838 11:47:16.031038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20839 11:47:16.062553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20840 11:47:16.062992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20842 11:47:16.095913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20843 11:47:16.096387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20845 11:47:16.128027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20846 11:47:16.128502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20848 11:47:16.159595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20849 11:47:16.160055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20851 11:47:16.192880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20853 11:47:16.193577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20854 11:47:16.224416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20856 11:47:16.224891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20857 11:47:16.256225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20858 11:47:16.256642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20860 11:47:16.288872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20861 11:47:16.289283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20863 11:47:16.321293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20865 11:47:16.321868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20866 11:47:16.354172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20867 11:47:16.354681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20869 11:47:16.386844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20871 11:47:16.387407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20872 11:47:16.419007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20874 11:47:16.419588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20875 11:47:16.451357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20876 11:47:16.451841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20878 11:47:16.482906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20880 11:47:16.483452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20881 11:47:16.519662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20882 11:47:16.520164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20884 11:47:16.564034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20885 11:47:16.564536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20887 11:47:16.598388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20889 11:47:16.598948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20890 11:47:16.641615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20891 11:47:16.642119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20893 11:47:16.676040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20895 11:47:16.676411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20896 11:47:16.708462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20898 11:47:16.708843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20899 11:47:16.740460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20901 11:47:16.741036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20902 11:47:16.772060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20904 11:47:16.772600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20905 11:47:16.803587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20906 11:47:16.804056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20908 11:47:16.836431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20910 11:47:16.836996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20911 11:47:16.869015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20912 11:47:16.869446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20914 11:47:16.901134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20915 11:47:16.901566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20917 11:47:16.932360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20919 11:47:16.932921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20920 11:47:16.964696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20921 11:47:16.965160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20923 11:47:16.996124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20924 11:47:16.996568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20926 11:47:17.028210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20928 11:47:17.028746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20929 11:47:17.060653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20931 11:47:17.061200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20932 11:47:17.093095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20934 11:47:17.093682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20935 11:47:17.125566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
20936 11:47:17.126007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
20938 11:47:17.158441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
20939 11:47:17.158885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
20941 11:47:17.190081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
20942 11:47:17.190503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
20944 11:47:17.221616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
20945 11:47:17.222077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
20947 11:47:17.253370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
20948 11:47:17.253871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
20950 11:47:17.285418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
20951 11:47:17.285849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
20953 11:47:17.319201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
20954 11:47:17.319618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
20956 11:47:17.353700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
20957 11:47:17.354114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
20959 11:47:17.386687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
20960 11:47:17.387183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
20962 11:47:17.420128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
20963 11:47:17.420597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
20965 11:47:17.454400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
20967 11:47:17.454863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
20968 11:47:17.489470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
20969 11:47:17.489986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
20971 11:47:17.523656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
20972 11:47:17.524150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
20974 11:47:17.557520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
20975 11:47:17.558001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
20977 11:47:17.593011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
20979 11:47:17.593588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
20980 11:47:17.626850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
20981 11:47:17.627313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
20983 11:47:17.661179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
20985 11:47:17.661820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
20986 11:47:17.693692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
20987 11:47:17.694163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
20989 11:47:17.726201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
20991 11:47:17.726835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
20992 11:47:17.757706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
20993 11:47:17.758180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
20995 11:47:17.789231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
20996 11:47:17.789700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
20998 11:47:17.821238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
21000 11:47:17.821878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
21001 11:47:17.852646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
21003 11:47:17.853266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
21004 11:47:17.885406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
21006 11:47:17.886045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
21007 11:47:17.917313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
21009 11:47:17.917939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
21010 11:47:17.949231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
21011 11:47:17.949700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
21013 11:47:17.981359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
21015 11:47:17.981987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
21016 11:47:18.013600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
21018 11:47:18.014071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
21019 11:47:18.045643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
21020 11:47:18.046072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
21022 11:47:18.077688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
21023 11:47:18.078157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
21025 11:47:18.109911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
21026 11:47:18.110367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
21028 11:47:18.141532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
21030 11:47:18.141987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
21031 11:47:18.172984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
21032 11:47:18.173402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
21034 11:47:18.204736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
21035 11:47:18.205159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
21037 11:47:18.236351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
21039 11:47:18.236819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
21040 11:47:18.268162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
21042 11:47:18.268629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
21043 11:47:18.303740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
21044 11:47:18.304194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
21046 11:47:18.336303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
21048 11:47:18.336762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
21049 11:47:18.368442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
21051 11:47:18.368907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
21052 11:47:18.401712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
21054 11:47:18.402167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
21055 11:47:18.433733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
21056 11:47:18.434178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
21058 11:47:18.465587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
21060 11:47:18.466066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
21061 11:47:18.497627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
21063 11:47:18.498113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
21064 11:47:18.528944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
21066 11:47:18.529421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
21067 11:47:18.559885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
21069 11:47:18.560547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
21070 11:47:18.591207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
21071 11:47:18.591662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
21073 11:47:18.622624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
21075 11:47:18.623258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
21076 11:47:18.654143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
21078 11:47:18.654610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
21079 11:47:18.685474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
21080 11:47:18.685910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
21082 11:47:18.716219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
21084 11:47:18.716681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
21085 11:47:18.748081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
21086 11:47:18.748557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
21088 11:47:18.778997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
21089 11:47:18.779414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
21091 11:47:18.810734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
21092 11:47:18.811209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
21094 11:47:18.842043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
21095 11:47:18.842512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
21097 11:47:18.873554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
21099 11:47:18.874200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
21100 11:47:18.905500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
21101 11:47:18.905985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
21103 11:47:18.941341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
21105 11:47:18.942116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
21106 11:47:18.976893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
21108 11:47:18.977462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
21109 11:47:19.008391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
21111 11:47:19.009048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
21112 11:47:19.040515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
21114 11:47:19.041141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
21115 11:47:19.071130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
21116 11:47:19.071563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
21118 11:47:19.105976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
21119 11:47:19.106390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
21121 11:47:19.138020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
21123 11:47:19.138476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
21124 11:47:19.170433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
21125 11:47:19.170830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
21127 11:47:19.202352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
21128 11:47:19.202798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
21130 11:47:19.233999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
21132 11:47:19.234473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
21133 11:47:19.266113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
21135 11:47:19.266587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
21136 11:47:19.297670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
21137 11:47:19.298147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
21139 11:47:19.329887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
21140 11:47:19.330383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
21142 11:47:19.361933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
21143 11:47:19.362400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
21145 11:47:19.394420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
21146 11:47:19.394893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
21148 11:47:19.426615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
21149 11:47:19.427025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
21151 11:47:19.482455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
21152 11:47:19.482861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
21154 11:47:19.514361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
21155 11:47:19.514823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
21157 11:47:19.545715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
21159 11:47:19.546161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
21160 11:47:19.577724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
21162 11:47:19.578321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
21163 11:47:19.609021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
21164 11:47:19.609484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
21166 11:47:19.640004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
21167 11:47:19.640450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
21169 11:47:19.671954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
21170 11:47:19.672407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
21172 11:47:19.702781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
21173 11:47:19.703271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
21175 11:47:19.733748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
21176 11:47:19.734243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
21178 11:47:19.765532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21180 11:47:19.766011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
21181 11:47:19.797688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21183 11:47:19.798157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21184 11:47:19.829140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21185 11:47:19.829566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21187 11:47:19.860207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21189 11:47:19.860795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21190 11:47:19.892263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21191 11:47:19.892744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21193 11:47:19.925890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21194 11:47:19.926307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21196 11:47:19.957555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21197 11:47:19.958073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21199 11:47:19.990091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21201 11:47:19.990717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21202 11:47:20.022637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21204 11:47:20.023236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21205 11:47:20.058648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21206 11:47:20.059211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21208 11:47:20.094658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21209 11:47:20.095118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21211 11:47:20.129976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21212 11:47:20.130433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21214 11:47:20.165826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21215 11:47:20.166239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21217 11:47:20.202042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21218 11:47:20.202510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21220 11:47:20.237788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21222 11:47:20.238426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21223 11:47:20.273234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21225 11:47:20.273812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21226 11:47:20.308120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21227 11:47:20.308561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21229 11:47:20.343308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21230 11:47:20.343781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21232 11:47:20.378698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21234 11:47:20.379248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21235 11:47:20.414257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21237 11:47:20.414831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21238 11:47:20.449690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21239 11:47:20.450149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21241 11:47:20.485614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21242 11:47:20.486088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21244 11:47:20.521385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21245 11:47:20.521868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21247 11:47:20.556946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21249 11:47:20.557507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21250 11:47:20.592891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21251 11:47:20.593350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21253 11:47:20.627823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21254 11:47:20.628261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21256 11:47:20.663165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21258 11:47:20.663770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21259 11:47:20.699518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21260 11:47:20.699930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21262 11:47:20.737716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21264 11:47:20.738168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21265 11:47:20.774419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21266 11:47:20.774855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21268 11:47:20.811984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21270 11:47:20.812455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21271 11:47:20.849096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21273 11:47:20.849547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21274 11:47:20.885686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21275 11:47:20.886136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21277 11:47:20.923169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21278 11:47:20.923608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21280 11:47:20.960296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21282 11:47:20.960764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21283 11:47:20.996821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21284 11:47:20.997252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21286 11:47:21.034250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21287 11:47:21.034660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21289 11:47:21.070173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21290 11:47:21.070597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21292 11:47:21.105624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21294 11:47:21.106079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21295 11:47:21.140282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21297 11:47:21.140747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21298 11:47:21.177430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21299 11:47:21.177876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21301 11:47:21.214084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21302 11:47:21.214543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21304 11:47:21.249836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21305 11:47:21.250354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21307 11:47:21.285043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21308 11:47:21.285580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21310 11:47:21.320731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21312 11:47:21.321386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21313 11:47:21.357465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21314 11:47:21.357890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21316 11:47:21.395687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21317 11:47:21.396081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21319 11:47:21.433445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21321 11:47:21.434080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21322 11:47:21.469231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21323 11:47:21.469707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21325 11:47:21.505190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21326 11:47:21.505612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21328 11:47:21.541426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21329 11:47:21.541857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21331 11:47:21.569657 <47>[ 203.630486] systemd-journald[109]: Sent WATCHDOG=1 notification.
21332 11:47:21.584462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21334 11:47:21.584924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21335 11:47:21.621889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21336 11:47:21.622318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21338 11:47:21.662085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21340 11:47:21.662539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21341 11:47:21.698737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21342 11:47:21.699150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21344 11:47:21.734299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21346 11:47:21.734749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21347 11:47:21.769570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21349 11:47:21.769954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21350 11:47:21.805035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21352 11:47:21.805590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21353 11:47:21.840076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21355 11:47:21.840691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21356 11:47:21.875443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21357 11:47:21.875893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21359 11:47:21.910761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21360 11:47:21.911224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21362 11:47:21.946616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21364 11:47:21.947203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21365 11:47:21.982505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21366 11:47:21.982980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21368 11:47:22.017958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21370 11:47:22.018509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21371 11:47:22.053666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21373 11:47:22.054234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21374 11:47:22.090414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21375 11:47:22.090888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21377 11:47:22.125829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21378 11:47:22.126257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21380 11:47:22.163985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21382 11:47:22.164449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21383 11:47:22.199312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21385 11:47:22.199872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21386 11:47:22.234787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21388 11:47:22.235374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21389 11:47:22.270532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21390 11:47:22.271007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21392 11:47:22.310888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21394 11:47:22.311457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21395 11:47:22.357714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21397 11:47:22.358292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21398 11:47:22.393316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21399 11:47:22.393756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21401 11:47:22.428879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21402 11:47:22.429351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21404 11:47:22.463843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21406 11:47:22.464417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21407 11:47:22.499173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21408 11:47:22.499624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21410 11:47:22.534442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21411 11:47:22.534896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21413 11:47:22.569940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21415 11:47:22.570495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21416 11:47:22.605554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21418 11:47:22.606120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21419 11:47:22.640593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21421 11:47:22.641155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21422 11:47:22.675869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21423 11:47:22.676322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21425 11:47:22.711425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21427 11:47:22.711984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21428 11:47:22.747481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21430 11:47:22.748012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21431 11:47:22.783497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21433 11:47:22.784025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21434 11:47:22.818627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21436 11:47:22.819147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21437 11:47:22.854456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21439 11:47:22.855055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21440 11:47:22.889970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21441 11:47:22.890440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21443 11:47:22.925634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21444 11:47:22.926115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21446 11:47:22.961635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21448 11:47:22.962215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21449 11:47:22.997420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21451 11:47:22.997992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21452 11:47:23.033828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21453 11:47:23.034291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21455 11:47:23.071046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21456 11:47:23.071487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21458 11:47:23.107503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21460 11:47:23.107947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21461 11:47:23.143844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21462 11:47:23.144305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21464 11:47:23.180269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21465 11:47:23.180677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21467 11:47:23.217658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21468 11:47:23.218127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21470 11:47:23.255303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21471 11:47:23.255727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21473 11:47:23.293539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21474 11:47:23.294021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21476 11:47:23.330689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21478 11:47:23.331152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21479 11:47:23.367659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21480 11:47:23.368053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21482 11:47:23.403810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21483 11:47:23.404232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21485 11:47:23.440978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21486 11:47:23.441448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21488 11:47:23.476049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21489 11:47:23.476493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21491 11:47:23.511725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21492 11:47:23.512172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21494 11:47:23.547738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21495 11:47:23.548159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21497 11:47:23.583866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21498 11:47:23.584299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21500 11:47:23.619442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21501 11:47:23.619878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21503 11:47:23.655198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21505 11:47:23.655670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21506 11:47:23.690759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21507 11:47:23.691179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21509 11:47:23.726586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21511 11:47:23.727035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21512 11:47:23.762216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21513 11:47:23.762632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21515 11:47:23.798095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21517 11:47:23.798675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21518 11:47:23.834067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21520 11:47:23.834626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21521 11:47:23.869737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21522 11:47:23.870190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21524 11:47:23.906207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21525 11:47:23.906681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21527 11:47:23.942392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21529 11:47:23.942846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21530 11:47:23.978208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21531 11:47:23.978678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21533 11:47:24.013301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21534 11:47:24.013772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21536 11:47:24.048090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21538 11:47:24.048684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21539 11:47:24.083379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21540 11:47:24.083836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21542 11:47:24.118464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21543 11:47:24.118939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21545 11:47:24.154056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21547 11:47:24.154612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21548 11:47:24.190545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21550 11:47:24.191080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21551 11:47:24.226101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21552 11:47:24.226536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21554 11:47:24.261713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21556 11:47:24.262241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21557 11:47:24.297691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21558 11:47:24.298127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21560 11:47:24.333744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21561 11:47:24.334248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21563 11:47:24.369305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21565 11:47:24.369786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21566 11:47:24.405850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21568 11:47:24.406307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21569 11:47:24.441656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21570 11:47:24.442073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21572 11:47:24.477166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21573 11:47:24.477640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21575 11:47:24.513039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21577 11:47:24.513690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21578 11:47:24.549064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21579 11:47:24.549454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21581 11:47:24.620025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21582 11:47:24.620442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21584 11:47:24.662334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21585 11:47:24.662816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21587 11:47:24.698234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21589 11:47:24.698817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21590 11:47:24.733925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21592 11:47:24.734375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21593 11:47:24.770038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21595 11:47:24.770499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21596 11:47:24.806224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21597 11:47:24.806677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21599 11:47:24.842424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21600 11:47:24.842903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21602 11:47:24.877909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21604 11:47:24.878487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21605 11:47:24.913592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21606 11:47:24.914058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21608 11:47:24.948774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21609 11:47:24.949201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21611 11:47:24.983631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21612 11:47:24.984085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21614 11:47:25.019147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21615 11:47:25.019616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21617 11:47:25.054789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21619 11:47:25.055428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21620 11:47:25.091050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21621 11:47:25.091478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21623 11:47:25.126230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21625 11:47:25.126792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21626 11:47:25.162054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21628 11:47:25.162607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21629 11:47:25.197692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21631 11:47:25.198280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21632 11:47:25.234343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21634 11:47:25.234901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21635 11:47:25.269495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21637 11:47:25.270080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21638 11:47:25.306741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21639 11:47:25.307169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21641 11:47:25.342967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21642 11:47:25.343386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21644 11:47:25.379335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21645 11:47:25.379773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21647 11:47:25.414658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21648 11:47:25.415045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21650 11:47:25.450109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21651 11:47:25.450534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21653 11:47:25.485929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21654 11:47:25.486411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21656 11:47:25.521628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21658 11:47:25.522276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21659 11:47:25.557400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21660 11:47:25.557816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21662 11:47:25.594141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21664 11:47:25.594696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21665 11:47:25.629729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21667 11:47:25.630286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21668 11:47:25.665458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21669 11:47:25.665884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21671 11:47:25.701656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21672 11:47:25.702073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21674 11:47:25.737005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21675 11:47:25.737435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21677 11:47:25.773449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21679 11:47:25.773922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21680 11:47:25.808500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21682 11:47:25.808899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21683 11:47:25.852042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21685 11:47:25.852610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21686 11:47:25.887410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21688 11:47:25.887875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21689 11:47:25.922403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21691 11:47:25.922878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21692 11:47:25.957273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21693 11:47:25.957685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21695 11:47:25.993299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21697 11:47:25.993915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21698 11:47:26.029212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21699 11:47:26.029690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21701 11:47:26.064782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21702 11:47:26.065281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21704 11:47:26.100302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21706 11:47:26.100774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21707 11:47:26.137406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21708 11:47:26.137813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21710 11:47:26.173402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21711 11:47:26.173839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21713 11:47:26.209619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21714 11:47:26.210052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21716 11:47:26.246207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21717 11:47:26.246784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21719 11:47:26.282032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21720 11:47:26.282612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21722 11:47:26.319005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21723 11:47:26.319425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21725 11:47:26.355946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21727 11:47:26.356424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21728 11:47:26.392629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21730 11:47:26.393194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21731 11:47:26.427819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21733 11:47:26.428273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21734 11:47:26.463167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21735 11:47:26.463628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21737 11:47:26.498589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21738 11:47:26.499009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21740 11:47:26.534372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21742 11:47:26.534820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21743 11:47:26.573120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21744 11:47:26.573590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21746 11:47:26.609024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21748 11:47:26.609598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21749 11:47:26.644504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21751 11:47:26.644974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21752 11:47:26.679909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21753 11:47:26.680342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21755 11:47:26.714998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21756 11:47:26.715485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21758 11:47:26.750647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21760 11:47:26.751223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21761 11:47:26.785820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21763 11:47:26.786386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21764 11:47:26.821606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21766 11:47:26.822212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21767 11:47:26.857202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21768 11:47:26.857681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21770 11:47:26.892048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21771 11:47:26.892498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21773 11:47:26.927797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21774 11:47:26.928218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21776 11:47:26.962931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21778 11:47:26.963450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21779 11:47:26.997718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21781 11:47:26.998264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21782 11:47:27.032992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21783 11:47:27.033444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21785 11:47:27.067576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21786 11:47:27.067994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21788 11:47:27.102485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21789 11:47:27.102897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21791 11:47:27.137043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21793 11:47:27.137617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21794 11:47:27.171432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21795 11:47:27.171914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21797 11:47:27.206439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21798 11:47:27.206862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21800 11:47:27.241691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21801 11:47:27.242109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21803 11:47:27.276814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21804 11:47:27.277232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21806 11:47:27.311586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21807 11:47:27.312066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21809 11:47:27.347092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21810 11:47:27.347493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21812 11:47:27.382355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21813 11:47:27.382754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21815 11:47:27.417125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21817 11:47:27.417689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21818 11:47:27.452762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21820 11:47:27.453330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21821 11:47:27.488239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21823 11:47:27.488829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21824 11:47:27.523418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21825 11:47:27.523906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21827 11:47:27.562036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21828 11:47:27.562507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21830 11:47:27.607259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21831 11:47:27.607687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21833 11:47:27.649558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21834 11:47:27.650075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21836 11:47:27.690469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21837 11:47:27.690952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21839 11:47:27.734263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21841 11:47:27.734926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21842 11:47:27.776665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21844 11:47:27.777475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21845 11:47:27.814419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21847 11:47:27.815202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21848 11:47:27.851550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21849 11:47:27.851950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21851 11:47:27.885476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21852 11:47:27.885881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21854 11:47:27.919634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21855 11:47:27.920089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21857 11:47:27.952713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21858 11:47:27.953216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21860 11:47:27.983571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21861 11:47:27.984015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21863 11:47:28.013891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21864 11:47:28.014339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21866 11:47:28.044541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21868 11:47:28.045200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21869 11:47:28.076121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21870 11:47:28.076560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21872 11:47:28.107772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21873 11:47:28.108265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21875 11:47:28.138842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21876 11:47:28.139263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21878 11:47:28.170435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21879 11:47:28.170899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21881 11:47:28.202612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21883 11:47:28.203064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21884 11:47:28.234482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21885 11:47:28.234879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21887 11:47:28.268618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21889 11:47:28.269191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21890 11:47:28.300423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21892 11:47:28.300969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21893 11:47:28.332867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21894 11:47:28.333254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21896 11:47:28.364883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21897 11:47:28.365288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21899 11:47:28.396985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21900 11:47:28.397390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21902 11:47:28.429013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21903 11:47:28.429411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21905 11:47:28.461108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21906 11:47:28.461533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21908 11:47:28.494347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21910 11:47:28.494820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21911 11:47:28.526259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21912 11:47:28.526721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21914 11:47:28.557897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21915 11:47:28.558363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21917 11:47:28.589925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21918 11:47:28.590373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21920 11:47:28.621909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21922 11:47:28.622474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21923 11:47:28.653372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21924 11:47:28.653787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21926 11:47:28.685261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21927 11:47:28.685698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21929 11:47:28.717605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21930 11:47:28.718096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21932 11:47:28.749717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21933 11:47:28.750194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21935 11:47:28.781125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
21936 11:47:28.781604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
21938 11:47:28.813064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
21940 11:47:28.813541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
21941 11:47:28.844590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
21943 11:47:28.845049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
21944 11:47:28.876130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
21945 11:47:28.876539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
21947 11:47:28.907913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
21948 11:47:28.908370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
21950 11:47:28.940652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
21952 11:47:28.941109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
21953 11:47:28.972081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
21954 11:47:28.972500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
21956 11:47:29.003765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
21957 11:47:29.004187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
21959 11:47:29.035025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
21960 11:47:29.035471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
21962 11:47:29.066779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
21963 11:47:29.067217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
21965 11:47:29.099159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
21966 11:47:29.099628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
21968 11:47:29.130559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
21969 11:47:29.131020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
21971 11:47:29.162391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
21972 11:47:29.162846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
21974 11:47:29.193832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
21975 11:47:29.194266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
21977 11:47:29.225734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
21978 11:47:29.226169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
21980 11:47:29.257365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
21981 11:47:29.257794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
21983 11:47:29.291758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
21984 11:47:29.292165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
21986 11:47:29.323966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
21987 11:47:29.324388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
21989 11:47:29.357318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
21991 11:47:29.357789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
21992 11:47:29.390145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
21994 11:47:29.390605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
21995 11:47:29.422180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
21997 11:47:29.422630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
21998 11:47:29.454724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
21999 11:47:29.455152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
22001 11:47:29.486833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
22003 11:47:29.487299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
22004 11:47:29.519598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
22006 11:47:29.520064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
22007 11:47:29.551146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
22008 11:47:29.551586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
22010 11:47:29.582672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
22011 11:47:29.583089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
22013 11:47:29.613770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
22014 11:47:29.614159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
22016 11:47:29.645713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
22017 11:47:29.646125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
22019 11:47:29.677250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
22021 11:47:29.677692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
22022 11:47:29.729711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
22024 11:47:29.730162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
22025 11:47:29.762064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
22026 11:47:29.762524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
22028 11:47:29.794424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
22029 11:47:29.794909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
22031 11:47:29.826315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
22032 11:47:29.826719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
22034 11:47:29.858236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
22035 11:47:29.858693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
22037 11:47:29.890341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
22038 11:47:29.890806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
22040 11:47:29.921927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
22041 11:47:29.922392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
22043 11:47:29.953977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
22045 11:47:29.954540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
22046 11:47:29.986252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
22047 11:47:29.986722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
22049 11:47:30.018415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
22050 11:47:30.018836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
22052 11:47:30.050828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
22054 11:47:30.051285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
22055 11:47:30.083191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
22056 11:47:30.083589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
22058 11:47:30.115340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
22059 11:47:30.115765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
22061 11:47:30.147734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
22063 11:47:30.148198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
22064 11:47:30.180917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
22066 11:47:30.181369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
22067 11:47:30.212077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
22068 11:47:30.212469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
22070 11:47:30.245618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
22071 11:47:30.246064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
22073 11:47:30.279902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
22074 11:47:30.280346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
22076 11:47:30.314452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
22078 11:47:30.314909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
22079 11:47:30.348487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
22081 11:47:30.348962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
22082 11:47:30.380970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
22084 11:47:30.381526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
22085 11:47:30.412986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
22087 11:47:30.413454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
22088 11:47:30.445408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
22090 11:47:30.445882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
22091 11:47:30.477513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
22092 11:47:30.477933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
22094 11:47:30.508979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
22095 11:47:30.509458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
22097 11:47:30.541058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
22098 11:47:30.541516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
22100 11:47:30.573297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
22102 11:47:30.573881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
22103 11:47:30.605102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
22104 11:47:30.605558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
22106 11:47:30.639662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
22107 11:47:30.640140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
22109 11:47:30.671930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
22111 11:47:30.672515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
22112 11:47:30.703210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
22113 11:47:30.703688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
22115 11:47:30.734178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
22116 11:47:30.734627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
22118 11:47:30.765163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
22119 11:47:30.765672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
22121 11:47:30.797365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
22123 11:47:30.797929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
22124 11:47:30.829726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
22125 11:47:30.830190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
22127 11:47:30.861714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
22129 11:47:30.862175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
22130 11:47:30.893453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
22132 11:47:30.894029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
22133 11:47:30.926146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
22135 11:47:30.926615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
22136 11:47:30.958581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
22138 11:47:30.959016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
22139 11:47:30.990361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
22140 11:47:30.990818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
22142 11:47:31.022552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
22144 11:47:31.023007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
22145 11:47:31.054276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
22147 11:47:31.054743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
22148 11:47:31.086568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
22149 11:47:31.086977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
22151 11:47:31.120468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
22153 11:47:31.121027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
22154 11:47:31.154573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
22155 11:47:31.155016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
22157 11:47:31.187641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
22159 11:47:31.188203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
22160 11:47:31.221446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
22161 11:47:31.221932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
22163 11:47:31.259037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
22164 11:47:31.259481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
22166 11:47:31.292444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
22168 11:47:31.292901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
22169 11:47:31.326517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
22170 11:47:31.326991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
22172 11:47:31.361142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
22174 11:47:31.361739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
22175 11:47:31.396957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
22176 11:47:31.397373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
22178 11:47:31.433336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22179 11:47:31.433783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
22181 11:47:31.465929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22183 11:47:31.466517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22184 11:47:31.497967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22186 11:47:31.498429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22187 11:47:31.530188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22188 11:47:31.530643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22190 11:47:31.562842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22191 11:47:31.563312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22193 11:47:31.597571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22194 11:47:31.598072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22196 11:47:31.633042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22197 11:47:31.633532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22199 11:47:31.668107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22200 11:47:31.668588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22202 11:47:31.704419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22204 11:47:31.704882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22205 11:47:31.739983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22206 11:47:31.740431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22208 11:47:31.771964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22209 11:47:31.772458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22211 11:47:31.803943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22212 11:47:31.804380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22214 11:47:31.835649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22216 11:47:31.836093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22217 11:47:31.866609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22219 11:47:31.867069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22220 11:47:31.898842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22221 11:47:31.899291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22223 11:47:31.933334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22224 11:47:31.933777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22226 11:47:31.965159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22227 11:47:31.965634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22229 11:47:31.997097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22230 11:47:31.997590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22232 11:47:32.029866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22233 11:47:32.030357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22235 11:47:32.062447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22236 11:47:32.062874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22238 11:47:32.095512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22239 11:47:32.095973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22241 11:47:32.127518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22243 11:47:32.128108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22244 11:47:32.159287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22245 11:47:32.159695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22247 11:47:32.190352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22248 11:47:32.190772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22250 11:47:32.222206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22251 11:47:32.222634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22253 11:47:32.254731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22255 11:47:32.255176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22256 11:47:32.286183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22257 11:47:32.286600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22259 11:47:32.317841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22260 11:47:32.318300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22262 11:47:32.349657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22264 11:47:32.350216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22265 11:47:32.381520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22266 11:47:32.382018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22268 11:47:32.412993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22270 11:47:32.413528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22271 11:47:32.444238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22272 11:47:32.444679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22274 11:47:32.478302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22275 11:47:32.478723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22277 11:47:32.509696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22279 11:47:32.510264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22280 11:47:32.541567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22281 11:47:32.542044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22283 11:47:32.573506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22284 11:47:32.573973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22286 11:47:32.605168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22287 11:47:32.605661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22289 11:47:32.637019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22290 11:47:32.637465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22292 11:47:32.669531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22293 11:47:32.670013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22295 11:47:32.701669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22296 11:47:32.702137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22298 11:47:32.736434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22300 11:47:32.737017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22301 11:47:32.769455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22302 11:47:32.769905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22304 11:47:32.801833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22305 11:47:32.802295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22307 11:47:32.834098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22308 11:47:32.834542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22310 11:47:32.866307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22311 11:47:32.866768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22313 11:47:32.898007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22314 11:47:32.898482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22316 11:47:32.930816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22317 11:47:32.931305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22319 11:47:32.965379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22321 11:47:32.965970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22322 11:47:32.997720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22324 11:47:32.998278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22325 11:47:33.030146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22326 11:47:33.030602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22328 11:47:33.062491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22329 11:47:33.062947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22331 11:47:33.094729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22333 11:47:33.095283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22334 11:47:33.127311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22336 11:47:33.127861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22337 11:47:33.159003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22339 11:47:33.159550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22340 11:47:33.190586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22341 11:47:33.191026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22343 11:47:33.221986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22344 11:47:33.222417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22346 11:47:33.253687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22348 11:47:33.254330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22349 11:47:33.286313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22351 11:47:33.286858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22352 11:47:33.318229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22354 11:47:33.318776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22355 11:47:33.350380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22356 11:47:33.350823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22358 11:47:33.382904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22359 11:47:33.383360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22361 11:47:33.414793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22362 11:47:33.415242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22364 11:47:33.446621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22365 11:47:33.447073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22367 11:47:33.479332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22368 11:47:33.479788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22370 11:47:33.511567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22371 11:47:33.512008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22373 11:47:33.543061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22374 11:47:33.543486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22376 11:47:33.576521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22378 11:47:33.577019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22379 11:47:33.609378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22381 11:47:33.609853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22382 11:47:33.640479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22384 11:47:33.640953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22385 11:47:33.671514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22386 11:47:33.671936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22388 11:47:33.702579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22390 11:47:33.703051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22391 11:47:33.733411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22392 11:47:33.733883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22394 11:47:33.765124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22395 11:47:33.765603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22397 11:47:33.796560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22399 11:47:33.797116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22400 11:47:33.828631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22402 11:47:33.829049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22403 11:47:33.859780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22404 11:47:33.860199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22406 11:47:33.891502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22407 11:47:33.891905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22409 11:47:33.923104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22410 11:47:33.923508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22412 11:47:33.954914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22413 11:47:33.955341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22415 11:47:33.986052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22416 11:47:33.986476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22418 11:47:34.017326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22419 11:47:34.017735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22421 11:47:34.049064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22423 11:47:34.049482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22424 11:47:34.081103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22425 11:47:34.081493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22427 11:47:34.113449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22429 11:47:34.113874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22430 11:47:34.145965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22431 11:47:34.146341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22433 11:47:34.177560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22435 11:47:34.178008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22436 11:47:34.209421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22438 11:47:34.209879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22439 11:47:34.241241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22441 11:47:34.241815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22442 11:47:34.272139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22444 11:47:34.272695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22445 11:47:34.303773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22446 11:47:34.304213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22448 11:47:34.335700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22450 11:47:34.336259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22451 11:47:34.367502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22452 11:47:34.367938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22454 11:47:34.399409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22455 11:47:34.399841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22457 11:47:34.431195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22458 11:47:34.431646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22460 11:47:34.462664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22461 11:47:34.463143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22463 11:47:34.495020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22464 11:47:34.495475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22466 11:47:34.527275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22467 11:47:34.527735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22469 11:47:34.559156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22470 11:47:34.559598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22472 11:47:34.591182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22473 11:47:34.591660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22475 11:47:34.623837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22476 11:47:34.624269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22478 11:47:34.655707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22479 11:47:34.656129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22481 11:47:34.687177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22482 11:47:34.687567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22484 11:47:34.719280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22485 11:47:34.719703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22487 11:47:34.750975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22488 11:47:34.751402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22490 11:47:34.782614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22491 11:47:34.783037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22493 11:47:34.833712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22494 11:47:34.834121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22496 11:47:34.864538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22498 11:47:34.865009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22499 11:47:34.895751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22500 11:47:34.896221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22502 11:47:34.927598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22504 11:47:34.928020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22505 11:47:34.959270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22506 11:47:34.959733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22508 11:47:34.991262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22510 11:47:34.991829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22511 11:47:35.022757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22513 11:47:35.023312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22514 11:47:35.054010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22515 11:47:35.054451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22517 11:47:35.085444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22518 11:47:35.085837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22520 11:47:35.117249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22522 11:47:35.117675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22523 11:47:35.148952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22524 11:47:35.149333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22526 11:47:35.182019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22528 11:47:35.182473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22529 11:47:35.214683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22530 11:47:35.215142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22532 11:47:35.246387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22534 11:47:35.246858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22535 11:47:35.277824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22536 11:47:35.278269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22538 11:47:35.309689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22539 11:47:35.310129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22541 11:47:35.341911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22542 11:47:35.342407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22544 11:47:35.373663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22545 11:47:35.374147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22547 11:47:35.405422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22548 11:47:35.405894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22550 11:47:35.437412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22551 11:47:35.437960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22553 11:47:35.469765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22554 11:47:35.470233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22556 11:47:35.501086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22557 11:47:35.501539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22559 11:47:35.533199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22561 11:47:35.533747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22562 11:47:35.565198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22564 11:47:35.565783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22565 11:47:35.597333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22566 11:47:35.597803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22568 11:47:35.628300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22570 11:47:35.628956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22571 11:47:35.661879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22572 11:47:35.662363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22574 11:47:35.693745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22575 11:47:35.694226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22577 11:47:35.725385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22578 11:47:35.725800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22580 11:47:35.757756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22582 11:47:35.758197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22583 11:47:35.789450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22584 11:47:35.789946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22586 11:47:35.821297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22588 11:47:35.821951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22589 11:47:35.853109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22590 11:47:35.853590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22592 11:47:35.884222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22594 11:47:35.884859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22595 11:47:35.916092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22596 11:47:35.916576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22598 11:47:35.947930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22599 11:47:35.948340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22601 11:47:35.979275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22602 11:47:35.979701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22604 11:47:36.011386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22605 11:47:36.011809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22607 11:47:36.043127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22609 11:47:36.043780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22610 11:47:36.076248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22611 11:47:36.076731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22613 11:47:36.108257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22615 11:47:36.108897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22616 11:47:36.139781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22617 11:47:36.140264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22619 11:47:36.172127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22620 11:47:36.172603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22622 11:47:36.204931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22623 11:47:36.205408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22625 11:47:36.237239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22627 11:47:36.237810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22628 11:47:36.271653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22630 11:47:36.272448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22631 11:47:36.307189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22633 11:47:36.307892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22634 11:47:36.344630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22636 11:47:36.345087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22637 11:47:36.382376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22639 11:47:36.383019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22640 11:47:36.417194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22641 11:47:36.417703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22643 11:47:36.452245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22645 11:47:36.452804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22646 11:47:36.486210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22648 11:47:36.486773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22649 11:47:36.517691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22650 11:47:36.518151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22652 11:47:36.549309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22653 11:47:36.549773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22655 11:47:36.580504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22657 11:47:36.581071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22658 11:47:36.625548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22659 11:47:36.625985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22661 11:47:36.659833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22662 11:47:36.660277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22664 11:47:36.693944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22666 11:47:36.694414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22667 11:47:36.729118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22669 11:47:36.729583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22670 11:47:36.762355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22671 11:47:36.762768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22673 11:47:36.793471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22674 11:47:36.793873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22676 11:47:36.825485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22677 11:47:36.825870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22679 11:47:36.857096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22681 11:47:36.857664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22682 11:47:36.889065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22683 11:47:36.889521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22685 11:47:36.921163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22687 11:47:36.921811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22688 11:47:36.952158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22690 11:47:36.952788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22691 11:47:36.983500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22692 11:47:36.983945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22694 11:47:37.015253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22695 11:47:37.015733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22697 11:47:37.046083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22698 11:47:37.046473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22700 11:47:37.077895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22702 11:47:37.078357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22703 11:47:37.109317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22704 11:47:37.109791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22706 11:47:37.140621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22708 11:47:37.141183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22709 11:47:37.172046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22711 11:47:37.172594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22712 11:47:37.203221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22713 11:47:37.203724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22715 11:47:37.235114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22717 11:47:37.235549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22718 11:47:37.267100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22719 11:47:37.267561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22721 11:47:37.299115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22722 11:47:37.299560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22724 11:47:37.330328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22725 11:47:37.330757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22727 11:47:37.361686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22728 11:47:37.362128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22730 11:47:37.393467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22731 11:47:37.393936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22733 11:47:37.429036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22735 11:47:37.429601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22736 11:47:37.459979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22737 11:47:37.460460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22739 11:47:37.491412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22741 11:47:37.491965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22742 11:47:37.522797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22743 11:47:37.523230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22745 11:47:37.553832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22746 11:47:37.554331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22748 11:47:37.585771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22749 11:47:37.586165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22751 11:47:37.617244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22753 11:47:37.617851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22754 11:47:37.649537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22755 11:47:37.650005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22757 11:47:37.681491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22758 11:47:37.681969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22760 11:47:37.713699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22761 11:47:37.714148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22763 11:47:37.745718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22764 11:47:37.746121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22766 11:47:37.777473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22767 11:47:37.777886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22769 11:47:37.809537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22770 11:47:37.810008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22772 11:47:37.841935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22774 11:47:37.842495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22775 11:47:37.873770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22776 11:47:37.874210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22778 11:47:37.905112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22779 11:47:37.905576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22781 11:47:37.936944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22782 11:47:37.937402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22784 11:47:37.968211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22785 11:47:37.968670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22787 11:47:37.998622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22788 11:47:37.999099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22790 11:47:38.029504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22791 11:47:38.029977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22793 11:47:38.060692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22795 11:47:38.061136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22796 11:47:38.093874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22798 11:47:38.094306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22799 11:47:38.125364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22800 11:47:38.125787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22802 11:47:38.157374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22803 11:47:38.157786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22805 11:47:38.189595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22807 11:47:38.190180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22808 11:47:38.221479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22809 11:47:38.221959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22811 11:47:38.253620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22813 11:47:38.254068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22814 11:47:38.287515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22815 11:47:38.287961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22817 11:47:38.322764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22818 11:47:38.323179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22820 11:47:38.355044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22821 11:47:38.355477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22823 11:47:38.389092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22824 11:47:38.389528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22826 11:47:38.421466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22827 11:47:38.421892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22829 11:47:38.453038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22830 11:47:38.453504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22832 11:47:38.484264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22834 11:47:38.484739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22835 11:47:38.515843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22837 11:47:38.516304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22838 11:47:38.546941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22839 11:47:38.547418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22841 11:47:38.578160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22842 11:47:38.578646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22844 11:47:38.609821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22846 11:47:38.610523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22847 11:47:38.643269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22849 11:47:38.643856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22850 11:47:38.674802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22851 11:47:38.675240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22853 11:47:38.706742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22854 11:47:38.707178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22856 11:47:38.738917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22857 11:47:38.739343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22859 11:47:38.770854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22860 11:47:38.771293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22862 11:47:38.802704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22864 11:47:38.803130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22865 11:47:38.835141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22867 11:47:38.835597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22868 11:47:38.867425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22869 11:47:38.867846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22871 11:47:38.899056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22872 11:47:38.899497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22874 11:47:38.931031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22875 11:47:38.931487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22877 11:47:38.962979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22879 11:47:38.963579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22880 11:47:38.996892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22882 11:47:38.997360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22883 11:47:39.028430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22885 11:47:39.028890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22886 11:47:39.060861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22888 11:47:39.061329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22889 11:47:39.101693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22890 11:47:39.102121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22892 11:47:39.134624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22893 11:47:39.135098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22895 11:47:39.166838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22897 11:47:39.167383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22898 11:47:39.198582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22899 11:47:39.199021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22901 11:47:39.230522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22902 11:47:39.230979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22904 11:47:39.262488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22906 11:47:39.263039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22907 11:47:39.294684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22908 11:47:39.295111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22910 11:47:39.326999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22912 11:47:39.327459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22913 11:47:39.358488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22914 11:47:39.358910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22916 11:47:39.390139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22917 11:47:39.390561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22919 11:47:39.421614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22920 11:47:39.422102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22922 11:47:39.453631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22923 11:47:39.454123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22925 11:47:39.486059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22927 11:47:39.486513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22928 11:47:39.517850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22929 11:47:39.518252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22931 11:47:39.549740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22932 11:47:39.550223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22934 11:47:39.582037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
22936 11:47:39.582644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22937 11:47:39.613849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
22938 11:47:39.614293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
22940 11:47:39.645831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
22941 11:47:39.646284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
22943 11:47:39.677833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
22945 11:47:39.678283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
22946 11:47:39.709581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
22948 11:47:39.710022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
22949 11:47:39.741679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
22951 11:47:39.742228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
22952 11:47:39.773794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
22953 11:47:39.774241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
22955 11:47:39.805921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
22956 11:47:39.806307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
22958 11:47:39.838137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
22959 11:47:39.838616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
22961 11:47:39.869811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
22963 11:47:39.870441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
22964 11:47:39.904022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
22965 11:47:39.904480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
22967 11:47:39.959778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
22968 11:47:39.960244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
22970 11:47:39.991771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
22971 11:47:39.992237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
22973 11:47:40.023626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
22975 11:47:40.024179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
22976 11:47:40.054695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
22977 11:47:40.055126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
22979 11:47:40.086318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
22980 11:47:40.086751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
22982 11:47:40.117662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
22983 11:47:40.118094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
22985 11:47:40.148948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
22987 11:47:40.149490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
22988 11:47:40.181229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
22989 11:47:40.181691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
22991 11:47:40.212658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
22992 11:47:40.213110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
22994 11:47:40.244417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
22996 11:47:40.244883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
22997 11:47:40.276339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
22999 11:47:40.276807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
23000 11:47:40.307858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
23001 11:47:40.308277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
23003 11:47:40.341725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
23004 11:47:40.342139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
23006 11:47:40.374404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
23008 11:47:40.374835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
23009 11:47:40.405706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
23010 11:47:40.406108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
23012 11:47:40.437448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
23013 11:47:40.437835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
23015 11:47:40.469011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
23016 11:47:40.469450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
23018 11:47:40.501753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
23019 11:47:40.502186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
23021 11:47:40.536135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
23022 11:47:40.536593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
23024 11:47:40.567825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
23026 11:47:40.568558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
23027 11:47:40.600930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
23029 11:47:40.601568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
23030 11:47:40.632108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
23032 11:47:40.632580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
23033 11:47:40.662960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
23034 11:47:40.663450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
23036 11:47:40.694109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
23037 11:47:40.694519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
23039 11:47:40.725438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
23040 11:47:40.725904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
23042 11:47:40.757209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
23043 11:47:40.757607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
23045 11:47:40.789076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
23046 11:47:40.789556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
23048 11:47:40.820966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
23050 11:47:40.821584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
23051 11:47:40.851995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
23052 11:47:40.852442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
23054 11:47:40.883413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
23056 11:47:40.883949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
23057 11:47:40.914975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
23058 11:47:40.915405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
23060 11:47:40.949210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
23062 11:47:40.949780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
23063 11:47:40.981474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
23064 11:47:40.981900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
23066 11:47:41.013010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
23067 11:47:41.013455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
23069 11:47:41.044061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
23071 11:47:41.044537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
23072 11:47:41.075465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
23073 11:47:41.075910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
23075 11:47:41.107004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
23076 11:47:41.107430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
23078 11:47:41.138131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
23080 11:47:41.138593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
23081 11:47:41.169343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
23082 11:47:41.169793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
23084 11:47:41.201986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
23086 11:47:41.202457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
23087 11:47:41.233131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
23088 11:47:41.233551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
23090 11:47:41.263826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
23091 11:47:41.264272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
23093 11:47:41.296977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
23095 11:47:41.297449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
23096 11:47:41.334717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
23098 11:47:41.335294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
23099 11:47:41.367849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
23101 11:47:41.368487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
23102 11:47:41.400124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
23103 11:47:41.400578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
23105 11:47:41.432435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
23107 11:47:41.432888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
23108 11:47:41.463371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
23110 11:47:41.463865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
23111 11:47:41.494550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
23112 11:47:41.494974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
23114 11:47:41.526305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
23115 11:47:41.526718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
23117 11:47:41.558314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
23119 11:47:41.558769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
23120 11:47:41.589463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
23121 11:47:41.589895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
23123 11:47:41.620965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
23124 11:47:41.621447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
23126 11:47:41.653618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
23128 11:47:41.654363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
23129 11:47:41.684226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
23131 11:47:41.684871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
23132 11:47:41.716295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
23134 11:47:41.716762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
23135 11:47:41.748635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
23137 11:47:41.749135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
23138 11:47:41.780140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
23139 11:47:41.780611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
23141 11:47:41.813629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
23143 11:47:41.814257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
23144 11:47:41.845456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
23146 11:47:41.846045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
23147 11:47:41.876974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
23149 11:47:41.877517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
23150 11:47:41.908487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
23152 11:47:41.909054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
23153 11:47:41.939654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
23154 11:47:41.940111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
23156 11:47:41.971289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
23157 11:47:41.971770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
23159 11:47:42.003042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
23160 11:47:42.003508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
23162 11:47:42.034276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
23163 11:47:42.034746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
23165 11:47:42.065686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
23166 11:47:42.066163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
23168 11:47:42.097281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
23170 11:47:42.097829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
23171 11:47:42.130559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
23172 11:47:42.131019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
23174 11:47:42.162298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
23176 11:47:42.162870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
23177 11:47:42.193227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
23178 11:47:42.193707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
23180 11:47:42.225200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23181 11:47:42.225684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23183 11:47:42.256788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23185 11:47:42.257407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23186 11:47:42.288033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23187 11:47:42.288498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23189 11:47:42.319412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23191 11:47:42.319860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23192 11:47:42.351014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23193 11:47:42.351465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23195 11:47:42.382086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23196 11:47:42.382511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23198 11:47:42.413665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23199 11:47:42.414090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23201 11:47:42.445103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23202 11:47:42.445526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23204 11:47:42.476060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23205 11:47:42.476481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23207 11:47:42.506561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23208 11:47:42.506951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23210 11:47:42.537375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23211 11:47:42.537791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23213 11:47:42.569011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23214 11:47:42.569492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23216 11:47:42.599641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23217 11:47:42.600118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23219 11:47:42.631094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23220 11:47:42.631548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23222 11:47:42.662740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23224 11:47:42.663214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23225 11:47:42.694155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23226 11:47:42.694590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23228 11:47:42.725466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23230 11:47:42.725952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23231 11:47:42.756170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23232 11:47:42.756596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23234 11:47:42.787069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23235 11:47:42.787505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23237 11:47:42.818145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23238 11:47:42.818669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23240 11:47:42.850353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23242 11:47:42.850899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23243 11:47:42.882195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23244 11:47:42.882646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23246 11:47:42.914465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23247 11:47:42.914931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23249 11:47:42.946187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23250 11:47:42.946598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23252 11:47:42.979250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23253 11:47:42.979673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23255 11:47:43.010957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23257 11:47:43.011600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23258 11:47:43.041919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23260 11:47:43.042475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23261 11:47:43.073035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23262 11:47:43.073432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23264 11:47:43.104599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23266 11:47:43.105136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23267 11:47:43.136501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23269 11:47:43.136947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23270 11:47:43.168128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23271 11:47:43.168517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23273 11:47:43.199732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23275 11:47:43.200193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23276 11:47:43.231882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23277 11:47:43.232332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23279 11:47:43.265363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23280 11:47:43.265848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23282 11:47:43.298117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23283 11:47:43.298571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23285 11:47:43.330463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23286 11:47:43.330917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23288 11:47:43.362685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23290 11:47:43.363231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23291 11:47:43.394933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23292 11:47:43.395352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23294 11:47:43.427954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23296 11:47:43.428522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23297 11:47:43.460098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23298 11:47:43.460565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23300 11:47:43.492245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23302 11:47:43.492860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23303 11:47:43.524535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23305 11:47:43.525067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23306 11:47:43.556232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23308 11:47:43.556820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23309 11:47:43.587984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23310 11:47:43.588370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23312 11:47:43.619414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23314 11:47:43.619888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23315 11:47:43.651004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23316 11:47:43.651447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23318 11:47:43.683235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23319 11:47:43.683666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23321 11:47:43.714754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23322 11:47:43.715176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23324 11:47:43.746328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23325 11:47:43.746752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23327 11:47:43.777994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23328 11:47:43.778413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23330 11:47:43.810856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23331 11:47:43.811287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23333 11:47:43.843166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23335 11:47:43.843781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23336 11:47:43.874574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23337 11:47:43.875016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23339 11:47:43.906377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23341 11:47:43.906968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23342 11:47:43.938284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23343 11:47:43.938763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23345 11:47:43.970249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23347 11:47:43.970879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23348 11:47:44.002312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23349 11:47:44.002787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23351 11:47:44.034145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23352 11:47:44.034616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23354 11:47:44.065678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23356 11:47:44.066224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23357 11:47:44.097411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23359 11:47:44.098032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23360 11:47:44.129253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23361 11:47:44.129708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23363 11:47:44.161161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23364 11:47:44.161611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23366 11:47:44.193186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23367 11:47:44.193571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23369 11:47:44.225576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23370 11:47:44.225961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23372 11:47:44.258369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23373 11:47:44.258763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23375 11:47:44.289700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23377 11:47:44.290152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23378 11:47:44.321148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23379 11:47:44.321571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23381 11:47:44.353218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23383 11:47:44.353672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23384 11:47:44.385405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23385 11:47:44.385829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23387 11:47:44.417344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23388 11:47:44.417769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23390 11:47:44.452883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23391 11:47:44.453367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23393 11:47:44.485291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23395 11:47:44.485926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23396 11:47:44.518497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23398 11:47:44.518970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23399 11:47:44.551087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23400 11:47:44.551558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23402 11:47:44.583321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23403 11:47:44.583726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23405 11:47:44.617096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23406 11:47:44.617534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23408 11:47:44.649617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23410 11:47:44.650095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23411 11:47:44.681424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23412 11:47:44.681846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23414 11:47:44.713785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23416 11:47:44.714224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23417 11:47:44.746561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23418 11:47:44.746957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23420 11:47:44.778202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23422 11:47:44.778672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23423 11:47:44.809519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23424 11:47:44.810005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23426 11:47:44.841583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23427 11:47:44.842040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23429 11:47:44.873767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23431 11:47:44.874225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23432 11:47:44.906011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23434 11:47:44.906458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23435 11:47:44.938787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23437 11:47:44.939231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23438 11:47:44.971053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23439 11:47:44.971507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23441 11:47:45.002324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23442 11:47:45.002770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23444 11:47:45.034463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23445 11:47:45.034906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23447 11:47:45.092200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23449 11:47:45.092767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23450 11:47:45.129901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23451 11:47:45.130262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23453 11:47:45.166880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23454 11:47:45.167292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23456 11:47:45.203553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23457 11:47:45.203997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23459 11:47:45.242174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23460 11:47:45.242592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23462 11:47:45.277668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23463 11:47:45.278178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23465 11:47:45.309469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23466 11:47:45.309939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23468 11:47:45.341138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23469 11:47:45.341592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23471 11:47:45.372258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23472 11:47:45.372722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23474 11:47:45.403303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23476 11:47:45.403869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23477 11:47:45.434155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23478 11:47:45.434609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23480 11:47:45.465060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23481 11:47:45.465528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23483 11:47:45.496158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23484 11:47:45.496620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23486 11:47:45.528321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23488 11:47:45.528911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23489 11:47:45.559856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23491 11:47:45.560412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23492 11:47:45.591025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23493 11:47:45.591479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23495 11:47:45.623746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23496 11:47:45.624232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23498 11:47:45.655926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23500 11:47:45.656556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23501 11:47:45.688105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23502 11:47:45.688595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23504 11:47:45.719594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23505 11:47:45.720073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23507 11:47:45.751426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23509 11:47:45.751958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23510 11:47:45.783502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23511 11:47:45.783970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23513 11:47:45.817618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23514 11:47:45.818119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23516 11:47:45.849530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23517 11:47:45.849981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23519 11:47:45.881123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23520 11:47:45.881580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23522 11:47:45.912489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23524 11:47:45.913267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23525 11:47:45.943871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23526 11:47:45.944370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23528 11:47:45.974831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23530 11:47:45.975312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23531 11:47:46.006245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23533 11:47:46.006713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23534 11:47:46.037607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23535 11:47:46.038064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23537 11:47:46.069066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23538 11:47:46.069488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23540 11:47:46.101323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23541 11:47:46.101748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23543 11:47:46.132445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23545 11:47:46.132906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23546 11:47:46.164079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23548 11:47:46.164537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23549 11:47:46.195712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23551 11:47:46.196169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23552 11:47:46.227395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23553 11:47:46.227873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23555 11:47:46.260031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23557 11:47:46.260619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23558 11:47:46.292123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23559 11:47:46.292586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23561 11:47:46.325631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23563 11:47:46.326193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23564 11:47:46.358426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23565 11:47:46.358890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23567 11:47:46.391108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23568 11:47:46.391495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23570 11:47:46.423108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23572 11:47:46.423516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23573 11:47:46.462632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23574 11:47:46.463070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23576 11:47:46.495371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23577 11:47:46.495806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23579 11:47:46.526837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23580 11:47:46.527305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23582 11:47:46.559688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23584 11:47:46.560150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23585 11:47:46.592533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23587 11:47:46.593084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23588 11:47:46.625584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23589 11:47:46.626077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23591 11:47:46.657739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23593 11:47:46.658544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23594 11:47:46.689760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23595 11:47:46.690332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23597 11:47:46.722979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23599 11:47:46.723561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23600 11:47:46.754883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23601 11:47:46.755303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23603 11:47:46.787070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23604 11:47:46.787473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23606 11:47:46.819346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23607 11:47:46.819726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23609 11:47:46.850644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23611 11:47:46.851167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23612 11:47:46.881958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23613 11:47:46.882380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23615 11:47:46.914423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23616 11:47:46.914847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23618 11:47:46.945593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23619 11:47:46.946024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23621 11:47:46.977700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23622 11:47:46.978141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23624 11:47:47.009464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23625 11:47:47.009970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23627 11:47:47.042181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23628 11:47:47.042597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23630 11:47:47.073697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23631 11:47:47.074158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23633 11:47:47.105514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23634 11:47:47.105948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23636 11:47:47.137586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23637 11:47:47.138073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23639 11:47:47.168896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23641 11:47:47.169525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23642 11:47:47.199788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23643 11:47:47.200265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23645 11:47:47.231550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23646 11:47:47.231978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23648 11:47:47.262613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23649 11:47:47.263091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23651 11:47:47.293546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23652 11:47:47.294021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23654 11:47:47.325001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23655 11:47:47.325418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23657 11:47:47.356934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23659 11:47:47.357571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23660 11:47:47.388167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23662 11:47:47.388793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23663 11:47:47.418895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23664 11:47:47.419376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23666 11:47:47.450101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23667 11:47:47.450583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23669 11:47:47.481292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23670 11:47:47.481770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23672 11:47:47.512767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23674 11:47:47.513329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23675 11:47:47.544017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23676 11:47:47.544441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23678 11:47:47.576600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23680 11:47:47.577064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23681 11:47:47.607931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23683 11:47:47.608395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23684 11:47:47.639685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23685 11:47:47.640082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23687 11:47:47.674214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23688 11:47:47.674681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23690 11:47:47.706234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23691 11:47:47.706766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23693 11:47:47.738216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23694 11:47:47.738684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23696 11:47:47.770054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23697 11:47:47.770460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23699 11:47:47.801742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23700 11:47:47.802198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23702 11:47:47.834244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23703 11:47:47.834804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23705 11:47:47.866013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23706 11:47:47.866407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23708 11:47:47.899220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23709 11:47:47.899687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23711 11:47:47.933918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23712 11:47:47.934404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23714 11:47:47.966042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23715 11:47:47.966511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23717 11:47:47.998597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23719 11:47:47.999166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23720 11:47:48.029895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23721 11:47:48.030357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23723 11:47:48.061935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23724 11:47:48.062356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23726 11:47:48.095731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23728 11:47:48.096364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23729 11:47:48.127062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23730 11:47:48.127477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23732 11:47:48.159487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23733 11:47:48.159969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23735 11:47:48.191498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23737 11:47:48.192106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23738 11:47:48.225044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23739 11:47:48.225494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23741 11:47:48.257158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23742 11:47:48.257601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23744 11:47:48.290271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23746 11:47:48.290816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23747 11:47:48.322266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23748 11:47:48.322714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23750 11:47:48.354906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23752 11:47:48.355442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23753 11:47:48.387558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23754 11:47:48.387984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23756 11:47:48.419607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23757 11:47:48.420021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23759 11:47:48.451522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23760 11:47:48.451996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23762 11:47:48.483655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23763 11:47:48.484113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23765 11:47:48.515386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23766 11:47:48.515841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23768 11:47:48.546225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23769 11:47:48.546698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23771 11:47:48.578434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23772 11:47:48.578843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23774 11:47:48.611389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23776 11:47:48.611940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23777 11:47:48.643031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23778 11:47:48.643503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23780 11:47:48.675174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23782 11:47:48.675825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23783 11:47:48.707400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23785 11:47:48.707939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23786 11:47:48.738798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23787 11:47:48.739241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23789 11:47:48.771070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23790 11:47:48.771519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23792 11:47:48.802380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23793 11:47:48.802772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23795 11:47:48.834201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23796 11:47:48.834624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23798 11:47:48.866101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23800 11:47:48.866562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23801 11:47:48.897757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23802 11:47:48.898191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23804 11:47:48.929342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23805 11:47:48.929827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23807 11:47:48.961028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23809 11:47:48.961590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23810 11:47:48.991882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23811 11:47:48.992308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23813 11:47:49.023035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23814 11:47:49.023482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23816 11:47:49.054128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23817 11:47:49.054595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23819 11:47:49.086234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23820 11:47:49.086681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23822 11:47:49.117625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23824 11:47:49.118168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23825 11:47:49.149050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23826 11:47:49.149500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23828 11:47:49.181350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23829 11:47:49.181787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23831 11:47:49.215194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23832 11:47:49.215609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23834 11:47:49.246666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23835 11:47:49.247132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23837 11:47:49.279727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23838 11:47:49.280185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23840 11:47:49.311172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23841 11:47:49.311593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23843 11:47:49.346262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23845 11:47:49.346830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23846 11:47:49.377921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23847 11:47:49.378379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23849 11:47:49.410013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23851 11:47:49.410571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23852 11:47:49.442292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23854 11:47:49.442844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23855 11:47:49.473502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23857 11:47:49.474072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23858 11:47:49.505321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23860 11:47:49.505910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23861 11:47:49.538645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23862 11:47:49.539054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23864 11:47:49.570091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23865 11:47:49.570502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23867 11:47:49.602044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23869 11:47:49.602476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23870 11:47:49.634588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23871 11:47:49.635047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23873 11:47:49.666015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23874 11:47:49.666440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23876 11:47:49.697558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23877 11:47:49.698034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23879 11:47:49.729389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23880 11:47:49.729785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23882 11:47:49.761283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23883 11:47:49.761708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23885 11:47:49.793896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23887 11:47:49.794483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23888 11:47:49.828095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23890 11:47:49.828659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23891 11:47:49.859982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23893 11:47:49.860540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23894 11:47:49.891864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23895 11:47:49.892294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23897 11:47:49.923165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23898 11:47:49.923655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23900 11:47:49.954534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23902 11:47:49.955169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23903 11:47:49.985816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23904 11:47:49.986293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23906 11:47:50.019632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23907 11:47:50.020108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23909 11:47:50.052144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23910 11:47:50.052602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23912 11:47:50.083773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23914 11:47:50.084236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23915 11:47:50.115208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23916 11:47:50.115625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23918 11:47:50.147079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23919 11:47:50.147482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23921 11:47:50.200163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23922 11:47:50.200586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23924 11:47:50.232820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23926 11:47:50.233417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23927 11:47:50.263859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23928 11:47:50.264291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23930 11:47:50.295248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23931 11:47:50.295687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23933 11:47:50.326250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
23935 11:47:50.326710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23936 11:47:50.357624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
23938 11:47:50.358261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
23939 11:47:50.389258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
23940 11:47:50.389705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
23942 11:47:50.420535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
23944 11:47:50.421096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
23945 11:47:50.452849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
23947 11:47:50.453330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
23948 11:47:50.485271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
23950 11:47:50.485756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
23951 11:47:50.519183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
23952 11:47:50.519642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
23954 11:47:50.550781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
23955 11:47:50.551207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
23957 11:47:50.582789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
23958 11:47:50.583246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
23960 11:47:50.614790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
23961 11:47:50.615244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
23963 11:47:50.646888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
23965 11:47:50.647355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
23966 11:47:50.679319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
23967 11:47:50.679766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
23969 11:47:50.713721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
23971 11:47:50.714335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
23972 11:47:50.745481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
23973 11:47:50.745960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
23975 11:47:50.777130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
23977 11:47:50.777767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
23978 11:47:50.808978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
23979 11:47:50.809430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
23981 11:47:50.842263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
23983 11:47:50.842902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
23984 11:47:50.873801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
23985 11:47:50.874286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
23987 11:47:50.905596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
23988 11:47:50.906084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
23990 11:47:50.937542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
23992 11:47:50.938017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
23993 11:47:50.969072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
23994 11:47:50.969557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
23996 11:47:51.001463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
23998 11:47:51.001925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
23999 11:47:51.033562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
24001 11:47:51.034031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
24002 11:47:51.065096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
24003 11:47:51.065570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
24005 11:47:51.096973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
24006 11:47:51.097424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
24008 11:47:51.128201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
24009 11:47:51.128625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
24011 11:47:51.159452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
24012 11:47:51.159932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
24014 11:47:51.192086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
24015 11:47:51.192572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
24017 11:47:51.226887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
24019 11:47:51.227502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
24020 11:47:51.259193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
24022 11:47:51.259674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
24023 11:47:51.291795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
24025 11:47:51.292263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
24026 11:47:51.324188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
24027 11:47:51.324652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
24029 11:47:51.357716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
24031 11:47:51.358291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
24032 11:47:51.391095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
24034 11:47:51.391540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
24035 11:47:51.425342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
24037 11:47:51.425922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
24038 11:47:51.457976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
24040 11:47:51.458522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
24041 11:47:51.490248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
24042 11:47:51.490656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
24044 11:47:51.523672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
24045 11:47:51.524086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
24047 11:47:51.556032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
24048 11:47:51.556492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
24050 11:47:51.587825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
24051 11:47:51.588221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
24053 11:47:51.620047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
24054 11:47:51.620455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
24056 11:47:51.653722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
24057 11:47:51.654167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
24059 11:47:51.686991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
24060 11:47:51.687462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
24062 11:47:51.723411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
24063 11:47:51.723804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
24065 11:47:51.761205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
24067 11:47:51.761787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
24068 11:47:51.796932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
24070 11:47:51.797496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
24071 11:47:51.828645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
24072 11:47:51.829124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
24074 11:47:51.860175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
24076 11:47:51.860736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
24077 11:47:51.893102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
24079 11:47:51.893673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
24080 11:47:51.924555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
24082 11:47:51.925115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
24083 11:47:51.955922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
24084 11:47:51.956356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
24086 11:47:51.987115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
24087 11:47:51.987541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
24089 11:47:52.017977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
24091 11:47:52.018443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
24092 11:47:52.049494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
24093 11:47:52.049905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
24095 11:47:52.080922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
24097 11:47:52.081344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
24098 11:47:52.111689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
24099 11:47:52.112118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
24101 11:47:52.143030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
24102 11:47:52.143501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
24104 11:47:52.174157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
24105 11:47:52.174610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
24107 11:47:52.205732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
24108 11:47:52.206186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
24110 11:47:52.237274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
24111 11:47:52.237699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
24113 11:47:52.272155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
24114 11:47:52.272643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
24116 11:47:52.304061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
24117 11:47:52.304553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
24119 11:47:52.335985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
24120 11:47:52.336454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
24122 11:47:52.367287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
24123 11:47:52.367781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
24125 11:47:52.398088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
24126 11:47:52.398506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
24128 11:47:52.429643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
24129 11:47:52.430105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
24131 11:47:52.460971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
24132 11:47:52.461449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
24134 11:47:52.492203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
24135 11:47:52.492721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
24137 11:47:52.525074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
24138 11:47:52.525482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
24140 11:47:52.557376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
24141 11:47:52.557895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
24143 11:47:52.588661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
24145 11:47:52.589216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
24146 11:47:52.620024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
24147 11:47:52.620450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
24149 11:47:52.651476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
24151 11:47:52.651950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
24152 11:47:52.682544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
24154 11:47:52.683025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
24155 11:47:52.713941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
24156 11:47:52.714367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
24158 11:47:52.746291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
24159 11:47:52.746774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
24161 11:47:52.778007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
24162 11:47:52.778476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
24164 11:47:52.809564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
24166 11:47:52.810185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
24167 11:47:52.841608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
24168 11:47:52.842043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
24170 11:47:52.873636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
24171 11:47:52.874070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
24173 11:47:52.906211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
24174 11:47:52.906631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
24176 11:47:52.937527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
24177 11:47:52.937931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
24179 11:47:52.969448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24181 11:47:52.969917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
24182 11:47:53.000365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24184 11:47:53.000839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24185 11:47:53.031412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24186 11:47:53.031839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24188 11:47:53.062963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24189 11:47:53.063387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24191 11:47:53.094229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24192 11:47:53.094659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24194 11:47:53.125508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24195 11:47:53.125938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24197 11:47:53.157365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24198 11:47:53.157856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24200 11:47:53.189213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24201 11:47:53.189682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24203 11:47:53.220929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24205 11:47:53.221482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24206 11:47:53.252061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24207 11:47:53.252528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24209 11:47:53.283596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24210 11:47:53.283986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24212 11:47:53.315067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24213 11:47:53.315506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24215 11:47:53.346996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24216 11:47:53.347421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24218 11:47:53.378818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24220 11:47:53.379271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24221 11:47:53.410419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24222 11:47:53.410886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24224 11:47:53.441508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24226 11:47:53.442090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24227 11:47:53.473263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24228 11:47:53.473694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24230 11:47:53.505420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24231 11:47:53.505904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24233 11:47:53.536944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24234 11:47:53.537422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24236 11:47:53.567999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24238 11:47:53.568465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24239 11:47:53.598842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24241 11:47:53.599296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24242 11:47:53.630114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24243 11:47:53.630559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24245 11:47:53.661352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24246 11:47:53.661759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24248 11:47:53.692779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24250 11:47:53.693214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24251 11:47:53.724085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24252 11:47:53.724553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24254 11:47:53.755928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24256 11:47:53.756496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24257 11:47:53.787339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24258 11:47:53.787760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24260 11:47:53.819359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24261 11:47:53.819789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24263 11:47:53.851211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24264 11:47:53.851664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24266 11:47:53.883224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24268 11:47:53.883711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24269 11:47:53.915894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24271 11:47:53.916360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24272 11:47:53.947614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24274 11:47:53.948085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24275 11:47:53.979590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24277 11:47:53.980045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24278 11:47:54.011769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24279 11:47:54.012182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24281 11:47:54.045079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24282 11:47:54.045547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24284 11:47:54.076855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24286 11:47:54.077282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24287 11:47:54.108276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24289 11:47:54.108757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24290 11:47:54.139654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24292 11:47:54.140222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24293 11:47:54.171428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24295 11:47:54.171974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24296 11:47:54.203483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24298 11:47:54.204041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24299 11:47:54.235352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24300 11:47:54.235807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24302 11:47:54.267125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24303 11:47:54.267587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24305 11:47:54.299258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24307 11:47:54.299826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24308 11:47:54.332050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24310 11:47:54.332511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24311 11:47:54.363448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24312 11:47:54.363870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24314 11:47:54.395406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24315 11:47:54.395908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24317 11:47:54.427414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24318 11:47:54.427874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24320 11:47:54.459519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24321 11:47:54.459975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24323 11:47:54.491912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24324 11:47:54.492404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24326 11:47:54.525039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24328 11:47:54.525717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24329 11:47:54.556226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24330 11:47:54.556697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24332 11:47:54.588111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24334 11:47:54.588750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24335 11:47:54.619835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24336 11:47:54.620323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24338 11:47:54.651122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24339 11:47:54.651594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24341 11:47:54.682345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24343 11:47:54.682969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24344 11:47:54.713517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24345 11:47:54.714011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24347 11:47:54.745488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24349 11:47:54.745955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24350 11:47:54.777303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24352 11:47:54.777965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24353 11:47:54.808693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24355 11:47:54.809334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24356 11:47:54.839652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24358 11:47:54.840215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24359 11:47:54.870906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24360 11:47:54.871312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24362 11:47:54.902139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24363 11:47:54.902531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24365 11:47:54.933951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24366 11:47:54.934376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24368 11:47:54.966203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24369 11:47:54.966633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24371 11:47:54.997946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24372 11:47:54.998371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24374 11:47:55.029780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24375 11:47:55.030200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24377 11:47:55.061718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24378 11:47:55.062216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24380 11:47:55.093484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24382 11:47:55.094142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24383 11:47:55.125096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24384 11:47:55.125569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24386 11:47:55.157939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24387 11:47:55.158358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24389 11:47:55.189383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24390 11:47:55.189863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24392 11:47:55.221262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24394 11:47:55.221847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24395 11:47:55.252904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24396 11:47:55.253351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24398 11:47:55.284397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24400 11:47:55.289018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24401 11:47:55.339701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24403 11:47:55.340165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24404 11:47:55.371219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24406 11:47:55.371680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24407 11:47:55.402552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24409 11:47:55.403124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24410 11:47:55.433967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24411 11:47:55.434433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24413 11:47:55.466103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24414 11:47:55.466543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24416 11:47:55.497470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24417 11:47:55.497966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24419 11:47:55.531745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24420 11:47:55.532227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24422 11:47:55.563399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24424 11:47:55.563941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24425 11:47:55.595089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24426 11:47:55.595537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24428 11:47:55.626999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24430 11:47:55.627689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24431 11:47:55.658427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24433 11:47:55.659060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24434 11:47:55.689506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24435 11:47:55.689995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24437 11:47:55.720697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24439 11:47:55.721330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24440 11:47:55.751234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24441 11:47:55.751708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24443 11:47:55.783223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24444 11:47:55.783678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24446 11:47:55.815453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24447 11:47:55.815869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24449 11:47:55.846168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24450 11:47:55.846594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24452 11:47:55.877124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24453 11:47:55.877588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24455 11:47:55.907830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24457 11:47:55.908491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24458 11:47:55.938584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24459 11:47:55.939003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24461 11:47:55.970073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24463 11:47:55.970552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24464 11:47:56.003255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24466 11:47:56.003731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24467 11:47:56.035449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24469 11:47:56.035811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24470 11:47:56.066851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24471 11:47:56.067277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24473 11:47:56.100228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24475 11:47:56.100700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24476 11:47:56.131311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24478 11:47:56.131778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24479 11:47:56.162806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24481 11:47:56.163362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24482 11:47:56.194298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24483 11:47:56.194697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24485 11:47:56.226383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24486 11:47:56.226836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24488 11:47:56.257809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24489 11:47:56.258257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24491 11:47:56.289697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24492 11:47:56.290129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24494 11:47:56.321374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24495 11:47:56.321850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24497 11:47:56.353228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24499 11:47:56.353925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24500 11:47:56.387347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24502 11:47:56.387900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24503 11:47:56.423032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24505 11:47:56.423403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24506 11:47:56.459680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24507 11:47:56.460109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24509 11:47:56.494185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24510 11:47:56.494687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24512 11:47:56.528107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24513 11:47:56.528658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24515 11:47:56.561675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24516 11:47:56.562221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24518 11:47:56.593709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24519 11:47:56.594172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24521 11:47:56.625506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24522 11:47:56.625998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24524 11:47:56.658836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24525 11:47:56.659279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24527 11:47:56.693547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24529 11:47:56.694214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24530 11:47:56.728213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24531 11:47:56.728678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24533 11:47:56.763452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24534 11:47:56.763942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24536 11:47:56.798951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24537 11:47:56.799383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24539 11:47:56.835235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24540 11:47:56.835740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24542 11:47:56.867976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24544 11:47:56.868571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24545 11:47:56.900079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24546 11:47:56.900539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24548 11:47:56.931908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24549 11:47:56.932320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24551 11:47:56.963293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24552 11:47:56.963739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24554 11:47:56.994735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24555 11:47:56.995199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24557 11:47:57.026909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24558 11:47:57.027388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24560 11:47:57.058654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24562 11:47:57.059209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24563 11:47:57.089727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24564 11:47:57.090179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24566 11:47:57.121344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24567 11:47:57.121798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24569 11:47:57.153075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24570 11:47:57.153549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24572 11:47:57.184184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24574 11:47:57.184646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24575 11:47:57.215868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24576 11:47:57.216349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24578 11:47:57.247804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24579 11:47:57.248281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24581 11:47:57.279723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24582 11:47:57.280190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24584 11:47:57.310922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24585 11:47:57.311345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24587 11:47:57.343892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24589 11:47:57.344665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24590 11:47:57.376896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24592 11:47:57.377442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24593 11:47:57.408117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24594 11:47:57.408590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24596 11:47:57.440981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24598 11:47:57.441601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24599 11:47:57.472609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24601 11:47:57.473026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24602 11:47:57.504976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24603 11:47:57.505410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24605 11:47:57.537493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24606 11:47:57.538007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24608 11:47:57.572323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24610 11:47:57.572915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24611 11:47:57.605349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24612 11:47:57.605770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24614 11:47:57.636296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24615 11:47:57.636757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24617 11:47:57.667810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24618 11:47:57.668301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24620 11:47:57.699285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24621 11:47:57.699740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24623 11:47:57.731100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24625 11:47:57.731749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24626 11:47:57.762857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24628 11:47:57.763495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24629 11:47:57.796454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24631 11:47:57.796922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24632 11:47:57.830599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24633 11:47:57.831028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24635 11:47:57.863224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24637 11:47:57.863675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24638 11:47:57.895915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24640 11:47:57.896364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24641 11:47:57.927458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24643 11:47:57.927880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24644 11:47:57.958716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24645 11:47:57.959105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24647 11:47:57.990435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24648 11:47:57.990813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24650 11:47:58.022084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24651 11:47:58.022529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24653 11:47:58.053929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24655 11:47:58.054557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24656 11:47:58.085948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24658 11:47:58.086497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24659 11:47:58.117509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24661 11:47:58.118075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24662 11:47:58.149442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24664 11:47:58.150008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24665 11:47:58.181519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24666 11:47:58.182076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24668 11:47:58.214118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24670 11:47:58.214588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24671 11:47:58.246644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24672 11:47:58.247141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24674 11:47:58.280958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24675 11:47:58.281395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24677 11:47:58.317031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24678 11:47:58.317510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24680 11:47:58.355304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24682 11:47:58.355771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24683 11:47:58.388880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24684 11:47:58.389319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24686 11:47:58.421641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24688 11:47:58.422109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24689 11:47:58.457711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24690 11:47:58.458123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24692 11:47:58.489898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24693 11:47:58.490321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24695 11:47:58.521468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24696 11:47:58.521848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24698 11:47:58.553183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24699 11:47:58.553666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24701 11:47:58.585502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24702 11:47:58.585967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24704 11:47:58.617087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24705 11:47:58.617532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24707 11:47:58.649172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24709 11:47:58.649756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24710 11:47:58.682731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24712 11:47:58.683292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24713 11:47:58.714255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24715 11:47:58.714800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24716 11:47:58.746575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24718 11:47:58.747113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24719 11:47:58.778526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24721 11:47:58.779082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24722 11:47:58.810372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24723 11:47:58.810852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24725 11:47:58.842016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24727 11:47:58.842581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24728 11:47:58.873895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24729 11:47:58.874343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24731 11:47:58.905659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24733 11:47:58.906198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24734 11:47:58.938517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24736 11:47:58.939122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24737 11:47:58.970569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24739 11:47:58.971129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24740 11:47:59.002067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24741 11:47:59.002476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24743 11:47:59.034031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24744 11:47:59.034434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24746 11:47:59.065897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24747 11:47:59.066307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24749 11:47:59.098297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24750 11:47:59.098681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24752 11:47:59.129657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24754 11:47:59.130119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24755 11:47:59.160582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24757 11:47:59.161038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24758 11:47:59.192059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24759 11:47:59.192537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24761 11:47:59.223313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24762 11:47:59.223785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24764 11:47:59.254770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24765 11:47:59.255292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24767 11:47:59.289159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24769 11:47:59.289621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24770 11:47:59.321535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24771 11:47:59.321973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24773 11:47:59.353531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24775 11:47:59.353998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24776 11:47:59.384503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24778 11:47:59.384947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24779 11:47:59.416039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24780 11:47:59.416493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24782 11:47:59.446904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24783 11:47:59.447396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24785 11:47:59.478344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24787 11:47:59.478956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24788 11:47:59.510039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24789 11:47:59.510518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24791 11:47:59.541887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24793 11:47:59.542443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24794 11:47:59.573552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24795 11:47:59.574010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24797 11:47:59.606276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24798 11:47:59.606751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24800 11:47:59.638456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24802 11:47:59.639047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24803 11:47:59.669880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24804 11:47:59.670343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24806 11:47:59.701353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24807 11:47:59.701830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24809 11:47:59.732203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24811 11:47:59.732765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24812 11:47:59.763587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24814 11:47:59.764151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24815 11:47:59.794932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24816 11:47:59.795311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24818 11:47:59.826615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24820 11:47:59.827221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24821 11:47:59.857865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24822 11:47:59.858410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24824 11:47:59.889324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24825 11:47:59.889793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24827 11:47:59.920912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24828 11:47:59.921376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24830 11:47:59.953248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24832 11:47:59.953824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24833 11:47:59.984579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24835 11:47:59.985043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24836 11:48:00.016036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24838 11:48:00.016615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24839 11:48:00.047323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24840 11:48:00.047746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24842 11:48:00.078565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24844 11:48:00.079129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24845 11:48:00.110589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24847 11:48:00.111228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24848 11:48:00.142221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24850 11:48:00.142682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24851 11:48:00.173452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24853 11:48:00.173913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24854 11:48:00.204998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24855 11:48:00.205413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24857 11:48:00.236414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24859 11:48:00.236861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24860 11:48:00.268020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24861 11:48:00.268511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24863 11:48:00.299357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24864 11:48:00.299825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24866 11:48:00.331102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24868 11:48:00.331662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24869 11:48:00.362665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24870 11:48:00.363143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24872 11:48:00.394348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24874 11:48:00.394898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24875 11:48:00.447701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24877 11:48:00.448247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24878 11:48:00.478767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24880 11:48:00.479175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24881 11:48:00.509900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24882 11:48:00.510304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24884 11:48:00.542069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24886 11:48:00.542514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24887 11:48:00.573912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24889 11:48:00.574462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24890 11:48:00.605369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24892 11:48:00.605934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24893 11:48:00.637504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24894 11:48:00.637984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24896 11:48:00.668904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24898 11:48:00.669464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24899 11:48:00.699817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24900 11:48:00.700270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24902 11:48:00.731420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24903 11:48:00.731885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24905 11:48:00.763015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24906 11:48:00.763461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24908 11:48:00.794649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24909 11:48:00.795100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24911 11:48:00.825728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24912 11:48:00.826172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24914 11:48:00.857693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24915 11:48:00.858078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24917 11:48:00.889581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24919 11:48:00.890146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24920 11:48:00.922231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24921 11:48:00.922711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24923 11:48:00.954257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24925 11:48:00.954812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24926 11:48:00.986496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24927 11:48:00.986921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24929 11:48:01.018269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24930 11:48:01.018727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24932 11:48:01.049770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24933 11:48:01.050195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24935 11:48:01.081378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
24936 11:48:01.081877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
24938 11:48:01.116552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
24940 11:48:01.117021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
24941 11:48:01.149665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
24943 11:48:01.150112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
24944 11:48:01.182647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
24945 11:48:01.183091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
24947 11:48:01.217026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
24948 11:48:01.217522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
24950 11:48:01.250089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
24952 11:48:01.250536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
24953 11:48:01.281575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
24954 11:48:01.281980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
24956 11:48:01.313884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
24957 11:48:01.314365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
24959 11:48:01.348153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
24961 11:48:01.348706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
24962 11:48:01.380028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
24964 11:48:01.380517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
24965 11:48:01.414841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
24966 11:48:01.415256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
24968 11:48:01.447667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
24970 11:48:01.448118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
24971 11:48:01.481624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
24972 11:48:01.482043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
24974 11:48:01.516207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
24975 11:48:01.516623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
24977 11:48:01.551503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
24978 11:48:01.551924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
24980 11:48:01.586620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
24981 11:48:01.587055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
24983 11:48:01.618640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
24984 11:48:01.619079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
24986 11:48:01.650907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
24987 11:48:01.651331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
24989 11:48:01.684056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
24990 11:48:01.684569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
24992 11:48:01.716088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
24994 11:48:01.716895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
24995 11:48:01.748545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
24997 11:48:01.749016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
24998 11:48:01.781636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
24999 11:48:01.782074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
25001 11:48:01.814517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
25002 11:48:01.814947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
25004 11:48:01.848204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
25005 11:48:01.848628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
25007 11:48:01.880611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
25009 11:48:01.881076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
25010 11:48:01.911905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
25012 11:48:01.912522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
25013 11:48:01.943726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
25014 11:48:01.944198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
25016 11:48:01.975048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
25018 11:48:01.975700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
25019 11:48:02.006198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
25021 11:48:02.006831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
25022 11:48:02.038377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
25024 11:48:02.038827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
25025 11:48:02.070007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
25027 11:48:02.070572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
25028 11:48:02.101615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
25030 11:48:02.102182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
25031 11:48:02.132829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
25032 11:48:02.133316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
25034 11:48:02.164154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
25035 11:48:02.164686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
25037 11:48:02.198107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
25038 11:48:02.198575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
25040 11:48:02.229739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
25041 11:48:02.230195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
25043 11:48:02.261070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
25044 11:48:02.261477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
25046 11:48:02.292813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
25048 11:48:02.293443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
25049 11:48:02.323930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
25051 11:48:02.324527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
25052 11:48:02.354542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
25053 11:48:02.355049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
25055 11:48:02.386117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
25057 11:48:02.386703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
25058 11:48:02.417678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
25059 11:48:02.418141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
25061 11:48:02.451197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
25062 11:48:02.451656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
25064 11:48:02.482989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
25065 11:48:02.483441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
25067 11:48:02.515293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
25068 11:48:02.515746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
25070 11:48:02.546670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
25071 11:48:02.547112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
25073 11:48:02.578141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
25074 11:48:02.578590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
25076 11:48:02.610992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
25077 11:48:02.611454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
25079 11:48:02.645283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
25080 11:48:02.645751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
25082 11:48:02.680455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
25084 11:48:02.680943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
25085 11:48:02.713843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
25087 11:48:02.714314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
25088 11:48:02.753697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
25090 11:48:02.754169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
25091 11:48:02.790267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
25092 11:48:02.790710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
25094 11:48:02.824211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
25095 11:48:02.824621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
25097 11:48:02.859689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
25098 11:48:02.860175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
25100 11:48:02.892146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
25101 11:48:02.892593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
25103 11:48:02.923935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
25104 11:48:02.924382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
25106 11:48:02.955568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
25107 11:48:02.956003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
25109 11:48:02.986977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
25111 11:48:02.987489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
25112 11:48:03.018270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
25114 11:48:03.018916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
25115 11:48:03.049683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
25116 11:48:03.050107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
25118 11:48:03.081962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
25119 11:48:03.082426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
25121 11:48:03.115021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
25122 11:48:03.115501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
25124 11:48:03.146729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
25126 11:48:03.147315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
25127 11:48:03.183155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
25128 11:48:03.183623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
25130 11:48:03.216561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
25132 11:48:03.217156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
25133 11:48:03.249732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
25134 11:48:03.250192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
25136 11:48:03.281754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
25137 11:48:03.282237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
25139 11:48:03.314189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
25140 11:48:03.314652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
25142 11:48:03.348089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
25143 11:48:03.348524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
25145 11:48:03.380981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
25146 11:48:03.381441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
25148 11:48:03.412582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
25150 11:48:03.413041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
25151 11:48:03.445135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
25152 11:48:03.445670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
25154 11:48:03.478107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
25156 11:48:03.478559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
25157 11:48:03.512285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
25159 11:48:03.512993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
25160 11:48:03.545203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
25161 11:48:03.545643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
25163 11:48:03.577515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
25164 11:48:03.577984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
25166 11:48:03.609571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
25167 11:48:03.610037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
25169 11:48:03.642402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
25170 11:48:03.642806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
25172 11:48:03.675508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
25173 11:48:03.675958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
25175 11:48:03.707412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
25177 11:48:03.707876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
25178 11:48:03.738685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25179 11:48:03.739072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
25181 11:48:03.770013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25182 11:48:03.770419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25184 11:48:03.801909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25185 11:48:03.802340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25187 11:48:03.834010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25188 11:48:03.834414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25190 11:48:03.865917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25191 11:48:03.866316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25193 11:48:03.898090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25194 11:48:03.898500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25196 11:48:03.930522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25198 11:48:03.931084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25199 11:48:03.961667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25200 11:48:03.962094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25202 11:48:03.993716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25203 11:48:03.994186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25205 11:48:04.025075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25206 11:48:04.025501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25208 11:48:04.056763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25209 11:48:04.057182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25211 11:48:04.088052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25212 11:48:04.088448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25214 11:48:04.119508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25216 11:48:04.120163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25217 11:48:04.151223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25218 11:48:04.151679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25220 11:48:04.183367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25222 11:48:04.183938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25223 11:48:04.215283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25224 11:48:04.215701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25226 11:48:04.247503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25227 11:48:04.247904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25229 11:48:04.279777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25231 11:48:04.280420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25232 11:48:04.311619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25234 11:48:04.312172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25235 11:48:04.343323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25236 11:48:04.343778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25238 11:48:04.375444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25239 11:48:04.375893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25241 11:48:04.407322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25242 11:48:04.407854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25244 11:48:04.438859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25245 11:48:04.439325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25247 11:48:04.470658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25249 11:48:04.471118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25250 11:48:04.502412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25252 11:48:04.502975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25253 11:48:04.534476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25255 11:48:04.535078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25256 11:48:04.566105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25257 11:48:04.566515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25259 11:48:04.597820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25260 11:48:04.598277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25262 11:48:04.629594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25263 11:48:04.630062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25265 11:48:04.661288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25266 11:48:04.661737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25268 11:48:04.693705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25270 11:48:04.694258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25271 11:48:04.725577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25272 11:48:04.725992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25274 11:48:04.757523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25275 11:48:04.757942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25277 11:48:04.789449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25278 11:48:04.789879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25280 11:48:04.821300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25281 11:48:04.821741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25283 11:48:04.852918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25285 11:48:04.853380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25286 11:48:04.884275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25287 11:48:04.884696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25289 11:48:04.915658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25291 11:48:04.916130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25292 11:48:04.946913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25293 11:48:04.947357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25295 11:48:04.978161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25296 11:48:04.978610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25298 11:48:05.009536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25300 11:48:05.010002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25301 11:48:05.041125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25303 11:48:05.041771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25304 11:48:05.071908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25305 11:48:05.072330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25307 11:48:05.103083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25309 11:48:05.103540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25310 11:48:05.134822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25311 11:48:05.135207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25313 11:48:05.166227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25314 11:48:05.166663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25316 11:48:05.197318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25317 11:48:05.197766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25319 11:48:05.229074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25321 11:48:05.229549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25322 11:48:05.260443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25324 11:48:05.260910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25325 11:48:05.293251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25326 11:48:05.293678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25328 11:48:05.323983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25329 11:48:05.324422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25331 11:48:05.355270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25333 11:48:05.355727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25334 11:48:05.386272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25335 11:48:05.386682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25337 11:48:05.417418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25338 11:48:05.417817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25340 11:48:05.448486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25342 11:48:05.448910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25343 11:48:05.479604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25345 11:48:05.480080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25346 11:48:05.510512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25347 11:48:05.510927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25349 11:48:05.563253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25350 11:48:05.563665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25352 11:48:05.594719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25354 11:48:05.595163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25355 11:48:05.626108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25356 11:48:05.626512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25358 11:48:05.657734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25359 11:48:05.658162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25361 11:48:05.689328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25362 11:48:05.689757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25364 11:48:05.721442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25365 11:48:05.721914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25367 11:48:05.753363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25369 11:48:05.754005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25370 11:48:05.784902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25372 11:48:05.785376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25373 11:48:05.816108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25374 11:48:05.816574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25376 11:48:05.847500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25378 11:48:05.848161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25379 11:48:05.879714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25380 11:48:05.880113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25382 11:48:05.911633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25383 11:48:05.912070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25385 11:48:05.943477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25386 11:48:05.943872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25388 11:48:05.975175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25389 11:48:05.975592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25391 11:48:06.006132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25393 11:48:06.006688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25394 11:48:06.037246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25395 11:48:06.037696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25397 11:48:06.068866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25398 11:48:06.069287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25400 11:48:06.100004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25401 11:48:06.100427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25403 11:48:06.131637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25405 11:48:06.132282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25406 11:48:06.163978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25407 11:48:06.164389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25409 11:48:06.195792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25410 11:48:06.196206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25412 11:48:06.227782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25413 11:48:06.228166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25415 11:48:06.259713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25416 11:48:06.260163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25418 11:48:06.291925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25419 11:48:06.292387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25421 11:48:06.326665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25422 11:48:06.327127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25424 11:48:06.361918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25425 11:48:06.362326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25427 11:48:06.397475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25428 11:48:06.397854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25430 11:48:06.433607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25432 11:48:06.434179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25433 11:48:06.469800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25435 11:48:06.470353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25436 11:48:06.507023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25438 11:48:06.507562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25439 11:48:06.542025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25440 11:48:06.542419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25442 11:48:06.577241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25443 11:48:06.577698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25445 11:48:06.612944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25446 11:48:06.613386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25448 11:48:06.647828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25450 11:48:06.648447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25451 11:48:06.682899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25452 11:48:06.683317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25454 11:48:06.720665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25456 11:48:06.721455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25457 11:48:06.755536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25458 11:48:06.756002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25460 11:48:06.791377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25462 11:48:06.791814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25463 11:48:06.826755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25464 11:48:06.827218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25466 11:48:06.862007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25467 11:48:06.862410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25469 11:48:06.896924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25470 11:48:06.897265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25472 11:48:06.931666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25473 11:48:06.932128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25475 11:48:06.966563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25476 11:48:06.966983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25478 11:48:07.001745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25480 11:48:07.002289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25481 11:48:07.036897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25482 11:48:07.037283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25484 11:48:07.071798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25486 11:48:07.072353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25487 11:48:07.106502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25488 11:48:07.106920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25490 11:48:07.141363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25491 11:48:07.141785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25493 11:48:07.176232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25494 11:48:07.176707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25496 11:48:07.211340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25497 11:48:07.211806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25499 11:48:07.245857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25500 11:48:07.246327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25502 11:48:07.281625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25503 11:48:07.282101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25505 11:48:07.316547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25507 11:48:07.317086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25508 11:48:07.351451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25509 11:48:07.351949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25511 11:48:07.386256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25512 11:48:07.386710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25514 11:48:07.420992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25515 11:48:07.421434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25517 11:48:07.456092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25518 11:48:07.456533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25520 11:48:07.491075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25522 11:48:07.491538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25523 11:48:07.526076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25524 11:48:07.526503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25526 11:48:07.561167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25527 11:48:07.561657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25529 11:48:07.595957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25530 11:48:07.596464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25532 11:48:07.630508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25534 11:48:07.631132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25535 11:48:07.664983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25536 11:48:07.665426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25538 11:48:07.700193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25539 11:48:07.700623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25541 11:48:07.735777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25543 11:48:07.736248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25544 11:48:07.770675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25546 11:48:07.771149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25547 11:48:07.806266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25549 11:48:07.806736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25550 11:48:07.842518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25552 11:48:07.843162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25553 11:48:07.878221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25554 11:48:07.878647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25556 11:48:07.915847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25558 11:48:07.916314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25559 11:48:07.953219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25560 11:48:07.953665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25562 11:48:07.988491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25564 11:48:07.988958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25565 11:48:08.025102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25566 11:48:08.025588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25568 11:48:08.060102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25569 11:48:08.060598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25571 11:48:08.096195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25572 11:48:08.096604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25574 11:48:08.132515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25576 11:48:08.133075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25577 11:48:08.171256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25579 11:48:08.171905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25580 11:48:08.207417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25582 11:48:08.207995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25583 11:48:08.242752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25584 11:48:08.243176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25586 11:48:08.278869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25587 11:48:08.279311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25589 11:48:08.313949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25590 11:48:08.314414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25592 11:48:08.349078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25593 11:48:08.349556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25595 11:48:08.384745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25596 11:48:08.385231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25598 11:48:08.421276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25599 11:48:08.421686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25601 11:48:08.456461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25603 11:48:08.456923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25604 11:48:08.492519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25606 11:48:08.493130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25607 11:48:08.528954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25609 11:48:08.529534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25610 11:48:08.564070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25612 11:48:08.564640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25613 11:48:08.600455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25615 11:48:08.600999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25616 11:48:08.635878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25617 11:48:08.636316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25619 11:48:08.671423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25620 11:48:08.671845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25622 11:48:08.706643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25623 11:48:08.707011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25625 11:48:08.742449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25627 11:48:08.742915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25628 11:48:08.778545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25629 11:48:08.778978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25631 11:48:08.814331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25633 11:48:08.814872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25634 11:48:08.849818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25635 11:48:08.850240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25637 11:48:08.885358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25638 11:48:08.885791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25640 11:48:08.920827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25641 11:48:08.921234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25643 11:48:08.956607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25645 11:48:08.957024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25646 11:48:08.991920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25647 11:48:08.992293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25649 11:48:09.027654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25651 11:48:09.028130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25652 11:48:09.063361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25654 11:48:09.064034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25655 11:48:09.099210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25656 11:48:09.099710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25658 11:48:09.134571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25659 11:48:09.135049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25661 11:48:09.170265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25662 11:48:09.170725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25664 11:48:09.205917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25666 11:48:09.206403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25667 11:48:09.241375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25668 11:48:09.241792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25670 11:48:09.277146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25671 11:48:09.277610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25673 11:48:09.313407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25674 11:48:09.313877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25676 11:48:09.350107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25678 11:48:09.350671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25679 11:48:09.385903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25681 11:48:09.386467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25682 11:48:09.421585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25683 11:48:09.422071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25685 11:48:09.457915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25686 11:48:09.458329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25688 11:48:09.493897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25689 11:48:09.494310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25691 11:48:09.529845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25692 11:48:09.530266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25694 11:48:09.566464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25696 11:48:09.567107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25697 11:48:09.601837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25698 11:48:09.602280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25700 11:48:09.637605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25701 11:48:09.638038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25703 11:48:09.673258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25704 11:48:09.673618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25706 11:48:09.709153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25707 11:48:09.709523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25709 11:48:09.745415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25710 11:48:09.745779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25712 11:48:09.781205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25714 11:48:09.781642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25715 11:48:09.817279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25716 11:48:09.817690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25718 11:48:09.852859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25719 11:48:09.853222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25721 11:48:09.887951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25722 11:48:09.888373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25724 11:48:09.922626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25726 11:48:09.923043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25727 11:48:09.957920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25728 11:48:09.958285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25730 11:48:09.993235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25732 11:48:09.993693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25733 11:48:10.028654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25735 11:48:10.029116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25736 11:48:10.063970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25737 11:48:10.064453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25739 11:48:10.099504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25741 11:48:10.099962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25742 11:48:10.135415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25743 11:48:10.135826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25745 11:48:10.170534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25746 11:48:10.170951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25748 11:48:10.206447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25750 11:48:10.206897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25751 11:48:10.241884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25752 11:48:10.242298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25754 11:48:10.277262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25755 11:48:10.277680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25757 11:48:10.313987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25758 11:48:10.314472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25760 11:48:10.349384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25761 11:48:10.349871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25763 11:48:10.385177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25764 11:48:10.385609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25766 11:48:10.419989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25767 11:48:10.420411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25769 11:48:10.455278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25771 11:48:10.455924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25772 11:48:10.490585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25774 11:48:10.491157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25775 11:48:10.525798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25776 11:48:10.526228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25778 11:48:10.561565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25779 11:48:10.561987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25781 11:48:10.597035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25782 11:48:10.597473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25784 11:48:10.632610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25786 11:48:10.633204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25787 11:48:10.702422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25788 11:48:10.702897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25790 11:48:10.737959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25791 11:48:10.738377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25793 11:48:10.773202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25794 11:48:10.773616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25796 11:48:10.809141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25798 11:48:10.809687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25799 11:48:10.844024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25801 11:48:10.844564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25802 11:48:10.879423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25804 11:48:10.879967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25805 11:48:10.915703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25806 11:48:10.916140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25808 11:48:10.951348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25809 11:48:10.951773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25811 11:48:10.986818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25813 11:48:10.987406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25814 11:48:11.021886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25816 11:48:11.022438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25817 11:48:11.056927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25818 11:48:11.057358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25820 11:48:11.092174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25822 11:48:11.092678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25823 11:48:11.127984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25825 11:48:11.128510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25826 11:48:11.162720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25827 11:48:11.163144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25829 11:48:11.197324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25830 11:48:11.197684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25832 11:48:11.232373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25834 11:48:11.232843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25835 11:48:11.267971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25837 11:48:11.268446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25838 11:48:11.302788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25839 11:48:11.303158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25841 11:48:11.337612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25842 11:48:11.338078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25844 11:48:11.373915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25845 11:48:11.374326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25847 11:48:11.409997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25848 11:48:11.410434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25850 11:48:11.446771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25852 11:48:11.447214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25853 11:48:11.482707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25854 11:48:11.483108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25856 11:48:11.521175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25858 11:48:11.521631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25859 11:48:11.566242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25860 11:48:11.566700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25862 11:48:11.625308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25863 11:48:11.625682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25865 11:48:11.660971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25866 11:48:11.661381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25868 11:48:11.696935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25869 11:48:11.697312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25871 11:48:11.731676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25872 11:48:11.732097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25874 11:48:11.766931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25876 11:48:11.767419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25877 11:48:11.801679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25878 11:48:11.802102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25880 11:48:11.836225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25882 11:48:11.836703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25883 11:48:11.870350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25884 11:48:11.870819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25886 11:48:11.906525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25887 11:48:11.907013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25889 11:48:11.941305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25890 11:48:11.941684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25892 11:48:11.976205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25894 11:48:11.976553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25895 11:48:12.011311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25896 11:48:12.011661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25898 11:48:12.046484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25900 11:48:12.047017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25901 11:48:12.081957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25902 11:48:12.082416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25904 11:48:12.117278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25905 11:48:12.117739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25907 11:48:12.152060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25908 11:48:12.152479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25910 11:48:12.186810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25911 11:48:12.187234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25913 11:48:12.221785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25914 11:48:12.222214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25916 11:48:12.256649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25918 11:48:12.257210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25919 11:48:12.291617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25920 11:48:12.292099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25922 11:48:12.326746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25924 11:48:12.327296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25925 11:48:12.361800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25926 11:48:12.362268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25928 11:48:12.396826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25929 11:48:12.397293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25931 11:48:12.432036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25933 11:48:12.432598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25934 11:48:12.466981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
25936 11:48:12.467533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25937 11:48:12.501698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
25938 11:48:12.502155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
25940 11:48:12.545011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
25942 11:48:12.545471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
25943 11:48:12.579332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
25944 11:48:12.579755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
25946 11:48:12.614398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
25948 11:48:12.614979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
25949 11:48:12.651633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
25951 11:48:12.652197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
25952 11:48:12.687022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
25953 11:48:12.687432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
25955 11:48:12.721891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
25956 11:48:12.722353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
25958 11:48:12.757266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
25959 11:48:12.757681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
25961 11:48:12.791854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
25962 11:48:12.792231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
25964 11:48:12.827580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
25965 11:48:12.827955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
25967 11:48:12.862320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
25969 11:48:12.862889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
25970 11:48:12.897288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
25971 11:48:12.897660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
25973 11:48:12.932203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
25974 11:48:12.932631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
25976 11:48:12.967113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
25978 11:48:12.967581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
25979 11:48:13.001864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
25980 11:48:13.002283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
25982 11:48:13.037926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
25983 11:48:13.038349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
25985 11:48:13.073345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
25986 11:48:13.073774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
25988 11:48:13.107994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
25990 11:48:13.108452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
25991 11:48:13.142644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
25992 11:48:13.143033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
25994 11:48:13.177521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
25995 11:48:13.177957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
25997 11:48:13.212921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
25998 11:48:13.213341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
26000 11:48:13.247702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
26002 11:48:13.248297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
26003 11:48:13.282329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
26004 11:48:13.282781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
26006 11:48:13.317835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
26007 11:48:13.318295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
26009 11:48:13.353474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
26010 11:48:13.353956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
26012 11:48:13.387824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
26014 11:48:13.388287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
26015 11:48:13.422954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
26017 11:48:13.423412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
26018 11:48:13.457807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
26019 11:48:13.458241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
26021 11:48:13.493226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
26023 11:48:13.493688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
26024 11:48:13.528464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
26026 11:48:13.528923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
26027 11:48:13.563687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
26028 11:48:13.564183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
26030 11:48:13.598344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
26032 11:48:13.598877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
26033 11:48:13.633276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
26035 11:48:13.633749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
26036 11:48:13.669513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
26037 11:48:13.669989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
26039 11:48:13.704580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
26041 11:48:13.705128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
26042 11:48:13.739508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
26043 11:48:13.739938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
26045 11:48:13.774674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
26046 11:48:13.775083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
26048 11:48:13.810016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
26050 11:48:13.810598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
26051 11:48:13.844886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
26052 11:48:13.845303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
26054 11:48:13.879574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
26055 11:48:13.880005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
26057 11:48:13.914367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
26058 11:48:13.914833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
26060 11:48:13.949805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
26061 11:48:13.950246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
26063 11:48:13.985704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
26064 11:48:13.986124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
26066 11:48:14.021085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
26067 11:48:14.021505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
26069 11:48:14.056520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
26071 11:48:14.056973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
26072 11:48:14.091951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
26073 11:48:14.092441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
26075 11:48:14.127569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
26076 11:48:14.128027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
26078 11:48:14.163112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
26079 11:48:14.163568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
26081 11:48:14.198111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
26082 11:48:14.198568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
26084 11:48:14.233621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
26086 11:48:14.234043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
26087 11:48:14.268888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
26088 11:48:14.269319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
26090 11:48:14.303501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
26091 11:48:14.303897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
26093 11:48:14.338849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
26095 11:48:14.339447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
26096 11:48:14.373754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
26098 11:48:14.374288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
26099 11:48:14.408652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
26101 11:48:14.409200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
26102 11:48:14.443847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
26104 11:48:14.444474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
26105 11:48:14.478386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
26107 11:48:14.478952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
26108 11:48:14.513726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
26110 11:48:14.514285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
26111 11:48:14.548651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
26113 11:48:14.549205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
26114 11:48:14.583683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
26115 11:48:14.584158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
26117 11:48:14.618794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
26118 11:48:14.619253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
26120 11:48:14.653591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
26122 11:48:14.654187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
26123 11:48:14.689272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
26124 11:48:14.689694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
26126 11:48:14.725799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
26127 11:48:14.726228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
26129 11:48:14.761314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
26131 11:48:14.761786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
26132 11:48:14.797778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
26134 11:48:14.798272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
26135 11:48:14.833343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
26136 11:48:14.833785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
26138 11:48:14.869620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
26139 11:48:14.870065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
26141 11:48:14.905785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
26143 11:48:14.906222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
26144 11:48:14.941378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
26146 11:48:14.941865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
26147 11:48:14.977517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
26148 11:48:14.978007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
26150 11:48:15.013886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
26152 11:48:15.014455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
26153 11:48:15.049494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
26154 11:48:15.049899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
26156 11:48:15.086498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
26158 11:48:15.086950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
26159 11:48:15.122244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
26160 11:48:15.122612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
26162 11:48:15.157548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
26163 11:48:15.157976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
26165 11:48:15.193779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
26166 11:48:15.194204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
26168 11:48:15.229478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
26169 11:48:15.229908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
26171 11:48:15.265082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
26173 11:48:15.265551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
26174 11:48:15.300493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
26176 11:48:15.300966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
26177 11:48:15.336105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
26178 11:48:15.336528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26180 11:48:15.371787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26181 11:48:15.372220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26183 11:48:15.407563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26184 11:48:15.407986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26186 11:48:15.442804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26187 11:48:15.443228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26189 11:48:15.478910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26190 11:48:15.479339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26192 11:48:15.514715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26194 11:48:15.515190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26195 11:48:15.550050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26197 11:48:15.550684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26198 11:48:15.585977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26199 11:48:15.586404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26201 11:48:15.621457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26202 11:48:15.621945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26204 11:48:15.657091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26206 11:48:15.657734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26207 11:48:15.692594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26209 11:48:15.693053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26210 11:48:15.727706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26211 11:48:15.728211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26213 11:48:15.763305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26214 11:48:15.763774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26216 11:48:15.823311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26217 11:48:15.823728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26219 11:48:15.857663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26221 11:48:15.858130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26222 11:48:15.891178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26223 11:48:15.891585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26225 11:48:15.926426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26226 11:48:15.926838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26228 11:48:15.961854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26229 11:48:15.962293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26231 11:48:15.997637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26233 11:48:15.998104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26234 11:48:16.032517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26236 11:48:16.032967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26237 11:48:16.067635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26238 11:48:16.068044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26240 11:48:16.102439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26241 11:48:16.102857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26243 11:48:16.136498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26245 11:48:16.136953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26246 11:48:16.170580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26247 11:48:16.171014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26249 11:48:16.205393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26250 11:48:16.205784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26252 11:48:16.241468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26254 11:48:16.241923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26255 11:48:16.275257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26256 11:48:16.275678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26258 11:48:16.310588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26259 11:48:16.311052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26261 11:48:16.345407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26263 11:48:16.345964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26264 11:48:16.379810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26265 11:48:16.380275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26267 11:48:16.414153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26268 11:48:16.414607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26270 11:48:16.462205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26271 11:48:16.462665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26273 11:48:16.519261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26274 11:48:16.519676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26276 11:48:16.575721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26278 11:48:16.576200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26279 11:48:16.611658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26280 11:48:16.612145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26282 11:48:16.646263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26283 11:48:16.646741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26285 11:48:16.681283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26286 11:48:16.681767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26288 11:48:16.714782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26289 11:48:16.715236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26291 11:48:16.749719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26293 11:48:16.750203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26294 11:48:16.785463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26295 11:48:16.785951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26297 11:48:16.820185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26299 11:48:16.820825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26300 11:48:16.854780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26301 11:48:16.855271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26303 11:48:16.889061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26304 11:48:16.889559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26306 11:48:16.923881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26307 11:48:16.924356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26309 11:48:16.959082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26310 11:48:16.959565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26312 11:48:16.994097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26314 11:48:16.994660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26315 11:48:17.029808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26316 11:48:17.030281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26318 11:48:17.065955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26320 11:48:17.066504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26321 11:48:17.101728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26322 11:48:17.102202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26324 11:48:17.137239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26326 11:48:17.137701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26327 11:48:17.172999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26328 11:48:17.173395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26330 11:48:17.207864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26331 11:48:17.208339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26333 11:48:17.242619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26334 11:48:17.243037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26336 11:48:17.277335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26337 11:48:17.277779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26339 11:48:17.312662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26341 11:48:17.313130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26342 11:48:17.346933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26343 11:48:17.347350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26345 11:48:17.381883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26346 11:48:17.382320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26348 11:48:17.416132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26349 11:48:17.416552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26351 11:48:17.450579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26352 11:48:17.450997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26354 11:48:17.485907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26355 11:48:17.486341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26357 11:48:17.521048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26358 11:48:17.521491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26360 11:48:17.554978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26361 11:48:17.555410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26363 11:48:17.590069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26365 11:48:17.590541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26366 11:48:17.626078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26367 11:48:17.626512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26369 11:48:17.661006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26371 11:48:17.661463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26372 11:48:17.695727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26374 11:48:17.696190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26375 11:48:17.730304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26376 11:48:17.730773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26378 11:48:17.765010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26379 11:48:17.765481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26381 11:48:17.800401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26383 11:48:17.800992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26384 11:48:17.834467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26385 11:48:17.834938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26387 11:48:17.869396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26389 11:48:17.869871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26390 11:48:17.904657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26392 11:48:17.905207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26393 11:48:17.939147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26394 11:48:17.939605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26396 11:48:17.973789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26397 11:48:17.974256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26399 11:48:18.009487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26401 11:48:18.009974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26402 11:48:18.043936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26404 11:48:18.044399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26405 11:48:18.078694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26407 11:48:18.079153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26408 11:48:18.113544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26409 11:48:18.113985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26411 11:48:18.149208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26412 11:48:18.149623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26414 11:48:18.184966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26416 11:48:18.185418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26417 11:48:18.219953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26418 11:48:18.220382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26420 11:48:18.255511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26421 11:48:18.255969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26423 11:48:18.290057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26424 11:48:18.290528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26426 11:48:18.331411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26428 11:48:18.331860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26429 11:48:18.365677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26431 11:48:18.366223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26432 11:48:18.399841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26434 11:48:18.400437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26435 11:48:18.433922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26436 11:48:18.434371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26438 11:48:18.468481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26440 11:48:18.468938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26441 11:48:18.502894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26442 11:48:18.503301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26444 11:48:18.538045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26446 11:48:18.538510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26447 11:48:18.572598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26449 11:48:18.573058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26450 11:48:18.606938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26452 11:48:18.607575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26453 11:48:18.642346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26455 11:48:18.642919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26456 11:48:18.677786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26457 11:48:18.678242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26459 11:48:18.713215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26460 11:48:18.713695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26462 11:48:18.748489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26464 11:48:18.749115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26465 11:48:18.782895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26466 11:48:18.783320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26468 11:48:18.817765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26470 11:48:18.818244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26471 11:48:18.853719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26472 11:48:18.854142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26474 11:48:18.888903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26475 11:48:18.889318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26477 11:48:18.925000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26479 11:48:18.925564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26480 11:48:18.958978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26481 11:48:18.959388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26483 11:48:18.993639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26485 11:48:18.994294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26486 11:48:19.029090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26487 11:48:19.029559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26489 11:48:19.063930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26491 11:48:19.064557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26492 11:48:19.098299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26494 11:48:19.098919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26495 11:48:19.133253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26496 11:48:19.133694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26498 11:48:19.168241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26499 11:48:19.168665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26501 11:48:19.203510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26502 11:48:19.203939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26504 11:48:19.238282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26505 11:48:19.238756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26507 11:48:19.273710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26508 11:48:19.274129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26510 11:48:19.308282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26512 11:48:19.308748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26513 11:48:19.342951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26514 11:48:19.343393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26516 11:48:19.378603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26518 11:48:19.379168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26519 11:48:19.413096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26520 11:48:19.413510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26522 11:48:19.447854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26524 11:48:19.448319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26525 11:48:19.482792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26526 11:48:19.483255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26528 11:48:19.517341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26529 11:48:19.517825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26531 11:48:19.552934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26532 11:48:19.553386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26534 11:48:19.587401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26536 11:48:19.587949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26537 11:48:19.621696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26538 11:48:19.622158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26540 11:48:19.657630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26541 11:48:19.658120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26543 11:48:19.694048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26545 11:48:19.694655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26546 11:48:19.729236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26547 11:48:19.729690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26549 11:48:19.763578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26551 11:48:19.764157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26552 11:48:19.797936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26554 11:48:19.798561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26555 11:48:19.831897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26556 11:48:19.832393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26558 11:48:19.866584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26560 11:48:19.867160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26561 11:48:19.900311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26563 11:48:19.900868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26564 11:48:19.934069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26565 11:48:19.934548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26567 11:48:19.968078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26569 11:48:19.968644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26570 11:48:20.002136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26571 11:48:20.002545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26573 11:48:20.037491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26574 11:48:20.037956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26576 11:48:20.071491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26577 11:48:20.071942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26579 11:48:20.105574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26580 11:48:20.106005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26582 11:48:20.139253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26583 11:48:20.139671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26585 11:48:20.173523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26586 11:48:20.173950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26588 11:48:20.207655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26590 11:48:20.208283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26591 11:48:20.241565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26592 11:48:20.242037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26594 11:48:20.275657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26596 11:48:20.276315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26597 11:48:20.309132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26598 11:48:20.309549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26600 11:48:20.342343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26601 11:48:20.342789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26603 11:48:20.376340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26605 11:48:20.376904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26606 11:48:20.410067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26607 11:48:20.410534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26609 11:48:20.443761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26611 11:48:20.444363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26612 11:48:20.478114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26613 11:48:20.478581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26615 11:48:20.512080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26616 11:48:20.512559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26618 11:48:20.545683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26620 11:48:20.546310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26621 11:48:20.579647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26623 11:48:20.580235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26624 11:48:20.613794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26626 11:48:20.614251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26627 11:48:20.647909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26628 11:48:20.648321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26630 11:48:20.682286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26631 11:48:20.682675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26633 11:48:20.716472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26635 11:48:20.716894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26636 11:48:20.750804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26638 11:48:20.751252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26639 11:48:20.785559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26640 11:48:20.786039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26642 11:48:20.821239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26643 11:48:20.821703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26645 11:48:20.855653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26646 11:48:20.856102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26648 11:48:20.906669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26649 11:48:20.907151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26651 11:48:20.964525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26653 11:48:20.964993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26654 11:48:20.999706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26655 11:48:21.000133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26657 11:48:21.034602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26659 11:48:21.035080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26660 11:48:21.069150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26662 11:48:21.069622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26663 11:48:21.103438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26665 11:48:21.103894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26666 11:48:21.137340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26667 11:48:21.137793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26669 11:48:21.172024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26670 11:48:21.172451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26672 11:48:21.206257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26674 11:48:21.206715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26675 11:48:21.240543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26677 11:48:21.240998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26678 11:48:21.274721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26680 11:48:21.275178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26681 11:48:21.309551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26683 11:48:21.310203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26684 11:48:21.345499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26686 11:48:21.346161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26687 11:48:21.380570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26689 11:48:21.381415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26690 11:48:21.417638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26691 11:48:21.418159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26693 11:48:21.453776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26695 11:48:21.454339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26696 11:48:21.488625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26698 11:48:21.489637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26699 11:48:21.523906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26700 11:48:21.524357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26702 11:48:21.559449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26703 11:48:21.559882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26705 11:48:21.605343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26706 11:48:21.605676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26708 11:48:21.641344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26710 11:48:21.641722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26711 11:48:21.676247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26713 11:48:21.676662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26714 11:48:21.710835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26715 11:48:21.711300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26717 11:48:21.745739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26719 11:48:21.746423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26720 11:48:21.780166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26721 11:48:21.780620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26723 11:48:21.814372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26725 11:48:21.814963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26726 11:48:21.848838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26727 11:48:21.849296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26729 11:48:21.883887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26730 11:48:21.884324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26732 11:48:21.919005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26733 11:48:21.919475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26735 11:48:21.953854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26736 11:48:21.954394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26738 11:48:21.989078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26739 11:48:21.989542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26741 11:48:22.023048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26742 11:48:22.023469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26744 11:48:22.057304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26745 11:48:22.057686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26747 11:48:22.091980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26748 11:48:22.092409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26750 11:48:22.127714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26752 11:48:22.128176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26753 11:48:22.162476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26754 11:48:22.162939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26756 11:48:22.197161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26757 11:48:22.197616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26759 11:48:22.231015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26760 11:48:22.231469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26762 11:48:22.265304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26763 11:48:22.265750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26765 11:48:22.300249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26767 11:48:22.300797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26768 11:48:22.334327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26769 11:48:22.334769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26771 11:48:22.368933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26773 11:48:22.369523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26774 11:48:22.402381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26775 11:48:22.402788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26777 11:48:22.436653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26779 11:48:22.437103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26780 11:48:22.471672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26782 11:48:22.472125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26783 11:48:22.506450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26784 11:48:22.506938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26786 11:48:22.540906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26787 11:48:22.541417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26789 11:48:22.577036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26791 11:48:22.577619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26792 11:48:22.610389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26793 11:48:22.610841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26795 11:48:22.645395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26796 11:48:22.645810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26798 11:48:22.680979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26799 11:48:22.681377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26801 11:48:22.715939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26802 11:48:22.716363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26804 11:48:22.751429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26806 11:48:22.751892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26807 11:48:22.786116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26808 11:48:22.786543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26810 11:48:22.820079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26812 11:48:22.820557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26813 11:48:22.854256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26815 11:48:22.854711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26816 11:48:22.887958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26818 11:48:22.888426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26819 11:48:22.922585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26820 11:48:22.923009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26822 11:48:22.957843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26824 11:48:22.958399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26825 11:48:22.993315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26827 11:48:22.993888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26828 11:48:23.029284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26830 11:48:23.029857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26831 11:48:23.064071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26832 11:48:23.064486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26834 11:48:23.098984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26835 11:48:23.099383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26837 11:48:23.133954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26838 11:48:23.134405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26840 11:48:23.169058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26841 11:48:23.169526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26843 11:48:23.202855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26844 11:48:23.203300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26846 11:48:23.237492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26847 11:48:23.237947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26849 11:48:23.271744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26850 11:48:23.272221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26852 11:48:23.307339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26854 11:48:23.307885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26855 11:48:23.341585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26856 11:48:23.342058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26858 11:48:23.376297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26860 11:48:23.376854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26861 11:48:23.411518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26863 11:48:23.412065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26864 11:48:23.445584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26865 11:48:23.446056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26867 11:48:23.480554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26869 11:48:23.481135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26870 11:48:23.514387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26871 11:48:23.514840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26873 11:48:23.549798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26875 11:48:23.550355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26876 11:48:23.585295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26877 11:48:23.585751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26879 11:48:23.620145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26880 11:48:23.620690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26882 11:48:23.655363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26884 11:48:23.655937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26885 11:48:23.689507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26886 11:48:23.689969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26888 11:48:23.723409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26889 11:48:23.723865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26891 11:48:23.757954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26892 11:48:23.758401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26894 11:48:23.793323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26895 11:48:23.793778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26897 11:48:23.827910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26898 11:48:23.828364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26900 11:48:23.863440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26902 11:48:23.863916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26903 11:48:23.898024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26904 11:48:23.898438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26906 11:48:23.933710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26907 11:48:23.934124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26909 11:48:23.968613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26911 11:48:23.969068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26912 11:48:24.003523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26914 11:48:24.004085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26915 11:48:24.038105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26916 11:48:24.038539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26918 11:48:24.073311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26919 11:48:24.073748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26921 11:48:24.107749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26922 11:48:24.108152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26924 11:48:24.142342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26926 11:48:24.142786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26927 11:48:24.176886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26928 11:48:24.177315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26930 11:48:24.211165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26931 11:48:24.211564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26933 11:48:24.245720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
26935 11:48:24.246257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26936 11:48:24.279778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
26937 11:48:24.280249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
26939 11:48:24.314560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
26940 11:48:24.315000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
26942 11:48:24.350374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
26944 11:48:24.351140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
26945 11:48:24.385098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
26946 11:48:24.385551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
26948 11:48:24.419118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
26949 11:48:24.419594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
26951 11:48:24.453947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
26952 11:48:24.454432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
26954 11:48:24.488801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
26956 11:48:24.489424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
26957 11:48:24.523950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
26959 11:48:24.524599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
26960 11:48:24.558531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
26961 11:48:24.559009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
26963 11:48:24.593483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
26964 11:48:24.594037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
26966 11:48:24.628931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
26967 11:48:24.629349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
26969 11:48:24.664492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
26971 11:48:24.664956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
26972 11:48:24.698673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
26974 11:48:24.699131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
26975 11:48:24.733146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
26976 11:48:24.733576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
26978 11:48:24.767527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
26980 11:48:24.767995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
26981 11:48:24.802789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
26982 11:48:24.803206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
26984 11:48:24.837833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
26985 11:48:24.838249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
26987 11:48:24.872644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
26989 11:48:24.873211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
26990 11:48:24.907313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
26991 11:48:24.907772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
26993 11:48:24.941050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
26994 11:48:24.941516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
26996 11:48:24.975474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
26998 11:48:24.976032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
26999 11:48:25.009145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
27000 11:48:25.009628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
27002 11:48:25.043930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
27003 11:48:25.044408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
27005 11:48:25.078574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
27007 11:48:25.079209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
27008 11:48:25.112507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
27010 11:48:25.113146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
27011 11:48:25.146955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
27012 11:48:25.147405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
27014 11:48:25.181788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
27015 11:48:25.182273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
27017 11:48:25.217513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
27018 11:48:25.217973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
27020 11:48:25.253219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
27022 11:48:25.253875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
27023 11:48:25.287434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
27025 11:48:25.288004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
27026 11:48:25.321933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
27027 11:48:25.322352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
27029 11:48:25.357020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
27031 11:48:25.357481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
27032 11:48:25.391881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
27034 11:48:25.392338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
27035 11:48:25.426319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
27037 11:48:25.426899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
27038 11:48:25.461726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
27039 11:48:25.462169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
27041 11:48:25.496868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
27042 11:48:25.497330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
27044 11:48:25.531533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
27046 11:48:25.532187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
27047 11:48:25.566510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
27048 11:48:25.566969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
27050 11:48:25.601685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
27051 11:48:25.602151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
27053 11:48:25.637068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
27054 11:48:25.637505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
27056 11:48:25.670920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
27058 11:48:25.671472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
27059 11:48:25.705353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
27061 11:48:25.705932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
27062 11:48:25.739409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
27064 11:48:25.740157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
27065 11:48:25.774093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
27067 11:48:25.774731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
27068 11:48:25.808103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
27069 11:48:25.808582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
27071 11:48:25.842772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
27073 11:48:25.843406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
27074 11:48:25.877482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
27076 11:48:25.878137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
27077 11:48:25.913050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
27078 11:48:25.913514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
27080 11:48:25.947574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
27081 11:48:25.948044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
27083 11:48:25.982660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
27084 11:48:25.983111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
27086 11:48:26.045819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
27087 11:48:26.046244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
27089 11:48:26.093537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
27090 11:48:26.093975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
27092 11:48:26.129327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
27093 11:48:26.129754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
27095 11:48:26.164936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
27096 11:48:26.165353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
27098 11:48:26.200558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
27100 11:48:26.201180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
27101 11:48:26.236110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
27102 11:48:26.236583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
27104 11:48:26.271546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
27105 11:48:26.272021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
27107 11:48:26.306980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
27109 11:48:26.307550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
27110 11:48:26.342855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
27111 11:48:26.343278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
27113 11:48:26.378547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
27114 11:48:26.378924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
27116 11:48:26.414720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
27117 11:48:26.415144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
27119 11:48:26.449912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
27120 11:48:26.450305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
27122 11:48:26.486014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
27124 11:48:26.486570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
27125 11:48:26.522283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
27126 11:48:26.522723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
27128 11:48:26.557596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
27129 11:48:26.558041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
27131 11:48:26.593203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
27132 11:48:26.593670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
27134 11:48:26.629295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
27135 11:48:26.629746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
27137 11:48:26.664049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
27138 11:48:26.664461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
27140 11:48:26.698765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
27142 11:48:26.699075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
27143 11:48:26.734387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
27145 11:48:26.735030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
27146 11:48:26.768968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
27147 11:48:26.769482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
27149 11:48:26.807668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
27151 11:48:26.808284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
27152 11:48:26.845735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
27153 11:48:26.846215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
27155 11:48:26.880826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
27156 11:48:26.881319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
27158 11:48:26.915386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
27159 11:48:26.915847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
27161 11:48:26.950736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
27162 11:48:26.951220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
27164 11:48:26.985740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
27165 11:48:26.986154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
27167 11:48:27.021375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
27169 11:48:27.021842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
27170 11:48:27.056912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
27171 11:48:27.057327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
27173 11:48:27.093768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
27174 11:48:27.094187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
27176 11:48:27.126436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
27177 11:48:27.126917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
27179 11:48:27.161659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27180 11:48:27.162078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27182 11:48:27.197028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27184 11:48:27.197508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27185 11:48:27.231828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27186 11:48:27.232249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27188 11:48:27.267260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27189 11:48:27.267736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27191 11:48:27.302612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27192 11:48:27.303109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27194 11:48:27.337830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27196 11:48:27.338399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27197 11:48:27.373317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27198 11:48:27.373758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27200 11:48:27.408122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27201 11:48:27.408565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27203 11:48:27.443014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27204 11:48:27.443448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27206 11:48:27.477947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27207 11:48:27.478343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27209 11:48:27.513107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27210 11:48:27.513503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27212 11:48:27.549056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27214 11:48:27.549510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27215 11:48:27.583795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27216 11:48:27.584293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27218 11:48:27.620536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27220 11:48:27.621087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27221 11:48:27.655958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27222 11:48:27.656412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27224 11:48:27.693196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27225 11:48:27.693708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27227 11:48:27.730508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27228 11:48:27.730965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27230 11:48:27.768024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27232 11:48:27.768578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27233 11:48:27.805629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27234 11:48:27.806080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27236 11:48:27.842608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27237 11:48:27.843062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27239 11:48:27.879681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27240 11:48:27.880151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27242 11:48:27.917572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27243 11:48:27.918047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27245 11:48:27.958393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27246 11:48:27.958821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27248 11:48:28.000870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27249 11:48:28.001288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27251 11:48:28.034696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27252 11:48:28.035187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27254 11:48:28.069312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27256 11:48:28.069888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27257 11:48:28.103796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27259 11:48:28.104355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27260 11:48:28.138098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27261 11:48:28.138564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27263 11:48:28.173375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27264 11:48:28.173828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27266 11:48:28.208537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27268 11:48:28.209119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27269 11:48:28.243308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27270 11:48:28.243774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27272 11:48:28.277770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27273 11:48:28.278242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27275 11:48:28.312642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27277 11:48:28.313226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27278 11:48:28.347919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27279 11:48:28.348410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27281 11:48:28.383675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27282 11:48:28.384130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27284 11:48:28.419542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27286 11:48:28.420108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27287 11:48:28.455474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27288 11:48:28.455944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27290 11:48:28.490694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27291 11:48:28.491174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27293 11:48:28.526009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27295 11:48:28.526596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27296 11:48:28.561325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27297 11:48:28.561784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27299 11:48:28.596153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27300 11:48:28.596612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27302 11:48:28.631587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27304 11:48:28.632169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27305 11:48:28.666312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27307 11:48:28.666858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27308 11:48:28.701612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27309 11:48:28.702027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27311 11:48:28.736463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27313 11:48:28.736916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27314 11:48:28.771663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27315 11:48:28.772074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27317 11:48:28.806607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27319 11:48:28.807063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27320 11:48:28.841696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27321 11:48:28.842125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27323 11:48:28.876780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27324 11:48:28.877194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27326 11:48:28.911885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27327 11:48:28.912247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27329 11:48:28.946489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27331 11:48:28.947071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27332 11:48:28.981547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27333 11:48:28.982009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27335 11:48:29.016234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27337 11:48:29.016790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27338 11:48:29.051068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27340 11:48:29.051608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27341 11:48:29.086386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27342 11:48:29.086856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27344 11:48:29.121725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27345 11:48:29.122178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27347 11:48:29.156593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27349 11:48:29.157151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27350 11:48:29.190896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27352 11:48:29.191460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27353 11:48:29.225835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27354 11:48:29.226281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27356 11:48:29.261002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27357 11:48:29.261460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27359 11:48:29.295335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27361 11:48:29.295890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27362 11:48:29.330099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27363 11:48:29.330521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27365 11:48:29.365226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27366 11:48:29.365644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27368 11:48:29.400259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27370 11:48:29.400726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27371 11:48:29.435827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27373 11:48:29.436304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27374 11:48:29.471400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27375 11:48:29.471788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27377 11:48:29.506469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27378 11:48:29.506950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27380 11:48:29.541749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27381 11:48:29.542219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27383 11:48:29.577394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27384 11:48:29.577870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27386 11:48:29.612624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27388 11:48:29.613192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27389 11:48:29.660274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27391 11:48:29.660735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27392 11:48:29.694942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27393 11:48:29.695434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27395 11:48:29.729841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27397 11:48:29.730405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27398 11:48:29.765283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27400 11:48:29.765910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27401 11:48:29.799303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27403 11:48:29.799909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27404 11:48:29.833737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27405 11:48:29.834197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27407 11:48:29.867932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27408 11:48:29.868376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27410 11:48:29.902727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27411 11:48:29.903131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27413 11:48:29.937384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27414 11:48:29.937781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27416 11:48:29.970865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27418 11:48:29.971407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27419 11:48:30.004545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27421 11:48:30.005156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27422 11:48:30.040132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27424 11:48:30.040698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27425 11:48:30.074241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27427 11:48:30.074722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27428 11:48:30.109253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27430 11:48:30.109750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27431 11:48:30.143795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27432 11:48:30.144219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27434 11:48:30.178855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27435 11:48:30.179336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27437 11:48:30.214436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27439 11:48:30.215032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27440 11:48:30.249365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27441 11:48:30.249779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27443 11:48:30.285025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27444 11:48:30.285467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27446 11:48:30.319191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27448 11:48:30.319715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27449 11:48:30.353997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27451 11:48:30.354559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27452 11:48:30.389245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27454 11:48:30.389725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27455 11:48:30.424297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27457 11:48:30.424867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27458 11:48:30.458736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27460 11:48:30.459197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27461 11:48:30.493370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27462 11:48:30.493803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27464 11:48:30.528140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27465 11:48:30.528613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27467 11:48:30.563059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27469 11:48:30.563609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27470 11:48:30.597910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27471 11:48:30.598379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27473 11:48:30.633400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27474 11:48:30.633880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27476 11:48:30.668919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27477 11:48:30.669398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27479 11:48:30.703787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27480 11:48:30.704271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27482 11:48:30.738870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27483 11:48:30.739289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27485 11:48:30.775857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27487 11:48:30.776331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27488 11:48:30.811490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27489 11:48:30.811966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27491 11:48:30.846353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27493 11:48:30.846830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27494 11:48:30.881600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27495 11:48:30.882093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27497 11:48:30.917466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27498 11:48:30.917944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27500 11:48:30.953941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27502 11:48:30.954514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27503 11:48:30.991968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27504 11:48:30.992416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27506 11:48:31.029205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27507 11:48:31.029684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27509 11:48:31.063741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27510 11:48:31.064166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27512 11:48:31.098896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27514 11:48:31.099546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27515 11:48:31.158418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27517 11:48:31.158822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27518 11:48:31.195610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27519 11:48:31.195988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27521 11:48:31.231551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27523 11:48:31.232145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27524 11:48:31.269057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27525 11:48:31.269492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27527 11:48:31.304264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27528 11:48:31.304681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27530 11:48:31.341418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27531 11:48:31.341997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27533 11:48:31.378791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27534 11:48:31.379357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27536 11:48:31.415523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27537 11:48:31.415953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27539 11:48:31.452205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27541 11:48:31.452577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27542 11:48:31.487898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27544 11:48:31.488501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27545 11:48:31.523324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27547 11:48:31.523794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27548 11:48:31.559234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27550 11:48:31.559708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27551 11:48:31.597456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27553 11:48:31.597969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27554 11:48:31.632030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27555 11:48:31.632489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27557 11:48:31.666960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27558 11:48:31.667373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27560 11:48:31.701451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27561 11:48:31.701858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27563 11:48:31.735586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27564 11:48:31.736026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27566 11:48:31.770066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27567 11:48:31.770532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27569 11:48:31.806413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27570 11:48:31.806897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27572 11:48:31.843728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27573 11:48:31.844240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27575 11:48:31.882210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27576 11:48:31.882655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27578 11:48:31.921000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27579 11:48:31.921393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27581 11:48:31.957996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27582 11:48:31.958356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27584 11:48:31.993214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27586 11:48:31.993683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27587 11:48:32.029498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27589 11:48:32.029962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27590 11:48:32.063854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27591 11:48:32.064302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27593 11:48:32.098674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27594 11:48:32.099169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27596 11:48:32.133239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27597 11:48:32.133669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27599 11:48:32.167718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27600 11:48:32.168137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27602 11:48:32.202672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27604 11:48:32.203238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27605 11:48:32.237281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27607 11:48:32.237854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27608 11:48:32.270801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27610 11:48:32.271436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27611 11:48:32.304884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27612 11:48:32.305329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27614 11:48:32.339511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27616 11:48:32.340060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27617 11:48:32.373719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27618 11:48:32.374131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27620 11:48:32.409154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27621 11:48:32.409563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27623 11:48:32.444137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27625 11:48:32.444716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27626 11:48:32.478762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27627 11:48:32.479211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27629 11:48:32.514139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27631 11:48:32.514760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27632 11:48:32.549221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27633 11:48:32.549696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27635 11:48:32.583676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27636 11:48:32.584123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27638 11:48:32.618317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27639 11:48:32.618775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27641 11:48:32.653003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27643 11:48:32.653555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27644 11:48:32.687116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27645 11:48:32.687544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27647 11:48:32.721962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27648 11:48:32.722393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27650 11:48:32.757263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27651 11:48:32.757691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27653 11:48:32.792143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27654 11:48:32.792580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27656 11:48:32.826775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27657 11:48:32.827227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27659 11:48:32.861789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27661 11:48:32.862329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27662 11:48:32.896004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27664 11:48:32.896557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27665 11:48:32.929841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27666 11:48:32.930253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27668 11:48:32.965805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27670 11:48:32.966256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27671 11:48:33.000010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27672 11:48:33.000452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27674 11:48:33.034629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27675 11:48:33.035061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27677 11:48:33.069982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27679 11:48:33.070618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27680 11:48:33.105023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27681 11:48:33.105456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27683 11:48:33.138883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27684 11:48:33.139330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27686 11:48:33.174143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27688 11:48:33.174701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27689 11:48:33.208521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27691 11:48:33.209135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27692 11:48:33.243261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27694 11:48:33.243826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27695 11:48:33.277715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27697 11:48:33.278273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27698 11:48:33.312164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27700 11:48:33.312701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27701 11:48:33.345923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27702 11:48:33.346353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27704 11:48:33.380329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27706 11:48:33.380800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27707 11:48:33.414322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27708 11:48:33.414750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27710 11:48:33.449497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27711 11:48:33.449949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27713 11:48:33.483944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27714 11:48:33.484386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27716 11:48:33.517711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27717 11:48:33.518158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27719 11:48:33.552149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27720 11:48:33.552550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27722 11:48:33.586614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27723 11:48:33.587032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27725 11:48:33.621967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27727 11:48:33.622557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27728 11:48:33.655346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27729 11:48:33.655824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27731 11:48:33.690384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27732 11:48:33.690804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27734 11:48:33.725462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27736 11:48:33.726025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27737 11:48:33.759946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27739 11:48:33.760495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27740 11:48:33.794524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27741 11:48:33.794998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27743 11:48:33.829697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27745 11:48:33.830249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27746 11:48:33.865045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27748 11:48:33.865605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27749 11:48:33.899358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27750 11:48:33.899807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27752 11:48:33.934199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27753 11:48:33.934644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27755 11:48:33.969497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27756 11:48:33.969953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27758 11:48:34.005121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27759 11:48:34.005577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27761 11:48:34.040075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27762 11:48:34.040496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27764 11:48:34.074894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27765 11:48:34.075361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27767 11:48:34.109590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27768 11:48:34.110070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27770 11:48:34.144355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27772 11:48:34.144926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27773 11:48:34.179390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27775 11:48:34.179860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27776 11:48:34.214225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27778 11:48:34.214870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27779 11:48:34.249080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27780 11:48:34.249556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27782 11:48:34.283508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27784 11:48:34.284068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27785 11:48:34.317411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27786 11:48:34.317882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27788 11:48:34.352136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27790 11:48:34.352682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27791 11:48:34.386479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27792 11:48:34.386888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27794 11:48:34.420848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27795 11:48:34.421253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27797 11:48:34.454922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27799 11:48:34.455353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27800 11:48:34.489174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27802 11:48:34.489615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27803 11:48:34.522822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27804 11:48:34.523254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27806 11:48:34.557431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27808 11:48:34.557903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27809 11:48:34.591573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27811 11:48:34.592118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27812 11:48:34.626509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27813 11:48:34.626968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27815 11:48:34.661278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27817 11:48:34.661945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27818 11:48:34.695614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27820 11:48:34.696253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27821 11:48:34.730473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27822 11:48:34.730932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27824 11:48:34.765084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27825 11:48:34.765570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27827 11:48:34.799746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27829 11:48:34.800394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27830 11:48:34.833833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27831 11:48:34.834281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27833 11:48:34.868024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27835 11:48:34.868615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27836 11:48:34.902294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27838 11:48:34.902849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27839 11:48:34.937118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27841 11:48:34.937689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27842 11:48:34.971401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27843 11:48:34.971902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27845 11:48:35.005955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27846 11:48:35.006405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27848 11:48:35.041106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27850 11:48:35.041560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27851 11:48:35.076050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27853 11:48:35.076657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27854 11:48:35.109577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27855 11:48:35.110070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27857 11:48:35.143402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27859 11:48:35.143876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27860 11:48:35.177915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27861 11:48:35.178321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27863 11:48:35.212058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27865 11:48:35.212492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27866 11:48:35.246375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27867 11:48:35.246778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27869 11:48:35.290319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27871 11:48:35.290903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27872 11:48:35.324938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27874 11:48:35.325568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27875 11:48:35.359423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27877 11:48:35.359895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27878 11:48:35.393432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27879 11:48:35.393911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27881 11:48:35.427650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27882 11:48:35.428086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27884 11:48:35.462676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27885 11:48:35.463151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27887 11:48:35.496970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27888 11:48:35.497405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27890 11:48:35.531477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27892 11:48:35.532058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27893 11:48:35.565720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27895 11:48:35.566313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27896 11:48:35.599564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27898 11:48:35.600205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27899 11:48:35.632948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27900 11:48:35.633439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27902 11:48:35.667750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27903 11:48:35.668240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27905 11:48:35.701633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27906 11:48:35.702118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27908 11:48:35.735577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27910 11:48:35.736199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27911 11:48:35.770038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27912 11:48:35.770529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27914 11:48:35.804538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27916 11:48:35.805119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27917 11:48:35.839297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27919 11:48:35.839762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27920 11:48:35.873515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27921 11:48:35.873961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27923 11:48:35.907692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27925 11:48:35.908154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27926 11:48:35.941535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27927 11:48:35.941989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27929 11:48:35.975704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27930 11:48:35.976149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27932 11:48:36.009717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27933 11:48:36.010144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
27935 11:48:36.043376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
27937 11:48:36.043842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
27938 11:48:36.077568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
27940 11:48:36.078033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
27941 11:48:36.111567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
27943 11:48:36.112192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
27944 11:48:36.145117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
27946 11:48:36.145681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
27947 11:48:36.178820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
27949 11:48:36.179405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
27950 11:48:36.211602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
27951 11:48:36.212085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
27953 11:48:36.250172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
27955 11:48:36.250761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
27956 11:48:36.302344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
27958 11:48:36.302778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
27959 11:48:36.335961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
27960 11:48:36.336405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
27962 11:48:36.369680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
27963 11:48:36.370108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
27965 11:48:36.404127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
27966 11:48:36.404582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
27968 11:48:36.438165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
27970 11:48:36.438707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
27971 11:48:36.472143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
27972 11:48:36.472625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
27974 11:48:36.506396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
27975 11:48:36.506831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
27977 11:48:36.540957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
27978 11:48:36.541364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
27980 11:48:36.575897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
27981 11:48:36.576329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
27983 11:48:36.610780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
27984 11:48:36.611188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
27986 11:48:36.645526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
27988 11:48:36.645971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
27989 11:48:36.679693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
27991 11:48:36.680141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
27992 11:48:36.714696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
27993 11:48:36.715172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
27995 11:48:36.749061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
27996 11:48:36.749507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
27998 11:48:36.782811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
27999 11:48:36.783347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
28001 11:48:36.817799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
28003 11:48:36.818368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
28004 11:48:36.851881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
28005 11:48:36.852379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
28007 11:48:36.885712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
28009 11:48:36.886269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
28010 11:48:36.919909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
28011 11:48:36.920354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
28013 11:48:36.954871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
28015 11:48:36.955360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
28016 11:48:36.988471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
28018 11:48:36.988837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
28019 11:48:37.023924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
28020 11:48:37.024314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
28022 11:48:37.058330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
28023 11:48:37.058779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
28025 11:48:37.093409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
28026 11:48:37.093905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
28028 11:48:37.128267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
28030 11:48:37.128817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
28031 11:48:37.162784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
28033 11:48:37.163233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
28034 11:48:37.197151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
28035 11:48:37.197567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
28037 11:48:37.231043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
28038 11:48:37.231480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
28040 11:48:37.265554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
28042 11:48:37.266009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
28043 11:48:37.299601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
28044 11:48:37.300097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
28046 11:48:37.333051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
28047 11:48:37.333485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
28049 11:48:37.366860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
28050 11:48:37.367289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
28052 11:48:37.401198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
28053 11:48:37.401632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
28055 11:48:37.435441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
28056 11:48:37.435879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
28058 11:48:37.470062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
28060 11:48:37.470506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
28061 11:48:37.504789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
28062 11:48:37.505259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
28064 11:48:37.539641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
28066 11:48:37.540250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
28067 11:48:37.573947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
28069 11:48:37.574504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
28070 11:48:37.607867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
28071 11:48:37.608335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
28073 11:48:37.641709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
28075 11:48:37.642268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
28076 11:48:37.675808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
28078 11:48:37.676283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
28079 11:48:37.709965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
28081 11:48:37.710429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
28082 11:48:37.744437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
28084 11:48:37.744900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
28085 11:48:37.779100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
28087 11:48:37.779659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
28088 11:48:37.813475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
28089 11:48:37.813954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
28091 11:48:37.848248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
28093 11:48:37.848804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
28094 11:48:37.883404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
28096 11:48:37.883871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
28097 11:48:37.917504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
28098 11:48:37.917990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
28100 11:48:37.952087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
28101 11:48:37.952512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
28103 11:48:37.986621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
28104 11:48:37.987064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
28106 11:48:38.020828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
28107 11:48:38.021263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
28109 11:48:38.056223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
28110 11:48:38.056645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
28112 11:48:38.090240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
28113 11:48:38.090651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
28115 11:48:38.124542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
28117 11:48:38.124988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
28118 11:48:38.158394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
28120 11:48:38.158940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
28121 11:48:38.191942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
28122 11:48:38.192397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
28124 11:48:38.225671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
28125 11:48:38.226090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
28127 11:48:38.259302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
28129 11:48:38.259866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
28130 11:48:38.293147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
28132 11:48:38.293613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
28133 11:48:38.326842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
28135 11:48:38.327303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
28136 11:48:38.361966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
28138 11:48:38.362423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
28139 11:48:38.396470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
28141 11:48:38.397142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
28142 11:48:38.431266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
28144 11:48:38.431909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
28145 11:48:38.465114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
28147 11:48:38.465688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
28148 11:48:38.499417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
28149 11:48:38.499895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
28151 11:48:38.533542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
28152 11:48:38.534017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
28154 11:48:38.567492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
28155 11:48:38.567980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
28157 11:48:38.602316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
28159 11:48:38.602895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
28160 11:48:38.637066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
28161 11:48:38.637504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
28163 11:48:38.671113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
28165 11:48:38.671575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
28166 11:48:38.705162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
28167 11:48:38.705599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
28169 11:48:38.738425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
28170 11:48:38.738896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
28172 11:48:38.773430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
28174 11:48:38.774079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
28175 11:48:38.806643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
28177 11:48:38.807276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
28178 11:48:38.839943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28179 11:48:38.840432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28181 11:48:38.873628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28182 11:48:38.874115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28184 11:48:38.908620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28186 11:48:38.909166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28187 11:48:38.942596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28188 11:48:38.943047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28190 11:48:38.977519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28191 11:48:38.977992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28193 11:48:39.011868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28194 11:48:39.012417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28196 11:48:39.046282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28198 11:48:39.046890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28199 11:48:39.080930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28201 11:48:39.081379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28202 11:48:39.115139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28203 11:48:39.115639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28205 11:48:39.150219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28207 11:48:39.150672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28208 11:48:39.184832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28209 11:48:39.185275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28211 11:48:39.218631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28213 11:48:39.219202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28214 11:48:39.253586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28216 11:48:39.254060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28217 11:48:39.287232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28218 11:48:39.287669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28220 11:48:39.321565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28221 11:48:39.322057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28223 11:48:39.355836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28225 11:48:39.356475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28226 11:48:39.390312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28228 11:48:39.390942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28229 11:48:39.424500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28231 11:48:39.424952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28232 11:48:39.458243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28233 11:48:39.458679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28235 11:48:39.492334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28237 11:48:39.492795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28238 11:48:39.525933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28239 11:48:39.526430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28241 11:48:39.559940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28242 11:48:39.560438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28244 11:48:39.595117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28245 11:48:39.595612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28247 11:48:39.629575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28249 11:48:39.630225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28250 11:48:39.663365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28251 11:48:39.663820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28253 11:48:39.697329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28254 11:48:39.697810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28256 11:48:39.731058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28257 11:48:39.731540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28259 11:48:39.765181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28260 11:48:39.765590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28262 11:48:39.799002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28264 11:48:39.799449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28265 11:48:39.833320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28266 11:48:39.833746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28268 11:48:39.867458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28269 11:48:39.867889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28271 11:48:39.901415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28272 11:48:39.901858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28274 11:48:39.935323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28275 11:48:39.935762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28277 11:48:39.969268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28278 11:48:39.969701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28280 11:48:40.002943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28282 11:48:40.003507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28283 11:48:40.036936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28285 11:48:40.037400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28286 11:48:40.070359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28288 11:48:40.070914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28289 11:48:40.104419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28291 11:48:40.105005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28292 11:48:40.138887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28294 11:48:40.139527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28295 11:48:40.173578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28297 11:48:40.174158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28298 11:48:40.207602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28299 11:48:40.208083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28301 11:48:40.242166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28302 11:48:40.242623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28304 11:48:40.275927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28305 11:48:40.276421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28307 11:48:40.309775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28308 11:48:40.310242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28310 11:48:40.344282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28312 11:48:40.344752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28313 11:48:40.378294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28315 11:48:40.378750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28316 11:48:40.412120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28317 11:48:40.412539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28319 11:48:40.446423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28321 11:48:40.447011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28322 11:48:40.480424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28324 11:48:40.481066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28325 11:48:40.514125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28327 11:48:40.514685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28328 11:48:40.547803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28329 11:48:40.548303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28331 11:48:40.581911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28333 11:48:40.582345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28334 11:48:40.616211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28336 11:48:40.616676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28337 11:48:40.650207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28339 11:48:40.650837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28340 11:48:40.684868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28341 11:48:40.685359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28343 11:48:40.718567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28345 11:48:40.719193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28346 11:48:40.752178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28348 11:48:40.752755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28349 11:48:40.785666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28350 11:48:40.786142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28352 11:48:40.819574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28353 11:48:40.820063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28355 11:48:40.853877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28357 11:48:40.854329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28358 11:48:40.888033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28359 11:48:40.888470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28361 11:48:40.922050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28362 11:48:40.922481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28364 11:48:40.957306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28366 11:48:40.957759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28367 11:48:40.990928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28368 11:48:40.991360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28370 11:48:41.024696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28372 11:48:41.025290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28373 11:48:41.059870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28375 11:48:41.060476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28376 11:48:41.094166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28378 11:48:41.094729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28379 11:48:41.128273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28380 11:48:41.128730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28382 11:48:41.163076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28383 11:48:41.163493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28385 11:48:41.196953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28386 11:48:41.197379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28388 11:48:41.231370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28390 11:48:41.231848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28391 11:48:41.266022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28393 11:48:41.266613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28394 11:48:41.299809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28396 11:48:41.300401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28397 11:48:41.334273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28398 11:48:41.334750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28400 11:48:41.378197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28401 11:48:41.378659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28403 11:48:41.424537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28405 11:48:41.425118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28406 11:48:41.459170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28407 11:48:41.459666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28409 11:48:41.493957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28410 11:48:41.494432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28412 11:48:41.530309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28413 11:48:41.530761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28415 11:48:41.565617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28416 11:48:41.566093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28418 11:48:41.600004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28419 11:48:41.600463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28421 11:48:41.634279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28423 11:48:41.634721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28424 11:48:41.668862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28425 11:48:41.669355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28427 11:48:41.703553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28428 11:48:41.703946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28430 11:48:41.737602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28432 11:48:41.738066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28433 11:48:41.771720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28435 11:48:41.772470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28436 11:48:41.807623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28437 11:48:41.808045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28439 11:48:41.843465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28441 11:48:41.843935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28442 11:48:41.881089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28444 11:48:41.881542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28445 11:48:41.917540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28446 11:48:41.917963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28448 11:48:41.952800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28449 11:48:41.953220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28451 11:48:41.987679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28452 11:48:41.988082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28454 11:48:42.022674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28456 11:48:42.023150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28457 11:48:42.057142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28458 11:48:42.057629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28460 11:48:42.093598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28461 11:48:42.094024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28463 11:48:42.129365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28465 11:48:42.130020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28466 11:48:42.181822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28467 11:48:42.182297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28469 11:48:42.213450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28471 11:48:42.214039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28472 11:48:42.245070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28473 11:48:42.245524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28475 11:48:42.275920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28476 11:48:42.276408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28478 11:48:42.308521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28480 11:48:42.309091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28481 11:48:42.340774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28482 11:48:42.341227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28484 11:48:42.378061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28486 11:48:42.378525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28487 11:48:42.411941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28488 11:48:42.412455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28490 11:48:42.443539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28491 11:48:42.443984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28493 11:48:42.478438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28494 11:48:42.478932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28496 11:48:42.510862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28498 11:48:42.511502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28499 11:48:42.542804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28501 11:48:42.543263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28502 11:48:42.573906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28503 11:48:42.574351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28505 11:48:42.605304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28506 11:48:42.605802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28508 11:48:42.636088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28510 11:48:42.636557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28511 11:48:42.669430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28513 11:48:42.670072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28514 11:48:42.701143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28515 11:48:42.701537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28517 11:48:42.731602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28518 11:48:42.732008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28520 11:48:42.762444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28521 11:48:42.762875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28523 11:48:42.793774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28525 11:48:42.794251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28526 11:48:42.824892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28527 11:48:42.825380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28529 11:48:42.855501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28530 11:48:42.856002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28532 11:48:42.887612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28534 11:48:42.888225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28535 11:48:42.918818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28537 11:48:42.919466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28538 11:48:42.950039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28539 11:48:42.950524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28541 11:48:42.981685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28542 11:48:42.982165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28544 11:48:43.013578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28546 11:48:43.014155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28547 11:48:43.045634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28548 11:48:43.046042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28550 11:48:43.077830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28551 11:48:43.078281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28553 11:48:43.109825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28555 11:48:43.110431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28556 11:48:43.142561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28558 11:48:43.143156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28559 11:48:43.174176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28561 11:48:43.174736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28562 11:48:43.206006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28564 11:48:43.206634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28565 11:48:43.237671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28566 11:48:43.238148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28568 11:48:43.269603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28570 11:48:43.270229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28571 11:48:43.301359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28572 11:48:43.301826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28574 11:48:43.333691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28576 11:48:43.334258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28577 11:48:43.365357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28578 11:48:43.365814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28580 11:48:43.397459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28582 11:48:43.398020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28583 11:48:43.429057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28585 11:48:43.429596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28586 11:48:43.460707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28587 11:48:43.461165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28589 11:48:43.493314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28590 11:48:43.493774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28592 11:48:43.524736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28593 11:48:43.525196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28595 11:48:43.556260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28597 11:48:43.556837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28598 11:48:43.588403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28600 11:48:43.591060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28601 11:48:43.620017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28602 11:48:43.620517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28604 11:48:43.652281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28606 11:48:43.652736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28607 11:48:43.683371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28608 11:48:43.683794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28610 11:48:43.714549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28611 11:48:43.715013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28613 11:48:43.745798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28614 11:48:43.746261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28616 11:48:43.777493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28618 11:48:43.778055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28619 11:48:43.808316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28621 11:48:43.808767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28622 11:48:43.840499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28624 11:48:43.841092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28625 11:48:43.872562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28627 11:48:43.873142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28628 11:48:43.905274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28630 11:48:43.905865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28631 11:48:43.937188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28632 11:48:43.937662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28634 11:48:43.970242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28635 11:48:43.970719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28637 11:48:44.003744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28639 11:48:44.004330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28640 11:48:44.035606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28641 11:48:44.036025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28643 11:48:44.066665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28644 11:48:44.067117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28646 11:48:44.097709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28647 11:48:44.098152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28649 11:48:44.129225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28650 11:48:44.129681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28652 11:48:44.162139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28653 11:48:44.162565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28655 11:48:44.193488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28656 11:48:44.193940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28658 11:48:44.225539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28660 11:48:44.226179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28661 11:48:44.262448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28662 11:48:44.262925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28664 11:48:44.298423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28665 11:48:44.298902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28667 11:48:44.330374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28668 11:48:44.330864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28670 11:48:44.362316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28671 11:48:44.362807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28673 11:48:44.393835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28674 11:48:44.394314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28676 11:48:44.425392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28677 11:48:44.425874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28679 11:48:44.457025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28681 11:48:44.457577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28682 11:48:44.487877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28684 11:48:44.488328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28685 11:48:44.520235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28686 11:48:44.520678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28688 11:48:44.552383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28690 11:48:44.552950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28691 11:48:44.584792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28692 11:48:44.585276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28694 11:48:44.622169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28695 11:48:44.622654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28697 11:48:44.657736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28699 11:48:44.658477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28700 11:48:44.691149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28701 11:48:44.691582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28703 11:48:44.722867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28704 11:48:44.723299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28706 11:48:44.754324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28707 11:48:44.754822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28709 11:48:44.786204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28710 11:48:44.786680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28712 11:48:44.818106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28713 11:48:44.818571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28715 11:48:44.849492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28716 11:48:44.849961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28718 11:48:44.880951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28719 11:48:44.881365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28721 11:48:44.912806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28723 11:48:44.913232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28724 11:48:44.945257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28725 11:48:44.945679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28727 11:48:44.977432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28729 11:48:44.977873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28730 11:48:45.009075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28731 11:48:45.009474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28733 11:48:45.041289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28734 11:48:45.041677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28736 11:48:45.075505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28737 11:48:45.075984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28739 11:48:45.107925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28741 11:48:45.108386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28742 11:48:45.140552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28744 11:48:45.140975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28745 11:48:45.171930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28746 11:48:45.172365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28748 11:48:45.203725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28750 11:48:45.204169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28751 11:48:45.234736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28753 11:48:45.235282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28754 11:48:45.265614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28756 11:48:45.266145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28757 11:48:45.296649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28758 11:48:45.297103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28760 11:48:45.327591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28761 11:48:45.328006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28763 11:48:45.358300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28765 11:48:45.358820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28766 11:48:45.390124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28767 11:48:45.390592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28769 11:48:45.420605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28770 11:48:45.421019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28772 11:48:45.451090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28774 11:48:45.451600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28775 11:48:45.481596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28777 11:48:45.482106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28778 11:48:45.512236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28779 11:48:45.512651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28781 11:48:45.543357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28783 11:48:45.543777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28784 11:48:45.574866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28785 11:48:45.575205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28787 11:48:45.606063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28788 11:48:45.606472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28790 11:48:45.639111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28791 11:48:45.639597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28793 11:48:45.670606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28794 11:48:45.671081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28796 11:48:45.701836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28797 11:48:45.702277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28799 11:48:45.732909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28801 11:48:45.733429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28802 11:48:45.763898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28804 11:48:45.764432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28805 11:48:45.795491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28806 11:48:45.795935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28808 11:48:45.826455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28810 11:48:45.827006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28811 11:48:45.857570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28812 11:48:45.858001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28814 11:48:45.888720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28815 11:48:45.889164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28817 11:48:45.919571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28819 11:48:45.920105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28820 11:48:45.951056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28821 11:48:45.951468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28823 11:48:45.982191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28825 11:48:45.982732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28826 11:48:46.013252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28827 11:48:46.013688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28829 11:48:46.043855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28830 11:48:46.044267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28832 11:48:46.074834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28833 11:48:46.075288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28835 11:48:46.105566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28836 11:48:46.106019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28838 11:48:46.136456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28840 11:48:46.137002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28841 11:48:46.167464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28843 11:48:46.167994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28844 11:48:46.198974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28845 11:48:46.199481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28847 11:48:46.230021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28848 11:48:46.230420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28850 11:48:46.261992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28852 11:48:46.262448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28853 11:48:46.293265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28854 11:48:46.293749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28856 11:48:46.324628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28858 11:48:46.325178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28859 11:48:46.357692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28860 11:48:46.358174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28862 11:48:46.391725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28863 11:48:46.392160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28865 11:48:46.422826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28866 11:48:46.423401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28868 11:48:46.457146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28869 11:48:46.457599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28871 11:48:46.531873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28873 11:48:46.532447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28874 11:48:46.573309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28876 11:48:46.573794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28877 11:48:46.611239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28878 11:48:46.611651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28880 11:48:46.647792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28882 11:48:46.648196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28883 11:48:46.683628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28884 11:48:46.684070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28886 11:48:46.718054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28887 11:48:46.718476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28889 11:48:46.751978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28890 11:48:46.752404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28892 11:48:46.786104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28893 11:48:46.786525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28895 11:48:46.820469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28897 11:48:46.820937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28898 11:48:46.854341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28899 11:48:46.854791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28901 11:48:46.888932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28902 11:48:46.889392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28904 11:48:46.923046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28905 11:48:46.923391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28907 11:48:46.955335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28908 11:48:46.955766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28910 11:48:46.986737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28912 11:48:46.987237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28913 11:48:47.017904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28915 11:48:47.018415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28916 11:48:47.049706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28917 11:48:47.050095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28919 11:48:47.082921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28920 11:48:47.083368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28922 11:48:47.113912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28923 11:48:47.114337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28925 11:48:47.145437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28926 11:48:47.145853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28928 11:48:47.177256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28930 11:48:47.177778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28931 11:48:47.209270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28933 11:48:47.209816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28934 11:48:47.240778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
28936 11:48:47.241264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
28937 11:48:47.271570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
28938 11:48:47.271977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
28940 11:48:47.303197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
28941 11:48:47.303602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
28943 11:48:47.334144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
28944 11:48:47.334522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
28946 11:48:47.365524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
28948 11:48:47.365949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
28949 11:48:47.397076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
28951 11:48:47.397500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
28952 11:48:47.427943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
28953 11:48:47.428343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
28955 11:48:47.459428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
28956 11:48:47.459827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
28958 11:48:47.491667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
28960 11:48:47.492267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
28961 11:48:47.522525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
28962 11:48:47.523004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
28964 11:48:47.555758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
28965 11:48:47.556306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
28967 11:48:47.590368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
28968 11:48:47.590855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
28970 11:48:47.625107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
28971 11:48:47.625608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
28973 11:48:47.659947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
28974 11:48:47.660471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
28976 11:48:47.694467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
28978 11:48:47.694893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
28979 11:48:47.729008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
28981 11:48:47.729492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
28982 11:48:47.763731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
28983 11:48:47.764169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
28985 11:48:47.795641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
28987 11:48:47.796356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
28988 11:48:47.830018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
28989 11:48:47.830441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
28991 11:48:47.861552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
28993 11:48:47.861987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
28994 11:48:47.892890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
28996 11:48:47.893296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
28997 11:48:47.923638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
28999 11:48:47.924233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
29000 11:48:47.956906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
29001 11:48:47.957396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
29003 11:48:47.989496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
29004 11:48:47.989963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
29006 11:48:48.020016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
29007 11:48:48.020433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
29009 11:48:48.050334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
29010 11:48:48.050744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
29012 11:48:48.083836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
29014 11:48:48.084386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
29015 11:48:48.114666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
29017 11:48:48.115111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
29018 11:48:48.145426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
29020 11:48:48.145963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
29021 11:48:48.176079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
29023 11:48:48.176533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
29024 11:48:48.209111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
29025 11:48:48.209599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
29027 11:48:48.240587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
29029 11:48:48.241107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
29030 11:48:48.271718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
29031 11:48:48.272128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
29033 11:48:48.302290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
29034 11:48:48.302694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
29036 11:48:48.333477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
29037 11:48:48.333920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
29039 11:48:48.363887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
29040 11:48:48.364302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
29042 11:48:48.394435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
29043 11:48:48.394788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
29045 11:48:48.425409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
29047 11:48:48.425980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
29048 11:48:48.456628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
29049 11:48:48.457070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
29051 11:48:48.488940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
29052 11:48:48.489397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
29054 11:48:48.520978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
29055 11:48:48.521394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
29057 11:48:48.551640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
29058 11:48:48.552037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
29060 11:48:48.582157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
29061 11:48:48.582630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
29063 11:48:48.613499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
29065 11:48:48.613960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
29066 11:48:48.645072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
29068 11:48:48.645506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
29069 11:48:48.676921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
29071 11:48:48.677361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
29072 11:48:48.708071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
29074 11:48:48.708624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
29075 11:48:48.738705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
29076 11:48:48.739110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
29078 11:48:48.769490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
29080 11:48:48.770004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
29081 11:48:48.799682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
29082 11:48:48.800175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
29084 11:48:48.831200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
29086 11:48:48.831733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
29087 11:48:48.861416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
29089 11:48:48.861910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
29090 11:48:48.891776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
29091 11:48:48.892153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
29093 11:48:48.923043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
29095 11:48:48.923509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
29096 11:48:48.953939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
29097 11:48:48.954332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
29099 11:48:48.984139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
29101 11:48:48.984614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
29102 11:48:49.015199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
29103 11:48:49.015620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
29105 11:48:49.045820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
29106 11:48:49.046204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
29108 11:48:49.077711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
29110 11:48:49.078211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
29111 11:48:49.109104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
29112 11:48:49.109491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
29114 11:48:49.139566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
29116 11:48:49.140036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
29117 11:48:49.170052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
29118 11:48:49.170452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
29120 11:48:49.200800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
29121 11:48:49.201193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
29123 11:48:49.231298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
29125 11:48:49.231868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
29126 11:48:49.263655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
29127 11:48:49.264133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
29129 11:48:49.294937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
29130 11:48:49.295364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
29132 11:48:49.326433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
29133 11:48:49.326790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
29135 11:48:49.357482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
29137 11:48:49.358039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
29138 11:48:49.388815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
29139 11:48:49.389255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
29141 11:48:49.419611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
29143 11:48:49.420139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
29144 11:48:49.450649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
29146 11:48:49.451272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
29147 11:48:49.481715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
29149 11:48:49.482266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
29150 11:48:49.513550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
29152 11:48:49.514103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
29153 11:48:49.545144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
29155 11:48:49.545689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
29156 11:48:49.575990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
29157 11:48:49.576443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
29159 11:48:49.606554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
29161 11:48:49.607077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
29162 11:48:49.637635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
29164 11:48:49.638283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
29165 11:48:49.670567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
29166 11:48:49.671081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
29168 11:48:49.703690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
29169 11:48:49.704174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
29171 11:48:49.735502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
29172 11:48:49.735989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
29174 11:48:49.767342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
29176 11:48:49.767972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
29177 11:48:49.798772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
29178 11:48:49.799246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29180 11:48:49.829902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29181 11:48:49.830379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29183 11:48:49.861406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29184 11:48:49.861880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29186 11:48:49.892732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29187 11:48:49.893148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29189 11:48:49.924063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29191 11:48:49.924607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29192 11:48:49.955193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29193 11:48:49.955661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29195 11:48:49.986101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29196 11:48:49.986565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29198 11:48:50.016959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29199 11:48:50.017440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29201 11:48:50.047827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29203 11:48:50.048329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29204 11:48:50.079556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29206 11:48:50.080081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29207 11:48:50.110053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29209 11:48:50.110590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29210 11:48:50.141212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29212 11:48:50.141667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29213 11:48:50.172231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29215 11:48:50.172680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29216 11:48:50.204003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29217 11:48:50.204436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29219 11:48:50.235580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29221 11:48:50.236024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29222 11:48:50.267701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29223 11:48:50.268135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29225 11:48:50.301200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29227 11:48:50.301659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29228 11:48:50.333194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29229 11:48:50.333634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29231 11:48:50.363710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29232 11:48:50.364156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29234 11:48:50.394362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29235 11:48:50.394798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29237 11:48:50.425233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29238 11:48:50.425607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29240 11:48:50.455595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29242 11:48:50.456140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29243 11:48:50.486190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29244 11:48:50.486642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29246 11:48:50.517716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29248 11:48:50.518262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29249 11:48:50.549000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29251 11:48:50.549535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29252 11:48:50.579650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29253 11:48:50.580081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29255 11:48:50.610459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29257 11:48:50.610998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29258 11:48:50.641521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29260 11:48:50.642067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29261 11:48:50.673033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29263 11:48:50.673566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29264 11:48:50.703509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29265 11:48:50.703983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29267 11:48:50.733687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29268 11:48:50.734109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29270 11:48:50.764876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29272 11:48:50.765361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29273 11:48:50.795627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29275 11:48:50.796037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29276 11:48:50.826296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29278 11:48:50.826859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29279 11:48:50.858917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29281 11:48:50.859489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29282 11:48:50.890075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29284 11:48:50.890624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29285 11:48:50.921672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29286 11:48:50.922132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29288 11:48:50.953682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29289 11:48:50.954139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29291 11:48:50.985112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29292 11:48:50.985562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29294 11:48:51.016851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29295 11:48:51.017332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29297 11:48:51.049016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29298 11:48:51.049480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29300 11:48:51.081284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29302 11:48:51.081840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29303 11:48:51.111908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29304 11:48:51.112335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29306 11:48:51.142215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29307 11:48:51.142560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29309 11:48:51.172960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29310 11:48:51.173320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29312 11:48:51.203406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29314 11:48:51.203789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29315 11:48:51.233727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29316 11:48:51.234088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29318 11:48:51.266124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29319 11:48:51.266562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29321 11:48:51.297632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29322 11:48:51.298063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29324 11:48:51.329431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29325 11:48:51.329813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29327 11:48:51.361604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29329 11:48:51.362071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29330 11:48:51.391974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29332 11:48:51.392350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29333 11:48:51.422396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29334 11:48:51.422841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29336 11:48:51.453419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29337 11:48:51.453829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29339 11:48:51.483840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29341 11:48:51.484460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29342 11:48:51.515145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29343 11:48:51.515564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29345 11:48:51.546147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29347 11:48:51.546766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29348 11:48:51.578131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29349 11:48:51.578604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29351 11:48:51.621724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29353 11:48:51.622276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29354 11:48:51.664452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29356 11:48:51.665051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29357 11:48:51.697148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29358 11:48:51.697626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29360 11:48:51.729490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29362 11:48:51.730073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29363 11:48:51.761721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29365 11:48:51.762261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29366 11:48:51.793588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29367 11:48:51.794066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29369 11:48:51.825381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29370 11:48:51.825824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29372 11:48:51.857097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29374 11:48:51.857657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29375 11:48:51.888083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29376 11:48:51.888519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29378 11:48:51.919923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29380 11:48:51.920484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29381 11:48:51.951305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29382 11:48:51.951764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29384 11:48:51.982715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29386 11:48:51.983282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29387 11:48:52.014098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29388 11:48:52.014540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29390 11:48:52.045706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29391 11:48:52.046170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29393 11:48:52.077059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29395 11:48:52.077581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29396 11:48:52.109032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29398 11:48:52.109531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29399 11:48:52.140198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29400 11:48:52.140600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29402 11:48:52.171024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29403 11:48:52.171357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29405 11:48:52.201776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29406 11:48:52.202189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29408 11:48:52.233303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29409 11:48:52.233673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29411 11:48:52.263572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29412 11:48:52.263902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29414 11:48:52.300106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29416 11:48:52.300572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29417 11:48:52.333186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29418 11:48:52.333595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29420 11:48:52.365270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29421 11:48:52.365669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29423 11:48:52.396152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29424 11:48:52.396553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29426 11:48:52.427186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29427 11:48:52.427591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29429 11:48:52.458188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29431 11:48:52.458680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29432 11:48:52.489242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29433 11:48:52.489639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29435 11:48:52.520171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29437 11:48:52.520712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29438 11:48:52.551290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29439 11:48:52.551689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29441 11:48:52.583327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29443 11:48:52.583865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29444 11:48:52.614450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29446 11:48:52.614967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29447 11:48:52.645593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29448 11:48:52.646002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29450 11:48:52.676961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29451 11:48:52.677375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29453 11:48:52.709107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29455 11:48:52.709614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29456 11:48:52.739960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29457 11:48:52.740421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29459 11:48:52.771264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29460 11:48:52.771685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29462 11:48:52.803801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29463 11:48:52.804286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29465 11:48:52.835309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29467 11:48:52.835911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29468 11:48:52.866969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29469 11:48:52.867371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29471 11:48:52.898255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29472 11:48:52.898669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29474 11:48:52.929555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29476 11:48:52.930123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29477 11:48:52.961419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29479 11:48:52.961877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29480 11:48:52.993475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29481 11:48:52.993930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29483 11:48:53.024893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29485 11:48:53.025421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29486 11:48:53.056511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29488 11:48:53.057070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29489 11:48:53.088140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29491 11:48:53.088690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29492 11:48:53.120114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29494 11:48:53.120659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29495 11:48:53.151523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29497 11:48:53.152092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29498 11:48:53.182615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29499 11:48:53.183020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29501 11:48:53.214611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29503 11:48:53.215046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29504 11:48:53.246404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29506 11:48:53.246942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29507 11:48:53.278045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29508 11:48:53.278494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29510 11:48:53.309507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29512 11:48:53.310137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29513 11:48:53.341143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29515 11:48:53.341711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29516 11:48:53.373939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29517 11:48:53.374394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29519 11:48:53.407274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29520 11:48:53.407702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29522 11:48:53.441377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29524 11:48:53.441931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29525 11:48:53.472661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29527 11:48:53.473204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29528 11:48:53.503798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29530 11:48:53.504425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29531 11:48:53.535067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29533 11:48:53.535609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29534 11:48:53.566712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29536 11:48:53.567370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29537 11:48:53.597436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29539 11:48:53.598022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29540 11:48:53.628031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29542 11:48:53.628630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29543 11:48:53.658151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29544 11:48:53.658566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29546 11:48:53.688761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29548 11:48:53.689261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29549 11:48:53.719841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29551 11:48:53.720339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29552 11:48:53.750298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29554 11:48:53.750774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29555 11:48:53.780873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29556 11:48:53.781257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29558 11:48:53.811529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29559 11:48:53.811943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29561 11:48:53.841868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29563 11:48:53.842339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29564 11:48:53.874942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29565 11:48:53.875400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29567 11:48:53.908013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29569 11:48:53.908528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29570 11:48:53.939156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29572 11:48:53.939631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29573 11:48:53.969361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29575 11:48:53.969824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29576 11:48:53.999942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29577 11:48:54.000371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29579 11:48:54.031145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29581 11:48:54.031775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29582 11:48:54.061630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29584 11:48:54.062263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29585 11:48:54.092903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29586 11:48:54.093354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29588 11:48:54.123706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29590 11:48:54.124314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29591 11:48:54.154561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29593 11:48:54.155136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29594 11:48:54.185063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29595 11:48:54.185517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29597 11:48:54.215733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29598 11:48:54.216152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29600 11:48:54.246008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29601 11:48:54.246432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29603 11:48:54.276793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29604 11:48:54.277220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29606 11:48:54.307243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29607 11:48:54.307649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29609 11:48:54.338056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29610 11:48:54.338460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29612 11:48:54.369424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29614 11:48:54.370027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29615 11:48:54.400116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29617 11:48:54.400511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29618 11:48:54.430387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29620 11:48:54.430770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29621 11:48:54.460943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29623 11:48:54.461307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29624 11:48:54.493144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29626 11:48:54.493794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29627 11:48:54.524416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29629 11:48:54.525041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29630 11:48:54.555260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29631 11:48:54.555659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29633 11:48:54.585776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29634 11:48:54.586246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29636 11:48:54.616698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29637 11:48:54.617159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29639 11:48:54.647733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29640 11:48:54.648197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29642 11:48:54.678276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29643 11:48:54.678668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29645 11:48:54.709233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29646 11:48:54.709630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29648 11:48:54.740052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29650 11:48:54.740532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29651 11:48:54.770635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29652 11:48:54.771036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29654 11:48:54.801463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29655 11:48:54.801876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29657 11:48:54.832664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29659 11:48:54.833108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29660 11:48:54.864917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29662 11:48:54.865506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29663 11:48:54.895229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29665 11:48:54.895724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29666 11:48:54.925706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29668 11:48:54.926239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29669 11:48:54.956013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29670 11:48:54.956465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29672 11:48:54.986361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29673 11:48:54.986807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29675 11:48:55.017289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29676 11:48:55.017681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29678 11:48:55.048391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29680 11:48:55.048837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29681 11:48:55.079224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29682 11:48:55.079690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29684 11:48:55.110596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29686 11:48:55.111205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29687 11:48:55.141331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29688 11:48:55.141799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29690 11:48:55.171994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29692 11:48:55.172612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29693 11:48:55.202693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29694 11:48:55.203137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29696 11:48:55.235545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29698 11:48:55.235999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29699 11:48:55.267540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29700 11:48:55.267966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29702 11:48:55.299373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29704 11:48:55.299923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29705 11:48:55.331303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29706 11:48:55.331730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29708 11:48:55.362981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29709 11:48:55.363454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29711 11:48:55.395345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29713 11:48:55.395921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29714 11:48:55.426338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29716 11:48:55.426892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29717 11:48:55.457512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29718 11:48:55.457936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29720 11:48:55.488613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29721 11:48:55.489037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29723 11:48:55.519810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29724 11:48:55.520206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29726 11:48:55.551662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29727 11:48:55.552096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29729 11:48:55.583239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29730 11:48:55.583660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29732 11:48:55.614433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29734 11:48:55.614862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29735 11:48:55.645466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29737 11:48:55.646024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29738 11:48:55.675951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29739 11:48:55.676360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29741 11:48:55.708191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29742 11:48:55.708657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29744 11:48:55.738646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29745 11:48:55.739120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29747 11:48:55.770449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29748 11:48:55.770913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29750 11:48:55.801385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29751 11:48:55.801870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29753 11:48:55.831614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29755 11:48:55.832253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29756 11:48:55.862556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29757 11:48:55.863012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29759 11:48:55.893722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29760 11:48:55.894172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29762 11:48:55.924466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29764 11:48:55.925014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29765 11:48:55.955875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29766 11:48:55.956335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29768 11:48:55.987084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29770 11:48:55.987632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29771 11:48:56.017961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29773 11:48:56.018530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29774 11:48:56.049212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29776 11:48:56.049704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29777 11:48:56.079956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29779 11:48:56.080533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29780 11:48:56.113585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29782 11:48:56.114156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29783 11:48:56.144105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29784 11:48:56.144508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29786 11:48:56.175237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29788 11:48:56.175735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29789 11:48:56.205917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29791 11:48:56.206407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29792 11:48:56.236987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29793 11:48:56.237382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29795 11:48:56.267899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29796 11:48:56.268290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29798 11:48:56.298605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29799 11:48:56.298995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29801 11:48:56.329712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29802 11:48:56.330124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29804 11:48:56.361435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29805 11:48:56.361846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29807 11:48:56.392064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29809 11:48:56.392475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29810 11:48:56.423339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29811 11:48:56.423723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29813 11:48:56.456236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29815 11:48:56.456819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29816 11:48:56.487435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29817 11:48:56.487878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29819 11:48:56.518162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29821 11:48:56.518717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29822 11:48:56.549804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29824 11:48:56.550297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29825 11:48:56.583339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29827 11:48:56.583872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29828 11:48:56.615774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29829 11:48:56.616158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29831 11:48:56.649193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29833 11:48:56.649788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29834 11:48:56.682167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29836 11:48:56.682682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29837 11:48:56.714808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29839 11:48:56.715259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29840 11:48:56.776799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29842 11:48:56.777173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29843 11:48:56.808212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29845 11:48:56.808576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29846 11:48:56.839422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29847 11:48:56.839781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29849 11:48:56.871936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29851 11:48:56.872356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29852 11:48:56.903444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29853 11:48:56.903896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29855 11:48:56.936834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29856 11:48:56.937320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29858 11:48:56.970212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29859 11:48:56.970685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29861 11:48:57.003385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29863 11:48:57.003957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29864 11:48:57.034529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29865 11:48:57.034942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29867 11:48:57.066006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29869 11:48:57.066582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29870 11:48:57.097390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29872 11:48:57.097927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29873 11:48:57.128605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29875 11:48:57.129091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29876 11:48:57.162247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29878 11:48:57.162786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29879 11:48:57.194000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29881 11:48:57.194537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29882 11:48:57.225317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29883 11:48:57.225687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29885 11:48:57.255929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29886 11:48:57.256331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29888 11:48:57.286541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29890 11:48:57.287021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29891 11:48:57.317699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29893 11:48:57.318176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29894 11:48:57.348365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29896 11:48:57.348846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29897 11:48:57.379103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29899 11:48:57.379606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29900 11:48:57.410356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29902 11:48:57.410926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29903 11:48:57.441404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29905 11:48:57.442066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29906 11:48:57.473034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29908 11:48:57.473670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29909 11:48:57.503869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29910 11:48:57.504334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29912 11:48:57.534971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29914 11:48:57.535595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29915 11:48:57.566156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29916 11:48:57.566624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29918 11:48:57.598429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29919 11:48:57.598841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29921 11:48:57.629242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29922 11:48:57.629686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29924 11:48:57.663230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29925 11:48:57.663703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29927 11:48:57.694353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29928 11:48:57.694761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29930 11:48:57.725426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29931 11:48:57.725831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29933 11:48:57.757050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
29935 11:48:57.757539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29936 11:48:57.787985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
29937 11:48:57.788385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
29939 11:48:57.818718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
29941 11:48:57.819226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
29942 11:48:57.849501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
29943 11:48:57.849913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
29945 11:48:57.880837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
29947 11:48:57.881327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
29948 11:48:57.911308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
29950 11:48:57.911829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
29951 11:48:57.941797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
29953 11:48:57.942320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
29954 11:48:57.973228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
29955 11:48:57.973639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
29957 11:48:58.004263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
29958 11:48:58.004667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
29960 11:48:58.034604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
29961 11:48:58.035021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
29963 11:48:58.065462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
29964 11:48:58.065875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
29966 11:48:58.096120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
29968 11:48:58.096620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
29969 11:48:58.126364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
29971 11:48:58.126845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
29972 11:48:58.157984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
29974 11:48:58.158471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
29975 11:48:58.189349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
29977 11:48:58.189855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
29978 11:48:58.219675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
29980 11:48:58.220172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
29981 11:48:58.250235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
29982 11:48:58.250618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
29984 11:48:58.281446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
29986 11:48:58.281917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
29987 11:48:58.312552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
29989 11:48:58.313038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
29990 11:48:58.345163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
29991 11:48:58.345500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
29993 11:48:58.378961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
29994 11:48:58.379408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
29996 11:48:58.414054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
29997 11:48:58.414501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
29999 11:48:58.447134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
30000 11:48:58.447542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
30002 11:48:58.478078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
30003 11:48:58.478551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
30005 11:48:58.509858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
30006 11:48:58.510315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
30008 11:48:58.541051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
30009 11:48:58.541512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
30011 11:48:58.572543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
30013 11:48:58.572981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
30014 11:48:58.604546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
30015 11:48:58.604971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
30017 11:48:58.636110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
30019 11:48:58.636569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
30020 11:48:58.667902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
30022 11:48:58.668529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
30023 11:48:58.699159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
30025 11:48:58.699599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
30026 11:48:58.730088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
30028 11:48:58.730523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
30029 11:48:58.762094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
30031 11:48:58.762705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
30032 11:48:58.793598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
30034 11:48:58.794169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
30035 11:48:58.825106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
30036 11:48:58.825530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
30038 11:48:58.855494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
30039 11:48:58.856003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
30041 11:48:58.889299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
30042 11:48:58.889740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
30044 11:48:58.921785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
30045 11:48:58.922224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
30047 11:48:58.953500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
30049 11:48:58.953970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
30050 11:48:58.985149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
30051 11:48:58.985572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
30053 11:48:59.016906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
30055 11:48:59.017348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
30056 11:48:59.047938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
30057 11:48:59.048382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
30059 11:48:59.078902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
30060 11:48:59.079403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
30062 11:48:59.109832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
30063 11:48:59.110307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
30065 11:48:59.141097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
30066 11:48:59.141575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
30068 11:48:59.172423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
30070 11:48:59.173008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
30071 11:48:59.203912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
30072 11:48:59.204394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
30074 11:48:59.235446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
30076 11:48:59.235880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
30077 11:48:59.266921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
30079 11:48:59.267470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
30080 11:48:59.297861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
30082 11:48:59.298399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
30083 11:48:59.328934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
30085 11:48:59.329459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
30086 11:48:59.359540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
30088 11:48:59.360084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
30089 11:48:59.391257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
30090 11:48:59.391726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
30092 11:48:59.426512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
30093 11:48:59.426987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
30095 11:48:59.457343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
30096 11:48:59.457805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
30098 11:48:59.488325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
30100 11:48:59.488862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
30101 11:48:59.520189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
30103 11:48:59.520738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
30104 11:48:59.551764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
30106 11:48:59.552294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
30107 11:48:59.583171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
30109 11:48:59.583601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
30110 11:48:59.615647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
30111 11:48:59.616060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
30113 11:48:59.646922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
30115 11:48:59.647366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
30116 11:48:59.678184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
30118 11:48:59.678617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
30119 11:48:59.709447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
30120 11:48:59.709858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
30122 11:48:59.739947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
30123 11:48:59.740372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
30125 11:48:59.771876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
30127 11:48:59.772329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
30128 11:48:59.802907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
30129 11:48:59.803322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
30131 11:48:59.833960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
30132 11:48:59.834361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
30134 11:48:59.865666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
30136 11:48:59.866119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
30137 11:48:59.897016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
30138 11:48:59.897413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
30140 11:48:59.939356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
30141 11:48:59.939801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
30143 11:48:59.970930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
30144 11:48:59.971357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
30146 11:49:00.001796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
30147 11:49:00.002220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
30149 11:49:00.033282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
30150 11:49:00.033677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
30152 11:49:00.064601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
30154 11:49:00.065167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
30155 11:49:00.095764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
30156 11:49:00.096187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
30158 11:49:00.126535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
30160 11:49:00.127115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
30161 11:49:00.157596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
30163 11:49:00.158120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
30164 11:49:00.189587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
30165 11:49:00.189994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
30167 11:49:00.220972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
30169 11:49:00.221459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
30170 11:49:00.251625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
30171 11:49:00.252051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
30173 11:49:00.283014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
30174 11:49:00.283427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
30176 11:49:00.313824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
30178 11:49:00.314220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
30179 11:49:00.353490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30181 11:49:00.353959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30182 11:49:00.385583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30184 11:49:00.386208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30185 11:49:00.416859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30186 11:49:00.417304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30188 11:49:00.449172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30190 11:49:00.449809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30191 11:49:00.479929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30193 11:49:00.480578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30194 11:49:00.510833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30195 11:49:00.511291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30197 11:49:00.542457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30199 11:49:00.543051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30200 11:49:00.574097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30201 11:49:00.574539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30203 11:49:00.605315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30204 11:49:00.605773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30206 11:49:00.637136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30208 11:49:00.637749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30209 11:49:00.668570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30211 11:49:00.669146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30212 11:49:00.699405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30214 11:49:00.699969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30215 11:49:00.730782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30216 11:49:00.731227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30218 11:49:00.762200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30220 11:49:00.762738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30221 11:49:00.794071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30223 11:49:00.794608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30224 11:49:00.825459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30226 11:49:00.825992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30227 11:49:00.857094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30228 11:49:00.857551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30230 11:49:00.889235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30231 11:49:00.889702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30233 11:49:00.923796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30234 11:49:00.924283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30236 11:49:00.955427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30238 11:49:00.955973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30239 11:49:00.986710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30240 11:49:00.987148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30242 11:49:01.018126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30243 11:49:01.018567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30245 11:49:01.050106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30247 11:49:01.050735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30248 11:49:01.081774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30250 11:49:01.082304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30251 11:49:01.113516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30252 11:49:01.113974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30254 11:49:01.144751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30255 11:49:01.145179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30257 11:49:01.175871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30258 11:49:01.176339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30260 11:49:01.208029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30261 11:49:01.208493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30263 11:49:01.239109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30265 11:49:01.239664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30266 11:49:01.270326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30267 11:49:01.270813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30269 11:49:01.301541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30270 11:49:01.301968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30272 11:49:01.332845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30274 11:49:01.333219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30275 11:49:01.366719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30276 11:49:01.367192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30278 11:49:01.399615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30279 11:49:01.400106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30281 11:49:01.431065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30282 11:49:01.431544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30284 11:49:01.462525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30285 11:49:01.463016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30287 11:49:01.494334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30288 11:49:01.494790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30290 11:49:01.525536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30292 11:49:01.526003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30293 11:49:01.557240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30295 11:49:01.557822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30296 11:49:01.569735 <47>[ 303.630498] systemd-journald[109]: Sent WATCHDOG=1 notification.
30297 11:49:01.596368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30298 11:49:01.596918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30300 11:49:01.629208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30301 11:49:01.629785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30303 11:49:01.664505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30305 11:49:01.665193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30306 11:49:01.698949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30307 11:49:01.699368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30309 11:49:01.734081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30310 11:49:01.734500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30312 11:49:01.768953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30314 11:49:01.769313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30315 11:49:01.801269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30316 11:49:01.801682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30318 11:49:01.833719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30320 11:49:01.834303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30321 11:49:01.887750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30322 11:49:01.888251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30324 11:49:01.919415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30325 11:49:01.919888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30327 11:49:01.951111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30328 11:49:01.951513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30330 11:49:01.981952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30331 11:49:01.982436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30333 11:49:02.013550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30334 11:49:02.014031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30336 11:49:02.045162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30337 11:49:02.045617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30339 11:49:02.079662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30340 11:49:02.080127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30342 11:49:02.111761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30344 11:49:02.112357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30345 11:49:02.144188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30346 11:49:02.144630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30348 11:49:02.176897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30350 11:49:02.177359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30351 11:49:02.208073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30352 11:49:02.208509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30354 11:49:02.239557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30355 11:49:02.240028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30357 11:49:02.270461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30358 11:49:02.270904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30360 11:49:02.301528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30361 11:49:02.301985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30363 11:49:02.332831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30365 11:49:02.333289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30366 11:49:02.363073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30367 11:49:02.363488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30369 11:49:02.396020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30370 11:49:02.396476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30372 11:49:02.428715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30373 11:49:02.429161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30375 11:49:02.459723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30376 11:49:02.460156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30378 11:49:02.490297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30380 11:49:02.490757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30381 11:49:02.521453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30382 11:49:02.521976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30384 11:49:02.552677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30385 11:49:02.553157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30387 11:49:02.583606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30389 11:49:02.584222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30390 11:49:02.614236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30391 11:49:02.614677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30393 11:49:02.645302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30395 11:49:02.645892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30396 11:49:02.676967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30397 11:49:02.677451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30399 11:49:02.709421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30400 11:49:02.709896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30402 11:49:02.741058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30404 11:49:02.741657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30405 11:49:02.772059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30407 11:49:02.772632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30408 11:49:02.803557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30410 11:49:02.804192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30411 11:49:02.838740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30412 11:49:02.839191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30414 11:49:02.871630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30415 11:49:02.872119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30417 11:49:02.903821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30418 11:49:02.904314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30420 11:49:02.935579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30421 11:49:02.936073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30423 11:49:02.973045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30425 11:49:02.973697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30426 11:49:03.003263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30427 11:49:03.003736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30429 11:49:03.033701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30430 11:49:03.034171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30432 11:49:03.064358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30434 11:49:03.064923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30435 11:49:03.099282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30437 11:49:03.099742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30438 11:49:03.130823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30439 11:49:03.131308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30441 11:49:03.161530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30442 11:49:03.162029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30444 11:49:03.192043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30445 11:49:03.192553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30447 11:49:03.222554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30448 11:49:03.223035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30450 11:49:03.253137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30451 11:49:03.253622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30453 11:49:03.285101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30455 11:49:03.285550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30456 11:49:03.316557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30458 11:49:03.317182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30459 11:49:03.347321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30460 11:49:03.347794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30462 11:49:03.381341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30463 11:49:03.381820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30465 11:49:03.412876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30467 11:49:03.413432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30468 11:49:03.443615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30470 11:49:03.444217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30471 11:49:03.474557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30472 11:49:03.474999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30474 11:49:03.505583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30476 11:49:03.506130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30477 11:49:03.537444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30479 11:49:03.538010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30480 11:49:03.567984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30481 11:49:03.568460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30483 11:49:03.599971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30484 11:49:03.600423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30486 11:49:03.631668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30487 11:49:03.632155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30489 11:49:03.663325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30491 11:49:03.663957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30492 11:49:03.693342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30493 11:49:03.693680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30495 11:49:03.725119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30497 11:49:03.725588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30498 11:49:03.755825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30500 11:49:03.756296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30501 11:49:03.786535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30502 11:49:03.786968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30504 11:49:03.817461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30505 11:49:03.817894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30507 11:49:03.850369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30509 11:49:03.850837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30510 11:49:03.881861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30511 11:49:03.882296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30513 11:49:03.912979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30515 11:49:03.913557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30516 11:49:03.943567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30517 11:49:03.944048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30519 11:49:03.974480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30520 11:49:03.974965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30522 11:49:04.005481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30524 11:49:04.006058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30525 11:49:04.036035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30526 11:49:04.036552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30528 11:49:04.066719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30529 11:49:04.067215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30531 11:49:04.097469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30532 11:49:04.097965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30534 11:49:04.128945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30535 11:49:04.129403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30537 11:49:04.159787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30538 11:49:04.160269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30540 11:49:04.190550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30541 11:49:04.191016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30543 11:49:04.222100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30544 11:49:04.222571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30546 11:49:04.252763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30547 11:49:04.253235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30549 11:49:04.284391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30551 11:49:04.284856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30552 11:49:04.321885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30554 11:49:04.322340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30555 11:49:04.353102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30556 11:49:04.353529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30558 11:49:04.384088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30559 11:49:04.384416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30561 11:49:04.414758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30562 11:49:04.415170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30564 11:49:04.445564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30565 11:49:04.445945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30567 11:49:04.477243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30568 11:49:04.477596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30570 11:49:04.507990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30572 11:49:04.508457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30573 11:49:04.539247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30575 11:49:04.539702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30576 11:49:04.569772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30578 11:49:04.570267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30579 11:49:04.600095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30580 11:49:04.600492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30582 11:49:04.630781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30583 11:49:04.631185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30585 11:49:04.661501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30587 11:49:04.661983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30588 11:49:04.692034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30589 11:49:04.692423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30591 11:49:04.723092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30592 11:49:04.723520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30594 11:49:04.753917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30595 11:49:04.754375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30597 11:49:04.785086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30598 11:49:04.785482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30600 11:49:04.815989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30601 11:49:04.816426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30603 11:49:04.847110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30605 11:49:04.847666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30606 11:49:04.878193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30608 11:49:04.878681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30609 11:49:04.908392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30611 11:49:04.908811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30612 11:49:04.940073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30613 11:49:04.940499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30615 11:49:04.971534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30616 11:49:04.971882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30618 11:49:05.001535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30620 11:49:05.001953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30621 11:49:05.031847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30623 11:49:05.032243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30624 11:49:05.061997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30625 11:49:05.062397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30627 11:49:05.092189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30629 11:49:05.092686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30630 11:49:05.122969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30631 11:49:05.123396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30633 11:49:05.154083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30634 11:49:05.154497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30636 11:49:05.184936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30638 11:49:05.185494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30639 11:49:05.214791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30640 11:49:05.215246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30642 11:49:05.245248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30643 11:49:05.245698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30645 11:49:05.276053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30646 11:49:05.276519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30648 11:49:05.309185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30650 11:49:05.309744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30651 11:49:05.341725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30652 11:49:05.342305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30654 11:49:05.374778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30655 11:49:05.375254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30657 11:49:05.406117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30659 11:49:05.406653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30660 11:49:05.437912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30661 11:49:05.438341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30663 11:49:05.470619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30665 11:49:05.471184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30666 11:49:05.501561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30667 11:49:05.501991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30669 11:49:05.533552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30670 11:49:05.534043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30672 11:49:05.564931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30674 11:49:05.565471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30675 11:49:05.596104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30677 11:49:05.596638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30678 11:49:05.627884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30680 11:49:05.628354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30681 11:49:05.661308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30682 11:49:05.661693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30684 11:49:05.692125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30686 11:49:05.692602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30687 11:49:05.722896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30688 11:49:05.723294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30690 11:49:05.753576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30692 11:49:05.753995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30693 11:49:05.783822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30695 11:49:05.784178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30696 11:49:05.815644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30698 11:49:05.816155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30699 11:49:05.845939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30701 11:49:05.846406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30702 11:49:05.877195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30704 11:49:05.877761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30705 11:49:05.908256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30707 11:49:05.908821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30708 11:49:05.939938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30709 11:49:05.940380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30711 11:49:05.970167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30713 11:49:05.970634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30714 11:49:06.000733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30716 11:49:06.001207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30717 11:49:06.031238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30719 11:49:06.031625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30720 11:49:06.061778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30722 11:49:06.062250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30723 11:49:06.091917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30725 11:49:06.092484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30726 11:49:06.122010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30727 11:49:06.122460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30729 11:49:06.153532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30731 11:49:06.154094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30732 11:49:06.184129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30733 11:49:06.184553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30735 11:49:06.215257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30737 11:49:06.215703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30738 11:49:06.246946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30739 11:49:06.247370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30741 11:49:06.278688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30743 11:49:06.279231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30744 11:49:06.311421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30746 11:49:06.311956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30747 11:49:06.343640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30749 11:49:06.344100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30750 11:49:06.374361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30751 11:49:06.374712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30753 11:49:06.405288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30755 11:49:06.405698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30756 11:49:06.435306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30757 11:49:06.435743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30759 11:49:06.465732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30760 11:49:06.466149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30762 11:49:06.496106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30763 11:49:06.496502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30765 11:49:06.527398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30767 11:49:06.527929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30768 11:49:06.557811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30769 11:49:06.558245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30771 11:49:06.590199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30772 11:49:06.590659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30774 11:49:06.621453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30776 11:49:06.622175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30777 11:49:06.652950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30779 11:49:06.653692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30780 11:49:06.687753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30782 11:49:06.688238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30783 11:49:06.720154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30785 11:49:06.720700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30786 11:49:06.751569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30788 11:49:06.751969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30789 11:49:06.783113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30790 11:49:06.783555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30792 11:49:06.813693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30794 11:49:06.814321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30795 11:49:06.844831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30797 11:49:06.845444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30798 11:49:06.875756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30799 11:49:06.876256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30801 11:49:06.907076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30802 11:49:06.907522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30804 11:49:06.938536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30806 11:49:06.939163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30807 11:49:06.986149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30808 11:49:06.986561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30810 11:49:07.026161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30811 11:49:07.026579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30813 11:49:07.057345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30814 11:49:07.057675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30816 11:49:07.088328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30818 11:49:07.088893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30819 11:49:07.119921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30821 11:49:07.120387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30822 11:49:07.154323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30823 11:49:07.154791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30825 11:49:07.185310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30826 11:49:07.185776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30828 11:49:07.216187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30830 11:49:07.216730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30831 11:49:07.247305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30833 11:49:07.247879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30834 11:49:07.277711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30836 11:49:07.278245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30837 11:49:07.312987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30838 11:49:07.313467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30840 11:49:07.344497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30842 11:49:07.345050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30843 11:49:07.375696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30844 11:49:07.376161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30846 11:49:07.407443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30847 11:49:07.407920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30849 11:49:07.438168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30850 11:49:07.438619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30852 11:49:07.469160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30853 11:49:07.469604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30855 11:49:07.499574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30857 11:49:07.500099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30858 11:49:07.530368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30859 11:49:07.530785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30861 11:49:07.561782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30863 11:49:07.562306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30864 11:49:07.592221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30866 11:49:07.592739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30867 11:49:07.623406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30868 11:49:07.623854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30870 11:49:07.654081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30871 11:49:07.654554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30873 11:49:07.685418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30875 11:49:07.685983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30876 11:49:07.717300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30877 11:49:07.717782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30879 11:49:07.748951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30880 11:49:07.749386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30882 11:49:07.780008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30883 11:49:07.780496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30885 11:49:07.811110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30886 11:49:07.811575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30888 11:49:07.841945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30890 11:49:07.842682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30891 11:49:07.872462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30893 11:49:07.873031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30894 11:49:07.904139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30896 11:49:07.904685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30897 11:49:07.935453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30898 11:49:07.935931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30900 11:49:07.966788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30902 11:49:07.967351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30903 11:49:07.997516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30904 11:49:07.998000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30906 11:49:08.028984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30907 11:49:08.029411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30909 11:49:08.061045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30911 11:49:08.061491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30912 11:49:08.092124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30913 11:49:08.092536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30915 11:49:08.122934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30916 11:49:08.123401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30918 11:49:08.154550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30919 11:49:08.154956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30921 11:49:08.186598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30922 11:49:08.187001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30924 11:49:08.217304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30925 11:49:08.217688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30927 11:49:08.248446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30929 11:49:08.249022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30930 11:49:08.279449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30932 11:49:08.279982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30933 11:49:08.310197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
30934 11:49:08.310648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30936 11:49:08.341463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
30937 11:49:08.341922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
30939 11:49:08.372565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
30941 11:49:08.373249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
30942 11:49:08.403465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
30943 11:49:08.403894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
30945 11:49:08.434925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
30946 11:49:08.435401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
30948 11:49:08.469167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
30949 11:49:08.469660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
30951 11:49:08.499676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
30952 11:49:08.500146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
30954 11:49:08.529994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
30955 11:49:08.530453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
30957 11:49:08.561518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
30958 11:49:08.561983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
30960 11:49:08.592317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
30962 11:49:08.592909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
30963 11:49:08.623595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
30964 11:49:08.624066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
30966 11:49:08.654548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
30967 11:49:08.655011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
30969 11:49:08.686365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
30970 11:49:08.686820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
30972 11:49:08.717794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
30974 11:49:08.718271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
30975 11:49:08.750023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
30977 11:49:08.750510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
30978 11:49:08.780981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
30980 11:49:08.781321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
30981 11:49:08.811817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
30982 11:49:08.812107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
30984 11:49:08.843501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
30985 11:49:08.843849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
30987 11:49:08.874437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
30988 11:49:08.874752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
30990 11:49:08.906273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
30992 11:49:08.906811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
30993 11:49:08.937455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
30994 11:49:08.937876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
30996 11:49:08.967954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
30997 11:49:08.968370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
30999 11:49:09.001709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
31000 11:49:09.002175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
31002 11:49:09.033454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
31004 11:49:09.033991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
31005 11:49:09.063668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
31006 11:49:09.064074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
31008 11:49:09.094116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
31010 11:49:09.094622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
31011 11:49:09.124356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
31013 11:49:09.124881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
31014 11:49:09.154867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
31015 11:49:09.155229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
31017 11:49:09.185186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
31018 11:49:09.185589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
31020 11:49:09.215266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
31021 11:49:09.215681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
31023 11:49:09.245548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
31024 11:49:09.245976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
31026 11:49:09.275931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
31027 11:49:09.276357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
31029 11:49:09.307509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
31030 11:49:09.307898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
31032 11:49:09.338059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
31034 11:49:09.338525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
31035 11:49:09.368518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
31037 11:49:09.368917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
31038 11:49:09.398443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
31039 11:49:09.398790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
31041 11:49:09.428912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
31043 11:49:09.429314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
31044 11:49:09.458684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
31045 11:49:09.459061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
31047 11:49:09.489396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
31048 11:49:09.489739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
31050 11:49:09.519681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
31051 11:49:09.520081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
31053 11:49:09.550481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
31054 11:49:09.550872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
31056 11:49:09.581011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
31057 11:49:09.581434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
31059 11:49:09.610867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
31061 11:49:09.611365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
31062 11:49:09.641620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
31064 11:49:09.642120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
31065 11:49:09.672061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
31067 11:49:09.672548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
31068 11:49:09.702130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
31070 11:49:09.702607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
31071 11:49:09.733205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
31072 11:49:09.733652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
31074 11:49:09.763466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
31075 11:49:09.763825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
31077 11:49:09.793921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
31079 11:49:09.794372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
31080 11:49:09.825031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
31082 11:49:09.825476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
31083 11:49:09.854989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
31084 11:49:09.855359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
31086 11:49:09.886000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
31088 11:49:09.886505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
31089 11:49:09.916733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
31091 11:49:09.917207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
31092 11:49:09.947419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
31093 11:49:09.947816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
31095 11:49:09.977874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
31097 11:49:09.978371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
31098 11:49:10.008068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
31100 11:49:10.008556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
31101 11:49:10.038433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
31103 11:49:10.038943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
31104 11:49:10.069031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
31106 11:49:10.069505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
31107 11:49:10.098977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
31108 11:49:10.099398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
31110 11:49:10.129797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
31111 11:49:10.130196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
31113 11:49:10.159927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
31114 11:49:10.160266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
31116 11:49:10.190325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
31118 11:49:10.190827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
31119 11:49:10.220897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
31121 11:49:10.221472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
31122 11:49:10.250987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
31124 11:49:10.251557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
31125 11:49:10.282416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
31126 11:49:10.282876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
31128 11:49:10.313197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
31130 11:49:10.313785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
31131 11:49:10.347054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
31132 11:49:10.347536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
31134 11:49:10.378278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
31136 11:49:10.378770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
31137 11:49:10.409399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
31139 11:49:10.409913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
31140 11:49:10.439907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
31142 11:49:10.440515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
31143 11:49:10.470527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
31144 11:49:10.470991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
31146 11:49:10.501320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
31148 11:49:10.501960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
31149 11:49:10.532023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
31151 11:49:10.532657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
31152 11:49:10.562767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
31153 11:49:10.563234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
31155 11:49:10.593333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
31156 11:49:10.593823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
31158 11:49:10.623868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
31160 11:49:10.624491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
31161 11:49:10.666430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
31163 11:49:10.666980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
31164 11:49:10.702615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
31165 11:49:10.703081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
31167 11:49:10.733955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
31168 11:49:10.734440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
31170 11:49:10.764950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
31171 11:49:10.765394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
31173 11:49:10.795968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
31175 11:49:10.796558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
31176 11:49:10.826202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
31178 11:49:10.826547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
31179 11:49:10.856567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31181 11:49:10.857060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31182 11:49:10.888246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31183 11:49:10.888667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31185 11:49:10.920211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31187 11:49:10.920751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31188 11:49:10.951199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31189 11:49:10.951658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31191 11:49:10.982289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31193 11:49:10.982829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31194 11:49:11.013535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31196 11:49:11.014088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31197 11:49:11.044575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31199 11:49:11.045119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31200 11:49:11.075612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31202 11:49:11.076053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31203 11:49:11.106814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31205 11:49:11.107350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31206 11:49:11.137991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31208 11:49:11.138523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31209 11:49:11.169399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31211 11:49:11.169945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31212 11:49:11.200584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31214 11:49:11.201115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31215 11:49:11.231502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31217 11:49:11.232075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31218 11:49:11.266818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31220 11:49:11.267267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31221 11:49:11.298543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31222 11:49:11.298949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31224 11:49:11.329902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31225 11:49:11.330320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31227 11:49:11.361164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31229 11:49:11.361743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31230 11:49:11.391576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31232 11:49:11.392163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31233 11:49:11.422252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31234 11:49:11.422708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31236 11:49:11.453186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31237 11:49:11.453632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31239 11:49:11.483645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31240 11:49:11.484105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31242 11:49:11.514243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31243 11:49:11.514704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31245 11:49:11.546023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31246 11:49:11.546477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31248 11:49:11.576923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31250 11:49:11.577458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31251 11:49:11.611645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31252 11:49:11.612130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31254 11:49:11.643011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31255 11:49:11.643472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31257 11:49:11.673899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31258 11:49:11.674349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31260 11:49:11.705332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31261 11:49:11.705820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31263 11:49:11.737575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31264 11:49:11.738067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31266 11:49:11.769504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31267 11:49:11.769973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31269 11:49:11.801681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31271 11:49:11.802230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31272 11:49:11.833501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31274 11:49:11.833964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31275 11:49:11.864287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31277 11:49:11.864859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31278 11:49:11.896023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31279 11:49:11.896491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31281 11:49:11.927067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31282 11:49:11.927456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31284 11:49:11.960037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31285 11:49:11.960520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31287 11:49:11.991589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31289 11:49:11.992276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31290 11:49:12.023181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31292 11:49:12.023741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31293 11:49:12.053494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31294 11:49:12.053970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31296 11:49:12.083903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31298 11:49:12.084474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31299 11:49:12.135155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31300 11:49:12.135628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31302 11:49:12.165993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31303 11:49:12.166440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31305 11:49:12.197403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31307 11:49:12.197945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31308 11:49:12.228619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31309 11:49:12.229066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31311 11:49:12.259621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31312 11:49:12.260051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31314 11:49:12.290587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31315 11:49:12.291018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31317 11:49:12.322699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31318 11:49:12.323164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31320 11:49:12.353715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31321 11:49:12.354171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31323 11:49:12.385438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31324 11:49:12.385915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31326 11:49:12.416035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31327 11:49:12.416454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31329 11:49:12.446834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31330 11:49:12.447295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31332 11:49:12.477999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31333 11:49:12.478429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31335 11:49:12.509408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31336 11:49:12.509870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31338 11:49:12.540101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31340 11:49:12.540568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31341 11:49:12.571539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31342 11:49:12.571902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31344 11:49:12.602420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31345 11:49:12.602772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31347 11:49:12.633522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31349 11:49:12.633912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31350 11:49:12.664483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31352 11:49:12.665007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31353 11:49:12.695029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31355 11:49:12.695435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31356 11:49:12.725286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31358 11:49:12.725700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31359 11:49:12.756000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31361 11:49:12.756380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31362 11:49:12.786478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31363 11:49:12.786855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31365 11:49:12.817020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31366 11:49:12.817398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31368 11:49:12.847562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31369 11:49:12.847919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31371 11:49:12.880630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31372 11:49:12.881105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31374 11:49:12.911709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31375 11:49:12.912171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31377 11:49:12.942486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31378 11:49:12.942957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31380 11:49:12.973477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31381 11:49:12.973940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31383 11:49:13.003660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31384 11:49:13.004098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31386 11:49:13.034850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31388 11:49:13.035412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31389 11:49:13.066235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31390 11:49:13.066702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31392 11:49:13.098253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31393 11:49:13.098747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31395 11:49:13.129045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31397 11:49:13.129550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31398 11:49:13.159497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31399 11:49:13.159896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31401 11:49:13.189675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31403 11:49:13.190161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31404 11:49:13.219622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31406 11:49:13.220153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31407 11:49:13.249930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31409 11:49:13.250447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31410 11:49:13.279668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31411 11:49:13.280047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31413 11:49:13.310525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31414 11:49:13.310927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31416 11:49:13.341415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31418 11:49:13.342010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31419 11:49:13.371586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31421 11:49:13.372151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31422 11:49:13.401762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31423 11:49:13.402177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31425 11:49:13.432166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31427 11:49:13.432721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31428 11:49:13.463832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31430 11:49:13.464395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31431 11:49:13.494781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31432 11:49:13.495235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31434 11:49:13.526279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31436 11:49:13.526832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31437 11:49:13.557579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31438 11:49:13.558002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31440 11:49:13.588156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31441 11:49:13.588600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31443 11:49:13.619083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31445 11:49:13.619522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31446 11:49:13.649858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31447 11:49:13.650289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31449 11:49:13.681577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31451 11:49:13.682031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31452 11:49:13.712232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31453 11:49:13.712639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31455 11:49:13.743392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31457 11:49:13.743832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31458 11:49:13.773852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31459 11:49:13.774242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31461 11:49:13.804883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31462 11:49:13.805279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31464 11:49:13.835244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31466 11:49:13.835675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31467 11:49:13.866365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31468 11:49:13.866815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31470 11:49:13.898334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31471 11:49:13.898758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31473 11:49:13.936744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31475 11:49:13.937375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31476 11:49:13.967753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31478 11:49:13.968318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31479 11:49:13.997971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31480 11:49:13.998377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31482 11:49:14.028622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31483 11:49:14.029037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31485 11:49:14.058705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31487 11:49:14.059283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31488 11:49:14.088940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31489 11:49:14.089352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31491 11:49:14.119755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31492 11:49:14.120235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31494 11:49:14.153265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31495 11:49:14.153751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31497 11:49:14.183847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31498 11:49:14.184264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31500 11:49:14.215035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31501 11:49:14.215497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31503 11:49:14.245990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31505 11:49:14.246529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31506 11:49:14.276518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31508 11:49:14.276989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31509 11:49:14.307137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31511 11:49:14.307634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31512 11:49:14.337465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31514 11:49:14.337963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31515 11:49:14.367743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31517 11:49:14.368332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31518 11:49:14.397839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31519 11:49:14.398228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31521 11:49:14.428423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31523 11:49:14.429004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31524 11:49:14.458666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31525 11:49:14.459035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31527 11:49:14.490155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31528 11:49:14.490636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31530 11:49:14.521895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31532 11:49:14.522436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31533 11:49:14.553377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31535 11:49:14.553905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31536 11:49:14.583673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31538 11:49:14.584228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31539 11:49:14.613703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31541 11:49:14.614196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31542 11:49:14.644185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31544 11:49:14.644574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31545 11:49:14.674412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31547 11:49:14.674816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31548 11:49:14.704790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31549 11:49:14.705153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31551 11:49:14.735985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31553 11:49:14.736530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31554 11:49:14.765956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31555 11:49:14.766350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31557 11:49:14.796085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31558 11:49:14.796514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31560 11:49:14.826718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31561 11:49:14.827196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31563 11:49:14.857445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31565 11:49:14.857981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31566 11:49:14.889218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31568 11:49:14.889776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31569 11:49:14.919726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31570 11:49:14.920120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31572 11:49:14.950948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31573 11:49:14.951344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31575 11:49:14.981402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31576 11:49:14.981806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31578 11:49:15.012059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31579 11:49:15.012525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31581 11:49:15.042603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31583 11:49:15.043135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31584 11:49:15.073329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31585 11:49:15.073772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31587 11:49:15.104246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31589 11:49:15.104814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31590 11:49:15.134699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31592 11:49:15.135167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31593 11:49:15.165156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31594 11:49:15.165561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31596 11:49:15.195184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31597 11:49:15.195589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31599 11:49:15.225709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31601 11:49:15.226204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31602 11:49:15.255956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31603 11:49:15.256394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31605 11:49:15.288862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31606 11:49:15.289328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31608 11:49:15.320983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31609 11:49:15.321411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31611 11:49:15.353025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31612 11:49:15.353445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31614 11:49:15.384980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31615 11:49:15.385452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31617 11:49:15.415527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31619 11:49:15.416054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31620 11:49:15.446013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31622 11:49:15.446542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31623 11:49:15.476872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31624 11:49:15.477304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31626 11:49:15.507004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31628 11:49:15.507422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31629 11:49:15.538583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31630 11:49:15.538981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31632 11:49:15.569533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31634 11:49:15.569979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31635 11:49:15.600435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31637 11:49:15.600988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31638 11:49:15.630944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31639 11:49:15.631384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31641 11:49:15.661674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31643 11:49:15.662206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31644 11:49:15.691983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31645 11:49:15.692433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31647 11:49:15.723549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31649 11:49:15.724073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31650 11:49:15.755850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31652 11:49:15.756409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31653 11:49:15.786994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31655 11:49:15.787515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31656 11:49:15.817832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31658 11:49:15.818360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31659 11:49:15.848822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31661 11:49:15.849341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31662 11:49:15.879636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31663 11:49:15.880129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31665 11:49:15.909946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31666 11:49:15.910350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31668 11:49:15.940920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31670 11:49:15.941512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31671 11:49:15.971367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31673 11:49:15.971929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31674 11:49:16.001459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31675 11:49:16.001819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31677 11:49:16.031639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31679 11:49:16.032068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31680 11:49:16.062157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31681 11:49:16.062507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31683 11:49:16.092681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31685 11:49:16.093087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31686 11:49:16.124885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31687 11:49:16.125318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31689 11:49:16.154943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31690 11:49:16.155353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31692 11:49:16.185433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31693 11:49:16.185812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31695 11:49:16.215900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31697 11:49:16.216423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31698 11:49:16.246006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31699 11:49:16.246415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31701 11:49:16.277489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31703 11:49:16.277988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31704 11:49:16.307872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31705 11:49:16.308276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31707 11:49:16.338051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31709 11:49:16.338455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31710 11:49:16.368053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31712 11:49:16.368468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31713 11:49:16.398522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31715 11:49:16.399043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31716 11:49:16.429250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31717 11:49:16.429659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31719 11:49:16.459649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31720 11:49:16.460035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31722 11:49:16.490061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31723 11:49:16.490509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31725 11:49:16.521656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31726 11:49:16.522098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31728 11:49:16.552587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31730 11:49:16.553106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31731 11:49:16.583016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31732 11:49:16.583454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31734 11:49:16.615624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31735 11:49:16.616107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31737 11:49:16.648498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31739 11:49:16.648954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31740 11:49:16.681635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31742 11:49:16.682192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31743 11:49:16.715596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31745 11:49:16.716139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31746 11:49:16.747213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31747 11:49:16.747663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31749 11:49:16.778376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31751 11:49:16.778919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31752 11:49:16.809338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31753 11:49:16.809814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31755 11:49:16.840642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31756 11:49:16.841102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31758 11:49:16.872431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31760 11:49:16.872997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31761 11:49:16.903467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31763 11:49:16.904076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31764 11:49:16.934623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31765 11:49:16.935086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31767 11:49:16.966908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31769 11:49:16.967553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31770 11:49:16.997985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31772 11:49:16.998545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31773 11:49:17.028784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31774 11:49:17.029194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31776 11:49:17.058982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31777 11:49:17.059395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31779 11:49:17.089428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31780 11:49:17.089891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31782 11:49:17.120147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31784 11:49:17.120695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31785 11:49:17.150199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31786 11:49:17.150564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31788 11:49:17.180527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31790 11:49:17.180943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31791 11:49:17.229698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31792 11:49:17.230113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31794 11:49:17.262056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31796 11:49:17.262457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31797 11:49:17.293187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31798 11:49:17.293566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31800 11:49:17.323174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31801 11:49:17.323517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31803 11:49:17.353491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31804 11:49:17.353863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31806 11:49:17.383583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31807 11:49:17.383941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31809 11:49:17.413938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31810 11:49:17.414316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31812 11:49:17.445177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31814 11:49:17.445554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31815 11:49:17.475274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31816 11:49:17.475702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31818 11:49:17.505916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31819 11:49:17.506381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31821 11:49:17.537300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31823 11:49:17.537887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31824 11:49:17.567304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31826 11:49:17.567865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31827 11:49:17.597914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31829 11:49:17.598513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31830 11:49:17.629248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31831 11:49:17.629699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31833 11:49:17.659739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31834 11:49:17.660173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31836 11:49:17.690327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31838 11:49:17.690857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31839 11:49:17.721446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31840 11:49:17.721861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31842 11:49:17.751920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31844 11:49:17.752466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31845 11:49:17.782919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31847 11:49:17.783478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31848 11:49:17.813640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31850 11:49:17.814169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31851 11:49:17.844052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31853 11:49:17.844665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31854 11:49:17.875244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31855 11:49:17.875652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31857 11:49:17.906295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31859 11:49:17.906836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31860 11:49:17.936640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31861 11:49:17.937084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31863 11:49:17.967193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31864 11:49:17.967658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31866 11:49:17.998311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31868 11:49:17.998908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31869 11:49:18.028810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31871 11:49:18.029414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31872 11:49:18.059614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31873 11:49:18.060098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31875 11:49:18.089925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31876 11:49:18.090362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31878 11:49:18.120192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31879 11:49:18.120555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31881 11:49:18.150476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31882 11:49:18.150886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31884 11:49:18.181247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31886 11:49:18.181770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31887 11:49:18.213171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31888 11:49:18.213673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31890 11:49:18.244160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31891 11:49:18.244618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31893 11:49:18.276095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31894 11:49:18.276563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31896 11:49:18.306566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31897 11:49:18.307034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31899 11:49:18.338289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31901 11:49:18.338919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31902 11:49:18.369668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31904 11:49:18.370208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31905 11:49:18.401228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31907 11:49:18.401791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31908 11:49:18.435222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31909 11:49:18.435696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31911 11:49:18.466665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31912 11:49:18.467069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31914 11:49:18.499013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31915 11:49:18.499482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31917 11:49:18.531069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31919 11:49:18.531656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31920 11:49:18.562276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31921 11:49:18.562739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31923 11:49:18.593178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31924 11:49:18.593658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31926 11:49:18.625601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31927 11:49:18.626068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31929 11:49:18.656663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31931 11:49:18.657218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31932 11:49:18.687689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31933 11:49:18.688126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31935 11:49:18.721592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
31936 11:49:18.722085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
31938 11:49:18.753192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
31939 11:49:18.753586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
31941 11:49:18.784141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
31943 11:49:18.784717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
31944 11:49:18.815227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
31945 11:49:18.815668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
31947 11:49:18.846335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
31948 11:49:18.846788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
31950 11:49:18.877432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
31951 11:49:18.877840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
31953 11:49:18.908557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
31955 11:49:18.909172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
31956 11:49:18.939596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
31958 11:49:18.940143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
31959 11:49:18.970521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
31961 11:49:18.971059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
31962 11:49:19.001410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
31964 11:49:19.001981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
31965 11:49:19.031517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
31966 11:49:19.031918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
31968 11:49:19.061452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
31969 11:49:19.061894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
31971 11:49:19.091884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
31973 11:49:19.092390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
31974 11:49:19.122713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
31976 11:49:19.123172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
31977 11:49:19.153235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
31978 11:49:19.153625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
31980 11:49:19.183410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
31981 11:49:19.183764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
31983 11:49:19.213668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
31984 11:49:19.214111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
31986 11:49:19.244134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
31988 11:49:19.244659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
31989 11:49:19.275251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
31991 11:49:19.275773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
31992 11:49:19.305806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
31993 11:49:19.306262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
31995 11:49:19.336333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
31997 11:49:19.336865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
31998 11:49:19.366917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
31999 11:49:19.367313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
32001 11:49:19.397504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
32002 11:49:19.397908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
32004 11:49:19.427655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
32005 11:49:19.428062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
32007 11:49:19.458356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
32008 11:49:19.458790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
32010 11:49:19.489122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
32012 11:49:19.489556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
32013 11:49:19.520825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
32015 11:49:19.521270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
32016 11:49:19.551518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
32017 11:49:19.551977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
32019 11:49:19.581715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
32020 11:49:19.582115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
32022 11:49:19.612831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
32024 11:49:19.613373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
32025 11:49:19.643093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
32026 11:49:19.643505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
32028 11:49:19.673504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
32029 11:49:19.673930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
32031 11:49:19.705013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
32032 11:49:19.705472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
32034 11:49:19.735665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
32035 11:49:19.736099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
32037 11:49:19.766510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
32038 11:49:19.766923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
32040 11:49:19.797313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
32041 11:49:19.797745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
32043 11:49:19.827952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
32044 11:49:19.828445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
32046 11:49:19.858737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
32047 11:49:19.859151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
32049 11:49:19.889063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
32050 11:49:19.889453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
32052 11:49:19.919108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
32054 11:49:19.919633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
32055 11:49:19.949303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
32056 11:49:19.949692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
32058 11:49:19.979426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
32059 11:49:19.979849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
32061 11:49:20.009780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
32063 11:49:20.010270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
32064 11:49:20.039900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
32065 11:49:20.040300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
32067 11:49:20.069912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
32069 11:49:20.070393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
32070 11:49:20.099852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
32071 11:49:20.100295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
32073 11:49:20.130337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
32074 11:49:20.130731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
32076 11:49:20.160678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
32078 11:49:20.161153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
32079 11:49:20.190884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
32080 11:49:20.191305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
32082 11:49:20.221567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
32083 11:49:20.221991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
32085 11:49:20.252590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
32086 11:49:20.252991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
32088 11:49:20.282569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
32089 11:49:20.282973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
32091 11:49:20.312995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
32092 11:49:20.313418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
32094 11:49:20.343374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
32096 11:49:20.343763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
32097 11:49:20.373505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
32098 11:49:20.373935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
32100 11:49:20.403782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
32102 11:49:20.404283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
32103 11:49:20.433847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
32105 11:49:20.434328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
32106 11:49:20.464197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
32107 11:49:20.464597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
32109 11:49:20.495482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
32111 11:49:20.496031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
32112 11:49:20.525696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
32113 11:49:20.526105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
32115 11:49:20.556198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
32117 11:49:20.556693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
32118 11:49:20.586473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
32119 11:49:20.586890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
32121 11:49:20.617149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
32123 11:49:20.617597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
32124 11:49:20.648675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
32125 11:49:20.649108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
32127 11:49:20.681591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
32129 11:49:20.682060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
32130 11:49:20.712376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
32132 11:49:20.712936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
32133 11:49:20.743444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
32135 11:49:20.744113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
32136 11:49:20.774178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
32137 11:49:20.774586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
32139 11:49:20.804224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
32140 11:49:20.804615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
32142 11:49:20.835380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
32144 11:49:20.835888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
32145 11:49:20.866185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
32146 11:49:20.866616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
32148 11:49:20.897258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
32150 11:49:20.897765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
32151 11:49:20.927571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
32152 11:49:20.927937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
32154 11:49:20.958627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
32155 11:49:20.959000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
32157 11:49:20.989566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
32158 11:49:20.989998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
32160 11:49:21.021364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
32161 11:49:21.021939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
32163 11:49:21.053826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
32165 11:49:21.054378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
32166 11:49:21.085021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
32167 11:49:21.085456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
32169 11:49:21.116385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
32171 11:49:21.116947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
32172 11:49:21.147219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
32174 11:49:21.147840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
32175 11:49:21.178272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
32177 11:49:21.178709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
32178 11:49:21.209879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
32179 11:49:21.210275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32181 11:49:21.243874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32182 11:49:21.244289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32184 11:49:21.275652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32186 11:49:21.276112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32187 11:49:21.306526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32188 11:49:21.306882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32190 11:49:21.337414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32191 11:49:21.337793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32193 11:49:21.369720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32194 11:49:21.370197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32196 11:49:21.401715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32198 11:49:21.402287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32199 11:49:21.435020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32200 11:49:21.435465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32202 11:49:21.467250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32204 11:49:21.467610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32205 11:49:21.499737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32206 11:49:21.500144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32208 11:49:21.533752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32209 11:49:21.534284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32211 11:49:21.565072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32212 11:49:21.565609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32214 11:49:21.601471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32215 11:49:21.601906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32217 11:49:21.635448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32218 11:49:21.635873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32220 11:49:21.671242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32221 11:49:21.671708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32223 11:49:21.708435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32225 11:49:21.708893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32226 11:49:21.743124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32227 11:49:21.743478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32229 11:49:21.777505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32231 11:49:21.777776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32232 11:49:21.812217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32233 11:49:21.812624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32235 11:49:21.845629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32237 11:49:21.846106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32238 11:49:21.877342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32240 11:49:21.877833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32241 11:49:21.907952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32242 11:49:21.908403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32244 11:49:21.938519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32246 11:49:21.939059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32247 11:49:21.969265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32249 11:49:21.969863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32250 11:49:21.999657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32251 11:49:22.000108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32253 11:49:22.030223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32254 11:49:22.030677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32256 11:49:22.060898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32258 11:49:22.061474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32259 11:49:22.091315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32260 11:49:22.091767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32262 11:49:22.123209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32264 11:49:22.123657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32265 11:49:22.155864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32266 11:49:22.156301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32268 11:49:22.187675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32270 11:49:22.188231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32271 11:49:22.218883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32272 11:49:22.219300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32274 11:49:22.249296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32275 11:49:22.249691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32277 11:49:22.281154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32279 11:49:22.281617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32280 11:49:22.312590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32282 11:49:22.313144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32283 11:49:22.371731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32284 11:49:22.372229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32286 11:49:22.403944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32287 11:49:22.404425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32289 11:49:22.434953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32290 11:49:22.435435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32292 11:49:22.469700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32293 11:49:22.470259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32295 11:49:22.502791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32297 11:49:22.503357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32298 11:49:22.534502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32299 11:49:22.534977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32301 11:49:22.565344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32302 11:49:22.565778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32304 11:49:22.595690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32305 11:49:22.596125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32307 11:49:22.626456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32308 11:49:22.626896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32310 11:49:22.656831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32311 11:49:22.657313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32313 11:49:22.687684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32314 11:49:22.688147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32316 11:49:22.718716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32318 11:49:22.719164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32319 11:49:22.750420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32320 11:49:22.750848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32322 11:49:22.781708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32324 11:49:22.782149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32325 11:49:22.813084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32326 11:49:22.813496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32328 11:49:22.845168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32330 11:49:22.845619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32331 11:49:22.875938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32332 11:49:22.876425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32334 11:49:22.907058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32336 11:49:22.907542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32337 11:49:22.937635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32339 11:49:22.938130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32340 11:49:22.968764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32342 11:49:22.969237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32343 11:49:22.999244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32344 11:49:22.999667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32346 11:49:23.030342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32348 11:49:23.030967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32349 11:49:23.061678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32351 11:49:23.062315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32352 11:49:23.093217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32353 11:49:23.093686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32355 11:49:23.124141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32356 11:49:23.124599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32358 11:49:23.155498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32360 11:49:23.156046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32361 11:49:23.186279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32362 11:49:23.186736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32364 11:49:23.217255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32365 11:49:23.217700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32367 11:49:23.249265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32368 11:49:23.249698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32370 11:49:23.280623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32372 11:49:23.281205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32373 11:49:23.311662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32375 11:49:23.312262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32376 11:49:23.343169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32378 11:49:23.343766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32379 11:49:23.374018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32380 11:49:23.374482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32382 11:49:23.406128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32384 11:49:23.406690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32385 11:49:23.437232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32386 11:49:23.437702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32388 11:49:23.468752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32389 11:49:23.469236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32391 11:49:23.499366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32392 11:49:23.499848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32394 11:49:23.530808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32396 11:49:23.531362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32397 11:49:23.563058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32399 11:49:23.563613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32400 11:49:23.595687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32401 11:49:23.596135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32403 11:49:23.627473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32405 11:49:23.627943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32406 11:49:23.659327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32407 11:49:23.659734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32409 11:49:23.690719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32411 11:49:23.691189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32412 11:49:23.721904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32413 11:49:23.722362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32415 11:49:23.753485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32417 11:49:23.754068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32418 11:49:23.791197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32419 11:49:23.791668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32421 11:49:23.823226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32422 11:49:23.823644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32424 11:49:23.855451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32425 11:49:23.855934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32427 11:49:23.887672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32428 11:49:23.888079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32430 11:49:23.926408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32431 11:49:23.926901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32433 11:49:23.959791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32434 11:49:23.960211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32436 11:49:23.991411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32437 11:49:23.991894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32439 11:49:24.022778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32441 11:49:24.023413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32442 11:49:24.053992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32443 11:49:24.054468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32445 11:49:24.087269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32446 11:49:24.087756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32448 11:49:24.120229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32449 11:49:24.120690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32451 11:49:24.152101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32452 11:49:24.152550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32454 11:49:24.183778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32455 11:49:24.184270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32457 11:49:24.214952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32458 11:49:24.215440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32460 11:49:24.246007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32461 11:49:24.246504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32463 11:49:24.277275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32464 11:49:24.277755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32466 11:49:24.308412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32468 11:49:24.308999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32469 11:49:24.340380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32471 11:49:24.340867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32472 11:49:24.373031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32473 11:49:24.373504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32475 11:49:24.405284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32476 11:49:24.405759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32478 11:49:24.437311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32479 11:49:24.437771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32481 11:49:24.470058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32482 11:49:24.470542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32484 11:49:24.504017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32486 11:49:24.504624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32487 11:49:24.535594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32488 11:49:24.536000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32490 11:49:24.567760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32491 11:49:24.568168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32493 11:49:24.600291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32495 11:49:24.600864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32496 11:49:24.632553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32498 11:49:24.633133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32499 11:49:24.665669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32500 11:49:24.666126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32502 11:49:24.701290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32503 11:49:24.701774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32505 11:49:24.733813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32506 11:49:24.734232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32508 11:49:24.765619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32509 11:49:24.766097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32511 11:49:24.803402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32512 11:49:24.803871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32514 11:49:24.835638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32515 11:49:24.836054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32517 11:49:24.869804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32519 11:49:24.870450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32520 11:49:24.901680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32521 11:49:24.902172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32523 11:49:24.934946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32525 11:49:24.935577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32526 11:49:24.967512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32527 11:49:24.967951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32529 11:49:24.999700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32530 11:49:25.000135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32532 11:49:25.032515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32534 11:49:25.033116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32535 11:49:25.066092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32536 11:49:25.066563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32538 11:49:25.098427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32539 11:49:25.098883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32541 11:49:25.131702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32542 11:49:25.132136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32544 11:49:25.166629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32545 11:49:25.167065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32547 11:49:25.199892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32548 11:49:25.200315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32550 11:49:25.235701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32552 11:49:25.236112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32553 11:49:25.276681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32555 11:49:25.277144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32556 11:49:25.310254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32557 11:49:25.310638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32559 11:49:25.342781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32560 11:49:25.343198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32562 11:49:25.374860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32563 11:49:25.375324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32565 11:49:25.407022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32566 11:49:25.407497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32568 11:49:25.444728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32570 11:49:25.445200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32571 11:49:25.478090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32572 11:49:25.478512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32574 11:49:25.510237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32575 11:49:25.510705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32577 11:49:25.542130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32578 11:49:25.542540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32580 11:49:25.578045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32581 11:49:25.578462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32583 11:49:25.610667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32584 11:49:25.611143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32586 11:49:25.643669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32587 11:49:25.644078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32589 11:49:25.675336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32590 11:49:25.675754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32592 11:49:25.707556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32593 11:49:25.707972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32595 11:49:25.739139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32597 11:49:25.739591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32598 11:49:25.770265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32599 11:49:25.770696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32601 11:49:25.801289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32602 11:49:25.801687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32604 11:49:25.831804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32605 11:49:25.832227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32607 11:49:25.862702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32609 11:49:25.863154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32610 11:49:25.893595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32611 11:49:25.894018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32613 11:49:25.924993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32614 11:49:25.925414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32616 11:49:25.957336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32617 11:49:25.957738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32619 11:49:25.989899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32621 11:49:25.990346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32622 11:49:26.021089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32623 11:49:26.021481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32625 11:49:26.052587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32627 11:49:26.053024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32628 11:49:26.083824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32630 11:49:26.084276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32631 11:49:26.115546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32633 11:49:26.115991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32634 11:49:26.147015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32635 11:49:26.147415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32637 11:49:26.179507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32638 11:49:26.179920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32640 11:49:26.211503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32641 11:49:26.211907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32643 11:49:26.243015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32644 11:49:26.243475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32646 11:49:26.275740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32647 11:49:26.276232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32649 11:49:26.307366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32650 11:49:26.307776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32652 11:49:26.339219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32654 11:49:26.339879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32655 11:49:26.371574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32656 11:49:26.371986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32658 11:49:26.406340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32660 11:49:26.406920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32661 11:49:26.440597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32663 11:49:26.441174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32664 11:49:26.473705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32665 11:49:26.474176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32667 11:49:26.505641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32668 11:49:26.506103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32670 11:49:26.537364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32671 11:49:26.537794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32673 11:49:26.570513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32674 11:49:26.570990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32676 11:49:26.603167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32677 11:49:26.603583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32679 11:49:26.636980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32681 11:49:26.637541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32682 11:49:26.669440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32683 11:49:26.669934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32685 11:49:26.701460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32686 11:49:26.701925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32688 11:49:26.733401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32689 11:49:26.733858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32691 11:49:26.765963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32692 11:49:26.766402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32694 11:49:26.799252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32695 11:49:26.799737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32697 11:49:26.831781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32698 11:49:26.832250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32700 11:49:26.863585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32702 11:49:26.864133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32703 11:49:26.895493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32704 11:49:26.895956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32706 11:49:26.927156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32707 11:49:26.927585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32709 11:49:26.958773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32710 11:49:26.959179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32712 11:49:26.991617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32713 11:49:26.992002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32715 11:49:27.023885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32716 11:49:27.024341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32718 11:49:27.055795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32719 11:49:27.056217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32721 11:49:27.087660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32722 11:49:27.088076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32724 11:49:27.119643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32725 11:49:27.120114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32727 11:49:27.152051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32728 11:49:27.152528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32730 11:49:27.184703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32731 11:49:27.185189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32733 11:49:27.216195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32735 11:49:27.216709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32736 11:49:27.247297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32737 11:49:27.247719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32739 11:49:27.280000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32740 11:49:27.280468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32742 11:49:27.311119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32744 11:49:27.311625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32745 11:49:27.342053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32746 11:49:27.342461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32748 11:49:27.374021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32750 11:49:27.374587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32751 11:49:27.406159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32752 11:49:27.406613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32754 11:49:27.437533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32755 11:49:27.437990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32757 11:49:27.502009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32758 11:49:27.502478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32760 11:49:27.534256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32761 11:49:27.534713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32763 11:49:27.566029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32764 11:49:27.566481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32766 11:49:27.597462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32767 11:49:27.597879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32769 11:49:27.629038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32770 11:49:27.629566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32772 11:49:27.661174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32773 11:49:27.661626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32775 11:49:27.693422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32776 11:49:27.693883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32778 11:49:27.725264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32779 11:49:27.725695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32781 11:49:27.756642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32783 11:49:27.757273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32784 11:49:27.787782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32786 11:49:27.788410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32787 11:49:27.820136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32788 11:49:27.820587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32790 11:49:27.851763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32791 11:49:27.852233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32793 11:49:27.884069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32794 11:49:27.884531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32796 11:49:27.916565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32798 11:49:27.917153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32799 11:49:27.948570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32801 11:49:27.949216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32802 11:49:27.981886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32803 11:49:27.982326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32805 11:49:28.015408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32806 11:49:28.015824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32808 11:49:28.047541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32809 11:49:28.047948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32811 11:49:28.080727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32813 11:49:28.081171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32814 11:49:28.113012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32815 11:49:28.113415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32817 11:49:28.145034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32818 11:49:28.145436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32820 11:49:28.177405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32821 11:49:28.177819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32823 11:49:28.209406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32825 11:49:28.209978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32826 11:49:28.240764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32827 11:49:28.241234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32829 11:49:28.271474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32830 11:49:28.271932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32832 11:49:28.302672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32833 11:49:28.303118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32835 11:49:28.335606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32837 11:49:28.336223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32838 11:49:28.367682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32839 11:49:28.368188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32841 11:49:28.399083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32842 11:49:28.399514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32844 11:49:28.430062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32846 11:49:28.430564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32847 11:49:28.461615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32848 11:49:28.462024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32850 11:49:28.492919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32852 11:49:28.493419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32853 11:49:28.523384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32854 11:49:28.523806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32856 11:49:28.555345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32858 11:49:28.555864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32859 11:49:28.586083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32861 11:49:28.586562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32862 11:49:28.617413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32864 11:49:28.617943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32865 11:49:28.648608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32867 11:49:28.649149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32868 11:49:28.679729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32870 11:49:28.680276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32871 11:49:28.711294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32872 11:49:28.711741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32874 11:49:28.743271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32876 11:49:28.743827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32877 11:49:28.774796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32878 11:49:28.775240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32880 11:49:28.805806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32881 11:49:28.806255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32883 11:49:28.838243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32885 11:49:28.838790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32886 11:49:28.870094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32888 11:49:28.870722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32889 11:49:28.901608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32891 11:49:28.902255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32892 11:49:28.932951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32893 11:49:28.933369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32895 11:49:28.963649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32897 11:49:28.964269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32898 11:49:28.995958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32900 11:49:28.996514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32901 11:49:29.027381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32903 11:49:29.027961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32904 11:49:29.058763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32905 11:49:29.059155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32907 11:49:29.094715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32908 11:49:29.095150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32910 11:49:29.126215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32911 11:49:29.126629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32913 11:49:29.157008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32914 11:49:29.157365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32916 11:49:29.187920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32918 11:49:29.188473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32919 11:49:29.218858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32920 11:49:29.219260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32922 11:49:29.249728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32923 11:49:29.250150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32925 11:49:29.280714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32926 11:49:29.281187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32928 11:49:29.311609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32929 11:49:29.312066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32931 11:49:29.342085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32932 11:49:29.342554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32934 11:49:29.373719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
32936 11:49:29.374337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
32937 11:49:29.404192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
32939 11:49:29.404796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
32940 11:49:29.434607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
32941 11:49:29.435072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
32943 11:49:29.465770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
32944 11:49:29.466266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
32946 11:49:29.496192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
32947 11:49:29.496673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
32949 11:49:29.526355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
32950 11:49:29.526837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
32952 11:49:29.558070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
32953 11:49:29.558560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
32955 11:49:29.589100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
32956 11:49:29.589591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
32958 11:49:29.619549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
32959 11:49:29.620038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
32961 11:49:29.650351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
32962 11:49:29.650838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
32964 11:49:29.681230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
32966 11:49:29.681833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
32967 11:49:29.711766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
32969 11:49:29.712221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
32970 11:49:29.744152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
32972 11:49:29.744622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
32973 11:49:29.774882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
32975 11:49:29.775360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
32976 11:49:29.806385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
32977 11:49:29.806819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
32979 11:49:29.841608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
32980 11:49:29.842115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
32982 11:49:29.873469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
32983 11:49:29.873962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
32985 11:49:29.906268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
32987 11:49:29.906855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
32988 11:49:29.938485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
32990 11:49:29.939048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
32991 11:49:29.969595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
32993 11:49:29.970145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
32994 11:49:30.001957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
32996 11:49:30.002612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
32997 11:49:30.036299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
32999 11:49:30.036709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
33000 11:49:30.067915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
33001 11:49:30.068413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
33003 11:49:30.101955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
33004 11:49:30.102350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
33006 11:49:30.133781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
33008 11:49:30.134342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
33009 11:49:30.165209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
33011 11:49:30.165760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
33012 11:49:30.198333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
33013 11:49:30.198871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
33015 11:49:30.230970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
33017 11:49:30.231430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
33018 11:49:30.265442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
33019 11:49:30.265843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
33021 11:49:30.299202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
33023 11:49:30.299605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
33024 11:49:30.329968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
33026 11:49:30.330399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
33027 11:49:30.363705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
33029 11:49:30.364118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
33030 11:49:30.398016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
33032 11:49:30.398460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
33033 11:49:30.432460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
33035 11:49:30.433094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
33036 11:49:30.466998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
33038 11:49:30.467433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
33039 11:49:30.498305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
33041 11:49:30.498728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
33042 11:49:30.529631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
33044 11:49:30.530163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
33045 11:49:30.564092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
33046 11:49:30.564633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
33048 11:49:30.598534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
33049 11:49:30.599015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
33051 11:49:30.631277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
33053 11:49:30.631963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
33054 11:49:30.666478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
33055 11:49:30.666952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
33057 11:49:30.698452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33058 11:49:30.698901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33060 11:49:30.731774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
33062 11:49:30.732494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33063 11:49:30.765492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33064 11:49:30.765953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33066 11:49:30.796695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33067 11:49:30.797122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33069 11:49:30.830572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33070 11:49:30.830997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
33072 11:49:30.862458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33073 11:49:30.862890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33075 11:49:30.894797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33076 11:49:30.895223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33078 11:49:30.930145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33079 11:49:30.930580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
33081 11:49:30.962615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33082 11:49:30.963036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33084 11:49:30.994561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33085 11:49:30.994969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33087 11:49:31.028081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
33089 11:49:31.028551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33090 11:49:31.059654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33091 11:49:31.060054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33093 11:49:31.092534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33095 11:49:31.093140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33096 11:49:31.126043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33097 11:49:31.126471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
33099 11:49:31.157457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33100 11:49:31.157799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33102 11:49:31.190056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
33103 11:49:31.190442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
33105 11:49:31.222966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33107 11:49:31.223562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33108 11:49:31.254878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
33110 11:49:31.255489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33111 11:49:31.293481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33113 11:49:31.294162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33114 11:49:31.326359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33116 11:49:31.326935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33117 11:49:31.358459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
33119 11:49:31.358914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33120 11:49:31.393833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33121 11:49:31.394205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33123 11:49:31.427479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33124 11:49:31.427855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33126 11:49:31.460806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33127 11:49:31.461418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
33129 11:49:31.493910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33130 11:49:31.494370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33132 11:49:31.525086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33133 11:49:31.525502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33135 11:49:31.557130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
33137 11:49:31.557611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33138 11:49:31.590147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33140 11:49:31.590697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33141 11:49:31.624694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33142 11:49:31.625127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33144 11:49:31.659508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33145 11:49:31.659950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
33147 11:49:31.691448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33148 11:49:31.691891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33150 11:49:31.723188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
33152 11:49:31.723657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
33153 11:49:31.757502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33154 11:49:31.757945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33156 11:49:31.790172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33157 11:49:31.790584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
33159 11:49:31.824251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33160 11:49:31.824672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33162 11:49:31.858701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33164 11:49:31.859082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33165 11:49:31.891264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
33167 11:49:31.891680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33168 11:49:31.923844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33169 11:49:31.924305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33171 11:49:31.958472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33172 11:49:31.958893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33174 11:49:31.990139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33175 11:49:31.990472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
33177 11:49:32.023244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33178 11:49:32.023768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33180 11:49:32.055278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33181 11:49:32.055727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33183 11:49:32.086868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33185 11:49:32.087330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33186 11:49:32.122466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33187 11:49:32.122909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33189 11:49:32.155936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33190 11:49:32.156381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33192 11:49:32.188128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33193 11:49:32.188488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33195 11:49:32.219470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33196 11:49:32.219877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33198 11:49:32.250375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33199 11:49:32.250788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33201 11:49:32.281831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33202 11:49:32.282196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33204 11:49:32.313510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33205 11:49:32.313936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33207 11:49:32.346091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33209 11:49:32.346657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33210 11:49:32.378014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33211 11:49:32.378443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33213 11:49:32.409588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33214 11:49:32.409956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33216 11:49:32.441412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33217 11:49:32.441793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33219 11:49:32.473125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33220 11:49:32.473492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33222 11:49:32.503850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33224 11:49:32.504284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33225 11:49:32.536118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33227 11:49:32.536602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33228 11:49:32.590378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33229 11:49:32.590928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33231 11:49:32.656432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33232 11:49:32.656821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33234 11:49:32.690755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33235 11:49:32.691167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33237 11:49:32.722594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33238 11:49:32.723032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33240 11:49:32.754760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33241 11:49:32.755178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33243 11:49:32.787743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33245 11:49:32.788262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33246 11:49:32.819221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33247 11:49:32.819659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33249 11:49:32.850533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33251 11:49:32.851110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33252 11:49:32.883158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33253 11:49:32.883566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33255 11:49:32.914697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33257 11:49:32.915133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33258 11:49:32.945998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33260 11:49:32.946483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33261 11:49:32.977008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33262 11:49:32.977454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33264 11:49:33.007798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33265 11:49:33.008278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33267 11:49:33.039863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33268 11:49:33.040337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33270 11:49:33.071235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33272 11:49:33.071683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33273 11:49:33.102445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33274 11:49:33.102817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33276 11:49:33.133867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33278 11:49:33.134262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33279 11:49:33.165454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33280 11:49:33.165802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33282 11:49:33.196437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33284 11:49:33.196870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33285 11:49:33.240059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33287 11:49:33.240500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33288 11:49:33.273248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33290 11:49:33.273729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33291 11:49:33.304497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33293 11:49:33.304948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33294 11:49:33.336109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33296 11:49:33.336567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33297 11:49:33.367151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33298 11:49:33.367594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33300 11:49:33.398123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33301 11:49:33.398579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33303 11:49:33.430110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33305 11:49:33.430669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33306 11:49:33.461424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33307 11:49:33.461807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33309 11:49:33.492442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33311 11:49:33.492861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33312 11:49:33.523328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33313 11:49:33.523723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33315 11:49:33.554655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33317 11:49:33.555057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33318 11:49:33.585904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33319 11:49:33.586269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33321 11:49:33.617242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33322 11:49:33.617663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33324 11:49:33.648619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33326 11:49:33.649172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33327 11:49:33.679853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33329 11:49:33.680398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33330 11:49:33.711149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33331 11:49:33.711573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33333 11:49:33.742125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33334 11:49:33.742496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33336 11:49:33.774141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33338 11:49:33.774532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33339 11:49:33.805557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33340 11:49:33.805979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33342 11:49:33.836733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33344 11:49:33.837157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33345 11:49:33.867672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33346 11:49:33.868066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33348 11:49:33.898775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33349 11:49:33.899144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33351 11:49:33.930144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33352 11:49:33.930601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33354 11:49:33.961851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33355 11:49:33.962297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33357 11:49:33.993571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33358 11:49:33.993989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33360 11:49:34.025055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33361 11:49:34.025490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33363 11:49:34.057196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33364 11:49:34.057585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33366 11:49:34.088714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33367 11:49:34.089096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33369 11:49:34.120157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33370 11:49:34.120590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33372 11:49:34.151795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33374 11:49:34.152328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33375 11:49:34.182744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33376 11:49:34.183099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33378 11:49:34.214138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33379 11:49:34.214553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33381 11:49:34.245972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33383 11:49:34.246418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33384 11:49:34.278544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33385 11:49:34.278968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33387 11:49:34.310315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33388 11:49:34.310701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33390 11:49:34.341696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33392 11:49:34.342133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33393 11:49:34.373557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33394 11:49:34.374048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33396 11:49:34.405610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33397 11:49:34.406102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33399 11:49:34.438213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33401 11:49:34.438775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33402 11:49:34.470443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33403 11:49:34.470909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33405 11:49:34.502481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33406 11:49:34.502896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33408 11:49:34.534355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33409 11:49:34.534787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33411 11:49:34.566279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33413 11:49:34.566722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33414 11:49:34.598540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33415 11:49:34.598992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33417 11:49:34.629927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33418 11:49:34.630375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33420 11:49:34.661494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33421 11:49:34.661898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33423 11:49:34.693210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33425 11:49:34.693808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33426 11:49:34.724169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33428 11:49:34.724685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33429 11:49:34.757039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33430 11:49:34.757462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33432 11:49:34.789460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33433 11:49:34.789802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33435 11:49:34.821638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33436 11:49:34.822005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33438 11:49:34.853406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33439 11:49:34.853807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33441 11:49:34.885330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33442 11:49:34.885738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33444 11:49:34.918063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33445 11:49:34.918454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33447 11:49:34.949696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33449 11:49:34.950142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33450 11:49:34.981303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33452 11:49:34.981800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33453 11:49:35.012092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33454 11:49:35.012516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33456 11:49:35.043204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33457 11:49:35.043620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33459 11:49:35.075245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33460 11:49:35.075626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33462 11:49:35.106385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33464 11:49:35.106819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33465 11:49:35.137956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33466 11:49:35.138394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33468 11:49:35.169196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33469 11:49:35.169632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33471 11:49:35.201058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33473 11:49:35.201637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33474 11:49:35.231771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33475 11:49:35.232213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33477 11:49:35.263180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33479 11:49:35.263631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33480 11:49:35.295949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33482 11:49:35.296569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33483 11:49:35.327365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33484 11:49:35.327849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33486 11:49:35.358838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33488 11:49:35.359481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33489 11:49:35.390521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33490 11:49:35.390994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33492 11:49:35.422562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33494 11:49:35.423107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33495 11:49:35.455031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33497 11:49:35.455480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33498 11:49:35.486351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33499 11:49:35.486827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33501 11:49:35.518279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33502 11:49:35.518701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33504 11:49:35.550217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33505 11:49:35.550636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33507 11:49:35.582843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33508 11:49:35.583295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33510 11:49:35.614568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33512 11:49:35.615152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33513 11:49:35.645799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33514 11:49:35.646204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33516 11:49:35.677689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33518 11:49:35.678334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33519 11:49:35.709682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33520 11:49:35.710091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33522 11:49:35.741235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33523 11:49:35.741709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33525 11:49:35.772428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33527 11:49:35.773023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33528 11:49:35.805012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33530 11:49:35.805588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33531 11:49:35.836909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33533 11:49:35.837668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33534 11:49:35.868995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33535 11:49:35.869408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33537 11:49:35.901139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33539 11:49:35.901580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33540 11:49:35.933234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33541 11:49:35.933689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33543 11:49:35.965210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33545 11:49:35.965767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33546 11:49:35.997000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33547 11:49:35.997442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33549 11:49:36.027934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33551 11:49:36.028381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33552 11:49:36.059406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33554 11:49:36.060098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33555 11:49:36.091166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33556 11:49:36.091577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33558 11:49:36.122783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33559 11:49:36.123269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33561 11:49:36.154716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33563 11:49:36.155281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33564 11:49:36.185909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33565 11:49:36.186311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33567 11:49:36.217665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33568 11:49:36.218117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33570 11:49:36.249450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33571 11:49:36.249850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33573 11:49:36.280510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33575 11:49:36.280898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33576 11:49:36.312456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33578 11:49:36.312839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33579 11:49:36.343898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33580 11:49:36.344285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33582 11:49:36.375637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33583 11:49:36.376094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33585 11:49:36.406731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33586 11:49:36.407143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33588 11:49:36.440018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33589 11:49:36.440520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33591 11:49:36.472025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33592 11:49:36.472437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33594 11:49:36.505323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33596 11:49:36.505769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33597 11:49:36.537042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33598 11:49:36.537514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33600 11:49:36.568347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33602 11:49:36.568785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33603 11:49:36.599986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33604 11:49:36.600468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33606 11:49:36.631540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33607 11:49:36.631949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33609 11:49:36.664648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33610 11:49:36.665076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33612 11:49:36.697279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33613 11:49:36.697816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33615 11:49:36.732558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33617 11:49:36.733210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33618 11:49:36.767086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33620 11:49:36.767543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33621 11:49:36.801603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33622 11:49:36.802048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33624 11:49:36.835066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33625 11:49:36.835464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33627 11:49:36.866987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33628 11:49:36.867399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33630 11:49:36.899658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33631 11:49:36.900089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33633 11:49:36.931852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33634 11:49:36.932283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33636 11:49:36.963053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33637 11:49:36.963459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33639 11:49:36.995120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33640 11:49:36.995595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33642 11:49:37.026680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33644 11:49:37.027305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33645 11:49:37.057979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33646 11:49:37.058413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33648 11:49:37.090014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33649 11:49:37.090423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33651 11:49:37.122523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33652 11:49:37.123003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33654 11:49:37.153902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33656 11:49:37.154440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33657 11:49:37.185031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33658 11:49:37.185490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33660 11:49:37.216127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33662 11:49:37.216669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33663 11:49:37.247484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33664 11:49:37.247935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33666 11:49:37.278531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33667 11:49:37.278938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33669 11:49:37.310839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33670 11:49:37.311305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33672 11:49:37.342619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33673 11:49:37.343066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33675 11:49:37.374006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33677 11:49:37.374546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33678 11:49:37.405072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33679 11:49:37.405512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33681 11:49:37.436585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33683 11:49:37.436981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33684 11:49:37.467849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33685 11:49:37.468330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33687 11:49:37.500636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33689 11:49:37.501189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33690 11:49:37.532374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33692 11:49:37.532850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33693 11:49:37.564128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33694 11:49:37.564560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33696 11:49:37.596085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33697 11:49:37.596515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33699 11:49:37.628053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33700 11:49:37.628476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33702 11:49:37.661182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33704 11:49:37.661641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33705 11:49:37.709719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33706 11:49:37.710129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33708 11:49:37.746698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33709 11:49:37.747133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33711 11:49:37.778305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33713 11:49:37.778750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33714 11:49:37.809577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33715 11:49:37.809990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33717 11:49:37.841181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33719 11:49:37.841822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33720 11:49:37.873690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33721 11:49:37.874099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33723 11:49:37.905379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33724 11:49:37.905798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33726 11:49:37.937355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33727 11:49:37.937757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33729 11:49:37.969420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33730 11:49:37.969825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33732 11:49:38.001789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33733 11:49:38.002193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33735 11:49:38.034173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33736 11:49:38.034640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33738 11:49:38.065814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33740 11:49:38.066442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33741 11:49:38.098206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33742 11:49:38.098690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33744 11:49:38.130186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33745 11:49:38.130651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33747 11:49:38.163426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33748 11:49:38.163834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33750 11:49:38.195796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33752 11:49:38.196216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33753 11:49:38.227043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33754 11:49:38.227395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33756 11:49:38.258345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33758 11:49:38.258793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33759 11:49:38.290400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33761 11:49:38.290979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33762 11:49:38.322101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33763 11:49:38.322529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33765 11:49:38.354980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33767 11:49:38.355561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33768 11:49:38.387896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33769 11:49:38.388383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33771 11:49:38.419797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33773 11:49:38.420443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33774 11:49:38.452613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33775 11:49:38.453113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33777 11:49:38.484208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33778 11:49:38.484628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33780 11:49:38.516793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33781 11:49:38.517210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33783 11:49:38.549932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33785 11:49:38.550388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33786 11:49:38.586008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33787 11:49:38.586419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33789 11:49:38.618515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33791 11:49:38.618960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33792 11:49:38.650893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33794 11:49:38.651482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33795 11:49:38.682662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33797 11:49:38.683079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33798 11:49:38.716176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33800 11:49:38.716636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33801 11:49:38.748581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33803 11:49:38.749120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33804 11:49:38.779994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33805 11:49:38.780456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33807 11:49:38.811243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33808 11:49:38.811697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33810 11:49:38.842761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33812 11:49:38.843351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33813 11:49:38.873696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33814 11:49:38.874047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33816 11:49:38.907135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33817 11:49:38.907607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33819 11:49:38.939324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33820 11:49:38.939735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33822 11:49:38.970359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33823 11:49:38.970773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33825 11:49:39.001377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33826 11:49:39.001799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33828 11:49:39.033378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33829 11:49:39.033788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33831 11:49:39.065457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33832 11:49:39.065948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33834 11:49:39.097278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33835 11:49:39.097692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33837 11:49:39.129183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33838 11:49:39.129615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33840 11:49:39.160406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33842 11:49:39.160915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33843 11:49:39.191900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33844 11:49:39.192258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33846 11:49:39.223023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33847 11:49:39.223399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33849 11:49:39.254004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33850 11:49:39.254360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33852 11:49:39.286769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33853 11:49:39.287219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33855 11:49:39.319104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33856 11:49:39.319538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33858 11:49:39.351872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33859 11:49:39.352362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33861 11:49:39.383381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33863 11:49:39.383962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33864 11:49:39.415188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33866 11:49:39.415835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33867 11:49:39.446886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33868 11:49:39.447354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33870 11:49:39.478285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33871 11:49:39.478684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33873 11:49:39.510088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33875 11:49:39.510705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33876 11:49:39.541966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33877 11:49:39.542435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33879 11:49:39.574146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33880 11:49:39.574637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33882 11:49:39.605623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33883 11:49:39.606101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33885 11:49:39.637036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33886 11:49:39.637435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33888 11:49:39.668635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33890 11:49:39.669072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33891 11:49:39.700128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33893 11:49:39.700763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33894 11:49:39.732202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33896 11:49:39.732654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33897 11:49:39.763681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33898 11:49:39.764084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33900 11:49:39.795351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33901 11:49:39.795822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33903 11:49:39.826989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33904 11:49:39.827462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33906 11:49:39.858471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33907 11:49:39.858936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33909 11:49:39.889819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33910 11:49:39.890176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33912 11:49:39.922259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33914 11:49:39.922685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33915 11:49:39.955319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33916 11:49:39.955729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33918 11:49:39.987401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33920 11:49:39.987841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33921 11:49:40.018507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33922 11:49:40.018908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33924 11:49:40.050198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33925 11:49:40.050599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33927 11:49:40.081726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33928 11:49:40.082181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33930 11:49:40.113710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33932 11:49:40.114246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33933 11:49:40.144904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33934 11:49:40.145295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33936 11:49:40.176207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33937 11:49:40.176679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
33939 11:49:40.208174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33941 11:49:40.208795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33942 11:49:40.239559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33943 11:49:40.240027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33945 11:49:40.270947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
33947 11:49:40.271522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33948 11:49:40.301711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33949 11:49:40.302135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33951 11:49:40.333302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33952 11:49:40.333689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33954 11:49:40.364496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
33956 11:49:40.364947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33957 11:49:40.396085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33958 11:49:40.396487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33960 11:49:40.428184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33961 11:49:40.428659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33963 11:49:40.459835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33964 11:49:40.460325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
33966 11:49:40.491211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33968 11:49:40.491752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33969 11:49:40.522800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
33971 11:49:40.523329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
33972 11:49:40.554442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33973 11:49:40.554857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33975 11:49:40.586710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
33977 11:49:40.587121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33978 11:49:40.618019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33979 11:49:40.618473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33981 11:49:40.649729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33982 11:49:40.650208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33984 11:49:40.681405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33985 11:49:40.681875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
33987 11:49:40.713838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33988 11:49:40.714264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33990 11:49:40.746390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33991 11:49:40.746827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33993 11:49:40.777995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33994 11:49:40.778417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
33996 11:49:40.809372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33997 11:49:40.809729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33999 11:49:40.840525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
34001 11:49:40.841104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
34002 11:49:40.871691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
34003 11:49:40.872124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
34005 11:49:40.902748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
34006 11:49:40.903115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
34008 11:49:40.935311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
34009 11:49:40.935766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
34011 11:49:40.966997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
34012 11:49:40.967448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
34014 11:49:41.000468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
34016 11:49:41.001128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
34017 11:49:41.031679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
34018 11:49:41.032069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
34020 11:49:41.062698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
34021 11:49:41.063133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
34023 11:49:41.093995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
34025 11:49:41.094556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
34026 11:49:41.125692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
34028 11:49:41.126234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
34029 11:49:41.157280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
34030 11:49:41.157694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
34032 11:49:41.188299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
34034 11:49:41.188862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
34035 11:49:41.221377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
34036 11:49:41.221792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
34038 11:49:41.253133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
34039 11:49:41.253576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
34041 11:49:41.284467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
34043 11:49:41.284875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
34044 11:49:41.315971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
34045 11:49:41.316424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
34047 11:49:41.347895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
34049 11:49:41.348441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
34050 11:49:41.381862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
34052 11:49:41.382321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
34053 11:49:41.416256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
34055 11:49:41.416722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
34056 11:49:41.449081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
34057 11:49:41.449550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
34059 11:49:41.481254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
34060 11:49:41.481677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
34062 11:49:41.512965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
34064 11:49:41.513377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
34065 11:49:41.544309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
34067 11:49:41.544740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
34068 11:49:41.575708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
34069 11:49:41.576085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
34071 11:49:41.608403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
34073 11:49:41.608868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
34074 11:49:41.640905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
34075 11:49:41.641314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
34077 11:49:41.675209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
34078 11:49:41.675627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
34080 11:49:41.709300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
34081 11:49:41.709743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
34083 11:49:41.741970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
34084 11:49:41.742404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
34086 11:49:41.774719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
34087 11:49:41.775124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
34089 11:49:41.806861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
34090 11:49:41.807270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
34092 11:49:41.839126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
34094 11:49:41.839581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
34095 11:49:41.871114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
34096 11:49:41.871646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
34098 11:49:41.905222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
34099 11:49:41.905701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
34101 11:49:41.937509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
34103 11:49:41.938141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
34104 11:49:41.970293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
34106 11:49:41.970745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
34107 11:49:42.001834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
34108 11:49:42.002246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
34110 11:49:42.033467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
34111 11:49:42.033902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
34113 11:49:42.065226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
34114 11:49:42.065627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
34116 11:49:42.097268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
34117 11:49:42.097656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
34119 11:49:42.128875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
34120 11:49:42.129255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
34122 11:49:42.160112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
34123 11:49:42.160658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
34125 11:49:42.191310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
34126 11:49:42.191739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
34128 11:49:42.222508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
34129 11:49:42.222925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
34131 11:49:42.254500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
34132 11:49:42.254916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
34134 11:49:42.285960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
34135 11:49:42.286368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
34137 11:49:42.317707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
34138 11:49:42.318103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
34140 11:49:42.349174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
34141 11:49:42.349533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
34143 11:49:42.380224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
34144 11:49:42.380670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
34146 11:49:42.411750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
34147 11:49:42.412129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
34149 11:49:42.442755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
34150 11:49:42.443130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
34152 11:49:42.474480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
34153 11:49:42.474862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
34155 11:49:42.505524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
34156 11:49:42.505906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
34158 11:49:42.536920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
34160 11:49:42.537370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
34161 11:49:42.567519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
34162 11:49:42.567985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
34164 11:49:42.598559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
34165 11:49:42.598941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
34167 11:49:42.630512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
34168 11:49:42.630924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
34170 11:49:42.663057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
34171 11:49:42.663458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
34173 11:49:42.694484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
34175 11:49:42.695104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
34176 11:49:42.725663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
34178 11:49:42.726122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
34179 11:49:42.757242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34180 11:49:42.757699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34182 11:49:42.788127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34183 11:49:42.788568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34185 11:49:42.839892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34187 11:49:42.840508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34188 11:49:42.870989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34190 11:49:42.871532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34191 11:49:42.901622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34192 11:49:42.902060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34194 11:49:42.932564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34196 11:49:42.932947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34197 11:49:42.963762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34199 11:49:42.964193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34200 11:49:42.995357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34201 11:49:42.995745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34203 11:49:43.026603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34204 11:49:43.027051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34206 11:49:43.057510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34207 11:49:43.057908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34209 11:49:43.088452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34211 11:49:43.088900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34212 11:49:43.119701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34214 11:49:43.120159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34215 11:49:43.151371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34216 11:49:43.151841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34218 11:49:43.182868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34220 11:49:43.183418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34221 11:49:43.214226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34222 11:49:43.214694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34224 11:49:43.245551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34225 11:49:43.245970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34227 11:49:43.277917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34229 11:49:43.278540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34230 11:49:43.309680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34232 11:49:43.310121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34233 11:49:43.341557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34234 11:49:43.342066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34236 11:49:43.374147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34237 11:49:43.374569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34239 11:49:43.405637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34240 11:49:43.406056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34242 11:49:43.436825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34243 11:49:43.437195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34245 11:49:43.469673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34246 11:49:43.470095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34248 11:49:43.502461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34249 11:49:43.502911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34251 11:49:43.533907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34252 11:49:43.534368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34254 11:49:43.565267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34255 11:49:43.565694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34257 11:49:43.596065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34258 11:49:43.596478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34260 11:49:43.627412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34261 11:49:43.627883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34263 11:49:43.659015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34265 11:49:43.659547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34266 11:49:43.689924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34268 11:49:43.690561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34269 11:49:43.721516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34270 11:49:43.721928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34272 11:49:43.753491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34273 11:49:43.753927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34275 11:49:43.784463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34277 11:49:43.784910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34278 11:49:43.815952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34279 11:49:43.816386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34281 11:49:43.846964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34282 11:49:43.847395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34284 11:49:43.877928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34285 11:49:43.878345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34287 11:49:43.909284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34288 11:49:43.909690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34290 11:49:43.940544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34292 11:49:43.940969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34293 11:49:43.971572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34294 11:49:43.971942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34296 11:49:44.003320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34297 11:49:44.003702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34299 11:49:44.034499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34300 11:49:44.034886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34302 11:49:44.065946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34303 11:49:44.066405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34305 11:49:44.097170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34306 11:49:44.097637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34308 11:49:44.128176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34309 11:49:44.128625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34311 11:49:44.159737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34312 11:49:44.160151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34314 11:49:44.191599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34315 11:49:44.192018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34317 11:49:44.223928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34318 11:49:44.224351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34320 11:49:44.255663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34322 11:49:44.256298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34323 11:49:44.287684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34324 11:49:44.288093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34326 11:49:44.319284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34328 11:49:44.319743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34329 11:49:44.350794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34330 11:49:44.351263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34332 11:49:44.382101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34334 11:49:44.382643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34335 11:49:44.413703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34337 11:49:44.414241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34338 11:49:44.445536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34339 11:49:44.445995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34341 11:49:44.477229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34343 11:49:44.477841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34344 11:49:44.509760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34345 11:49:44.510216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34347 11:49:44.541691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34348 11:49:44.542110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34350 11:49:44.575915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34352 11:49:44.576565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34353 11:49:44.608048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34355 11:49:44.608646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34356 11:49:44.649216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34357 11:49:44.649801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34359 11:49:44.683695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34361 11:49:44.684255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34362 11:49:44.715451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34363 11:49:44.715911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34365 11:49:44.746822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34367 11:49:44.747389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34368 11:49:44.778028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34369 11:49:44.778442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34371 11:49:44.809502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34372 11:49:44.809915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34374 11:49:44.843990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34375 11:49:44.844410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34377 11:49:44.875814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34378 11:49:44.876223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34380 11:49:44.907631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34382 11:49:44.908183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34383 11:49:44.939049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34384 11:49:44.939531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34386 11:49:44.969986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34387 11:49:44.970448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34389 11:49:45.001290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34390 11:49:45.001760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34392 11:49:45.033404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34393 11:49:45.033889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34395 11:49:45.064563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34397 11:49:45.065190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34398 11:49:45.095557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34399 11:49:45.095976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34401 11:49:45.126642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34403 11:49:45.127206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34404 11:49:45.158069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34406 11:49:45.158504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34407 11:49:45.189912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34408 11:49:45.190324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34410 11:49:45.222385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34412 11:49:45.222848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34413 11:49:45.253804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34415 11:49:45.254367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34416 11:49:45.285229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34417 11:49:45.285686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34419 11:49:45.317503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34420 11:49:45.317925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34422 11:49:45.349446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34423 11:49:45.349873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34425 11:49:45.381289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34427 11:49:45.381923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34428 11:49:45.412287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34430 11:49:45.412916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34431 11:49:45.443786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34433 11:49:45.444375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34434 11:49:45.474971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34435 11:49:45.475453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34437 11:49:45.506251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34439 11:49:45.506712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34440 11:49:45.538544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34442 11:49:45.538990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34443 11:49:45.570120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34445 11:49:45.570726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34446 11:49:45.601282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34447 11:49:45.601692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34449 11:49:45.632428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34451 11:49:45.633069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34452 11:49:45.663794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34453 11:49:45.664251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34455 11:49:45.695741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34456 11:49:45.696204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34458 11:49:45.727445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34460 11:49:45.728063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34461 11:49:45.758572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34462 11:49:45.759029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34464 11:49:45.790022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34466 11:49:45.790634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34467 11:49:45.821598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34469 11:49:45.822040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34470 11:49:45.853570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34471 11:49:45.853978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34473 11:49:45.885428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34475 11:49:45.885875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34476 11:49:45.917160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34478 11:49:45.917785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34479 11:49:45.948919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34481 11:49:45.949452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34482 11:49:45.979928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34484 11:49:45.980372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34485 11:49:46.011434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34487 11:49:46.011873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34488 11:49:46.043241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34489 11:49:46.043648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34491 11:49:46.074474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34493 11:49:46.075018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34494 11:49:46.105987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34495 11:49:46.106438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34497 11:49:46.137697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34499 11:49:46.138271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34500 11:49:46.168755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34502 11:49:46.169184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34503 11:49:46.199591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34504 11:49:46.199969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34506 11:49:46.230620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34507 11:49:46.230965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34509 11:49:46.261757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34511 11:49:46.262117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34512 11:49:46.293070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34513 11:49:46.293509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34515 11:49:46.325477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34517 11:49:46.325949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34518 11:49:46.356786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34519 11:49:46.357228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34521 11:49:46.387727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34522 11:49:46.388239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34524 11:49:46.419481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34526 11:49:46.419928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34527 11:49:46.451335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34528 11:49:46.451737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34530 11:49:46.482951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34532 11:49:46.483536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34533 11:49:46.514119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34534 11:49:46.514589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34536 11:49:46.546088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34538 11:49:46.546567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34539 11:49:46.577443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34541 11:49:46.578105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34542 11:49:46.609117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34543 11:49:46.609692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34545 11:49:46.640909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34546 11:49:46.641390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34548 11:49:46.677533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34549 11:49:46.677984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34551 11:49:46.711693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34553 11:49:46.712149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34554 11:49:46.746085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34556 11:49:46.746548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34557 11:49:46.780087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34559 11:49:46.780569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34560 11:49:46.814298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34561 11:49:46.814707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34563 11:49:46.848414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34565 11:49:46.849002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34566 11:49:46.880004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34567 11:49:46.880404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34569 11:49:46.911443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34571 11:49:46.911935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34572 11:49:46.942816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34573 11:49:46.943247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34575 11:49:46.978052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34576 11:49:46.978538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34578 11:49:47.009999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34580 11:49:47.010557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34581 11:49:47.041471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34582 11:49:47.041953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34584 11:49:47.074000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34586 11:49:47.074569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34587 11:49:47.105634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34588 11:49:47.106130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34590 11:49:47.137613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34591 11:49:47.138036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34593 11:49:47.168714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34594 11:49:47.169146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34596 11:49:47.199328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34597 11:49:47.199817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34599 11:49:47.230266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34600 11:49:47.230737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34602 11:49:47.261692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34603 11:49:47.262093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34605 11:49:47.293152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34606 11:49:47.293572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34608 11:49:47.324725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34610 11:49:47.325163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34611 11:49:47.356037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34612 11:49:47.356472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34614 11:49:47.359380 + set +x
34615 11:49:47.359566 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 615297_1.1.3.5>
34616 11:49:47.359849 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 615297_1.1.3.5
34617 11:49:47.359958 Ending use of test pattern.
34618 11:49:47.360048 Ending test lava.1_kselftest-arm64_qemu (615297_1.1.3.5), duration 326.30
34620 11:49:47.363268 ok: lava_test_shell seems to have completed
34621 11:49:47.441321 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34622 11:49:47.446164 end: 3.1 lava-test-shell (duration 00:05:28) [common]
34623 11:49:47.446297 end: 3 lava-test-retry (duration 00:05:28) [common]
34624 11:49:47.446391 start: 4 finalize (timeout 00:03:22) [common]
34625 11:49:47.446481 start: 4.1 power-off (timeout 00:00:30) [common]
34626 11:49:47.446564 end: 4.1 power-off (duration 00:00:00) [common]
34627 11:49:47.446647 start: 4.2 read-feedback (timeout 00:03:22) [common]
34629 11:49:47.447098 Listened to connection for namespace 'common' for up to 1s
34630 11:49:48.451865 Finalising connection for namespace 'common'
34632 11:49:48.552837 / # poweroff
34633 11:49:48.553305 Already disconnected
34634 11:49:48.553522 poweroff
34635 11:49:48.956083 end: 4.2 read-feedback (duration 00:00:02) [common]
34636 11:49:48.956374 Already disconnected
34637 11:49:48.956541 end: 4 finalize (duration 00:00:02) [common]
34638 11:49:48.956716 Cleaning after the job
34639 11:49:48.956904 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/615297/deployimages-0qs6rb_b/kernel
34640 11:49:48.965587 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/615297/deployimages-0qs6rb_b/ramdisk
34641 11:49:48.981282 Stopping the qemu container lava-docker-qemu-615297-2.1.1-4f2zuaprig
34642 11:49:50.275891 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/615297
34643 11:49:50.368235 Job finished correctly