Boot log: qemu_arm64-virt-gicv3
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
- Errors: 0
1 11:42:01.435515 lava-dispatcher, installed at version: 2023.01
2 11:42:01.435715 start: 0 validate
3 11:42:01.435825 Start time: 2023-06-15 11:42:01.435818+00:00 (UTC)
4 11:42:01.436873 Validating that http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig/gcc-10/kernel/Image exists
5 11:42:01.770907 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/rootfs.cpio.gz exists
6 11:42:01.938045 cmd: ['docker', 'pull', 'kernelci/qemu']
7 11:42:01.938270 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 11:42:02.100227 >> Using default tag: latest
9 11:42:03.224265 >> latest: Pulling from kernelci/qemu
10 11:42:03.256097 >> Digest: sha256:ce67b4aa6149816ab5c39a34ebc77720cac0c3651072f2c36655342e38024d42
11 11:42:03.256308 >> Status: Image is up to date for kernelci/qemu:latest
12 11:42:03.289388 >> docker.io/kernelci/qemu:latest
13 11:42:03.293230 Returned 0 in 1 seconds
14 11:42:03.431328 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 11:42:03.431815 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 11:42:05.650592 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 11:42:05.651053 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 11:42:06.966861 Returned 0 in 3 seconds
19 11:42:07.068057 validate duration: 5.63
21 11:42:07.068596 start: 1 deployimages (timeout 00:03:00) [common]
22 11:42:07.068780 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 11:42:07.069253 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez
24 11:42:07.069506 makedir: /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin
25 11:42:07.069716 makedir: /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/tests
26 11:42:07.069912 makedir: /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/results
27 11:42:07.070109 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-add-keys
28 11:42:07.070364 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-add-sources
29 11:42:07.070600 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-background-process-start
30 11:42:07.070835 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-background-process-stop
31 11:42:07.071064 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-common-functions
32 11:42:07.071289 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-echo-ipv4
33 11:42:07.071516 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-install-packages
34 11:42:07.071744 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-installed-packages
35 11:42:07.071964 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-os-build
36 11:42:07.072189 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-probe-channel
37 11:42:07.072410 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-probe-ip
38 11:42:07.072633 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-target-ip
39 11:42:07.072857 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-target-mac
40 11:42:07.073080 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-target-storage
41 11:42:07.073304 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-test-case
42 11:42:07.073527 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-test-event
43 11:42:07.073762 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-test-feedback
44 11:42:07.073987 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-test-raise
45 11:42:07.074215 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-test-reference
46 11:42:07.074439 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-test-runner
47 11:42:07.074661 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-test-set
48 11:42:07.074881 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-test-shell
49 11:42:07.075112 Updating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-install-packages (oe)
50 11:42:07.075387 Updating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/bin/lava-installed-packages (oe)
51 11:42:07.075618 Creating /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/environment
52 11:42:07.075806 LAVA metadata
53 11:42:07.075937 - LAVA_JOB_ID=615224
54 11:42:07.076059 - LAVA_DISPATCHER_IP=172.27.0.2
55 11:42:07.076244 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 11:42:07.076378 skipped lava-vland-overlay
57 11:42:07.076520 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 11:42:07.076671 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 11:42:07.076793 skipped lava-multinode-overlay
60 11:42:07.076930 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 11:42:07.077077 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 11:42:07.077220 Loading test definitions
63 11:42:07.077396 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 11:42:07.077541 Using /lava-615224 at stage 0
65 11:42:07.078134 uuid=615224_1.1.3.1 testdef=None
66 11:42:07.078310 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 11:42:07.078465 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 11:42:07.079320 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 11:42:07.079773 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 11:42:07.080809 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 11:42:07.081274 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 11:42:07.082282 runner path: /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/0/tests/0_timesync-off test_uuid 615224_1.1.3.1
75 11:42:07.082559 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 11:42:07.083013 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 11:42:07.083150 Using /lava-615224 at stage 0
79 11:42:07.083333 Fetching tests from https://github.com/kernelci/test-definitions.git
80 11:42:07.083478 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/0/tests/1_kselftest-arm64_qemu'
81 11:42:12.338536 Running '/usr/bin/git checkout kernelci.org
82 11:42:12.484256 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 11:42:12.485337 uuid=615224_1.1.3.5 testdef=None
84 11:42:12.485577 end: 1.1.3.5 git-repo-action (duration 00:00:05) [common]
86 11:42:12.486075 start: 1.1.3.6 test-overlay (timeout 00:02:55) [common]
87 11:42:12.487754 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 11:42:12.488397 start: 1.1.3.7 test-install-overlay (timeout 00:02:55) [common]
90 11:42:12.490705 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 11:42:12.491305 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:55) [common]
93 11:42:12.495960 runner path: /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/0/tests/1_kselftest-arm64_qemu test_uuid 615224_1.1.3.5
94 11:42:12.496171 BOARD='qemu_arm64-virt-gicv3'
95 11:42:12.496339 BRANCH='cip'
96 11:42:12.496488 SKIPFILE='/dev/null'
97 11:42:12.496633 SKIP_INSTALL='True'
98 11:42:12.496777 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig/gcc-10/kselftest.tar.xz'
99 11:42:12.496969 TST_CASENAME=''
100 11:42:12.497154 TST_CMDFILES='arm64'
101 11:42:12.497517 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 11:42:12.498042 Creating lava-test-runner.conf files
104 11:42:12.498198 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/615224/lava-overlay-27utecez/lava-615224/0 for stage 0
105 11:42:12.498417 - 0_timesync-off
106 11:42:12.498572 - 1_kselftest-arm64_qemu
107 11:42:12.498791 end: 1.1.3 test-definition (duration 00:00:05) [common]
108 11:42:12.498984 start: 1.1.4 compress-overlay (timeout 00:02:55) [common]
109 11:42:21.263618 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 11:42:21.263845 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:46) [common]
111 11:42:21.263954 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 11:42:21.264076 end: 1.1 lava-overlay (duration 00:00:14) [common]
113 11:42:21.264185 start: 1.2 apply-overlay-guest (timeout 00:02:46) [common]
114 11:42:21.264282 Overlay: /var/lib/lava/dispatcher/tmp/615224/compress-overlay-wjb9q9nt/overlay-1.1.4.tar.gz
115 11:42:36.972715 end: 1.2 apply-overlay-guest (duration 00:00:16) [common]
117 11:42:36.973484 start: 1.3 deploy-device-env (timeout 00:02:30) [common]
118 11:42:36.973652 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 11:42:36.973814 start: 1.4 download-retry (timeout 00:02:30) [common]
120 11:42:36.973974 start: 1.4.1 http-download (timeout 00:02:30) [common]
121 11:42:36.974264 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig/gcc-10/kernel/Image
122 11:42:36.974395 saving as /var/lib/lava/dispatcher/tmp/615224/deployimages-s0kp_k2_/kernel/Image
123 11:42:36.974512 total size: 37358080 (35MB)
124 11:42:36.974625 No compression specified
125 11:42:37.308589 progress 0% (0MB)
126 11:42:38.300665 progress 5% (1MB)
127 11:42:38.487313 progress 10% (3MB)
128 11:42:38.648028 progress 15% (5MB)
129 11:42:38.816903 progress 20% (7MB)
130 11:42:39.157479 progress 25% (8MB)
131 11:42:39.325917 progress 30% (10MB)
132 11:42:39.492689 progress 35% (12MB)
133 11:42:39.659155 progress 40% (14MB)
134 11:42:39.825469 progress 45% (16MB)
135 11:42:40.059459 progress 50% (17MB)
136 11:42:40.300067 progress 55% (19MB)
137 11:42:40.465822 progress 60% (21MB)
138 11:42:40.631220 progress 65% (23MB)
139 11:42:40.679188 progress 70% (24MB)
140 11:42:40.824839 progress 75% (26MB)
141 11:42:40.990940 progress 80% (28MB)
142 11:42:41.156133 progress 85% (30MB)
143 11:42:41.322339 progress 90% (32MB)
144 11:42:41.487250 progress 95% (33MB)
145 11:42:41.651919 progress 100% (35MB)
146 11:42:41.652188 35MB downloaded in 4.68s (7.62MB/s)
147 11:42:41.652461 end: 1.4.1 http-download (duration 00:00:05) [common]
149 11:42:41.652935 end: 1.4 download-retry (duration 00:00:05) [common]
150 11:42:41.653094 start: 1.5 download-retry (timeout 00:02:25) [common]
151 11:42:41.653248 start: 1.5.1 http-download (timeout 00:02:25) [common]
152 11:42:41.653470 Not decompressing ramdisk as can be used compressed.
153 11:42:41.653636 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/rootfs.cpio.gz
154 11:42:41.653767 saving as /var/lib/lava/dispatcher/tmp/615224/deployimages-s0kp_k2_/ramdisk/rootfs.cpio.gz
155 11:42:41.653889 total size: 88950412 (84MB)
156 11:42:41.654004 No compression specified
157 11:42:41.820972 progress 0% (0MB)
158 11:42:42.156696 progress 5% (4MB)
159 11:42:42.492858 progress 10% (8MB)
160 11:42:42.833151 progress 15% (12MB)
161 11:42:43.167978 progress 20% (16MB)
162 11:42:43.644835 progress 25% (21MB)
163 11:42:43.980730 progress 30% (25MB)
164 11:42:44.315250 progress 35% (29MB)
165 11:42:44.651775 progress 40% (33MB)
166 11:42:44.988225 progress 45% (38MB)
167 11:42:45.323377 progress 50% (42MB)
168 11:42:45.658001 progress 55% (46MB)
169 11:42:45.991390 progress 60% (50MB)
170 11:42:46.460953 progress 65% (55MB)
171 11:42:46.794927 progress 70% (59MB)
172 11:42:47.128062 progress 75% (63MB)
173 11:42:47.461696 progress 80% (67MB)
174 11:42:47.799408 progress 85% (72MB)
175 11:42:48.133546 progress 90% (76MB)
176 11:42:48.467912 progress 95% (80MB)
177 11:42:48.802508 progress 100% (84MB)
178 11:42:48.802878 84MB downloaded in 7.15s (11.87MB/s)
179 11:42:48.803139 end: 1.5.1 http-download (duration 00:00:07) [common]
181 11:42:48.803612 end: 1.5 download-retry (duration 00:00:07) [common]
182 11:42:48.803768 end: 1 deployimages (duration 00:00:42) [common]
183 11:42:48.803924 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 11:42:48.804083 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 11:42:48.804235 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 11:42:48.804577 Extending command line for qcow2 test overlay
187 11:42:48.805183 Pulling docker image
188 11:42:48.805339 cmd: ['docker', 'pull', 'kernelci/qemu']
189 11:42:48.805467 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 11:42:48.967314 >> Using default tag: latest
191 11:42:50.070482 >> latest: Pulling from kernelci/qemu
192 11:42:50.102582 >> Digest: sha256:ce67b4aa6149816ab5c39a34ebc77720cac0c3651072f2c36655342e38024d42
193 11:42:50.102766 >> Status: Image is up to date for kernelci/qemu:latest
194 11:42:50.135741 >> docker.io/kernelci/qemu:latest
195 11:42:50.139585 Returned 0 in 1 seconds
196 11:42:50.276727 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-615224-2.1.1-m890tun4wp --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/615224/deployimages-s0kp_k2_/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/615224/deployimages-s0kp_k2_/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/615224/apply-overlay-guest-ry9v22hw/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 11:42:50.418671 started a shell command
198 11:42:50.419192 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 11:42:50.419384 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 11:42:50.419559 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 11:42:50.419731 Setting prompt string to ['Linux version [0-9]']
202 11:42:50.419867 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 11:42:52.792849 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 11:42:52.793199 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40532-arm64-gcc-10-defconfig-gqkzw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:20:52 UTC 2023
205 11:42:52.793413 [ 0.000000] random: crng init done
206 11:42:52.793580 [ 0.000000] Machine model: linux,dummy-virt
207 11:42:52.793724 [ 0.000000] efi: UEFI not found.
208 11:42:52.793878 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
209 11:42:52.793994 [ 0.000000] printk: bootconsole [pl11] enabled
210 11:42:52.794381 start: 2.2.1 login-action (timeout 00:04:56) [common]
211 11:42:52.794526 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
212 11:42:52.794684 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
213 11:42:52.794844 Using line separator: #'\n'#
214 11:42:52.794969 No login prompt set.
215 11:42:52.795101 Parsing kernel messages
216 11:42:52.795220 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
217 11:42:52.795445 [login-action] Waiting for messages, (timeout 00:04:56)
218 11:42:52.797145 [ 0.000000] NUMA: No NUMA configuration found
219 11:42:52.797522 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 11:42:52.798179 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf2a00-0x7fdf4fff]
221 11:42:52.800189 [ 0.000000] Zone ranges:
222 11:42:52.801018 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 11:42:52.801254 [ 0.000000] DMA32 empty
224 11:42:52.801434 [ 0.000000] Normal empty
225 11:42:52.801558 [ 0.000000] Movable zone start for each node
226 11:42:52.801720 [ 0.000000] Early memory node ranges
227 11:42:52.801874 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 11:42:52.802047 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 11:42:52.816308 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 11:42:52.817333 [ 0.000000] psci: probing for conduit method from DT.
231 11:42:52.817707 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 11:42:52.817837 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 11:42:52.817972 [ 0.000000] psci: Trusted OS migration not required
234 11:42:52.818115 [ 0.000000] psci: SMC Calling Convention v1.0
235 11:42:52.820371 [ 0.000000] percpu: Embedded 20 pages/cpu s44840 r8192 d28888 u81920
236 11:42:52.820965 [ 0.000000] pcpu-alloc: s44840 r8192 d28888 u81920 alloc=20*4096
237 11:42:52.821114 [ 0.000000] pcpu-alloc: [0] 0
238 11:42:52.822445 [ 0.000000] Detected PIPT I-cache on CPU0
239 11:42:52.827809 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 11:42:52.828566 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 11:42:52.828754 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 11:42:52.829152 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 11:42:52.829292 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 11:42:52.829444 [ 0.000000] CPU features: detected: Spectre-v4
245 11:42:52.833144 [ 0.000000] alternatives: applying boot alternatives
246 11:42:52.836000 [ 0.000000] Fallback order for Node 0: 0
247 11:42:52.836137 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 11:42:52.836275 [ 0.000000] Policy zone: DMA
249 11:42:52.836641 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 11:42:52.839080 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 11:42:52.841525 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 11:42:52.841935 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 11:42:52.842315 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 11:42:52.851337 <6>[ 0.000000] Memory: 870696K/1048576K available (16192K kernel code, 3714K rwdata, 8860K rodata, 7552K init, 609K bss, 145112K reserved, 32768K cma-reserved)
255 11:42:52.857187 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 11:42:52.863785 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 11:42:52.863941 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 11:42:52.864098 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 11:42:52.864296 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 11:42:52.864490 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 11:42:52.864697 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 11:42:52.864877 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 11:42:52.865796 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 11:42:52.872248 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 11:42:52.872676 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 11:42:52.874306 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 11:42:52.874508 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 11:42:52.875180 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 11:42:52.879528 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 11:42:52.880283 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @42830000 (indirect, esz 8, psz 64K, shr 1)
271 11:42:52.880772 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @42840000 (flat, esz 8, psz 64K, shr 1)
272 11:42:52.881217 <6>[ 0.000000] GICv3: using LPI property table @0x0000000042850000
273 11:42:52.882049 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000042860000
274 11:42:52.883322 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 11:42:52.891222 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 11:42:52.891587 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 11:42:52.892223 <6>[ 0.000073] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 11:42:52.908911 <6>[ 0.014318] Console: colour dummy device 80x25
279 11:42:52.912902 <6>[ 0.020172] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 11:42:52.913079 <6>[ 0.021021] pid_max: default: 32768 minimum: 301
281 11:42:52.914301 <6>[ 0.022429] LSM: Security Framework initializing
282 11:42:52.918630 <6>[ 0.026479] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 11:42:52.918830 <6>[ 0.026741] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 11:42:52.950253 <4>[ 0.058090] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 11:42:52.955980 <6>[ 0.063812] cblist_init_generic: Setting adjustable number of callback queues.
286 11:42:52.956187 <6>[ 0.064193] cblist_init_generic: Setting shift to 0 and lim to 1.
287 11:42:52.956857 <6>[ 0.064747] cblist_init_generic: Setting shift to 0 and lim to 1.
288 11:42:52.958469 <6>[ 0.066376] rcu: Hierarchical SRCU implementation.
289 11:42:52.958619 <6>[ 0.066564] rcu: Max phase no-delay instances is 1000.
290 11:42:52.963065 <6>[ 0.071188] Platform MSI: its@8080000 domain created
291 11:42:52.964049 <6>[ 0.071752] PCI/MSI: /intc@8000000/its@8080000 domain created
292 11:42:52.964254 <6>[ 0.072323] fsl-mc MSI: its@8080000 domain created
293 11:42:52.967741 <6>[ 0.075637] EFI services will not be available.
294 11:42:52.968605 <6>[ 0.076469] smp: Bringing up secondary CPUs ...
295 11:42:52.969042 <6>[ 0.077050] smp: Brought up 1 node, 1 CPU
296 11:42:52.969242 <6>[ 0.077182] SMP: Total of 1 processors activated.
297 11:42:52.969477 <6>[ 0.077510] CPU features: detected: Branch Target Identification
298 11:42:52.969703 <6>[ 0.077725] CPU features: detected: 32-bit EL0 Support
299 11:42:52.969926 <6>[ 0.077880] CPU features: detected: 32-bit EL1 Support
300 11:42:52.970125 <6>[ 0.078031] CPU features: detected: ARMv8.4 Translation Table Level
301 11:42:52.970290 <6>[ 0.078226] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 11:42:52.970512 <6>[ 0.078481] CPU features: detected: Common not Private translations
303 11:42:52.970745 <6>[ 0.078645] CPU features: detected: CRC32 instructions
304 11:42:52.970944 <6>[ 0.078752] CPU features: detected: E0PD
305 11:42:52.971174 <6>[ 0.078903] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 11:42:52.971374 <6>[ 0.079045] CPU features: detected: RCpc load-acquire (LDAPR)
307 11:42:52.971554 <6>[ 0.079166] CPU features: detected: LSE atomic instructions
308 11:42:52.971701 <6>[ 0.079284] CPU features: detected: Privileged Access Never
309 11:42:52.971880 <6>[ 0.079390] CPU features: detected: RAS Extension Support
310 11:42:52.972018 <6>[ 0.079524] CPU features: detected: Random Number Generator
311 11:42:52.972192 <6>[ 0.079677] CPU features: detected: Speculation barrier (SB)
312 11:42:52.972358 <6>[ 0.079812] CPU features: detected: Stage-2 Force Write-Back
313 11:42:52.972558 <6>[ 0.079952] CPU features: detected: TLB range maintenance instructions
314 11:42:52.972752 <6>[ 0.080158] CPU features: detected: Scalable Matrix Extension
315 11:42:52.972886 <6>[ 0.080307] CPU features: detected: FA64
316 11:42:52.973003 <6>[ 0.080418] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 11:42:52.973118 <6>[ 0.080583] CPU features: detected: Scalable Vector Extension
318 11:42:52.983623 <6>[ 0.089071] SVE: maximum available vector length 256 bytes per vector
319 11:42:52.984097 <6>[ 0.092193] SVE: default vector length 64 bytes per vector
320 11:42:52.985883 <6>[ 0.093965] SME: minimum available vector length 16 bytes per vector
321 11:42:52.986332 <6>[ 0.094137] SME: maximum available vector length 256 bytes per vector
322 11:42:52.986475 <6>[ 0.094309] SME: default vector length 32 bytes per vector
323 11:42:52.986640 <6>[ 0.094712] CPU: All CPU(s) started at EL1
324 11:42:52.987068 <6>[ 0.095100] alternatives: applying system-wide alternatives
325 11:42:53.037823 <6>[ 0.145756] devtmpfs: initialized
326 11:42:53.057242 <6>[ 0.164832] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 11:42:53.057678 <6>[ 0.165664] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 11:42:53.063358 <6>[ 0.171242] pinctrl core: initialized pinctrl subsystem
329 11:42:53.073703 <6>[ 0.181827] DMI not present or invalid.
330 11:42:53.082714 <6>[ 0.190573] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 11:42:53.093896 <6>[ 0.201580] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 11:42:53.094601 <6>[ 0.202395] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 11:42:53.095063 <6>[ 0.202894] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 11:42:53.095503 <6>[ 0.203376] audit: initializing netlink subsys (disabled)
335 11:42:53.101130 <5>[ 0.209019] audit: type=2000 audit(0.172:1): state=initialized audit_enabled=0 res=1
336 11:42:53.103130 <6>[ 0.210921] thermal_sys: Registered thermal governor 'step_wise'
337 11:42:53.103573 <6>[ 0.210986] thermal_sys: Registered thermal governor 'power_allocator'
338 11:42:53.103722 <6>[ 0.211515] cpuidle: using governor menu
339 11:42:53.105261 <6>[ 0.213144] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
340 11:42:53.105672 <6>[ 0.213723] ASID allocator initialised with 65536 entries
341 11:42:53.111748 <6>[ 0.219642] Serial: AMBA PL011 UART driver
342 11:42:53.159419 <6>[ 0.267239] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
343 11:42:53.161061 <6>[ 0.268838] printk: console [ttyAMA0] enabled
344 11:42:53.161231 <6>[ 0.268838] printk: console [ttyAMA0] enabled
345 11:42:53.161408 <6>[ 0.269319] printk: bootconsole [pl11] disabled
346 11:42:53.161537 <6>[ 0.269319] printk: bootconsole [pl11] disabled
347 11:42:53.171636 <6>[ 0.279770] KASLR enabled
348 11:42:53.203981 <6>[ 0.311740] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
349 11:42:53.204157 <6>[ 0.311970] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
350 11:42:53.204365 <6>[ 0.312161] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
351 11:42:53.204497 <6>[ 0.312342] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
352 11:42:53.204663 <6>[ 0.312509] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
353 11:42:53.204821 <6>[ 0.312684] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
354 11:42:53.205018 <6>[ 0.312888] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
355 11:42:53.205144 <6>[ 0.313051] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
356 11:42:53.214332 <6>[ 0.322439] ACPI: Interpreter disabled.
357 11:42:53.222831 <6>[ 0.330597] iommu: Default domain type: Translated
358 11:42:53.223387 <6>[ 0.330772] iommu: DMA domain TLB invalidation policy: strict mode
359 11:42:53.224449 <5>[ 0.332323] SCSI subsystem initialized
360 11:42:53.225207 <7>[ 0.333125] libata version 3.00 loaded.
361 11:42:53.226844 <6>[ 0.334664] usbcore: registered new interface driver usbfs
362 11:42:53.227096 <6>[ 0.335077] usbcore: registered new interface driver hub
363 11:42:53.227339 <6>[ 0.335398] usbcore: registered new device driver usb
364 11:42:53.230083 <6>[ 0.338185] pps_core: LinuxPPS API ver. 1 registered
365 11:42:53.230544 <6>[ 0.338330] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
366 11:42:53.230734 <6>[ 0.338793] PTP clock support registered
367 11:42:53.231497 <6>[ 0.339387] EDAC MC: Ver: 3.0.0
368 11:42:53.236785 <6>[ 0.344672] FPGA manager framework
369 11:42:53.237531 <6>[ 0.345448] Advanced Linux Sound Architecture Driver Initialized.
370 11:42:53.246070 <6>[ 0.354183] vgaarb: loaded
371 11:42:53.249958 <6>[ 0.357837] clocksource: Switched to clocksource arch_sys_counter
372 11:42:53.251147 <5>[ 0.358996] VFS: Disk quotas dquot_6.6.0
373 11:42:53.251372 <6>[ 0.359298] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
374 11:42:53.254691 <6>[ 0.362806] pnp: PnP ACPI: disabled
375 11:42:53.272163 <6>[ 0.380264] NET: Registered PF_INET protocol family
376 11:42:53.274522 <6>[ 0.382387] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
377 11:42:53.279384 <6>[ 0.387193] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
378 11:42:53.279602 <6>[ 0.387483] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
379 11:42:53.279842 <6>[ 0.387783] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
380 11:42:53.280297 <6>[ 0.388229] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
381 11:42:53.280805 <6>[ 0.388813] TCP: Hash tables configured (established 8192 bind 8192)
382 11:42:53.282172 <6>[ 0.390077] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
383 11:42:53.282637 <6>[ 0.390463] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
384 11:42:53.283670 <6>[ 0.391588] NET: Registered PF_UNIX/PF_LOCAL protocol family
385 11:42:53.285913 <6>[ 0.393764] RPC: Registered named UNIX socket transport module.
386 11:42:53.286023 <6>[ 0.393997] RPC: Registered udp transport module.
387 11:42:53.286134 <6>[ 0.394144] RPC: Registered tcp transport module.
388 11:42:53.286531 <6>[ 0.394340] RPC: Registered tcp NFSv4.1 backchannel transport module.
389 11:42:53.286654 <6>[ 0.394702] PCI: CLS 0 bytes, default 64
390 11:42:53.291056 <6>[ 0.399172] Unpacking initramfs...
391 11:42:53.298156 <6>[ 0.406018] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
392 11:42:53.298859 <6>[ 0.406767] kvm [1]: HYP mode not available
393 11:42:53.307804 <5>[ 0.415676] Initialise system trusted keyrings
394 11:42:53.314073 <6>[ 0.421941] workingset: timestamp_bits=42 max_order=18 bucket_order=0
395 11:42:53.345386 <6>[ 0.453265] squashfs: version 4.0 (2009/01/31) Phillip Lougher
396 11:42:53.355068 <5>[ 0.462964] NFS: Registering the id_resolver key type
397 11:42:53.355251 <5>[ 0.463366] Key type id_resolver registered
398 11:42:53.355424 <5>[ 0.463537] Key type id_legacy registered
399 11:42:53.356187 <6>[ 0.464017] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
400 11:42:53.356367 <6>[ 0.464303] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
401 11:42:53.357250 <6>[ 0.465146] 9p: Installing v9fs 9p2000 file system support
402 11:42:53.426034 <5>[ 0.534123] Key type asymmetric registered
403 11:42:53.426461 <5>[ 0.534317] Asymmetric key parser 'x509' registered
404 11:42:53.426921 <6>[ 0.534690] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
405 11:42:53.427101 <6>[ 0.535051] io scheduler mq-deadline registered
406 11:42:53.427255 <6>[ 0.535267] io scheduler kyber registered
407 11:42:53.486574 <6>[ 0.594181] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
408 11:42:53.496631 <6>[ 0.604451] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
409 11:42:53.497583 <6>[ 0.605355] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
410 11:42:53.506359 <6>[ 0.614169] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
411 11:42:53.506573 <6>[ 0.614495] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
412 11:42:53.507304 <4>[ 0.615223] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
413 11:42:53.508485 <6>[ 0.616097] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
414 11:42:53.513868 <6>[ 0.621751] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
415 11:42:53.514069 <6>[ 0.622176] pci_bus 0000:00: root bus resource [bus 00-ff]
416 11:42:53.514480 <6>[ 0.622387] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
417 11:42:53.514656 <6>[ 0.622624] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
418 11:42:53.514836 <6>[ 0.622826] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
419 11:42:53.516453 <6>[ 0.624342] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
420 11:42:53.523919 <6>[ 0.631752] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
421 11:42:53.524138 <6>[ 0.632139] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
422 11:42:53.524291 <6>[ 0.632339] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
423 11:42:53.524724 <6>[ 0.632606] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
424 11:42:53.524919 <6>[ 0.632911] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
425 11:42:53.529735 <6>[ 0.633530] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
426 11:42:53.529900 <6>[ 0.637779] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
427 11:42:53.530091 <6>[ 0.637978] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
428 11:42:53.530262 <6>[ 0.638198] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
429 11:42:53.532986 <6>[ 0.640893] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
430 11:42:53.533449 <6>[ 0.641393] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
431 11:42:53.537861 <6>[ 0.645752] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
432 11:42:53.538060 <6>[ 0.646049] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
433 11:42:53.538502 <6>[ 0.646303] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
434 11:42:53.538636 <6>[ 0.646513] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
435 11:42:53.538775 <6>[ 0.646719] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
436 11:42:53.548632 <6>[ 0.656764] EINJ: ACPI disabled.
437 11:42:53.634232 <6>[ 0.742046] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
438 11:42:53.636918 <6>[ 0.744818] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
439 11:42:53.666941 <6>[ 0.774764] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
440 11:42:53.681812 <6>[ 0.785526] SuperH (H)SCI(F) driver initialized
441 11:42:53.683209 <6>[ 0.791088] msm_serial: driver initialized
442 11:42:53.691536 <4>[ 0.799408] cacheinfo: Unable to detect cache hierarchy for CPU 0
443 11:42:53.720378 <6>[ 0.828484] loop: module loaded
444 11:42:53.721571 <6>[ 0.829454] virtio_blk virtio1: 1/0/0 default/read/poll queues
445 11:42:53.742214 <5>[ 0.850002] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
446 11:42:53.767858 <6>[ 0.875953] megasas: 07.719.03.00-rc1
447 11:42:53.777693 <5>[ 0.885493] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
448 11:42:53.783214 <6>[ 0.891059] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
449 11:42:53.783657 <6>[ 0.891720] Intel/Sharp Extended Query Table at 0x0031
450 11:42:53.784578 <6>[ 0.892477] Using buffer write method
451 11:42:53.784978 <7>[ 0.892933] erase region 0: offset=0x0,size=0x40000,blocks=256
452 11:42:53.785422 <5>[ 0.893285] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
453 11:42:53.790323 <6>[ 0.898071] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
454 11:42:53.790607 <6>[ 0.898401] Intel/Sharp Extended Query Table at 0x0031
455 11:42:53.791058 <6>[ 0.899046] Using buffer write method
456 11:42:53.791283 <7>[ 0.899200] erase region 0: offset=0x0,size=0x40000,blocks=256
457 11:42:53.791486 <5>[ 0.899432] Concatenating MTD devices:
458 11:42:53.791644 <5>[ 0.899569] (0): \"0.flash\"
459 11:42:53.791789 <5>[ 0.899671] (1): \"0.flash\"
460 11:42:53.791909 <5>[ 0.899772] into device \"0.flash\"
461 11:42:58.322222 <6>[ 5.430099] Freeing initrd memory: 86864K
462 11:42:58.431150 <6>[ 5.539066] tun: Universal TUN/TAP device driver, 1.6
463 11:42:58.440697 <6>[ 5.548574] thunder_xcv, ver 1.0
464 11:42:58.440950 <6>[ 5.548768] thunder_bgx, ver 1.0
465 11:42:58.441370 <6>[ 5.548991] nicpf, ver 1.0
466 11:42:58.444379 <6>[ 5.552236] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
467 11:42:58.444494 <6>[ 5.552400] hns3: Copyright (c) 2017 Huawei Corporation.
468 11:42:58.444830 <6>[ 5.552879] hclge is initializing
469 11:42:58.445174 <6>[ 5.553174] e1000: Intel(R) PRO/1000 Network Driver
470 11:42:58.445304 <6>[ 5.553335] e1000: Copyright (c) 1999-2006 Intel Corporation.
471 11:42:58.445733 <6>[ 5.553799] e1000e: Intel(R) PRO/1000 Network Driver
472 11:42:58.445957 <6>[ 5.553965] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
473 11:42:58.446424 <6>[ 5.554290] igb: Intel(R) Gigabit Ethernet Network Driver
474 11:42:58.446631 <6>[ 5.554420] igb: Copyright (c) 2007-2014 Intel Corporation.
475 11:42:58.446824 <6>[ 5.554708] igbvf: Intel(R) Gigabit Virtual Function Network Driver
476 11:42:58.446977 <6>[ 5.554944] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
477 11:42:58.447799 <6>[ 5.555929] sky2: driver version 1.30
478 11:42:58.450889 <6>[ 5.558811] VFIO - User Level meta-driver version: 0.3
479 11:42:58.459516 <6>[ 5.567406] usbcore: registered new interface driver usb-storage
480 11:42:58.468101 <6>[ 5.576038] rtc-pl031 9010000.pl031: registered as rtc0
481 11:42:58.469130 <6>[ 5.576709] rtc-pl031 9010000.pl031: setting system clock to 2023-06-15T11:42:58 UTC (1686829378)
482 11:42:58.470715 <6>[ 5.578794] i2c_dev: i2c /dev entries driver
483 11:42:58.485747 <6>[ 5.593630] sdhci: Secure Digital Host Controller Interface driver
484 11:42:58.485922 <6>[ 5.593767] sdhci: Copyright(c) Pierre Ossman
485 11:42:58.487507 <6>[ 5.595526] Synopsys Designware Multimedia Card Interface Driver
486 11:42:58.489884 <6>[ 5.597826] sdhci-pltfm: SDHCI platform and OF driver helper
487 11:42:58.494295 <6>[ 5.602346] ledtrig-cpu: registered to indicate activity on CPUs
488 11:42:58.499764 <6>[ 5.607591] usbcore: registered new interface driver usbhid
489 11:42:58.499932 <6>[ 5.607778] usbhid: USB HID core driver
490 11:42:58.515201 <6>[ 5.623132] NET: Registered PF_PACKET protocol family
491 11:42:58.516068 <6>[ 5.624165] 9pnet: Installing 9P2000 support
492 11:42:58.516514 <5>[ 5.624500] Key type dns_resolver registered
493 11:42:58.517721 <6>[ 5.625798] registered taskstats version 1
494 11:42:58.518173 <5>[ 5.626161] Loading compiled-in X.509 certificates
495 11:42:58.539259 <6>[ 5.647051] input: gpio-keys as /devices/platform/gpio-keys/input/input0
496 11:42:58.545989 <6>[ 5.654081] ALSA device list:
497 11:42:58.546481 <6>[ 5.654240] No soundcards found.
498 11:42:58.548969 <6>[ 5.656798] uart-pl011 9000000.pl011: no DMA platform data
499 11:42:58.602422 <6>[ 5.710373] Freeing unused kernel memory: 7552K
500 11:42:58.603443 <6>[ 5.711251] Run /init as init process
501 11:42:58.603638 <7>[ 5.711409] with arguments:
502 11:42:58.603784 <7>[ 5.711513] /init
503 11:42:58.603901 <7>[ 5.711593] verbose
504 11:42:58.604040 <7>[ 5.711686] with environment:
505 11:42:58.604158 <7>[ 5.711797] HOME=/
506 11:42:58.604270 <7>[ 5.711893] TERM=linux
507 11:42:58.732646 <30>[ 5.840228] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
508 11:42:58.733565 <31>[ 5.841422] systemd[1]: No virtualization found in DMI
509 11:42:58.734880 <31>[ 5.842621] systemd[1]: UML virtualization not found in /proc/cpuinfo.
510 11:42:58.735070 <31>[ 5.842923] systemd[1]: No virtualization found in CPUID
511 11:42:58.735223 <31>[ 5.843166] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
512 11:42:58.736276 <31>[ 5.844183] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
513 11:42:58.736508 <31>[ 5.844555] systemd[1]: Found VM virtualization qemu
514 11:42:58.736702 <30>[ 5.844777] systemd[1]: Detected virtualization qemu.
515 11:42:58.737104 <30>[ 5.845090] systemd[1]: Detected architecture arm64.
516 11:42:58.737566 <31>[ 5.845418] systemd[1]: Detected initialized system, this is not the first boot.
517 11:42:58.741385
518 11:42:58.742041 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
519 11:42:58.742176
520 11:42:58.743862 <30>[ 5.851755] systemd[1]: Set hostname to <debian-bullseye-arm64>.
521 11:42:58.762292 <31>[ 5.870120] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
522 11:42:58.763306 <31>[ 5.871241] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
523 11:42:58.763714 <31>[ 5.871765] systemd[1]: Successfully brought loopback interface up
524 11:42:58.768336 <31>[ 5.876174] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
525 11:42:58.779746 <31>[ 5.887628] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
526 11:42:58.779889 <31>[ 5.887903] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
527 11:42:58.819613 <31>[ 5.927338] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
528 11:42:58.820905 <31>[ 5.928729] systemd[1]: Controller 'cpu' supported: yes
529 11:42:58.821098 <31>[ 5.928943] systemd[1]: Controller 'cpuacct' supported: no
530 11:42:58.821284 <31>[ 5.929130] systemd[1]: Controller 'cpuset' supported: yes
531 11:42:58.821434 <31>[ 5.929314] systemd[1]: Controller 'io' supported: yes
532 11:42:58.821574 <31>[ 5.929499] systemd[1]: Controller 'blkio' supported: no
533 11:42:58.822024 <31>[ 5.929919] systemd[1]: Controller 'memory' supported: yes
534 11:42:58.822229 <31>[ 5.930128] systemd[1]: Controller 'devices' supported: no
535 11:42:58.822390 <31>[ 5.930312] systemd[1]: Controller 'pids' supported: yes
536 11:42:58.822565 <31>[ 5.930487] systemd[1]: Controller 'bpf-firewall' supported: yes
537 11:42:58.822728 <31>[ 5.930680] systemd[1]: Controller 'bpf-devices' supported: yes
538 11:42:58.823901 <31>[ 5.931790] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
539 11:42:58.824098 <31>[ 5.932132] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
540 11:42:58.824787 <31>[ 5.932655] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
541 11:42:58.832335 <31>[ 5.940088] systemd[1]: Enabling (yes) showing of status (commandline).
542 11:42:58.839703 <31>[ 5.947579] systemd[1]: Successfully forked off '(sd-executor)' as PID 94.
543 11:42:58.848619 <31>[ 5.956514] systemd[94]: Successfully forked off '(direxec)' as PID 95.
544 11:42:58.850787 <31>[ 5.958666] systemd[94]: Successfully forked off '(direxec)' as PID 96.
545 11:42:58.852640 <31>[ 5.960530] systemd[94]: Successfully forked off '(direxec)' as PID 97.
546 11:42:58.866764 <31>[ 5.974833] systemd[94]: Successfully forked off '(direxec)' as PID 98.
547 11:42:58.869593 <31>[ 5.977433] systemd[94]: Successfully forked off '(direxec)' as PID 99.
548 11:42:59.016232 <31>[ 6.124085] systemd-bless-boot-generator[95]: Skipping generator, not an EFI boot.
549 11:42:59.026982 <31>[ 6.134874] systemd-fstab-generator[96]: Parsing /etc/fstab...
550 11:42:59.028927 <31>[ 6.136828] systemd-fstab-generator[96]: Found entry what=/dev/disk/by-uuid/e8944c3c-78ff-4c74-a97d-ff60ed2bed2f where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
551 11:42:59.030191 <31>[ 6.138017] systemd-getty-generator[97]: Automatically adding serial getty for /dev/ttyAMA0.
552 11:42:59.031481 <31>[ 6.139301] systemd-getty-generator[97]: SELinux enabled state cached to: disabled
553 11:42:59.040694 <31>[ 6.148619] systemd[94]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
554 11:42:59.042148 <31>[ 6.149942] systemd[94]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
555 11:42:59.044258 <31>[ 6.151939] systemd-fstab-generator[96]: Checking was requested for /dev/disk/by-uuid/e8944c3c-78ff-4c74-a97d-ff60ed2bed2f, but fsck.ext4 does not exist.
556 11:42:59.050248 <31>[ 6.158081] systemd[94]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
557 11:42:59.050472 <31>[ 6.158416] systemd[94]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
558 11:42:59.051887 <31>[ 6.159769] systemd-fstab-generator[96]: SELinux enabled state cached to: disabled
559 11:42:59.056907 <31>[ 6.164800] systemd[94]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
560 11:42:59.059815 <31>[ 6.167669] systemd[1]: (sd-executor) succeeded.
561 11:42:59.061282 <31>[ 6.169098] systemd[1]: Looking for unit files in (higher priority first):
562 11:42:59.061465 <31>[ 6.169308] systemd[1]: /etc/systemd/system.control
563 11:42:59.061622 <31>[ 6.169449] systemd[1]: /run/systemd/system.control
564 11:42:59.062056 <31>[ 6.170044] systemd[1]: /run/systemd/transient
565 11:42:59.062249 <31>[ 6.170201] systemd[1]: /run/systemd/generator.early
566 11:42:59.062402 <31>[ 6.170361] systemd[1]: /etc/systemd/system
567 11:42:59.062575 <31>[ 6.170491] systemd[1]: /etc/systemd/system.attached
568 11:42:59.062716 <31>[ 6.170644] systemd[1]: /run/systemd/system
569 11:42:59.062860 <31>[ 6.170762] systemd[1]: /run/systemd/system.attached
570 11:42:59.062993 <31>[ 6.170906] systemd[1]: /run/systemd/generator
571 11:42:59.063173 <31>[ 6.171061] systemd[1]: /usr/local/lib/systemd/system
572 11:42:59.063334 <31>[ 6.171223] systemd[1]: /lib/systemd/system
573 11:42:59.063490 <31>[ 6.171372] systemd[1]: /usr/lib/systemd/system
574 11:42:59.063612 <31>[ 6.171533] systemd[1]: /run/systemd/generator.late
575 11:42:59.098284 <31>[ 6.206081] systemd[1]: Modification times have changed, need to update cache.
576 11:42:59.099856 <31>[ 6.207606] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
577 11:42:59.100649 <31>[ 6.208466] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
578 11:42:59.101582 <31>[ 6.209228] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
579 11:42:59.102841 <31>[ 6.210734] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
580 11:42:59.104109 <31>[ 6.211995] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/autovt@.service → getty@.service
581 11:42:59.104323 <31>[ 6.212293] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
582 11:42:59.104829 <31>[ 6.212589] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub@.service
583 11:42:59.105037 <31>[ 6.212910] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
584 11:42:59.105237 <31>[ 6.213205] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
585 11:42:59.106003 <31>[ 6.213553] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
586 11:42:59.106238 <31>[ 6.214213] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
587 11:42:59.106685 <31>[ 6.214555] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
588 11:42:59.107418 <31>[ 6.215267] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
589 11:42:59.107596 <31>[ 6.215568] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
590 11:42:59.108092 <31>[ 6.215839] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
591 11:42:59.108268 <31>[ 6.216104] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sysinit.target
592 11:42:59.108434 <31>[ 6.216370] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
593 11:42:59.108746 <31>[ 6.216667] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
594 11:42:59.109557 <31>[ 6.217287] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
595 11:42:59.110431 <31>[ 6.218245] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
596 11:42:59.110634 <31>[ 6.218612] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/swap.target
597 11:42:59.111185 <31>[ 6.218923] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
598 11:42:59.111386 <31>[ 6.219284] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
599 11:42:59.111687 <31>[ 6.219616] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
600 11:42:59.112190 <31>[ 6.219970] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
601 11:42:59.112410 <31>[ 6.220369] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
602 11:42:59.113265 <31>[ 6.220959] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
603 11:42:59.113466 <31>[ 6.221257] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
604 11:42:59.113941 <31>[ 6.221888] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
605 11:42:59.114498 <31>[ 6.222207] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
606 11:42:59.114693 <31>[ 6.222559] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
607 11:42:59.115221 <31>[ 6.222854] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
608 11:42:59.115376 <31>[ 6.223201] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
609 11:42:59.115856 <31>[ 6.223865] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel6.target → reboot.target
610 11:42:59.116884 <31>[ 6.224712] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/ctrl-alt-del.target → reboot.target
611 11:42:59.117105 <31>[ 6.225003] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
612 11:42:59.117705 <31>[ 6.225322] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
613 11:42:59.118162 <31>[ 6.225971] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rc-local.service
614 11:42:59.118523 <31>[ 6.226294] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
615 11:42:59.118705 <31>[ 6.226645] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
616 11:42:59.119083 <31>[ 6.227013] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
617 11:42:59.119664 <31>[ 6.227339] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
618 11:42:59.119882 <31>[ 6.227685] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
619 11:42:59.120418 <31>[ 6.228011] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
620 11:42:59.120628 <31>[ 6.228356] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
621 11:42:59.120890 <31>[ 6.228679] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.mount
622 11:42:59.121496 <31>[ 6.229065] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs.target
623 11:42:59.121734 <31>[ 6.229456] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hostnamed.service
624 11:42:59.122548 <31>[ 6.230287] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-remount-fs.service
625 11:42:59.123072 <31>[ 6.230841] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/final.target
626 11:42:59.123314 <31>[ 6.231207] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
627 11:42:59.123867 <31>[ 6.231603] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.service
628 11:42:59.124344 <31>[ 6.232070] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
629 11:42:59.125515 <31>[ 6.233188] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
630 11:42:59.126298 <31>[ 6.234155] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
631 11:42:59.126857 <31>[ 6.234663] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
632 11:42:59.127086 <31>[ 6.234982] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
633 11:42:59.127666 <31>[ 6.235319] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs.target
634 11:42:59.127883 <31>[ 6.235686] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
635 11:42:59.128154 <31>[ 6.236101] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
636 11:42:59.128465 <31>[ 6.236450] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
637 11:42:59.129321 <31>[ 6.237105] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel0.target → poweroff.target
638 11:42:59.129577 <31>[ 6.237473] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
639 11:42:59.132619 <31>[ 6.238158] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/debug-shell.service
640 11:42:59.132815 <31>[ 6.238533] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
641 11:42:59.133008 <31>[ 6.238858] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
642 11:42:59.133154 <31>[ 6.239484] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
643 11:42:59.133452 <31>[ 6.239797] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
644 11:42:59.133586 <31>[ 6.240092] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
645 11:42:59.133741 <31>[ 6.240330] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
646 11:42:59.134223 <31>[ 6.240620] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
647 11:42:59.134418 <31>[ 6.240984] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
648 11:42:59.134554 <31>[ 6.241362] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
649 11:42:59.134671 <31>[ 6.241915] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
650 11:42:59.134816 <31>[ 6.242230] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
651 11:42:59.134981 <31>[ 6.242523] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
652 11:42:59.135156 <31>[ 6.243066] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
653 11:42:59.135357 <31>[ 6.243349] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
654 11:42:59.135870 <31>[ 6.243676] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_fail@.service
655 11:42:59.136647 <31>[ 6.244341] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
656 11:42:59.136871 <31>[ 6.244795] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
657 11:42:59.137913 <31>[ 6.245780] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
658 11:42:59.138406 <31>[ 6.246230] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-localed.service
659 11:42:59.139248 <31>[ 6.246948] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
660 11:42:59.139436 <31>[ 6.247251] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
661 11:42:59.139997 <31>[ 6.247607] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.path
662 11:42:59.140212 <31>[ 6.247965] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.service
663 11:42:59.140444 <31>[ 6.248274] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/shutdown.target
664 11:42:59.140653 <31>[ 6.248589] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
665 11:42:59.141231 <31>[ 6.248897] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-check-no-failures.service
666 11:42:59.141398 <31>[ 6.249260] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
667 11:42:59.141832 <31>[ 6.249802] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
668 11:42:59.142341 <31>[ 6.250136] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
669 11:42:59.142549 <31>[ 6.250420] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
670 11:42:59.142720 <31>[ 6.250682] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
671 11:42:59.143267 <31>[ 6.251003] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-exit.service
672 11:42:59.143449 <31>[ 6.251334] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsckd.service
673 11:42:59.143962 <31>[ 6.251728] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
674 11:42:59.144183 <31>[ 6.252005] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
675 11:42:59.144399 <31>[ 6.252264] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
676 11:42:59.144593 <31>[ 6.252542] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
677 11:42:59.144866 <31>[ 6.252822] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
678 11:42:59.145404 <31>[ 6.253172] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
679 11:42:59.145601 <31>[ 6.253480] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
680 11:42:59.146580 <31>[ 6.254309] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
681 11:42:59.146772 <31>[ 6.254661] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.service
682 11:42:59.147259 <31>[ 6.255089] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
683 11:42:59.147459 <31>[ 6.255401] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
684 11:42:59.147672 <31>[ 6.255649] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-sync.target
685 11:42:59.148177 <31>[ 6.255936] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-user-lookup.target
686 11:42:59.148379 <31>[ 6.256214] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
687 11:42:59.148586 <31>[ 6.256512] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
688 11:42:59.148828 <31>[ 6.256814] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.socket
689 11:42:59.149310 <31>[ 6.257116] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
690 11:42:59.149689 <31>[ 6.257414] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
691 11:42:59.150292 <31>[ 6.258108] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
692 11:42:59.150653 <31>[ 6.258450] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
693 11:42:59.151023 <31>[ 6.258826] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/first-boot-complete.target
694 11:42:59.151462 <31>[ 6.259209] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
695 11:42:59.151672 <31>[ 6.259578] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
696 11:42:59.151920 <31>[ 6.259893] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
697 11:42:59.152491 <31>[ 6.260219] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
698 11:42:59.152694 <31>[ 6.260530] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
699 11:42:59.153493 <31>[ 6.261262] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
700 11:42:59.154027 <31>[ 6.261851] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
701 11:42:59.154231 <31>[ 6.262175] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-mqueue.mount
702 11:42:59.154771 <31>[ 6.262473] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
703 11:42:59.154950 <31>[ 6.262846] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
704 11:42:59.155442 <31>[ 6.263166] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
705 11:42:59.155644 <31>[ 6.263462] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-config.mount
706 11:42:59.155821 <31>[ 6.263747] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
707 11:42:59.155997 <31>[ 6.264010] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
708 11:42:59.156550 <31>[ 6.264278] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
709 11:42:59.156741 <31>[ 6.264562] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/container-getty@.service
710 11:42:59.156977 <31>[ 6.264898] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
711 11:42:59.157233 <31>[ 6.265218] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
712 11:42:59.157751 <31>[ 6.265520] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-trigger.service
713 11:42:59.158176 <31>[ 6.266089] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
714 11:42:59.158728 <31>[ 6.266431] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
715 11:42:59.158961 <31>[ 6.266796] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
716 11:42:59.159739 <31>[ 6.267493] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
717 11:42:59.160115 <31>[ 6.267839] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
718 11:42:59.160235 <31>[ 6.268204] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
719 11:42:59.160613 <31>[ 6.268553] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
720 11:42:59.161046 <31>[ 6.268933] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
721 11:42:59.161558 <31>[ 6.269256] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/smartcard.target
722 11:42:59.162204 <31>[ 6.269914] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
723 11:42:59.162411 <31>[ 6.270294] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
724 11:42:59.162897 <31>[ 6.270613] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
725 11:42:59.163065 <31>[ 6.270932] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
726 11:42:59.163264 <31>[ 6.271269] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
727 11:42:59.557410 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
728 11:42:59.561846 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
729 11:42:59.564893 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
730 11:42:59.568153 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
731 11:42:59.571730 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
732 11:42:59.573042 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
733 11:42:59.575577 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
734 11:42:59.576533 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
735 11:42:59.577244 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
736 11:42:59.578202 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
737 11:42:59.578931 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
738 11:42:59.582751 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
739 11:42:59.586730 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
740 11:42:59.589204 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
741 11:42:59.591546 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
742 11:42:59.594193 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
743 11:42:59.596335 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
744 11:42:59.598538 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
745 11:42:59.623532 Mounting [0;1;39mHuge Pages File System[0m...
746 11:42:59.642907 Mounting [0;1;39mPOSIX Message Queue File System[0m...
747 11:42:59.678740 Mounting [0;1;39mKernel Debug File System[0m...
748 11:42:59.731607 Starting [0;1;39mLoad Kernel Module configfs[0m...
749 11:42:59.775120 Starting [0;1;39mLoad Kernel Module drm[0m...
750 11:42:59.831309 Starting [0;1;39mJournal Service[0m...
751 11:42:59.863337 Starting [0;1;39mLoad Kernel Modules[0m...
752 11:42:59.903151 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
753 11:42:59.939452 Starting [0;1;39mColdplug All udev Devices[0m...
754 11:43:00.039816 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
755 11:43:00.047679 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
756 11:43:00.067244 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
757 11:43:00.110916 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
758 11:43:00.159752 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
759 11:43:00.178744 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
760 11:43:00.251000 Mounting [0;1;39mKernel Configuration File System[0m...
761 11:43:00.371002 Starting [0;1;39mApply Kernel Variables[0m...
762 11:43:00.419756 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
763 11:43:00.471526 <47>[ 7.579296] systemd-journald[105]: SELinux enabled state cached to: disabled
764 11:43:00.472520 <47>[ 7.580582] systemd-journald[105]: Auditing in kernel turned off.
765 11:43:00.510756 <47>[ 7.618575] systemd-journald[105]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
766 11:43:00.562967 <47>[ 7.670669] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
767 11:43:00.565203 <47>[ 7.673094] systemd-journald[105]: Fixed min_use=3.8M max_use=19.4M max_size=2.4M min_size=512.0K keep_free=9.7M n_max_files=100
768 11:43:00.570523 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
769 11:43:00.574239 See 'systemctl status systemd-remount-fs.service' for details.
770 11:43:00.580581 <47>[ 7.688407] systemd-journald[105]: Reserving 333 entries in field hash table.
771 11:43:00.615091 Starting [0;1;39mLoad/Save Random Seed[0m...
772 11:43:00.616232 <47>[ 7.724265] systemd-journald[105]: Reserving 4437 entries in data hash table.
773 11:43:00.626214 <47>[ 7.734282] systemd-journald[105]: Vacuuming...
774 11:43:00.627145 <47>[ 7.734969] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
775 11:43:00.627604 <47>[ 7.735532] systemd-journald[105]: Flushing /dev/kmsg...
776 11:43:00.671586 Starting [0;1;39mCreate System Users[0m...
777 11:43:00.699641 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
778 11:43:00.799741 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
779 11:43:00.987886 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
780 11:43:01.019305 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
781 11:43:01.121370 <47>[ 8.229151] systemd-journald[105]: systemd-journald running as PID 105 for the system.
782 11:43:01.135846 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
783 11:43:01.146160 <47>[ 8.253985] systemd-journald[105]: Sent READY=1 notification.
784 11:43:01.146788 <47>[ 8.254433] systemd-journald[105]: Sent WATCHDOG=1 notification.
785 11:43:01.180729 <47>[ 8.288645] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
786 11:43:01.191222 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
787 11:43:01.204748 <47>[ 8.312490] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
788 11:43:01.223627 <47>[ 8.331570] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
789 11:43:01.243329 <47>[ 8.351020] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
790 11:43:01.258930 <47>[ 8.366932] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
791 11:43:01.267787 <47>[ 8.375764] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
792 11:43:01.282068 <47>[ 8.389862] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
793 11:43:01.294906 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
794 11:43:01.297101 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
795 11:43:01.302938 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
796 11:43:01.305865 <47>[ 8.413537] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
797 11:43:01.320396 <47>[ 8.428323] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
798 11:43:01.334961 <47>[ 8.442694] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
799 11:43:01.337381 <47>[ 8.445272] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
800 11:43:01.350702 <47>[ 8.458521] systemd-journald[105]: n/a: New incoming connection.
801 11:43:01.351333 <47>[ 8.459280] systemd-journald[105]: varlink-18: varlink: setting state idle-server
802 11:43:01.368872 <47>[ 8.476701] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
803 11:43:01.381835 <47>[ 8.489466] systemd-journald[105]: varlink-18: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
804 11:43:01.387822 <47>[ 8.495669] systemd-journald[105]: varlink-18: varlink: changing state idle-server → processing-method
805 11:43:01.388241 <46>[ 8.496115] systemd-journald[105]: Received client request to flush runtime journal.
806 11:43:01.388580 <47>[ 8.496531] systemd-journald[105]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
807 11:43:01.389208 <47>[ 8.497324] systemd-journald[105]: Vacuuming...
808 11:43:01.403797 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
809 11:43:01.406229 <47>[ 8.514088] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
810 11:43:01.407534 <47>[ 8.515442] systemd-journald[105]: varlink-18: Sending message: {\"parameters\":{}}
811 11:43:01.407877 <47>[ 8.515706] systemd-journald[105]: varlink-18: varlink: changing state processing-method → processed-method
812 11:43:01.408207 <47>[ 8.516074] systemd-journald[105]: varlink-18: varlink: changing state processed-method → idle-server
813 11:43:01.426505 <47>[ 8.534263] systemd-journald[105]: varlink-18: varlink: changing state idle-server → pending-disconnect
814 11:43:01.426721 <47>[ 8.534644] systemd-journald[105]: varlink-18: varlink: changing state pending-disconnect → processing-disconnect
815 11:43:01.427019 <47>[ 8.534968] systemd-journald[105]: varlink-18: varlink: changing state processing-disconnect → disconnected
816 11:43:01.428859 <47>[ 8.536691] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
817 11:43:01.443797 <47>[ 8.551782] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
818 11:43:01.455123 <47>[ 8.563153] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
819 11:43:01.459626 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
820 11:43:01.523184 Starting [0;1;39mCreate Volatile Files and Directories[0m...
821 11:43:01.534325 <47>[ 8.642082] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
822 11:43:01.950392 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
823 11:43:02.027927 Starting [0;1;39mNetwork Service[0m...
824 11:43:02.056473 <47>[ 9.164179] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
825 11:43:02.062665 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
826 11:43:02.151332 Starting [0;1;39mNetwork Time Synchronization[0m...
827 11:43:02.192504 <47>[ 9.300245] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
828 11:43:02.219490 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
829 11:43:02.232227 <47>[ 9.339951] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
830 11:43:02.624901 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
831 11:43:03.567235 <47>[ 10.674311] systemd-journald[105]: Data hash table of /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal has a fill level at 75.0 (3329 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
832 11:43:03.567873 <47>[ 10.674963] systemd-journald[105]: /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal: Journal header limits reached or header out-of-date, rotating.
833 11:43:03.568108 <47>[ 10.675446] systemd-journald[105]: Rotating...
834 11:43:03.568753 <47>[ 10.676392] systemd-journald[105]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
835 11:43:03.586553 <47>[ 10.694478] systemd-journald[105]: Reserving 333 entries in field hash table.
836 11:43:03.633430 <47>[ 10.741149] systemd-journald[105]: Reserving 4437 entries in data hash table.
837 11:43:03.652462 <47>[ 10.760417] systemd-journald[105]: Vacuuming...
838 11:43:03.677164 <47>[ 10.784872] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
839 11:43:03.692153 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
840 11:43:03.791277 Starting [0;1;39mNetwork Name Resolution[0m...
841 11:43:03.830171 <47>[ 10.937861] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
842 11:43:04.097098 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
843 11:43:04.099765 <47>[ 11.207608] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
844 11:43:04.114133 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
845 11:43:04.118614 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
846 11:43:05.320420 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
847 11:43:05.331750 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
848 11:43:05.350605 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
849 11:43:05.369201 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
850 11:43:05.375510 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
851 11:43:05.380704 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
852 11:43:05.410725 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
853 11:43:05.411861 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
854 11:43:05.412457 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
855 11:43:05.495039 <47>[ 12.602751] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
856 11:43:05.500537 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
857 11:43:05.644951 <47>[ 12.752653] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
858 11:43:05.659172 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
859 11:43:05.851540 Starting [0;1;39mUser Login Management[0m...
860 11:43:05.911864 <47>[ 13.019544] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
861 11:43:06.174539 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
862 11:43:06.176636 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
863 11:43:06.183728 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
864 11:43:06.265006 Starting [0;1;39mPermit User Sessions[0m...
865 11:43:06.308640 <47>[ 13.416281] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
866 11:43:06.503595 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
867 11:43:06.576772 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
868 11:43:06.661217 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
869 11:43:07.055761 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
870 11:43:09.033045 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
871 11:43:09.120118 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
872 11:43:09.140481 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
873 11:43:09.156438 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
874 11:43:09.165081 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
875 11:43:09.214687 <47>[ 16.322583] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
876 11:43:09.228936 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
877 11:43:09.435372 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
878 11:43:09.470943 <47>[ 16.578655] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
879 11:43:09.474984 <47>[ 16.582782] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
880 11:43:09.547743
881 11:43:09.548203 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
882 11:43:09.548345
883 11:43:09.548506 debian-bullseye-arm64 login: root (automatic login)
884 11:43:09.548912
885 11:43:09.651816 <6>[ 16.759526] virtio_net virtio0 enp0s1: renamed from eth0
886 11:43:09.810016 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:20:52 UTC 2023 aarch64
887 11:43:09.810644
888 11:43:09.811113 The programs included with the Debian GNU/Linux system are free software;
889 11:43:09.811303 the exact distribution terms for each program are described in the
890 11:43:09.811440 individual files in /usr/share/doc/*/copyright.
891 11:43:09.811566
892 11:43:09.811714 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
893 11:43:09.811844 permitted by applicable law.
894 11:43:10.405070 <47>[ 17.512993] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
895 11:43:10.455955 <47>[ 17.563281] systemd-journald[105]: Data hash table of /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal has a fill level at 75.0 (3329 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
896 11:43:10.456189 <47>[ 17.563904] systemd-journald[105]: /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal: Journal header limits reached or header out-of-date, rotating.
897 11:43:10.456685 <47>[ 17.564433] systemd-journald[105]: Rotating...
898 11:43:10.462613 <47>[ 17.570420] systemd-journald[105]: Reserving 333 entries in field hash table.
899 11:43:10.488827 <47>[ 17.596471] systemd-journald[105]: Reserving 4437 entries in data hash table.
900 11:43:10.500165 <47>[ 17.608213] systemd-journald[105]: Vacuuming...
901 11:43:10.501418 <47>[ 17.609306] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
902 11:43:10.748040 <47>[ 17.855623] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
903 11:43:12.502437 <47>[ 19.610216] systemd-journald[105]: Successfully sent stream file descriptor to service manager.
904 11:43:12.903456 Matched prompt #10: / #
906 11:43:12.904020 Setting prompt string to ['/ #']
907 11:43:12.904201 end: 2.2.1 login-action (duration 00:00:20) [common]
909 11:43:12.904608 end: 2.2 auto-login-action (duration 00:00:22) [common]
910 11:43:12.904777 start: 2.3 expect-shell-connection (timeout 00:04:36) [common]
911 11:43:12.904913 Setting prompt string to ['/ #']
912 11:43:12.905034 Forcing a shell prompt, looking for ['/ #']
914 11:43:12.955615 / #
915 11:43:12.956024 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
916 11:43:12.956248 Waiting using forced prompt support (timeout 00:02:30)
917 11:43:12.958148
918 11:43:12.976746 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
919 11:43:12.977007 start: 2.4 export-device-env (timeout 00:04:36) [common]
920 11:43:12.977142 end: 2.4 export-device-env (duration 00:00:00) [common]
921 11:43:12.977269 end: 2 boot-image-retry (duration 00:00:24) [common]
922 11:43:12.977386 start: 3 lava-test-retry (timeout 00:08:54) [common]
923 11:43:12.977500 start: 3.1 lava-test-shell (timeout 00:08:54) [common]
924 11:43:12.977594 Using namespace: common
926 11:43:13.078408 / # #
927 11:43:13.078709 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
928 11:43:13.079532 #
930 11:43:13.188961 / # mkdir /lava-615224
931 11:43:13.189868 mkdir /lava-615224
933 11:43:13.320291 / # mount /dev/disk/by-uuid/9eddc269-afb8-49f4-9776-78b8ed32dda1 -t ext2 /lava-615224
934 11:43:13.321099 mount /dev/disk/by-uuid/9eddc269-afb8-49f4-9776-78b8ed32dda1 -t ext2 /lava-615224
935 11:43:13.356720 <4>[ 20.464419] ext2 filesystem being mounted at /lava-615224 supports timestamps until 2038 (0x7fffffff)
937 11:43:13.503975 / # ls -la /lava-615224/bin/lava-test-runner
938 11:43:13.504780 ls -la /lava-615224/bin/lava-test-runner
939 11:43:13.544120 -rwxr-xr-x 1 root root 1039 Jun 15 11:42 /lava-615224/bin/lava-test-runner
940 11:43:13.555737 Using /lava-615224
942 11:43:13.656647 / # export SHELL=/bin/sh
943 11:43:13.657520 export SHELL=/bin/sh
945 11:43:13.765705 / # . /lava-615224/environment
946 11:43:13.766412 . /lava-615224/environment
948 11:43:13.875792 / # /lava-615224/bin/lava-test-runner /lava-615224/0
949 11:43:13.875968 Test shell timeout: 10s (minimum of the action and connection timeout)
950 11:43:13.876712 /lava-615224/bin/lava-test-runner /lava-615224/0
951 11:43:14.030329 + export TESTRUN_ID=0_timesync-off
952 11:43:14.030673 + cd /lava-615224/0/tests/0_timesync-off
953 11:43:14.032460 + cat uuid
954 11:43:14.040130 + UUID=615224_1.1.3.1
955 11:43:14.040249 + set +x
956 11:43:14.040716 Received signal: <STARTRUN> 0_timesync-off 615224_1.1.3.1
957 11:43:14.040841 Starting test lava.0_timesync-off (615224_1.1.3.1)
958 11:43:14.040967 Skipping test definition patterns.
959 11:43:14.041115 <LAVA_SIGNAL_STARTRUN 0_timesync-off 615224_1.1.3.1>
960 11:43:14.041213 + systemctl stop systemd-timesyncd
961 11:43:14.281199 + set +x
962 11:43:14.281703 <LAVA_SIGNAL_ENDRUN 0_timesync-off 615224_1.1.3.1>
963 11:43:14.282038 Received signal: <ENDRUN> 0_timesync-off 615224_1.1.3.1
964 11:43:14.282193 Ending use of test pattern.
965 11:43:14.282314 Ending test lava.0_timesync-off (615224_1.1.3.1), duration 0.24
967 11:43:14.324125 + export TESTRUN_ID=1_kselftest-arm64_qemu
968 11:43:14.324325 + cd /lava-615224/0/tests/1_kselftest-arm64_qemu
969 11:43:14.326608 + cat uuid
970 11:43:14.334499 + UUID=615224_1.1.3.5
971 11:43:14.334732 + set +x
972 11:43:14.334831 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 615224_1.1.3.5>
973 11:43:14.335114 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 615224_1.1.3.5
974 11:43:14.335204 Starting test lava.1_kselftest-arm64_qemu (615224_1.1.3.5)
975 11:43:14.335312 Skipping test definition patterns.
976 11:43:14.335445 + cd ./automated/linux/kselftest/
977 11:43:14.339344 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip -e -p /opt/kselftests/mainline/ -n 1 -i 1
978 11:43:14.431588 INFO: install_deps skipped
979 11:43:14.463564 --2023-06-15 11:43:14-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig/gcc-10/kselftest.tar.xz
980 11:43:14.633697 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
981 11:43:14.829875 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
982 11:43:15.011903 HTTP request sent, awaiting response... 200 OK
983 11:43:15.014613 Length: 2879956 (2.7M) [application/octet-stream]
984 11:43:15.016078 Saving to: 'kselftest.tar.xz'
985 11:43:15.017283
986 11:43:16.234439 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 159KB/s kselftest.tar.xz 7%[> ] 209.94K 324KB/s kselftest.tar.xz 30%[=====> ] 859.00K 869KB/s kselftest.tar.xz 79%[==============> ] 2.18M 1.84MB/s kselftest.tar.xz 100%[===================>] 2.75M 2.27MB/s in 1.2s
987 11:43:16.234747
988 11:43:16.239241 2023-06-15 11:43:16 (2.27 MB/s) - 'kselftest.tar.xz' saved [2879956/2879956]
989 11:43:16.239421
990 11:43:19.273046 skiplist:
991 11:43:19.273275 ========================================
992 11:43:19.273554 ========================================
993 11:43:19.323715 arm64:tags_test
994 11:43:19.323946 arm64:run_tags_test.sh
995 11:43:19.324454 arm64:fake_sigreturn_bad_magic
996 11:43:19.324556 arm64:fake_sigreturn_bad_size
997 11:43:19.324636 arm64:fake_sigreturn_bad_size_for_magic0
998 11:43:19.324712 arm64:fake_sigreturn_duplicated_fpsimd
999 11:43:19.324785 arm64:fake_sigreturn_misaligned_sp
1000 11:43:19.324858 arm64:fake_sigreturn_missing_fpsimd
1001 11:43:19.324930 arm64:fake_sigreturn_sme_change_vl
1002 11:43:19.325002 arm64:fake_sigreturn_sve_change_vl
1003 11:43:19.325074 arm64:mangle_pstate_invalid_compat_toggle
1004 11:43:19.325163 arm64:mangle_pstate_invalid_daif_bits
1005 11:43:19.325239 arm64:mangle_pstate_invalid_mode_el1h
1006 11:43:19.325311 arm64:mangle_pstate_invalid_mode_el1t
1007 11:43:19.325383 arm64:mangle_pstate_invalid_mode_el2h
1008 11:43:19.325455 arm64:mangle_pstate_invalid_mode_el2t
1009 11:43:19.325528 arm64:mangle_pstate_invalid_mode_el3h
1010 11:43:19.325600 arm64:mangle_pstate_invalid_mode_el3t
1011 11:43:19.325682 arm64:sme_trap_no_sm
1012 11:43:19.325755 arm64:sme_trap_non_streaming
1013 11:43:19.325828 arm64:sme_trap_za
1014 11:43:19.325901 arm64:sme_vl
1015 11:43:19.325973 arm64:ssve_regs
1016 11:43:19.326067 arm64:sve_regs
1017 11:43:19.326144 arm64:sve_vl
1018 11:43:19.326217 arm64:za_no_regs
1019 11:43:19.326288 arm64:za_regs
1020 11:43:19.326360 arm64:pac
1021 11:43:19.326431 arm64:fp-stress
1022 11:43:19.326503 arm64:sve-ptrace
1023 11:43:19.326575 arm64:sve-probe-vls
1024 11:43:19.326646 arm64:vec-syscfg
1025 11:43:19.326726 arm64:za-fork
1026 11:43:19.326800 arm64:za-ptrace
1027 11:43:19.326870 arm64:check_buffer_fill
1028 11:43:19.326948 arm64:check_child_memory
1029 11:43:19.327021 arm64:check_gcr_el1_cswitch
1030 11:43:19.327093 arm64:check_ksm_options
1031 11:43:19.327165 arm64:check_mmap_options
1032 11:43:19.327253 arm64:check_prctl
1033 11:43:19.327329 arm64:check_tags_inclusion
1034 11:43:19.327401 arm64:check_user_mem
1035 11:43:19.327473 arm64:btitest
1036 11:43:19.327544 arm64:nobtitest
1037 11:43:19.327612 arm64:hwcap
1038 11:43:19.327680 arm64:ptrace
1039 11:43:19.327752 arm64:syscall-abi
1040 11:43:19.327825 arm64:tpidr2
1041 11:43:19.337929 ============== Tests to run ===============
1042 11:43:19.343016 arm64:tags_test
1043 11:43:19.343311 arm64:run_tags_test.sh
1044 11:43:19.343409 arm64:fake_sigreturn_bad_magic
1045 11:43:19.343486 arm64:fake_sigreturn_bad_size
1046 11:43:19.343572 arm64:fake_sigreturn_bad_size_for_magic0
1047 11:43:19.343648 arm64:fake_sigreturn_duplicated_fpsimd
1048 11:43:19.343725 arm64:fake_sigreturn_misaligned_sp
1049 11:43:19.343811 arm64:fake_sigreturn_missing_fpsimd
1050 11:43:19.343886 arm64:fake_sigreturn_sme_change_vl
1051 11:43:19.343959 arm64:fake_sigreturn_sve_change_vl
1052 11:43:19.344045 arm64:mangle_pstate_invalid_compat_toggle
1053 11:43:19.344121 arm64:mangle_pstate_invalid_daif_bits
1054 11:43:19.344208 arm64:mangle_pstate_invalid_mode_el1h
1055 11:43:19.344284 arm64:mangle_pstate_invalid_mode_el1t
1056 11:43:19.344377 arm64:mangle_pstate_invalid_mode_el2h
1057 11:43:19.344454 arm64:mangle_pstate_invalid_mode_el2t
1058 11:43:19.344540 arm64:mangle_pstate_invalid_mode_el3h
1059 11:43:19.344616 arm64:mangle_pstate_invalid_mode_el3t
1060 11:43:19.344884 arm64:sme_trap_no_sm
1061 11:43:19.344980 arm64:sme_trap_non_streaming
1062 11:43:19.345056 arm64:sme_trap_za
1063 11:43:19.345129 arm64:sme_vl
1064 11:43:19.345204 arm64:ssve_regs
1065 11:43:19.345299 arm64:sve_regs
1066 11:43:19.345374 arm64:sve_vl
1067 11:43:19.345446 arm64:za_no_regs
1068 11:43:19.345517 arm64:za_regs
1069 11:43:19.345588 arm64:pac
1070 11:43:19.345676 arm64:fp-stress
1071 11:43:19.345749 arm64:sve-ptrace
1072 11:43:19.345818 arm64:sve-probe-vls
1073 11:43:19.345904 arm64:vec-syscfg
1074 11:43:19.345978 arm64:za-fork
1075 11:43:19.346050 arm64:za-ptrace
1076 11:43:19.346121 arm64:check_buffer_fill
1077 11:43:19.346193 arm64:check_child_memory
1078 11:43:19.346264 arm64:check_gcr_el1_cswitch
1079 11:43:19.346335 arm64:check_ksm_options
1080 11:43:19.346406 arm64:check_mmap_options
1081 11:43:19.346476 arm64:check_prctl
1082 11:43:19.346561 arm64:check_tags_inclusion
1083 11:43:19.346634 arm64:check_user_mem
1084 11:43:19.346706 arm64:btitest
1085 11:43:19.346777 arm64:nobtitest
1086 11:43:19.346848 arm64:hwcap
1087 11:43:19.346920 arm64:ptrace
1088 11:43:19.346991 arm64:syscall-abi
1089 11:43:19.347062 arm64:tpidr2
1090 11:43:19.348153 ===========End Tests to run ===============
1091 11:43:20.236147 <12>[ 27.344096] kselftest: Running tests in arm64
1092 11:43:20.262965 TAP version 13
1093 11:43:20.280006 1..48
1094 11:43:20.326317 # selftests: arm64: tags_test
1095 11:43:20.377452 ok 1 selftests: arm64: tags_test
1096 11:43:20.422279 # selftests: arm64: run_tags_test.sh
1097 11:43:20.471327 # --------------------
1098 11:43:20.471623 # running tags test
1099 11:43:20.471724 # --------------------
1100 11:43:20.471806 # [PASS]
1101 11:43:20.478986 ok 2 selftests: arm64: run_tags_test.sh
1102 11:43:20.524006 # selftests: arm64: fake_sigreturn_bad_magic
1103 11:43:20.574256 # Registered handlers for all signals.
1104 11:43:20.574493 # Detected MINSTKSIGSZ:10000
1105 11:43:20.574595 # Testcase initialized.
1106 11:43:20.574671 # uc context validated.
1107 11:43:20.574959 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1108 11:43:20.575058 # Handled SIG_COPYCTX
1109 11:43:20.575135 # Available space:3536
1110 11:43:20.575209 # Using badly built context - ERR: BAD MAGIC !
1111 11:43:20.575297 # SIG_OK -- SP:0xFFFFEAE46890 si_addr@:0xffffeae46890 si_code:2 token@:0xffffeae45630 offset:-4704
1112 11:43:20.575375 # ==>> completed. PASS(1)
1113 11:43:20.575449 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1114 11:43:20.575527 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEAE45630
1115 11:43:20.582485 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1116 11:43:20.626309 # selftests: arm64: fake_sigreturn_bad_size
1117 11:43:20.674399 # Registered handlers for all signals.
1118 11:43:20.674637 # Detected MINSTKSIGSZ:10000
1119 11:43:20.674823 # Testcase initialized.
1120 11:43:20.674998 # uc context validated.
1121 11:43:20.675198 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1122 11:43:20.675334 # Handled SIG_COPYCTX
1123 11:43:20.675452 # Available space:3536
1124 11:43:20.675567 # uc context validated.
1125 11:43:20.675681 # Using badly built context - ERR: Bad size for esr_context
1126 11:43:20.675798 # SIG_OK -- SP:0xFFFFD63604E0 si_addr@:0xffffd63604e0 si_code:2 token@:0xffffd635f280 offset:-4704
1127 11:43:20.675913 # ==>> completed. PASS(1)
1128 11:43:20.676027 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1129 11:43:20.676165 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD635F280
1130 11:43:20.682880 ok 4 selftests: arm64: fake_sigreturn_bad_size
1131 11:43:20.728780 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1132 11:43:20.776611 # Registered handlers for all signals.
1133 11:43:20.776745 # Detected MINSTKSIGSZ:10000
1134 11:43:20.776839 # Testcase initialized.
1135 11:43:20.777156 # uc context validated.
1136 11:43:20.777251 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1137 11:43:20.777333 # Handled SIG_COPYCTX
1138 11:43:20.777413 # Available space:3536
1139 11:43:20.777491 # Using badly built context - ERR: Bad size for terminator
1140 11:43:20.777582 # SIG_OK -- SP:0xFFFFC98A29A0 si_addr@:0xffffc98a29a0 si_code:2 token@:0xffffc98a1740 offset:-4704
1141 11:43:20.777671 # ==>> completed. PASS(1)
1142 11:43:20.777764 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1143 11:43:20.777856 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC98A1740
1144 11:43:20.786422 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1145 11:43:20.828721 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1146 11:43:20.878297 # Registered handlers for all signals.
1147 11:43:20.878838 # Detected MINSTKSIGSZ:10000
1148 11:43:20.878950 # Testcase initialized.
1149 11:43:20.879036 # uc context validated.
1150 11:43:20.879117 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1151 11:43:20.879197 # Handled SIG_COPYCTX
1152 11:43:20.879276 # Available space:3536
1153 11:43:20.879371 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1154 11:43:20.879454 # SIG_OK -- SP:0xFFFFC3A8FFC0 si_addr@:0xffffc3a8ffc0 si_code:2 token@:0xffffc3a8ed60 offset:-4704
1155 11:43:20.879534 # ==>> completed. PASS(1)
1156 11:43:20.879612 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1157 11:43:20.879707 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC3A8ED60
1158 11:43:20.887239 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1159 11:43:20.931396 # selftests: arm64: fake_sigreturn_misaligned_sp
1160 11:43:20.979025 # Registered handlers for all signals.
1161 11:43:20.979436 # Detected MINSTKSIGSZ:10000
1162 11:43:20.979536 # Testcase initialized.
1163 11:43:20.979617 # uc context validated.
1164 11:43:20.979691 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1165 11:43:20.979765 # Handled SIG_COPYCTX
1166 11:43:20.979851 # SIG_OK -- SP:0xFFFFD6AA90F3 si_addr@:0xffffd6aa90f3 si_code:2 token@:0xffffd6aa90f3 offset:0
1167 11:43:20.979927 # ==>> completed. PASS(1)
1168 11:43:20.980062 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1169 11:43:20.980246 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD6AA90F3
1170 11:43:20.987803 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1171 11:43:21.032499 # selftests: arm64: fake_sigreturn_missing_fpsimd
1172 11:43:21.081054 # Registered handlers for all signals.
1173 11:43:21.081267 # Detected MINSTKSIGSZ:10000
1174 11:43:21.081446 # Testcase initialized.
1175 11:43:21.081645 # uc context validated.
1176 11:43:21.081943 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1177 11:43:21.082100 # Handled SIG_COPYCTX
1178 11:43:21.082246 # Mangling template header. Spare space:4096
1179 11:43:21.082391 # Using badly built context - ERR: Missing FPSIMD
1180 11:43:21.082537 # SIG_OK -- SP:0xFFFFF42E9530 si_addr@:0xfffff42e9530 si_code:2 token@:0xfffff42e82d0 offset:-4704
1181 11:43:21.082682 # ==>> completed. PASS(1)
1182 11:43:21.082827 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1183 11:43:21.082971 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF42E82D0
1184 11:43:21.090193 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1185 11:43:21.137022 # selftests: arm64: fake_sigreturn_sme_change_vl
1186 11:43:21.188615 # Registered handlers for all signals.
1187 11:43:21.190612 # Detected MINSTKSIGSZ:10000
1188 11:43:21.191009 # Required Features: [ SME ] supported
1189 11:43:21.191210 # Incompatible Features: [] absent
1190 11:43:21.191368 # Testcase initialized.
1191 11:43:21.191512 # uc context validated.
1192 11:43:21.191652 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1193 11:43:21.191794 # Handled SIG_COPYCTX
1194 11:43:21.191963 # Attempting to change VL from 16 to 256
1195 11:43:21.192110 # SIG_OK -- SP:0xFFFFDC228390 si_addr@:0xffffdc228390 si_code:2 token@:0xffffdc227130 offset:-4704
1196 11:43:21.192255 # ==>> completed. PASS(1)
1197 11:43:21.192397 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1198 11:43:21.192539 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDC227130
1199 11:43:21.198233 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1200 11:43:21.242742 # selftests: arm64: fake_sigreturn_sve_change_vl
1201 11:43:21.291340 # Registered handlers for all signals.
1202 11:43:21.291812 # Detected MINSTKSIGSZ:10000
1203 11:43:21.291919 # Required Features: [ SVE ] supported
1204 11:43:21.292010 # Incompatible Features: [] absent
1205 11:43:21.292096 # Testcase initialized.
1206 11:43:21.292181 # uc context validated.
1207 11:43:21.292267 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1208 11:43:21.292370 # Handled SIG_COPYCTX
1209 11:43:21.292458 # Attempting to change VL from 16 to 256
1210 11:43:21.292541 # SIG_OK -- SP:0xFFFFFAE48260 si_addr@:0xfffffae48260 si_code:2 token@:0xfffffae47000 offset:-4704
1211 11:43:21.292631 # ==>> completed. PASS(1)
1212 11:43:21.292739 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1213 11:43:21.299878 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFAE47000
1214 11:43:21.300198 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1215 11:43:21.345245 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1216 11:43:21.395714 # Registered handlers for all signals.
1217 11:43:21.395882 # Detected MINSTKSIGSZ:10000
1218 11:43:21.396161 # Testcase initialized.
1219 11:43:21.396248 # uc context validated.
1220 11:43:21.396325 # Handled SIG_TRIG
1221 11:43:21.396400 # SIG_OK -- SP:0xFFFFD9E47590 si_addr@:0xffffd9e47590 si_code:2 token@:(nil) offset:-281474337371536
1222 11:43:21.396477 # ==>> completed. PASS(1)
1223 11:43:21.396551 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1224 11:43:21.401698 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1225 11:43:21.449619 # selftests: arm64: mangle_pstate_invalid_daif_bits
1226 11:43:21.497667 # Registered handlers for all signals.
1227 11:43:21.497784 # Detected MINSTKSIGSZ:10000
1228 11:43:21.497869 # Testcase initialized.
1229 11:43:21.497952 # uc context validated.
1230 11:43:21.498034 # Handled SIG_TRIG
1231 11:43:21.498114 # SIG_OK -- SP:0xFFFFD11F8CF0 si_addr@:0xffffd11f8cf0 si_code:2 token@:(nil) offset:-281474190249200
1232 11:43:21.498211 # ==>> completed. PASS(1)
1233 11:43:21.498291 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1234 11:43:21.506229 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1235 11:43:21.553591 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1236 11:43:21.601706 # Registered handlers for all signals.
1237 11:43:21.601915 # Detected MINSTKSIGSZ:10000
1238 11:43:21.602083 # Testcase initialized.
1239 11:43:21.602206 # uc context validated.
1240 11:43:21.602324 # Handled SIG_TRIG
1241 11:43:21.602463 # SIG_OK -- SP:0xFFFFC40B9940 si_addr@:0xffffc40b9940 si_code:2 token@:(nil) offset:-281473970837824
1242 11:43:21.602583 # ==>> completed. PASS(1)
1243 11:43:21.602698 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1244 11:43:21.610281 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1245 11:43:21.655486 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1246 11:43:21.701605 # Registered handlers for all signals.
1247 11:43:21.702064 # Detected MINSTKSIGSZ:10000
1248 11:43:21.702165 # Testcase initialized.
1249 11:43:21.702245 # uc context validated.
1250 11:43:21.702319 # Handled SIG_TRIG
1251 11:43:21.702410 # SIG_OK -- SP:0xFFFFDC3D2260 si_addr@:0xffffdc3d2260 si_code:2 token@:(nil) offset:-281474376737376
1252 11:43:21.702491 # ==>> completed. PASS(1)
1253 11:43:21.702577 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1254 11:43:21.710305 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1255 11:43:21.754031 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1256 11:43:21.801877 # Registered handlers for all signals.
1257 11:43:21.802058 # Detected MINSTKSIGSZ:10000
1258 11:43:21.802258 # Testcase initialized.
1259 11:43:21.802424 # uc context validated.
1260 11:43:21.802578 # Handled SIG_TRIG
1261 11:43:21.802702 # SIG_OK -- SP:0xFFFFC303C210 si_addr@:0xffffc303c210 si_code:2 token@:(nil) offset:-281473953546768
1262 11:43:21.802834 # ==>> completed. PASS(1)
1263 11:43:21.803007 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1264 11:43:21.810186 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1265 11:43:21.854033 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1266 11:43:21.903124 # Registered handlers for all signals.
1267 11:43:21.903273 # Detected MINSTKSIGSZ:10000
1268 11:43:21.903674 # Testcase initialized.
1269 11:43:21.903848 # uc context validated.
1270 11:43:21.903974 # Handled SIG_TRIG
1271 11:43:21.904091 # SIG_OK -- SP:0xFFFFEDBA8780 si_addr@:0xffffedba8780 si_code:2 token@:(nil) offset:-281474670167936
1272 11:43:21.904211 # ==>> completed. PASS(1)
1273 11:43:21.904354 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1274 11:43:21.910353 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1275 11:43:21.955474 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1276 11:43:22.002364 # Registered handlers for all signals.
1277 11:43:22.002600 # Detected MINSTKSIGSZ:10000
1278 11:43:22.002768 # Testcase initialized.
1279 11:43:22.002945 # uc context validated.
1280 11:43:22.003128 # Handled SIG_TRIG
1281 11:43:22.003266 # SIG_OK -- SP:0xFFFFEEC53210 si_addr@:0xffffeec53210 si_code:2 token@:(nil) offset:-281474687644176
1282 11:43:22.003411 # ==>> completed. PASS(1)
1283 11:43:22.003554 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1284 11:43:22.011169 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1285 11:43:22.056155 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1286 11:43:22.102382 # Registered handlers for all signals.
1287 11:43:22.102693 # Detected MINSTKSIGSZ:10000
1288 11:43:22.103133 # Testcase initialized.
1289 11:43:22.103294 # uc context validated.
1290 11:43:22.103418 # Handled SIG_TRIG
1291 11:43:22.103536 # SIG_OK -- SP:0xFFFFCAB10460 si_addr@:0xffffcab10460 si_code:2 token@:(nil) offset:-281474082341984
1292 11:43:22.103656 # ==>> completed. PASS(1)
1293 11:43:22.103774 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1294 11:43:22.112154 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1295 11:43:22.156852 # selftests: arm64: sme_trap_no_sm
1296 11:43:22.273274 # Registered handlers for all signals.
1297 11:43:22.273680 # Detected MINSTKSIGSZ:10000
1298 11:43:22.274102 # Required Features: [ SME ] supported
1299 11:43:22.274310 # Incompatible Features: [] absent
1300 11:43:22.274488 # Testcase initialized.
1301 11:43:22.274652 # SIG_OK -- SP:0xFFFFCA54B3B0 si_addr@:0xaaaaab4f2514 si_code:1 token@:(nil) offset:-187649995253012
1302 11:43:22.274815 # ==>> completed. PASS(1)
1303 11:43:22.276068 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1304 11:43:22.290877 ok 19 selftests: arm64: sme_trap_no_sm
1305 11:43:22.388182 # selftests: arm64: sme_trap_non_streaming
1306 11:43:22.446908 # Registered handlers for all signals.
1307 11:43:22.447183 # Detected MINSTKSIGSZ:10000
1308 11:43:22.447347 # Required Features: [] NOT supported
1309 11:43:22.447477 # Incompatible Features: [] supported
1310 11:43:22.447626 # ==>> completed. SKIP.
1311 11:43:22.447754 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1312 11:43:22.455439 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1313 11:43:22.508192 # selftests: arm64: sme_trap_za
1314 11:43:22.556875 # Registered handlers for all signals.
1315 11:43:22.557024 # Detected MINSTKSIGSZ:10000
1316 11:43:22.557359 # Testcase initialized.
1317 11:43:22.557464 # SIG_OK -- SP:0xFFFFDA266F60 si_addr@:0xaaaac7be2510 si_code:1 token@:(nil) offset:-187650472289552
1318 11:43:22.557552 # ==>> completed. PASS(1)
1319 11:43:22.557655 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1320 11:43:22.565877 ok 21 selftests: arm64: sme_trap_za
1321 11:43:22.613721 # selftests: arm64: sme_vl
1322 11:43:22.663027 # Registered handlers for all signals.
1323 11:43:22.663351 # Detected MINSTKSIGSZ:10000
1324 11:43:22.663766 # Required Features: [ SME ] supported
1325 11:43:22.663924 # Incompatible Features: [] absent
1326 11:43:22.664076 # Testcase initialized.
1327 11:43:22.664221 # uc context validated.
1328 11:43:22.664365 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1329 11:43:22.664509 # Handled SIG_COPYCTX
1330 11:43:22.664653 # got expected VL 32
1331 11:43:22.664795 # ==>> completed. PASS(1)
1332 11:43:22.664935 # # SME VL :: Check that we get the right SME VL reported
1333 11:43:22.671853 ok 22 selftests: arm64: sme_vl
1334 11:43:22.717444 # selftests: arm64: ssve_regs
1335 11:43:22.901263 # Registered handlers for all signals.
1336 11:43:22.901520 # Detected MINSTKSIGSZ:10000
1337 11:43:22.901915 # Required Features: [ SME FA64 ] supported
1338 11:43:22.902116 # Incompatible Features: [] absent
1339 11:43:22.902216 # Testcase initialized.
1340 11:43:22.902301 # Testing VL 256
1341 11:43:22.902382 # Validating EXTRA...
1342 11:43:22.902462 # uc context validated.
1343 11:43:22.902542 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1344 11:43:22.902623 # Handled SIG_COPYCTX
1345 11:43:22.902723 # Got expected size 8752 and VL 256
1346 11:43:22.902808 # Testing VL 128
1347 11:43:22.902888 # Validating EXTRA...
1348 11:43:22.902968 # uc context validated.
1349 11:43:22.903048 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1350 11:43:22.903128 # Handled SIG_COPYCTX
1351 11:43:22.903207 # Got expected size 4384 and VL 128
1352 11:43:22.903286 # Testing VL 64
1353 11:43:22.903366 # uc context validated.
1354 11:43:22.903445 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1355 11:43:22.903525 # Handled SIG_COPYCTX
1356 11:43:22.909996 # Got expected size 2208 and VL 64
1357 11:43:22.910202 # Testing VL 32
1358 11:43:22.910562 # uc context validated.
1359 11:43:22.910667 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1360 11:43:22.910754 # Handled SIG_COPYCTX
1361 11:43:22.910836 # Got expected size 1120 and VL 32
1362 11:43:22.910918 # Testing VL 16
1363 11:43:22.911001 # uc context validated.
1364 11:43:22.911082 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1365 11:43:22.911164 # Handled SIG_COPYCTX
1366 11:43:22.911244 # Got expected size 576 and VL 16
1367 11:43:22.911528 # ==>> completed. PASS(1)
1368 11:43:22.911632 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1369 11:43:22.911906 ok 23 selftests: arm64: ssve_regs
1370 11:43:22.956870 # selftests: arm64: sve_regs
1371 11:43:23.377929 # Registered handlers for all signals.
1372 11:43:23.378285 # Detected MINSTKSIGSZ:10000
1373 11:43:23.378768 # Required Features: [ SVE ] supported
1374 11:43:23.379026 # Incompatible Features: [] absent
1375 11:43:23.379222 # Testcase initialized.
1376 11:43:23.379362 # Testing VL 256
1377 11:43:23.379486 # Validating EXTRA...
1378 11:43:23.379605 # uc context validated.
1379 11:43:23.379725 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1380 11:43:23.379844 # Handled SIG_COPYCTX
1381 11:43:23.379961 # Got expected size 8752 and VL 256
1382 11:43:23.380078 # Testing VL 240
1383 11:43:23.380194 # Validating EXTRA...
1384 11:43:23.380310 # uc context validated.
1385 11:43:23.380454 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1386 11:43:23.380581 # Handled SIG_COPYCTX
1387 11:43:23.380700 # Got expected size 8208 and VL 240
1388 11:43:23.380817 # Testing VL 224
1389 11:43:23.387092 # Validating EXTRA...
1390 11:43:23.387301 # uc context validated.
1391 11:43:23.387467 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1392 11:43:23.387592 # Handled SIG_COPYCTX
1393 11:43:23.388069 # Got expected size 7664 and VL 224
1394 11:43:23.388217 # Testing VL 208
1395 11:43:23.388512 # Validating EXTRA...
1396 11:43:23.388621 # uc context validated.
1397 11:43:23.388711 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1398 11:43:23.388796 # Handled SIG_COPYCTX
1399 11:43:23.388893 # Got expected size 7120 and VL 208
1400 11:43:23.388991 # Testing VL 192
1401 11:43:23.389073 # Validating EXTRA...
1402 11:43:23.389153 # uc context validated.
1403 11:43:23.389231 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1404 11:43:23.389311 # Handled SIG_COPYCTX
1405 11:43:23.389406 # Got expected size 6576 and VL 192
1406 11:43:23.389489 # Testing VL 176
1407 11:43:23.389568 # Validating EXTRA...
1408 11:43:23.389654 # uc context validated.
1409 11:43:23.389750 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1410 11:43:23.389832 # Handled SIG_COPYCTX
1411 11:43:23.389912 # Got expected size 6032 and VL 176
1412 11:43:23.389992 # Testing VL 160
1413 11:43:23.390071 # Validating EXTRA...
1414 11:43:23.390149 # uc context validated.
1415 11:43:23.390247 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1416 11:43:23.390331 # Handled SIG_COPYCTX
1417 11:43:23.390903 # Got expected size 5488 and VL 160
1418 11:43:23.391053 # Testing VL 144
1419 11:43:23.391138 # Validating EXTRA...
1420 11:43:23.391218 # uc context validated.
1421 11:43:23.391297 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1422 11:43:23.391376 # Handled SIG_COPYCTX
1423 11:43:23.391455 # Got expected size 4944 and VL 144
1424 11:43:23.391539 # Testing VL 128
1425 11:43:23.391815 # Validating EXTRA...
1426 11:43:23.391919 # uc context validated.
1427 11:43:23.392004 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1428 11:43:23.392125 # Handled SIG_COPYCTX
1429 11:43:23.392210 # Got expected size 4384 and VL 128
1430 11:43:23.392292 # Testing VL 112
1431 11:43:23.395457 # Validating EXTRA...
1432 11:43:23.395574 # uc context validated.
1433 11:43:23.395859 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1434 11:43:23.395965 # Handled SIG_COPYCTX
1435 11:43:23.396050 # Got expected size 3840 and VL 112
1436 11:43:23.396133 # Testing VL 96
1437 11:43:23.396213 # uc context validated.
1438 11:43:23.396309 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1439 11:43:23.396391 # Handled SIG_COPYCTX
1440 11:43:23.396471 # Got expected size 3296 and VL 96
1441 11:43:23.396549 # Testing VL 80
1442 11:43:23.396629 # uc context validated.
1443 11:43:23.396723 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1444 11:43:23.396805 # Handled SIG_COPYCTX
1445 11:43:23.396883 # Got expected size 2752 and VL 80
1446 11:43:23.396962 # Testing VL 64
1447 11:43:23.397056 # uc context validated.
1448 11:43:23.397138 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1449 11:43:23.397218 # Handled SIG_COPYCTX
1450 11:43:23.397310 # Got expected size 2208 and VL 64
1451 11:43:23.397405 # Testing VL 48
1452 11:43:23.397486 # uc context validated.
1453 11:43:23.397566 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1454 11:43:23.397667 # Handled SIG_COPYCTX
1455 11:43:23.397750 # Got expected size 1664 and VL 48
1456 11:43:23.397830 # Testing VL 32
1457 11:43:23.397909 # uc context validated.
1458 11:43:23.398002 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1459 11:43:23.398085 # Handled SIG_COPYCTX
1460 11:43:23.398179 # Got expected size 1120 and VL 32
1461 11:43:23.398261 # Testing VL 16
1462 11:43:23.398341 # uc context validated.
1463 11:43:23.398434 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1464 11:43:23.398516 # Handled SIG_COPYCTX
1465 11:43:23.398596 # Got expected size 576 and VL 16
1466 11:43:23.398693 # ==>> completed. PASS(1)
1467 11:43:23.398774 # # SVE registers :: Check that we get the right SVE registers reported
1468 11:43:23.399352 ok 24 selftests: arm64: sve_regs
1469 11:43:23.441245 # selftests: arm64: sve_vl
1470 11:43:23.489809 # Registered handlers for all signals.
1471 11:43:23.490289 # Detected MINSTKSIGSZ:10000
1472 11:43:23.490408 # Required Features: [ SVE ] supported
1473 11:43:23.490502 # Incompatible Features: [] absent
1474 11:43:23.490586 # Testcase initialized.
1475 11:43:23.490673 # uc context validated.
1476 11:43:23.490758 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1477 11:43:23.490864 # Handled SIG_COPYCTX
1478 11:43:23.490954 # got expected VL 64
1479 11:43:23.491042 # ==>> completed. PASS(1)
1480 11:43:23.491131 # # SVE VL :: Check that we get the right SVE VL reported
1481 11:43:23.498413 ok 25 selftests: arm64: sve_vl
1482 11:43:23.542768 # selftests: arm64: za_no_regs
1483 11:43:23.599996 # Registered handlers for all signals.
1484 11:43:23.600316 # Detected MINSTKSIGSZ:10000
1485 11:43:23.600489 # Required Features: [ SME ] supported
1486 11:43:23.600654 # Incompatible Features: [] absent
1487 11:43:23.600809 # Testcase initialized.
1488 11:43:23.601003 # Testing VL 256
1489 11:43:23.601167 # uc context validated.
1490 11:43:23.601328 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1491 11:43:23.601487 # Handled SIG_COPYCTX
1492 11:43:23.601655 # Got expected size 16 and VL 256
1493 11:43:23.601822 # Testing VL 128
1494 11:43:23.601988 # uc context validated.
1495 11:43:23.602131 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1496 11:43:23.602250 # Handled SIG_COPYCTX
1497 11:43:23.602365 # Got expected size 16 and VL 128
1498 11:43:23.602478 # Testing VL 64
1499 11:43:23.602623 # uc context validated.
1500 11:43:23.602749 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1501 11:43:23.602865 # Handled SIG_COPYCTX
1502 11:43:23.602977 # Got expected size 16 and VL 64
1503 11:43:23.603092 # Testing VL 32
1504 11:43:23.603231 # uc context validated.
1505 11:43:23.603385 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1506 11:43:23.603506 # Handled SIG_COPYCTX
1507 11:43:23.603620 # Got expected size 16 and VL 32
1508 11:43:23.603733 # Testing VL 16
1509 11:43:23.603847 # uc context validated.
1510 11:43:23.603961 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1511 11:43:23.604074 # Handled SIG_COPYCTX
1512 11:43:23.604186 # Got expected size 16 and VL 16
1513 11:43:23.604298 # ==>> completed. PASS(1)
1514 11:43:23.604412 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1515 11:43:23.610202 ok 26 selftests: arm64: za_no_regs
1516 11:43:23.711133 # selftests: arm64: za_regs
1517 11:43:23.898305 # Registered handlers for all signals.
1518 11:43:23.898558 # Detected MINSTKSIGSZ:10000
1519 11:43:23.898651 # Required Features: [ SME ] supported
1520 11:43:23.898965 # Incompatible Features: [] absent
1521 11:43:23.899075 # Testcase initialized.
1522 11:43:23.899162 # Testing VL 256
1523 11:43:23.899245 # Validating EXTRA...
1524 11:43:23.899328 # uc context validated.
1525 11:43:23.899411 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1526 11:43:23.899498 # Handled SIG_COPYCTX
1527 11:43:23.899581 # Got expected size 65552 and VL 256
1528 11:43:23.899681 # Testing VL 128
1529 11:43:23.899764 # Validating EXTRA...
1530 11:43:23.899848 # uc context validated.
1531 11:43:23.899932 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1532 11:43:23.900015 # Handled SIG_COPYCTX
1533 11:43:23.900100 # Got expected size 16400 and VL 128
1534 11:43:23.900185 # Testing VL 64
1535 11:43:23.900270 # Validating EXTRA...
1536 11:43:23.900373 # uc context validated.
1537 11:43:23.900464 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1538 11:43:23.900555 # Handled SIG_COPYCTX
1539 11:43:23.900641 # Got expected size 4112 and VL 64
1540 11:43:23.900725 # Testing VL 32
1541 11:43:23.900809 # uc context validated.
1542 11:43:23.900911 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1543 11:43:23.900999 # Handled SIG_COPYCTX
1544 11:43:23.901083 # Got expected size 1040 and VL 32
1545 11:43:23.901167 # Testing VL 16
1546 11:43:23.901250 # uc context validated.
1547 11:43:23.901333 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1548 11:43:23.901437 # Handled SIG_COPYCTX
1549 11:43:23.901526 # Got expected size 272 and VL 16
1550 11:43:23.901614 # ==>> completed. PASS(1)
1551 11:43:23.901708 # # ZA register :: Check that we get the right ZA registers reported
1552 11:43:23.909699 ok 27 selftests: arm64: za_regs
1553 11:43:23.953399 # selftests: arm64: pac
1554 11:43:24.099601 # TAP version 13
1555 11:43:24.099848 # 1..7
1556 11:43:24.099946 # # Starting 7 tests from 1 test cases.
1557 11:43:24.100247 # # RUN global.corrupt_pac ...
1558 11:43:24.100346 # # OK global.corrupt_pac
1559 11:43:24.100439 # ok 1 global.corrupt_pac
1560 11:43:24.102256 # # RUN global.pac_instructions_not_nop ...
1561 11:43:24.102608 # # OK global.pac_instructions_not_nop
1562 11:43:24.102828 # ok 2 global.pac_instructions_not_nop
1563 11:43:24.103096 # # RUN global.pac_instructions_not_nop_generic ...
1564 11:43:24.103327 # # OK global.pac_instructions_not_nop_generic
1565 11:43:24.103521 # ok 3 global.pac_instructions_not_nop_generic
1566 11:43:24.103735 # # RUN global.single_thread_different_keys ...
1567 11:43:24.103926 # # OK global.single_thread_different_keys
1568 11:43:24.104061 # ok 4 global.single_thread_different_keys
1569 11:43:24.104205 # # RUN global.exec_changed_keys ...
1570 11:43:24.109881 # # OK global.exec_changed_keys
1571 11:43:24.110104 # ok 5 global.exec_changed_keys
1572 11:43:24.110569 # # RUN global.context_switch_keep_keys ...
1573 11:43:24.110849 # # OK global.context_switch_keep_keys
1574 11:43:24.111064 # ok 6 global.context_switch_keep_keys
1575 11:43:24.111258 # # RUN global.context_switch_keep_keys_generic ...
1576 11:43:24.111451 # # OK global.context_switch_keep_keys_generic
1577 11:43:24.111583 # ok 7 global.context_switch_keep_keys_generic
1578 11:43:24.111701 # # PASSED: 7 / 7 tests passed.
1579 11:43:24.111816 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1580 11:43:24.111936 ok 28 selftests: arm64: pac
1581 11:43:24.155448 # selftests: arm64: fp-stress
1582 11:43:38.916051 # TAP version 13
1583 11:43:38.916383 # 1..27
1584 11:43:38.916571 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1585 11:43:38.916711 # # Will run for 10s
1586 11:43:38.916835 # # Started FPSIMD-0-0
1587 11:43:38.916965 # # Started SVE-VL-256-0
1588 11:43:38.917100 # # Started SVE-VL-240-0
1589 11:43:38.917235 # # Started SVE-VL-224-0
1590 11:43:38.917367 # # Started SVE-VL-208-0
1591 11:43:38.917675 # # Started SVE-VL-192-0
1592 11:43:38.917879 # # Started SVE-VL-176-0
1593 11:43:38.918053 # # Started SVE-VL-160-0
1594 11:43:38.918165 # # Started SVE-VL-144-0
1595 11:43:38.918271 # # Started SVE-VL-128-0
1596 11:43:38.918376 # # Started SVE-VL-112-0
1597 11:43:38.918482 # # Started SVE-VL-96-0
1598 11:43:38.918588 # # Started SVE-VL-80-0
1599 11:43:38.918693 # # Started SVE-VL-64-0
1600 11:43:38.918796 # # Started SVE-VL-48-0
1601 11:43:38.918904 # # Started SVE-VL-32-0
1602 11:43:38.919021 # # Started SVE-VL-16-0
1603 11:43:38.919132 # # Started SSVE-VL-256-0
1604 11:43:38.920379 # # Started ZA-VL-256-0
1605 11:43:38.920746 # # Started SSVE-VL-128-0
1606 11:43:38.920884 # # Started ZA-VL-128-0
1607 11:43:38.921009 # # Started SSVE-VL-64-0
1608 11:43:38.921135 # # Started ZA-VL-64-0
1609 11:43:38.921281 # # Started SSVE-VL-32-0
1610 11:43:38.921410 # # Started ZA-VL-32-0
1611 11:43:38.921528 # # Started SSVE-VL-16-0
1612 11:43:38.921638 # # Started ZA-VL-16-0
1613 11:43:38.922649 # # FPSIMD-0-0: Vector length: 128 bits
1614 11:43:38.922746 # # FPSIMD-0-0: PID: 908
1615 11:43:38.923020 # # SVE-VL-208-0: Vector length: 1664 bits
1616 11:43:38.923109 # # SVE-VL-208-0: PID: 912
1617 11:43:38.923190 # # SVE-VL-192-0: Vector length: 1536 bits
1618 11:43:38.923272 # # SVE-VL-240-0: Vector length: 1920 bits
1619 11:43:38.923368 # # SVE-VL-240-0: PID: 910
1620 11:43:38.923451 # # SVE-VL-192-0: PID: 913
1621 11:43:38.923532 # # SVE-VL-256-0: Vector length: 2048 bits
1622 11:43:38.923629 # # SVE-VL-256-0: PID: 909
1623 11:43:38.923713 # # SVE-VL-224-0: Vector length: 1792 bits
1624 11:43:38.923810 # # SVE-VL-224-0: PID: 911
1625 11:43:38.923906 # # SVE-VL-160-0: Vector length: 1280 bits
1626 11:43:38.923994 # # SVE-VL-160-0: PID: 915
1627 11:43:38.924094 # # SVE-VL-80-0: Vector length: 640 bits
1628 11:43:38.924191 # # SVE-VL-80-0: PID: 920
1629 11:43:38.924289 # # SVE-VL-128-0: Vector length: 1024 bits
1630 11:43:38.924386 # # SVE-VL-128-0: PID: 917
1631 11:43:38.924501 # # SVE-VL-176-0: Vector length: 1408 bits
1632 11:43:38.924598 # # SVE-VL-176-0: PID: 914
1633 11:43:38.924891 # # SVE-VL-96-0: Vector length: 768 bits
1634 11:43:38.924993 # # SVE-VL-96-0: PID: 919
1635 11:43:38.925090 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1636 11:43:38.925173 # # ZA-VL-32-0: PID: 932
1637 11:43:38.925268 # # SVE-VL-112-0: Vector length: 896 bits
1638 11:43:38.925350 # # SVE-VL-112-0: PID: 918
1639 11:43:38.925463 # # SVE-VL-144-0: Vector length: 1152 bits
1640 11:43:38.927375 # # SVE-VL-144-0: PID: 916
1641 11:43:38.927481 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1642 11:43:38.927580 # # ZA-VL-16-0: PID: 934
1643 11:43:38.927665 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1644 11:43:38.927761 # # SSVE-VL-256-0: PID: 925
1645 11:43:38.928035 # # SVE-VL-64-0: Vector length: 512 bits
1646 11:43:38.928123 # # SVE-VL-64-0: PID: 921
1647 11:43:38.928222 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1648 11:43:38.928308 # # SSVE-VL-128-0: PID: 927
1649 11:43:38.928579 # # SVE-VL-16-0: Vector length: 128 bits
1650 11:43:38.928682 # # SVE-VL-16-0: PID: 924
1651 11:43:38.929083 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1652 11:43:38.929324 # # SSVE-VL-32-0: PID: 931
1653 11:43:38.929527 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1654 11:43:38.929709 # # ZA-VL-128-0: PID: 928
1655 11:43:38.929835 # # SVE-VL-32-0: Vector length: 256 bits
1656 11:43:38.929951 # # SVE-VL-32-0: PID: 923
1657 11:43:38.930063 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1658 11:43:38.930175 # # SSVE-VL-64-0: PID: 929
1659 11:43:38.946118 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1660 11:43:38.946707 # # ZA-VL-256-0: PID: 926
1661 11:43:38.946901 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1662 11:43:38.947045 # # ZA-VL-64-0: PID: 930
1663 11:43:38.947222 # # SVE-VL-48-0: Vector length: 384 bits
1664 11:43:38.947390 # # SVE-VL-48-0: PID: 922
1665 11:43:38.947562 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1666 11:43:38.947719 # # SSVE-VL-16-0: PID: 933
1667 11:43:38.947900 # # Finishing up...
1668 11:43:38.948064 # ok 1 FPSIMD-0-0
1669 11:43:38.948225 # ok 2 SVE-VL-256-0
1670 11:43:38.948408 # ok 3 SVE-VL-240-0
1671 11:43:38.948584 # ok 4 SVE-VL-224-0
1672 11:43:38.948713 # ok 5 SVE-VL-208-0
1673 11:43:38.948841 # ok 6 SVE-VL-192-0
1674 11:43:38.948977 # ok 7 SVE-VL-176-0
1675 11:43:38.949131 # ok 8 SVE-VL-160-0
1676 11:43:38.949289 # ok 9 SVE-VL-144-0
1677 11:43:38.949450 # ok 10 SVE-VL-128-0
1678 11:43:38.949613 # ok 11 SVE-VL-112-0
1679 11:43:38.949760 # ok 12 SVE-VL-96-0
1680 11:43:38.949916 # ok 13 SVE-VL-80-0
1681 11:43:38.950037 # ok 14 SVE-VL-64-0
1682 11:43:38.950151 # ok 15 SVE-VL-48-0
1683 11:43:38.950264 # ok 16 SVE-VL-32-0
1684 11:43:38.950376 # ok 17 SVE-VL-16-0
1685 11:43:38.950490 # ok 18 SSVE-VL-256-0
1686 11:43:38.950603 # ok 19 ZA-VL-256-0
1687 11:43:38.950716 # ok 20 SSVE-VL-128-0
1688 11:43:38.950828 # ok 21 ZA-VL-128-0
1689 11:43:38.950939 # ok 22 SSVE-VL-64-0
1690 11:43:38.951052 # ok 23 ZA-VL-64-0
1691 11:43:38.951163 # ok 24 SSVE-VL-32-0
1692 11:43:38.951273 # ok 25 ZA-VL-32-0
1693 11:43:38.951385 # ok 26 SSVE-VL-16-0
1694 11:43:38.951496 # ok 27 ZA-VL-16-0
1695 11:43:38.951607 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=1458, signals=9
1696 11:43:38.951720 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=7200, signals=9
1697 11:43:38.951834 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=2955, signals=9
1698 11:43:38.951947 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=2959, signals=9
1699 11:43:38.952062 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=2244, signals=9
1700 11:43:38.952174 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=1009, signals=9
1701 11:43:38.952288 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=6057, signals=9
1702 11:43:38.962931 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=2633, signals=9
1703 11:43:38.963438 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=148, signals=9
1704 11:43:38.963580 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=1361, signals=9
1705 11:43:39.043642 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=3025, signals=9
1706 11:43:39.043957 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=3707, signals=9
1707 11:43:39.044157 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=2483, signals=9
1708 11:43:39.044299 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=8836, signals=8
1709 11:43:39.044431 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=10908, signals=9
1710 11:43:39.044593 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=3725, signals=9
1711 11:43:39.044731 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=5526, signals=9
1712 11:43:39.044884 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=8772, signals=9
1713 11:43:39.045071 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2147, signals=9
1714 11:43:39.045242 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=2295, signals=9
1715 11:43:39.045413 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=5180, signals=9
1716 11:43:39.045630 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=5159, signals=9
1717 11:43:39.045837 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=526, signals=9
1718 11:43:39.062762 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=3916, signals=9
1719 11:43:39.063115 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=2751, signals=9
1720 11:43:39.063517 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=4878, signals=9
1721 11:43:39.063683 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=2758, signals=9
1722 11:43:39.063872 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1723 11:43:39.064075 ok 29 selftests: arm64: fp-stress
1724 11:43:39.193409 # selftests: arm64: sve-ptrace
1725 11:43:39.313111 # TAP version 13
1726 11:43:39.313396 # 1..4104
1727 11:43:39.313595 # # Parent is 951, child is 952
1728 11:43:39.314021 # ok 1 SVE FPSIMD set via SVE: 0
1729 11:43:39.314210 # ok 2 SVE get_fpsimd() gave same state
1730 11:43:39.314374 # ok 3 SVE SVE_PT_VL_INHERIT set
1731 11:43:39.314523 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1732 11:43:39.314671 # ok 5 Set SVE VL 16
1733 11:43:39.314806 # ok 6 Set and get SVE data for VL 16
1734 11:43:39.314952 # ok 7 Set and get FPSIMD data for SVE VL 16
1735 11:43:39.315131 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1736 11:43:39.315273 # ok 9 Set SVE VL 32
1737 11:43:39.315419 # ok 10 Set and get SVE data for VL 32
1738 11:43:39.315569 # ok 11 Set and get FPSIMD data for SVE VL 32
1739 11:43:39.315721 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1740 11:43:39.315864 # ok 13 Set SVE VL 48
1741 11:43:39.316005 # ok 14 Set and get SVE data for VL 48
1742 11:43:39.316137 # ok 15 Set and get FPSIMD data for SVE VL 48
1743 11:43:39.316276 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1744 11:43:39.316406 # ok 17 Set SVE VL 64
1745 11:43:39.316533 # ok 18 Set and get SVE data for VL 64
1746 11:43:39.316652 # ok 19 Set and get FPSIMD data for SVE VL 64
1747 11:43:39.316800 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1748 11:43:39.316917 # ok 21 Set SVE VL 80
1749 11:43:39.317032 # ok 22 Set and get SVE data for VL 80
1750 11:43:39.317147 # ok 23 Set and get FPSIMD data for SVE VL 80
1751 11:43:39.317280 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1752 11:43:39.317408 # ok 25 Set SVE VL 96
1753 11:43:39.317555 # ok 26 Set and get SVE data for VL 96
1754 11:43:39.317715 # ok 27 Set and get FPSIMD data for SVE VL 96
1755 11:43:39.317831 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1756 11:43:39.317941 # ok 29 Set SVE VL 112
1757 11:43:39.318050 # ok 30 Set and get SVE data for VL 112
1758 11:43:39.318160 # ok 31 Set and get FPSIMD data for SVE VL 112
1759 11:43:39.318269 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1760 11:43:39.318384 # ok 33 Set SVE VL 128
1761 11:43:39.318496 # ok 34 Set and get SVE data for VL 128
1762 11:43:39.318636 # ok 35 Set and get FPSIMD data for SVE VL 128
1763 11:43:39.318755 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1764 11:43:39.318869 # ok 37 Set SVE VL 144
1765 11:43:39.318981 # ok 38 Set and get SVE data for VL 144
1766 11:43:39.319093 # ok 39 Set and get FPSIMD data for SVE VL 144
1767 11:43:39.319205 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1768 11:43:39.319317 # ok 41 Set SVE VL 160
1769 11:43:39.319428 # ok 42 Set and get SVE data for VL 160
1770 11:43:39.322622 # ok 43 Set and get FPSIMD data for SVE VL 160
1771 11:43:39.323055 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1772 11:43:39.323242 # ok 45 Set SVE VL 176
1773 11:43:39.323418 # ok 46 Set and get SVE data for VL 176
1774 11:43:39.323576 # ok 47 Set and get FPSIMD data for SVE VL 176
1775 11:43:39.323731 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1776 11:43:39.323885 # ok 49 Set SVE VL 192
1777 11:43:39.324056 # ok 50 Set and get SVE data for VL 192
1778 11:43:39.324204 # ok 51 Set and get FPSIMD data for SVE VL 192
1779 11:43:39.324338 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1780 11:43:39.324521 # ok 53 Set SVE VL 208
1781 11:43:39.324688 # ok 54 Set and get SVE data for VL 208
1782 11:43:39.324860 # ok 55 Set and get FPSIMD data for SVE VL 208
1783 11:43:39.325013 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1784 11:43:39.325176 # ok 57 Set SVE VL 224
1785 11:43:39.325307 # ok 58 Set and get SVE data for VL 224
1786 11:43:39.325481 # ok 59 Set and get FPSIMD data for SVE VL 224
1787 11:43:39.325635 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1788 11:43:39.325800 # ok 61 Set SVE VL 240
1789 11:43:39.325923 # ok 62 Set and get SVE data for VL 240
1790 11:43:39.326036 # ok 63 Set and get FPSIMD data for SVE VL 240
1791 11:43:39.326150 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1792 11:43:39.326262 # ok 65 Set SVE VL 256
1793 11:43:39.326373 # ok 66 Set and get SVE data for VL 256
1794 11:43:39.326486 # ok 67 Set and get FPSIMD data for SVE VL 256
1795 11:43:39.326599 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1796 11:43:39.326712 # ok 69 Set SVE VL 272
1797 11:43:39.326822 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1798 11:43:39.326934 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1799 11:43:39.327046 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1800 11:43:39.327157 # ok 73 Set SVE VL 288
1801 11:43:39.327294 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1802 11:43:39.327416 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1803 11:43:39.330231 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1804 11:43:39.330415 # ok 77 Set SVE VL 304
1805 11:43:39.330774 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1806 11:43:39.330916 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1807 11:43:39.331042 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1808 11:43:39.331163 # ok 81 Set SVE VL 320
1809 11:43:39.331301 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1810 11:43:39.331419 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1811 11:43:39.331534 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1812 11:43:39.331648 # ok 85 Set SVE VL 336
1813 11:43:39.331785 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1814 11:43:39.331947 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1815 11:43:39.332117 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1816 11:43:39.332260 # ok 89 Set SVE VL 352
1817 11:43:39.332385 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1818 11:43:39.332547 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1819 11:43:39.332745 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1820 11:43:39.332904 # ok 93 Set SVE VL 368
1821 11:43:39.333023 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1822 11:43:39.333137 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1823 11:43:39.333251 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1824 11:43:39.333362 # ok 97 Set SVE VL 384
1825 11:43:39.333476 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1826 11:43:39.333659 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1827 11:43:39.333821 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1828 11:43:39.333942 # ok 101 Set SVE VL 400
1829 11:43:39.334056 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1830 11:43:39.338332 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1831 11:43:39.338758 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1832 11:43:39.338919 # ok 105 Set SVE VL 416
1833 11:43:39.339101 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1834 11:43:39.339266 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1835 11:43:39.339450 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1836 11:43:39.339600 # ok 109 Set SVE VL 432
1837 11:43:39.339725 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1838 11:43:39.339845 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1839 11:43:39.339960 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1840 11:43:39.340090 # ok 113 Set SVE VL 448
1841 11:43:39.340216 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1842 11:43:39.340399 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1843 11:43:39.340551 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1844 11:43:39.340688 # ok 117 Set SVE VL 464
1845 11:43:39.340839 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1846 11:43:39.340976 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1847 11:43:39.341150 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1848 11:43:39.341340 # ok 121 Set SVE VL 480
1849 11:43:39.341505 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1850 11:43:39.341657 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1851 11:43:39.341845 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1852 11:43:39.341969 # ok 125 Set SVE VL 496
1853 11:43:39.342081 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1854 11:43:39.342191 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1855 11:43:39.342302 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1856 11:43:39.342411 # ok 129 Set SVE VL 512
1857 11:43:39.342520 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1858 11:43:39.342629 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1859 11:43:39.342738 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1860 11:43:39.342847 # ok 133 Set SVE VL 528
1861 11:43:39.342955 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1862 11:43:39.343064 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1863 11:43:39.348069 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1864 11:43:39.348241 # ok 137 Set SVE VL 544
1865 11:43:39.348663 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1866 11:43:39.348841 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1867 11:43:39.349035 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1868 11:43:39.349205 # ok 141 Set SVE VL 560
1869 11:43:39.349367 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1870 11:43:39.349558 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1871 11:43:39.349713 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1872 11:43:39.349833 # ok 145 Set SVE VL 576
1873 11:43:39.350013 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1874 11:43:39.350180 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1875 11:43:39.350358 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1876 11:43:39.350543 # ok 149 Set SVE VL 592
1877 11:43:39.350748 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1878 11:43:39.350920 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1879 11:43:39.351077 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1880 11:43:39.351268 # ok 153 Set SVE VL 608
1881 11:43:39.351415 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1882 11:43:39.351565 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1883 11:43:39.351719 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1884 11:43:39.351877 # ok 157 Set SVE VL 624
1885 11:43:39.352083 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1886 11:43:39.352251 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1887 11:43:39.352428 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1888 11:43:39.352574 # ok 161 Set SVE VL 640
1889 11:43:39.352727 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1890 11:43:39.352876 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1891 11:43:39.353048 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1892 11:43:39.353241 # ok 165 Set SVE VL 656
1893 11:43:39.353437 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1894 11:43:39.353596 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1895 11:43:39.353827 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1896 11:43:39.354017 # ok 169 Set SVE VL 672
1897 11:43:39.354193 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1898 11:43:39.354373 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1899 11:43:39.354511 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1900 11:43:39.354648 # ok 173 Set SVE VL 688
1901 11:43:39.354783 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1902 11:43:39.354920 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1903 11:43:39.355058 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1904 11:43:39.355196 # ok 177 Set SVE VL 704
1905 11:43:39.355332 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1906 11:43:39.355467 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1907 11:43:39.355602 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1908 11:43:39.355739 # ok 181 Set SVE VL 720
1909 11:43:39.356092 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1910 11:43:39.356225 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1911 11:43:39.356364 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1912 11:43:39.356503 # ok 185 Set SVE VL 736
1913 11:43:39.356640 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1914 11:43:39.356777 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1915 11:43:39.356914 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1916 11:43:39.357051 # ok 189 Set SVE VL 752
1917 11:43:39.357186 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1918 11:43:39.357322 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1919 11:43:39.362246 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1920 11:43:39.362651 # ok 193 Set SVE VL 768
1921 11:43:39.362841 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1922 11:43:39.363003 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1923 11:43:39.363155 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1924 11:43:39.363311 # ok 197 Set SVE VL 784
1925 11:43:39.363473 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1926 11:43:39.363625 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1927 11:43:39.363758 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1928 11:43:39.363905 # ok 201 Set SVE VL 800
1929 11:43:39.364036 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1930 11:43:39.364165 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1931 11:43:39.364277 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1932 11:43:39.364450 # ok 205 Set SVE VL 816
1933 11:43:39.364661 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1934 11:43:39.364827 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1935 11:43:39.364993 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1936 11:43:39.365162 # ok 209 Set SVE VL 832
1937 11:43:39.365313 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1938 11:43:39.365496 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1939 11:43:39.365701 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1940 11:43:39.365842 # ok 213 Set SVE VL 848
1941 11:43:39.365968 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1942 11:43:39.366089 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1943 11:43:39.366201 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1944 11:43:39.366381 # ok 217 Set SVE VL 864
1945 11:43:39.366577 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1946 11:43:39.366714 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1947 11:43:39.366833 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1948 11:43:39.366937 # ok 221 Set SVE VL 880
1949 11:43:39.367029 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1950 11:43:39.367119 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1951 11:43:39.367209 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1952 11:43:39.367300 # ok 225 Set SVE VL 896
1953 11:43:39.367388 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1954 11:43:39.367482 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1955 11:43:39.367570 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1956 11:43:39.372282 # ok 229 Set SVE VL 912
1957 11:43:39.372739 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1958 11:43:39.372930 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1959 11:43:39.373062 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1960 11:43:39.373205 # ok 233 Set SVE VL 928
1961 11:43:39.373336 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1962 11:43:39.373528 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1963 11:43:39.373720 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1964 11:43:39.373910 # ok 237 Set SVE VL 944
1965 11:43:39.374091 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1966 11:43:39.374283 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1967 11:43:39.374467 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1968 11:43:39.374635 # ok 241 Set SVE VL 960
1969 11:43:39.374794 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1970 11:43:39.374964 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1971 11:43:39.375194 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1972 11:43:39.375387 # ok 245 Set SVE VL 976
1973 11:43:39.375567 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1974 11:43:39.375771 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1975 11:43:39.375956 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1976 11:43:39.376144 # ok 249 Set SVE VL 992
1977 11:43:39.376309 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1978 11:43:39.376476 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1979 11:43:39.376669 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1980 11:43:39.376838 # ok 253 Set SVE VL 1008
1981 11:43:39.377015 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1982 11:43:39.377160 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1983 11:43:39.377286 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1984 11:43:39.377426 # ok 257 Set SVE VL 1024
1985 11:43:39.377635 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1986 11:43:39.377885 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1987 11:43:39.378066 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1988 11:43:39.378212 # ok 261 Set SVE VL 1040
1989 11:43:39.378349 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1990 11:43:39.378487 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1991 11:43:39.378624 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1992 11:43:39.378761 # ok 265 Set SVE VL 1056
1993 11:43:39.378897 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1994 11:43:39.379032 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1995 11:43:39.379169 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1996 11:43:39.379305 # ok 269 Set SVE VL 1072
1997 11:43:39.379440 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
1998 11:43:39.379575 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
1999 11:43:39.379711 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2000 11:43:39.379847 # ok 273 Set SVE VL 1088
2001 11:43:39.380199 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2002 11:43:39.380334 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2003 11:43:39.380474 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2004 11:43:39.380612 # ok 277 Set SVE VL 1104
2005 11:43:39.380748 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2006 11:43:39.380885 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2007 11:43:39.381021 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2008 11:43:39.381157 # ok 281 Set SVE VL 1120
2009 11:43:39.381294 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2010 11:43:39.383851 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2011 11:43:39.384265 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2012 11:43:39.384469 # ok 285 Set SVE VL 1136
2013 11:43:39.384687 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2014 11:43:39.384859 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2015 11:43:39.384980 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2016 11:43:39.385093 # ok 289 Set SVE VL 1152
2017 11:43:39.385202 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2018 11:43:39.385311 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2019 11:43:39.385421 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2020 11:43:39.394467 # ok 293 Set SVE VL 1168
2021 11:43:39.394670 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2022 11:43:39.394809 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2023 11:43:39.394964 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2024 11:43:39.395094 # ok 297 Set SVE VL 1184
2025 11:43:39.395222 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2026 11:43:39.395393 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2027 11:43:39.395598 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2028 11:43:39.395791 # ok 301 Set SVE VL 1200
2029 11:43:39.395962 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2030 11:43:39.396160 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2031 11:43:39.396343 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2032 11:43:39.396510 # ok 305 Set SVE VL 1216
2033 11:43:39.396691 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2034 11:43:39.396824 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2035 11:43:39.396963 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2036 11:43:39.397101 # ok 309 Set SVE VL 1232
2037 11:43:39.397238 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2038 11:43:39.397375 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2039 11:43:39.397513 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2040 11:43:39.397660 # ok 313 Set SVE VL 1248
2041 11:43:39.397801 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2042 11:43:39.397937 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2043 11:43:39.398075 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2044 11:43:39.398254 # ok 317 Set SVE VL 1264
2045 11:43:39.398383 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2046 11:43:39.398521 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2047 11:43:39.398670 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2048 11:43:39.398859 # ok 321 Set SVE VL 1280
2049 11:43:39.399014 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2050 11:43:39.399154 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2051 11:43:39.399302 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2052 11:43:39.399447 # ok 325 Set SVE VL 1296
2053 11:43:39.399655 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2054 11:43:39.399832 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2055 11:43:39.399983 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2056 11:43:39.400130 # ok 329 Set SVE VL 1312
2057 11:43:39.400314 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2058 11:43:39.400477 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2059 11:43:39.400625 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2060 11:43:39.400771 # ok 333 Set SVE VL 1328
2061 11:43:39.400915 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2062 11:43:39.401061 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2063 11:43:39.401199 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2064 11:43:39.401613 # ok 337 Set SVE VL 1344
2065 11:43:39.401782 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2066 11:43:39.401905 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2067 11:43:39.402019 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2068 11:43:39.402131 # ok 341 Set SVE VL 1360
2069 11:43:39.402243 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2070 11:43:39.402355 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2071 11:43:39.402467 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2072 11:43:39.402579 # ok 345 Set SVE VL 1376
2073 11:43:39.402691 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2074 11:43:39.402803 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2075 11:43:39.402915 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2076 11:43:39.403029 # ok 349 Set SVE VL 1392
2077 11:43:39.403142 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2078 11:43:39.403253 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2079 11:43:39.403365 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2080 11:43:39.403476 # ok 353 Set SVE VL 1408
2081 11:43:39.403587 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2082 11:43:39.403698 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2083 11:43:39.403810 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2084 11:43:39.403921 # ok 357 Set SVE VL 1424
2085 11:43:39.404033 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2086 11:43:39.404146 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2087 11:43:39.404258 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2088 11:43:39.404395 # ok 361 Set SVE VL 1440
2089 11:43:39.404514 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2090 11:43:39.410118 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2091 11:43:39.410301 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2092 11:43:39.410477 # ok 365 Set SVE VL 1456
2093 11:43:39.410702 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2094 11:43:39.410896 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2095 11:43:39.411062 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2096 11:43:39.411256 # ok 369 Set SVE VL 1472
2097 11:43:39.411422 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2098 11:43:39.411577 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2099 11:43:39.411776 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2100 11:43:39.411941 # ok 373 Set SVE VL 1488
2101 11:43:39.412086 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2102 11:43:39.412273 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2103 11:43:39.412467 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2104 11:43:39.412645 # ok 377 Set SVE VL 1504
2105 11:43:39.412781 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2106 11:43:39.412923 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2107 11:43:39.413065 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2108 11:43:39.413207 # ok 381 Set SVE VL 1520
2109 11:43:39.413353 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2110 11:43:39.413547 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2111 11:43:39.413745 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2112 11:43:39.413926 # ok 385 Set SVE VL 1536
2113 11:43:39.414104 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2114 11:43:39.414251 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2115 11:43:39.414416 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2116 11:43:39.414573 # ok 389 Set SVE VL 1552
2117 11:43:39.414727 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2118 11:43:39.414879 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2119 11:43:39.415031 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2120 11:43:39.415179 # ok 393 Set SVE VL 1568
2121 11:43:39.415330 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2122 11:43:39.415489 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2123 11:43:39.415684 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2124 11:43:39.415855 # ok 397 Set SVE VL 1584
2125 11:43:39.416001 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2126 11:43:39.416150 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2127 11:43:39.416326 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2128 11:43:39.416458 # ok 401 Set SVE VL 1600
2129 11:43:39.416600 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2130 11:43:39.416753 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2131 11:43:39.416884 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2132 11:43:39.417027 # ok 405 Set SVE VL 1616
2133 11:43:39.417170 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2134 11:43:39.417606 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2135 11:43:39.417828 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2136 11:43:39.417963 # ok 409 Set SVE VL 1632
2137 11:43:39.418079 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2138 11:43:39.418191 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2139 11:43:39.418302 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2140 11:43:39.418415 # ok 413 Set SVE VL 1648
2141 11:43:39.418526 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2142 11:43:39.418637 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2143 11:43:39.418750 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2144 11:43:39.418862 # ok 417 Set SVE VL 1664
2145 11:43:39.418976 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2146 11:43:39.419089 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2147 11:43:39.419200 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2148 11:43:39.419375 # ok 421 Set SVE VL 1680
2149 11:43:39.419515 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2150 11:43:39.419631 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2151 11:43:39.419743 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2152 11:43:39.419856 # ok 425 Set SVE VL 1696
2153 11:43:39.419969 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2154 11:43:39.420082 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2155 11:43:39.420195 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2156 11:43:39.420308 # ok 429 Set SVE VL 1712
2157 11:43:39.420419 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2158 11:43:39.420530 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2159 11:43:39.420643 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2160 11:43:39.420756 # ok 433 Set SVE VL 1728
2161 11:43:39.420868 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2162 11:43:39.420980 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2163 11:43:39.421091 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2164 11:43:39.421203 # ok 437 Set SVE VL 1744
2165 11:43:39.421315 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2166 11:43:39.422154 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2167 11:43:39.422551 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2168 11:43:39.422749 # ok 441 Set SVE VL 1760
2169 11:43:39.422910 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2170 11:43:39.423069 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2171 11:43:39.423260 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2172 11:43:39.423423 # ok 445 Set SVE VL 1776
2173 11:43:39.423583 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2174 11:43:39.423742 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2175 11:43:39.423884 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2176 11:43:39.424025 # ok 449 Set SVE VL 1792
2177 11:43:39.424208 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2178 11:43:39.424439 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2179 11:43:39.424602 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2180 11:43:39.424750 # ok 453 Set SVE VL 1808
2181 11:43:39.424905 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2182 11:43:39.425081 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2183 11:43:39.425247 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2184 11:43:39.425412 # ok 457 Set SVE VL 1824
2185 11:43:39.425606 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2186 11:43:39.425796 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2187 11:43:39.425961 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2188 11:43:39.426082 # ok 461 Set SVE VL 1840
2189 11:43:39.426222 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2190 11:43:39.426326 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2191 11:43:39.426435 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2192 11:43:39.426544 # ok 465 Set SVE VL 1856
2193 11:43:39.426650 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2194 11:43:39.426758 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2195 11:43:39.426865 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2196 11:43:39.426972 # ok 469 Set SVE VL 1872
2197 11:43:39.427081 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2198 11:43:39.427188 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2199 11:43:39.427295 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2200 11:43:39.427404 # ok 473 Set SVE VL 1888
2201 11:43:39.427511 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2202 11:43:39.429939 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2203 11:43:39.430246 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2204 11:43:39.430346 # ok 477 Set SVE VL 1904
2205 11:43:39.430447 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2206 11:43:39.430552 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2207 11:43:39.438126 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2208 11:43:39.438323 # ok 481 Set SVE VL 1920
2209 11:43:39.438535 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2210 11:43:39.438720 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2211 11:43:39.438913 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2212 11:43:39.439113 # ok 485 Set SVE VL 1936
2213 11:43:39.439320 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2214 11:43:39.439538 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2215 11:43:39.439699 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2216 11:43:39.439892 # ok 489 Set SVE VL 1952
2217 11:43:39.440078 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2218 11:43:39.440245 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2219 11:43:39.440385 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2220 11:43:39.440546 # ok 493 Set SVE VL 1968
2221 11:43:39.440751 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2222 11:43:39.440916 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2223 11:43:39.441089 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2224 11:43:39.441208 # ok 497 Set SVE VL 1984
2225 11:43:39.441301 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2226 11:43:39.441393 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2227 11:43:39.441487 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2228 11:43:39.441581 # ok 501 Set SVE VL 2000
2229 11:43:39.441684 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2230 11:43:39.441777 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2231 11:43:39.441864 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2232 11:43:39.441949 # ok 505 Set SVE VL 2016
2233 11:43:39.442040 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2234 11:43:39.442106 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2235 11:43:39.442187 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2236 11:43:39.442253 # ok 509 Set SVE VL 2032
2237 11:43:39.442317 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2238 11:43:39.442381 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2239 11:43:39.442443 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2240 11:43:39.442508 # ok 513 Set SVE VL 2048
2241 11:43:39.442603 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2242 11:43:39.442696 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2243 11:43:39.442791 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2244 11:43:39.442867 # ok 517 Set SVE VL 2064
2245 11:43:39.442944 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2246 11:43:39.443044 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2247 11:43:39.443128 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2248 11:43:39.443219 # ok 521 Set SVE VL 2080
2249 11:43:39.443300 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2250 11:43:39.443371 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2251 11:43:39.443657 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2252 11:43:39.443754 # ok 525 Set SVE VL 2096
2253 11:43:39.443839 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2254 11:43:39.443909 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2255 11:43:39.443976 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2256 11:43:39.444046 # ok 529 Set SVE VL 2112
2257 11:43:39.444109 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2258 11:43:39.444179 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2259 11:43:39.444260 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2260 11:43:39.444337 # ok 533 Set SVE VL 2128
2261 11:43:39.444398 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2262 11:43:39.444458 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2263 11:43:39.444536 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2264 11:43:39.444601 # ok 537 Set SVE VL 2144
2265 11:43:39.444667 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2266 11:43:39.444725 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2267 11:43:39.444797 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2268 11:43:39.444876 # ok 541 Set SVE VL 2160
2269 11:43:39.444950 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2270 11:43:39.445026 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2271 11:43:39.445108 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2272 11:43:39.445189 # ok 545 Set SVE VL 2176
2273 11:43:39.445288 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2274 11:43:39.445360 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2275 11:43:39.445436 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2276 11:43:39.445501 # ok 549 Set SVE VL 2192
2277 11:43:39.445566 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2278 11:43:39.445657 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2279 11:43:39.445766 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2280 11:43:39.445862 # ok 553 Set SVE VL 2208
2281 11:43:39.445955 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2282 11:43:39.449976 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2283 11:43:39.450258 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2284 11:43:39.450345 # ok 557 Set SVE VL 2224
2285 11:43:39.450442 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2286 11:43:39.450550 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2287 11:43:39.450639 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2288 11:43:39.450718 # ok 561 Set SVE VL 2240
2289 11:43:39.450837 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2290 11:43:39.450930 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2291 11:43:39.451088 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2292 11:43:39.451232 # ok 565 Set SVE VL 2256
2293 11:43:39.451369 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2294 11:43:39.451547 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2295 11:43:39.451673 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2296 11:43:39.451814 # ok 569 Set SVE VL 2272
2297 11:43:39.451945 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2298 11:43:39.452072 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2299 11:43:39.452197 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2300 11:43:39.452342 # ok 573 Set SVE VL 2288
2301 11:43:39.452462 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2302 11:43:39.452583 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2303 11:43:39.452708 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2304 11:43:39.452815 # ok 577 Set SVE VL 2304
2305 11:43:39.452938 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2306 11:43:39.453072 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2307 11:43:39.453212 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2308 11:43:39.453350 # ok 581 Set SVE VL 2320
2309 11:43:39.453463 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2310 11:43:39.453580 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2311 11:43:39.454099 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2312 11:43:39.454229 # ok 585 Set SVE VL 2336
2313 11:43:39.454339 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2314 11:43:39.454446 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2315 11:43:39.454552 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2316 11:43:39.454660 # ok 589 Set SVE VL 2352
2317 11:43:39.454766 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2318 11:43:39.454899 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2319 11:43:39.455002 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2320 11:43:39.455110 # ok 593 Set SVE VL 2368
2321 11:43:39.457923 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2322 11:43:39.458349 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2323 11:43:39.458527 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2324 11:43:39.458707 # ok 597 Set SVE VL 2384
2325 11:43:39.458878 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2326 11:43:39.459118 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2327 11:43:39.459288 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2328 11:43:39.459437 # ok 601 Set SVE VL 2400
2329 11:43:39.459591 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2330 11:43:39.459747 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2331 11:43:39.459900 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2332 11:43:39.460055 # ok 605 Set SVE VL 2416
2333 11:43:39.460215 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2334 11:43:39.460440 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2335 11:43:39.460613 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2336 11:43:39.460781 # ok 609 Set SVE VL 2432
2337 11:43:39.460927 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2338 11:43:39.461065 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2339 11:43:39.461192 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2340 11:43:39.461303 # ok 613 Set SVE VL 2448
2341 11:43:39.461436 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2342 11:43:39.461575 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2343 11:43:39.462156 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2344 11:43:39.462285 # ok 617 Set SVE VL 2464
2345 11:43:39.462396 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2346 11:43:39.462506 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2347 11:43:39.462645 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2348 11:43:39.462761 # ok 621 Set SVE VL 2480
2349 11:43:39.462872 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2350 11:43:39.462982 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2351 11:43:39.463092 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2352 11:43:39.463201 # ok 625 Set SVE VL 2496
2353 11:43:39.463310 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2354 11:43:39.463419 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2355 11:43:39.463528 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2356 11:43:39.463635 # ok 629 Set SVE VL 2512
2357 11:43:39.463743 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2358 11:43:39.463851 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2359 11:43:39.466131 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2360 11:43:39.466542 # ok 633 Set SVE VL 2528
2361 11:43:39.466728 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2362 11:43:39.466914 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2363 11:43:39.467082 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2364 11:43:39.467264 # ok 637 Set SVE VL 2544
2365 11:43:39.467424 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2366 11:43:39.467603 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2367 11:43:39.467755 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2368 11:43:39.467897 # ok 641 Set SVE VL 2560
2369 11:43:39.468088 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2370 11:43:39.468250 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2371 11:43:39.468391 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2372 11:43:39.468591 # ok 645 Set SVE VL 2576
2373 11:43:39.468809 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2374 11:43:39.468983 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2375 11:43:39.469159 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2376 11:43:39.469324 # ok 649 Set SVE VL 2592
2377 11:43:39.469542 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2378 11:43:39.469741 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2379 11:43:39.469933 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2380 11:43:39.470107 # ok 653 Set SVE VL 2608
2381 11:43:39.470250 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2382 11:43:39.470385 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2383 11:43:39.471247 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2384 11:43:39.471603 # ok 657 Set SVE VL 2624
2385 11:43:39.471831 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2386 11:43:39.472026 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2387 11:43:39.472243 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2388 11:43:39.472386 # ok 661 Set SVE VL 2640
2389 11:43:39.472517 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2390 11:43:39.472644 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2391 11:43:39.472771 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2392 11:43:39.472899 # ok 665 Set SVE VL 2656
2393 11:43:39.473026 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2394 11:43:39.478269 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2395 11:43:39.478633 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2396 11:43:39.478792 # ok 669 Set SVE VL 2672
2397 11:43:39.478939 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2398 11:43:39.479108 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2399 11:43:39.479264 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2400 11:43:39.479383 # ok 673 Set SVE VL 2688
2401 11:43:39.479531 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2402 11:43:39.479678 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2403 11:43:39.479810 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2404 11:43:39.480000 # ok 677 Set SVE VL 2704
2405 11:43:39.480142 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2406 11:43:39.480272 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2407 11:43:39.480413 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2408 11:43:39.480540 # ok 681 Set SVE VL 2720
2409 11:43:39.480664 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2410 11:43:39.480789 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2411 11:43:39.480907 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2412 11:43:39.481025 # ok 685 Set SVE VL 2736
2413 11:43:39.481145 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2414 11:43:39.481272 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2415 11:43:39.481395 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2416 11:43:39.481517 # ok 689 Set SVE VL 2752
2417 11:43:39.481632 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2418 11:43:39.482172 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2419 11:43:39.482300 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2420 11:43:39.482425 # ok 693 Set SVE VL 2768
2421 11:43:39.482531 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2422 11:43:39.482638 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2423 11:43:39.482751 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2424 11:43:39.482867 # ok 697 Set SVE VL 2784
2425 11:43:39.482972 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2426 11:43:39.483074 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2427 11:43:39.483180 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2428 11:43:39.483289 # ok 701 Set SVE VL 2800
2429 11:43:39.483460 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2430 11:43:39.483618 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2431 11:43:39.483746 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2432 11:43:39.483864 # ok 705 Set SVE VL 2816
2433 11:43:39.483979 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2434 11:43:39.484091 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2435 11:43:39.484202 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2436 11:43:39.484306 # ok 709 Set SVE VL 2832
2437 11:43:39.484407 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2438 11:43:39.484777 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2439 11:43:39.484937 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2440 11:43:39.485077 # ok 713 Set SVE VL 2848
2441 11:43:39.485215 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2442 11:43:39.485360 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2443 11:43:39.485489 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2444 11:43:39.485614 # ok 717 Set SVE VL 2864
2445 11:43:39.485754 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2446 11:43:39.485891 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2447 11:43:39.486052 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2448 11:43:39.486196 # ok 721 Set SVE VL 2880
2449 11:43:39.486359 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2450 11:43:39.486516 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2451 11:43:39.486670 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2452 11:43:39.486822 # ok 725 Set SVE VL 2896
2453 11:43:39.486980 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2454 11:43:39.487114 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2455 11:43:39.487216 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2456 11:43:39.487383 # ok 729 Set SVE VL 2912
2457 11:43:39.487531 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2458 11:43:39.487673 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2459 11:43:39.487840 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2460 11:43:39.488010 # ok 733 Set SVE VL 2928
2461 11:43:39.488142 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2462 11:43:39.488280 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2463 11:43:39.488423 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2464 11:43:39.488577 # ok 737 Set SVE VL 2944
2465 11:43:39.488716 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2466 11:43:39.488855 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2467 11:43:39.489032 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2468 11:43:39.489176 # ok 741 Set SVE VL 2960
2469 11:43:39.489333 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2470 11:43:39.489493 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2471 11:43:39.490126 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2472 11:43:39.490216 # ok 745 Set SVE VL 2976
2473 11:43:39.490296 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2474 11:43:39.490363 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2475 11:43:39.490434 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2476 11:43:39.490507 # ok 749 Set SVE VL 2992
2477 11:43:39.490586 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2478 11:43:39.490658 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2479 11:43:39.490738 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2480 11:43:39.490809 # ok 753 Set SVE VL 3008
2481 11:43:39.490903 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2482 11:43:39.491256 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2483 11:43:39.491471 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2484 11:43:39.491676 # ok 757 Set SVE VL 3024
2485 11:43:39.491884 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2486 11:43:39.492043 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2487 11:43:39.492164 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2488 11:43:39.492304 # ok 761 Set SVE VL 3040
2489 11:43:39.492438 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2490 11:43:39.492564 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2491 11:43:39.492682 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2492 11:43:39.492806 # ok 765 Set SVE VL 3056
2493 11:43:39.492945 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2494 11:43:39.493114 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2495 11:43:39.493258 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2496 11:43:39.493379 # ok 769 Set SVE VL 3072
2497 11:43:39.493505 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2498 11:43:39.493624 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2499 11:43:39.493746 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2500 11:43:39.493869 # ok 773 Set SVE VL 3088
2501 11:43:39.493992 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2502 11:43:39.494089 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2503 11:43:39.494172 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2504 11:43:39.494270 # ok 777 Set SVE VL 3104
2505 11:43:39.494365 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2506 11:43:39.494444 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2507 11:43:39.494542 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2508 11:43:39.494646 # ok 781 Set SVE VL 3120
2509 11:43:39.494755 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2510 11:43:39.494864 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2511 11:43:39.494959 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2512 11:43:39.495056 # ok 785 Set SVE VL 3136
2513 11:43:39.495126 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2514 11:43:39.495185 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2515 11:43:39.495243 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2516 11:43:39.495301 # ok 789 Set SVE VL 3152
2517 11:43:39.495362 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2518 11:43:39.495420 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2519 11:43:39.495478 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2520 11:43:39.495544 # ok 793 Set SVE VL 3168
2521 11:43:39.495602 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2522 11:43:39.495660 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2523 11:43:39.495724 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2524 11:43:39.495783 # ok 797 Set SVE VL 3184
2525 11:43:39.495840 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2526 11:43:39.496118 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2527 11:43:39.496231 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2528 11:43:39.496318 # ok 801 Set SVE VL 3200
2529 11:43:39.496405 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2530 11:43:39.496492 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2531 11:43:39.496577 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2532 11:43:39.496661 # ok 805 Set SVE VL 3216
2533 11:43:39.496745 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2534 11:43:39.496830 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2535 11:43:39.496915 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2536 11:43:39.497001 # ok 809 Set SVE VL 3232
2537 11:43:39.497089 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2538 11:43:39.497174 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2539 11:43:39.497258 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2540 11:43:39.497342 # ok 813 Set SVE VL 3248
2541 11:43:39.497427 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2542 11:43:39.497512 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2543 11:43:39.497596 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2544 11:43:39.497694 # ok 817 Set SVE VL 3264
2545 11:43:39.497780 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2546 11:43:39.497863 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2547 11:43:39.497946 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2548 11:43:39.498030 # ok 821 Set SVE VL 3280
2549 11:43:39.498098 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2550 11:43:39.498155 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2551 11:43:39.498212 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2552 11:43:39.498269 # ok 825 Set SVE VL 3296
2553 11:43:39.498325 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2554 11:43:39.498382 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2555 11:43:39.498439 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2556 11:43:39.498496 # ok 829 Set SVE VL 3312
2557 11:43:39.498553 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2558 11:43:39.498610 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2559 11:43:39.498667 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2560 11:43:39.498725 # ok 833 Set SVE VL 3328
2561 11:43:39.498782 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2562 11:43:39.498839 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2563 11:43:39.498896 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2564 11:43:39.498953 # ok 837 Set SVE VL 3344
2565 11:43:39.499010 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2566 11:43:39.499067 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2567 11:43:39.499124 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2568 11:43:39.499182 # ok 841 Set SVE VL 3360
2569 11:43:39.499238 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2570 11:43:39.499476 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2571 11:43:39.499538 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2572 11:43:39.499595 # ok 845 Set SVE VL 3376
2573 11:43:39.499652 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2574 11:43:39.499709 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2575 11:43:39.499766 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2576 11:43:39.499823 # ok 849 Set SVE VL 3392
2577 11:43:39.499880 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2578 11:43:39.499937 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2579 11:43:39.499994 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2580 11:43:39.500061 # ok 853 Set SVE VL 3408
2581 11:43:39.500129 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2582 11:43:39.500228 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2583 11:43:39.500322 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2584 11:43:39.500401 # ok 857 Set SVE VL 3424
2585 11:43:39.500478 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2586 11:43:39.500776 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2587 11:43:39.500865 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2588 11:43:39.500936 # ok 861 Set SVE VL 3440
2589 11:43:39.501038 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2590 11:43:39.501145 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2591 11:43:39.501302 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2592 11:43:39.501390 # ok 865 Set SVE VL 3456
2593 11:43:39.501480 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2594 11:43:39.501572 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2595 11:43:39.501655 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2596 11:43:39.501728 # ok 869 Set SVE VL 3472
2597 11:43:39.501794 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2598 11:43:39.501864 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2599 11:43:39.502155 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2600 11:43:39.502342 # ok 873 Set SVE VL 3488
2601 11:43:39.502513 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2602 11:43:39.502729 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2603 11:43:39.502936 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2604 11:43:39.503129 # ok 877 Set SVE VL 3504
2605 11:43:39.503335 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2606 11:43:39.503504 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2607 11:43:39.503693 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2608 11:43:39.503862 # ok 881 Set SVE VL 3520
2609 11:43:39.504044 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2610 11:43:39.504256 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2611 11:43:39.504421 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2612 11:43:39.504564 # ok 885 Set SVE VL 3536
2613 11:43:39.504720 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2614 11:43:39.504868 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2615 11:43:39.505025 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2616 11:43:39.505180 # ok 889 Set SVE VL 3552
2617 11:43:39.505381 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2618 11:43:39.505585 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2619 11:43:39.505803 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2620 11:43:39.505989 # ok 893 Set SVE VL 3568
2621 11:43:39.506126 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2622 11:43:39.506240 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2623 11:43:39.506343 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2624 11:43:39.506450 # ok 897 Set SVE VL 3584
2625 11:43:39.506566 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2626 11:43:39.506669 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2627 11:43:39.506782 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2628 11:43:39.506891 # ok 901 Set SVE VL 3600
2629 11:43:39.507032 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2630 11:43:39.507177 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2631 11:43:39.507289 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2632 11:43:39.507401 # ok 905 Set SVE VL 3616
2633 11:43:39.507544 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2634 11:43:39.507667 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2635 11:43:39.507778 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2636 11:43:39.507875 # ok 909 Set SVE VL 3632
2637 11:43:39.507986 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2638 11:43:39.508129 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2639 11:43:39.508253 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2640 11:43:39.508371 # ok 913 Set SVE VL 3648
2641 11:43:39.508510 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2642 11:43:39.508662 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2643 11:43:39.509007 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2644 11:43:39.509132 # ok 917 Set SVE VL 3664
2645 11:43:39.509227 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2646 11:43:39.509331 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2647 11:43:39.509425 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2648 11:43:39.509527 # ok 921 Set SVE VL 3680
2649 11:43:39.509622 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2650 11:43:39.509709 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2651 11:43:39.509773 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2652 11:43:39.509830 # ok 925 Set SVE VL 3696
2653 11:43:39.509887 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2654 11:43:39.509945 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2655 11:43:39.510003 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2656 11:43:39.510063 # ok 929 Set SVE VL 3712
2657 11:43:39.510124 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2658 11:43:39.510182 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2659 11:43:39.510239 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2660 11:43:39.510332 # ok 933 Set SVE VL 3728
2661 11:43:39.510425 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2662 11:43:39.510505 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2663 11:43:39.510597 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2664 11:43:39.510692 # ok 937 Set SVE VL 3744
2665 11:43:39.510784 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2666 11:43:39.510886 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2667 11:43:39.510977 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2668 11:43:39.511077 # ok 941 Set SVE VL 3760
2669 11:43:39.511200 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2670 11:43:39.511288 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2671 11:43:39.511360 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2672 11:43:39.511419 # ok 945 Set SVE VL 3776
2673 11:43:39.511477 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2674 11:43:39.511534 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2675 11:43:39.511591 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2676 11:43:39.511648 # ok 949 Set SVE VL 3792
2677 11:43:39.511728 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2678 11:43:39.511806 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2679 11:43:39.511876 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2680 11:43:39.511947 # ok 953 Set SVE VL 3808
2681 11:43:39.512046 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2682 11:43:39.512161 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2683 11:43:39.512244 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2684 11:43:39.512344 # ok 957 Set SVE VL 3824
2685 11:43:39.512433 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2686 11:43:39.512517 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2687 11:43:39.512773 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2688 11:43:39.512852 # ok 961 Set SVE VL 3840
2689 11:43:39.512929 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2690 11:43:39.513014 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2691 11:43:39.513099 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2692 11:43:39.513175 # ok 965 Set SVE VL 3856
2693 11:43:39.513253 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2694 11:43:39.513327 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2695 11:43:39.513402 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2696 11:43:39.513498 # ok 969 Set SVE VL 3872
2697 11:43:39.513599 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2698 11:43:39.513679 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2699 11:43:39.513747 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2700 11:43:39.513807 # ok 973 Set SVE VL 3888
2701 11:43:39.513865 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2702 11:43:39.513923 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2703 11:43:39.513981 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2704 11:43:39.514039 # ok 977 Set SVE VL 3904
2705 11:43:39.514097 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2706 11:43:39.514185 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2707 11:43:39.514262 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2708 11:43:39.514336 # ok 981 Set SVE VL 3920
2709 11:43:39.514420 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2710 11:43:39.514488 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2711 11:43:39.514547 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2712 11:43:39.514605 # ok 985 Set SVE VL 3936
2713 11:43:39.514662 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2714 11:43:39.514721 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2715 11:43:39.514778 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2716 11:43:39.514848 # ok 989 Set SVE VL 3952
2717 11:43:39.514908 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2718 11:43:39.514970 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2719 11:43:39.515059 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2720 11:43:39.515132 # ok 993 Set SVE VL 3968
2721 11:43:39.515231 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2722 11:43:39.515311 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2723 11:43:39.515387 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2724 11:43:39.515463 # ok 997 Set SVE VL 3984
2725 11:43:39.515556 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2726 11:43:39.515629 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2727 11:43:39.515716 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2728 11:43:39.515811 # ok 1001 Set SVE VL 4000
2729 11:43:39.515909 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2730 11:43:39.515985 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2731 11:43:39.516257 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2732 11:43:39.516341 # ok 1005 Set SVE VL 4016
2733 11:43:39.516417 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2734 11:43:39.516510 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2735 11:43:39.516572 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2736 11:43:39.516643 # ok 1009 Set SVE VL 4032
2737 11:43:39.516717 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2738 11:43:39.516992 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2739 11:43:39.517109 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2740 11:43:39.517186 # ok 1013 Set SVE VL 4048
2741 11:43:39.517274 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2742 11:43:39.517347 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2743 11:43:39.517434 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2744 11:43:39.517522 # ok 1017 Set SVE VL 4064
2745 11:43:39.517610 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2746 11:43:39.517882 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2747 11:43:39.518179 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2748 11:43:39.518577 # ok 1021 Set SVE VL 4080
2749 11:43:39.518672 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2750 11:43:39.518751 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2751 11:43:39.518822 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2752 11:43:39.518896 # ok 1025 Set SVE VL 4096
2753 11:43:39.518973 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2754 11:43:39.519239 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2755 11:43:39.519336 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2756 11:43:39.519430 # ok 1029 Set SVE VL 4112
2757 11:43:39.519539 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2758 11:43:39.519638 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2759 11:43:39.519776 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2760 11:43:39.519867 # ok 1033 Set SVE VL 4128
2761 11:43:39.519974 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2762 11:43:39.520085 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2763 11:43:39.520183 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2764 11:43:39.520271 # ok 1037 Set SVE VL 4144
2765 11:43:39.520352 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2766 11:43:39.520414 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2767 11:43:39.520473 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2768 11:43:39.531757 # ok 1041 Set SVE VL 4160
2769 11:43:39.531849 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2770 11:43:39.531956 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2771 11:43:39.532056 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2772 11:43:39.532135 # ok 1045 Set SVE VL 4176
2773 11:43:39.532224 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2774 11:43:39.532309 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2775 11:43:39.532447 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2776 11:43:39.532525 # ok 1049 Set SVE VL 4192
2777 11:43:39.532616 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2778 11:43:39.532889 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2779 11:43:39.533213 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2780 11:43:39.533456 # ok 1053 Set SVE VL 4208
2781 11:43:39.533740 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2782 11:43:39.533971 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2783 11:43:39.534211 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2784 11:43:39.534368 # ok 1057 Set SVE VL 4224
2785 11:43:39.534517 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2786 11:43:39.534700 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2787 11:43:39.534876 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2788 11:43:39.534980 # ok 1061 Set SVE VL 4240
2789 11:43:39.535153 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2790 11:43:39.535314 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2791 11:43:39.535469 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2792 11:43:39.535588 # ok 1065 Set SVE VL 4256
2793 11:43:39.535726 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2794 11:43:39.535851 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2795 11:43:39.536005 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2796 11:43:39.536121 # ok 1069 Set SVE VL 4272
2797 11:43:39.536297 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2798 11:43:39.536451 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2799 11:43:39.536587 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2800 11:43:39.536717 # ok 1073 Set SVE VL 4288
2801 11:43:39.536879 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2802 11:43:39.537061 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2803 11:43:39.537248 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2804 11:43:39.537437 # ok 1077 Set SVE VL 4304
2805 11:43:39.537618 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2806 11:43:39.537767 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2807 11:43:39.537883 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2808 11:43:39.538059 # ok 1081 Set SVE VL 4320
2809 11:43:39.538210 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2810 11:43:39.538319 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2811 11:43:39.538399 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2812 11:43:39.538520 # ok 1085 Set SVE VL 4336
2813 11:43:39.538602 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2814 11:43:39.538719 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2815 11:43:39.538797 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2816 11:43:39.538915 # ok 1089 Set SVE VL 4352
2817 11:43:39.538999 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2818 11:43:39.539126 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2819 11:43:39.539217 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2820 11:43:39.539334 # ok 1093 Set SVE VL 4368
2821 11:43:39.539657 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2822 11:43:39.539752 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2823 11:43:39.539875 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2824 11:43:39.539957 # ok 1097 Set SVE VL 4384
2825 11:43:39.540067 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2826 11:43:39.540141 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2827 11:43:39.540251 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2828 11:43:39.540337 # ok 1101 Set SVE VL 4400
2829 11:43:39.540445 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2830 11:43:39.540530 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2831 11:43:39.540633 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2832 11:43:39.540708 # ok 1105 Set SVE VL 4416
2833 11:43:39.540820 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2834 11:43:39.540899 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2835 11:43:39.540995 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2836 11:43:39.541071 # ok 1109 Set SVE VL 4432
2837 11:43:39.541142 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2838 11:43:39.541233 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2839 11:43:39.541301 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2840 11:43:39.541399 # ok 1113 Set SVE VL 4448
2841 11:43:39.541484 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2842 11:43:39.541595 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2843 11:43:39.541676 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2844 11:43:39.541781 # ok 1117 Set SVE VL 4464
2845 11:43:39.541851 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2846 11:43:39.541920 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2847 11:43:39.541994 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2848 11:43:39.542052 # ok 1121 Set SVE VL 4480
2849 11:43:39.542140 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2850 11:43:39.542203 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2851 11:43:39.542260 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2852 11:43:39.542330 # ok 1125 Set SVE VL 4496
2853 11:43:39.542389 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2854 11:43:39.542445 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2855 11:43:39.542534 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2856 11:43:39.542617 # ok 1129 Set SVE VL 4512
2857 11:43:39.542718 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2858 11:43:39.542795 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2859 11:43:39.542871 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2860 11:43:39.542959 # ok 1133 Set SVE VL 4528
2861 11:43:39.543025 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2862 11:43:39.543125 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2863 11:43:39.543200 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2864 11:43:39.543518 # ok 1137 Set SVE VL 4544
2865 11:43:39.543617 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2866 11:43:39.543744 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2867 11:43:39.543843 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2868 11:43:39.543954 # ok 1141 Set SVE VL 4560
2869 11:43:39.544092 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2870 11:43:39.544185 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2871 11:43:39.544311 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2872 11:43:39.544417 # ok 1145 Set SVE VL 4576
2873 11:43:39.544549 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2874 11:43:39.544693 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2875 11:43:39.544780 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2876 11:43:39.544942 # ok 1149 Set SVE VL 4592
2877 11:43:39.545088 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2878 11:43:39.545181 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2879 11:43:39.545330 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2880 11:43:39.545512 # ok 1153 Set SVE VL 4608
2881 11:43:39.545671 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2882 11:43:39.545806 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2883 11:43:39.545877 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2884 11:43:39.545936 # ok 1157 Set SVE VL 4624
2885 11:43:39.546033 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2886 11:43:39.546091 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2887 11:43:39.546223 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2888 11:43:39.546321 # ok 1161 Set SVE VL 4640
2889 11:43:39.546481 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2890 11:43:39.546646 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2891 11:43:39.546791 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2892 11:43:39.546880 # ok 1165 Set SVE VL 4656
2893 11:43:39.546995 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2894 11:43:39.547090 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2895 11:43:39.547233 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2896 11:43:39.547343 # ok 1169 Set SVE VL 4672
2897 11:43:39.547443 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2898 11:43:39.547573 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2899 11:43:39.547656 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2900 11:43:39.547764 # ok 1173 Set SVE VL 4688
2901 11:43:39.547849 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2902 11:43:39.547929 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2903 11:43:39.548012 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2904 11:43:39.548099 # ok 1177 Set SVE VL 4704
2905 11:43:39.548181 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2906 11:43:39.548282 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2907 11:43:39.548563 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2908 11:43:39.548652 # ok 1181 Set SVE VL 4720
2909 11:43:39.548720 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2910 11:43:39.548793 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2911 11:43:39.548865 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2912 11:43:39.548930 # ok 1185 Set SVE VL 4736
2913 11:43:39.548995 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2914 11:43:39.549068 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2915 11:43:39.549139 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2916 11:43:39.549212 # ok 1189 Set SVE VL 4752
2917 11:43:39.549295 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2918 11:43:39.549360 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2919 11:43:39.549431 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2920 11:43:39.549509 # ok 1193 Set SVE VL 4768
2921 11:43:39.549588 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2922 11:43:39.549681 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2923 11:43:39.549758 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2924 11:43:39.549821 # ok 1197 Set SVE VL 4784
2925 11:43:39.549896 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2926 11:43:39.549977 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2927 11:43:39.550057 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2928 11:43:39.550132 # ok 1201 Set SVE VL 4800
2929 11:43:39.550191 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2930 11:43:39.550247 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2931 11:43:39.550303 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2932 11:43:39.550358 # ok 1205 Set SVE VL 4816
2933 11:43:39.550415 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2934 11:43:39.550486 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2935 11:43:39.550545 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2936 11:43:39.550602 # ok 1209 Set SVE VL 4832
2937 11:43:39.550658 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2938 11:43:39.550714 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2939 11:43:39.550770 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2940 11:43:39.550827 # ok 1213 Set SVE VL 4848
2941 11:43:39.550883 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2942 11:43:39.550939 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2943 11:43:39.550995 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2944 11:43:39.551053 # ok 1217 Set SVE VL 4864
2945 11:43:39.551109 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2946 11:43:39.551168 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2947 11:43:39.551224 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2948 11:43:39.551280 # ok 1221 Set SVE VL 4880
2949 11:43:39.551335 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2950 11:43:39.551570 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2951 11:43:39.559135 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2952 11:43:39.559334 # ok 1225 Set SVE VL 4896
2953 11:43:39.559495 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2954 11:43:39.559684 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2955 11:43:39.559852 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2956 11:43:39.560017 # ok 1229 Set SVE VL 4912
2957 11:43:39.560173 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2958 11:43:39.560339 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2959 11:43:39.560484 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2960 11:43:39.560675 # ok 1233 Set SVE VL 4928
2961 11:43:39.560837 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2962 11:43:39.560995 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2963 11:43:39.561148 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2964 11:43:39.561308 # ok 1237 Set SVE VL 4944
2965 11:43:39.561442 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2966 11:43:39.561564 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2967 11:43:39.561715 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2968 11:43:39.561840 # ok 1241 Set SVE VL 4960
2969 11:43:39.561954 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2970 11:43:39.562068 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2971 11:43:39.562180 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2972 11:43:39.562291 # ok 1245 Set SVE VL 4976
2973 11:43:39.562382 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2974 11:43:39.562469 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2975 11:43:39.562555 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2976 11:43:39.562642 # ok 1249 Set SVE VL 4992
2977 11:43:39.562729 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2978 11:43:39.562814 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2979 11:43:39.562902 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2980 11:43:39.562991 # ok 1253 Set SVE VL 5008
2981 11:43:39.563077 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2982 11:43:39.563164 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2983 11:43:39.563691 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2984 11:43:39.564058 # ok 1257 Set SVE VL 5024
2985 11:43:39.564197 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2986 11:43:39.564283 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2987 11:43:39.564361 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2988 11:43:39.564449 # ok 1261 Set SVE VL 5040
2989 11:43:39.564528 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2990 11:43:39.564599 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2991 11:43:39.564672 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2992 11:43:39.564745 # ok 1265 Set SVE VL 5056
2993 11:43:39.564839 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2994 11:43:39.564919 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2995 11:43:39.564999 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2996 11:43:39.565076 # ok 1269 Set SVE VL 5072
2997 11:43:39.565162 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
2998 11:43:39.565229 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
2999 11:43:39.565292 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3000 11:43:39.565369 # ok 1273 Set SVE VL 5088
3001 11:43:39.565445 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3002 11:43:39.565530 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3003 11:43:39.565615 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3004 11:43:39.565706 # ok 1277 Set SVE VL 5104
3005 11:43:39.565774 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3006 11:43:39.566646 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3007 11:43:39.566946 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3008 11:43:39.567042 # ok 1281 Set SVE VL 5120
3009 11:43:39.567131 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3010 11:43:39.567214 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3011 11:43:39.567290 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3012 11:43:39.567367 # ok 1285 Set SVE VL 5136
3013 11:43:39.567461 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3014 11:43:39.567570 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3015 11:43:39.567670 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3016 11:43:39.567780 # ok 1289 Set SVE VL 5152
3017 11:43:39.567877 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3018 11:43:39.567971 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3019 11:43:39.568049 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3020 11:43:39.568144 # ok 1293 Set SVE VL 5168
3021 11:43:39.568235 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3022 11:43:39.568321 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3023 11:43:39.568412 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3024 11:43:39.568526 # ok 1297 Set SVE VL 5184
3025 11:43:39.568628 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3026 11:43:39.568719 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3027 11:43:39.568819 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3028 11:43:39.568901 # ok 1301 Set SVE VL 5200
3029 11:43:39.568979 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3030 11:43:39.569060 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3031 11:43:39.569177 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3032 11:43:39.569291 # ok 1305 Set SVE VL 5216
3033 11:43:39.569403 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3034 11:43:39.569504 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3035 11:43:39.569603 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3036 11:43:39.569712 # ok 1309 Set SVE VL 5232
3037 11:43:39.569815 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3038 11:43:39.569881 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3039 11:43:39.569939 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3040 11:43:39.570002 # ok 1313 Set SVE VL 5248
3041 11:43:39.570076 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3042 11:43:39.570171 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3043 11:43:39.570292 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3044 11:43:39.570389 # ok 1317 Set SVE VL 5264
3045 11:43:39.570465 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3046 11:43:39.570553 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3047 11:43:39.570630 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3048 11:43:39.570717 # ok 1321 Set SVE VL 5280
3049 11:43:39.570792 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3050 11:43:39.571089 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3051 11:43:39.571191 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3052 11:43:39.571296 # ok 1325 Set SVE VL 5296
3053 11:43:39.571393 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3054 11:43:39.571502 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3055 11:43:39.571598 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3056 11:43:39.571680 # ok 1329 Set SVE VL 5312
3057 11:43:39.571772 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3058 11:43:39.571852 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3059 11:43:39.571932 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3060 11:43:39.572009 # ok 1333 Set SVE VL 5328
3061 11:43:39.572102 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3062 11:43:39.572192 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3063 11:43:39.572268 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3064 11:43:39.572364 # ok 1337 Set SVE VL 5344
3065 11:43:39.572444 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3066 11:43:39.572517 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3067 11:43:39.572600 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3068 11:43:39.572694 # ok 1341 Set SVE VL 5360
3069 11:43:39.572782 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3070 11:43:39.572870 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3071 11:43:39.572993 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3072 11:43:39.573071 # ok 1345 Set SVE VL 5376
3073 11:43:39.573145 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3074 11:43:39.573220 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3075 11:43:39.573299 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3076 11:43:39.573374 # ok 1349 Set SVE VL 5392
3077 11:43:39.573466 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3078 11:43:39.573542 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3079 11:43:39.573623 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3080 11:43:39.573696 # ok 1353 Set SVE VL 5408
3081 11:43:39.573762 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3082 11:43:39.573837 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3083 11:43:39.573900 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3084 11:43:39.574170 # ok 1357 Set SVE VL 5424
3085 11:43:39.574271 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3086 11:43:39.574347 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3087 11:43:39.574441 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3088 11:43:39.574524 # ok 1361 Set SVE VL 5440
3089 11:43:39.574621 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3090 11:43:39.574724 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3091 11:43:39.574800 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3092 11:43:39.574900 # ok 1365 Set SVE VL 5456
3093 11:43:39.574997 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3094 11:43:39.575084 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3095 11:43:39.575166 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3096 11:43:39.575262 # ok 1369 Set SVE VL 5472
3097 11:43:39.575350 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3098 11:43:39.575464 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3099 11:43:39.575600 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3100 11:43:39.575720 # ok 1373 Set SVE VL 5488
3101 11:43:39.575839 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3102 11:43:39.575941 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3103 11:43:39.576054 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3104 11:43:39.576141 # ok 1377 Set SVE VL 5504
3105 11:43:39.576226 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3106 11:43:39.576341 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3107 11:43:39.576432 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3108 11:43:39.576515 # ok 1381 Set SVE VL 5520
3109 11:43:39.576619 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3110 11:43:39.576714 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3111 11:43:39.576799 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3112 11:43:39.576905 # ok 1385 Set SVE VL 5536
3113 11:43:39.576986 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3114 11:43:39.577061 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3115 11:43:39.577171 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3116 11:43:39.577262 # ok 1389 Set SVE VL 5552
3117 11:43:39.577359 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3118 11:43:39.577453 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3119 11:43:39.577560 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3120 11:43:39.577877 # ok 1393 Set SVE VL 5568
3121 11:43:39.577991 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3122 11:43:39.578081 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3123 11:43:39.578174 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3124 11:43:39.578287 # ok 1397 Set SVE VL 5584
3125 11:43:39.578370 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3126 11:43:39.578448 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3127 11:43:39.578727 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3128 11:43:39.578822 # ok 1401 Set SVE VL 5600
3129 11:43:39.578889 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3130 11:43:39.578948 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3131 11:43:39.579006 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3132 11:43:39.579065 # ok 1405 Set SVE VL 5616
3133 11:43:39.579134 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3134 11:43:39.600618 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3135 11:43:39.600728 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3136 11:43:39.600822 # ok 1409 Set SVE VL 5632
3137 11:43:39.600927 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3138 11:43:39.601035 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3139 11:43:39.601130 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3140 11:43:39.601263 # ok 1413 Set SVE VL 5648
3141 11:43:39.601354 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3142 11:43:39.601462 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3143 11:43:39.601557 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3144 11:43:39.601686 # ok 1417 Set SVE VL 5664
3145 11:43:39.601770 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3146 11:43:39.601834 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3147 11:43:39.601894 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3148 11:43:39.601963 # ok 1421 Set SVE VL 5680
3149 11:43:39.611605 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3150 11:43:39.612014 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3151 11:43:39.612128 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3152 11:43:39.612233 # ok 1425 Set SVE VL 5696
3153 11:43:39.612329 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3154 11:43:39.612427 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3155 11:43:39.612521 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3156 11:43:39.612617 # ok 1429 Set SVE VL 5712
3157 11:43:39.612713 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3158 11:43:39.612812 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3159 11:43:39.612892 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3160 11:43:39.631230 # ok 1433 Set SVE VL 5728
3161 11:43:39.631438 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3162 11:43:39.631520 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3163 11:43:39.631639 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3164 11:43:39.631720 # ok 1437 Set SVE VL 5744
3165 11:43:39.631796 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3166 11:43:39.631869 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3167 11:43:39.631942 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3168 11:43:39.632014 # ok 1441 Set SVE VL 5760
3169 11:43:39.632088 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3170 11:43:39.632165 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3171 11:43:39.632250 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3172 11:43:39.632347 # ok 1445 Set SVE VL 5776
3173 11:43:39.632433 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3174 11:43:39.632501 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3175 11:43:39.632570 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3176 11:43:39.632630 # ok 1449 Set SVE VL 5792
3177 11:43:39.632700 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3178 11:43:39.632765 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3179 11:43:39.632833 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3180 11:43:39.632910 # ok 1453 Set SVE VL 5808
3181 11:43:39.632981 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3182 11:43:39.633059 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3183 11:43:39.633140 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3184 11:43:39.633219 # ok 1457 Set SVE VL 5824
3185 11:43:39.633296 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3186 11:43:39.633372 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3187 11:43:39.633453 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3188 11:43:39.633534 # ok 1461 Set SVE VL 5840
3189 11:43:39.633614 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3190 11:43:39.633715 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3191 11:43:39.633790 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3192 11:43:39.633850 # ok 1465 Set SVE VL 5856
3193 11:43:39.634112 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3194 11:43:39.634177 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3195 11:43:39.634236 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3196 11:43:39.634295 # ok 1469 Set SVE VL 5872
3197 11:43:39.634353 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3198 11:43:39.634410 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3199 11:43:39.634467 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3200 11:43:39.634525 # ok 1473 Set SVE VL 5888
3201 11:43:39.634599 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3202 11:43:39.634678 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3203 11:43:39.634756 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3204 11:43:39.634831 # ok 1477 Set SVE VL 5904
3205 11:43:39.634906 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3206 11:43:39.634976 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3207 11:43:39.635056 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3208 11:43:39.635134 # ok 1481 Set SVE VL 5920
3209 11:43:39.635210 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3210 11:43:39.635281 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3211 11:43:39.635360 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3212 11:43:39.635438 # ok 1485 Set SVE VL 5936
3213 11:43:39.635516 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3214 11:43:39.635597 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3215 11:43:39.635675 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3216 11:43:39.635752 # ok 1489 Set SVE VL 5952
3217 11:43:39.635828 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3218 11:43:39.635902 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3219 11:43:39.635979 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3220 11:43:39.636057 # ok 1493 Set SVE VL 5968
3221 11:43:39.636133 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3222 11:43:39.636209 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3223 11:43:39.636284 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3224 11:43:39.636360 # ok 1497 Set SVE VL 5984
3225 11:43:39.636437 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3226 11:43:39.636514 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3227 11:43:39.636593 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3228 11:43:39.636673 # ok 1501 Set SVE VL 6000
3229 11:43:39.636753 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3230 11:43:39.636831 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3231 11:43:39.636899 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3232 11:43:39.636967 # ok 1505 Set SVE VL 6016
3233 11:43:39.637045 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3234 11:43:39.637129 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3235 11:43:39.637205 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3236 11:43:39.637474 # ok 1509 Set SVE VL 6032
3237 11:43:39.637559 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3238 11:43:39.637639 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3239 11:43:39.637729 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3240 11:43:39.637790 # ok 1513 Set SVE VL 6048
3241 11:43:39.637847 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3242 11:43:39.637903 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3243 11:43:39.637960 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3244 11:43:39.638017 # ok 1517 Set SVE VL 6064
3245 11:43:39.638077 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3246 11:43:39.638137 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3247 11:43:39.638235 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3248 11:43:39.638346 # ok 1521 Set SVE VL 6080
3249 11:43:39.638439 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3250 11:43:39.638540 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3251 11:43:39.638626 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3252 11:43:39.638709 # ok 1525 Set SVE VL 6096
3253 11:43:39.638790 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3254 11:43:39.638853 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3255 11:43:39.638912 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3256 11:43:39.638971 # ok 1529 Set SVE VL 6112
3257 11:43:39.639030 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3258 11:43:39.639090 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3259 11:43:39.639148 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3260 11:43:39.639208 # ok 1533 Set SVE VL 6128
3261 11:43:39.639267 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3262 11:43:39.639326 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3263 11:43:39.639385 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3264 11:43:39.639445 # ok 1537 Set SVE VL 6144
3265 11:43:39.639504 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3266 11:43:39.639564 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3267 11:43:39.639622 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3268 11:43:39.639682 # ok 1541 Set SVE VL 6160
3269 11:43:39.639741 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3270 11:43:39.639799 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3271 11:43:39.639858 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3272 11:43:39.639917 # ok 1545 Set SVE VL 6176
3273 11:43:39.639976 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3274 11:43:39.640035 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3275 11:43:39.640094 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3276 11:43:39.640153 # ok 1549 Set SVE VL 6192
3277 11:43:39.640212 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3278 11:43:39.640271 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3279 11:43:39.640526 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3280 11:43:39.640592 # ok 1553 Set SVE VL 6208
3281 11:43:39.640653 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3282 11:43:39.640751 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3283 11:43:39.640844 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3284 11:43:39.640932 # ok 1557 Set SVE VL 6224
3285 11:43:39.641007 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3286 11:43:39.641091 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3287 11:43:39.641178 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3288 11:43:39.641268 # ok 1561 Set SVE VL 6240
3289 11:43:39.641356 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3290 11:43:39.641449 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3291 11:43:39.641541 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3292 11:43:39.641626 # ok 1565 Set SVE VL 6256
3293 11:43:39.641724 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3294 11:43:39.641792 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3295 11:43:39.641850 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3296 11:43:39.641908 # ok 1569 Set SVE VL 6272
3297 11:43:39.641965 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3298 11:43:39.642023 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3299 11:43:39.642081 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3300 11:43:39.642138 # ok 1573 Set SVE VL 6288
3301 11:43:39.642207 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3302 11:43:39.642273 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3303 11:43:39.642349 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3304 11:43:39.642430 # ok 1577 Set SVE VL 6304
3305 11:43:39.642504 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3306 11:43:39.642582 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3307 11:43:39.642657 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3308 11:43:39.642732 # ok 1581 Set SVE VL 6320
3309 11:43:39.642814 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3310 11:43:39.642897 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3311 11:43:39.642976 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3312 11:43:39.643044 # ok 1585 Set SVE VL 6336
3313 11:43:39.643113 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3314 11:43:39.643201 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3315 11:43:39.643291 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3316 11:43:39.643362 # ok 1589 Set SVE VL 6352
3317 11:43:39.643456 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3318 11:43:39.643535 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3319 11:43:39.643615 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3320 11:43:39.643701 # ok 1593 Set SVE VL 6368
3321 11:43:39.643778 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3322 11:43:39.644118 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3323 11:43:39.644314 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3324 11:43:39.644517 # ok 1597 Set SVE VL 6384
3325 11:43:39.644687 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3326 11:43:39.644857 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3327 11:43:39.645022 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3328 11:43:39.645190 # ok 1601 Set SVE VL 6400
3329 11:43:39.645352 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3330 11:43:39.645513 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3331 11:43:39.645695 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3332 11:43:39.645844 # ok 1605 Set SVE VL 6416
3333 11:43:39.646037 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3334 11:43:39.646210 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3335 11:43:39.646367 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3336 11:43:39.646512 # ok 1609 Set SVE VL 6432
3337 11:43:39.646677 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3338 11:43:39.646828 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3339 11:43:39.646952 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3340 11:43:39.647097 # ok 1613 Set SVE VL 6448
3341 11:43:39.647252 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3342 11:43:39.647405 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3343 11:43:39.647550 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3344 11:43:39.647685 # ok 1617 Set SVE VL 6464
3345 11:43:39.647879 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3346 11:43:39.648031 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3347 11:43:39.648180 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3348 11:43:39.648322 # ok 1621 Set SVE VL 6480
3349 11:43:39.648478 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3350 11:43:39.648642 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3351 11:43:39.648809 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3352 11:43:39.648973 # ok 1625 Set SVE VL 6496
3353 11:43:39.649140 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3354 11:43:39.649300 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3355 11:43:39.649427 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3356 11:43:39.649545 # ok 1629 Set SVE VL 6512
3357 11:43:39.649669 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3358 11:43:39.649774 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3359 11:43:39.649888 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3360 11:43:39.650004 # ok 1633 Set SVE VL 6528
3361 11:43:39.650119 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3362 11:43:39.650237 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3363 11:43:39.650352 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3364 11:43:39.650469 # ok 1637 Set SVE VL 6544
3365 11:43:39.650949 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3366 11:43:39.651083 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3367 11:43:39.651185 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3368 11:43:39.651292 # ok 1641 Set SVE VL 6560
3369 11:43:39.651389 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3370 11:43:39.651454 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3371 11:43:39.651515 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3372 11:43:39.651580 # ok 1645 Set SVE VL 6576
3373 11:43:39.651654 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3374 11:43:39.651720 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3375 11:43:39.651781 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3376 11:43:39.651842 # ok 1649 Set SVE VL 6592
3377 11:43:39.651915 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3378 11:43:39.651977 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3379 11:43:39.652043 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3380 11:43:39.652104 # ok 1653 Set SVE VL 6608
3381 11:43:39.652164 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3382 11:43:39.652224 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3383 11:43:39.652291 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3384 11:43:39.652356 # ok 1657 Set SVE VL 6624
3385 11:43:39.652422 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3386 11:43:39.652482 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3387 11:43:39.652542 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3388 11:43:39.652602 # ok 1661 Set SVE VL 6640
3389 11:43:39.652661 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3390 11:43:39.652721 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3391 11:43:39.652781 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3392 11:43:39.652841 # ok 1665 Set SVE VL 6656
3393 11:43:39.652902 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3394 11:43:39.652963 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3395 11:43:39.653024 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3396 11:43:39.653087 # ok 1669 Set SVE VL 6672
3397 11:43:39.653155 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3398 11:43:39.653216 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3399 11:43:39.653284 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3400 11:43:39.653346 # ok 1673 Set SVE VL 6688
3401 11:43:39.653414 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3402 11:43:39.653481 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3403 11:43:39.653544 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3404 11:43:39.653617 # ok 1677 Set SVE VL 6704
3405 11:43:39.653692 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3406 11:43:39.653754 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3407 11:43:39.654005 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3408 11:43:39.654075 # ok 1681 Set SVE VL 6720
3409 11:43:39.654145 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3410 11:43:39.654217 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3411 11:43:39.654297 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3412 11:43:39.654403 # ok 1685 Set SVE VL 6736
3413 11:43:39.654487 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3414 11:43:39.654559 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3415 11:43:39.654630 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3416 11:43:39.654701 # ok 1689 Set SVE VL 6752
3417 11:43:39.654772 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3418 11:43:39.654844 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3419 11:43:39.654907 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3420 11:43:39.654978 # ok 1693 Set SVE VL 6768
3421 11:43:39.655041 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3422 11:43:39.655112 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3423 11:43:39.655190 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3424 11:43:39.655258 # ok 1697 Set SVE VL 6784
3425 11:43:39.655329 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3426 11:43:39.655396 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3427 11:43:39.655463 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3428 11:43:39.655536 # ok 1701 Set SVE VL 6800
3429 11:43:39.655606 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3430 11:43:39.655678 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3431 11:43:39.655758 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3432 11:43:39.655834 # ok 1705 Set SVE VL 6816
3433 11:43:39.655908 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3434 11:43:39.655981 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3435 11:43:39.656047 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3436 11:43:39.656116 # ok 1709 Set SVE VL 6832
3437 11:43:39.656182 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3438 11:43:39.656271 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3439 11:43:39.656360 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3440 11:43:39.656441 # ok 1713 Set SVE VL 6848
3441 11:43:39.656513 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3442 11:43:39.656579 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3443 11:43:39.656640 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3444 11:43:39.656713 # ok 1717 Set SVE VL 6864
3445 11:43:39.656800 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3446 11:43:39.656874 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3447 11:43:39.656942 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3448 11:43:39.657020 # ok 1721 Set SVE VL 6880
3449 11:43:39.657095 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3450 11:43:39.657382 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3451 11:43:39.657479 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3452 11:43:39.657545 # ok 1725 Set SVE VL 6896
3453 11:43:39.657612 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3454 11:43:39.657682 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3455 11:43:39.657744 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3456 11:43:39.657803 # ok 1729 Set SVE VL 6912
3457 11:43:39.657863 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3458 11:43:39.657923 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3459 11:43:39.657982 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3460 11:43:39.658042 # ok 1733 Set SVE VL 6928
3461 11:43:39.658101 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3462 11:43:39.658160 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3463 11:43:39.658219 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3464 11:43:39.658279 # ok 1737 Set SVE VL 6944
3465 11:43:39.658338 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3466 11:43:39.658400 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3467 11:43:39.658462 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3468 11:43:39.658549 # ok 1741 Set SVE VL 6960
3469 11:43:39.658624 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3470 11:43:39.658686 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3471 11:43:39.658746 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3472 11:43:39.658819 # ok 1745 Set SVE VL 6976
3473 11:43:39.658882 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3474 11:43:39.658942 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3475 11:43:39.659002 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3476 11:43:39.659062 # ok 1749 Set SVE VL 6992
3477 11:43:39.659121 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3478 11:43:39.659199 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3479 11:43:39.659262 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3480 11:43:39.659323 # ok 1753 Set SVE VL 7008
3481 11:43:39.659384 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3482 11:43:39.659447 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3483 11:43:39.659506 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3484 11:43:39.659565 # ok 1757 Set SVE VL 7024
3485 11:43:39.659623 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3486 11:43:39.659683 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3487 11:43:39.659741 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3488 11:43:39.659800 # ok 1761 Set SVE VL 7040
3489 11:43:39.659858 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3490 11:43:39.659918 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3491 11:43:39.659976 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3492 11:43:39.660036 # ok 1765 Set SVE VL 7056
3493 11:43:39.660284 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3494 11:43:39.660349 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3495 11:43:39.660414 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3496 11:43:39.660477 # ok 1769 Set SVE VL 7072
3497 11:43:39.660538 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3498 11:43:39.660598 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3499 11:43:39.660658 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3500 11:43:39.661103 # ok 1773 Set SVE VL 7088
3501 11:43:39.661171 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3502 11:43:39.661233 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3503 11:43:39.661306 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3504 11:43:39.661368 # ok 1777 Set SVE VL 7104
3505 11:43:39.661440 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3506 11:43:39.661513 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3507 11:43:39.661587 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3508 11:43:39.661684 # ok 1781 Set SVE VL 7120
3509 11:43:39.661932 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3510 11:43:39.662407 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3511 11:43:39.662491 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3512 11:43:39.662553 # ok 1785 Set SVE VL 7136
3513 11:43:39.662644 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3514 11:43:39.662732 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3515 11:43:39.662848 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3516 11:43:39.662946 # ok 1789 Set SVE VL 7152
3517 11:43:39.663043 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3518 11:43:39.663130 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3519 11:43:39.663216 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3520 11:43:39.663322 # ok 1793 Set SVE VL 7168
3521 11:43:39.663423 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3522 11:43:39.663699 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3523 11:43:39.663781 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3524 11:43:39.663857 # ok 1797 Set SVE VL 7184
3525 11:43:39.663948 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3526 11:43:39.664029 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3527 11:43:39.664119 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3528 11:43:39.664190 # ok 1801 Set SVE VL 7200
3529 11:43:39.664279 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3530 11:43:39.664364 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3531 11:43:39.664454 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3532 11:43:39.664540 # ok 1805 Set SVE VL 7216
3533 11:43:39.664646 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3534 11:43:39.664955 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3535 11:43:39.665042 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3536 11:43:39.665163 # ok 1809 Set SVE VL 7232
3537 11:43:39.665247 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3538 11:43:39.665338 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3539 11:43:39.665413 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3540 11:43:39.665509 # ok 1813 Set SVE VL 7248
3541 11:43:39.665784 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3542 11:43:39.665871 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3543 11:43:39.665982 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3544 11:43:39.666070 # ok 1817 Set SVE VL 7264
3545 11:43:39.666196 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3546 11:43:39.666285 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3547 11:43:39.666391 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3548 11:43:39.666483 # ok 1821 Set SVE VL 7280
3549 11:43:39.666581 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3550 11:43:39.666657 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3551 11:43:39.666746 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3552 11:43:39.666838 # ok 1825 Set SVE VL 7296
3553 11:43:39.666917 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3554 11:43:39.667006 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3555 11:43:39.667099 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3556 11:43:39.667187 # ok 1829 Set SVE VL 7312
3557 11:43:39.667277 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3558 11:43:39.667568 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3559 11:43:39.667662 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3560 11:43:39.667751 # ok 1833 Set SVE VL 7328
3561 11:43:39.667850 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3562 11:43:39.667931 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3563 11:43:39.668025 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3564 11:43:39.668122 # ok 1837 Set SVE VL 7344
3565 11:43:39.668239 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3566 11:43:39.668563 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3567 11:43:39.668662 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3568 11:43:39.668748 # ok 1841 Set SVE VL 7360
3569 11:43:39.668870 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3570 11:43:39.668980 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3571 11:43:39.669090 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3572 11:43:39.669203 # ok 1845 Set SVE VL 7376
3573 11:43:39.669340 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3574 11:43:39.669438 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3575 11:43:39.669523 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3576 11:43:39.669607 # ok 1849 Set SVE VL 7392
3577 11:43:39.669726 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3578 11:43:39.669808 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3579 11:43:39.669874 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3580 11:43:39.669952 # ok 1853 Set SVE VL 7408
3581 11:43:39.670047 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3582 11:43:39.670139 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3583 11:43:39.670239 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3584 11:43:39.670338 # ok 1857 Set SVE VL 7424
3585 11:43:39.670435 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3586 11:43:39.673721 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3587 11:43:39.673827 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3588 11:43:39.673910 # ok 1861 Set SVE VL 7440
3589 11:43:39.673990 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3590 11:43:39.674070 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3591 11:43:39.674148 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3592 11:43:39.674227 # ok 1865 Set SVE VL 7456
3593 11:43:39.674305 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3594 11:43:39.674383 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3595 11:43:39.674462 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3596 11:43:39.674541 # ok 1869 Set SVE VL 7472
3597 11:43:39.674618 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3598 11:43:39.674697 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3599 11:43:39.674776 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3600 11:43:39.674855 # ok 1873 Set SVE VL 7488
3601 11:43:39.674932 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3602 11:43:39.675011 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3603 11:43:39.675089 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3604 11:43:39.675170 # ok 1877 Set SVE VL 7504
3605 11:43:39.675249 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3606 11:43:39.675328 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3607 11:43:39.675414 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3608 11:43:39.675493 # ok 1881 Set SVE VL 7520
3609 11:43:39.675571 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3610 11:43:39.675651 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3611 11:43:39.675730 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3612 11:43:39.675809 # ok 1885 Set SVE VL 7536
3613 11:43:39.675889 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3614 11:43:39.675970 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3615 11:43:39.676050 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3616 11:43:39.676130 # ok 1889 Set SVE VL 7552
3617 11:43:39.676230 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3618 11:43:39.676314 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3619 11:43:39.676395 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3620 11:43:39.676475 # ok 1893 Set SVE VL 7568
3621 11:43:39.676555 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3622 11:43:39.676635 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3623 11:43:39.676715 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3624 11:43:39.676796 # ok 1897 Set SVE VL 7584
3625 11:43:39.676876 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3626 11:43:39.676956 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3627 11:43:39.677036 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3628 11:43:39.677115 # ok 1901 Set SVE VL 7600
3629 11:43:39.677402 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3630 11:43:39.677505 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3631 11:43:39.677588 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3632 11:43:39.677678 # ok 1905 Set SVE VL 7616
3633 11:43:39.677760 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3634 11:43:39.677841 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3635 11:43:39.677922 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3636 11:43:39.677999 # ok 1909 Set SVE VL 7632
3637 11:43:39.678074 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3638 11:43:39.678150 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3639 11:43:39.678225 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3640 11:43:39.678301 # ok 1913 Set SVE VL 7648
3641 11:43:39.678375 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3642 11:43:39.678450 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3643 11:43:39.678524 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3644 11:43:39.678598 # ok 1917 Set SVE VL 7664
3645 11:43:39.678673 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3646 11:43:39.678748 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3647 11:43:39.678829 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3648 11:43:39.678918 # ok 1921 Set SVE VL 7680
3649 11:43:39.679009 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3650 11:43:39.679097 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3651 11:43:39.679169 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3652 11:43:39.679255 # ok 1925 Set SVE VL 7696
3653 11:43:39.679346 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3654 11:43:39.679440 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3655 11:43:39.679530 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3656 11:43:39.679618 # ok 1929 Set SVE VL 7712
3657 11:43:39.679708 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3658 11:43:39.679820 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3659 11:43:39.679930 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3660 11:43:39.680010 # ok 1933 Set SVE VL 7728
3661 11:43:39.680096 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3662 11:43:39.680183 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3663 11:43:39.680271 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3664 11:43:39.680373 # ok 1937 Set SVE VL 7744
3665 11:43:39.680459 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3666 11:43:39.680545 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3667 11:43:39.680631 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3668 11:43:39.680717 # ok 1941 Set SVE VL 7760
3669 11:43:39.680804 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3670 11:43:39.680890 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3671 11:43:39.680975 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3672 11:43:39.681259 # ok 1945 Set SVE VL 7776
3673 11:43:39.681360 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3674 11:43:39.681451 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3675 11:43:39.681540 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3676 11:43:39.681628 # ok 1949 Set SVE VL 7792
3677 11:43:39.681717 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3678 11:43:39.681797 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3679 11:43:39.681884 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3680 11:43:39.681967 # ok 1953 Set SVE VL 7808
3681 11:43:39.682049 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3682 11:43:39.682125 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3683 11:43:39.684881 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3684 11:43:39.685010 # ok 1957 Set SVE VL 7824
3685 11:43:39.685115 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3686 11:43:39.685211 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3687 11:43:39.685306 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3688 11:43:39.685740 # ok 1961 Set SVE VL 7840
3689 11:43:39.685907 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3690 11:43:39.686030 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3691 11:43:39.686172 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3692 11:43:39.686292 # ok 1965 Set SVE VL 7856
3693 11:43:39.686825 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3694 11:43:39.686989 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3695 11:43:39.687118 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3696 11:43:39.687259 # ok 1969 Set SVE VL 7872
3697 11:43:39.687382 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3698 11:43:39.687488 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3699 11:43:39.687588 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3700 11:43:39.687684 # ok 1973 Set SVE VL 7888
3701 11:43:39.687776 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3702 11:43:39.687869 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3703 11:43:39.688173 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3704 11:43:39.688261 # ok 1977 Set SVE VL 7904
3705 11:43:39.688341 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3706 11:43:39.688421 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3707 11:43:39.688500 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3708 11:43:39.688581 # ok 1981 Set SVE VL 7920
3709 11:43:39.688828 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3710 11:43:39.688909 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3711 11:43:39.689161 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3712 11:43:39.689228 # ok 1985 Set SVE VL 7936
3713 11:43:39.689300 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3714 11:43:39.689371 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3715 11:43:39.689626 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3716 11:43:39.689708 # ok 1989 Set SVE VL 7952
3717 11:43:39.689797 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3718 11:43:39.690116 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3719 11:43:39.690385 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3720 11:43:39.690481 # ok 1993 Set SVE VL 7968
3721 11:43:39.690567 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3722 11:43:39.690657 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3723 11:43:39.690923 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3724 11:43:39.690997 # ok 1997 Set SVE VL 7984
3725 11:43:39.691092 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3726 11:43:39.691354 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3727 11:43:39.691444 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3728 11:43:39.691527 # ok 2001 Set SVE VL 8000
3729 11:43:39.691608 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3730 11:43:39.691873 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3731 11:43:39.691957 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3732 11:43:39.692026 # ok 2005 Set SVE VL 8016
3733 11:43:39.692120 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3734 11:43:39.692387 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3735 11:43:39.692505 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3736 11:43:39.692606 # ok 2009 Set SVE VL 8032
3737 11:43:39.692699 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3738 11:43:39.692793 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3739 11:43:39.693068 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3740 11:43:39.693147 # ok 2013 Set SVE VL 8048
3741 11:43:39.693218 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3742 11:43:39.693296 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3743 11:43:39.693553 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3744 11:43:39.693627 # ok 2017 Set SVE VL 8064
3745 11:43:39.693725 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3746 11:43:39.694141 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3747 11:43:39.694218 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3748 11:43:39.694298 # ok 2021 Set SVE VL 8080
3749 11:43:39.694386 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3750 11:43:39.694670 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3751 11:43:39.694742 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3752 11:43:39.694813 # ok 2025 Set SVE VL 8096
3753 11:43:39.694884 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3754 11:43:39.695130 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3755 11:43:39.695204 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3756 11:43:39.695275 # ok 2029 Set SVE VL 8112
3757 11:43:39.695519 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3758 11:43:39.695795 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3759 11:43:39.695881 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3760 11:43:39.695945 # ok 2033 Set SVE VL 8128
3761 11:43:39.696017 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3762 11:43:39.696096 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3763 11:43:39.696386 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3764 11:43:39.696472 # ok 2037 Set SVE VL 8144
3765 11:43:39.696566 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3766 11:43:39.696660 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3767 11:43:39.696782 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3768 11:43:39.696909 # ok 2041 Set SVE VL 8160
3769 11:43:39.697222 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3770 11:43:39.697310 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3771 11:43:39.697411 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3772 11:43:39.697495 # ok 2045 Set SVE VL 8176
3773 11:43:39.697586 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3774 11:43:39.697681 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3775 11:43:39.697976 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3776 11:43:39.698251 # ok 2049 Set SVE VL 8192
3777 11:43:39.698342 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3778 11:43:39.698426 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3779 11:43:39.698511 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3780 11:43:39.698606 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3781 11:43:39.698765 # ok 2054 Streaming SVE get_fpsimd() gave same state
3782 11:43:39.698866 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3783 11:43:39.699143 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3784 11:43:39.699215 # ok 2057 Set Streaming SVE VL 16
3785 11:43:39.701834 # ok 2058 Set and get Streaming SVE data for VL 16
3786 11:43:39.701917 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3787 11:43:39.702013 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3788 11:43:39.702114 # ok 2061 Set Streaming SVE VL 32
3789 11:43:39.702200 # ok 2062 Set and get Streaming SVE data for VL 32
3790 11:43:39.702269 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3791 11:43:39.702333 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3792 11:43:39.702398 # ok 2065 Set Streaming SVE VL 48
3793 11:43:39.702479 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3794 11:43:39.702562 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3795 11:43:39.702628 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3796 11:43:39.702692 # ok 2069 Set Streaming SVE VL 64
3797 11:43:39.702757 # ok 2070 Set and get Streaming SVE data for VL 64
3798 11:43:39.702820 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3799 11:43:39.702880 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3800 11:43:39.702938 # ok 2073 Set Streaming SVE VL 80
3801 11:43:39.702996 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3802 11:43:39.703055 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3803 11:43:39.703113 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3804 11:43:39.703171 # ok 2077 Set Streaming SVE VL 96
3805 11:43:39.703230 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3806 11:43:39.703288 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3807 11:43:39.703346 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3808 11:43:39.703405 # ok 2081 Set Streaming SVE VL 112
3809 11:43:39.703463 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3810 11:43:39.703521 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3811 11:43:39.703580 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3812 11:43:39.703638 # ok 2085 Set Streaming SVE VL 128
3813 11:43:39.703696 # ok 2086 Set and get Streaming SVE data for VL 128
3814 11:43:39.703754 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3815 11:43:39.704012 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3816 11:43:39.704098 # ok 2089 Set Streaming SVE VL 144
3817 11:43:39.704170 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3818 11:43:39.704244 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3819 11:43:39.704321 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3820 11:43:39.704393 # ok 2093 Set Streaming SVE VL 160
3821 11:43:39.704456 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3822 11:43:39.704557 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3823 11:43:39.704642 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3824 11:43:39.704714 # ok 2097 Set Streaming SVE VL 176
3825 11:43:39.704803 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3826 11:43:39.704869 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3827 11:43:39.704929 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3828 11:43:39.704989 # ok 2101 Set Streaming SVE VL 192
3829 11:43:39.705048 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3830 11:43:39.705123 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3831 11:43:39.705186 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3832 11:43:39.705246 # ok 2105 Set Streaming SVE VL 208
3833 11:43:39.705305 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3834 11:43:39.705364 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3835 11:43:39.705423 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3836 11:43:39.705482 # ok 2109 Set Streaming SVE VL 224
3837 11:43:39.705540 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3838 11:43:39.705599 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3839 11:43:39.705679 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3840 11:43:39.705742 # ok 2113 Set Streaming SVE VL 240
3841 11:43:39.705801 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3842 11:43:39.705860 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3843 11:43:39.705918 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3844 11:43:39.705989 # ok 2117 Set Streaming SVE VL 256
3845 11:43:39.706060 # ok 2118 Set and get Streaming SVE data for VL 256
3846 11:43:39.706138 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3847 11:43:39.711486 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3848 11:43:39.711692 # ok 2121 Set Streaming SVE VL 272
3849 11:43:39.711755 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3850 11:43:39.711817 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3851 11:43:39.711880 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3852 11:43:39.711940 # ok 2125 Set Streaming SVE VL 288
3853 11:43:39.712191 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3854 11:43:39.713475 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3855 11:43:39.713578 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3856 11:43:39.713677 # ok 2129 Set Streaming SVE VL 304
3857 11:43:39.713773 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3858 11:43:39.713852 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3859 11:43:39.713929 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3860 11:43:39.714004 # ok 2133 Set Streaming SVE VL 320
3861 11:43:39.714078 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3862 11:43:39.714152 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3863 11:43:39.714227 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3864 11:43:39.714300 # ok 2137 Set Streaming SVE VL 336
3865 11:43:39.714374 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3866 11:43:39.714452 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3867 11:43:39.714548 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3868 11:43:39.714631 # ok 2141 Set Streaming SVE VL 352
3869 11:43:39.714708 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3870 11:43:39.714778 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3871 11:43:39.714858 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3872 11:43:39.714932 # ok 2145 Set Streaming SVE VL 368
3873 11:43:39.715199 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3874 11:43:39.715284 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3875 11:43:39.715363 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3876 11:43:39.715436 # ok 2149 Set Streaming SVE VL 384
3877 11:43:39.715530 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3878 11:43:39.715617 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3879 11:43:39.715687 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3880 11:43:39.715757 # ok 2153 Set Streaming SVE VL 400
3881 11:43:39.715824 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3882 11:43:39.715912 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3883 11:43:39.715996 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3884 11:43:39.716070 # ok 2157 Set Streaming SVE VL 416
3885 11:43:39.716137 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3886 11:43:39.716197 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3887 11:43:39.716270 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3888 11:43:39.716332 # ok 2161 Set Streaming SVE VL 432
3889 11:43:39.716391 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3890 11:43:39.716462 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3891 11:43:39.716733 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3892 11:43:39.716822 # ok 2165 Set Streaming SVE VL 448
3893 11:43:39.716895 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3894 11:43:39.716967 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3895 11:43:39.717229 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3896 11:43:39.717307 # ok 2169 Set Streaming SVE VL 464
3897 11:43:39.717379 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3898 11:43:39.717672 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3899 11:43:39.717792 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3900 11:43:39.718062 # ok 2173 Set Streaming SVE VL 480
3901 11:43:39.718169 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3902 11:43:39.718248 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3903 11:43:39.718333 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3904 11:43:39.718426 # ok 2177 Set Streaming SVE VL 496
3905 11:43:39.718694 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3906 11:43:39.718775 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3907 11:43:39.718862 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3908 11:43:39.718942 # ok 2181 Set Streaming SVE VL 512
3909 11:43:39.719036 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3910 11:43:39.719319 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3911 11:43:39.719420 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3912 11:43:39.719501 # ok 2185 Set Streaming SVE VL 528
3913 11:43:39.719590 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3914 11:43:39.719680 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3915 11:43:39.719771 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3916 11:43:39.719864 # ok 2189 Set Streaming SVE VL 544
3917 11:43:39.720161 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3918 11:43:39.720250 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3919 11:43:39.720342 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3920 11:43:39.720418 # ok 2193 Set Streaming SVE VL 560
3921 11:43:39.720508 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3922 11:43:39.720600 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3923 11:43:39.720693 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3924 11:43:39.720787 # ok 2197 Set Streaming SVE VL 576
3925 11:43:39.720880 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3926 11:43:39.720981 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3927 11:43:39.721256 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3928 11:43:39.721342 # ok 2201 Set Streaming SVE VL 592
3929 11:43:39.721440 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3930 11:43:39.721533 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3931 11:43:39.721632 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3932 11:43:39.721735 # ok 2205 Set Streaming SVE VL 608
3933 11:43:39.722012 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3934 11:43:39.722111 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3935 11:43:39.722204 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3936 11:43:39.722301 # ok 2209 Set Streaming SVE VL 624
3937 11:43:39.722400 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3938 11:43:39.722675 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3939 11:43:39.722761 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3940 11:43:39.722857 # ok 2213 Set Streaming SVE VL 640
3941 11:43:39.722949 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3942 11:43:39.723233 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3943 11:43:39.723329 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3944 11:43:39.723400 # ok 2217 Set Streaming SVE VL 656
3945 11:43:39.723476 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3946 11:43:39.723562 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3947 11:43:39.723844 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3948 11:43:39.723927 # ok 2221 Set Streaming SVE VL 672
3949 11:43:39.724020 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3950 11:43:39.724114 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3951 11:43:39.724210 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3952 11:43:39.724301 # ok 2225 Set Streaming SVE VL 688
3953 11:43:39.724590 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3954 11:43:39.724674 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3955 11:43:39.724757 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3956 11:43:39.724837 # ok 2229 Set Streaming SVE VL 704
3957 11:43:39.724923 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3958 11:43:39.725017 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3959 11:43:39.725285 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3960 11:43:39.725368 # ok 2233 Set Streaming SVE VL 720
3961 11:43:39.725459 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3962 11:43:39.725554 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3963 11:43:39.725665 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3964 11:43:39.725774 # ok 2237 Set Streaming SVE VL 736
3965 11:43:39.726034 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3966 11:43:39.726321 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3967 11:43:39.726406 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3968 11:43:39.726493 # ok 2241 Set Streaming SVE VL 752
3969 11:43:39.726581 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3970 11:43:39.726861 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3971 11:43:39.726966 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3972 11:43:39.727030 # ok 2245 Set Streaming SVE VL 768
3973 11:43:39.727099 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3974 11:43:39.727354 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3975 11:43:39.727444 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3976 11:43:39.727519 # ok 2249 Set Streaming SVE VL 784
3977 11:43:39.727772 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3978 11:43:39.727844 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3979 11:43:39.727933 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3980 11:43:39.728027 # ok 2253 Set Streaming SVE VL 800
3981 11:43:39.728302 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3982 11:43:39.728395 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3983 11:43:39.728673 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3984 11:43:39.728753 # ok 2257 Set Streaming SVE VL 816
3985 11:43:39.728845 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3986 11:43:39.728925 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3987 11:43:39.729018 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3988 11:43:39.729113 # ok 2261 Set Streaming SVE VL 832
3989 11:43:39.729398 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3990 11:43:39.729474 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3991 11:43:39.729567 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3992 11:43:39.729709 # ok 2265 Set Streaming SVE VL 848
3993 11:43:39.730037 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3994 11:43:39.730150 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3995 11:43:39.730454 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3996 11:43:39.730562 # ok 2269 Set Streaming SVE VL 864
3997 11:43:39.730675 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
3998 11:43:39.730787 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
3999 11:43:39.730899 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4000 11:43:39.731011 # ok 2273 Set Streaming SVE VL 880
4001 11:43:39.731122 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4002 11:43:39.731424 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4003 11:43:39.731528 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4004 11:43:39.731644 # ok 2277 Set Streaming SVE VL 896
4005 11:43:39.731756 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4006 11:43:39.734692 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4007 11:43:39.734834 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4008 11:43:39.734933 # ok 2281 Set Streaming SVE VL 912
4009 11:43:39.735024 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4010 11:43:39.735097 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4011 11:43:39.735187 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4012 11:43:39.735258 # ok 2285 Set Streaming SVE VL 928
4013 11:43:39.735348 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4014 11:43:39.735434 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4015 11:43:39.735716 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4016 11:43:39.735800 # ok 2289 Set Streaming SVE VL 944
4017 11:43:39.735918 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4018 11:43:39.736026 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4019 11:43:39.736122 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4020 11:43:39.736218 # ok 2293 Set Streaming SVE VL 960
4021 11:43:39.736315 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4022 11:43:39.736578 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4023 11:43:39.736655 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4024 11:43:39.736718 # ok 2297 Set Streaming SVE VL 976
4025 11:43:39.736788 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4026 11:43:39.737040 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4027 11:43:39.737105 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4028 11:43:39.737176 # ok 2301 Set Streaming SVE VL 992
4029 11:43:39.737262 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4030 11:43:39.737539 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4031 11:43:39.737612 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4032 11:43:39.737719 # ok 2305 Set Streaming SVE VL 1008
4033 11:43:39.737817 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4034 11:43:39.738094 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4035 11:43:39.738219 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4036 11:43:39.738328 # ok 2309 Set Streaming SVE VL 1024
4037 11:43:39.738627 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4038 11:43:39.738742 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4039 11:43:39.738844 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4040 11:43:39.738944 # ok 2313 Set Streaming SVE VL 1040
4041 11:43:39.739229 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4042 11:43:39.739319 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4043 11:43:39.739611 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4044 11:43:39.739704 # ok 2317 Set Streaming SVE VL 1056
4045 11:43:39.739785 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4046 11:43:39.739858 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4047 11:43:39.740107 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4048 11:43:39.740172 # ok 2321 Set Streaming SVE VL 1072
4049 11:43:39.740243 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4050 11:43:39.740315 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4051 11:43:39.740586 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4052 11:43:39.740684 # ok 2325 Set Streaming SVE VL 1088
4053 11:43:39.740781 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4054 11:43:39.740877 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4055 11:43:39.740956 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4056 11:43:39.741047 # ok 2329 Set Streaming SVE VL 1104
4057 11:43:39.741136 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4058 11:43:39.741408 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4059 11:43:39.741488 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4060 11:43:39.741586 # ok 2333 Set Streaming SVE VL 1120
4061 11:43:39.741674 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4062 11:43:39.741763 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4063 11:43:39.742026 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4064 11:43:39.742109 # ok 2337 Set Streaming SVE VL 1136
4065 11:43:39.742189 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4066 11:43:39.742277 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4067 11:43:39.742372 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4068 11:43:39.742459 # ok 2341 Set Streaming SVE VL 1152
4069 11:43:39.742555 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4070 11:43:39.742649 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4071 11:43:39.742956 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4072 11:43:39.743077 # ok 2345 Set Streaming SVE VL 1168
4073 11:43:39.743202 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4074 11:43:39.743342 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4075 11:43:39.743480 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4076 11:43:39.743595 # ok 2349 Set Streaming SVE VL 1184
4077 11:43:39.743691 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4078 11:43:39.743830 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4079 11:43:39.743938 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4080 11:43:39.744053 # ok 2353 Set Streaming SVE VL 1200
4081 11:43:39.744166 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4082 11:43:39.744261 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4083 11:43:39.744351 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4084 11:43:39.744456 # ok 2357 Set Streaming SVE VL 1216
4085 11:43:39.744568 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4086 11:43:39.744706 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4087 11:43:39.744818 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4088 11:43:39.744930 # ok 2361 Set Streaming SVE VL 1232
4089 11:43:39.745064 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4090 11:43:39.745173 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4091 11:43:39.745293 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4092 11:43:39.745411 # ok 2365 Set Streaming SVE VL 1248
4093 11:43:39.745520 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4094 11:43:39.745655 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4095 11:43:39.745840 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4096 11:43:39.745986 # ok 2369 Set Streaming SVE VL 1264
4097 11:43:39.746125 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4098 11:43:39.746287 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4099 11:43:39.746395 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4100 11:43:39.746503 # ok 2373 Set Streaming SVE VL 1280
4101 11:43:39.746599 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4102 11:43:39.746705 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4103 11:43:39.746774 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4104 11:43:39.746853 # ok 2377 Set Streaming SVE VL 1296
4105 11:43:39.746947 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4106 11:43:39.747028 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4107 11:43:39.747315 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4108 11:43:39.747403 # ok 2381 Set Streaming SVE VL 1312
4109 11:43:39.747489 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4110 11:43:39.747590 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4111 11:43:39.747666 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4112 11:43:39.747743 # ok 2385 Set Streaming SVE VL 1328
4113 11:43:39.747817 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4114 11:43:39.747914 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4115 11:43:39.748003 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4116 11:43:39.748111 # ok 2389 Set Streaming SVE VL 1344
4117 11:43:39.748404 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4118 11:43:39.748513 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4119 11:43:39.748621 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4120 11:43:39.748721 # ok 2393 Set Streaming SVE VL 1360
4121 11:43:39.749014 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4122 11:43:39.749115 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4123 11:43:39.749217 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4124 11:43:39.749352 # ok 2397 Set Streaming SVE VL 1376
4125 11:43:39.749664 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4126 11:43:39.749748 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4127 11:43:39.750049 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4128 11:43:39.750138 # ok 2401 Set Streaming SVE VL 1392
4129 11:43:39.750419 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4130 11:43:39.750522 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4131 11:43:39.750628 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4132 11:43:39.750702 # ok 2405 Set Streaming SVE VL 1408
4133 11:43:39.750821 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4134 11:43:39.750910 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4135 11:43:39.751043 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4136 11:43:39.751140 # ok 2409 Set Streaming SVE VL 1424
4137 11:43:39.751253 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4138 11:43:39.751343 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4139 11:43:39.751633 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4140 11:43:39.751736 # ok 2413 Set Streaming SVE VL 1440
4141 11:43:39.751836 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4142 11:43:39.751939 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4143 11:43:39.752061 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4144 11:43:39.752158 # ok 2417 Set Streaming SVE VL 1456
4145 11:43:39.752439 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4146 11:43:39.752534 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4147 11:43:39.752631 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4148 11:43:39.752707 # ok 2421 Set Streaming SVE VL 1472
4149 11:43:39.752802 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4150 11:43:39.753084 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4151 11:43:39.753177 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4152 11:43:39.753281 # ok 2425 Set Streaming SVE VL 1488
4153 11:43:39.753402 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4154 11:43:39.753530 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4155 11:43:39.753638 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4156 11:43:39.755559 # ok 2429 Set Streaming SVE VL 1504
4157 11:43:39.755711 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4158 11:43:39.755881 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4159 11:43:39.755992 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4160 11:43:39.756127 # ok 2433 Set Streaming SVE VL 1520
4161 11:43:39.756246 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4162 11:43:39.756359 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4163 11:43:39.756480 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4164 11:43:39.756618 # ok 2437 Set Streaming SVE VL 1536
4165 11:43:39.756724 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4166 11:43:39.756819 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4167 11:43:39.757101 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4168 11:43:39.757197 # ok 2441 Set Streaming SVE VL 1552
4169 11:43:39.757293 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4170 11:43:39.757389 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4171 11:43:39.757485 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4172 11:43:39.757587 # ok 2445 Set Streaming SVE VL 1568
4173 11:43:39.757859 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4174 11:43:39.758269 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4175 11:43:39.758563 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4176 11:43:39.758665 # ok 2449 Set Streaming SVE VL 1584
4177 11:43:39.758763 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4178 11:43:39.758838 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4179 11:43:39.758932 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4180 11:43:39.759023 # ok 2453 Set Streaming SVE VL 1600
4181 11:43:39.759110 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4182 11:43:39.759397 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4183 11:43:39.759495 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4184 11:43:39.759617 # ok 2457 Set Streaming SVE VL 1616
4185 11:43:39.759701 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4186 11:43:39.759792 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4187 11:43:39.759876 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4188 11:43:39.760141 # ok 2461 Set Streaming SVE VL 1632
4189 11:43:39.760212 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4190 11:43:39.760302 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4191 11:43:39.760386 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4192 11:43:39.760471 # ok 2465 Set Streaming SVE VL 1648
4193 11:43:39.760743 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4194 11:43:39.760837 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4195 11:43:39.760937 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4196 11:43:39.761023 # ok 2469 Set Streaming SVE VL 1664
4197 11:43:39.761308 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4198 11:43:39.761406 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4199 11:43:39.761495 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4200 11:43:39.761605 # ok 2473 Set Streaming SVE VL 1680
4201 11:43:39.761943 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4202 11:43:39.762052 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4203 11:43:39.762168 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4204 11:43:39.762261 # ok 2477 Set Streaming SVE VL 1696
4205 11:43:39.762613 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4206 11:43:39.762708 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4207 11:43:39.762797 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4208 11:43:39.762890 # ok 2481 Set Streaming SVE VL 1712
4209 11:43:39.763168 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4210 11:43:39.763250 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4211 11:43:39.763363 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4212 11:43:39.763485 # ok 2485 Set Streaming SVE VL 1728
4213 11:43:39.763596 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4214 11:43:39.763908 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4215 11:43:39.763998 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4216 11:43:39.764113 # ok 2489 Set Streaming SVE VL 1744
4217 11:43:39.764197 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4218 11:43:39.764275 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4219 11:43:39.764390 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4220 11:43:39.764506 # ok 2493 Set Streaming SVE VL 1760
4221 11:43:39.764631 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4222 11:43:39.764741 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4223 11:43:39.764978 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4224 11:43:39.765104 # ok 2497 Set Streaming SVE VL 1776
4225 11:43:39.765428 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4226 11:43:39.765544 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4227 11:43:39.765653 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4228 11:43:39.765736 # ok 2501 Set Streaming SVE VL 1792
4229 11:43:39.765832 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4230 11:43:39.766308 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4231 11:43:39.766586 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4232 11:43:39.766678 # ok 2505 Set Streaming SVE VL 1808
4233 11:43:39.766774 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4234 11:43:39.766863 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4235 11:43:39.767129 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4236 11:43:39.767223 # ok 2509 Set Streaming SVE VL 1824
4237 11:43:39.767347 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4238 11:43:39.767432 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4239 11:43:39.767530 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4240 11:43:39.767721 # ok 2513 Set Streaming SVE VL 1840
4241 11:43:39.767839 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4242 11:43:39.767934 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4243 11:43:39.768220 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4244 11:43:39.768302 # ok 2517 Set Streaming SVE VL 1856
4245 11:43:39.768397 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4246 11:43:39.768477 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4247 11:43:39.768559 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4248 11:43:39.768647 # ok 2521 Set Streaming SVE VL 1872
4249 11:43:39.768739 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4250 11:43:39.769011 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4251 11:43:39.769108 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4252 11:43:39.769232 # ok 2525 Set Streaming SVE VL 1888
4253 11:43:39.769323 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4254 11:43:39.769434 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4255 11:43:39.769668 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4256 11:43:39.769781 # ok 2529 Set Streaming SVE VL 1904
4257 11:43:39.770069 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4258 11:43:39.770183 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4259 11:43:39.770281 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4260 11:43:39.770368 # ok 2533 Set Streaming SVE VL 1920
4261 11:43:39.770644 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4262 11:43:39.770735 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4263 11:43:39.771003 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4264 11:43:39.771075 # ok 2537 Set Streaming SVE VL 1936
4265 11:43:39.771166 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4266 11:43:39.771458 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4267 11:43:39.771554 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4268 11:43:39.771655 # ok 2541 Set Streaming SVE VL 1952
4269 11:43:39.771747 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4270 11:43:39.772043 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4271 11:43:39.772151 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4272 11:43:39.772229 # ok 2545 Set Streaming SVE VL 1968
4273 11:43:39.772319 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4274 11:43:39.772415 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4275 11:43:39.772511 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4276 11:43:39.772603 # ok 2549 Set Streaming SVE VL 1984
4277 11:43:39.772893 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4278 11:43:39.772989 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4279 11:43:39.773085 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4280 11:43:39.773169 # ok 2553 Set Streaming SVE VL 2000
4281 11:43:39.773259 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4282 11:43:39.773350 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4283 11:43:39.773643 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4284 11:43:39.773745 # ok 2557 Set Streaming SVE VL 2016
4285 11:43:39.773850 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4286 11:43:39.773952 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4287 11:43:39.774221 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4288 11:43:39.774298 # ok 2561 Set Streaming SVE VL 2032
4289 11:43:39.774388 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4290 11:43:39.774481 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4291 11:43:39.774567 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4292 11:43:39.774656 # ok 2565 Set Streaming SVE VL 2048
4293 11:43:39.774923 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4294 11:43:39.775014 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4295 11:43:39.775131 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4296 11:43:39.775248 # ok 2569 Set Streaming SVE VL 2064
4297 11:43:39.775351 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4298 11:43:39.775450 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4299 11:43:39.775731 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4300 11:43:39.775821 # ok 2573 Set Streaming SVE VL 2080
4301 11:43:39.775918 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4302 11:43:39.776002 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4303 11:43:39.776259 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4304 11:43:39.776346 # ok 2577 Set Streaming SVE VL 2096
4305 11:43:39.776430 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4306 11:43:39.778762 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4307 11:43:39.778873 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4308 11:43:39.778969 # ok 2581 Set Streaming SVE VL 2112
4309 11:43:39.779051 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4310 11:43:39.779144 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4311 11:43:39.779234 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4312 11:43:39.779504 # ok 2585 Set Streaming SVE VL 2128
4313 11:43:39.779582 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4314 11:43:39.779677 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4315 11:43:39.779765 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4316 11:43:39.779852 # ok 2589 Set Streaming SVE VL 2144
4317 11:43:39.779943 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4318 11:43:39.780042 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4319 11:43:39.780332 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4320 11:43:39.780420 # ok 2593 Set Streaming SVE VL 2160
4321 11:43:39.780513 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4322 11:43:39.780787 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4323 11:43:39.780887 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4324 11:43:39.780973 # ok 2597 Set Streaming SVE VL 2176
4325 11:43:39.781045 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4326 11:43:39.781316 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4327 11:43:39.781396 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4328 11:43:39.781487 # ok 2601 Set Streaming SVE VL 2192
4329 11:43:39.781570 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4330 11:43:39.781860 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4331 11:43:39.782213 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4332 11:43:39.782567 # ok 2605 Set Streaming SVE VL 2208
4333 11:43:39.782678 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4334 11:43:39.782780 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4335 11:43:39.782885 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4336 11:43:39.782987 # ok 2609 Set Streaming SVE VL 2224
4337 11:43:39.783086 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4338 11:43:39.783392 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4339 11:43:39.783507 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4340 11:43:39.783607 # ok 2613 Set Streaming SVE VL 2240
4341 11:43:39.783907 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4342 11:43:39.784010 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4343 11:43:39.784325 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4344 11:43:39.784428 # ok 2617 Set Streaming SVE VL 2256
4345 11:43:39.784528 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4346 11:43:39.784629 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4347 11:43:39.784923 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4348 11:43:39.785026 # ok 2621 Set Streaming SVE VL 2272
4349 11:43:39.785124 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4350 11:43:39.785223 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4351 11:43:39.785518 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4352 11:43:39.785619 # ok 2625 Set Streaming SVE VL 2288
4353 11:43:39.785724 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4354 11:43:39.786104 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4355 11:43:39.786219 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4356 11:43:39.786319 # ok 2629 Set Streaming SVE VL 2304
4357 11:43:39.786611 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4358 11:43:39.786717 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4359 11:43:39.786816 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4360 11:43:39.786916 # ok 2633 Set Streaming SVE VL 2320
4361 11:43:39.787212 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4362 11:43:39.787312 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4363 11:43:39.787414 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4364 11:43:39.787517 # ok 2637 Set Streaming SVE VL 2336
4365 11:43:39.787805 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4366 11:43:39.787895 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4367 11:43:39.787993 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4368 11:43:39.788092 # ok 2641 Set Streaming SVE VL 2352
4369 11:43:39.788372 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4370 11:43:39.788474 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4371 11:43:39.788573 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4372 11:43:39.788673 # ok 2645 Set Streaming SVE VL 2368
4373 11:43:39.788958 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4374 11:43:39.789046 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4375 11:43:39.789144 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4376 11:43:39.789244 # ok 2649 Set Streaming SVE VL 2384
4377 11:43:39.789539 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4378 11:43:39.789629 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4379 11:43:39.789929 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4380 11:43:39.790046 # ok 2653 Set Streaming SVE VL 2400
4381 11:43:39.790150 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4382 11:43:39.790444 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4383 11:43:39.790586 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4384 11:43:39.790707 # ok 2657 Set Streaming SVE VL 2416
4385 11:43:39.790809 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4386 11:43:39.790909 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4387 11:43:39.791193 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4388 11:43:39.791284 # ok 2661 Set Streaming SVE VL 2432
4389 11:43:39.791381 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4390 11:43:39.791480 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4391 11:43:39.791762 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4392 11:43:39.791852 # ok 2665 Set Streaming SVE VL 2448
4393 11:43:39.791950 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4394 11:43:39.792050 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4395 11:43:39.792332 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4396 11:43:39.792421 # ok 2669 Set Streaming SVE VL 2464
4397 11:43:39.792518 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4398 11:43:39.792811 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4399 11:43:39.792912 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4400 11:43:39.793010 # ok 2673 Set Streaming SVE VL 2480
4401 11:43:39.793111 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4402 11:43:39.793447 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4403 11:43:39.793559 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4404 11:43:39.793644 # ok 2677 Set Streaming SVE VL 2496
4405 11:43:39.793788 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4406 11:43:39.794075 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4407 11:43:39.794181 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4408 11:43:39.794278 # ok 2681 Set Streaming SVE VL 2512
4409 11:43:39.794565 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4410 11:43:39.794653 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4411 11:43:39.794765 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4412 11:43:39.794845 # ok 2685 Set Streaming SVE VL 2528
4413 11:43:39.794931 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4414 11:43:39.795040 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4415 11:43:39.795133 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4416 11:43:39.795220 # ok 2689 Set Streaming SVE VL 2544
4417 11:43:39.795436 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4418 11:43:39.795546 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4419 11:43:39.795828 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4420 11:43:39.795920 # ok 2693 Set Streaming SVE VL 2560
4421 11:43:39.796022 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4422 11:43:39.796120 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4423 11:43:39.796421 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4424 11:43:39.796518 # ok 2697 Set Streaming SVE VL 2576
4425 11:43:39.796631 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4426 11:43:39.796759 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4427 11:43:39.797047 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4428 11:43:39.797131 # ok 2701 Set Streaming SVE VL 2592
4429 11:43:39.797256 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4430 11:43:39.797363 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4431 11:43:39.797452 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4432 11:43:39.797539 # ok 2705 Set Streaming SVE VL 2608
4433 11:43:39.797858 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4434 11:43:39.799330 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4435 11:43:39.799620 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4436 11:43:39.799726 # ok 2709 Set Streaming SVE VL 2624
4437 11:43:39.799848 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4438 11:43:39.799921 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4439 11:43:39.800011 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4440 11:43:39.800108 # ok 2713 Set Streaming SVE VL 2640
4441 11:43:39.800277 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4442 11:43:39.800394 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4443 11:43:39.800718 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4444 11:43:39.800801 # ok 2717 Set Streaming SVE VL 2656
4445 11:43:39.800907 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4446 11:43:39.800979 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4447 11:43:39.801067 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4448 11:43:39.801152 # ok 2721 Set Streaming SVE VL 2672
4449 11:43:39.801417 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4450 11:43:39.801487 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4451 11:43:39.801576 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4452 11:43:39.801672 # ok 2725 Set Streaming SVE VL 2688
4453 11:43:39.802264 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4454 11:43:39.802528 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4455 11:43:39.804224 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4456 11:43:39.804319 # ok 2729 Set Streaming SVE VL 2704
4457 11:43:39.804407 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4458 11:43:39.804485 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4459 11:43:39.804579 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4460 11:43:39.804856 # ok 2733 Set Streaming SVE VL 2720
4461 11:43:39.804943 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4462 11:43:39.805024 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4463 11:43:39.805104 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4464 11:43:39.805197 # ok 2737 Set Streaming SVE VL 2736
4465 11:43:39.805472 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4466 11:43:39.805553 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4467 11:43:39.805627 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4468 11:43:39.805715 # ok 2741 Set Streaming SVE VL 2752
4469 11:43:39.806143 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4470 11:43:39.806408 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4471 11:43:39.806504 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4472 11:43:39.806600 # ok 2745 Set Streaming SVE VL 2768
4473 11:43:39.806686 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4474 11:43:39.806775 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4475 11:43:39.806912 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4476 11:43:39.807035 # ok 2749 Set Streaming SVE VL 2784
4477 11:43:39.807332 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4478 11:43:39.807449 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4479 11:43:39.807551 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4480 11:43:39.807650 # ok 2753 Set Streaming SVE VL 2800
4481 11:43:39.807949 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4482 11:43:39.808062 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4483 11:43:39.808164 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4484 11:43:39.808458 # ok 2757 Set Streaming SVE VL 2816
4485 11:43:39.808570 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4486 11:43:39.808692 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4487 11:43:39.808988 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4488 11:43:39.809103 # ok 2761 Set Streaming SVE VL 2832
4489 11:43:39.809189 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4490 11:43:39.809487 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4491 11:43:39.809587 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4492 11:43:39.809696 # ok 2765 Set Streaming SVE VL 2848
4493 11:43:39.810000 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4494 11:43:39.810114 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4495 11:43:39.810431 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4496 11:43:39.810532 # ok 2769 Set Streaming SVE VL 2864
4497 11:43:39.810628 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4498 11:43:39.810725 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4499 11:43:39.811031 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4500 11:43:39.811132 # ok 2773 Set Streaming SVE VL 2880
4501 11:43:39.811231 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4502 11:43:39.811515 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4503 11:43:39.811605 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4504 11:43:39.811708 # ok 2777 Set Streaming SVE VL 2896
4505 11:43:39.811808 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4506 11:43:39.811967 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4507 11:43:39.812294 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4508 11:43:39.812395 # ok 2781 Set Streaming SVE VL 2912
4509 11:43:39.812493 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4510 11:43:39.812785 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4511 11:43:39.812899 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4512 11:43:39.812987 # ok 2785 Set Streaming SVE VL 2928
4513 11:43:39.813083 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4514 11:43:39.813373 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4515 11:43:39.813488 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4516 11:43:39.813783 # ok 2789 Set Streaming SVE VL 2944
4517 11:43:39.813883 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4518 11:43:39.814177 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4519 11:43:39.814277 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4520 11:43:39.814380 # ok 2793 Set Streaming SVE VL 2960
4521 11:43:39.814491 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4522 11:43:39.814611 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4523 11:43:39.814919 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4524 11:43:39.815018 # ok 2797 Set Streaming SVE VL 2976
4525 11:43:39.815145 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4526 11:43:39.815237 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4527 11:43:39.815327 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4528 11:43:39.815424 # ok 2801 Set Streaming SVE VL 2992
4529 11:43:39.815699 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4530 11:43:39.815795 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4531 11:43:39.815894 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4532 11:43:39.815977 # ok 2805 Set Streaming SVE VL 3008
4533 11:43:39.816065 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4534 11:43:39.816333 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4535 11:43:39.816469 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4536 11:43:39.816576 # ok 2809 Set Streaming SVE VL 3024
4537 11:43:39.816667 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4538 11:43:39.816759 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4539 11:43:39.817043 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4540 11:43:39.817137 # ok 2813 Set Streaming SVE VL 3040
4541 11:43:39.817220 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4542 11:43:39.817499 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4543 11:43:39.817583 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4544 11:43:39.817678 # ok 2817 Set Streaming SVE VL 3056
4545 11:43:39.817778 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4546 11:43:39.817872 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4547 11:43:39.818178 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4548 11:43:39.818272 # ok 2821 Set Streaming SVE VL 3072
4549 11:43:39.818392 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4550 11:43:39.818504 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4551 11:43:39.818616 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4552 11:43:39.818721 # ok 2825 Set Streaming SVE VL 3088
4553 11:43:39.818830 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4554 11:43:39.818918 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4555 11:43:39.819214 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4556 11:43:39.819312 # ok 2829 Set Streaming SVE VL 3104
4557 11:43:39.819413 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4558 11:43:39.819515 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4559 11:43:39.819622 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4560 11:43:39.819715 # ok 2833 Set Streaming SVE VL 3120
4561 11:43:39.819803 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4562 11:43:39.820115 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4563 11:43:39.820225 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4564 11:43:39.820313 # ok 2837 Set Streaming SVE VL 3136
4565 11:43:39.820406 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4566 11:43:39.820495 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4567 11:43:39.820794 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4568 11:43:39.820895 # ok 2841 Set Streaming SVE VL 3152
4569 11:43:39.820992 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4570 11:43:39.821084 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4571 11:43:39.821173 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4572 11:43:39.821251 # ok 2845 Set Streaming SVE VL 3168
4573 11:43:39.821538 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4574 11:43:39.821626 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4575 11:43:39.821736 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4576 11:43:39.821817 # ok 2849 Set Streaming SVE VL 3184
4577 11:43:39.822083 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4578 11:43:39.822198 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4579 11:43:39.822304 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4580 11:43:39.822400 # ok 2853 Set Streaming SVE VL 3200
4581 11:43:39.822671 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4582 11:43:39.822761 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4583 11:43:39.822871 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4584 11:43:39.822971 # ok 2857 Set Streaming SVE VL 3216
4585 11:43:39.823253 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4586 11:43:39.823343 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4587 11:43:39.823442 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4588 11:43:39.823531 # ok 2861 Set Streaming SVE VL 3232
4589 11:43:39.823617 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4590 11:43:39.823910 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4591 11:43:39.824003 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4592 11:43:39.824079 # ok 2865 Set Streaming SVE VL 3248
4593 11:43:39.824171 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4594 11:43:39.824452 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4595 11:43:39.824559 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4596 11:43:39.824690 # ok 2869 Set Streaming SVE VL 3264
4597 11:43:39.824828 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4598 11:43:39.824941 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4599 11:43:39.825071 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4600 11:43:39.825430 # ok 2873 Set Streaming SVE VL 3280
4601 11:43:39.825526 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4602 11:43:39.825606 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4603 11:43:39.825690 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4604 11:43:39.825765 # ok 2877 Set Streaming SVE VL 3296
4605 11:43:39.845106 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4606 11:43:39.845612 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4607 11:43:39.845724 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4608 11:43:39.845811 # ok 2881 Set Streaming SVE VL 3312
4609 11:43:39.845916 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4610 11:43:39.846014 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4611 11:43:39.853940 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4612 11:43:39.855956 # ok 2885 Set Streaming SVE VL 3328
4613 11:43:39.856114 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4614 11:43:39.856232 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4615 11:43:39.856511 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4616 11:43:39.856615 # ok 2889 Set Streaming SVE VL 3344
4617 11:43:39.856693 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4618 11:43:39.856796 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4619 11:43:39.856887 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4620 11:43:39.856986 # ok 2893 Set Streaming SVE VL 3360
4621 11:43:39.857287 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4622 11:43:39.857392 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4623 11:43:39.857494 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4624 11:43:39.857594 # ok 2897 Set Streaming SVE VL 3376
4625 11:43:39.857895 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4626 11:43:39.863128 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4627 11:43:39.863569 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4628 11:43:39.863673 # ok 2901 Set Streaming SVE VL 3392
4629 11:43:39.863782 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4630 11:43:39.863885 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4631 11:43:39.864172 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4632 11:43:39.864264 # ok 2905 Set Streaming SVE VL 3408
4633 11:43:39.864358 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4634 11:43:39.864665 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4635 11:43:39.864772 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4636 11:43:39.864854 # ok 2909 Set Streaming SVE VL 3424
4637 11:43:39.864932 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4638 11:43:39.865216 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4639 11:43:39.865323 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4640 11:43:39.865413 # ok 2913 Set Streaming SVE VL 3440
4641 11:43:39.865499 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4642 11:43:39.865772 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4643 11:43:39.870849 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4644 11:43:39.871275 # ok 2917 Set Streaming SVE VL 3456
4645 11:43:39.871357 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4646 11:43:39.871621 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4647 11:43:39.871718 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4648 11:43:39.871797 # ok 2921 Set Streaming SVE VL 3472
4649 11:43:39.871891 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4650 11:43:39.871969 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4651 11:43:39.872054 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4652 11:43:39.872131 # ok 2925 Set Streaming SVE VL 3488
4653 11:43:39.872421 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4654 11:43:39.872529 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4655 11:43:39.872622 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4656 11:43:39.872709 # ok 2929 Set Streaming SVE VL 3504
4657 11:43:39.872794 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4658 11:43:39.873069 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4659 11:43:39.873149 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4660 11:43:39.873260 # ok 2933 Set Streaming SVE VL 3520
4661 11:43:39.873557 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4662 11:43:39.873643 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4663 11:43:39.873746 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4664 11:43:39.873845 # ok 2937 Set Streaming SVE VL 3536
4665 11:43:39.879371 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4666 11:43:39.879789 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4667 11:43:39.879900 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4668 11:43:39.879987 # ok 2941 Set Streaming SVE VL 3552
4669 11:43:39.880086 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4670 11:43:39.880171 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4671 11:43:39.880268 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4672 11:43:39.880367 # ok 2945 Set Streaming SVE VL 3568
4673 11:43:39.880664 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4674 11:43:39.880780 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4675 11:43:39.881087 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4676 11:43:39.881189 # ok 2949 Set Streaming SVE VL 3584
4677 11:43:39.881287 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4678 11:43:39.881386 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4679 11:43:39.881675 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4680 11:43:39.881766 # ok 2953 Set Streaming SVE VL 3600
4681 11:43:39.882408 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4682 11:43:39.882693 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4683 11:43:39.882781 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4684 11:43:39.882882 # ok 2957 Set Streaming SVE VL 3616
4685 11:43:39.882982 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4686 11:43:39.883275 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4687 11:43:39.883389 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4688 11:43:39.883488 # ok 2961 Set Streaming SVE VL 3632
4689 11:43:39.883781 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4690 11:43:39.883886 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4691 11:43:39.883985 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4692 11:43:39.884086 # ok 2965 Set Streaming SVE VL 3648
4693 11:43:39.884401 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4694 11:43:39.884495 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4695 11:43:39.884594 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4696 11:43:39.884693 # ok 2969 Set Streaming SVE VL 3664
4697 11:43:39.884987 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4698 11:43:39.885099 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4699 11:43:39.885200 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4700 11:43:39.885300 # ok 2973 Set Streaming SVE VL 3680
4701 11:43:39.885596 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4702 11:43:39.885728 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4703 11:43:39.891479 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4704 11:43:39.891855 # ok 2977 Set Streaming SVE VL 3696
4705 11:43:39.891945 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4706 11:43:39.892025 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4707 11:43:39.892141 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4708 11:43:39.892220 # ok 2981 Set Streaming SVE VL 3712
4709 11:43:39.892295 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4710 11:43:39.892362 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4711 11:43:39.892439 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4712 11:43:39.892515 # ok 2985 Set Streaming SVE VL 3728
4713 11:43:39.892607 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4714 11:43:39.892869 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4715 11:43:39.892954 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4716 11:43:39.893039 # ok 2989 Set Streaming SVE VL 3744
4717 11:43:39.893121 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4718 11:43:39.893205 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4719 11:43:39.893456 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4720 11:43:39.893529 # ok 2993 Set Streaming SVE VL 3760
4721 11:43:39.893600 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4722 11:43:39.893686 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4723 11:43:39.893953 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4724 11:43:39.897641 # ok 2997 Set Streaming SVE VL 3776
4725 11:43:39.897992 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4726 11:43:39.898886 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4727 11:43:39.899149 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4728 11:43:39.899217 # ok 3001 Set Streaming SVE VL 3792
4729 11:43:39.899278 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4730 11:43:39.899410 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4731 11:43:39.899480 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4732 11:43:39.899550 # ok 3005 Set Streaming SVE VL 3808
4733 11:43:39.899626 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4734 11:43:39.899698 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4735 11:43:39.899778 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4736 11:43:39.899855 # ok 3009 Set Streaming SVE VL 3824
4737 11:43:39.900115 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4738 11:43:39.900211 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4739 11:43:39.900302 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4740 11:43:39.900384 # ok 3013 Set Streaming SVE VL 3840
4741 11:43:39.900459 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4742 11:43:39.900540 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4743 11:43:39.900820 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4744 11:43:39.900922 # ok 3017 Set Streaming SVE VL 3856
4745 11:43:39.901014 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4746 11:43:39.901088 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4747 11:43:39.901174 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4748 11:43:39.901246 # ok 3021 Set Streaming SVE VL 3872
4749 11:43:39.901329 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4750 11:43:39.901604 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4751 11:43:39.901707 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4752 11:43:39.901798 # ok 3025 Set Streaming SVE VL 3888
4753 11:43:39.901885 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4754 11:43:39.907540 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4755 11:43:39.907949 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4756 11:43:39.908053 # ok 3029 Set Streaming SVE VL 3904
4757 11:43:39.908126 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4758 11:43:39.908213 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4759 11:43:39.908309 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4760 11:43:39.908383 # ok 3033 Set Streaming SVE VL 3920
4761 11:43:39.908481 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4762 11:43:39.908765 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4763 11:43:39.908854 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4764 11:43:39.908948 # ok 3037 Set Streaming SVE VL 3936
4765 11:43:39.909041 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4766 11:43:39.909144 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4767 11:43:39.909414 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4768 11:43:39.909520 # ok 3041 Set Streaming SVE VL 3952
4769 11:43:39.909633 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4770 11:43:39.909758 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4771 11:43:39.915035 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4772 11:43:39.915451 # ok 3045 Set Streaming SVE VL 3968
4773 11:43:39.915552 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4774 11:43:39.915638 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4775 11:43:39.915736 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4776 11:43:39.915820 # ok 3049 Set Streaming SVE VL 3984
4777 11:43:39.915921 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4778 11:43:39.916221 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4779 11:43:39.916305 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4780 11:43:39.916404 # ok 3053 Set Streaming SVE VL 4000
4781 11:43:39.916509 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4782 11:43:39.916577 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4783 11:43:39.916653 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4784 11:43:39.916733 # ok 3057 Set Streaming SVE VL 4016
4785 11:43:39.917014 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4786 11:43:39.917104 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4787 11:43:39.917224 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4788 11:43:39.917306 # ok 3061 Set Streaming SVE VL 4032
4789 11:43:39.917395 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4790 11:43:39.917479 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4791 11:43:39.917562 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4792 11:43:39.917843 # ok 3065 Set Streaming SVE VL 4048
4793 11:43:39.917943 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4794 11:43:39.923193 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4795 11:43:39.923584 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4796 11:43:39.923660 # ok 3069 Set Streaming SVE VL 4064
4797 11:43:39.923738 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4798 11:43:39.923845 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4799 11:43:39.923963 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4800 11:43:39.924049 # ok 3073 Set Streaming SVE VL 4080
4801 11:43:39.924116 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4802 11:43:39.924225 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4803 11:43:39.924303 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4804 11:43:39.924403 # ok 3077 Set Streaming SVE VL 4096
4805 11:43:39.924497 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4806 11:43:39.924815 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4807 11:43:39.925013 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4808 11:43:39.925210 # ok 3081 Set Streaming SVE VL 4112
4809 11:43:39.925377 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4810 11:43:39.925522 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4811 11:43:39.925682 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4812 11:43:39.925897 # ok 3085 Set Streaming SVE VL 4128
4813 11:43:39.926029 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4814 11:43:39.926147 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4815 11:43:39.926264 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4816 11:43:39.926378 # ok 3089 Set Streaming SVE VL 4144
4817 11:43:39.928820 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4818 11:43:39.929155 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4819 11:43:39.929266 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4820 11:43:39.929355 # ok 3093 Set Streaming SVE VL 4160
4821 11:43:39.929498 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4822 11:43:39.929615 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4823 11:43:39.929752 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4824 11:43:39.929879 # ok 3097 Set Streaming SVE VL 4176
4825 11:43:39.929997 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4826 11:43:39.933641 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4827 11:43:39.934007 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4828 11:43:39.934739 # ok 3101 Set Streaming SVE VL 4192
4829 11:43:39.935010 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4830 11:43:39.935107 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4831 11:43:39.935203 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4832 11:43:39.935486 # ok 3105 Set Streaming SVE VL 4208
4833 11:43:39.935585 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4834 11:43:39.935690 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4835 11:43:39.935966 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4836 11:43:39.936061 # ok 3109 Set Streaming SVE VL 4224
4837 11:43:39.936166 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4838 11:43:39.936252 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4839 11:43:39.936376 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4840 11:43:39.936458 # ok 3113 Set Streaming SVE VL 4240
4841 11:43:39.936548 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4842 11:43:39.936824 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4843 11:43:39.936917 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4844 11:43:39.937027 # ok 3117 Set Streaming SVE VL 4256
4845 11:43:39.937108 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4846 11:43:39.937181 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4847 11:43:39.937252 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4848 11:43:39.937349 # ok 3121 Set Streaming SVE VL 4272
4849 11:43:39.937447 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4850 11:43:39.937734 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4851 11:43:39.937918 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4852 11:43:39.938124 # ok 3125 Set Streaming SVE VL 4288
4853 11:43:39.942875 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4854 11:43:39.943266 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4855 11:43:39.943369 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4856 11:43:39.943456 # ok 3129 Set Streaming SVE VL 4304
4857 11:43:39.943538 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4858 11:43:39.943637 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4859 11:43:39.943721 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4860 11:43:39.943815 # ok 3133 Set Streaming SVE VL 4320
4861 11:43:39.944107 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4862 11:43:39.944207 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4863 11:43:39.944305 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4864 11:43:39.944405 # ok 3137 Set Streaming SVE VL 4336
4865 11:43:39.944688 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4866 11:43:39.944777 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4867 11:43:39.945059 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4868 11:43:39.945146 # ok 3141 Set Streaming SVE VL 4352
4869 11:43:39.945243 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4870 11:43:39.945341 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4871 11:43:39.945630 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4872 11:43:39.945723 # ok 3145 Set Streaming SVE VL 4368
4873 11:43:39.945890 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4874 11:43:39.958564 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4875 11:43:39.959018 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4876 11:43:39.959174 # ok 3149 Set Streaming SVE VL 4384
4877 11:43:39.959319 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4878 11:43:39.959461 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4879 11:43:39.959601 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4880 11:43:39.959776 # ok 3153 Set Streaming SVE VL 4400
4881 11:43:39.959910 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4882 11:43:39.960054 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4883 11:43:39.960195 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4884 11:43:39.960335 # ok 3157 Set Streaming SVE VL 4416
4885 11:43:39.960475 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4886 11:43:39.960701 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4887 11:43:39.960863 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4888 11:43:39.961005 # ok 3161 Set Streaming SVE VL 4432
4889 11:43:39.961168 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4890 11:43:39.961303 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4891 11:43:39.961480 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4892 11:43:39.961658 # ok 3165 Set Streaming SVE VL 4448
4893 11:43:39.961795 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4894 11:43:39.961918 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4895 11:43:39.962063 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4896 11:43:39.962182 # ok 3169 Set Streaming SVE VL 4464
4897 11:43:39.962296 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4898 11:43:39.962408 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4899 11:43:39.962521 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4900 11:43:39.962632 # ok 3173 Set Streaming SVE VL 4480
4901 11:43:39.962743 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4902 11:43:39.962853 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4903 11:43:39.970947 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4904 11:43:39.971619 # ok 3177 Set Streaming SVE VL 4496
4905 11:43:39.972062 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4906 11:43:39.972255 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4907 11:43:39.972407 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4908 11:43:39.972554 # ok 3181 Set Streaming SVE VL 4512
4909 11:43:39.972751 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4910 11:43:39.972899 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4911 11:43:39.973087 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4912 11:43:39.973261 # ok 3185 Set Streaming SVE VL 4528
4913 11:43:39.973422 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4914 11:43:39.973621 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4915 11:43:39.973802 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4916 11:43:39.973947 # ok 3189 Set Streaming SVE VL 4544
4917 11:43:39.974061 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4918 11:43:39.974169 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4919 11:43:39.974278 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4920 11:43:39.974388 # ok 3193 Set Streaming SVE VL 4560
4921 11:43:39.974523 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4922 11:43:39.974639 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4923 11:43:39.985037 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4924 11:43:39.985353 # ok 3197 Set Streaming SVE VL 4576
4925 11:43:39.985747 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4926 11:43:39.985922 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4927 11:43:39.986045 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4928 11:43:39.986159 # ok 3201 Set Streaming SVE VL 4592
4929 11:43:39.986275 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4930 11:43:39.986411 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4931 11:43:39.998798 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4932 11:43:39.999225 # ok 3205 Set Streaming SVE VL 4608
4933 11:43:39.999324 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4934 11:43:39.999411 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4935 11:43:39.999495 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4936 11:43:39.999595 # ok 3209 Set Streaming SVE VL 4624
4937 11:43:39.999680 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4938 11:43:39.999779 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4939 11:43:39.999879 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4940 11:43:39.999978 # ok 3213 Set Streaming SVE VL 4640
4941 11:43:40.000305 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4942 11:43:40.000502 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4943 11:43:40.000646 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4944 11:43:40.000821 # ok 3217 Set Streaming SVE VL 4656
4945 11:43:40.000983 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4946 11:43:40.001138 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4947 11:43:40.001327 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4948 11:43:40.001499 # ok 3221 Set Streaming SVE VL 4672
4949 11:43:40.001671 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4950 11:43:40.001840 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4951 11:43:40.002008 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4952 11:43:40.002130 # ok 3225 Set Streaming SVE VL 4688
4953 11:43:40.002245 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4954 11:43:40.002358 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4955 11:43:40.017185 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4956 11:43:40.017746 # ok 3229 Set Streaming SVE VL 4704
4957 11:43:40.017941 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4958 11:43:40.018071 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4959 11:43:40.018187 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4960 11:43:40.018300 # ok 3233 Set Streaming SVE VL 4720
4961 11:43:40.018411 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4962 11:43:40.018548 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4963 11:43:40.019957 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4964 11:43:40.020368 # ok 3237 Set Streaming SVE VL 4736
4965 11:43:40.020551 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4966 11:43:40.020711 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4967 11:43:40.020897 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4968 11:43:40.021042 # ok 3241 Set Streaming SVE VL 4752
4969 11:43:40.021187 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4970 11:43:40.021371 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4971 11:43:40.021526 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4972 11:43:40.021682 # ok 3245 Set Streaming SVE VL 4768
4973 11:43:40.021832 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4974 11:43:40.021992 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4975 11:43:40.022113 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4976 11:43:40.022224 # ok 3249 Set Streaming SVE VL 4784
4977 11:43:40.022334 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4978 11:43:40.027092 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4979 11:43:40.027621 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4980 11:43:40.027810 # ok 3253 Set Streaming SVE VL 4800
4981 11:43:40.027962 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4982 11:43:40.028116 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4983 11:43:40.028297 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4984 11:43:40.028441 # ok 3257 Set Streaming SVE VL 4816
4985 11:43:40.028590 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4986 11:43:40.028714 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4987 11:43:40.028877 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4988 11:43:40.029057 # ok 3261 Set Streaming SVE VL 4832
4989 11:43:40.029209 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4990 11:43:40.029377 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4991 11:43:40.029533 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4992 11:43:40.029705 # ok 3265 Set Streaming SVE VL 4848
4993 11:43:40.029934 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4994 11:43:40.030069 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4995 11:43:40.030208 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4996 11:43:40.030347 # ok 3269 Set Streaming SVE VL 4864
4997 11:43:40.035151 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
4998 11:43:40.035423 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
4999 11:43:40.035624 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5000 11:43:40.035790 # ok 3273 Set Streaming SVE VL 4880
5001 11:43:40.035949 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5002 11:43:40.036110 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5003 11:43:40.036265 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5004 11:43:40.036417 # ok 3277 Set Streaming SVE VL 4896
5005 11:43:40.036568 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5006 11:43:40.036724 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5007 11:43:40.036880 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5008 11:43:40.037074 # ok 3281 Set Streaming SVE VL 4912
5009 11:43:40.037236 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5010 11:43:40.037393 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5011 11:43:40.037549 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5012 11:43:40.037721 # ok 3285 Set Streaming SVE VL 4928
5013 11:43:40.037881 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5014 11:43:40.038030 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5015 11:43:40.038177 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5016 11:43:40.038296 # ok 3289 Set Streaming SVE VL 4944
5017 11:43:40.038410 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5018 11:43:40.038521 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5019 11:43:40.038630 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5020 11:43:40.038740 # ok 3293 Set Streaming SVE VL 4960
5021 11:43:40.043191 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5022 11:43:40.043618 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5023 11:43:40.043808 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5024 11:43:40.043967 # ok 3297 Set Streaming SVE VL 4976
5025 11:43:40.044149 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5026 11:43:40.044305 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5027 11:43:40.044445 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5028 11:43:40.044593 # ok 3301 Set Streaming SVE VL 4992
5029 11:43:40.044742 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5030 11:43:40.044921 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5031 11:43:40.045076 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5032 11:43:40.045223 # ok 3305 Set Streaming SVE VL 5008
5033 11:43:40.045361 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5034 11:43:40.045511 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5035 11:43:40.045675 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5036 11:43:40.045891 # ok 3309 Set Streaming SVE VL 5024
5037 11:43:40.046076 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5038 11:43:40.046310 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5039 11:43:40.046464 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5040 11:43:40.046605 # ok 3313 Set Streaming SVE VL 5040
5041 11:43:40.046744 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5042 11:43:40.046882 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5043 11:43:40.047020 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5044 11:43:40.047160 # ok 3317 Set Streaming SVE VL 5056
5045 11:43:40.047297 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5046 11:43:40.050684 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5047 11:43:40.051156 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5048 11:43:40.051333 # ok 3321 Set Streaming SVE VL 5072
5049 11:43:40.051477 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5050 11:43:40.051593 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5051 11:43:40.051728 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5052 11:43:40.051846 # ok 3325 Set Streaming SVE VL 5088
5053 11:43:40.051958 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5054 11:43:40.052292 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5055 11:43:40.052486 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5056 11:43:40.052650 # ok 3329 Set Streaming SVE VL 5104
5057 11:43:40.052839 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5058 11:43:40.053002 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5059 11:43:40.053159 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5060 11:43:40.053348 # ok 3333 Set Streaming SVE VL 5120
5061 11:43:40.053511 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5062 11:43:40.053676 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5063 11:43:40.053836 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5064 11:43:40.053969 # ok 3337 Set Streaming SVE VL 5136
5065 11:43:40.054109 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5066 11:43:40.054227 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5067 11:43:40.054339 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5068 11:43:40.054452 # ok 3341 Set Streaming SVE VL 5152
5069 11:43:40.054562 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5070 11:43:40.055189 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5071 11:43:40.055571 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5072 11:43:40.055735 # ok 3345 Set Streaming SVE VL 5168
5073 11:43:40.055888 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5074 11:43:40.056069 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5075 11:43:40.056205 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5076 11:43:40.056348 # ok 3349 Set Streaming SVE VL 5184
5077 11:43:40.056475 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5078 11:43:40.056624 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5079 11:43:40.056793 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5080 11:43:40.056940 # ok 3353 Set Streaming SVE VL 5200
5081 11:43:40.057088 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5082 11:43:40.057226 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5083 11:43:40.057375 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5084 11:43:40.057523 # ok 3357 Set Streaming SVE VL 5216
5085 11:43:40.057724 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5086 11:43:40.057887 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5087 11:43:40.058023 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5088 11:43:40.058143 # ok 3361 Set Streaming SVE VL 5232
5089 11:43:40.058254 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5090 11:43:40.058366 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5091 11:43:40.058478 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5092 11:43:40.058589 # ok 3365 Set Streaming SVE VL 5248
5093 11:43:40.058723 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5094 11:43:40.061894 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5095 11:43:40.063184 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5096 11:43:40.063475 # ok 3369 Set Streaming SVE VL 5264
5097 11:43:40.063767 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5098 11:43:40.064053 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5099 11:43:40.064146 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5100 11:43:40.064440 # ok 3373 Set Streaming SVE VL 5280
5101 11:43:40.064709 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5102 11:43:40.064989 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5103 11:43:40.065259 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5104 11:43:40.065329 # ok 3377 Set Streaming SVE VL 5296
5105 11:43:40.065704 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5106 11:43:40.065911 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5107 11:43:40.070861 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5108 11:43:40.071323 # ok 3381 Set Streaming SVE VL 5312
5109 11:43:40.071494 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5110 11:43:40.071646 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5111 11:43:40.071797 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5112 11:43:40.072020 # ok 3385 Set Streaming SVE VL 5328
5113 11:43:40.072238 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5114 11:43:40.072457 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5115 11:43:40.072668 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5116 11:43:40.072848 # ok 3389 Set Streaming SVE VL 5344
5117 11:43:40.073062 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5118 11:43:40.073234 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5119 11:43:40.073402 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5120 11:43:40.073548 # ok 3393 Set Streaming SVE VL 5360
5121 11:43:40.073722 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5122 11:43:40.073898 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5123 11:43:40.074027 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5124 11:43:40.074157 # ok 3397 Set Streaming SVE VL 5376
5125 11:43:40.074301 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5126 11:43:40.074420 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5127 11:43:40.074533 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5128 11:43:40.074645 # ok 3401 Set Streaming SVE VL 5392
5129 11:43:40.074755 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5130 11:43:40.074868 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5131 11:43:40.078646 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5132 11:43:40.079137 # ok 3405 Set Streaming SVE VL 5408
5133 11:43:40.079243 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5134 11:43:40.079330 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5135 11:43:40.079413 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5136 11:43:40.079497 # ok 3409 Set Streaming SVE VL 5424
5137 11:43:40.079594 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5138 11:43:40.079682 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5139 11:43:40.079782 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5140 11:43:40.079883 # ok 3413 Set Streaming SVE VL 5440
5141 11:43:40.079982 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5142 11:43:40.080286 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5143 11:43:40.080375 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5144 11:43:40.080472 # ok 3417 Set Streaming SVE VL 5456
5145 11:43:40.080569 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5146 11:43:40.080861 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5147 11:43:40.080976 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5148 11:43:40.081061 # ok 3421 Set Streaming SVE VL 5472
5149 11:43:40.081155 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5150 11:43:40.081438 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5151 11:43:40.081540 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5152 11:43:40.081625 # ok 3425 Set Streaming SVE VL 5488
5153 11:43:40.081732 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5154 11:43:40.082015 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5155 11:43:40.089382 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5156 11:43:40.089583 # ok 3429 Set Streaming SVE VL 5504
5157 11:43:40.089888 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5158 11:43:40.089993 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5159 11:43:40.090075 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5160 11:43:40.090154 # ok 3433 Set Streaming SVE VL 5520
5161 11:43:40.090597 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5162 11:43:40.091022 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5163 11:43:40.091204 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5164 11:43:40.091399 # ok 3437 Set Streaming SVE VL 5536
5165 11:43:40.091581 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5166 11:43:40.091812 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5167 11:43:40.091971 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5168 11:43:40.092117 # ok 3441 Set Streaming SVE VL 5552
5169 11:43:40.092262 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5170 11:43:40.092403 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5171 11:43:40.092579 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5172 11:43:40.092713 # ok 3445 Set Streaming SVE VL 5568
5173 11:43:40.092874 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5174 11:43:40.093058 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5175 11:43:40.093219 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5176 11:43:40.093383 # ok 3449 Set Streaming SVE VL 5584
5177 11:43:40.093541 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5178 11:43:40.093735 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5179 11:43:40.093886 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5180 11:43:40.094014 # ok 3453 Set Streaming SVE VL 5600
5181 11:43:40.094129 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5182 11:43:40.094244 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5183 11:43:40.094356 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5184 11:43:40.094468 # ok 3457 Set Streaming SVE VL 5616
5185 11:43:40.094579 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5186 11:43:40.094691 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5187 11:43:40.094803 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5188 11:43:40.094914 # ok 3461 Set Streaming SVE VL 5632
5189 11:43:40.095048 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5190 11:43:40.103147 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5191 11:43:40.103663 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5192 11:43:40.103835 # ok 3465 Set Streaming SVE VL 5648
5193 11:43:40.103998 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5194 11:43:40.104152 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5195 11:43:40.104316 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5196 11:43:40.104492 # ok 3469 Set Streaming SVE VL 5664
5197 11:43:40.104634 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5198 11:43:40.104751 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5199 11:43:40.104865 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5200 11:43:40.104978 # ok 3473 Set Streaming SVE VL 5680
5201 11:43:40.105090 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5202 11:43:40.105224 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5203 11:43:40.105404 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5204 11:43:40.105616 # ok 3477 Set Streaming SVE VL 5696
5205 11:43:40.105841 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5206 11:43:40.106005 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5207 11:43:40.106151 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5208 11:43:40.115025 # ok 3481 Set Streaming SVE VL 5712
5209 11:43:40.115591 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5210 11:43:40.115772 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5211 11:43:40.115977 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5212 11:43:40.116175 # ok 3485 Set Streaming SVE VL 5728
5213 11:43:40.116367 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5214 11:43:40.116604 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5215 11:43:40.116796 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5216 11:43:40.117000 # ok 3489 Set Streaming SVE VL 5744
5217 11:43:40.117179 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5218 11:43:40.117346 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5219 11:43:40.117504 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5220 11:43:40.117688 # ok 3493 Set Streaming SVE VL 5760
5221 11:43:40.117841 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5222 11:43:40.118002 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5223 11:43:40.118124 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5224 11:43:40.118236 # ok 3497 Set Streaming SVE VL 5776
5225 11:43:40.118350 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5226 11:43:40.118461 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5227 11:43:40.118571 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5228 11:43:40.118682 # ok 3501 Set Streaming SVE VL 5792
5229 11:43:40.118793 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5230 11:43:40.118904 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5231 11:43:40.119014 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5232 11:43:40.126487 # ok 3505 Set Streaming SVE VL 5808
5233 11:43:40.126906 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5234 11:43:40.127089 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5235 11:43:40.127233 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5236 11:43:40.127413 # ok 3509 Set Streaming SVE VL 5824
5237 11:43:40.127547 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5238 11:43:40.127688 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5239 11:43:40.127866 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5240 11:43:40.128093 # ok 3513 Set Streaming SVE VL 5840
5241 11:43:40.128253 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5242 11:43:40.128411 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5243 11:43:40.128611 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5244 11:43:40.128792 # ok 3517 Set Streaming SVE VL 5856
5245 11:43:40.128950 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5246 11:43:40.129109 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5247 11:43:40.129253 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5248 11:43:40.129375 # ok 3521 Set Streaming SVE VL 5872
5249 11:43:40.129490 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5250 11:43:40.129609 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5251 11:43:40.129754 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5252 11:43:40.129918 # ok 3525 Set Streaming SVE VL 5888
5253 11:43:40.130049 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5254 11:43:40.130194 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5255 11:43:40.130314 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5256 11:43:40.130427 # ok 3529 Set Streaming SVE VL 5904
5257 11:43:40.130540 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5258 11:43:40.130652 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5259 11:43:40.130764 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5260 11:43:40.130875 # ok 3533 Set Streaming SVE VL 5920
5261 11:43:40.136973 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5262 11:43:40.137341 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5263 11:43:40.137509 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5264 11:43:40.137638 # ok 3537 Set Streaming SVE VL 5936
5265 11:43:40.137798 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5266 11:43:40.137925 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5267 11:43:40.138047 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5268 11:43:40.138169 # ok 3541 Set Streaming SVE VL 5952
5269 11:43:40.146836 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5270 11:43:40.147265 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5271 11:43:40.147450 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5272 11:43:40.147592 # ok 3545 Set Streaming SVE VL 5968
5273 11:43:40.147714 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5274 11:43:40.147862 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5275 11:43:40.148021 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5276 11:43:40.148173 # ok 3549 Set Streaming SVE VL 5984
5277 11:43:40.148324 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5278 11:43:40.148503 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5279 11:43:40.148654 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5280 11:43:40.148784 # ok 3553 Set Streaming SVE VL 6000
5281 11:43:40.148922 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5282 11:43:40.149139 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5283 11:43:40.149322 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5284 11:43:40.149506 # ok 3557 Set Streaming SVE VL 6016
5285 11:43:40.149730 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5286 11:43:40.149911 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5287 11:43:40.150140 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5288 11:43:40.150293 # ok 3561 Set Streaming SVE VL 6032
5289 11:43:40.150434 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5290 11:43:40.150572 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5291 11:43:40.150710 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5292 11:43:40.150846 # ok 3565 Set Streaming SVE VL 6048
5293 11:43:40.150982 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5294 11:43:40.154722 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5295 11:43:40.155104 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5296 11:43:40.155292 # ok 3569 Set Streaming SVE VL 6064
5297 11:43:40.155513 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5298 11:43:40.155684 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5299 11:43:40.155839 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5300 11:43:40.155990 # ok 3573 Set Streaming SVE VL 6080
5301 11:43:40.156160 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5302 11:43:40.156329 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5303 11:43:40.156532 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5304 11:43:40.156696 # ok 3577 Set Streaming SVE VL 6096
5305 11:43:40.156867 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5306 11:43:40.157125 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5307 11:43:40.157308 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5308 11:43:40.157446 # ok 3581 Set Streaming SVE VL 6112
5309 11:43:40.157620 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5310 11:43:40.157819 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5311 11:43:40.158014 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5312 11:43:40.158145 # ok 3585 Set Streaming SVE VL 6128
5313 11:43:40.158261 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5314 11:43:40.158403 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5315 11:43:40.158524 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5316 11:43:40.158638 # ok 3589 Set Streaming SVE VL 6144
5317 11:43:40.158751 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5318 11:43:40.158863 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5319 11:43:40.158975 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5320 11:43:40.162869 # ok 3593 Set Streaming SVE VL 6160
5321 11:43:40.163300 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5322 11:43:40.163469 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5323 11:43:40.163634 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5324 11:43:40.163840 # ok 3597 Set Streaming SVE VL 6176
5325 11:43:40.164063 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5326 11:43:40.164236 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5327 11:43:40.164389 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5328 11:43:40.164548 # ok 3601 Set Streaming SVE VL 6192
5329 11:43:40.164713 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5330 11:43:40.164876 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5331 11:43:40.165076 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5332 11:43:40.165230 # ok 3605 Set Streaming SVE VL 6208
5333 11:43:40.165374 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5334 11:43:40.165519 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5335 11:43:40.165677 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5336 11:43:40.165806 # ok 3609 Set Streaming SVE VL 6224
5337 11:43:40.165955 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5338 11:43:40.166072 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5339 11:43:40.166210 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5340 11:43:40.166326 # ok 3613 Set Streaming SVE VL 6240
5341 11:43:40.166437 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5342 11:43:40.166547 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5343 11:43:40.166657 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5344 11:43:40.166767 # ok 3617 Set Streaming SVE VL 6256
5345 11:43:40.166876 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5346 11:43:40.176683 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5347 11:43:40.177534 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5348 11:43:40.177739 # ok 3621 Set Streaming SVE VL 6272
5349 11:43:40.177978 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5350 11:43:40.178133 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5351 11:43:40.178260 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5352 11:43:40.178686 # ok 3625 Set Streaming SVE VL 6288
5353 11:43:40.228971 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5354 11:43:40.229431 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5355 11:43:40.229624 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5356 11:43:40.229810 # ok 3629 Set Streaming SVE VL 6304
5357 11:43:40.230037 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5358 11:43:40.230191 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5359 11:43:40.230334 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5360 11:43:40.230474 # ok 3633 Set Streaming SVE VL 6320
5361 11:43:40.233604 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5362 11:43:40.234032 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5363 11:43:40.234184 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5364 11:43:40.234303 # ok 3637 Set Streaming SVE VL 6336
5365 11:43:40.234931 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5366 11:43:40.235351 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5367 11:43:40.235552 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5368 11:43:40.235719 # ok 3641 Set Streaming SVE VL 6352
5369 11:43:40.235866 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5370 11:43:40.236051 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5371 11:43:40.236197 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5372 11:43:40.236342 # ok 3645 Set Streaming SVE VL 6368
5373 11:43:40.236510 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5374 11:43:40.236659 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5375 11:43:40.236821 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5376 11:43:40.236980 # ok 3649 Set Streaming SVE VL 6384
5377 11:43:40.237115 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5378 11:43:40.237261 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5379 11:43:40.237411 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5380 11:43:40.237558 # ok 3653 Set Streaming SVE VL 6400
5381 11:43:40.237749 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5382 11:43:40.237946 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5383 11:43:40.238091 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5384 11:43:40.238207 # ok 3657 Set Streaming SVE VL 6416
5385 11:43:40.238318 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5386 11:43:40.238428 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5387 11:43:40.238536 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5388 11:43:40.238674 # ok 3661 Set Streaming SVE VL 6432
5389 11:43:40.238791 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5390 11:43:40.243902 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5391 11:43:40.244316 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5392 11:43:40.244498 # ok 3665 Set Streaming SVE VL 6448
5393 11:43:40.244648 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5394 11:43:40.244838 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5395 11:43:40.245004 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5396 11:43:40.245151 # ok 3669 Set Streaming SVE VL 6464
5397 11:43:40.245309 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5398 11:43:40.245467 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5399 11:43:40.245668 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5400 11:43:40.245830 # ok 3673 Set Streaming SVE VL 6480
5401 11:43:40.245983 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5402 11:43:40.246152 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5403 11:43:40.246293 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5404 11:43:40.246430 # ok 3677 Set Streaming SVE VL 6496
5405 11:43:40.246601 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5406 11:43:40.246734 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5407 11:43:40.246871 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5408 11:43:40.249616 # ok 3681 Set Streaming SVE VL 6512
5409 11:43:40.250024 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5410 11:43:40.250180 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5411 11:43:40.250328 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5412 11:43:40.250508 # ok 3685 Set Streaming SVE VL 6528
5413 11:43:40.250695 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5414 11:43:40.251093 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5415 11:43:40.251281 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5416 11:43:40.251440 # ok 3689 Set Streaming SVE VL 6544
5417 11:43:40.251628 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5418 11:43:40.251784 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5419 11:43:40.251943 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5420 11:43:40.252094 # ok 3693 Set Streaming SVE VL 6560
5421 11:43:40.252256 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5422 11:43:40.252461 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5423 11:43:40.252620 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5424 11:43:40.252765 # ok 3697 Set Streaming SVE VL 6576
5425 11:43:40.252910 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5426 11:43:40.253054 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5427 11:43:40.253194 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5428 11:43:40.253375 # ok 3701 Set Streaming SVE VL 6592
5429 11:43:40.253520 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5430 11:43:40.253675 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5431 11:43:40.253824 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5432 11:43:40.253961 # ok 3705 Set Streaming SVE VL 6608
5433 11:43:40.254090 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5434 11:43:40.254205 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5435 11:43:40.254344 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5436 11:43:40.254462 # ok 3709 Set Streaming SVE VL 6624
5437 11:43:40.254574 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5438 11:43:40.254687 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5439 11:43:40.254799 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5440 11:43:40.261294 # ok 3713 Set Streaming SVE VL 6640
5441 11:43:40.261688 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5442 11:43:40.261848 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5443 11:43:40.262019 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5444 11:43:40.262144 # ok 3717 Set Streaming SVE VL 6656
5445 11:43:40.262259 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5446 11:43:40.267821 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5447 11:43:40.268235 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5448 11:43:40.268428 # ok 3721 Set Streaming SVE VL 6672
5449 11:43:40.268627 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5450 11:43:40.268828 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5451 11:43:40.269011 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5452 11:43:40.269176 # ok 3725 Set Streaming SVE VL 6688
5453 11:43:40.269338 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5454 11:43:40.269516 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5455 11:43:40.269715 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5456 11:43:40.269895 # ok 3729 Set Streaming SVE VL 6704
5457 11:43:40.270045 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5458 11:43:40.270160 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5459 11:43:40.270273 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5460 11:43:40.270385 # ok 3733 Set Streaming SVE VL 6720
5461 11:43:40.270521 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5462 11:43:40.270639 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5463 11:43:40.270752 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5464 11:43:40.286825 # ok 3737 Set Streaming SVE VL 6736
5465 11:43:40.287006 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5466 11:43:40.287162 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5467 11:43:40.287294 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5468 11:43:40.287441 # ok 3741 Set Streaming SVE VL 6752
5469 11:43:40.287567 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5470 11:43:40.287714 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5471 11:43:40.287840 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5472 11:43:40.288008 # ok 3745 Set Streaming SVE VL 6768
5473 11:43:40.288147 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5474 11:43:40.288317 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5475 11:43:40.288479 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5476 11:43:40.288669 # ok 3749 Set Streaming SVE VL 6784
5477 11:43:40.288810 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5478 11:43:40.288945 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5479 11:43:40.289111 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5480 11:43:40.289264 # ok 3753 Set Streaming SVE VL 6800
5481 11:43:40.289425 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5482 11:43:40.289560 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5483 11:43:40.289766 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5484 11:43:40.289964 # ok 3757 Set Streaming SVE VL 6816
5485 11:43:40.290130 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5486 11:43:40.290269 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5487 11:43:40.290408 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5488 11:43:40.290576 # ok 3761 Set Streaming SVE VL 6832
5489 11:43:40.290709 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5490 11:43:40.294317 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5491 11:43:40.294717 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5492 11:43:40.294865 # ok 3765 Set Streaming SVE VL 6848
5493 11:43:40.295049 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5494 11:43:40.295220 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5495 11:43:40.295420 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5496 11:43:40.295570 # ok 3769 Set Streaming SVE VL 6864
5497 11:43:40.295707 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5498 11:43:40.295823 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5499 11:43:40.295962 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5500 11:43:40.296080 # ok 3773 Set Streaming SVE VL 6880
5501 11:43:40.296194 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5502 11:43:40.303170 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5503 11:43:40.303580 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5504 11:43:40.303777 # ok 3777 Set Streaming SVE VL 6896
5505 11:43:40.303950 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5506 11:43:40.304126 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5507 11:43:40.304284 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5508 11:43:40.304434 # ok 3781 Set Streaming SVE VL 6912
5509 11:43:40.304592 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5510 11:43:40.304769 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5511 11:43:40.304968 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5512 11:43:40.305159 # ok 3785 Set Streaming SVE VL 6928
5513 11:43:40.305352 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5514 11:43:40.305529 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5515 11:43:40.305738 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5516 11:43:40.305900 # ok 3789 Set Streaming SVE VL 6944
5517 11:43:40.306047 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5518 11:43:40.306216 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5519 11:43:40.306358 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5520 11:43:40.306497 # ok 3793 Set Streaming SVE VL 6960
5521 11:43:40.306635 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5522 11:43:40.306771 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5523 11:43:40.306943 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5524 11:43:40.307076 # ok 3797 Set Streaming SVE VL 6976
5525 11:43:40.307213 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5526 11:43:40.310154 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5527 11:43:40.310591 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5528 11:43:40.310782 # ok 3801 Set Streaming SVE VL 6992
5529 11:43:40.310945 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5530 11:43:40.311132 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5531 11:43:40.311281 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5532 11:43:40.311410 # ok 3805 Set Streaming SVE VL 7008
5533 11:43:40.311593 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5534 11:43:40.311829 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5535 11:43:40.312023 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5536 11:43:40.312217 # ok 3809 Set Streaming SVE VL 7024
5537 11:43:40.312380 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5538 11:43:40.312532 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5539 11:43:40.312741 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5540 11:43:40.312940 # ok 3813 Set Streaming SVE VL 7040
5541 11:43:40.313136 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5542 11:43:40.313290 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5543 11:43:40.313438 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5544 11:43:40.313577 # ok 3817 Set Streaming SVE VL 7056
5545 11:43:40.313792 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5546 11:43:40.314036 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5547 11:43:40.314189 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5548 11:43:40.314331 # ok 3821 Set Streaming SVE VL 7072
5549 11:43:40.314469 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5550 11:43:40.314606 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5551 11:43:40.314792 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5552 11:43:40.314929 # ok 3825 Set Streaming SVE VL 7088
5553 11:43:40.315044 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5554 11:43:40.315158 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5555 11:43:40.315269 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5556 11:43:40.318206 # ok 3829 Set Streaming SVE VL 7104
5557 11:43:40.318608 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5558 11:43:40.318794 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5559 11:43:40.318973 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5560 11:43:40.319156 # ok 3833 Set Streaming SVE VL 7120
5561 11:43:40.319319 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5562 11:43:40.319520 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5563 11:43:40.319681 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5564 11:43:40.319864 # ok 3837 Set Streaming SVE VL 7136
5565 11:43:40.320029 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5566 11:43:40.320169 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5567 11:43:40.320316 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5568 11:43:40.320487 # ok 3841 Set Streaming SVE VL 7152
5569 11:43:40.320654 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5570 11:43:40.320843 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5571 11:43:40.321001 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5572 11:43:40.321190 # ok 3845 Set Streaming SVE VL 7168
5573 11:43:40.321376 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5574 11:43:40.321561 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5575 11:43:40.322099 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5576 11:43:40.322231 # ok 3849 Set Streaming SVE VL 7184
5577 11:43:40.322346 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5578 11:43:40.322459 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5579 11:43:40.322573 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5580 11:43:40.322687 # ok 3853 Set Streaming SVE VL 7200
5581 11:43:40.322801 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5582 11:43:40.322945 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5583 11:43:40.323066 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5584 11:43:40.323181 # ok 3857 Set Streaming SVE VL 7216
5585 11:43:40.323292 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5586 11:43:40.323404 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5587 11:43:40.323515 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5588 11:43:40.326402 # ok 3861 Set Streaming SVE VL 7232
5589 11:43:40.326824 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5590 11:43:40.327017 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5591 11:43:40.327217 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5592 11:43:40.327448 # ok 3865 Set Streaming SVE VL 7248
5593 11:43:40.327655 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5594 11:43:40.327842 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5595 11:43:40.328013 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5596 11:43:40.328205 # ok 3869 Set Streaming SVE VL 7264
5597 11:43:40.328455 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5598 11:43:40.328637 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5599 11:43:40.328808 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5600 11:43:40.328951 # ok 3873 Set Streaming SVE VL 7280
5601 11:43:40.329099 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5602 11:43:40.329254 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5603 11:43:40.329392 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5604 11:43:40.329809 # ok 3877 Set Streaming SVE VL 7296
5605 11:43:40.330002 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5606 11:43:40.330163 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5607 11:43:40.330291 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5608 11:43:40.330403 # ok 3881 Set Streaming SVE VL 7312
5609 11:43:40.330512 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5610 11:43:40.330621 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5611 11:43:40.330729 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5612 11:43:40.330838 # ok 3885 Set Streaming SVE VL 7328
5613 11:43:40.330947 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5614 11:43:40.331057 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5615 11:43:40.331167 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5616 11:43:40.331275 # ok 3889 Set Streaming SVE VL 7344
5617 11:43:40.331411 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5618 11:43:40.334342 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5619 11:43:40.334791 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5620 11:43:40.334983 # ok 3893 Set Streaming SVE VL 7360
5621 11:43:40.335138 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5622 11:43:40.335531 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5623 11:43:40.335714 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5624 11:43:40.335859 # ok 3897 Set Streaming SVE VL 7376
5625 11:43:40.335997 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5626 11:43:40.336134 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5627 11:43:40.336271 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5628 11:43:40.336407 # ok 3901 Set Streaming SVE VL 7392
5629 11:43:40.336574 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5630 11:43:40.336716 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5631 11:43:40.336867 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5632 11:43:40.337034 # ok 3905 Set Streaming SVE VL 7408
5633 11:43:40.337201 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5634 11:43:40.337339 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5635 11:43:40.337467 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5636 11:43:40.337608 # ok 3909 Set Streaming SVE VL 7424
5637 11:43:40.337787 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5638 11:43:40.338000 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5639 11:43:40.338173 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5640 11:43:40.338344 # ok 3913 Set Streaming SVE VL 7440
5641 11:43:40.338520 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5642 11:43:40.338693 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5643 11:43:40.338845 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5644 11:43:40.338959 # ok 3917 Set Streaming SVE VL 7456
5645 11:43:40.339069 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5646 11:43:40.339179 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5647 11:43:40.339289 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5648 11:43:40.339398 # ok 3921 Set Streaming SVE VL 7472
5649 11:43:40.339507 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5650 11:43:40.342984 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5651 11:43:40.343353 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5652 11:43:40.343731 # ok 3925 Set Streaming SVE VL 7488
5653 11:43:40.343965 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5654 11:43:40.344166 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5655 11:43:40.344370 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5656 11:43:40.344532 # ok 3929 Set Streaming SVE VL 7504
5657 11:43:40.344703 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5658 11:43:40.344913 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5659 11:43:40.345089 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5660 11:43:40.345230 # ok 3933 Set Streaming SVE VL 7520
5661 11:43:40.345376 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5662 11:43:40.345520 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5663 11:43:40.345760 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5664 11:43:40.345961 # ok 3937 Set Streaming SVE VL 7536
5665 11:43:40.346138 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5666 11:43:40.346277 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5667 11:43:40.346391 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5668 11:43:40.346502 # ok 3941 Set Streaming SVE VL 7552
5669 11:43:40.346636 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5670 11:43:40.346752 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5671 11:43:40.350587 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5672 11:43:40.350746 # ok 3945 Set Streaming SVE VL 7568
5673 11:43:40.351111 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5674 11:43:40.351303 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5675 11:43:40.351499 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5676 11:43:40.351682 # ok 3949 Set Streaming SVE VL 7584
5677 11:43:40.351871 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5678 11:43:40.352059 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5679 11:43:40.352297 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5680 11:43:40.352531 # ok 3953 Set Streaming SVE VL 7600
5681 11:43:40.352761 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5682 11:43:40.352951 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5683 11:43:40.353130 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5684 11:43:40.353337 # ok 3957 Set Streaming SVE VL 7616
5685 11:43:40.353518 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5686 11:43:40.353725 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5687 11:43:40.353919 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5688 11:43:40.354108 # ok 3961 Set Streaming SVE VL 7632
5689 11:43:40.354245 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5690 11:43:40.354373 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5691 11:43:40.354501 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5692 11:43:40.354627 # ok 3965 Set Streaming SVE VL 7648
5693 11:43:40.354747 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5694 11:43:40.354834 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5695 11:43:40.354920 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5696 11:43:40.355007 # ok 3969 Set Streaming SVE VL 7664
5697 11:43:40.355114 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5698 11:43:40.355204 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5699 11:43:40.358588 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5700 11:43:40.358895 # ok 3973 Set Streaming SVE VL 7680
5701 11:43:40.359105 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5702 11:43:40.359349 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5703 11:43:40.359530 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5704 11:43:40.359681 # ok 3977 Set Streaming SVE VL 7696
5705 11:43:40.359847 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5706 11:43:40.360012 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5707 11:43:40.360164 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5708 11:43:40.360359 # ok 3981 Set Streaming SVE VL 7712
5709 11:43:40.360512 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5710 11:43:40.360663 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5711 11:43:40.360801 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5712 11:43:40.360934 # ok 3985 Set Streaming SVE VL 7728
5713 11:43:40.361110 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5714 11:43:40.361276 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5715 11:43:40.361415 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5716 11:43:40.361547 # ok 3989 Set Streaming SVE VL 7744
5717 11:43:40.361688 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5718 11:43:40.361844 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5719 11:43:40.361976 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5720 11:43:40.362101 # ok 3993 Set Streaming SVE VL 7760
5721 11:43:40.362230 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5722 11:43:40.362353 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5723 11:43:40.362504 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5724 11:43:40.362630 # ok 3997 Set Streaming SVE VL 7776
5725 11:43:40.362729 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5726 11:43:40.362821 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5727 11:43:40.362932 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5728 11:43:40.363027 # ok 4001 Set Streaming SVE VL 7792
5729 11:43:40.363136 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5730 11:43:40.363231 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5731 11:43:40.363323 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5732 11:43:40.363431 # ok 4005 Set Streaming SVE VL 7808
5733 11:43:40.363526 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5734 11:43:40.363671 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5735 11:43:40.363997 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5736 11:43:40.364124 # ok 4009 Set Streaming SVE VL 7824
5737 11:43:40.364216 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5738 11:43:40.364329 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5739 11:43:40.364444 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5740 11:43:40.364569 # ok 4013 Set Streaming SVE VL 7840
5741 11:43:40.364701 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5742 11:43:40.364827 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5743 11:43:40.365107 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5744 11:43:40.365207 # ok 4017 Set Streaming SVE VL 7856
5745 11:43:40.365301 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5746 11:43:40.365590 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5747 11:43:40.365806 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5748 11:43:40.366004 # ok 4021 Set Streaming SVE VL 7872
5749 11:43:40.366203 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5750 11:43:40.366366 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5751 11:43:40.366545 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5752 11:43:40.366686 # ok 4025 Set Streaming SVE VL 7888
5753 11:43:40.366861 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5754 11:43:40.367013 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5755 11:43:40.367156 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5756 11:43:40.367290 # ok 4029 Set Streaming SVE VL 7904
5757 11:43:40.367445 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5758 11:43:40.367619 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5759 11:43:40.367763 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5760 11:43:40.367889 # ok 4033 Set Streaming SVE VL 7920
5761 11:43:40.368000 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5762 11:43:40.368111 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5763 11:43:40.368269 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5764 11:43:40.368402 # ok 4037 Set Streaming SVE VL 7936
5765 11:43:40.378790 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5766 11:43:40.379273 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5767 11:43:40.379420 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5768 11:43:40.379553 # ok 4041 Set Streaming SVE VL 7952
5769 11:43:40.379679 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5770 11:43:40.379808 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5771 11:43:40.379906 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5772 11:43:40.379998 # ok 4045 Set Streaming SVE VL 7968
5773 11:43:40.380090 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5774 11:43:40.380205 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5775 11:43:40.380302 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5776 11:43:40.380393 # ok 4049 Set Streaming SVE VL 7984
5777 11:43:40.380502 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5778 11:43:40.380616 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5779 11:43:40.380714 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5780 11:43:40.380878 # ok 4053 Set Streaming SVE VL 8000
5781 11:43:40.381192 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5782 11:43:40.381297 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5783 11:43:40.381410 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5784 11:43:40.381509 # ok 4057 Set Streaming SVE VL 8016
5785 11:43:40.381622 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5786 11:43:40.381753 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5787 11:43:40.381858 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5788 11:43:40.381934 # ok 4061 Set Streaming SVE VL 8032
5789 11:43:40.386740 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5790 11:43:40.387105 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5791 11:43:40.387241 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5792 11:43:40.387366 # ok 4065 Set Streaming SVE VL 8048
5793 11:43:40.387512 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5794 11:43:40.387660 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5795 11:43:40.387814 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5796 11:43:40.387903 # ok 4069 Set Streaming SVE VL 8064
5797 11:43:40.387983 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5798 11:43:40.388070 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5799 11:43:40.388136 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5800 11:43:40.388221 # ok 4073 Set Streaming SVE VL 8080
5801 11:43:40.388285 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5802 11:43:40.389084 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5803 11:43:40.389348 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5804 11:43:40.389414 # ok 4077 Set Streaming SVE VL 8096
5805 11:43:40.389485 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5806 11:43:40.389734 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5807 11:43:40.389800 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5808 11:43:40.389872 # ok 4081 Set Streaming SVE VL 8112
5809 11:43:40.390121 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5810 11:43:40.394079 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5811 11:43:40.396453 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5812 11:43:40.396735 # ok 4085 Set Streaming SVE VL 8128
5813 11:43:40.396845 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5814 11:43:40.396964 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5815 11:43:40.397053 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5816 11:43:40.397157 # ok 4089 Set Streaming SVE VL 8144
5817 11:43:40.397247 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5818 11:43:40.397338 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5819 11:43:40.397611 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5820 11:43:40.397706 # ok 4093 Set Streaming SVE VL 8160
5821 11:43:40.397789 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5822 11:43:40.397871 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5823 11:43:40.397964 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5824 11:43:40.401172 # ok 4097 Set Streaming SVE VL 8176
5825 11:43:40.401494 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5826 11:43:40.401610 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5827 11:43:40.401748 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5828 11:43:40.401831 # ok 4101 Set Streaming SVE VL 8192
5829 11:43:40.401910 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5830 11:43:40.401991 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5831 11:43:40.403031 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5832 11:43:40.403300 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5833 11:43:40.403379 ok 30 selftests: arm64: sve-ptrace
5834 11:43:40.403469 # selftests: arm64: sve-probe-vls
5835 11:43:40.403545 # TAP version 13
5836 11:43:40.403609 # 1..2
5837 11:43:40.403694 # ok 1 Enumerated 16 vector lengths
5838 11:43:40.403765 # ok 2 All vector lengths valid
5839 11:43:40.403849 # # 16
5840 11:43:40.403954 # # 32
5841 11:43:40.404040 # # 48
5842 11:43:40.404134 # # 64
5843 11:43:40.404204 # # 80
5844 11:43:40.404282 # # 96
5845 11:43:40.404358 # # 112
5846 11:43:40.404418 # # 128
5847 11:43:40.404475 # # 144
5848 11:43:40.404532 # # 160
5849 11:43:40.404589 # # 176
5850 11:43:40.404647 # # 192
5851 11:43:40.404704 # # 208
5852 11:43:40.404760 # # 224
5853 11:43:40.404818 # # 240
5854 11:43:40.404874 # # 256
5855 11:43:40.404944 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5856 11:43:40.405007 ok 31 selftests: arm64: sve-probe-vls
5857 11:43:40.468753 # selftests: arm64: vec-syscfg
5858 11:43:41.319462 # TAP version 13
5859 11:43:41.319733 # 1..20
5860 11:43:41.320130 # ok 1 SVE default vector length 64
5861 11:43:41.320375 # ok 2 SVE minimum vector length 16
5862 11:43:41.320596 # ok 3 SVE maximum vector length 256
5863 11:43:41.320738 # ok 4 SVE current VL is 64
5864 11:43:41.320864 # ok 5 SVE set VL 64 and have VL 64
5865 11:43:41.320987 # ok 6 SVE prctl() set min/max
5866 11:43:41.321111 # ok 7 SVE vector length used default
5867 11:43:41.321269 # ok 8 SVE vector length was inherited
5868 11:43:41.321400 # ok 9 SVE vector length set on exec
5869 11:43:41.321523 # ok 10 SVE prctl() set all VLs, 0 errors
5870 11:43:41.321640 # ok 11 SME default vector length 32
5871 11:43:41.321773 # ok 12 SME minimum vector length 16
5872 11:43:41.321887 # ok 13 SME maximum vector length 256
5873 11:43:41.322001 # ok 14 SME current VL is 32
5874 11:43:41.322115 # ok 15 SME set VL 32 and have VL 32
5875 11:43:41.322227 # ok 16 SME prctl() set min/max
5876 11:43:41.322338 # ok 17 SME vector length used default
5877 11:43:41.322451 # ok 18 SME vector length was inherited
5878 11:43:41.322589 # ok 19 SME vector length set on exec
5879 11:43:41.322707 # ok 20 SME prctl() set all VLs, 0 errors
5880 11:43:41.322821 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5881 11:43:41.358375 ok 32 selftests: arm64: vec-syscfg
5882 11:43:41.489490 # selftests: arm64: za-fork
5883 11:43:41.658366 # TAP version 13
5884 11:43:41.658605 # 1..1
5885 11:43:41.658986 # # PID: 1015
5886 11:43:41.659124 # ok 1 fork_test
5887 11:43:41.659532 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5888 11:43:41.673793 ok 33 selftests: arm64: za-fork
5889 11:43:41.754403 # selftests: arm64: za-ptrace
5890 11:43:41.845635 # TAP version 13
5891 11:43:41.845870 # 1..1536
5892 11:43:41.846323 # # Parent is 1033, child is 1034
5893 11:43:41.846512 # ok 1 Set VL 16
5894 11:43:41.846643 # ok 2 Disabled ZA for VL 16
5895 11:43:41.846760 # ok 3 Data match for VL 16
5896 11:43:41.846873 # ok 4 Set VL 32
5897 11:43:41.847013 # ok 5 Disabled ZA for VL 32
5898 11:43:41.847169 # ok 6 Data match for VL 32
5899 11:43:41.847355 # ok 7 Set VL 48
5900 11:43:41.847534 # ok 8 # SKIP Disabled ZA for VL 48
5901 11:43:41.847693 # ok 9 # SKIP Get and set data for VL 48
5902 11:43:41.847851 # ok 10 Set VL 64
5903 11:43:41.848041 # ok 11 Disabled ZA for VL 64
5904 11:43:41.848200 # ok 12 Data match for VL 64
5905 11:43:41.848356 # ok 13 Set VL 80
5906 11:43:41.848514 # ok 14 # SKIP Disabled ZA for VL 80
5907 11:43:41.848709 # ok 15 # SKIP Get and set data for VL 80
5908 11:43:41.848880 # ok 16 Set VL 96
5909 11:43:41.849035 # ok 17 # SKIP Disabled ZA for VL 96
5910 11:43:41.849217 # ok 18 # SKIP Get and set data for VL 96
5911 11:43:41.849415 # ok 19 Set VL 112
5912 11:43:41.849578 # ok 20 # SKIP Disabled ZA for VL 112
5913 11:43:41.849782 # ok 21 # SKIP Get and set data for VL 112
5914 11:43:41.849971 # ok 22 Set VL 128
5915 11:43:41.850148 # ok 23 Disabled ZA for VL 128
5916 11:43:41.850287 # ok 24 Data match for VL 128
5917 11:43:41.850449 # ok 25 Set VL 144
5918 11:43:41.850616 # ok 26 # SKIP Disabled ZA for VL 144
5919 11:43:41.850754 # ok 27 # SKIP Get and set data for VL 144
5920 11:43:41.850938 # ok 28 Set VL 160
5921 11:43:41.851069 # ok 29 # SKIP Disabled ZA for VL 160
5922 11:43:41.851206 # ok 30 # SKIP Get and set data for VL 160
5923 11:43:41.851343 # ok 31 Set VL 176
5924 11:43:41.851480 # ok 32 # SKIP Disabled ZA for VL 176
5925 11:43:41.851617 # ok 33 # SKIP Get and set data for VL 176
5926 11:43:41.851753 # ok 34 Set VL 192
5927 11:43:41.851889 # ok 35 # SKIP Disabled ZA for VL 192
5928 11:43:41.852024 # ok 36 # SKIP Get and set data for VL 192
5929 11:43:41.852160 # ok 37 Set VL 208
5930 11:43:41.852295 # ok 38 # SKIP Disabled ZA for VL 208
5931 11:43:41.852430 # ok 39 # SKIP Get and set data for VL 208
5932 11:43:41.852566 # ok 40 Set VL 224
5933 11:43:41.852701 # ok 41 # SKIP Disabled ZA for VL 224
5934 11:43:41.852837 # ok 42 # SKIP Get and set data for VL 224
5935 11:43:41.852972 # ok 43 Set VL 240
5936 11:43:41.853108 # ok 44 # SKIP Disabled ZA for VL 240
5937 11:43:41.853244 # ok 45 # SKIP Get and set data for VL 240
5938 11:43:41.853380 # ok 46 Set VL 256
5939 11:43:41.853516 # ok 47 Disabled ZA for VL 256
5940 11:43:41.853657 # ok 48 Data match for VL 256
5941 11:43:41.853798 # ok 49 Set VL 272
5942 11:43:41.853934 # ok 50 # SKIP Disabled ZA for VL 272
5943 11:43:41.854071 # ok 51 # SKIP Get and set data for VL 272
5944 11:43:41.854207 # ok 52 Set VL 288
5945 11:43:41.854343 # ok 53 # SKIP Disabled ZA for VL 288
5946 11:43:41.854529 # ok 54 # SKIP Get and set data for VL 288
5947 11:43:41.854694 # ok 55 Set VL 304
5948 11:43:41.854867 # ok 56 # SKIP Disabled ZA for VL 304
5949 11:43:41.855022 # ok 57 # SKIP Get and set data for VL 304
5950 11:43:41.855167 # ok 58 Set VL 320
5951 11:43:41.855338 # ok 59 # SKIP Disabled ZA for VL 320
5952 11:43:41.855479 # ok 60 # SKIP Get and set data for VL 320
5953 11:43:41.855863 # ok 61 Set VL 336
5954 11:43:41.856033 # ok 62 # SKIP Disabled ZA for VL 336
5955 11:43:41.856237 # ok 63 # SKIP Get and set data for VL 336
5956 11:43:41.856427 # ok 64 Set VL 352
5957 11:43:41.856610 # ok 65 # SKIP Disabled ZA for VL 352
5958 11:43:41.856768 # ok 66 # SKIP Get and set data for VL 352
5959 11:43:41.856911 # ok 67 Set VL 368
5960 11:43:41.857082 # ok 68 # SKIP Disabled ZA for VL 368
5961 11:43:41.857248 # ok 69 # SKIP Get and set data for VL 368
5962 11:43:41.857376 # ok 70 Set VL 384
5963 11:43:41.857524 # ok 71 # SKIP Disabled ZA for VL 384
5964 11:43:41.857694 # ok 72 # SKIP Get and set data for VL 384
5965 11:43:41.857844 # ok 73 Set VL 400
5966 11:43:41.857986 # ok 74 # SKIP Disabled ZA for VL 400
5967 11:43:41.858162 # ok 75 # SKIP Get and set data for VL 400
5968 11:43:41.858331 # ok 76 Set VL 416
5969 11:43:41.858491 # ok 77 # SKIP Disabled ZA for VL 416
5970 11:43:41.858621 # ok 78 # SKIP Get and set data for VL 416
5971 11:43:41.858734 # ok 79 Set VL 432
5972 11:43:41.858882 # ok 80 # SKIP Disabled ZA for VL 432
5973 11:43:41.859001 # ok 81 # SKIP Get and set data for VL 432
5974 11:43:41.859113 # ok 82 Set VL 448
5975 11:43:41.859223 # ok 83 # SKIP Disabled ZA for VL 448
5976 11:43:41.859334 # ok 84 # SKIP Get and set data for VL 448
5977 11:43:41.859445 # ok 85 Set VL 464
5978 11:43:41.859556 # ok 86 # SKIP Disabled ZA for VL 464
5979 11:43:41.859667 # ok 87 # SKIP Get and set data for VL 464
5980 11:43:41.859777 # ok 88 Set VL 480
5981 11:43:41.859887 # ok 89 # SKIP Disabled ZA for VL 480
5982 11:43:41.859997 # ok 90 # SKIP Get and set data for VL 480
5983 11:43:41.860107 # ok 91 Set VL 496
5984 11:43:41.860215 # ok 92 # SKIP Disabled ZA for VL 496
5985 11:43:41.860325 # ok 93 # SKIP Get and set data for VL 496
5986 11:43:41.860436 # ok 94 Set VL 512
5987 11:43:41.860544 # ok 95 # SKIP Disabled ZA for VL 512
5988 11:43:41.860653 # ok 96 # SKIP Get and set data for VL 512
5989 11:43:41.860764 # ok 97 Set VL 528
5990 11:43:41.860874 # ok 98 # SKIP Disabled ZA for VL 528
5991 11:43:41.860983 # ok 99 # SKIP Get and set data for VL 528
5992 11:43:41.861093 # ok 100 Set VL 544
5993 11:43:41.861204 # ok 101 # SKIP Disabled ZA for VL 544
5994 11:43:41.861314 # ok 102 # SKIP Get and set data for VL 544
5995 11:43:41.861423 # ok 103 Set VL 560
5996 11:43:41.861533 # ok 104 # SKIP Disabled ZA for VL 560
5997 11:43:41.861642 # ok 105 # SKIP Get and set data for VL 560
5998 11:43:41.861873 # ok 106 Set VL 576
5999 11:43:41.862055 # ok 107 # SKIP Disabled ZA for VL 576
6000 11:43:41.862232 # ok 108 # SKIP Get and set data for VL 576
6001 11:43:41.862407 # ok 109 Set VL 592
6002 11:43:41.862582 # ok 110 # SKIP Disabled ZA for VL 592
6003 11:43:41.862758 # ok 111 # SKIP Get and set data for VL 592
6004 11:43:41.862938 # ok 112 Set VL 608
6005 11:43:41.863085 # ok 113 # SKIP Disabled ZA for VL 608
6006 11:43:41.867354 # ok 114 # SKIP Get and set data for VL 608
6007 11:43:41.867671 # ok 115 Set VL 624
6008 11:43:41.868095 # ok 116 # SKIP Disabled ZA for VL 624
6009 11:43:41.868206 # ok 117 # SKIP Get and set data for VL 624
6010 11:43:41.868296 # ok 118 Set VL 640
6011 11:43:41.868377 # ok 119 # SKIP Disabled ZA for VL 640
6012 11:43:41.868464 # ok 120 # SKIP Get and set data for VL 640
6013 11:43:41.868552 # ok 121 Set VL 656
6014 11:43:41.868641 # ok 122 # SKIP Disabled ZA for VL 656
6015 11:43:41.868747 # ok 123 # SKIP Get and set data for VL 656
6016 11:43:41.868839 # ok 124 Set VL 672
6017 11:43:41.875951 # ok 125 # SKIP Disabled ZA for VL 672
6018 11:43:41.876086 # ok 126 # SKIP Get and set data for VL 672
6019 11:43:41.876368 # ok 127 Set VL 688
6020 11:43:41.876461 # ok 128 # SKIP Disabled ZA for VL 688
6021 11:43:41.876550 # ok 129 # SKIP Get and set data for VL 688
6022 11:43:41.876633 # ok 130 Set VL 704
6023 11:43:41.876734 # ok 131 # SKIP Disabled ZA for VL 704
6024 11:43:41.876821 # ok 132 # SKIP Get and set data for VL 704
6025 11:43:41.876907 # ok 133 Set VL 720
6026 11:43:41.876989 # ok 134 # SKIP Disabled ZA for VL 720
6027 11:43:41.877087 # ok 135 # SKIP Get and set data for VL 720
6028 11:43:41.877174 # ok 136 Set VL 736
6029 11:43:41.877258 # ok 137 # SKIP Disabled ZA for VL 736
6030 11:43:41.877357 # ok 138 # SKIP Get and set data for VL 736
6031 11:43:41.877444 # ok 139 Set VL 752
6032 11:43:41.877543 # ok 140 # SKIP Disabled ZA for VL 752
6033 11:43:41.877634 # ok 141 # SKIP Get and set data for VL 752
6034 11:43:41.877739 # ok 142 Set VL 768
6035 11:43:41.877823 # ok 143 # SKIP Disabled ZA for VL 768
6036 11:43:41.877922 # ok 144 # SKIP Get and set data for VL 768
6037 11:43:41.878021 # ok 145 Set VL 784
6038 11:43:41.878118 # ok 146 # SKIP Disabled ZA for VL 784
6039 11:43:41.878215 # ok 147 # SKIP Get and set data for VL 784
6040 11:43:41.878313 # ok 148 Set VL 800
6041 11:43:41.878410 # ok 149 # SKIP Disabled ZA for VL 800
6042 11:43:41.885109 # ok 150 # SKIP Get and set data for VL 800
6043 11:43:41.885347 # ok 151 Set VL 816
6044 11:43:41.885527 # ok 152 # SKIP Disabled ZA for VL 816
6045 11:43:41.885754 # ok 153 # SKIP Get and set data for VL 816
6046 11:43:41.885941 # ok 154 Set VL 832
6047 11:43:41.886322 # ok 155 # SKIP Disabled ZA for VL 832
6048 11:43:41.886524 # ok 156 # SKIP Get and set data for VL 832
6049 11:43:41.886724 # ok 157 Set VL 848
6050 11:43:41.886903 # ok 158 # SKIP Disabled ZA for VL 848
6051 11:43:41.887089 # ok 159 # SKIP Get and set data for VL 848
6052 11:43:41.887267 # ok 160 Set VL 864
6053 11:43:41.887408 # ok 161 # SKIP Disabled ZA for VL 864
6054 11:43:41.887526 # ok 162 # SKIP Get and set data for VL 864
6055 11:43:41.887649 # ok 163 Set VL 880
6056 11:43:41.887776 # ok 164 # SKIP Disabled ZA for VL 880
6057 11:43:41.887897 # ok 165 # SKIP Get and set data for VL 880
6058 11:43:41.888029 # ok 166 Set VL 896
6059 11:43:41.888158 # ok 167 # SKIP Disabled ZA for VL 896
6060 11:43:41.888323 # ok 168 # SKIP Get and set data for VL 896
6061 11:43:41.888461 # ok 169 Set VL 912
6062 11:43:41.888592 # ok 170 # SKIP Disabled ZA for VL 912
6063 11:43:41.888762 # ok 171 # SKIP Get and set data for VL 912
6064 11:43:41.888931 # ok 172 Set VL 928
6065 11:43:41.889082 # ok 173 # SKIP Disabled ZA for VL 928
6066 11:43:41.889207 # ok 174 # SKIP Get and set data for VL 928
6067 11:43:41.889329 # ok 175 Set VL 944
6068 11:43:41.889486 # ok 176 # SKIP Disabled ZA for VL 944
6069 11:43:41.889699 # ok 177 # SKIP Get and set data for VL 944
6070 11:43:41.889870 # ok 178 Set VL 960
6071 11:43:41.890013 # ok 179 # SKIP Disabled ZA for VL 960
6072 11:43:41.890155 # ok 180 # SKIP Get and set data for VL 960
6073 11:43:41.890295 # ok 181 Set VL 976
6074 11:43:41.890436 # ok 182 # SKIP Disabled ZA for VL 976
6075 11:43:41.890579 # ok 183 # SKIP Get and set data for VL 976
6076 11:43:41.890720 # ok 184 Set VL 992
6077 11:43:41.890860 # ok 185 # SKIP Disabled ZA for VL 992
6078 11:43:41.891000 # ok 186 # SKIP Get and set data for VL 992
6079 11:43:41.891140 # ok 187 Set VL 1008
6080 11:43:41.891281 # ok 188 # SKIP Disabled ZA for VL 1008
6081 11:43:41.891421 # ok 189 # SKIP Get and set data for VL 1008
6082 11:43:41.891563 # ok 190 Set VL 1024
6083 11:43:41.891704 # ok 191 # SKIP Disabled ZA for VL 1024
6084 11:43:41.891844 # ok 192 # SKIP Get and set data for VL 1024
6085 11:43:41.891984 # ok 193 Set VL 1040
6086 11:43:41.892166 # ok 194 # SKIP Disabled ZA for VL 1040
6087 11:43:41.892299 # ok 195 # SKIP Get and set data for VL 1040
6088 11:43:41.892440 # ok 196 Set VL 1056
6089 11:43:41.892584 # ok 197 # SKIP Disabled ZA for VL 1056
6090 11:43:41.892724 # ok 198 # SKIP Get and set data for VL 1056
6091 11:43:41.892864 # ok 199 Set VL 1072
6092 11:43:41.893003 # ok 200 # SKIP Disabled ZA for VL 1072
6093 11:43:41.893143 # ok 201 # SKIP Get and set data for VL 1072
6094 11:43:41.893283 # ok 202 Set VL 1088
6095 11:43:41.893422 # ok 203 # SKIP Disabled ZA for VL 1088
6096 11:43:41.893563 # ok 204 # SKIP Get and set data for VL 1088
6097 11:43:41.893771 # ok 205 Set VL 1104
6098 11:43:41.893940 # ok 206 # SKIP Disabled ZA for VL 1104
6099 11:43:41.894071 # ok 207 # SKIP Get and set data for VL 1104
6100 11:43:41.894231 # ok 208 Set VL 1120
6101 11:43:41.894599 # ok 209 # SKIP Disabled ZA for VL 1120
6102 11:43:41.894743 # ok 210 # SKIP Get and set data for VL 1120
6103 11:43:41.894864 # ok 211 Set VL 1136
6104 11:43:41.894981 # ok 212 # SKIP Disabled ZA for VL 1136
6105 11:43:41.895098 # ok 213 # SKIP Get and set data for VL 1136
6106 11:43:41.895215 # ok 214 Set VL 1152
6107 11:43:41.895332 # ok 215 # SKIP Disabled ZA for VL 1152
6108 11:43:41.895448 # ok 216 # SKIP Get and set data for VL 1152
6109 11:43:41.895562 # ok 217 Set VL 1168
6110 11:43:41.895681 # ok 218 # SKIP Disabled ZA for VL 1168
6111 11:43:41.895798 # ok 219 # SKIP Get and set data for VL 1168
6112 11:43:41.895912 # ok 220 Set VL 1184
6113 11:43:41.896027 # ok 221 # SKIP Disabled ZA for VL 1184
6114 11:43:41.896142 # ok 222 # SKIP Get and set data for VL 1184
6115 11:43:41.896258 # ok 223 Set VL 1200
6116 11:43:41.896373 # ok 224 # SKIP Disabled ZA for VL 1200
6117 11:43:41.896488 # ok 225 # SKIP Get and set data for VL 1200
6118 11:43:41.896603 # ok 226 Set VL 1216
6119 11:43:41.896721 # ok 227 # SKIP Disabled ZA for VL 1216
6120 11:43:41.896838 # ok 228 # SKIP Get and set data for VL 1216
6121 11:43:41.896952 # ok 229 Set VL 1232
6122 11:43:41.897068 # ok 230 # SKIP Disabled ZA for VL 1232
6123 11:43:41.897185 # ok 231 # SKIP Get and set data for VL 1232
6124 11:43:41.897301 # ok 232 Set VL 1248
6125 11:43:41.897418 # ok 233 # SKIP Disabled ZA for VL 1248
6126 11:43:41.897533 # ok 234 # SKIP Get and set data for VL 1248
6127 11:43:41.897663 # ok 235 Set VL 1264
6128 11:43:41.897785 # ok 236 # SKIP Disabled ZA for VL 1264
6129 11:43:41.897899 # ok 237 # SKIP Get and set data for VL 1264
6130 11:43:41.898016 # ok 238 Set VL 1280
6131 11:43:41.898131 # ok 239 # SKIP Disabled ZA for VL 1280
6132 11:43:41.898246 # ok 240 # SKIP Get and set data for VL 1280
6133 11:43:41.898361 # ok 241 Set VL 1296
6134 11:43:41.898486 # ok 242 # SKIP Disabled ZA for VL 1296
6135 11:43:41.898611 # ok 243 # SKIP Get and set data for VL 1296
6136 11:43:41.898741 # ok 244 Set VL 1312
6137 11:43:41.898858 # ok 245 # SKIP Disabled ZA for VL 1312
6138 11:43:41.898975 # ok 246 # SKIP Get and set data for VL 1312
6139 11:43:41.899092 # ok 247 Set VL 1328
6140 11:43:41.899208 # ok 248 # SKIP Disabled ZA for VL 1328
6141 11:43:41.899323 # ok 249 # SKIP Get and set data for VL 1328
6142 11:43:41.899440 # ok 250 Set VL 1344
6143 11:43:41.899555 # ok 251 # SKIP Disabled ZA for VL 1344
6144 11:43:41.899671 # ok 252 # SKIP Get and set data for VL 1344
6145 11:43:41.899785 # ok 253 Set VL 1360
6146 11:43:41.899900 # ok 254 # SKIP Disabled ZA for VL 1360
6147 11:43:41.900014 # ok 255 # SKIP Get and set data for VL 1360
6148 11:43:41.900130 # ok 256 Set VL 1376
6149 11:43:41.906567 # ok 257 # SKIP Disabled ZA for VL 1376
6150 11:43:41.906982 # ok 258 # SKIP Get and set data for VL 1376
6151 11:43:41.907162 # ok 259 Set VL 1392
6152 11:43:41.907329 # ok 260 # SKIP Disabled ZA for VL 1392
6153 11:43:41.907597 # ok 261 # SKIP Get and set data for VL 1392
6154 11:43:41.907837 # ok 262 Set VL 1408
6155 11:43:41.908045 # ok 263 # SKIP Disabled ZA for VL 1408
6156 11:43:41.908223 # ok 264 # SKIP Get and set data for VL 1408
6157 11:43:41.908388 # ok 265 Set VL 1424
6158 11:43:41.908552 # ok 266 # SKIP Disabled ZA for VL 1424
6159 11:43:41.908756 # ok 267 # SKIP Get and set data for VL 1424
6160 11:43:41.908925 # ok 268 Set VL 1440
6161 11:43:41.909083 # ok 269 # SKIP Disabled ZA for VL 1440
6162 11:43:41.909240 # ok 270 # SKIP Get and set data for VL 1440
6163 11:43:41.909417 # ok 271 Set VL 1456
6164 11:43:41.909627 # ok 272 # SKIP Disabled ZA for VL 1456
6165 11:43:41.909833 # ok 273 # SKIP Get and set data for VL 1456
6166 11:43:41.910006 # ok 274 Set VL 1472
6167 11:43:41.910161 # ok 275 # SKIP Disabled ZA for VL 1472
6168 11:43:41.910321 # ok 276 # SKIP Get and set data for VL 1472
6169 11:43:41.910488 # ok 277 Set VL 1488
6170 11:43:41.910635 # ok 278 # SKIP Disabled ZA for VL 1488
6171 11:43:41.910756 # ok 279 # SKIP Get and set data for VL 1488
6172 11:43:41.910901 # ok 280 Set VL 1504
6173 11:43:41.911019 # ok 281 # SKIP Disabled ZA for VL 1504
6174 11:43:41.911131 # ok 282 # SKIP Get and set data for VL 1504
6175 11:43:41.911244 # ok 283 Set VL 1520
6176 11:43:41.911355 # ok 284 # SKIP Disabled ZA for VL 1520
6177 11:43:41.911465 # ok 285 # SKIP Get and set data for VL 1520
6178 11:43:41.911579 # ok 286 Set VL 1536
6179 11:43:41.911692 # ok 287 # SKIP Disabled ZA for VL 1536
6180 11:43:41.911803 # ok 288 # SKIP Get and set data for VL 1536
6181 11:43:41.911916 # ok 289 Set VL 1552
6182 11:43:41.912026 # ok 290 # SKIP Disabled ZA for VL 1552
6183 11:43:41.912138 # ok 291 # SKIP Get and set data for VL 1552
6184 11:43:41.912249 # ok 292 Set VL 1568
6185 11:43:41.912360 # ok 293 # SKIP Disabled ZA for VL 1568
6186 11:43:41.912471 # ok 294 # SKIP Get and set data for VL 1568
6187 11:43:41.912581 # ok 295 Set VL 1584
6188 11:43:41.912693 # ok 296 # SKIP Disabled ZA for VL 1584
6189 11:43:41.912804 # ok 297 # SKIP Get and set data for VL 1584
6190 11:43:41.912915 # ok 298 Set VL 1600
6191 11:43:41.913026 # ok 299 # SKIP Disabled ZA for VL 1600
6192 11:43:41.916547 # ok 300 # SKIP Get and set data for VL 1600
6193 11:43:41.917009 # ok 301 Set VL 1616
6194 11:43:41.917178 # ok 302 # SKIP Disabled ZA for VL 1616
6195 11:43:41.917369 # ok 303 # SKIP Get and set data for VL 1616
6196 11:43:41.917557 # ok 304 Set VL 1632
6197 11:43:41.917733 # ok 305 # SKIP Disabled ZA for VL 1632
6198 11:43:41.917916 # ok 306 # SKIP Get and set data for VL 1632
6199 11:43:41.918081 # ok 307 Set VL 1648
6200 11:43:41.918244 # ok 308 # SKIP Disabled ZA for VL 1648
6201 11:43:41.918411 # ok 309 # SKIP Get and set data for VL 1648
6202 11:43:41.918804 # ok 310 Set VL 1664
6203 11:43:41.918934 # ok 311 # SKIP Disabled ZA for VL 1664
6204 11:43:41.919051 # ok 312 # SKIP Get and set data for VL 1664
6205 11:43:41.919167 # ok 313 Set VL 1680
6206 11:43:41.919282 # ok 314 # SKIP Disabled ZA for VL 1680
6207 11:43:41.919398 # ok 315 # SKIP Get and set data for VL 1680
6208 11:43:41.919512 # ok 316 Set VL 1696
6209 11:43:41.919656 # ok 317 # SKIP Disabled ZA for VL 1696
6210 11:43:41.919786 # ok 318 # SKIP Get and set data for VL 1696
6211 11:43:41.919904 # ok 319 Set VL 1712
6212 11:43:41.920020 # ok 320 # SKIP Disabled ZA for VL 1712
6213 11:43:41.920136 # ok 321 # SKIP Get and set data for VL 1712
6214 11:43:41.920252 # ok 322 Set VL 1728
6215 11:43:41.920366 # ok 323 # SKIP Disabled ZA for VL 1728
6216 11:43:41.959831 # ok 324 # SKIP Get and set data for VL 1728
6217 11:43:41.960148 # ok 325 Set VL 1744
6218 11:43:41.960558 # ok 326 # SKIP Disabled ZA for VL 1744
6219 11:43:41.960740 # ok 327 # SKIP Get and set data for VL 1744
6220 11:43:41.960907 # ok 328 Set VL 1760
6221 11:43:41.961056 # ok 329 # SKIP Disabled ZA for VL 1760
6222 11:43:41.961212 # ok 330 # SKIP Get and set data for VL 1760
6223 11:43:41.961356 # ok 331 Set VL 1776
6224 11:43:41.961505 # ok 332 # SKIP Disabled ZA for VL 1776
6225 11:43:41.961666 # ok 333 # SKIP Get and set data for VL 1776
6226 11:43:41.961867 # ok 334 Set VL 1792
6227 11:43:41.962035 # ok 335 # SKIP Disabled ZA for VL 1792
6228 11:43:41.962195 # ok 336 # SKIP Get and set data for VL 1792
6229 11:43:41.962354 # ok 337 Set VL 1808
6230 11:43:41.962511 # ok 338 # SKIP Disabled ZA for VL 1808
6231 11:43:41.962637 # ok 339 # SKIP Get and set data for VL 1808
6232 11:43:41.962751 # ok 340 Set VL 1824
6233 11:43:41.962866 # ok 341 # SKIP Disabled ZA for VL 1824
6234 11:43:41.962977 # ok 342 # SKIP Get and set data for VL 1824
6235 11:43:41.963087 # ok 343 Set VL 1840
6236 11:43:41.963196 # ok 344 # SKIP Disabled ZA for VL 1840
6237 11:43:41.963305 # ok 345 # SKIP Get and set data for VL 1840
6238 11:43:41.963415 # ok 346 Set VL 1856
6239 11:43:41.963523 # ok 347 # SKIP Disabled ZA for VL 1856
6240 11:43:41.963632 # ok 348 # SKIP Get and set data for VL 1856
6241 11:43:41.963742 # ok 349 Set VL 1872
6242 11:43:41.963876 # ok 350 # SKIP Disabled ZA for VL 1872
6243 11:43:41.963989 # ok 351 # SKIP Get and set data for VL 1872
6244 11:43:41.964099 # ok 352 Set VL 1888
6245 11:43:41.964209 # ok 353 # SKIP Disabled ZA for VL 1888
6246 11:43:41.964318 # ok 354 # SKIP Get and set data for VL 1888
6247 11:43:41.964427 # ok 355 Set VL 1904
6248 11:43:41.964535 # ok 356 # SKIP Disabled ZA for VL 1904
6249 11:43:41.978146 # ok 357 # SKIP Get and set data for VL 1904
6250 11:43:41.978568 # ok 358 Set VL 1920
6251 11:43:41.979900 # ok 359 # SKIP Disabled ZA for VL 1920
6252 11:43:41.980091 # ok 360 # SKIP Get and set data for VL 1920
6253 11:43:41.980292 # ok 361 Set VL 1936
6254 11:43:41.980534 # ok 362 # SKIP Disabled ZA for VL 1936
6255 11:43:41.980738 # ok 363 # SKIP Get and set data for VL 1936
6256 11:43:41.980912 # ok 364 Set VL 1952
6257 11:43:41.981061 # ok 365 # SKIP Disabled ZA for VL 1952
6258 11:43:41.981245 # ok 366 # SKIP Get and set data for VL 1952
6259 11:43:41.981464 # ok 367 Set VL 1968
6260 11:43:41.981729 # ok 368 # SKIP Disabled ZA for VL 1968
6261 11:43:41.981912 # ok 369 # SKIP Get and set data for VL 1968
6262 11:43:41.982107 # ok 370 Set VL 1984
6263 11:43:41.982261 # ok 371 # SKIP Disabled ZA for VL 1984
6264 11:43:41.982439 # ok 372 # SKIP Get and set data for VL 1984
6265 11:43:41.982645 # ok 373 Set VL 2000
6266 11:43:41.982801 # ok 374 # SKIP Disabled ZA for VL 2000
6267 11:43:41.982923 # ok 375 # SKIP Get and set data for VL 2000
6268 11:43:41.983033 # ok 376 Set VL 2016
6269 11:43:41.983142 # ok 377 # SKIP Disabled ZA for VL 2016
6270 11:43:41.983251 # ok 378 # SKIP Get and set data for VL 2016
6271 11:43:41.983360 # ok 379 Set VL 2032
6272 11:43:41.983474 # ok 380 # SKIP Disabled ZA for VL 2032
6273 11:43:41.983583 # ok 381 # SKIP Get and set data for VL 2032
6274 11:43:41.983694 # ok 382 Set VL 2048
6275 11:43:41.983803 # ok 383 # SKIP Disabled ZA for VL 2048
6276 11:43:41.983913 # ok 384 # SKIP Get and set data for VL 2048
6277 11:43:41.984024 # ok 385 Set VL 2064
6278 11:43:41.984134 # ok 386 # SKIP Disabled ZA for VL 2064
6279 11:43:41.984242 # ok 387 # SKIP Get and set data for VL 2064
6280 11:43:41.984382 # ok 388 Set VL 2080
6281 11:43:41.984500 # ok 389 # SKIP Disabled ZA for VL 2080
6282 11:43:41.984610 # ok 390 # SKIP Get and set data for VL 2080
6283 11:43:41.984724 # ok 391 Set VL 2096
6284 11:43:41.984837 # ok 392 # SKIP Disabled ZA for VL 2096
6285 11:43:41.987329 # ok 393 # SKIP Get and set data for VL 2096
6286 11:43:41.987549 # ok 394 Set VL 2112
6287 11:43:41.987940 # ok 395 # SKIP Disabled ZA for VL 2112
6288 11:43:41.988097 # ok 396 # SKIP Get and set data for VL 2112
6289 11:43:41.988228 # ok 397 Set VL 2128
6290 11:43:41.988360 # ok 398 # SKIP Disabled ZA for VL 2128
6291 11:43:41.988536 # ok 399 # SKIP Get and set data for VL 2128
6292 11:43:41.988679 # ok 400 Set VL 2144
6293 11:43:41.988851 # ok 401 # SKIP Disabled ZA for VL 2144
6294 11:43:41.989039 # ok 402 # SKIP Get and set data for VL 2144
6295 11:43:41.989229 # ok 403 Set VL 2160
6296 11:43:41.989402 # ok 404 # SKIP Disabled ZA for VL 2160
6297 11:43:41.989555 # ok 405 # SKIP Get and set data for VL 2160
6298 11:43:41.989721 # ok 406 Set VL 2176
6299 11:43:41.989932 # ok 407 # SKIP Disabled ZA for VL 2176
6300 11:43:41.990138 # ok 408 # SKIP Get and set data for VL 2176
6301 11:43:41.990326 # ok 409 Set VL 2192
6302 11:43:41.990531 # ok 410 # SKIP Disabled ZA for VL 2192
6303 11:43:41.990685 # ok 411 # SKIP Get and set data for VL 2192
6304 11:43:41.990804 # ok 412 Set VL 2208
6305 11:43:41.990973 # ok 413 # SKIP Disabled ZA for VL 2208
6306 11:43:41.991120 # ok 414 # SKIP Get and set data for VL 2208
6307 11:43:41.991236 # ok 415 Set VL 2224
6308 11:43:41.991380 # ok 416 # SKIP Disabled ZA for VL 2224
6309 11:43:41.991498 # ok 417 # SKIP Get and set data for VL 2224
6310 11:43:41.991611 # ok 418 Set VL 2240
6311 11:43:41.991722 # ok 419 # SKIP Disabled ZA for VL 2240
6312 11:43:41.991832 # ok 420 # SKIP Get and set data for VL 2240
6313 11:43:41.991943 # ok 421 Set VL 2256
6314 11:43:41.992053 # ok 422 # SKIP Disabled ZA for VL 2256
6315 11:43:41.992164 # ok 423 # SKIP Get and set data for VL 2256
6316 11:43:41.992274 # ok 424 Set VL 2272
6317 11:43:41.992384 # ok 425 # SKIP Disabled ZA for VL 2272
6318 11:43:41.992495 # ok 426 # SKIP Get and set data for VL 2272
6319 11:43:41.992604 # ok 427 Set VL 2288
6320 11:43:41.992714 # ok 428 # SKIP Disabled ZA for VL 2288
6321 11:43:41.992827 # ok 429 # SKIP Get and set data for VL 2288
6322 11:43:41.992938 # ok 430 Set VL 2304
6323 11:43:41.993047 # ok 431 # SKIP Disabled ZA for VL 2304
6324 11:43:41.993158 # ok 432 # SKIP Get and set data for VL 2304
6325 11:43:41.993268 # ok 433 Set VL 2320
6326 11:43:41.995418 # ok 434 # SKIP Disabled ZA for VL 2320
6327 11:43:41.995730 # ok 435 # SKIP Get and set data for VL 2320
6328 11:43:41.995827 # ok 436 Set VL 2336
6329 11:43:41.995912 # ok 437 # SKIP Disabled ZA for VL 2336
6330 11:43:41.995995 # ok 438 # SKIP Get and set data for VL 2336
6331 11:43:41.996091 # ok 439 Set VL 2352
6332 11:43:41.996176 # ok 440 # SKIP Disabled ZA for VL 2352
6333 11:43:41.996256 # ok 441 # SKIP Get and set data for VL 2352
6334 11:43:41.996359 # ok 442 Set VL 2368
6335 11:43:41.996444 # ok 443 # SKIP Disabled ZA for VL 2368
6336 11:43:41.996526 # ok 444 # SKIP Get and set data for VL 2368
6337 11:43:41.996621 # ok 445 Set VL 2384
6338 11:43:41.996705 # ok 446 # SKIP Disabled ZA for VL 2384
6339 11:43:41.996800 # ok 447 # SKIP Get and set data for VL 2384
6340 11:43:41.996883 # ok 448 Set VL 2400
6341 11:43:41.996978 # ok 449 # SKIP Disabled ZA for VL 2400
6342 11:43:41.997280 # ok 450 # SKIP Get and set data for VL 2400
6343 11:43:41.997418 # ok 451 Set VL 2416
6344 11:43:41.997537 # ok 452 # SKIP Disabled ZA for VL 2416
6345 11:43:41.997685 # ok 453 # SKIP Get and set data for VL 2416
6346 11:43:41.997790 # ok 454 Set VL 2432
6347 11:43:41.997882 # ok 455 # SKIP Disabled ZA for VL 2432
6348 11:43:41.997987 # ok 456 # SKIP Get and set data for VL 2432
6349 11:43:41.998086 # ok 457 Set VL 2448
6350 11:43:41.998200 # ok 458 # SKIP Disabled ZA for VL 2448
6351 11:43:41.998316 # ok 459 # SKIP Get and set data for VL 2448
6352 11:43:41.998426 # ok 460 Set VL 2464
6353 11:43:41.998529 # ok 461 # SKIP Disabled ZA for VL 2464
6354 11:43:41.998616 # ok 462 # SKIP Get and set data for VL 2464
6355 11:43:41.998700 # ok 463 Set VL 2480
6356 11:43:41.998804 # ok 464 # SKIP Disabled ZA for VL 2480
6357 11:43:41.998891 # ok 465 # SKIP Get and set data for VL 2480
6358 11:43:41.998976 # ok 466 Set VL 2496
6359 11:43:41.999059 # ok 467 # SKIP Disabled ZA for VL 2496
6360 11:43:42.003915 # ok 468 # SKIP Get and set data for VL 2496
6361 11:43:42.004431 # ok 469 Set VL 2512
6362 11:43:42.004621 # ok 470 # SKIP Disabled ZA for VL 2512
6363 11:43:42.004785 # ok 471 # SKIP Get and set data for VL 2512
6364 11:43:42.004942 # ok 472 Set VL 2528
6365 11:43:42.005080 # ok 473 # SKIP Disabled ZA for VL 2528
6366 11:43:42.005265 # ok 474 # SKIP Get and set data for VL 2528
6367 11:43:42.005458 # ok 475 Set VL 2544
6368 11:43:42.005682 # ok 476 # SKIP Disabled ZA for VL 2544
6369 11:43:42.005850 # ok 477 # SKIP Get and set data for VL 2544
6370 11:43:42.006010 # ok 478 Set VL 2560
6371 11:43:42.006158 # ok 479 # SKIP Disabled ZA for VL 2560
6372 11:43:42.006309 # ok 480 # SKIP Get and set data for VL 2560
6373 11:43:42.006457 # ok 481 Set VL 2576
6374 11:43:42.006630 # ok 482 # SKIP Disabled ZA for VL 2576
6375 11:43:42.006757 # ok 483 # SKIP Get and set data for VL 2576
6376 11:43:42.006887 # ok 484 Set VL 2592
6377 11:43:42.007003 # ok 485 # SKIP Disabled ZA for VL 2592
6378 11:43:42.007116 # ok 486 # SKIP Get and set data for VL 2592
6379 11:43:42.007230 # ok 487 Set VL 2608
6380 11:43:42.007342 # ok 488 # SKIP Disabled ZA for VL 2608
6381 11:43:42.007454 # ok 489 # SKIP Get and set data for VL 2608
6382 11:43:42.007566 # ok 490 Set VL 2624
6383 11:43:42.007680 # ok 491 # SKIP Disabled ZA for VL 2624
6384 11:43:42.007825 # ok 492 # SKIP Get and set data for VL 2624
6385 11:43:42.007944 # ok 493 Set VL 2640
6386 11:43:42.008059 # ok 494 # SKIP Disabled ZA for VL 2640
6387 11:43:42.008174 # ok 495 # SKIP Get and set data for VL 2640
6388 11:43:42.008289 # ok 496 Set VL 2656
6389 11:43:42.008401 # ok 497 # SKIP Disabled ZA for VL 2656
6390 11:43:42.008514 # ok 498 # SKIP Get and set data for VL 2656
6391 11:43:42.008627 # ok 499 Set VL 2672
6392 11:43:42.008739 # ok 500 # SKIP Disabled ZA for VL 2672
6393 11:43:42.008853 # ok 501 # SKIP Get and set data for VL 2672
6394 11:43:42.008965 # ok 502 Set VL 2688
6395 11:43:42.009077 # ok 503 # SKIP Disabled ZA for VL 2688
6396 11:43:42.009976 # ok 504 # SKIP Get and set data for VL 2688
6397 11:43:42.010378 # ok 505 Set VL 2704
6398 11:43:42.010558 # ok 506 # SKIP Disabled ZA for VL 2704
6399 11:43:42.010709 # ok 507 # SKIP Get and set data for VL 2704
6400 11:43:42.010846 # ok 508 Set VL 2720
6401 11:43:42.010992 # ok 509 # SKIP Disabled ZA for VL 2720
6402 11:43:42.011135 # ok 510 # SKIP Get and set data for VL 2720
6403 11:43:42.011273 # ok 511 Set VL 2736
6404 11:43:42.011491 # ok 512 # SKIP Disabled ZA for VL 2736
6405 11:43:42.011660 # ok 513 # SKIP Get and set data for VL 2736
6406 11:43:42.011852 # ok 514 Set VL 2752
6407 11:43:42.012015 # ok 515 # SKIP Disabled ZA for VL 2752
6408 11:43:42.012209 # ok 516 # SKIP Get and set data for VL 2752
6409 11:43:42.012384 # ok 517 Set VL 2768
6410 11:43:42.012553 # ok 518 # SKIP Disabled ZA for VL 2768
6411 11:43:42.012765 # ok 519 # SKIP Get and set data for VL 2768
6412 11:43:42.012907 # ok 520 Set VL 2784
6413 11:43:42.013030 # ok 521 # SKIP Disabled ZA for VL 2784
6414 11:43:42.013153 # ok 522 # SKIP Get and set data for VL 2784
6415 11:43:42.013283 # ok 523 Set VL 2800
6416 11:43:42.013406 # ok 524 # SKIP Disabled ZA for VL 2800
6417 11:43:42.013531 # ok 525 # SKIP Get and set data for VL 2800
6418 11:43:42.013674 # ok 526 Set VL 2816
6419 11:43:42.013800 # ok 527 # SKIP Disabled ZA for VL 2816
6420 11:43:42.013923 # ok 528 # SKIP Get and set data for VL 2816
6421 11:43:42.014047 # ok 529 Set VL 2832
6422 11:43:42.014170 # ok 530 # SKIP Disabled ZA for VL 2832
6423 11:43:42.014326 # ok 531 # SKIP Get and set data for VL 2832
6424 11:43:42.014451 # ok 532 Set VL 2848
6425 11:43:42.014638 # ok 533 # SKIP Disabled ZA for VL 2848
6426 11:43:42.014806 # ok 534 # SKIP Get and set data for VL 2848
6427 11:43:42.014934 # ok 535 Set VL 2864
6428 11:43:42.015048 # ok 536 # SKIP Disabled ZA for VL 2864
6429 11:43:42.015160 # ok 537 # SKIP Get and set data for VL 2864
6430 11:43:42.015276 # ok 538 Set VL 2880
6431 11:43:42.015388 # ok 539 # SKIP Disabled ZA for VL 2880
6432 11:43:42.015501 # ok 540 # SKIP Get and set data for VL 2880
6433 11:43:42.015615 # ok 541 Set VL 2896
6434 11:43:42.015729 # ok 542 # SKIP Disabled ZA for VL 2896
6435 11:43:42.015844 # ok 543 # SKIP Get and set data for VL 2896
6436 11:43:42.015956 # ok 544 Set VL 2912
6437 11:43:42.016069 # ok 545 # SKIP Disabled ZA for VL 2912
6438 11:43:42.016182 # ok 546 # SKIP Get and set data for VL 2912
6439 11:43:42.016295 # ok 547 Set VL 2928
6440 11:43:42.016408 # ok 548 # SKIP Disabled ZA for VL 2928
6441 11:43:42.016549 # ok 549 # SKIP Get and set data for VL 2928
6442 11:43:42.016672 # ok 550 Set VL 2944
6443 11:43:42.016786 # ok 551 # SKIP Disabled ZA for VL 2944
6444 11:43:42.019419 # ok 552 # SKIP Get and set data for VL 2944
6445 11:43:42.019550 # ok 553 Set VL 2960
6446 11:43:42.019840 # ok 554 # SKIP Disabled ZA for VL 2960
6447 11:43:42.019943 # ok 555 # SKIP Get and set data for VL 2960
6448 11:43:42.020032 # ok 556 Set VL 2976
6449 11:43:42.020115 # ok 557 # SKIP Disabled ZA for VL 2976
6450 11:43:42.020220 # ok 558 # SKIP Get and set data for VL 2976
6451 11:43:42.020305 # ok 559 Set VL 2992
6452 11:43:42.020387 # ok 560 # SKIP Disabled ZA for VL 2992
6453 11:43:42.020469 # ok 561 # SKIP Get and set data for VL 2992
6454 11:43:42.020567 # ok 562 Set VL 3008
6455 11:43:42.020651 # ok 563 # SKIP Disabled ZA for VL 3008
6456 11:43:42.020734 # ok 564 # SKIP Get and set data for VL 3008
6457 11:43:42.020834 # ok 565 Set VL 3024
6458 11:43:42.020922 # ok 566 # SKIP Disabled ZA for VL 3024
6459 11:43:42.021018 # ok 567 # SKIP Get and set data for VL 3024
6460 11:43:42.021101 # ok 568 Set VL 3040
6461 11:43:42.021198 # ok 569 # SKIP Disabled ZA for VL 3040
6462 11:43:42.021281 # ok 570 # SKIP Get and set data for VL 3040
6463 11:43:42.021378 # ok 571 Set VL 3056
6464 11:43:42.021474 # ok 572 # SKIP Disabled ZA for VL 3056
6465 11:43:42.021571 # ok 573 # SKIP Get and set data for VL 3056
6466 11:43:42.021677 # ok 574 Set VL 3072
6467 11:43:42.022006 # ok 575 # SKIP Disabled ZA for VL 3072
6468 11:43:42.022191 # ok 576 # SKIP Get and set data for VL 3072
6469 11:43:42.022351 # ok 577 Set VL 3088
6470 11:43:42.022558 # ok 578 # SKIP Disabled ZA for VL 3088
6471 11:43:42.022723 # ok 579 # SKIP Get and set data for VL 3088
6472 11:43:42.022851 # ok 580 Set VL 3104
6473 11:43:42.022966 # ok 581 # SKIP Disabled ZA for VL 3104
6474 11:43:42.023079 # ok 582 # SKIP Get and set data for VL 3104
6475 11:43:42.023192 # ok 583 Set VL 3120
6476 11:43:42.027451 # ok 584 # SKIP Disabled ZA for VL 3120
6477 11:43:42.027902 # ok 585 # SKIP Get and set data for VL 3120
6478 11:43:42.028061 # ok 586 Set VL 3136
6479 11:43:42.028181 # ok 587 # SKIP Disabled ZA for VL 3136
6480 11:43:42.028297 # ok 588 # SKIP Get and set data for VL 3136
6481 11:43:42.028410 # ok 589 Set VL 3152
6482 11:43:42.028574 # ok 590 # SKIP Disabled ZA for VL 3152
6483 11:43:42.028754 # ok 591 # SKIP Get and set data for VL 3152
6484 11:43:42.028927 # ok 592 Set VL 3168
6485 11:43:42.029076 # ok 593 # SKIP Disabled ZA for VL 3168
6486 11:43:42.029228 # ok 594 # SKIP Get and set data for VL 3168
6487 11:43:42.029353 # ok 595 Set VL 3184
6488 11:43:42.029479 # ok 596 # SKIP Disabled ZA for VL 3184
6489 11:43:42.029634 # ok 597 # SKIP Get and set data for VL 3184
6490 11:43:42.029841 # ok 598 Set VL 3200
6491 11:43:42.030008 # ok 599 # SKIP Disabled ZA for VL 3200
6492 11:43:42.030169 # ok 600 # SKIP Get and set data for VL 3200
6493 11:43:42.030328 # ok 601 Set VL 3216
6494 11:43:42.030514 # ok 602 # SKIP Disabled ZA for VL 3216
6495 11:43:42.030671 # ok 603 # SKIP Get and set data for VL 3216
6496 11:43:42.030789 # ok 604 Set VL 3232
6497 11:43:42.030899 # ok 605 # SKIP Disabled ZA for VL 3232
6498 11:43:42.031013 # ok 606 # SKIP Get and set data for VL 3232
6499 11:43:42.031123 # ok 607 Set VL 3248
6500 11:43:42.031263 # ok 608 # SKIP Disabled ZA for VL 3248
6501 11:43:42.031380 # ok 609 # SKIP Get and set data for VL 3248
6502 11:43:42.031492 # ok 610 Set VL 3264
6503 11:43:42.031605 # ok 611 # SKIP Disabled ZA for VL 3264
6504 11:43:42.031714 # ok 612 # SKIP Get and set data for VL 3264
6505 11:43:42.031824 # ok 613 Set VL 3280
6506 11:43:42.031933 # ok 614 # SKIP Disabled ZA for VL 3280
6507 11:43:42.032043 # ok 615 # SKIP Get and set data for VL 3280
6508 11:43:42.032152 # ok 616 Set VL 3296
6509 11:43:42.035327 # ok 617 # SKIP Disabled ZA for VL 3296
6510 11:43:42.035641 # ok 618 # SKIP Get and set data for VL 3296
6511 11:43:42.035712 # ok 619 Set VL 3312
6512 11:43:42.035776 # ok 620 # SKIP Disabled ZA for VL 3312
6513 11:43:42.035842 # ok 621 # SKIP Get and set data for VL 3312
6514 11:43:42.035903 # ok 622 Set VL 3328
6515 11:43:42.035980 # ok 623 # SKIP Disabled ZA for VL 3328
6516 11:43:42.036045 # ok 624 # SKIP Get and set data for VL 3328
6517 11:43:42.036111 # ok 625 Set VL 3344
6518 11:43:42.036173 # ok 626 # SKIP Disabled ZA for VL 3344
6519 11:43:42.036245 # ok 627 # SKIP Get and set data for VL 3344
6520 11:43:42.036309 # ok 628 Set VL 3360
6521 11:43:42.036376 # ok 629 # SKIP Disabled ZA for VL 3360
6522 11:43:42.036462 # ok 630 # SKIP Get and set data for VL 3360
6523 11:43:42.036530 # ok 631 Set VL 3376
6524 11:43:42.036607 # ok 632 # SKIP Disabled ZA for VL 3376
6525 11:43:42.036686 # ok 633 # SKIP Get and set data for VL 3376
6526 11:43:42.036778 # ok 634 Set VL 3392
6527 11:43:42.036894 # ok 635 # SKIP Disabled ZA for VL 3392
6528 11:43:42.036985 # ok 636 # SKIP Get and set data for VL 3392
6529 11:43:42.037051 # ok 637 Set VL 3408
6530 11:43:42.037112 # ok 638 # SKIP Disabled ZA for VL 3408
6531 11:43:42.037173 # ok 639 # SKIP Get and set data for VL 3408
6532 11:43:42.037256 # ok 640 Set VL 3424
6533 11:43:42.037334 # ok 641 # SKIP Disabled ZA for VL 3424
6534 11:43:42.037401 # ok 642 # SKIP Get and set data for VL 3424
6535 11:43:42.037463 # ok 643 Set VL 3440
6536 11:43:42.037572 # ok 644 # SKIP Disabled ZA for VL 3440
6537 11:43:42.037670 # ok 645 # SKIP Get and set data for VL 3440
6538 11:43:42.037762 # ok 646 Set VL 3456
6539 11:43:42.037840 # ok 647 # SKIP Disabled ZA for VL 3456
6540 11:43:42.037939 # ok 648 # SKIP Get and set data for VL 3456
6541 11:43:42.038028 # ok 649 Set VL 3472
6542 11:43:42.038100 # ok 650 # SKIP Disabled ZA for VL 3472
6543 11:43:42.038173 # ok 651 # SKIP Get and set data for VL 3472
6544 11:43:42.038259 # ok 652 Set VL 3488
6545 11:43:42.038333 # ok 653 # SKIP Disabled ZA for VL 3488
6546 11:43:42.038409 # ok 654 # SKIP Get and set data for VL 3488
6547 11:43:42.038484 # ok 655 Set VL 3504
6548 11:43:42.038567 # ok 656 # SKIP Disabled ZA for VL 3504
6549 11:43:42.038637 # ok 657 # SKIP Get and set data for VL 3504
6550 11:43:42.038697 # ok 658 Set VL 3520
6551 11:43:42.039998 # ok 659 # SKIP Disabled ZA for VL 3520
6552 11:43:42.040296 # ok 660 # SKIP Get and set data for VL 3520
6553 11:43:42.040389 # ok 661 Set VL 3536
6554 11:43:42.040469 # ok 662 # SKIP Disabled ZA for VL 3536
6555 11:43:42.040552 # ok 663 # SKIP Get and set data for VL 3536
6556 11:43:42.040654 # ok 664 Set VL 3552
6557 11:43:42.040740 # ok 665 # SKIP Disabled ZA for VL 3552
6558 11:43:42.040822 # ok 666 # SKIP Get and set data for VL 3552
6559 11:43:42.040906 # ok 667 Set VL 3568
6560 11:43:42.041026 # ok 668 # SKIP Disabled ZA for VL 3568
6561 11:43:42.041126 # ok 669 # SKIP Get and set data for VL 3568
6562 11:43:42.041201 # ok 670 Set VL 3584
6563 11:43:42.041278 # ok 671 # SKIP Disabled ZA for VL 3584
6564 11:43:42.041351 # ok 672 # SKIP Get and set data for VL 3584
6565 11:43:42.041462 # ok 673 Set VL 3600
6566 11:43:42.041542 # ok 674 # SKIP Disabled ZA for VL 3600
6567 11:43:42.041654 # ok 675 # SKIP Get and set data for VL 3600
6568 11:43:42.041736 # ok 676 Set VL 3616
6569 11:43:42.041851 # ok 677 # SKIP Disabled ZA for VL 3616
6570 11:43:42.041949 # ok 678 # SKIP Get and set data for VL 3616
6571 11:43:42.042053 # ok 679 Set VL 3632
6572 11:43:42.042135 # ok 680 # SKIP Disabled ZA for VL 3632
6573 11:43:42.042216 # ok 681 # SKIP Get and set data for VL 3632
6574 11:43:42.042299 # ok 682 Set VL 3648
6575 11:43:42.042394 # ok 683 # SKIP Disabled ZA for VL 3648
6576 11:43:42.042498 # ok 684 # SKIP Get and set data for VL 3648
6577 11:43:42.042598 # ok 685 Set VL 3664
6578 11:43:42.042701 # ok 686 # SKIP Disabled ZA for VL 3664
6579 11:43:42.046058 # ok 687 # SKIP Get and set data for VL 3664
6580 11:43:42.046403 # ok 688 Set VL 3680
6581 11:43:42.046486 # ok 689 # SKIP Disabled ZA for VL 3680
6582 11:43:42.046563 # ok 690 # SKIP Get and set data for VL 3680
6583 11:43:42.046630 # ok 691 Set VL 3696
6584 11:43:42.046702 # ok 692 # SKIP Disabled ZA for VL 3696
6585 11:43:42.046764 # ok 693 # SKIP Get and set data for VL 3696
6586 11:43:42.047487 # ok 694 Set VL 3712
6587 11:43:42.047639 # ok 695 # SKIP Disabled ZA for VL 3712
6588 11:43:42.047771 # ok 696 # SKIP Get and set data for VL 3712
6589 11:43:42.048084 # ok 697 Set VL 3728
6590 11:43:42.048345 # ok 698 # SKIP Disabled ZA for VL 3728
6591 11:43:42.048605 # ok 699 # SKIP Get and set data for VL 3728
6592 11:43:42.048850 # ok 700 Set VL 3744
6593 11:43:42.049104 # ok 701 # SKIP Disabled ZA for VL 3744
6594 11:43:42.049385 # ok 702 # SKIP Get and set data for VL 3744
6595 11:43:42.049590 # ok 703 Set VL 3760
6596 11:43:42.049812 # ok 704 # SKIP Disabled ZA for VL 3760
6597 11:43:42.050020 # ok 705 # SKIP Get and set data for VL 3760
6598 11:43:42.050257 # ok 706 Set VL 3776
6599 11:43:42.050544 # ok 707 # SKIP Disabled ZA for VL 3776
6600 11:43:42.050827 # ok 708 # SKIP Get and set data for VL 3776
6601 11:43:42.051114 # ok 709 Set VL 3792
6602 11:43:42.051308 # ok 710 # SKIP Disabled ZA for VL 3792
6603 11:43:42.051520 # ok 711 # SKIP Get and set data for VL 3792
6604 11:43:42.051698 # ok 712 Set VL 3808
6605 11:43:42.051886 # ok 713 # SKIP Disabled ZA for VL 3808
6606 11:43:42.052028 # ok 714 # SKIP Get and set data for VL 3808
6607 11:43:42.052211 # ok 715 Set VL 3824
6608 11:43:42.052359 # ok 716 # SKIP Disabled ZA for VL 3824
6609 11:43:42.052474 # ok 717 # SKIP Get and set data for VL 3824
6610 11:43:42.052586 # ok 718 Set VL 3840
6611 11:43:42.052697 # ok 719 # SKIP Disabled ZA for VL 3840
6612 11:43:42.052808 # ok 720 # SKIP Get and set data for VL 3840
6613 11:43:42.052928 # ok 721 Set VL 3856
6614 11:43:42.053087 # ok 722 # SKIP Disabled ZA for VL 3856
6615 11:43:42.053220 # ok 723 # SKIP Get and set data for VL 3856
6616 11:43:42.053341 # ok 724 Set VL 3872
6617 11:43:42.053510 # ok 725 # SKIP Disabled ZA for VL 3872
6618 11:43:42.053693 # ok 726 # SKIP Get and set data for VL 3872
6619 11:43:42.053858 # ok 727 Set VL 3888
6620 11:43:42.053982 # ok 728 # SKIP Disabled ZA for VL 3888
6621 11:43:42.054093 # ok 729 # SKIP Get and set data for VL 3888
6622 11:43:42.054204 # ok 730 Set VL 3904
6623 11:43:42.054314 # ok 731 # SKIP Disabled ZA for VL 3904
6624 11:43:42.054426 # ok 732 # SKIP Get and set data for VL 3904
6625 11:43:42.055475 # ok 733 Set VL 3920
6626 11:43:42.056571 # ok 734 # SKIP Disabled ZA for VL 3920
6627 11:43:42.056723 # ok 735 # SKIP Get and set data for VL 3920
6628 11:43:42.056842 # ok 736 Set VL 3936
6629 11:43:42.056956 # ok 737 # SKIP Disabled ZA for VL 3936
6630 11:43:42.057070 # ok 738 # SKIP Get and set data for VL 3936
6631 11:43:42.057183 # ok 739 Set VL 3952
6632 11:43:42.057295 # ok 740 # SKIP Disabled ZA for VL 3952
6633 11:43:42.057407 # ok 741 # SKIP Get and set data for VL 3952
6634 11:43:42.057520 # ok 742 Set VL 3968
6635 11:43:42.057632 # ok 743 # SKIP Disabled ZA for VL 3968
6636 11:43:42.057799 # ok 744 # SKIP Get and set data for VL 3968
6637 11:43:42.057925 # ok 745 Set VL 3984
6638 11:43:42.058038 # ok 746 # SKIP Disabled ZA for VL 3984
6639 11:43:42.058151 # ok 747 # SKIP Get and set data for VL 3984
6640 11:43:42.058264 # ok 748 Set VL 4000
6641 11:43:42.058375 # ok 749 # SKIP Disabled ZA for VL 4000
6642 11:43:42.058487 # ok 750 # SKIP Get and set data for VL 4000
6643 11:43:42.058600 # ok 751 Set VL 4016
6644 11:43:42.058930 # ok 752 # SKIP Disabled ZA for VL 4016
6645 11:43:42.059055 # ok 753 # SKIP Get and set data for VL 4016
6646 11:43:42.059170 # ok 754 Set VL 4032
6647 11:43:42.059285 # ok 755 # SKIP Disabled ZA for VL 4032
6648 11:43:42.059398 # ok 756 # SKIP Get and set data for VL 4032
6649 11:43:42.059511 # ok 757 Set VL 4048
6650 11:43:42.059624 # ok 758 # SKIP Disabled ZA for VL 4048
6651 11:43:42.059736 # ok 759 # SKIP Get and set data for VL 4048
6652 11:43:42.059875 # ok 760 Set VL 4064
6653 11:43:42.060059 # ok 761 # SKIP Disabled ZA for VL 4064
6654 11:43:42.060185 # ok 762 # SKIP Get and set data for VL 4064
6655 11:43:42.060299 # ok 763 Set VL 4080
6656 11:43:42.060411 # ok 764 # SKIP Disabled ZA for VL 4080
6657 11:43:42.060525 # ok 765 # SKIP Get and set data for VL 4080
6658 11:43:42.060636 # ok 766 Set VL 4096
6659 11:43:42.060748 # ok 767 # SKIP Disabled ZA for VL 4096
6660 11:43:42.060860 # ok 768 # SKIP Get and set data for VL 4096
6661 11:43:42.060972 # ok 769 Set VL 4112
6662 11:43:42.061083 # ok 770 # SKIP Disabled ZA for VL 4112
6663 11:43:42.061197 # ok 771 # SKIP Get and set data for VL 4112
6664 11:43:42.061310 # ok 772 Set VL 4128
6665 11:43:42.061421 # ok 773 # SKIP Disabled ZA for VL 4128
6666 11:43:42.061533 # ok 774 # SKIP Get and set data for VL 4128
6667 11:43:42.061656 # ok 775 Set VL 4144
6668 11:43:42.061771 # ok 776 # SKIP Disabled ZA for VL 4144
6669 11:43:42.061884 # ok 777 # SKIP Get and set data for VL 4144
6670 11:43:42.061995 # ok 778 Set VL 4160
6671 11:43:42.062107 # ok 779 # SKIP Disabled ZA for VL 4160
6672 11:43:42.062218 # ok 780 # SKIP Get and set data for VL 4160
6673 11:43:42.071289 # ok 781 Set VL 4176
6674 11:43:42.071493 # ok 782 # SKIP Disabled ZA for VL 4176
6675 11:43:42.071612 # ok 783 # SKIP Get and set data for VL 4176
6676 11:43:42.072157 # ok 784 Set VL 4192
6677 11:43:42.072316 # ok 785 # SKIP Disabled ZA for VL 4192
6678 11:43:42.072434 # ok 786 # SKIP Get and set data for VL 4192
6679 11:43:42.072549 # ok 787 Set VL 4208
6680 11:43:42.072664 # ok 788 # SKIP Disabled ZA for VL 4208
6681 11:43:42.072778 # ok 789 # SKIP Get and set data for VL 4208
6682 11:43:42.072890 # ok 790 Set VL 4224
6683 11:43:42.073009 # ok 791 # SKIP Disabled ZA for VL 4224
6684 11:43:42.073126 # ok 792 # SKIP Get and set data for VL 4224
6685 11:43:42.073240 # ok 793 Set VL 4240
6686 11:43:42.073353 # ok 794 # SKIP Disabled ZA for VL 4240
6687 11:43:42.073464 # ok 795 # SKIP Get and set data for VL 4240
6688 11:43:42.073791 # ok 796 Set VL 4256
6689 11:43:42.073920 # ok 797 # SKIP Disabled ZA for VL 4256
6690 11:43:42.074035 # ok 798 # SKIP Get and set data for VL 4256
6691 11:43:42.074149 # ok 799 Set VL 4272
6692 11:43:42.074261 # ok 800 # SKIP Disabled ZA for VL 4272
6693 11:43:42.074375 # ok 801 # SKIP Get and set data for VL 4272
6694 11:43:42.074489 # ok 802 Set VL 4288
6695 11:43:42.074602 # ok 803 # SKIP Disabled ZA for VL 4288
6696 11:43:42.074715 # ok 804 # SKIP Get and set data for VL 4288
6697 11:43:42.074827 # ok 805 Set VL 4304
6698 11:43:42.074939 # ok 806 # SKIP Disabled ZA for VL 4304
6699 11:43:42.075053 # ok 807 # SKIP Get and set data for VL 4304
6700 11:43:42.075165 # ok 808 Set VL 4320
6701 11:43:42.075276 # ok 809 # SKIP Disabled ZA for VL 4320
6702 11:43:42.075391 # ok 810 # SKIP Get and set data for VL 4320
6703 11:43:42.075504 # ok 811 Set VL 4336
6704 11:43:42.075617 # ok 812 # SKIP Disabled ZA for VL 4336
6705 11:43:42.075729 # ok 813 # SKIP Get and set data for VL 4336
6706 11:43:42.075842 # ok 814 Set VL 4352
6707 11:43:42.075954 # ok 815 # SKIP Disabled ZA for VL 4352
6708 11:43:42.076068 # ok 816 # SKIP Get and set data for VL 4352
6709 11:43:42.076182 # ok 817 Set VL 4368
6710 11:43:42.076295 # ok 818 # SKIP Disabled ZA for VL 4368
6711 11:43:42.076434 # ok 819 # SKIP Get and set data for VL 4368
6712 11:43:42.076551 # ok 820 Set VL 4384
6713 11:43:42.076664 # ok 821 # SKIP Disabled ZA for VL 4384
6714 11:43:42.087535 # ok 822 # SKIP Get and set data for VL 4384
6715 11:43:42.087846 # ok 823 Set VL 4400
6716 11:43:42.088270 # ok 824 # SKIP Disabled ZA for VL 4400
6717 11:43:42.088462 # ok 825 # SKIP Get and set data for VL 4400
6718 11:43:42.088625 # ok 826 Set VL 4416
6719 11:43:42.088780 # ok 827 # SKIP Disabled ZA for VL 4416
6720 11:43:42.088937 # ok 828 # SKIP Get and set data for VL 4416
6721 11:43:42.089087 # ok 829 Set VL 4432
6722 11:43:42.089234 # ok 830 # SKIP Disabled ZA for VL 4432
6723 11:43:42.089439 # ok 831 # SKIP Get and set data for VL 4432
6724 11:43:42.089603 # ok 832 Set VL 4448
6725 11:43:42.089801 # ok 833 # SKIP Disabled ZA for VL 4448
6726 11:43:42.090039 # ok 834 # SKIP Get and set data for VL 4448
6727 11:43:42.090218 # ok 835 Set VL 4464
6728 11:43:42.090414 # ok 836 # SKIP Disabled ZA for VL 4464
6729 11:43:42.090572 # ok 837 # SKIP Get and set data for VL 4464
6730 11:43:42.090696 # ok 838 Set VL 4480
6731 11:43:42.090809 # ok 839 # SKIP Disabled ZA for VL 4480
6732 11:43:42.090922 # ok 840 # SKIP Get and set data for VL 4480
6733 11:43:42.091038 # ok 841 Set VL 4496
6734 11:43:42.091150 # ok 842 # SKIP Disabled ZA for VL 4496
6735 11:43:42.091262 # ok 843 # SKIP Get and set data for VL 4496
6736 11:43:42.091375 # ok 844 Set VL 4512
6737 11:43:42.091488 # ok 845 # SKIP Disabled ZA for VL 4512
6738 11:43:42.091599 # ok 846 # SKIP Get and set data for VL 4512
6739 11:43:42.091710 # ok 847 Set VL 4528
6740 11:43:42.091821 # ok 848 # SKIP Disabled ZA for VL 4528
6741 11:43:42.091936 # ok 849 # SKIP Get and set data for VL 4528
6742 11:43:42.092051 # ok 850 Set VL 4544
6743 11:43:42.092163 # ok 851 # SKIP Disabled ZA for VL 4544
6744 11:43:42.092314 # ok 852 # SKIP Get and set data for VL 4544
6745 11:43:42.092492 # ok 853 Set VL 4560
6746 11:43:42.092615 # ok 854 # SKIP Disabled ZA for VL 4560
6747 11:43:42.092731 # ok 855 # SKIP Get and set data for VL 4560
6748 11:43:42.092845 # ok 856 Set VL 4576
6749 11:43:42.092957 # ok 857 # SKIP Disabled ZA for VL 4576
6750 11:43:42.093070 # ok 858 # SKIP Get and set data for VL 4576
6751 11:43:42.093221 # ok 859 Set VL 4592
6752 11:43:42.102254 # ok 860 # SKIP Disabled ZA for VL 4592
6753 11:43:42.102709 # ok 861 # SKIP Get and set data for VL 4592
6754 11:43:42.102802 # ok 862 Set VL 4608
6755 11:43:42.102877 # ok 863 # SKIP Disabled ZA for VL 4608
6756 11:43:42.102952 # ok 864 # SKIP Get and set data for VL 4608
6757 11:43:42.103024 # ok 865 Set VL 4624
6758 11:43:42.107672 # ok 866 # SKIP Disabled ZA for VL 4624
6759 11:43:42.108023 # ok 867 # SKIP Get and set data for VL 4624
6760 11:43:42.108112 # ok 868 Set VL 4640
6761 11:43:42.108192 # ok 869 # SKIP Disabled ZA for VL 4640
6762 11:43:42.108270 # ok 870 # SKIP Get and set data for VL 4640
6763 11:43:42.108367 # ok 871 Set VL 4656
6764 11:43:42.108435 # ok 872 # SKIP Disabled ZA for VL 4656
6765 11:43:42.108511 # ok 873 # SKIP Get and set data for VL 4656
6766 11:43:42.108589 # ok 874 Set VL 4672
6767 11:43:42.108710 # ok 875 # SKIP Disabled ZA for VL 4672
6768 11:43:42.108808 # ok 876 # SKIP Get and set data for VL 4672
6769 11:43:42.108898 # ok 877 Set VL 4688
6770 11:43:42.108993 # ok 878 # SKIP Disabled ZA for VL 4688
6771 11:43:42.109104 # ok 879 # SKIP Get and set data for VL 4688
6772 11:43:42.109181 # ok 880 Set VL 4704
6773 11:43:42.109246 # ok 881 # SKIP Disabled ZA for VL 4704
6774 11:43:42.109315 # ok 882 # SKIP Get and set data for VL 4704
6775 11:43:42.109408 # ok 883 Set VL 4720
6776 11:43:42.109497 # ok 884 # SKIP Disabled ZA for VL 4720
6777 11:43:42.109599 # ok 885 # SKIP Get and set data for VL 4720
6778 11:43:42.109701 # ok 886 Set VL 4736
6779 11:43:42.109822 # ok 887 # SKIP Disabled ZA for VL 4736
6780 11:43:42.109931 # ok 888 # SKIP Get and set data for VL 4736
6781 11:43:42.110027 # ok 889 Set VL 4752
6782 11:43:42.110107 # ok 890 # SKIP Disabled ZA for VL 4752
6783 11:43:42.110219 # ok 891 # SKIP Get and set data for VL 4752
6784 11:43:42.110321 # ok 892 Set VL 4768
6785 11:43:42.110403 # ok 893 # SKIP Disabled ZA for VL 4768
6786 11:43:42.110481 # ok 894 # SKIP Get and set data for VL 4768
6787 11:43:42.110555 # ok 895 Set VL 4784
6788 11:43:42.110658 # ok 896 # SKIP Disabled ZA for VL 4784
6789 11:43:42.110733 # ok 897 # SKIP Get and set data for VL 4784
6790 11:43:42.110794 # ok 898 Set VL 4800
6791 11:43:42.110852 # ok 899 # SKIP Disabled ZA for VL 4800
6792 11:43:42.113223 # ok 900 # SKIP Get and set data for VL 4800
6793 11:43:42.113595 # ok 901 Set VL 4816
6794 11:43:42.113811 # ok 902 # SKIP Disabled ZA for VL 4816
6795 11:43:42.113987 # ok 903 # SKIP Get and set data for VL 4816
6796 11:43:42.114183 # ok 904 Set VL 4832
6797 11:43:42.114350 # ok 905 # SKIP Disabled ZA for VL 4832
6798 11:43:42.114547 # ok 906 # SKIP Get and set data for VL 4832
6799 11:43:42.114675 # ok 907 Set VL 4848
6800 11:43:42.114789 # ok 908 # SKIP Disabled ZA for VL 4848
6801 11:43:42.114902 # ok 909 # SKIP Get and set data for VL 4848
6802 11:43:42.115015 # ok 910 Set VL 4864
6803 11:43:42.115127 # ok 911 # SKIP Disabled ZA for VL 4864
6804 11:43:42.115238 # ok 912 # SKIP Get and set data for VL 4864
6805 11:43:42.115350 # ok 913 Set VL 4880
6806 11:43:42.115461 # ok 914 # SKIP Disabled ZA for VL 4880
6807 11:43:42.115571 # ok 915 # SKIP Get and set data for VL 4880
6808 11:43:42.115707 # ok 916 Set VL 4896
6809 11:43:42.121163 # ok 917 # SKIP Disabled ZA for VL 4896
6810 11:43:42.121364 # ok 918 # SKIP Get and set data for VL 4896
6811 11:43:42.121474 # ok 919 Set VL 4912
6812 11:43:42.121562 # ok 920 # SKIP Disabled ZA for VL 4912
6813 11:43:42.121656 # ok 921 # SKIP Get and set data for VL 4912
6814 11:43:42.121760 # ok 922 Set VL 4928
6815 11:43:42.121845 # ok 923 # SKIP Disabled ZA for VL 4928
6816 11:43:42.121930 # ok 924 # SKIP Get and set data for VL 4928
6817 11:43:42.122028 # ok 925 Set VL 4944
6818 11:43:42.122120 # ok 926 # SKIP Disabled ZA for VL 4944
6819 11:43:42.122223 # ok 927 # SKIP Get and set data for VL 4944
6820 11:43:42.122309 # ok 928 Set VL 4960
6821 11:43:42.122408 # ok 929 # SKIP Disabled ZA for VL 4960
6822 11:43:42.122494 # ok 930 # SKIP Get and set data for VL 4960
6823 11:43:42.122590 # ok 931 Set VL 4976
6824 11:43:42.122670 # ok 932 # SKIP Disabled ZA for VL 4976
6825 11:43:42.127944 # ok 933 # SKIP Get and set data for VL 4976
6826 11:43:42.128130 # ok 934 Set VL 4992
6827 11:43:42.128214 # ok 935 # SKIP Disabled ZA for VL 4992
6828 11:43:42.128315 # ok 936 # SKIP Get and set data for VL 4992
6829 11:43:42.128400 # ok 937 Set VL 5008
6830 11:43:42.128498 # ok 938 # SKIP Disabled ZA for VL 5008
6831 11:43:42.128583 # ok 939 # SKIP Get and set data for VL 5008
6832 11:43:42.128679 # ok 940 Set VL 5024
6833 11:43:42.128763 # ok 941 # SKIP Disabled ZA for VL 5024
6834 11:43:42.128859 # ok 942 # SKIP Get and set data for VL 5024
6835 11:43:42.128944 # ok 943 Set VL 5040
6836 11:43:42.129042 # ok 944 # SKIP Disabled ZA for VL 5040
6837 11:43:42.129148 # ok 945 # SKIP Get and set data for VL 5040
6838 11:43:42.129245 # ok 946 Set VL 5056
6839 11:43:42.129328 # ok 947 # SKIP Disabled ZA for VL 5056
6840 11:43:42.129424 # ok 948 # SKIP Get and set data for VL 5056
6841 11:43:42.129523 # ok 949 Set VL 5072
6842 11:43:42.129619 # ok 950 # SKIP Disabled ZA for VL 5072
6843 11:43:42.129726 # ok 951 # SKIP Get and set data for VL 5072
6844 11:43:42.129824 # ok 952 Set VL 5088
6845 11:43:42.130113 # ok 953 # SKIP Disabled ZA for VL 5088
6846 11:43:42.130203 # ok 954 # SKIP Get and set data for VL 5088
6847 11:43:42.130286 # ok 955 Set VL 5104
6848 11:43:42.130381 # ok 956 # SKIP Disabled ZA for VL 5104
6849 11:43:42.130464 # ok 957 # SKIP Get and set data for VL 5104
6850 11:43:42.130558 # ok 958 Set VL 5120
6851 11:43:42.130639 # ok 959 # SKIP Disabled ZA for VL 5120
6852 11:43:42.130729 # ok 960 # SKIP Get and set data for VL 5120
6853 11:43:42.131473 # ok 961 Set VL 5136
6854 11:43:42.131771 # ok 962 # SKIP Disabled ZA for VL 5136
6855 11:43:42.131866 # ok 963 # SKIP Get and set data for VL 5136
6856 11:43:42.131934 # ok 964 Set VL 5152
6857 11:43:42.132027 # ok 965 # SKIP Disabled ZA for VL 5152
6858 11:43:42.132111 # ok 966 # SKIP Get and set data for VL 5152
6859 11:43:42.132187 # ok 967 Set VL 5168
6860 11:43:42.132282 # ok 968 # SKIP Disabled ZA for VL 5168
6861 11:43:42.132362 # ok 969 # SKIP Get and set data for VL 5168
6862 11:43:42.132439 # ok 970 Set VL 5184
6863 11:43:42.132517 # ok 971 # SKIP Disabled ZA for VL 5184
6864 11:43:42.132609 # ok 972 # SKIP Get and set data for VL 5184
6865 11:43:42.132685 # ok 973 Set VL 5200
6866 11:43:42.132761 # ok 974 # SKIP Disabled ZA for VL 5200
6867 11:43:42.132837 # ok 975 # SKIP Get and set data for VL 5200
6868 11:43:42.132928 # ok 976 Set VL 5216
6869 11:43:42.133005 # ok 977 # SKIP Disabled ZA for VL 5216
6870 11:43:42.133075 # ok 978 # SKIP Get and set data for VL 5216
6871 11:43:42.133149 # ok 979 Set VL 5232
6872 11:43:42.133212 # ok 980 # SKIP Disabled ZA for VL 5232
6873 11:43:42.133298 # ok 981 # SKIP Get and set data for VL 5232
6874 11:43:42.133375 # ok 982 Set VL 5248
6875 11:43:42.133447 # ok 983 # SKIP Disabled ZA for VL 5248
6876 11:43:42.133514 # ok 984 # SKIP Get and set data for VL 5248
6877 11:43:42.133583 # ok 985 Set VL 5264
6878 11:43:42.133668 # ok 986 # SKIP Disabled ZA for VL 5264
6879 11:43:42.133746 # ok 987 # SKIP Get and set data for VL 5264
6880 11:43:42.133820 # ok 988 Set VL 5280
6881 11:43:42.133896 # ok 989 # SKIP Disabled ZA for VL 5280
6882 11:43:42.133967 # ok 990 # SKIP Get and set data for VL 5280
6883 11:43:42.134048 # ok 991 Set VL 5296
6884 11:43:42.134122 # ok 992 # SKIP Disabled ZA for VL 5296
6885 11:43:42.134196 # ok 993 # SKIP Get and set data for VL 5296
6886 11:43:42.134267 # ok 994 Set VL 5312
6887 11:43:42.134332 # ok 995 # SKIP Disabled ZA for VL 5312
6888 11:43:42.134412 # ok 996 # SKIP Get and set data for VL 5312
6889 11:43:42.134482 # ok 997 Set VL 5328
6890 11:43:42.134551 # ok 998 # SKIP Disabled ZA for VL 5328
6891 11:43:42.134611 # ok 999 # SKIP Get and set data for VL 5328
6892 11:43:42.134684 # ok 1000 Set VL 5344
6893 11:43:42.134744 # ok 1001 # SKIP Disabled ZA for VL 5344
6894 11:43:42.134803 # ok 1002 # SKIP Get and set data for VL 5344
6895 11:43:42.134861 # ok 1003 Set VL 5360
6896 11:43:42.139365 # ok 1004 # SKIP Disabled ZA for VL 5360
6897 11:43:42.139524 # ok 1005 # SKIP Get and set data for VL 5360
6898 11:43:42.139819 # ok 1006 Set VL 5376
6899 11:43:42.139927 # ok 1007 # SKIP Disabled ZA for VL 5376
6900 11:43:42.140020 # ok 1008 # SKIP Get and set data for VL 5376
6901 11:43:42.140105 # ok 1009 Set VL 5392
6902 11:43:42.140186 # ok 1010 # SKIP Disabled ZA for VL 5392
6903 11:43:42.140283 # ok 1011 # SKIP Get and set data for VL 5392
6904 11:43:42.140378 # ok 1012 Set VL 5408
6905 11:43:42.140474 # ok 1013 # SKIP Disabled ZA for VL 5408
6906 11:43:42.140556 # ok 1014 # SKIP Get and set data for VL 5408
6907 11:43:42.140637 # ok 1015 Set VL 5424
6908 11:43:42.140732 # ok 1016 # SKIP Disabled ZA for VL 5424
6909 11:43:42.140814 # ok 1017 # SKIP Get and set data for VL 5424
6910 11:43:42.140890 # ok 1018 Set VL 5440
6911 11:43:42.140966 # ok 1019 # SKIP Disabled ZA for VL 5440
6912 11:43:42.141053 # ok 1020 # SKIP Get and set data for VL 5440
6913 11:43:42.141137 # ok 1021 Set VL 5456
6914 11:43:42.141208 # ok 1022 # SKIP Disabled ZA for VL 5456
6915 11:43:42.141284 # ok 1023 # SKIP Get and set data for VL 5456
6916 11:43:42.141376 # ok 1024 Set VL 5472
6917 11:43:42.141459 # ok 1025 # SKIP Disabled ZA for VL 5472
6918 11:43:42.141537 # ok 1026 # SKIP Get and set data for VL 5472
6919 11:43:42.141631 # ok 1027 Set VL 5488
6920 11:43:42.141718 # ok 1028 # SKIP Disabled ZA for VL 5488
6921 11:43:42.141794 # ok 1029 # SKIP Get and set data for VL 5488
6922 11:43:42.141869 # ok 1030 Set VL 5504
6923 11:43:42.141962 # ok 1031 # SKIP Disabled ZA for VL 5504
6924 11:43:42.142040 # ok 1032 # SKIP Get and set data for VL 5504
6925 11:43:42.142115 # ok 1033 Set VL 5520
6926 11:43:42.142203 # ok 1034 # SKIP Disabled ZA for VL 5520
6927 11:43:42.142282 # ok 1035 # SKIP Get and set data for VL 5520
6928 11:43:42.142391 # ok 1036 Set VL 5536
6929 11:43:42.142483 # ok 1037 # SKIP Disabled ZA for VL 5536
6930 11:43:42.142573 # ok 1038 # SKIP Get and set data for VL 5536
6931 11:43:42.142650 # ok 1039 Set VL 5552
6932 11:43:42.146077 # ok 1040 # SKIP Disabled ZA for VL 5552
6933 11:43:42.146441 # ok 1041 # SKIP Get and set data for VL 5552
6934 11:43:42.146565 # ok 1042 Set VL 5568
6935 11:43:42.146684 # ok 1043 # SKIP Disabled ZA for VL 5568
6936 11:43:42.146798 # ok 1044 # SKIP Get and set data for VL 5568
6937 11:43:42.146886 # ok 1045 Set VL 5584
6938 11:43:42.146976 # ok 1046 # SKIP Disabled ZA for VL 5584
6939 11:43:42.151811 # ok 1047 # SKIP Get and set data for VL 5584
6940 11:43:42.151978 # ok 1048 Set VL 5600
6941 11:43:42.152093 # ok 1049 # SKIP Disabled ZA for VL 5600
6942 11:43:42.152165 # ok 1050 # SKIP Get and set data for VL 5600
6943 11:43:42.152238 # ok 1051 Set VL 5616
6944 11:43:42.152310 # ok 1052 # SKIP Disabled ZA for VL 5616
6945 11:43:42.153356 # ok 1053 # SKIP Get and set data for VL 5616
6946 11:43:42.153458 # ok 1054 Set VL 5632
6947 11:43:42.153536 # ok 1055 # SKIP Disabled ZA for VL 5632
6948 11:43:42.153623 # ok 1056 # SKIP Get and set data for VL 5632
6949 11:43:42.153709 # ok 1057 Set VL 5648
6950 11:43:42.153798 # ok 1058 # SKIP Disabled ZA for VL 5648
6951 11:43:42.153876 # ok 1059 # SKIP Get and set data for VL 5648
6952 11:43:42.153956 # ok 1060 Set VL 5664
6953 11:43:42.154047 # ok 1061 # SKIP Disabled ZA for VL 5664
6954 11:43:42.154147 # ok 1062 # SKIP Get and set data for VL 5664
6955 11:43:42.154230 # ok 1063 Set VL 5680
6956 11:43:42.154322 # ok 1064 # SKIP Disabled ZA for VL 5680
6957 11:43:42.154399 # ok 1065 # SKIP Get and set data for VL 5680
6958 11:43:42.154489 # ok 1066 Set VL 5696
6959 11:43:42.154567 # ok 1067 # SKIP Disabled ZA for VL 5696
6960 11:43:42.154646 # ok 1068 # SKIP Get and set data for VL 5696
6961 11:43:42.157102 # ok 1069 Set VL 5712
6962 11:43:42.157462 # ok 1070 # SKIP Disabled ZA for VL 5712
6963 11:43:42.157611 # ok 1071 # SKIP Get and set data for VL 5712
6964 11:43:42.157753 # ok 1072 Set VL 5728
6965 11:43:42.157907 # ok 1073 # SKIP Disabled ZA for VL 5728
6966 11:43:42.158023 # ok 1074 # SKIP Get and set data for VL 5728
6967 11:43:42.158138 # ok 1075 Set VL 5744
6968 11:43:42.158235 # ok 1076 # SKIP Disabled ZA for VL 5744
6969 11:43:42.158352 # ok 1077 # SKIP Get and set data for VL 5744
6970 11:43:42.158438 # ok 1078 Set VL 5760
6971 11:43:42.158515 # ok 1079 # SKIP Disabled ZA for VL 5760
6972 11:43:42.158589 # ok 1080 # SKIP Get and set data for VL 5760
6973 11:43:42.158667 # ok 1081 Set VL 5776
6974 11:43:42.158731 # ok 1082 # SKIP Disabled ZA for VL 5776
6975 11:43:42.158805 # ok 1083 # SKIP Get and set data for VL 5776
6976 11:43:42.158866 # ok 1084 Set VL 5792
6977 11:43:42.158925 # ok 1085 # SKIP Disabled ZA for VL 5792
6978 11:43:42.159419 # ok 1086 # SKIP Get and set data for VL 5792
6979 11:43:42.159766 # ok 1087 Set VL 5808
6980 11:43:42.159846 # ok 1088 # SKIP Disabled ZA for VL 5808
6981 11:43:42.159922 # ok 1089 # SKIP Get and set data for VL 5808
6982 11:43:42.159997 # ok 1090 Set VL 5824
6983 11:43:42.160087 # ok 1091 # SKIP Disabled ZA for VL 5824
6984 11:43:42.160183 # ok 1092 # SKIP Get and set data for VL 5824
6985 11:43:42.160267 # ok 1093 Set VL 5840
6986 11:43:42.160340 # ok 1094 # SKIP Disabled ZA for VL 5840
6987 11:43:42.160432 # ok 1095 # SKIP Get and set data for VL 5840
6988 11:43:42.160509 # ok 1096 Set VL 5856
6989 11:43:42.160573 # ok 1097 # SKIP Disabled ZA for VL 5856
6990 11:43:42.160640 # ok 1098 # SKIP Get and set data for VL 5856
6991 11:43:42.160729 # ok 1099 Set VL 5872
6992 11:43:42.160810 # ok 1100 # SKIP Disabled ZA for VL 5872
6993 11:43:42.160880 # ok 1101 # SKIP Get and set data for VL 5872
6994 11:43:42.160968 # ok 1102 Set VL 5888
6995 11:43:42.161041 # ok 1103 # SKIP Disabled ZA for VL 5888
6996 11:43:42.161130 # ok 1104 # SKIP Get and set data for VL 5888
6997 11:43:42.161274 # ok 1105 Set VL 5904
6998 11:43:42.161420 # ok 1106 # SKIP Disabled ZA for VL 5904
6999 11:43:42.161599 # ok 1107 # SKIP Get and set data for VL 5904
7000 11:43:42.161765 # ok 1108 Set VL 5920
7001 11:43:42.161919 # ok 1109 # SKIP Disabled ZA for VL 5920
7002 11:43:42.162076 # ok 1110 # SKIP Get and set data for VL 5920
7003 11:43:42.162221 # ok 1111 Set VL 5936
7004 11:43:42.162404 # ok 1112 # SKIP Disabled ZA for VL 5936
7005 11:43:42.162535 # ok 1113 # SKIP Get and set data for VL 5936
7006 11:43:42.162732 # ok 1114 Set VL 5952
7007 11:43:42.162905 # ok 1115 # SKIP Disabled ZA for VL 5952
7008 11:43:42.163050 # ok 1116 # SKIP Get and set data for VL 5952
7009 11:43:42.163194 # ok 1117 Set VL 5968
7010 11:43:42.163333 # ok 1118 # SKIP Disabled ZA for VL 5968
7011 11:43:42.163473 # ok 1119 # SKIP Get and set data for VL 5968
7012 11:43:42.163612 # ok 1120 Set VL 5984
7013 11:43:42.163751 # ok 1121 # SKIP Disabled ZA for VL 5984
7014 11:43:42.163924 # ok 1122 # SKIP Get and set data for VL 5984
7015 11:43:42.164062 # ok 1123 Set VL 6000
7016 11:43:42.168344 # ok 1124 # SKIP Disabled ZA for VL 6000
7017 11:43:42.168783 # ok 1125 # SKIP Get and set data for VL 6000
7018 11:43:42.168965 # ok 1126 Set VL 6016
7019 11:43:42.169172 # ok 1127 # SKIP Disabled ZA for VL 6016
7020 11:43:42.169344 # ok 1128 # SKIP Get and set data for VL 6016
7021 11:43:42.169550 # ok 1129 Set VL 6032
7022 11:43:42.169816 # ok 1130 # SKIP Disabled ZA for VL 6032
7023 11:43:42.169991 # ok 1131 # SKIP Get and set data for VL 6032
7024 11:43:42.170148 # ok 1132 Set VL 6048
7025 11:43:42.170299 # ok 1133 # SKIP Disabled ZA for VL 6048
7026 11:43:42.170462 # ok 1134 # SKIP Get and set data for VL 6048
7027 11:43:42.170619 # ok 1135 Set VL 6064
7028 11:43:42.170757 # ok 1136 # SKIP Disabled ZA for VL 6064
7029 11:43:42.170869 # ok 1137 # SKIP Get and set data for VL 6064
7030 11:43:42.170979 # ok 1138 Set VL 6080
7031 11:43:42.171087 # ok 1139 # SKIP Disabled ZA for VL 6080
7032 11:43:42.171195 # ok 1140 # SKIP Get and set data for VL 6080
7033 11:43:42.171304 # ok 1141 Set VL 6096
7034 11:43:42.171439 # ok 1142 # SKIP Disabled ZA for VL 6096
7035 11:43:42.171554 # ok 1143 # SKIP Get and set data for VL 6096
7036 11:43:42.171665 # ok 1144 Set VL 6112
7037 11:43:42.171774 # ok 1145 # SKIP Disabled ZA for VL 6112
7038 11:43:42.171882 # ok 1146 # SKIP Get and set data for VL 6112
7039 11:43:42.171991 # ok 1147 Set VL 6128
7040 11:43:42.172101 # ok 1148 # SKIP Disabled ZA for VL 6128
7041 11:43:42.172215 # ok 1149 # SKIP Get and set data for VL 6128
7042 11:43:42.172325 # ok 1150 Set VL 6144
7043 11:43:42.175003 # ok 1151 # SKIP Disabled ZA for VL 6144
7044 11:43:42.175468 # ok 1152 # SKIP Get and set data for VL 6144
7045 11:43:42.175636 # ok 1153 Set VL 6160
7046 11:43:42.175783 # ok 1154 # SKIP Disabled ZA for VL 6160
7047 11:43:42.175946 # ok 1155 # SKIP Get and set data for VL 6160
7048 11:43:42.176105 # ok 1156 Set VL 6176
7049 11:43:42.176293 # ok 1157 # SKIP Disabled ZA for VL 6176
7050 11:43:42.176446 # ok 1158 # SKIP Get and set data for VL 6176
7051 11:43:42.176588 # ok 1159 Set VL 6192
7052 11:43:42.176748 # ok 1160 # SKIP Disabled ZA for VL 6192
7053 11:43:42.176917 # ok 1161 # SKIP Get and set data for VL 6192
7054 11:43:42.177074 # ok 1162 Set VL 6208
7055 11:43:42.177204 # ok 1163 # SKIP Disabled ZA for VL 6208
7056 11:43:42.177361 # ok 1164 # SKIP Get and set data for VL 6208
7057 11:43:42.177506 # ok 1165 Set VL 6224
7058 11:43:42.177686 # ok 1166 # SKIP Disabled ZA for VL 6224
7059 11:43:42.177883 # ok 1167 # SKIP Get and set data for VL 6224
7060 11:43:42.178051 # ok 1168 Set VL 6240
7061 11:43:42.178221 # ok 1169 # SKIP Disabled ZA for VL 6240
7062 11:43:42.178384 # ok 1170 # SKIP Get and set data for VL 6240
7063 11:43:42.178552 # ok 1171 Set VL 6256
7064 11:43:42.178705 # ok 1172 # SKIP Disabled ZA for VL 6256
7065 11:43:42.178824 # ok 1173 # SKIP Get and set data for VL 6256
7066 11:43:42.178936 # ok 1174 Set VL 6272
7067 11:43:42.179047 # ok 1175 # SKIP Disabled ZA for VL 6272
7068 11:43:42.179158 # ok 1176 # SKIP Get and set data for VL 6272
7069 11:43:42.179270 # ok 1177 Set VL 6288
7070 11:43:42.179381 # ok 1178 # SKIP Disabled ZA for VL 6288
7071 11:43:42.179492 # ok 1179 # SKIP Get and set data for VL 6288
7072 11:43:42.179604 # ok 1180 Set VL 6304
7073 11:43:42.179715 # ok 1181 # SKIP Disabled ZA for VL 6304
7074 11:43:42.179826 # ok 1182 # SKIP Get and set data for VL 6304
7075 11:43:42.179937 # ok 1183 Set VL 6320
7076 11:43:42.180047 # ok 1184 # SKIP Disabled ZA for VL 6320
7077 11:43:42.180188 # ok 1185 # SKIP Get and set data for VL 6320
7078 11:43:42.180308 # ok 1186 Set VL 6336
7079 11:43:42.180421 # ok 1187 # SKIP Disabled ZA for VL 6336
7080 11:43:42.180533 # ok 1188 # SKIP Get and set data for VL 6336
7081 11:43:42.180646 # ok 1189 Set VL 6352
7082 11:43:42.180757 # ok 1190 # SKIP Disabled ZA for VL 6352
7083 11:43:42.180870 # ok 1191 # SKIP Get and set data for VL 6352
7084 11:43:42.180981 # ok 1192 Set VL 6368
7085 11:43:42.181093 # ok 1193 # SKIP Disabled ZA for VL 6368
7086 11:43:42.181205 # ok 1194 # SKIP Get and set data for VL 6368
7087 11:43:42.183235 # ok 1195 Set VL 6384
7088 11:43:42.183701 # ok 1196 # SKIP Disabled ZA for VL 6384
7089 11:43:42.183962 # ok 1197 # SKIP Get and set data for VL 6384
7090 11:43:42.184165 # ok 1198 Set VL 6400
7091 11:43:42.184369 # ok 1199 # SKIP Disabled ZA for VL 6400
7092 11:43:42.184549 # ok 1200 # SKIP Get and set data for VL 6400
7093 11:43:42.184720 # ok 1201 Set VL 6416
7094 11:43:42.184887 # ok 1202 # SKIP Disabled ZA for VL 6416
7095 11:43:42.185051 # ok 1203 # SKIP Get and set data for VL 6416
7096 11:43:42.185206 # ok 1204 Set VL 6432
7097 11:43:42.185324 # ok 1205 # SKIP Disabled ZA for VL 6432
7098 11:43:42.185432 # ok 1206 # SKIP Get and set data for VL 6432
7099 11:43:42.185550 # ok 1207 Set VL 6448
7100 11:43:42.185679 # ok 1208 # SKIP Disabled ZA for VL 6448
7101 11:43:42.185801 # ok 1209 # SKIP Get and set data for VL 6448
7102 11:43:42.185917 # ok 1210 Set VL 6464
7103 11:43:42.186032 # ok 1211 # SKIP Disabled ZA for VL 6464
7104 11:43:42.186145 # ok 1212 # SKIP Get and set data for VL 6464
7105 11:43:42.186224 # ok 1213 Set VL 6480
7106 11:43:42.186321 # ok 1214 # SKIP Disabled ZA for VL 6480
7107 11:43:42.186405 # ok 1215 # SKIP Get and set data for VL 6480
7108 11:43:42.186486 # ok 1216 Set VL 6496
7109 11:43:42.186567 # ok 1217 # SKIP Disabled ZA for VL 6496
7110 11:43:42.186639 # ok 1218 # SKIP Get and set data for VL 6496
7111 11:43:42.186698 # ok 1219 Set VL 6512
7112 11:43:42.186755 # ok 1220 # SKIP Disabled ZA for VL 6512
7113 11:43:42.186812 # ok 1221 # SKIP Get and set data for VL 6512
7114 11:43:42.186868 # ok 1222 Set VL 6528
7115 11:43:42.186925 # ok 1223 # SKIP Disabled ZA for VL 6528
7116 11:43:42.186981 # ok 1224 # SKIP Get and set data for VL 6528
7117 11:43:42.187038 # ok 1225 Set VL 6544
7118 11:43:42.187095 # ok 1226 # SKIP Disabled ZA for VL 6544
7119 11:43:42.187151 # ok 1227 # SKIP Get and set data for VL 6544
7120 11:43:42.187208 # ok 1228 Set VL 6560
7121 11:43:42.187263 # ok 1229 # SKIP Disabled ZA for VL 6560
7122 11:43:42.187334 # ok 1230 # SKIP Get and set data for VL 6560
7123 11:43:42.187394 # ok 1231 Set VL 6576
7124 11:43:42.187451 # ok 1232 # SKIP Disabled ZA for VL 6576
7125 11:43:42.187507 # ok 1233 # SKIP Get and set data for VL 6576
7126 11:43:42.199556 # ok 1234 Set VL 6592
7127 11:43:42.199938 # ok 1235 # SKIP Disabled ZA for VL 6592
7128 11:43:42.200036 # ok 1236 # SKIP Get and set data for VL 6592
7129 11:43:42.200134 # ok 1237 Set VL 6608
7130 11:43:42.200285 # ok 1238 # SKIP Disabled ZA for VL 6608
7131 11:43:42.200460 # ok 1239 # SKIP Get and set data for VL 6608
7132 11:43:42.200662 # ok 1240 Set VL 6624
7133 11:43:42.200817 # ok 1241 # SKIP Disabled ZA for VL 6624
7134 11:43:42.200964 # ok 1242 # SKIP Get and set data for VL 6624
7135 11:43:42.201128 # ok 1243 Set VL 6640
7136 11:43:42.201290 # ok 1244 # SKIP Disabled ZA for VL 6640
7137 11:43:42.201441 # ok 1245 # SKIP Get and set data for VL 6640
7138 11:43:42.201588 # ok 1246 Set VL 6656
7139 11:43:42.201812 # ok 1247 # SKIP Disabled ZA for VL 6656
7140 11:43:42.201999 # ok 1248 # SKIP Get and set data for VL 6656
7141 11:43:42.202162 # ok 1249 Set VL 6672
7142 11:43:42.202311 # ok 1250 # SKIP Disabled ZA for VL 6672
7143 11:43:42.202466 # ok 1251 # SKIP Get and set data for VL 6672
7144 11:43:42.202621 # ok 1252 Set VL 6688
7145 11:43:42.202789 # ok 1253 # SKIP Disabled ZA for VL 6688
7146 11:43:42.202917 # ok 1254 # SKIP Get and set data for VL 6688
7147 11:43:42.203033 # ok 1255 Set VL 6704
7148 11:43:42.203144 # ok 1256 # SKIP Disabled ZA for VL 6704
7149 11:43:42.203257 # ok 1257 # SKIP Get and set data for VL 6704
7150 11:43:42.203369 # ok 1258 Set VL 6720
7151 11:43:42.203478 # ok 1259 # SKIP Disabled ZA for VL 6720
7152 11:43:42.203621 # ok 1260 # SKIP Get and set data for VL 6720
7153 11:43:42.203739 # ok 1261 Set VL 6736
7154 11:43:42.203851 # ok 1262 # SKIP Disabled ZA for VL 6736
7155 11:43:42.203963 # ok 1263 # SKIP Get and set data for VL 6736
7156 11:43:42.204074 # ok 1264 Set VL 6752
7157 11:43:42.204186 # ok 1265 # SKIP Disabled ZA for VL 6752
7158 11:43:42.204301 # ok 1266 # SKIP Get and set data for VL 6752
7159 11:43:42.204412 # ok 1267 Set VL 6768
7160 11:43:42.204524 # ok 1268 # SKIP Disabled ZA for VL 6768
7161 11:43:42.204635 # ok 1269 # SKIP Get and set data for VL 6768
7162 11:43:42.207296 # ok 1270 Set VL 6784
7163 11:43:42.207879 # ok 1271 # SKIP Disabled ZA for VL 6784
7164 11:43:42.208152 # ok 1272 # SKIP Get and set data for VL 6784
7165 11:43:42.208296 # ok 1273 Set VL 6800
7166 11:43:42.208414 # ok 1274 # SKIP Disabled ZA for VL 6800
7167 11:43:42.208557 # ok 1275 # SKIP Get and set data for VL 6800
7168 11:43:42.208676 # ok 1276 Set VL 6816
7169 11:43:42.208839 # ok 1277 # SKIP Disabled ZA for VL 6816
7170 11:43:42.209089 # ok 1278 # SKIP Get and set data for VL 6816
7171 11:43:42.209313 # ok 1279 Set VL 6832
7172 11:43:42.209536 # ok 1280 # SKIP Disabled ZA for VL 6832
7173 11:43:42.209895 # ok 1281 # SKIP Get and set data for VL 6832
7174 11:43:42.210119 # ok 1282 Set VL 6848
7175 11:43:42.210330 # ok 1283 # SKIP Disabled ZA for VL 6848
7176 11:43:42.210515 # ok 1284 # SKIP Get and set data for VL 6848
7177 11:43:42.210660 # ok 1285 Set VL 6864
7178 11:43:42.210814 # ok 1286 # SKIP Disabled ZA for VL 6864
7179 11:43:42.210958 # ok 1287 # SKIP Get and set data for VL 6864
7180 11:43:42.211096 # ok 1288 Set VL 6880
7181 11:43:42.211211 # ok 1289 # SKIP Disabled ZA for VL 6880
7182 11:43:42.211330 # ok 1290 # SKIP Get and set data for VL 6880
7183 11:43:42.211467 # ok 1291 Set VL 6896
7184 11:43:42.211586 # ok 1292 # SKIP Disabled ZA for VL 6896
7185 11:43:42.211699 # ok 1293 # SKIP Get and set data for VL 6896
7186 11:43:42.211811 # ok 1294 Set VL 6912
7187 11:43:42.211922 # ok 1295 # SKIP Disabled ZA for VL 6912
7188 11:43:42.212033 # ok 1296 # SKIP Get and set data for VL 6912
7189 11:43:42.212145 # ok 1297 Set VL 6928
7190 11:43:42.223897 # ok 1298 # SKIP Disabled ZA for VL 6928
7191 11:43:42.224464 # ok 1299 # SKIP Get and set data for VL 6928
7192 11:43:42.224664 # ok 1300 Set VL 6944
7193 11:43:42.224870 # ok 1301 # SKIP Disabled ZA for VL 6944
7194 11:43:42.225021 # ok 1302 # SKIP Get and set data for VL 6944
7195 11:43:42.225161 # ok 1303 Set VL 6960
7196 11:43:42.225287 # ok 1304 # SKIP Disabled ZA for VL 6960
7197 11:43:42.225441 # ok 1305 # SKIP Get and set data for VL 6960
7198 11:43:42.225581 # ok 1306 Set VL 6976
7199 11:43:42.225748 # ok 1307 # SKIP Disabled ZA for VL 6976
7200 11:43:42.225915 # ok 1308 # SKIP Get and set data for VL 6976
7201 11:43:42.226079 # ok 1309 Set VL 6992
7202 11:43:42.226247 # ok 1310 # SKIP Disabled ZA for VL 6992
7203 11:43:42.226411 # ok 1311 # SKIP Get and set data for VL 6992
7204 11:43:42.226571 # ok 1312 Set VL 7008
7205 11:43:42.226748 # ok 1313 # SKIP Disabled ZA for VL 7008
7206 11:43:42.226880 # ok 1314 # SKIP Get and set data for VL 7008
7207 11:43:42.226994 # ok 1315 Set VL 7024
7208 11:43:42.227108 # ok 1316 # SKIP Disabled ZA for VL 7024
7209 11:43:42.227220 # ok 1317 # SKIP Get and set data for VL 7024
7210 11:43:42.227333 # ok 1318 Set VL 7040
7211 11:43:42.227477 # ok 1319 # SKIP Disabled ZA for VL 7040
7212 11:43:42.227597 # ok 1320 # SKIP Get and set data for VL 7040
7213 11:43:42.227714 # ok 1321 Set VL 7056
7214 11:43:42.227827 # ok 1322 # SKIP Disabled ZA for VL 7056
7215 11:43:42.227941 # ok 1323 # SKIP Get and set data for VL 7056
7216 11:43:42.228053 # ok 1324 Set VL 7072
7217 11:43:42.228165 # ok 1325 # SKIP Disabled ZA for VL 7072
7218 11:43:42.228278 # ok 1326 # SKIP Get and set data for VL 7072
7219 11:43:42.228392 # ok 1327 Set VL 7088
7220 11:43:42.228505 # ok 1328 # SKIP Disabled ZA for VL 7088
7221 11:43:42.228624 # ok 1329 # SKIP Get and set data for VL 7088
7222 11:43:42.228749 # ok 1330 Set VL 7104
7223 11:43:42.228862 # ok 1331 # SKIP Disabled ZA for VL 7104
7224 11:43:42.231394 # ok 1332 # SKIP Get and set data for VL 7104
7225 11:43:42.231642 # ok 1333 Set VL 7120
7226 11:43:42.232071 # ok 1334 # SKIP Disabled ZA for VL 7120
7227 11:43:42.232291 # ok 1335 # SKIP Get and set data for VL 7120
7228 11:43:42.232476 # ok 1336 Set VL 7136
7229 11:43:42.232667 # ok 1337 # SKIP Disabled ZA for VL 7136
7230 11:43:42.232884 # ok 1338 # SKIP Get and set data for VL 7136
7231 11:43:42.233056 # ok 1339 Set VL 7152
7232 11:43:42.233213 # ok 1340 # SKIP Disabled ZA for VL 7152
7233 11:43:42.233600 # ok 1341 # SKIP Get and set data for VL 7152
7234 11:43:42.233789 # ok 1342 Set VL 7168
7235 11:43:42.233951 # ok 1343 # SKIP Disabled ZA for VL 7168
7236 11:43:42.234114 # ok 1344 # SKIP Get and set data for VL 7168
7237 11:43:42.234271 # ok 1345 Set VL 7184
7238 11:43:42.234416 # ok 1346 # SKIP Disabled ZA for VL 7184
7239 11:43:42.234559 # ok 1347 # SKIP Get and set data for VL 7184
7240 11:43:42.234690 # ok 1348 Set VL 7200
7241 11:43:42.234805 # ok 1349 # SKIP Disabled ZA for VL 7200
7242 11:43:42.234919 # ok 1350 # SKIP Get and set data for VL 7200
7243 11:43:42.235035 # ok 1351 Set VL 7216
7244 11:43:42.235148 # ok 1352 # SKIP Disabled ZA for VL 7216
7245 11:43:42.235261 # ok 1353 # SKIP Get and set data for VL 7216
7246 11:43:42.235374 # ok 1354 Set VL 7232
7247 11:43:42.235485 # ok 1355 # SKIP Disabled ZA for VL 7232
7248 11:43:42.235599 # ok 1356 # SKIP Get and set data for VL 7232
7249 11:43:42.235712 # ok 1357 Set VL 7248
7250 11:43:42.235826 # ok 1358 # SKIP Disabled ZA for VL 7248
7251 11:43:42.235940 # ok 1359 # SKIP Get and set data for VL 7248
7252 11:43:42.236087 # ok 1360 Set VL 7264
7253 11:43:42.236208 # ok 1361 # SKIP Disabled ZA for VL 7264
7254 11:43:42.236323 # ok 1362 # SKIP Get and set data for VL 7264
7255 11:43:42.236437 # ok 1363 Set VL 7280
7256 11:43:42.236551 # ok 1364 # SKIP Disabled ZA for VL 7280
7257 11:43:42.236665 # ok 1365 # SKIP Get and set data for VL 7280
7258 11:43:42.236779 # ok 1366 Set VL 7296
7259 11:43:42.236894 # ok 1367 # SKIP Disabled ZA for VL 7296
7260 11:43:42.237008 # ok 1368 # SKIP Get and set data for VL 7296
7261 11:43:42.237123 # ok 1369 Set VL 7312
7262 11:43:42.237235 # ok 1370 # SKIP Disabled ZA for VL 7312
7263 11:43:42.237349 # ok 1371 # SKIP Get and set data for VL 7312
7264 11:43:42.239478 # ok 1372 Set VL 7328
7265 11:43:42.239654 # ok 1373 # SKIP Disabled ZA for VL 7328
7266 11:43:42.239996 # ok 1374 # SKIP Get and set data for VL 7328
7267 11:43:42.240134 # ok 1375 Set VL 7344
7268 11:43:42.240262 # ok 1376 # SKIP Disabled ZA for VL 7344
7269 11:43:42.240389 # ok 1377 # SKIP Get and set data for VL 7344
7270 11:43:42.240518 # ok 1378 Set VL 7360
7271 11:43:42.240661 # ok 1379 # SKIP Disabled ZA for VL 7360
7272 11:43:42.240793 # ok 1380 # SKIP Get and set data for VL 7360
7273 11:43:42.240950 # ok 1381 Set VL 7376
7274 11:43:42.241099 # ok 1382 # SKIP Disabled ZA for VL 7376
7275 11:43:42.241258 # ok 1383 # SKIP Get and set data for VL 7376
7276 11:43:42.241422 # ok 1384 Set VL 7392
7277 11:43:42.241623 # ok 1385 # SKIP Disabled ZA for VL 7392
7278 11:43:42.241827 # ok 1386 # SKIP Get and set data for VL 7392
7279 11:43:42.242001 # ok 1387 Set VL 7408
7280 11:43:42.242169 # ok 1388 # SKIP Disabled ZA for VL 7408
7281 11:43:42.242330 # ok 1389 # SKIP Get and set data for VL 7408
7282 11:43:42.242482 # ok 1390 Set VL 7424
7283 11:43:42.242624 # ok 1391 # SKIP Disabled ZA for VL 7424
7284 11:43:42.242779 # ok 1392 # SKIP Get and set data for VL 7424
7285 11:43:42.242898 # ok 1393 Set VL 7440
7286 11:43:42.243009 # ok 1394 # SKIP Disabled ZA for VL 7440
7287 11:43:42.243118 # ok 1395 # SKIP Get and set data for VL 7440
7288 11:43:42.243228 # ok 1396 Set VL 7456
7289 11:43:42.243336 # ok 1397 # SKIP Disabled ZA for VL 7456
7290 11:43:42.243446 # ok 1398 # SKIP Get and set data for VL 7456
7291 11:43:42.243555 # ok 1399 Set VL 7472
7292 11:43:42.243663 # ok 1400 # SKIP Disabled ZA for VL 7472
7293 11:43:42.243772 # ok 1401 # SKIP Get and set data for VL 7472
7294 11:43:42.243880 # ok 1402 Set VL 7488
7295 11:43:42.243988 # ok 1403 # SKIP Disabled ZA for VL 7488
7296 11:43:42.244097 # ok 1404 # SKIP Get and set data for VL 7488
7297 11:43:42.244206 # ok 1405 Set VL 7504
7298 11:43:42.244314 # ok 1406 # SKIP Disabled ZA for VL 7504
7299 11:43:42.244423 # ok 1407 # SKIP Get and set data for VL 7504
7300 11:43:42.244531 # ok 1408 Set VL 7520
7301 11:43:42.244640 # ok 1409 # SKIP Disabled ZA for VL 7520
7302 11:43:42.260190 # ok 1410 # SKIP Get and set data for VL 7520
7303 11:43:42.260503 # ok 1411 Set VL 7536
7304 11:43:42.260886 # ok 1412 # SKIP Disabled ZA for VL 7536
7305 11:43:42.260992 # ok 1413 # SKIP Get and set data for VL 7536
7306 11:43:42.261080 # ok 1414 Set VL 7552
7307 11:43:42.261168 # ok 1415 # SKIP Disabled ZA for VL 7552
7308 11:43:42.261250 # ok 1416 # SKIP Get and set data for VL 7552
7309 11:43:42.261334 # ok 1417 Set VL 7568
7310 11:43:42.261420 # ok 1418 # SKIP Disabled ZA for VL 7568
7311 11:43:42.261502 # ok 1419 # SKIP Get and set data for VL 7568
7312 11:43:42.261584 # ok 1420 Set VL 7584
7313 11:43:42.261691 # ok 1421 # SKIP Disabled ZA for VL 7584
7314 11:43:42.261780 # ok 1422 # SKIP Get and set data for VL 7584
7315 11:43:42.261864 # ok 1423 Set VL 7600
7316 11:43:42.261953 # ok 1424 # SKIP Disabled ZA for VL 7600
7317 11:43:42.262035 # ok 1425 # SKIP Get and set data for VL 7600
7318 11:43:42.262118 # ok 1426 Set VL 7616
7319 11:43:42.262201 # ok 1427 # SKIP Disabled ZA for VL 7616
7320 11:43:42.262301 # ok 1428 # SKIP Get and set data for VL 7616
7321 11:43:42.262386 # ok 1429 Set VL 7632
7322 11:43:42.262467 # ok 1430 # SKIP Disabled ZA for VL 7632
7323 11:43:42.262552 # ok 1431 # SKIP Get and set data for VL 7632
7324 11:43:42.262634 # ok 1432 Set VL 7648
7325 11:43:42.262734 # ok 1433 # SKIP Disabled ZA for VL 7648
7326 11:43:42.262821 # ok 1434 # SKIP Get and set data for VL 7648
7327 11:43:42.262903 # ok 1435 Set VL 7664
7328 11:43:42.262983 # ok 1436 # SKIP Disabled ZA for VL 7664
7329 11:43:42.263081 # ok 1437 # SKIP Get and set data for VL 7664
7330 11:43:42.263169 # ok 1438 Set VL 7680
7331 11:43:42.263267 # ok 1439 # SKIP Disabled ZA for VL 7680
7332 11:43:42.263353 # ok 1440 # SKIP Get and set data for VL 7680
7333 11:43:42.263449 # ok 1441 Set VL 7696
7334 11:43:42.263533 # ok 1442 # SKIP Disabled ZA for VL 7696
7335 11:43:42.263630 # ok 1443 # SKIP Get and set data for VL 7696
7336 11:43:42.263715 # ok 1444 Set VL 7712
7337 11:43:42.263811 # ok 1445 # SKIP Disabled ZA for VL 7712
7338 11:43:42.263916 # ok 1446 # SKIP Get and set data for VL 7712
7339 11:43:42.264051 # ok 1447 Set VL 7728
7340 11:43:42.264543 # ok 1448 # SKIP Disabled ZA for VL 7728
7341 11:43:42.264641 # ok 1449 # SKIP Get and set data for VL 7728
7342 11:43:42.264725 # ok 1450 Set VL 7744
7343 11:43:42.264828 # ok 1451 # SKIP Disabled ZA for VL 7744
7344 11:43:42.264932 # ok 1452 # SKIP Get and set data for VL 7744
7345 11:43:42.265020 # ok 1453 Set VL 7760
7346 11:43:42.265120 # ok 1454 # SKIP Disabled ZA for VL 7760
7347 11:43:42.265397 # ok 1455 # SKIP Get and set data for VL 7760
7348 11:43:42.265485 # ok 1456 Set VL 7776
7349 11:43:42.265570 # ok 1457 # SKIP Disabled ZA for VL 7776
7350 11:43:42.265661 # ok 1458 # SKIP Get and set data for VL 7776
7351 11:43:42.265761 # ok 1459 Set VL 7792
7352 11:43:42.265848 # ok 1460 # SKIP Disabled ZA for VL 7792
7353 11:43:42.265949 # ok 1461 # SKIP Get and set data for VL 7792
7354 11:43:42.266037 # ok 1462 Set VL 7808
7355 11:43:42.266123 # ok 1463 # SKIP Disabled ZA for VL 7808
7356 11:43:42.266222 # ok 1464 # SKIP Get and set data for VL 7808
7357 11:43:42.266309 # ok 1465 Set VL 7824
7358 11:43:42.266409 # ok 1466 # SKIP Disabled ZA for VL 7824
7359 11:43:42.266510 # ok 1467 # SKIP Get and set data for VL 7824
7360 11:43:42.266593 # ok 1468 Set VL 7840
7361 11:43:42.266696 # ok 1469 # SKIP Disabled ZA for VL 7840
7362 11:43:42.267006 # ok 1470 # SKIP Get and set data for VL 7840
7363 11:43:42.267134 # ok 1471 Set VL 7856
7364 11:43:42.267241 # ok 1472 # SKIP Disabled ZA for VL 7856
7365 11:43:42.267329 # ok 1473 # SKIP Get and set data for VL 7856
7366 11:43:42.267426 # ok 1474 Set VL 7872
7367 11:43:42.267511 # ok 1475 # SKIP Disabled ZA for VL 7872
7368 11:43:42.267608 # ok 1476 # SKIP Get and set data for VL 7872
7369 11:43:42.267693 # ok 1477 Set VL 7888
7370 11:43:42.267790 # ok 1478 # SKIP Disabled ZA for VL 7888
7371 11:43:42.267890 # ok 1479 # SKIP Get and set data for VL 7888
7372 11:43:42.267991 # ok 1480 Set VL 7904
7373 11:43:42.268088 # ok 1481 # SKIP Disabled ZA for VL 7904
7374 11:43:42.268186 # ok 1482 # SKIP Get and set data for VL 7904
7375 11:43:42.268283 # ok 1483 Set VL 7920
7376 11:43:42.268381 # ok 1484 # SKIP Disabled ZA for VL 7920
7377 11:43:42.268727 # ok 1485 # SKIP Get and set data for VL 7920
7378 11:43:42.268831 # ok 1486 Set VL 7936
7379 11:43:42.268917 # ok 1487 # SKIP Disabled ZA for VL 7936
7380 11:43:42.269017 # ok 1488 # SKIP Get and set data for VL 7936
7381 11:43:42.269102 # ok 1489 Set VL 7952
7382 11:43:42.269201 # ok 1490 # SKIP Disabled ZA for VL 7952
7383 11:43:42.269286 # ok 1491 # SKIP Get and set data for VL 7952
7384 11:43:42.269384 # ok 1492 Set VL 7968
7385 11:43:42.269469 # ok 1493 # SKIP Disabled ZA for VL 7968
7386 11:43:42.269567 # ok 1494 # SKIP Get and set data for VL 7968
7387 11:43:42.269661 # ok 1495 Set VL 7984
7388 11:43:42.269760 # ok 1496 # SKIP Disabled ZA for VL 7984
7389 11:43:42.269859 # ok 1497 # SKIP Get and set data for VL 7984
7390 11:43:42.269957 # ok 1498 Set VL 8000
7391 11:43:42.270065 # ok 1499 # SKIP Disabled ZA for VL 8000
7392 11:43:42.270165 # ok 1500 # SKIP Get and set data for VL 8000
7393 11:43:42.270267 # ok 1501 Set VL 8016
7394 11:43:42.270368 # ok 1502 # SKIP Disabled ZA for VL 8016
7395 11:43:42.271530 # ok 1503 # SKIP Get and set data for VL 8016
7396 11:43:42.271634 # ok 1504 Set VL 8032
7397 11:43:42.271720 # ok 1505 # SKIP Disabled ZA for VL 8032
7398 11:43:42.271821 # ok 1506 # SKIP Get and set data for VL 8032
7399 11:43:42.271908 # ok 1507 Set VL 8048
7400 11:43:42.271994 # ok 1508 # SKIP Disabled ZA for VL 8048
7401 11:43:42.272093 # ok 1509 # SKIP Get and set data for VL 8048
7402 11:43:42.272180 # ok 1510 Set VL 8064
7403 11:43:42.272282 # ok 1511 # SKIP Disabled ZA for VL 8064
7404 11:43:42.272368 # ok 1512 # SKIP Get and set data for VL 8064
7405 11:43:42.272466 # ok 1513 Set VL 8080
7406 11:43:42.272565 # ok 1514 # SKIP Disabled ZA for VL 8080
7407 11:43:42.272666 # ok 1515 # SKIP Get and set data for VL 8080
7408 11:43:42.272750 # ok 1516 Set VL 8096
7409 11:43:42.272847 # ok 1517 # SKIP Disabled ZA for VL 8096
7410 11:43:42.272947 # ok 1518 # SKIP Get and set data for VL 8096
7411 11:43:42.273047 # ok 1519 Set VL 8112
7412 11:43:42.273146 # ok 1520 # SKIP Disabled ZA for VL 8112
7413 11:43:42.273468 # ok 1521 # SKIP Get and set data for VL 8112
7414 11:43:42.280887 # ok 1522 Set VL 8128
7415 11:43:42.281426 # ok 1523 # SKIP Disabled ZA for VL 8128
7416 11:43:42.281631 # ok 1524 # SKIP Get and set data for VL 8128
7417 11:43:42.281813 # ok 1525 Set VL 8144
7418 11:43:42.281976 # ok 1526 # SKIP Disabled ZA for VL 8144
7419 11:43:42.282135 # ok 1527 # SKIP Get and set data for VL 8144
7420 11:43:42.282294 # ok 1528 Set VL 8160
7421 11:43:42.282422 # ok 1529 # SKIP Disabled ZA for VL 8160
7422 11:43:42.282577 # ok 1530 # SKIP Get and set data for VL 8160
7423 11:43:42.282734 # ok 1531 Set VL 8176
7424 11:43:42.282865 # ok 1532 # SKIP Disabled ZA for VL 8176
7425 11:43:42.282982 # ok 1533 # SKIP Get and set data for VL 8176
7426 11:43:42.283095 # ok 1534 Set VL 8192
7427 11:43:42.283206 # ok 1535 # SKIP Disabled ZA for VL 8192
7428 11:43:42.283317 # ok 1536 # SKIP Get and set data for VL 8192
7429 11:43:42.283430 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7430 11:43:42.283542 ok 34 selftests: arm64: za-ptrace
7431 11:43:42.283656 # selftests: arm64: check_buffer_fill
7432 11:43:42.535739 # 1..20
7433 11:43:42.536061 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7434 11:43:42.536517 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7435 11:43:42.536727 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7436 11:43:42.536893 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7437 11:43:42.537063 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7438 11:43:42.537255 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7439 11:43:42.537455 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7440 11:43:42.537634 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7441 11:43:42.537799 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7442 11:43:42.537981 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 11:43:42.538146 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7444 11:43:42.538288 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7445 11:43:42.538451 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7446 11:43:42.538645 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7447 11:43:42.538795 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7448 11:43:42.538961 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7449 11:43:42.539129 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7450 11:43:42.542373 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7451 11:43:42.542815 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7452 11:43:42.542986 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7453 11:43:42.552009 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7454 11:43:42.553851 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7455 11:43:42.632153 # selftests: arm64: check_child_memory
7456 11:43:42.985253 # 1..12
7457 11:43:42.985717 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7458 11:43:42.985854 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7459 11:43:42.986055 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7460 11:43:42.986218 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7461 11:43:42.986394 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7462 11:43:42.986531 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7463 11:43:42.986736 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7464 11:43:42.986929 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7465 11:43:42.987154 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7466 11:43:43.000499 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7467 11:43:43.000834 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7468 11:43:43.001009 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7469 11:43:43.001185 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7470 11:43:43.004055 not ok 36 selftests: arm64: check_child_memory # exit=1
7471 11:43:43.080239 # selftests: arm64: check_gcr_el1_cswitch
7472 11:44:28.876182 <47>[ 95.981997] systemd-journald[105]: Data hash table of /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal has a fill level at 75.0 (3329 of 4437 items, 2555904 file size, 767 bytes per hash table item), suggesting rotation.
7473 11:44:28.877944 <47>[ 95.985636] systemd-journald[105]: /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5/system.journal: Journal header limits reached or header out-of-date, rotating.
7474 11:44:28.878139 <47>[ 95.986046] systemd-journald[105]: Rotating...
7475 11:44:28.923002 <47>[ 96.030697] systemd-journald[105]: Reserving 333 entries in field hash table.
7476 11:44:28.970740 <47>[ 96.078615] systemd-journald[105]: Reserving 4437 entries in data hash table.
7477 11:44:28.983318 <47>[ 96.091080] systemd-journald[105]: Vacuuming...
7478 11:44:29.002853 <47>[ 96.110593] systemd-journald[105]: Vacuuming done, freed 0B of archived journals from /run/log/journal/aa3c2edede8c479b99ca75a0766ab7d5.
7479 11:44:30.552656 <47>[ 97.660560] systemd-journald[105]: Sent WATCHDOG=1 notification.
7480 11:44:31.104926 # 1..1
7481 11:44:31.105307 # 1..1
7482 11:44:31.105497 # 1..1
7483 11:44:31.105684 # 1..1
7484 11:44:31.105816 # 1..1
7485 11:44:31.105936 # 1..1
7486 11:44:31.106053 # 1..1
7487 11:44:31.106402 # 1..1
7488 11:44:31.106560 # 1..1
7489 11:44:31.106759 # 1..1
7490 11:44:31.106938 # 1..1
7491 11:44:31.107106 # 1..1
7492 11:44:31.107270 # 1..1
7493 11:44:31.107443 # 1..1
7494 11:44:31.107623 # 1..1
7495 11:44:31.107802 # 1..1
7496 11:44:31.107986 # 1..1
7497 11:44:31.108164 # 1..1
7498 11:44:31.108339 # 1..1
7499 11:44:31.108511 # 1..1
7500 11:44:31.108687 # 1..1
7501 11:44:31.108861 # 1..1
7502 11:44:31.109040 # 1..1
7503 11:44:31.109211 # 1..1
7504 11:44:31.109369 # 1..1
7505 11:44:31.109519 # 1..1
7506 11:44:31.109687 # 1..1
7507 11:44:31.109838 # 1..1
7508 11:44:31.109989 # 1..1
7509 11:44:31.110139 # 1..1
7510 11:44:31.110285 # 1..1
7511 11:44:31.110432 # 1..1
7512 11:44:31.110579 # 1..1
7513 11:44:31.110727 # 1..1
7514 11:44:31.110875 # 1..1
7515 11:44:31.111026 # 1..1
7516 11:44:31.111173 # 1..1
7517 11:44:31.111321 # 1..1
7518 11:44:31.111469 # 1..1
7519 11:44:31.111619 # 1..1
7520 11:44:31.111768 # 1..1
7521 11:44:31.111916 # 1..1
7522 11:44:31.112067 # 1..1
7523 11:44:31.112217 # 1..1
7524 11:44:31.112364 # 1..1
7525 11:44:31.112517 # 1..1
7526 11:44:31.112666 # 1..1
7527 11:44:31.112816 # 1..1
7528 11:44:31.112939 # 1..1
7529 11:44:31.113057 # 1..1
7530 11:44:31.113175 # 1..1
7531 11:44:31.113291 # 1..1
7532 11:44:31.113409 # 1..1
7533 11:44:31.113526 # 1..1
7534 11:44:31.113662 # 1..1
7535 11:44:31.113821 # 1..1
7536 11:44:31.113982 # 1..1
7537 11:44:31.114155 # 1..1
7538 11:44:31.114330 # 1..1
7539 11:44:31.114499 # 1..1
7540 11:44:31.114663 # 1..1
7541 11:44:31.114813 # 1..1
7542 11:44:31.114963 # 1..1
7543 11:44:31.115108 # 1..1
7544 11:44:31.115254 # 1..1
7545 11:44:31.115399 # 1..1
7546 11:44:31.115608 # 1..1
7547 11:44:31.115764 # 1..1
7548 11:44:31.115912 # 1..1
7549 11:44:31.116059 # 1..1
7550 11:44:31.116205 # 1..1
7551 11:44:31.116349 # 1..1
7552 11:44:31.116494 # 1..1
7553 11:44:31.116639 # 1..1
7554 11:44:31.116784 # 1..1
7555 11:44:31.116928 # 1..1
7556 11:44:31.117073 # 1..1
7557 11:44:31.117216 # 1..1
7558 11:44:31.117362 # 1..1
7559 11:44:31.117511 # 1..1
7560 11:44:31.117635 # 1..1
7561 11:44:31.117774 # 1..1
7562 11:44:31.117891 # 1..1
7563 11:44:31.118004 # 1..1
7564 11:44:31.118120 # 1..1
7565 11:44:31.118243 # 1..1
7566 11:44:31.118397 # 1..1
7567 11:44:31.118558 # 1..1
7568 11:44:31.118726 # 1..1
7569 11:44:31.118889 # 1..1
7570 11:44:31.119040 # 1..1
7571 11:44:31.119185 # 1..1
7572 11:44:31.119330 # 1..1
7573 11:44:31.119475 # 1..1
7574 11:44:31.119619 # 1..1
7575 11:44:31.119765 # 1..1
7576 11:44:31.119910 # 1..1
7577 11:44:31.120057 # 1..1
7578 11:44:31.120203 # 1..1
7579 11:44:31.120349 # 1..1
7580 11:44:31.120493 # 1..1
7581 11:44:31.120639 # 1..1
7582 11:44:31.120784 # 1..1
7583 11:44:31.120929 # 1..1
7584 11:44:31.121073 # 1..1
7585 11:44:31.121219 # 1..1
7586 11:44:31.121364 # 1..1
7587 11:44:31.121509 # 1..1
7588 11:44:31.121670 # 1..1
7589 11:44:31.121797 # 1..1
7590 11:44:31.121914 # 1..1
7591 11:44:31.122029 # 1..1
7592 11:44:31.149514 # 1..1
7593 11:44:31.149805 # 1..1
7594 11:44:31.149997 # 1..1
7595 11:44:31.150175 # 1..1
7596 11:44:31.150348 # 1..1
7597 11:44:31.150798 # 1..1
7598 11:44:31.150910 # 1..1
7599 11:44:31.151001 # 1..1
7600 11:44:31.151089 # 1..1
7601 11:44:31.151175 # 1..1
7602 11:44:31.151259 # 1..1
7603 11:44:31.151341 # 1..1
7604 11:44:31.151423 # 1..1
7605 11:44:31.151506 # 1..1
7606 11:44:31.151587 # 1..1
7607 11:44:31.151666 # 1..1
7608 11:44:31.151747 # 1..1
7609 11:44:31.151831 # 1..1
7610 11:44:31.151914 # 1..1
7611 11:44:31.151998 # 1..1
7612 11:44:31.152079 # 1..1
7613 11:44:31.152162 # 1..1
7614 11:44:31.152245 # 1..1
7615 11:44:31.152329 # 1..1
7616 11:44:31.152413 # 1..1
7617 11:44:31.152498 # 1..1
7618 11:44:31.152581 # 1..1
7619 11:44:31.152664 # 1..1
7620 11:44:31.152746 # 1..1
7621 11:44:31.152828 # 1..1
7622 11:44:31.152910 # 1..1
7623 11:44:31.152988 # 1..1
7624 11:44:31.153072 # 1..1
7625 11:44:31.153158 # 1..1
7626 11:44:31.153243 # 1..1
7627 11:44:31.153327 # 1..1
7628 11:44:31.153412 # 1..1
7629 11:44:31.153495 # 1..1
7630 11:44:31.153574 # 1..1
7631 11:44:31.153665 # 1..1
7632 11:44:31.153748 # 1..1
7633 11:44:31.153833 # 1..1
7634 11:44:31.153917 # 1..1
7635 11:44:31.154001 # 1..1
7636 11:44:31.154086 # 1..1
7637 11:44:31.154171 # 1..1
7638 11:44:31.154255 # 1..1
7639 11:44:31.154339 # 1..1
7640 11:44:31.154424 # 1..1
7641 11:44:31.154508 # 1..1
7642 11:44:31.154591 # 1..1
7643 11:44:31.154675 # 1..1
7644 11:44:31.154759 # 1..1
7645 11:44:31.154843 # 1..1
7646 11:44:31.154927 # 1..1
7647 11:44:31.155014 # 1..1
7648 11:44:31.155137 # 1..1
7649 11:44:31.155224 # 1..1
7650 11:44:31.155309 # 1..1
7651 11:44:31.155393 # 1..1
7652 11:44:31.155476 # 1..1
7653 11:44:31.155559 # 1..1
7654 11:44:31.155640 # 1..1
7655 11:44:31.155719 # 1..1
7656 11:44:31.155799 # 1..1
7657 11:44:31.155880 # 1..1
7658 11:44:31.155960 # 1..1
7659 11:44:31.156042 # 1..1
7660 11:44:31.156127 # 1..1
7661 11:44:31.156209 # 1..1
7662 11:44:31.156290 # 1..1
7663 11:44:31.156375 # 1..1
7664 11:44:31.156461 # 1..1
7665 11:44:31.156543 # 1..1
7666 11:44:31.156624 # 1..1
7667 11:44:31.156702 # 1..1
7668 11:44:31.156782 # 1..1
7669 11:44:31.156860 # 1..1
7670 11:44:31.179156 # 1..1
7671 11:44:31.179404 # 1..1
7672 11:44:31.179494 # 1..1
7673 11:44:31.179581 # 1..1
7674 11:44:31.179663 # 1..1
7675 11:44:31.179746 # 1..1
7676 11:44:31.180045 # 1..1
7677 11:44:31.180188 # 1..1
7678 11:44:31.180326 # 1..1
7679 11:44:31.180429 # 1..1
7680 11:44:31.180513 # 1..1
7681 11:44:31.180597 # 1..1
7682 11:44:31.180676 # 1..1
7683 11:44:31.180757 # 1..1
7684 11:44:31.180838 # 1..1
7685 11:44:31.180940 # 1..1
7686 11:44:31.181027 # 1..1
7687 11:44:31.181110 # 1..1
7688 11:44:31.181191 # 1..1
7689 11:44:31.181273 # 1..1
7690 11:44:31.181358 # 1..1
7691 11:44:31.181440 # 1..1
7692 11:44:31.181522 # 1..1
7693 11:44:31.181602 # 1..1
7694 11:44:31.181692 # 1..1
7695 11:44:31.181774 # 1..1
7696 11:44:31.181856 # 1..1
7697 11:44:31.181937 # 1..1
7698 11:44:31.182018 # 1..1
7699 11:44:31.182101 # 1..1
7700 11:44:31.182182 # 1..1
7701 11:44:31.182263 # 1..1
7702 11:44:31.182341 # 1..1
7703 11:44:31.182421 # 1..1
7704 11:44:31.182502 # 1..1
7705 11:44:31.182582 # 1..1
7706 11:44:31.182664 # 1..1
7707 11:44:31.182746 # 1..1
7708 11:44:31.182827 # 1..1
7709 11:44:31.182907 # 1..1
7710 11:44:31.182988 # 1..1
7711 11:44:31.183070 # 1..1
7712 11:44:31.183152 # 1..1
7713 11:44:31.183234 # 1..1
7714 11:44:31.183315 # 1..1
7715 11:44:31.183422 # 1..1
7716 11:44:31.183507 # 1..1
7717 11:44:31.183594 # 1..1
7718 11:44:31.183675 # 1..1
7719 11:44:31.183757 # 1..1
7720 11:44:31.183841 # 1..1
7721 11:44:31.183923 # 1..1
7722 11:44:31.184003 # 1..1
7723 11:44:31.184083 # 1..1
7724 11:44:31.184164 # 1..1
7725 11:44:31.184243 # 1..1
7726 11:44:31.184326 # 1..1
7727 11:44:31.184409 # 1..1
7728 11:44:31.184493 # 1..1
7729 11:44:31.184576 # 1..1
7730 11:44:31.184659 # 1..1
7731 11:44:31.184742 # 1..1
7732 11:44:31.184826 # 1..1
7733 11:44:31.184909 # 1..1
7734 11:44:31.184993 # 1..1
7735 11:44:31.185077 # 1..1
7736 11:44:31.185164 # 1..1
7737 11:44:31.185247 # 1..1
7738 11:44:31.185331 # 1..1
7739 11:44:31.185414 # 1..1
7740 11:44:31.185496 # 1..1
7741 11:44:31.185579 # 1..1
7742 11:44:31.186586 # 1..1
7743 11:44:31.186693 # 1..1
7744 11:44:31.186780 # 1..1
7745 11:44:31.186866 # 1..1
7746 11:44:31.186951 # 1..1
7747 11:44:31.187040 # 1..1
7748 11:44:31.187125 # 1..1
7749 11:44:31.187211 # 1..1
7750 11:44:31.187296 # 1..1
7751 11:44:31.187381 # 1..1
7752 11:44:31.187467 # 1..1
7753 11:44:31.187549 # 1..1
7754 11:44:31.187632 # 1..1
7755 11:44:31.187713 # 1..1
7756 11:44:31.187793 # 1..1
7757 11:44:31.187874 # 1..1
7758 11:44:31.187956 # 1..1
7759 11:44:31.188036 # 1..1
7760 11:44:31.188117 # 1..1
7761 11:44:31.188198 # 1..1
7762 11:44:31.188276 # 1..1
7763 11:44:31.188364 # 1..1
7764 11:44:31.188448 # 1..1
7765 11:44:31.188531 # 1..1
7766 11:44:31.188611 # 1..1
7767 11:44:31.188689 # 1..1
7768 11:44:31.188768 # 1..1
7769 11:44:31.188847 # 1..1
7770 11:44:31.188925 # 1..1
7771 11:44:31.189003 # 1..1
7772 11:44:31.189084 # 1..1
7773 11:44:31.189165 # 1..1
7774 11:44:31.189245 # 1..1
7775 11:44:31.189326 # 1..1
7776 11:44:31.189405 # 1..1
7777 11:44:31.189486 # 1..1
7778 11:44:31.189565 # 1..1
7779 11:44:31.189643 # 1..1
7780 11:44:31.190030 # 1..1
7781 11:44:31.190122 # 1..1
7782 11:44:31.190207 # 1..1
7783 11:44:31.215134 # 1..1
7784 11:44:31.215395 # 1..1
7785 11:44:31.215485 # 1..1
7786 11:44:31.215571 # 1..1
7787 11:44:31.215654 # 1..1
7788 11:44:31.215948 # 1..1
7789 11:44:31.216045 # 1..1
7790 11:44:31.216135 # 1..1
7791 11:44:31.216221 # 1..1
7792 11:44:31.216305 # 1..1
7793 11:44:31.216387 # 1..1
7794 11:44:31.216468 # 1..1
7795 11:44:31.216550 # 1..1
7796 11:44:31.216632 # 1..1
7797 11:44:31.216714 # 1..1
7798 11:44:31.230536 # 1..1
7799 11:44:31.230847 # 1..1
7800 11:44:31.231065 # 1..1
7801 11:44:31.231155 # 1..1
7802 11:44:31.231243 # 1..1
7803 11:44:31.231324 # 1..1
7804 11:44:31.231626 # 1..1
7805 11:44:31.231728 # 1..1
7806 11:44:31.231813 # 1..1
7807 11:44:31.231896 # 1..1
7808 11:44:31.231982 # 1..1
7809 11:44:31.232069 # 1..1
7810 11:44:31.232152 # 1..1
7811 11:44:31.232235 # 1..1
7812 11:44:31.232316 # 1..1
7813 11:44:31.232397 # 1..1
7814 11:44:31.232475 # 1..1
7815 11:44:31.232556 # 1..1
7816 11:44:31.232636 # 1..1
7817 11:44:31.232721 # 1..1
7818 11:44:31.232804 # 1..1
7819 11:44:31.232888 # 1..1
7820 11:44:31.232971 # 1..1
7821 11:44:31.233056 # 1..1
7822 11:44:31.233141 # 1..1
7823 11:44:31.233224 # 1..1
7824 11:44:31.233306 # 1..1
7825 11:44:31.233387 # 1..1
7826 11:44:31.233468 # 1..1
7827 11:44:31.233568 # 1..1
7828 11:44:31.233659 # 1..1
7829 11:44:31.233742 # 1..1
7830 11:44:31.233824 # 1..1
7831 11:44:31.233903 # 1..1
7832 11:44:31.233985 # 1..1
7833 11:44:31.234064 # 1..1
7834 11:44:31.234147 # 1..1
7835 11:44:31.234226 # 1..1
7836 11:44:31.234306 # 1..1
7837 11:44:31.234386 # 1..1
7838 11:44:31.234466 # 1..1
7839 11:44:31.234545 # 1..1
7840 11:44:31.234624 # 1..1
7841 11:44:31.234706 # 1..1
7842 11:44:31.234785 # 1..1
7843 11:44:31.234864 # 1..1
7844 11:44:31.234943 # 1..1
7845 11:44:31.235023 # 1..1
7846 11:44:31.235104 # 1..1
7847 11:44:31.235183 # 1..1
7848 11:44:31.235262 # 1..1
7849 11:44:31.235342 # 1..1
7850 11:44:31.235422 # 1..1
7851 11:44:31.235501 # 1..1
7852 11:44:31.235580 # 1..1
7853 11:44:31.235661 # 1..1
7854 11:44:31.235742 # 1..1
7855 11:44:31.235825 # 1..1
7856 11:44:31.235905 # 1..1
7857 11:44:31.235986 # 1..1
7858 11:44:31.236068 # 1..1
7859 11:44:31.236149 # 1..1
7860 11:44:31.236229 # 1..1
7861 11:44:31.236333 # 1..1
7862 11:44:31.236417 # 1..1
7863 11:44:31.236498 # 1..1
7864 11:44:31.236579 # 1..1
7865 11:44:31.236659 # 1..1
7866 11:44:31.236740 # 1..1
7867 11:44:31.236820 # 1..1
7868 11:44:31.236902 # 1..1
7869 11:44:31.236983 # 1..1
7870 11:44:31.237065 # 1..1
7871 11:44:31.237150 # 1..1
7872 11:44:31.237241 # 1..1
7873 11:44:31.237324 # 1..1
7874 11:44:31.237405 # 1..1
7875 11:44:31.237486 # 1..1
7876 11:44:31.237566 # 1..1
7877 11:44:31.238534 # 1..1
7878 11:44:31.238649 # 1..1
7879 11:44:31.238735 # 1..1
7880 11:44:31.238822 # 1..1
7881 11:44:31.238906 # 1..1
7882 11:44:31.238991 # 1..1
7883 11:44:31.239077 # 1..1
7884 11:44:31.239161 # 1..1
7885 11:44:31.239246 # 1..1
7886 11:44:31.239331 # 1..1
7887 11:44:31.239416 # 1..1
7888 11:44:31.239501 # 1..1
7889 11:44:31.239585 # 1..1
7890 11:44:31.239667 # 1..1
7891 11:44:31.239747 # 1..1
7892 11:44:31.239829 # 1..1
7893 11:44:31.239913 # 1..1
7894 11:44:31.239993 # 1..1
7895 11:44:31.240079 # 1..1
7896 11:44:31.240165 # 1..1
7897 11:44:31.240250 # 1..1
7898 11:44:31.240335 # 1..1
7899 11:44:31.240418 # 1..1
7900 11:44:31.240502 # 1..1
7901 11:44:31.240587 # 1..1
7902 11:44:31.240673 # 1..1
7903 11:44:31.240758 # 1..1
7904 11:44:31.240842 # 1..1
7905 11:44:31.240927 # 1..1
7906 11:44:31.241013 # 1..1
7907 11:44:31.241098 # 1..1
7908 11:44:31.241182 # 1..1
7909 11:44:31.241267 # 1..1
7910 11:44:31.241353 # 1..1
7911 11:44:31.241438 # 1..1
7912 11:44:31.241524 # 1..1
7913 11:44:31.241609 # 1..1
7914 11:44:31.241702 # 1..1
7915 11:44:31.241787 # 1..1
7916 11:44:31.241871 # 1..1
7917 11:44:31.252297 # 1..1
7918 11:44:31.252653 # 1..1
7919 11:44:31.252819 # 1..1
7920 11:44:31.252987 # 1..1
7921 11:44:31.253423 # 1..1
7922 11:44:31.253900 # 1..1
7923 11:44:31.254107 # 1..1
7924 11:44:31.254296 # 1..1
7925 11:44:31.254467 # 1..1
7926 11:44:31.254623 # 1..1
7927 11:44:31.254783 # 1..1
7928 11:44:31.254949 # 1..1
7929 11:44:31.255121 # 1..1
7930 11:44:31.255273 # 1..1
7931 11:44:31.255396 # 1..1
7932 11:44:31.255511 # 1..1
7933 11:44:31.255629 # 1..1
7934 11:44:31.255811 # 1..1
7935 11:44:31.255947 # 1..1
7936 11:44:31.256063 # 1..1
7937 11:44:31.256180 # 1..1
7938 11:44:31.256294 # 1..1
7939 11:44:31.256405 # 1..1
7940 11:44:31.256518 # 1..1
7941 11:44:31.256631 # 1..1
7942 11:44:31.256744 # 1..1
7943 11:44:31.256857 # 1..1
7944 11:44:31.256969 # 1..1
7945 11:44:31.257080 # 1..1
7946 11:44:31.257194 # 1..1
7947 11:44:31.257307 # 1..1
7948 11:44:31.257419 # 1..1
7949 11:44:31.257533 # 1..1
7950 11:44:31.257667 # 1..1
7951 11:44:31.257868 # 1..1
7952 11:44:31.258056 # 1..1
7953 11:44:31.258238 # 1..1
7954 11:44:31.258420 # 1..1
7955 11:44:31.258601 # 1..1
7956 11:44:31.258783 # 1..1
7957 11:44:31.258939 # 1..1
7958 11:44:31.259081 # 1..1
7959 11:44:31.259225 # 1..1
7960 11:44:31.259365 # 1..1
7961 11:44:31.259507 # 1..1
7962 11:44:31.259647 # 1..1
7963 11:44:31.259787 # 1..1
7964 11:44:31.259927 # 1..1
7965 11:44:31.260069 # 1..1
7966 11:44:31.260210 # 1..1
7967 11:44:31.260350 # 1..1
7968 11:44:31.260490 # 1..1
7969 11:44:31.260633 # 1..1
7970 11:44:31.260832 # 1..1
7971 11:44:31.260971 # 1..1
7972 11:44:31.261172 # 1..1
7973 11:44:31.261337 # 1..1
7974 11:44:31.261483 # 1..1
7975 11:44:31.261611 # 1..1
7976 11:44:31.261809 # 1..1
7977 11:44:31.261974 # 1..1
7978 11:44:31.262147 # 1..1
7979 11:44:31.262295 # 1..1
7980 11:44:31.262437 # 1..1
7981 11:44:31.262579 # 1..1
7982 11:44:31.262720 # 1..1
7983 11:44:31.262861 # 1..1
7984 11:44:31.263000 # 1..1
7985 11:44:31.263141 # 1..1
7986 11:44:31.263284 # 1..1
7987 11:44:31.263425 # 1..1
7988 11:44:31.263567 # 1..1
7989 11:44:31.263706 # 1..1
7990 11:44:31.263848 # 1..1
7991 11:44:31.263988 # 1..1
7992 11:44:31.264128 # 1..1
7993 11:44:31.264271 # 1..1
7994 11:44:31.264470 # 1..1
7995 11:44:31.264624 # 1..1
7996 11:44:31.264742 # 1..1
7997 11:44:31.264855 # 1..1
7998 11:44:31.264967 # 1..1
7999 11:44:31.265080 # 1..1
8000 11:44:31.265196 # 1..1
8001 11:44:31.265308 # 1..1
8002 11:44:31.265423 # 1..1
8003 11:44:31.265536 # 1..1
8004 11:44:31.270097 #
8005 11:44:31.270522 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
8006 11:44:31.870142 # selftests: arm64: check_ksm_options
8007 11:44:32.173027 # 1..4
8008 11:44:32.173246 # # Invalid MTE synchronous exception caught!
8009 11:44:32.210208 not ok 38 selftests: arm64: check_ksm_options # exit=1
8010 11:44:32.470479 # selftests: arm64: check_mmap_options
8011 11:44:33.247173 # 1..22
8012 11:44:33.247631 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
8013 11:44:33.248047 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
8014 11:44:33.248371 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
8015 11:44:33.248624 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
8016 11:44:33.248837 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
8017 11:44:33.249015 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8018 11:44:33.249188 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
8019 11:44:33.249667 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8020 11:44:33.249921 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
8021 11:44:33.250134 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8022 11:44:33.250331 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
8023 11:44:33.250531 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8024 11:44:33.250732 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
8025 11:44:33.250931 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8026 11:44:33.251464 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
8027 11:44:33.251678 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8028 11:44:33.251931 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
8029 11:44:33.252133 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8030 11:44:33.252339 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
8031 11:44:33.252504 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8032 11:44:33.252708 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
8033 11:44:33.253132 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
8034 11:44:33.253237 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
8035 11:44:33.312747 not ok 39 selftests: arm64: check_mmap_options # exit=1
8036 11:44:33.570233 # selftests: arm64: check_prctl
8037 11:44:33.824236 # TAP version 13
8038 11:44:33.824471 # 1..5
8039 11:44:33.824565 # ok 1 check_basic_read
8040 11:44:33.824849 # ok 2 NONE
8041 11:44:33.824948 # ok 3 SYNC
8042 11:44:33.825043 # ok 4 ASYNC
8043 11:44:33.825132 # ok 5 SYNC+ASYNC
8044 11:44:33.825219 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8045 11:44:33.849046 ok 40 selftests: arm64: check_prctl
8046 11:44:33.935290 # selftests: arm64: check_tags_inclusion
8047 11:44:34.044542 # 1..4
8048 11:44:34.045026 # # Unexpected fault recorded for 0x900ffff9bd47000-0x900ffff9bd47050 in mode 1
8049 11:44:34.045212 # not ok 1 Check an included tag value with sync mode
8050 11:44:34.045415 # # Unexpected fault recorded for 0xe00ffff9bd47000-0xe00ffff9bd47050 in mode 1
8051 11:44:34.045595 # not ok 2 Check different included tags value with sync mode
8052 11:44:34.045751 # ok 3 Check none included tags value with sync mode
8053 11:44:34.045879 # # Unexpected fault recorded for 0x800ffff9bd47000-0x800ffff9bd47050 in mode 1
8054 11:44:34.046022 # not ok 4 Check all included tags value with sync mode
8055 11:44:34.046145 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
8056 11:44:34.064927 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
8057 11:44:34.158430 # selftests: arm64: check_user_mem
8058 11:44:42.510473 # 1..64
8059 11:44:42.510961 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8060 11:44:42.511114 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8061 11:44:42.511246 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8062 11:44:42.511361 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8063 11:44:42.511690 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8064 11:44:42.511792 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8065 11:44:42.511877 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8066 11:44:42.512690 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8067 11:44:42.513102 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8068 11:44:42.513204 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8069 11:44:42.513305 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8070 11:44:42.513393 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8071 11:44:42.513488 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8072 11:44:42.513803 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8073 11:44:42.514109 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8074 11:44:42.514212 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8075 11:44:42.514525 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8076 11:44:42.514629 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8077 11:44:42.514725 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8078 11:44:42.514819 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8079 11:44:42.514913 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8080 11:44:42.515237 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8081 11:44:42.515487 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8082 11:44:42.521378 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8083 11:44:42.521853 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8084 11:44:42.521968 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8085 11:44:42.522077 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8086 11:44:42.522166 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8087 11:44:42.522268 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8088 11:44:42.522769 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8089 11:44:42.522875 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8090 11:44:42.522982 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8091 11:44:42.523150 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8092 11:44:42.523495 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8093 11:44:42.523797 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8094 11:44:42.524155 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8095 11:44:42.524391 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8096 11:44:42.524602 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8097 11:44:42.524815 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8098 11:44:42.525012 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8099 11:44:42.525244 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8100 11:44:42.525439 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8101 11:44:42.525608 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8102 11:44:42.525868 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8103 11:44:42.526085 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8104 11:44:42.526300 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8105 11:44:42.526500 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8106 11:44:42.526714 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8107 11:44:42.526964 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8108 11:44:42.527114 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8109 11:44:42.527239 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8110 11:44:44.194885 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8111 11:44:44.195419 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8112 11:44:44.195541 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8113 11:44:44.196925 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8114 11:44:44.200885 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8115 11:44:44.201301 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8116 11:44:44.201444 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8117 11:44:44.201588 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8118 11:44:44.201718 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8119 11:44:44.201854 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8120 11:44:44.201991 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8121 11:44:44.202142 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8122 11:44:44.202514 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8123 11:44:44.202660 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
8124 11:44:44.217980 ok 42 selftests: arm64: check_user_mem
8125 11:44:44.305316 # selftests: arm64: btitest
8126 11:44:44.399584 # TAP version 13
8127 11:44:44.402289 # 1..18
8128 11:44:44.402608 # # HWCAP_PACA present
8129 11:44:44.403040 # # HWCAP2_BTI present
8130 11:44:44.403238 # # Test binary built for BTI
8131 11:44:44.403411 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
8132 11:44:44.403544 # ok 1 nohint_func/call_using_br_x0
8133 11:44:44.403908 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
8134 11:44:44.404097 # ok 2 nohint_func/call_using_br_x16
8135 11:44:44.404248 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
8136 11:44:44.405121 # ok 3 nohint_func/call_using_blr
8137 11:44:44.405658 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
8138 11:44:44.405883 # ok 4 bti_none_func/call_using_br_x0
8139 11:44:44.406082 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
8140 11:44:44.406307 # ok 5 bti_none_func/call_using_br_x16
8141 11:44:44.406487 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
8142 11:44:44.406654 # ok 6 bti_none_func/call_using_blr
8143 11:44:44.406819 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
8144 11:44:44.407004 # ok 7 bti_c_func/call_using_br_x0
8145 11:44:44.407188 # ok 8 bti_c_func/call_using_br_x16
8146 11:44:44.407357 # ok 9 bti_c_func/call_using_blr
8147 11:44:44.407519 # ok 10 bti_j_func/call_using_br_x0
8148 11:44:44.407654 # ok 11 bti_j_func/call_using_br_x16
8149 11:44:44.407796 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
8150 11:44:44.407918 # ok 12 bti_j_func/call_using_blr
8151 11:44:44.408034 # ok 13 bti_jc_func/call_using_br_x0
8152 11:44:44.408151 # ok 14 bti_jc_func/call_using_br_x16
8153 11:44:44.408265 # ok 15 bti_jc_func/call_using_blr
8154 11:44:44.414237 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
8155 11:44:44.414805 # ok 16 paciasp_func/call_using_br_x0
8156 11:44:44.414966 # ok 17 paciasp_func/call_using_br_x16
8157 11:44:44.415092 # ok 18 paciasp_func/call_using_blr
8158 11:44:44.415212 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8159 11:44:44.437242 ok 43 selftests: arm64: btitest
8160 11:44:44.534358 # selftests: arm64: nobtitest
8161 11:44:44.621582 # TAP version 13
8162 11:44:44.622115 # 1..18
8163 11:44:44.622227 # # HWCAP_PACA present
8164 11:44:44.622319 # # HWCAP2_BTI present
8165 11:44:44.622406 # # Test binary not built for BTI
8166 11:44:44.622497 # ok 1 nohint_func/call_using_br_x0
8167 11:44:44.622582 # ok 2 nohint_func/call_using_br_x16
8168 11:44:44.622666 # ok 3 nohint_func/call_using_blr
8169 11:44:44.622750 # ok 4 bti_none_func/call_using_br_x0
8170 11:44:44.622851 # ok 5 bti_none_func/call_using_br_x16
8171 11:44:44.622936 # ok 6 bti_none_func/call_using_blr
8172 11:44:44.623023 # ok 7 bti_c_func/call_using_br_x0
8173 11:44:44.623108 # ok 8 bti_c_func/call_using_br_x16
8174 11:44:44.623192 # ok 9 bti_c_func/call_using_blr
8175 11:44:44.623278 # ok 10 bti_j_func/call_using_br_x0
8176 11:44:44.623367 # ok 11 bti_j_func/call_using_br_x16
8177 11:44:44.623470 # ok 12 bti_j_func/call_using_blr
8178 11:44:44.623557 # ok 13 bti_jc_func/call_using_br_x0
8179 11:44:44.623643 # ok 14 bti_jc_func/call_using_br_x16
8180 11:44:44.623729 # ok 15 bti_jc_func/call_using_blr
8181 11:44:44.623830 # ok 16 paciasp_func/call_using_br_x0
8182 11:44:44.623939 # ok 17 paciasp_func/call_using_br_x16
8183 11:44:44.624028 # ok 18 paciasp_func/call_using_blr
8184 11:44:44.624110 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8185 11:44:44.641323 ok 44 selftests: arm64: nobtitest
8186 11:44:44.734228 # selftests: arm64: hwcap
8187 11:44:44.902294 # TAP version 13
8188 11:44:44.902670 # 1..28
8189 11:44:44.902881 # # RNG present
8190 11:44:44.903075 # ok 1 cpuinfo_match_RNG
8191 11:44:44.903230 # ok 2 sigill_RNG
8192 11:44:44.903416 # # SME present
8193 11:44:44.903592 # ok 3 cpuinfo_match_SME
8194 11:44:44.903781 # ok 4 sigill_SME
8195 11:44:44.903910 # # SVE present
8196 11:44:44.904032 # ok 5 cpuinfo_match_SVE
8197 11:44:44.904148 # ok 6 sigill_SVE
8198 11:44:44.904262 # # SVE 2 present
8199 11:44:44.904377 # ok 7 cpuinfo_match_SVE 2
8200 11:44:44.904491 # ok 8 sigill_SVE 2
8201 11:44:44.904605 # # SVE AES present
8202 11:44:44.904718 # ok 9 cpuinfo_match_SVE AES
8203 11:44:44.904833 # ok 10 sigill_SVE AES
8204 11:44:44.904948 # # SVE2 PMULL present
8205 11:44:44.922124 # ok 11 cpuinfo_match_SVE2 PMULL
8206 11:44:44.922590 # ok 12 sigill_SVE2 PMULL
8207 11:44:44.922698 # # SVE2 BITPERM present
8208 11:44:44.922790 # ok 13 cpuinfo_match_SVE2 BITPERM
8209 11:44:44.922874 # ok 14 sigill_SVE2 BITPERM
8210 11:44:44.922979 # # SVE2 SHA3 present
8211 11:44:44.923072 # ok 15 cpuinfo_match_SVE2 SHA3
8212 11:44:44.923159 # ok 16 sigill_SVE2 SHA3
8213 11:44:44.923247 # # SVE2 SM4 present
8214 11:44:44.923331 # ok 17 cpuinfo_match_SVE2 SM4
8215 11:44:44.923421 # ok 18 sigill_SVE2 SM4
8216 11:44:44.923505 # # SVE2 I8MM present
8217 11:44:44.923587 # ok 19 cpuinfo_match_SVE2 I8MM
8218 11:44:44.923689 # ok 20 sigill_SVE2 I8MM
8219 11:44:44.923776 # # SVE2 F32MM present
8220 11:44:44.923857 # ok 21 cpuinfo_match_SVE2 F32MM
8221 11:44:44.923936 # ok 22 sigill_SVE2 F32MM
8222 11:44:44.924022 # # SVE2 F64MM present
8223 11:44:44.924105 # ok 23 cpuinfo_match_SVE2 F64MM
8224 11:44:44.924182 # ok 24 sigill_SVE2 F64MM
8225 11:44:44.925133 # # SVE2 BF16 present
8226 11:44:44.925596 # ok 25 cpuinfo_match_SVE2 BF16
8227 11:44:44.925773 # ok 26 sigill_SVE2 BF16
8228 11:44:44.925907 # ok 27 cpuinfo_match_SVE2 EBF16
8229 11:44:44.926035 # ok 28 # SKIP sigill_SVE2 EBF16
8230 11:44:44.926156 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8231 11:44:44.943307 ok 45 selftests: arm64: hwcap
8232 11:44:45.190414 # selftests: arm64: ptrace
8233 11:44:45.425276 # TAP version 13
8234 11:44:45.425522 # 1..7
8235 11:44:45.425614 # # Parent is 4413, child is 4414
8236 11:44:45.425918 # ok 1 read_tpidr_one
8237 11:44:45.426016 # ok 2 write_tpidr_one
8238 11:44:45.426101 # ok 3 verify_tpidr_one
8239 11:44:45.426186 # ok 4 count_tpidrs
8240 11:44:45.426269 # ok 5 tpidr2_write
8241 11:44:45.426353 # ok 6 tpidr2_read
8242 11:44:45.426435 # ok 7 write_tpidr_only
8243 11:44:45.426518 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8244 11:44:45.462513 ok 46 selftests: arm64: ptrace
8245 11:44:45.626307 # selftests: arm64: syscall-abi
8246 11:44:48.340542 # TAP version 13
8247 11:44:48.340997 # 1..514
8248 11:44:48.341112 # # SME with FA64
8249 11:44:48.341206 # ok 1 getpid() FPSIMD
8250 11:44:48.341296 # ok 2 getpid() SVE VL 256
8251 11:44:48.341388 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8252 11:44:48.341498 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8253 11:44:48.341594 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8254 11:44:48.341692 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8255 11:44:48.341782 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8256 11:44:48.341869 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8257 11:44:48.341974 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8258 11:44:48.342065 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8259 11:44:48.342148 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8260 11:44:48.342231 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8261 11:44:48.342313 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8262 11:44:48.342679 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8263 11:44:48.342788 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8264 11:44:48.342874 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8265 11:44:48.342960 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8266 11:44:48.343045 # ok 18 getpid() SVE VL 240
8267 11:44:48.343127 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8268 11:44:48.343211 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8269 11:44:48.343315 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8270 11:44:48.343405 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8271 11:44:48.343488 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8272 11:44:48.343569 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8273 11:44:48.343655 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8274 11:44:48.343738 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8275 11:44:48.343843 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8276 11:44:48.348355 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8277 11:44:48.348861 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8278 11:44:48.348974 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8279 11:44:48.349068 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8280 11:44:48.349156 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8281 11:44:48.349241 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8282 11:44:48.349327 # ok 34 getpid() SVE VL 224
8283 11:44:48.349430 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8284 11:44:48.349519 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8285 11:44:48.349613 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8286 11:44:48.349707 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8287 11:44:48.349811 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8288 11:44:48.349900 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8289 11:44:48.349986 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8290 11:44:48.350094 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8291 11:44:48.350183 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8292 11:44:48.350287 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8293 11:44:48.350391 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8294 11:44:48.350494 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8295 11:44:48.350602 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8296 11:44:48.350705 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8297 11:44:48.351257 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8298 11:44:48.351630 # ok 50 getpid() SVE VL 208
8299 11:44:48.351793 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8300 11:44:48.351922 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8301 11:44:48.356453 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8302 11:44:48.356710 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8303 11:44:48.356921 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8304 11:44:48.357102 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8305 11:44:48.357258 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8306 11:44:48.357436 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8307 11:44:48.357621 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8308 11:44:48.357845 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8309 11:44:48.358112 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8310 11:44:48.358310 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8311 11:44:48.358501 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8312 11:44:48.358713 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8313 11:44:48.358904 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8314 11:44:48.359094 # ok 66 getpid() SVE VL 192
8315 11:44:48.359304 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8316 11:44:48.359480 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8317 11:44:48.359630 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8318 11:44:48.359793 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8319 11:44:48.359924 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8320 11:44:48.360093 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8321 11:44:48.360277 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8322 11:44:48.360468 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8323 11:44:48.360603 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8324 11:44:48.360766 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8325 11:44:48.360898 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8326 11:44:48.361025 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8327 11:44:48.361149 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8328 11:44:48.361273 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8329 11:44:48.361398 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8330 11:44:48.361521 # ok 82 getpid() SVE VL 176
8331 11:44:48.364344 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8332 11:44:48.364568 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8333 11:44:48.365005 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8334 11:44:48.365205 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8335 11:44:48.365411 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8336 11:44:48.365618 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8337 11:44:48.365815 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8338 11:44:48.366025 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8339 11:44:48.366165 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8340 11:44:48.366308 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8341 11:44:48.366451 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8342 11:44:48.366593 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8343 11:44:48.366733 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8344 11:44:48.366874 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8345 11:44:48.367015 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8346 11:44:48.367156 # ok 98 getpid() SVE VL 160
8347 11:44:50.998426 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8348 11:44:50.998907 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8349 11:44:50.999004 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8350 11:44:50.999632 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8351 11:44:50.999744 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8352 11:44:50.999827 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8353 11:44:51.000610 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8354 11:44:51.000956 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8355 11:44:51.001071 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8356 11:44:51.001187 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8357 11:44:51.001576 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8358 11:44:51.001743 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8359 11:44:51.001871 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8360 11:44:51.002380 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8361 11:44:51.002524 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8362 11:44:51.002608 # ok 114 getpid() SVE VL 144
8363 11:44:51.002691 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8364 11:44:51.002773 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8365 11:44:51.003099 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8366 11:44:51.003200 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8367 11:44:51.003290 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8368 11:44:51.003376 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8369 11:44:51.003469 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8370 11:44:51.003597 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8371 11:44:51.003706 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8372 11:44:51.003789 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8373 11:44:51.012405 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8374 11:44:51.012724 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8375 11:44:51.013118 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8376 11:44:51.013320 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8377 11:44:51.013498 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8378 11:44:51.013690 # ok 130 getpid() SVE VL 128
8379 11:44:51.013859 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8380 11:44:51.014027 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8381 11:44:51.014198 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8382 11:44:51.014422 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8383 11:44:51.014590 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8384 11:44:51.014762 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8385 11:44:51.014935 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8386 11:44:51.015111 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8387 11:44:51.015284 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8388 11:44:51.015467 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8389 11:44:51.015618 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8390 11:44:51.015784 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8391 11:44:51.015939 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8392 11:44:51.016059 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8393 11:44:51.016172 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8394 11:44:51.016284 # ok 146 getpid() SVE VL 112
8395 11:44:51.016460 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8396 11:44:51.016657 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8397 11:44:51.016833 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8398 11:44:51.017006 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8399 11:44:51.017136 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8400 11:44:51.017258 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8401 11:44:51.017379 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8402 11:44:51.024289 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8403 11:44:51.024739 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8404 11:44:51.024844 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8405 11:44:51.024933 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8406 11:44:51.025020 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8407 11:44:51.025306 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8408 11:44:51.025413 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8409 11:44:51.025490 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8410 11:44:51.025564 # ok 162 getpid() SVE VL 96
8411 11:44:51.025639 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8412 11:44:51.025735 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8413 11:44:51.025809 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8414 11:44:51.025881 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8415 11:44:51.025954 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8416 11:44:51.026045 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8417 11:44:51.026132 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8418 11:44:51.026234 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8419 11:44:51.026316 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8420 11:44:51.026407 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8421 11:44:51.026498 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8422 11:44:51.026792 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8423 11:44:51.026996 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8424 11:44:51.027195 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8425 11:44:51.027351 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8426 11:44:51.027488 # ok 178 getpid() SVE VL 80
8427 11:44:51.027647 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8428 11:44:51.027825 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8429 11:44:51.027997 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8430 11:44:51.028658 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8431 11:44:51.028853 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8432 11:44:51.029219 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8433 11:44:51.029323 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8434 11:44:51.029418 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8435 11:44:51.029511 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8436 11:44:51.029599 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8437 11:44:51.029697 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8438 11:44:51.029808 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8439 11:44:51.029901 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8440 11:44:51.029990 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8441 11:44:51.030076 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8442 11:44:51.030160 # ok 194 getpid() SVE VL 64
8443 11:44:51.030263 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8444 11:44:53.390405 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8445 11:44:53.390981 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8446 11:44:53.391162 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8447 11:44:53.391333 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8448 11:44:53.391488 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8449 11:44:53.391621 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8450 11:44:53.391770 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8451 11:44:53.391891 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8452 11:44:53.392007 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8453 11:44:53.392124 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8454 11:44:53.392237 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8455 11:44:53.399887 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8456 11:44:53.400221 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8457 11:44:53.400632 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8458 11:44:53.400800 # ok 210 getpid() SVE VL 48
8459 11:44:53.400959 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8460 11:44:53.401120 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8461 11:44:53.401276 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8462 11:44:53.401433 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8463 11:44:53.401587 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8464 11:44:53.401757 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8465 11:44:53.401913 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8466 11:44:53.402106 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8467 11:44:53.402267 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8468 11:44:53.402424 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8469 11:44:53.402576 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8470 11:44:53.402727 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8471 11:44:53.402881 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8472 11:44:53.403036 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8473 11:44:53.403191 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8474 11:44:53.403325 # ok 226 getpid() SVE VL 32
8475 11:44:53.403445 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8476 11:44:53.403562 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8477 11:44:53.403678 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8478 11:44:53.403795 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8479 11:44:53.403939 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8480 11:44:53.404092 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8481 11:44:53.404293 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8482 11:44:53.404455 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8483 11:44:53.404611 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8484 11:44:53.404764 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8485 11:44:53.404918 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8486 11:44:53.405073 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8487 11:44:53.405227 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8488 11:44:53.405378 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8489 11:44:53.405533 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8490 11:44:53.405699 # ok 242 getpid() SVE VL 16
8491 11:44:53.405854 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8492 11:44:53.406007 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8493 11:44:53.406163 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8494 11:44:53.406318 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8495 11:44:53.406473 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8496 11:44:53.406627 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8497 11:44:53.406823 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8498 11:44:53.406988 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8499 11:44:53.407146 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8500 11:44:53.407298 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8501 11:44:53.407451 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8502 11:44:53.407593 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8503 11:44:53.407952 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8504 11:44:53.408061 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8505 11:44:53.408149 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8506 11:44:53.408226 # ok 258 sched_yield() FPSIMD
8507 11:44:53.408303 # ok 259 sched_yield() SVE VL 256
8508 11:44:53.408379 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8509 11:44:53.408455 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8510 11:44:53.408530 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8511 11:44:53.408605 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8512 11:44:53.408680 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8513 11:44:53.408755 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8514 11:44:53.408830 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8515 11:44:53.408906 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8516 11:44:53.408981 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8517 11:44:53.409056 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8518 11:44:53.409136 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8519 11:44:53.409211 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8520 11:44:53.409286 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8521 11:44:53.409360 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8522 11:44:53.409435 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8523 11:44:53.409510 # ok 275 sched_yield() SVE VL 240
8524 11:44:53.409585 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8525 11:44:53.409670 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8526 11:44:53.409747 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8527 11:44:53.409822 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8528 11:44:53.409897 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8529 11:44:53.411997 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8530 11:44:53.412121 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8531 11:44:53.412442 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8532 11:44:53.412549 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8533 11:44:53.412639 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8534 11:44:53.412721 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8535 11:44:53.412816 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8536 11:44:53.412899 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8537 11:44:53.412981 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8538 11:44:55.469256 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8539 11:44:55.469692 # ok 291 sched_yield() SVE VL 224
8540 11:44:55.469821 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8541 11:44:55.469916 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8542 11:44:55.470020 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8543 11:44:55.470111 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8544 11:44:55.470203 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8545 11:44:55.470294 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8546 11:44:55.470384 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8547 11:44:55.470462 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8548 11:44:55.470551 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8549 11:44:55.470630 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8550 11:44:55.470721 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8551 11:44:55.471008 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8552 11:44:55.471106 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8553 11:44:55.471199 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8554 11:44:55.471482 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8555 11:44:55.471586 # ok 307 sched_yield() SVE VL 208
8556 11:44:55.471674 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8557 11:44:55.479849 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8558 11:44:55.480248 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8559 11:44:55.480358 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8560 11:44:55.480448 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8561 11:44:55.480550 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8562 11:44:55.480640 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8563 11:44:55.480741 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8564 11:44:55.480823 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8565 11:44:55.480907 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8566 11:44:55.481004 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8567 11:44:55.481088 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8568 11:44:55.481169 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8569 11:44:55.481268 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8570 11:44:55.481354 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8571 11:44:55.481658 # ok 323 sched_yield() SVE VL 192
8572 11:44:55.481791 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8573 11:44:55.481886 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8574 11:44:55.481989 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8575 11:44:55.482087 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8576 11:44:55.482186 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8577 11:44:55.482408 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8578 11:44:55.482508 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8579 11:44:55.482583 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8580 11:44:55.482658 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8581 11:44:55.482741 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8582 11:44:55.482825 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8583 11:44:55.483111 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8584 11:44:55.483217 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8585 11:44:55.483294 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8586 11:44:55.483377 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8587 11:44:55.483448 # ok 339 sched_yield() SVE VL 176
8588 11:44:55.483531 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8589 11:44:55.484019 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8590 11:44:55.484308 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8591 11:44:55.484400 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8592 11:44:55.484488 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8593 11:44:55.484563 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8594 11:44:55.484660 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8595 11:44:55.484747 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8596 11:44:55.484845 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8597 11:44:55.484944 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8598 11:44:55.485044 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8599 11:44:55.485147 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8600 11:44:55.485246 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8601 11:44:55.485345 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8602 11:44:55.485443 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8603 11:44:55.485542 # ok 355 sched_yield() SVE VL 160
8604 11:44:55.485641 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8605 11:44:55.485751 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8606 11:44:55.485852 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8607 11:44:55.486217 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8608 11:44:55.486310 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8609 11:44:55.486398 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8610 11:44:55.486690 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8611 11:44:55.486881 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8612 11:44:55.487090 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8613 11:44:55.487280 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8614 11:44:55.487478 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8615 11:44:55.487651 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8616 11:44:55.487837 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8617 11:44:55.487977 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8618 11:44:55.488144 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8619 11:44:55.492146 # ok 371 sched_yield() SVE VL 144
8620 11:44:55.492514 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8621 11:44:55.492615 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8622 11:44:55.492699 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8623 11:44:55.492791 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8624 11:44:55.492872 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8625 11:44:57.605657 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8626 11:44:57.606098 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8627 11:44:57.606204 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8628 11:44:57.606293 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8629 11:44:57.606379 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8630 11:44:57.606481 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8631 11:44:57.606567 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8632 11:44:57.606653 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8633 11:44:57.606737 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8634 11:44:57.606837 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8635 11:44:57.606924 # ok 387 sched_yield() SVE VL 128
8636 11:44:57.607008 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8637 11:44:57.607112 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8638 11:44:57.607198 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8639 11:44:57.607298 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8640 11:44:57.607385 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8641 11:44:57.607469 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8642 11:44:57.607570 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8643 11:44:57.607653 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8644 11:44:57.607748 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8645 11:44:57.616500 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8646 11:44:57.616728 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8647 11:44:57.616817 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8648 11:44:57.616918 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8649 11:44:57.617006 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8650 11:44:57.617095 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8651 11:44:57.617179 # ok 403 sched_yield() SVE VL 112
8652 11:44:57.617278 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8653 11:44:57.617361 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8654 11:44:57.617443 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8655 11:44:57.617524 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8656 11:44:57.617624 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8657 11:44:57.617721 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8658 11:44:57.617817 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8659 11:44:57.617901 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8660 11:44:57.618001 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8661 11:44:57.618089 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8662 11:44:57.618190 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8663 11:44:57.618494 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8664 11:44:57.618593 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8665 11:44:57.618692 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8666 11:44:57.618776 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8667 11:44:57.618858 # ok 419 sched_yield() SVE VL 96
8668 11:44:57.619388 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8669 11:44:57.619489 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8670 11:44:57.619572 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8671 11:44:57.619845 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8672 11:44:57.619935 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8673 11:44:57.620672 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8674 11:44:57.620972 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8675 11:44:57.621279 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8676 11:44:57.621389 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8677 11:44:57.621497 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8678 11:44:57.621582 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8679 11:44:57.621679 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8680 11:44:57.621764 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8681 11:44:57.621849 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8682 11:44:57.621933 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8683 11:44:57.622016 # ok 435 sched_yield() SVE VL 80
8684 11:44:57.622310 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8685 11:44:57.622404 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8686 11:44:57.622476 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8687 11:44:57.622766 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8688 11:44:57.622858 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8689 11:44:57.622930 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8690 11:44:57.622999 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8691 11:44:57.623083 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8692 11:44:57.623160 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8693 11:44:57.623232 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8694 11:44:57.623301 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8695 11:44:57.623369 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8696 11:44:57.623452 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8697 11:44:57.623525 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8698 11:44:57.623599 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8699 11:44:57.623669 # ok 451 sched_yield() SVE VL 64
8700 11:44:57.628939 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8701 11:44:57.629298 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8702 11:44:57.629401 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8703 11:44:57.629488 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8704 11:44:57.629584 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8705 11:44:57.629672 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8706 11:44:57.629759 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8707 11:44:57.629833 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8708 11:44:57.629917 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8709 11:44:57.630196 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8710 11:44:57.630286 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8711 11:44:57.630358 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8712 11:44:58.311077 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8713 11:44:58.311305 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8714 11:44:58.311387 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8715 11:44:58.311662 # ok 467 sched_yield() SVE VL 48
8716 11:44:58.311826 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8717 11:44:58.311953 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8718 11:44:58.312071 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8719 11:44:58.313200 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8720 11:44:58.313582 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8721 11:44:58.313705 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8722 11:44:58.313796 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8723 11:44:58.313881 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8724 11:44:58.313964 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8725 11:44:58.314065 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8726 11:44:58.314151 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8727 11:44:58.314234 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8728 11:44:58.314332 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8729 11:44:58.314418 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8730 11:44:58.315407 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8731 11:44:58.315525 # ok 483 sched_yield() SVE VL 32
8732 11:44:58.315608 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8733 11:44:58.315689 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8734 11:44:58.315771 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8735 11:44:58.315854 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8736 11:44:58.315935 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8737 11:44:58.316017 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8738 11:44:58.316097 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8739 11:44:58.316179 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8740 11:44:58.316261 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8741 11:44:58.316342 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8742 11:44:58.322895 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8743 11:44:58.323136 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8744 11:44:58.323453 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8745 11:44:58.323559 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8746 11:44:58.323647 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8747 11:44:58.323728 # ok 499 sched_yield() SVE VL 16
8748 11:44:58.323810 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8749 11:44:58.323894 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8750 11:44:58.323994 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8751 11:44:58.324281 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8752 11:44:58.324385 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8753 11:44:58.324490 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8754 11:44:58.324579 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8755 11:44:58.324862 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8756 11:44:58.324960 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8757 11:44:58.325049 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8758 11:44:58.325138 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8759 11:44:58.325227 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8760 11:44:58.325317 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8761 11:44:58.325427 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8762 11:44:58.325519 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8763 11:44:58.325608 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8764 11:44:58.325897 ok 47 selftests: arm64: syscall-abi
8765 11:44:58.378587 # selftests: arm64: tpidr2
8766 11:44:58.543158 # TAP version 13
8767 11:44:58.543606 # 1..5
8768 11:44:58.543719 # # PID: 4448
8769 11:44:58.543812 # ok 1 default_value
8770 11:44:58.544486 # ok 2 write_read
8771 11:44:58.544799 # ok 3 write_sleep_read
8772 11:44:58.544904 # ok 4 write_fork_read
8773 11:44:58.545019 # ok 5 write_clone_read
8774 11:44:58.545324 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8775 11:44:58.561353 ok 48 selftests: arm64: tpidr2
8776 11:44:59.079268 arm64_tags_test pass
8777 11:44:59.079521 arm64_run_tags_test_sh pass
8778 11:44:59.079614 arm64_fake_sigreturn_bad_magic pass
8779 11:44:59.079924 arm64_fake_sigreturn_bad_size pass
8780 11:44:59.080023 arm64_fake_sigreturn_bad_size_for_magic0 pass
8781 11:44:59.080103 arm64_fake_sigreturn_duplicated_fpsimd pass
8782 11:44:59.080180 arm64_fake_sigreturn_misaligned_sp pass
8783 11:44:59.080426 arm64_fake_sigreturn_missing_fpsimd pass
8784 11:44:59.080519 arm64_fake_sigreturn_sme_change_vl pass
8785 11:44:59.080594 arm64_fake_sigreturn_sve_change_vl pass
8786 11:44:59.080666 arm64_mangle_pstate_invalid_compat_toggle pass
8787 11:44:59.080737 arm64_mangle_pstate_invalid_daif_bits pass
8788 11:44:59.080812 arm64_mangle_pstate_invalid_mode_el1h pass
8789 11:44:59.080900 arm64_mangle_pstate_invalid_mode_el1t pass
8790 11:44:59.080973 arm64_mangle_pstate_invalid_mode_el2h pass
8791 11:44:59.081042 arm64_mangle_pstate_invalid_mode_el2t pass
8792 11:44:59.081113 arm64_mangle_pstate_invalid_mode_el3h pass
8793 11:44:59.081186 arm64_mangle_pstate_invalid_mode_el3t pass
8794 11:44:59.081276 arm64_sme_trap_no_sm pass
8795 11:44:59.081356 arm64_sme_trap_non_streaming skip
8796 11:44:59.081430 arm64_sme_trap_za pass
8797 11:44:59.081501 arm64_sme_vl pass
8798 11:44:59.081573 arm64_ssve_regs pass
8799 11:44:59.081643 arm64_sve_regs pass
8800 11:44:59.081740 arm64_sve_vl pass
8801 11:44:59.081828 arm64_za_no_regs pass
8802 11:44:59.081905 arm64_za_regs pass
8803 11:44:59.081978 arm64_pac_global_corrupt_pac pass
8804 11:44:59.082049 arm64_pac_global_pac_instructions_not_nop pass
8805 11:44:59.082120 arm64_pac_global_pac_instructions_not_nop_generic pass
8806 11:44:59.082205 arm64_pac_global_single_thread_different_keys pass
8807 11:44:59.082279 arm64_pac_global_exec_changed_keys pass
8808 11:44:59.082572 arm64_pac_global_context_switch_keep_keys pass
8809 11:44:59.082668 arm64_pac_global_context_switch_keep_keys_generic pass
8810 11:44:59.082745 arm64_pac pass
8811 11:44:59.082818 arm64_fp-stress_FPSIMD-0-0 pass
8812 11:44:59.082890 arm64_fp-stress_SVE-VL-256-0 pass
8813 11:44:59.082962 arm64_fp-stress_SVE-VL-240-0 pass
8814 11:44:59.083037 arm64_fp-stress_SVE-VL-224-0 pass
8815 11:44:59.083114 arm64_fp-stress_SVE-VL-208-0 pass
8816 11:44:59.083206 arm64_fp-stress_SVE-VL-192-0 pass
8817 11:44:59.083284 arm64_fp-stress_SVE-VL-176-0 pass
8818 11:44:59.083363 arm64_fp-stress_SVE-VL-160-0 pass
8819 11:44:59.083438 arm64_fp-stress_SVE-VL-144-0 pass
8820 11:44:59.083512 arm64_fp-stress_SVE-VL-128-0 pass
8821 11:44:59.083585 arm64_fp-stress_SVE-VL-112-0 pass
8822 11:44:59.083657 arm64_fp-stress_SVE-VL-96-0 pass
8823 11:44:59.083730 arm64_fp-stress_SVE-VL-80-0 pass
8824 11:44:59.083802 arm64_fp-stress_SVE-VL-64-0 pass
8825 11:44:59.083877 arm64_fp-stress_SVE-VL-48-0 pass
8826 11:44:59.083964 arm64_fp-stress_SVE-VL-32-0 pass
8827 11:44:59.084037 arm64_fp-stress_SVE-VL-16-0 pass
8828 11:44:59.087731 arm64_fp-stress_SSVE-VL-256-0 pass
8829 11:44:59.088161 arm64_fp-stress_ZA-VL-256-0 pass
8830 11:44:59.088272 arm64_fp-stress_SSVE-VL-128-0 pass
8831 11:44:59.088364 arm64_fp-stress_ZA-VL-128-0 pass
8832 11:44:59.088449 arm64_fp-stress_SSVE-VL-64-0 pass
8833 11:44:59.088535 arm64_fp-stress_ZA-VL-64-0 pass
8834 11:44:59.088634 arm64_fp-stress_SSVE-VL-32-0 pass
8835 11:44:59.088724 arm64_fp-stress_ZA-VL-32-0 pass
8836 11:44:59.088809 arm64_fp-stress_SSVE-VL-16-0 pass
8837 11:44:59.088893 arm64_fp-stress_ZA-VL-16-0 pass
8838 11:44:59.088975 arm64_fp-stress pass
8839 11:44:59.089079 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8840 11:44:59.089166 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8841 11:44:59.089254 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8842 11:44:59.089336 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8843 11:44:59.089417 arm64_sve-ptrace_Set_SVE_VL_16 pass
8844 11:44:59.089517 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8845 11:44:59.089602 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8846 11:44:59.089693 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8847 11:44:59.089777 arm64_sve-ptrace_Set_SVE_VL_32 pass
8848 11:44:59.089878 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8849 11:44:59.089962 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8850 11:44:59.090042 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8851 11:44:59.090124 arm64_sve-ptrace_Set_SVE_VL_48 pass
8852 11:44:59.090223 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8853 11:44:59.090305 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8854 11:44:59.090403 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8855 11:44:59.090490 arm64_sve-ptrace_Set_SVE_VL_64 pass
8856 11:44:59.090593 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8857 11:44:59.090678 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8858 11:44:59.090758 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8859 11:44:59.090853 arm64_sve-ptrace_Set_SVE_VL_80 pass
8860 11:44:59.090937 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8861 11:44:59.091034 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8862 11:44:59.091134 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8863 11:44:59.091218 arm64_sve-ptrace_Set_SVE_VL_96 pass
8864 11:44:59.091314 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8865 11:44:59.091400 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8866 11:44:59.091495 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8867 11:44:59.095831 arm64_sve-ptrace_Set_SVE_VL_112 pass
8868 11:44:59.096131 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8869 11:44:59.096598 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8870 11:44:59.096802 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8871 11:44:59.096964 arm64_sve-ptrace_Set_SVE_VL_128 pass
8872 11:44:59.097115 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8873 11:44:59.097279 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8874 11:44:59.097420 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8875 11:44:59.097610 arm64_sve-ptrace_Set_SVE_VL_144 pass
8876 11:44:59.097822 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8877 11:44:59.098039 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8878 11:44:59.098222 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8879 11:44:59.098380 arm64_sve-ptrace_Set_SVE_VL_160 pass
8880 11:44:59.098547 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8881 11:44:59.098705 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8882 11:44:59.098877 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8883 11:44:59.099008 arm64_sve-ptrace_Set_SVE_VL_176 pass
8884 11:44:59.099133 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8885 11:44:59.099256 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8886 11:44:59.099373 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8887 11:44:59.099497 arm64_sve-ptrace_Set_SVE_VL_192 pass
8888 11:44:59.099614 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8889 11:44:59.099729 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8890 11:44:59.099845 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8891 11:44:59.099964 arm64_sve-ptrace_Set_SVE_VL_208 pass
8892 11:44:59.100107 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8893 11:44:59.100230 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8894 11:44:59.100347 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8895 11:44:59.100462 arm64_sve-ptrace_Set_SVE_VL_224 pass
8896 11:44:59.100578 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8897 11:44:59.103755 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8898 11:44:59.104263 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8899 11:44:59.104444 arm64_sve-ptrace_Set_SVE_VL_240 pass
8900 11:44:59.104616 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8901 11:44:59.104784 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8902 11:44:59.104951 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8903 11:44:59.105152 arm64_sve-ptrace_Set_SVE_VL_256 pass
8904 11:44:59.105307 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8905 11:44:59.105467 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8906 11:44:59.105634 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8907 11:44:59.105811 arm64_sve-ptrace_Set_SVE_VL_272 pass
8908 11:44:59.105980 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8909 11:44:59.106146 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8910 11:44:59.106340 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8911 11:44:59.106510 arm64_sve-ptrace_Set_SVE_VL_288 pass
8912 11:44:59.106675 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8913 11:44:59.106845 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8914 11:44:59.107008 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8915 11:44:59.107173 arm64_sve-ptrace_Set_SVE_VL_304 pass
8916 11:44:59.107334 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8917 11:44:59.107498 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8918 11:44:59.107657 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8919 11:44:59.107784 arm64_sve-ptrace_Set_SVE_VL_320 pass
8920 11:44:59.107901 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8921 11:44:59.108018 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8922 11:44:59.108134 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8923 11:44:59.108250 arm64_sve-ptrace_Set_SVE_VL_336 pass
8924 11:44:59.108367 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8925 11:44:59.108482 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8926 11:44:59.111914 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8927 11:44:59.112100 arm64_sve-ptrace_Set_SVE_VL_352 pass
8928 11:44:59.112203 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8929 11:44:59.112293 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8930 11:44:59.112400 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8931 11:44:59.112488 arm64_sve-ptrace_Set_SVE_VL_368 pass
8932 11:44:59.112573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8933 11:44:59.112672 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8934 11:44:59.112756 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8935 11:44:59.112838 arm64_sve-ptrace_Set_SVE_VL_384 pass
8936 11:44:59.112942 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8937 11:44:59.113027 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8938 11:44:59.113112 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8939 11:44:59.113214 arm64_sve-ptrace_Set_SVE_VL_400 pass
8940 11:44:59.113520 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8941 11:44:59.113624 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8942 11:44:59.113735 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8943 11:44:59.113820 arm64_sve-ptrace_Set_SVE_VL_416 pass
8944 11:44:59.113920 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8945 11:44:59.114011 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8946 11:44:59.114109 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8947 11:44:59.114195 arm64_sve-ptrace_Set_SVE_VL_432 pass
8948 11:44:59.114292 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
8949 11:44:59.114392 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
8950 11:44:59.114493 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
8951 11:44:59.114593 arm64_sve-ptrace_Set_SVE_VL_448 pass
8952 11:44:59.114695 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
8953 11:44:59.114794 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
8954 11:44:59.132044 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
8955 11:44:59.132290 arm64_sve-ptrace_Set_SVE_VL_464 pass
8956 11:44:59.132377 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
8957 11:44:59.132731 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
8958 11:44:59.132942 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
8959 11:44:59.133148 arm64_sve-ptrace_Set_SVE_VL_480 pass
8960 11:44:59.133431 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
8961 11:44:59.133798 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
8962 11:44:59.133995 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
8963 11:44:59.134189 arm64_sve-ptrace_Set_SVE_VL_496 pass
8964 11:44:59.134365 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
8965 11:44:59.134526 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
8966 11:44:59.134699 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
8967 11:44:59.134881 arm64_sve-ptrace_Set_SVE_VL_512 pass
8968 11:44:59.135057 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
8969 11:44:59.135204 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
8970 11:44:59.135348 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
8971 11:44:59.135491 arm64_sve-ptrace_Set_SVE_VL_528 pass
8972 11:44:59.135680 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
8973 11:44:59.135817 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
8974 11:44:59.135964 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
8975 11:44:59.136106 arm64_sve-ptrace_Set_SVE_VL_544 pass
8976 11:44:59.136250 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
8977 11:44:59.136391 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
8978 11:44:59.136534 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
8979 11:44:59.136677 arm64_sve-ptrace_Set_SVE_VL_560 pass
8980 11:44:59.136820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
8981 11:44:59.136967 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
8982 11:44:59.137110 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
8983 11:44:59.137264 arm64_sve-ptrace_Set_SVE_VL_576 pass
8984 11:44:59.137420 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
8985 11:44:59.137541 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
8986 11:44:59.137676 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
8987 11:44:59.139711 arm64_sve-ptrace_Set_SVE_VL_592 pass
8988 11:44:59.140111 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
8989 11:44:59.140290 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
8990 11:44:59.140441 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
8991 11:44:59.140627 arm64_sve-ptrace_Set_SVE_VL_608 pass
8992 11:44:59.140799 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
8993 11:44:59.140962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
8994 11:44:59.141157 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
8995 11:44:59.141367 arm64_sve-ptrace_Set_SVE_VL_624 pass
8996 11:44:59.141573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
8997 11:44:59.141793 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
8998 11:44:59.141996 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
8999 11:44:59.142243 arm64_sve-ptrace_Set_SVE_VL_640 pass
9000 11:44:59.142478 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
9001 11:44:59.142715 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
9002 11:44:59.142910 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
9003 11:44:59.143084 arm64_sve-ptrace_Set_SVE_VL_656 pass
9004 11:44:59.143252 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
9005 11:44:59.143419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
9006 11:44:59.143578 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
9007 11:44:59.143700 arm64_sve-ptrace_Set_SVE_VL_672 pass
9008 11:44:59.143814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
9009 11:44:59.143928 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
9010 11:44:59.144043 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
9011 11:44:59.144185 arm64_sve-ptrace_Set_SVE_VL_688 pass
9012 11:44:59.144303 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
9013 11:44:59.144418 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
9014 11:44:59.144531 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
9015 11:44:59.144644 arm64_sve-ptrace_Set_SVE_VL_704 pass
9016 11:44:59.144757 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
9017 11:44:59.147711 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
9018 11:44:59.148074 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
9019 11:44:59.148184 arm64_sve-ptrace_Set_SVE_VL_720 pass
9020 11:44:59.148275 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
9021 11:44:59.148378 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
9022 11:44:59.148467 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
9023 11:44:59.148572 arm64_sve-ptrace_Set_SVE_VL_736 pass
9024 11:44:59.148666 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
9025 11:44:59.148972 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
9026 11:44:59.149080 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
9027 11:44:59.149187 arm64_sve-ptrace_Set_SVE_VL_752 pass
9028 11:44:59.149279 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
9029 11:44:59.149379 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
9030 11:44:59.149465 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
9031 11:44:59.149563 arm64_sve-ptrace_Set_SVE_VL_768 pass
9032 11:44:59.149672 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
9033 11:44:59.149774 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
9034 11:44:59.149874 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
9035 11:44:59.149975 arm64_sve-ptrace_Set_SVE_VL_784 pass
9036 11:44:59.150370 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
9037 11:44:59.150699 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
9038 11:44:59.151017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
9039 11:44:59.151205 arm64_sve-ptrace_Set_SVE_VL_800 pass
9040 11:44:59.151377 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
9041 11:44:59.151537 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
9042 11:44:59.151685 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
9043 11:44:59.151813 arm64_sve-ptrace_Set_SVE_VL_816 pass
9044 11:44:59.151958 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
9045 11:44:59.152083 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
9046 11:44:59.152200 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
9047 11:44:59.152315 arm64_sve-ptrace_Set_SVE_VL_832 pass
9048 11:44:59.155765 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
9049 11:44:59.156253 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
9050 11:44:59.156453 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
9051 11:44:59.156658 arm64_sve-ptrace_Set_SVE_VL_848 pass
9052 11:44:59.156871 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
9053 11:44:59.157109 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
9054 11:44:59.157342 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
9055 11:44:59.157536 arm64_sve-ptrace_Set_SVE_VL_864 pass
9056 11:44:59.157724 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
9057 11:44:59.157888 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
9058 11:44:59.158048 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
9059 11:44:59.158206 arm64_sve-ptrace_Set_SVE_VL_880 pass
9060 11:44:59.158363 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
9061 11:44:59.158553 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
9062 11:44:59.158742 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
9063 11:44:59.158948 arm64_sve-ptrace_Set_SVE_VL_896 pass
9064 11:44:59.159121 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
9065 11:44:59.159274 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
9066 11:44:59.159421 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
9067 11:44:59.159588 arm64_sve-ptrace_Set_SVE_VL_912 pass
9068 11:44:59.159763 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
9069 11:44:59.159900 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
9070 11:44:59.160018 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
9071 11:44:59.160134 arm64_sve-ptrace_Set_SVE_VL_928 pass
9072 11:44:59.160248 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
9073 11:44:59.160362 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
9074 11:44:59.160475 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
9075 11:44:59.160588 arm64_sve-ptrace_Set_SVE_VL_944 pass
9076 11:44:59.160732 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
9077 11:44:59.160855 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
9078 11:44:59.160971 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
9079 11:44:59.161088 arm64_sve-ptrace_Set_SVE_VL_960 pass
9080 11:44:59.163693 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
9081 11:44:59.164012 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
9082 11:44:59.164117 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
9083 11:44:59.164205 arm64_sve-ptrace_Set_SVE_VL_976 pass
9084 11:44:59.164304 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
9085 11:44:59.164407 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
9086 11:44:59.164699 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
9087 11:44:59.164805 arm64_sve-ptrace_Set_SVE_VL_992 pass
9088 11:44:59.164905 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
9089 11:44:59.164990 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
9090 11:44:59.165088 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
9091 11:44:59.165173 arm64_sve-ptrace_Set_SVE_VL_1008 pass
9092 11:44:59.165467 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
9093 11:44:59.165571 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
9094 11:44:59.165680 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
9095 11:44:59.165767 arm64_sve-ptrace_Set_SVE_VL_1024 pass
9096 11:44:59.165861 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
9097 11:44:59.165959 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
9098 11:44:59.166251 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
9099 11:44:59.166352 arm64_sve-ptrace_Set_SVE_VL_1040 pass
9100 11:44:59.166438 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
9101 11:44:59.166539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
9102 11:44:59.166625 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
9103 11:44:59.166717 arm64_sve-ptrace_Set_SVE_VL_1056 pass
9104 11:44:59.166807 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
9105 11:44:59.167094 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
9106 11:44:59.167206 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
9107 11:44:59.167285 arm64_sve-ptrace_Set_SVE_VL_1072 pass
9108 11:44:59.167372 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
9109 11:44:59.167459 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
9110 11:44:59.171716 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
9111 11:44:59.172262 arm64_sve-ptrace_Set_SVE_VL_1088 pass
9112 11:44:59.172459 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
9113 11:44:59.172588 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
9114 11:44:59.172709 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
9115 11:44:59.172869 arm64_sve-ptrace_Set_SVE_VL_1104 pass
9116 11:44:59.185119 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
9117 11:44:59.185460 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
9118 11:44:59.185923 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
9119 11:44:59.186028 arm64_sve-ptrace_Set_SVE_VL_1120 pass
9120 11:44:59.186117 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
9121 11:44:59.186200 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
9122 11:44:59.186281 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
9123 11:44:59.186363 arm64_sve-ptrace_Set_SVE_VL_1136 pass
9124 11:44:59.186443 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
9125 11:44:59.186543 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
9126 11:44:59.186628 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
9127 11:44:59.186707 arm64_sve-ptrace_Set_SVE_VL_1152 pass
9128 11:44:59.186788 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
9129 11:44:59.186868 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
9130 11:44:59.186968 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
9131 11:44:59.187046 arm64_sve-ptrace_Set_SVE_VL_1168 pass
9132 11:44:59.187120 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
9133 11:44:59.187208 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
9134 11:44:59.187297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
9135 11:44:59.187384 arm64_sve-ptrace_Set_SVE_VL_1184 pass
9136 11:44:59.187695 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
9137 11:44:59.187897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
9138 11:44:59.188260 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
9139 11:44:59.188401 arm64_sve-ptrace_Set_SVE_VL_1200 pass
9140 11:44:59.188560 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
9141 11:44:59.188697 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
9142 11:44:59.188846 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
9143 11:44:59.188985 arm64_sve-ptrace_Set_SVE_VL_1216 pass
9144 11:44:59.189140 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
9145 11:44:59.189277 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
9146 11:44:59.189430 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
9147 11:44:59.189587 arm64_sve-ptrace_Set_SVE_VL_1232 pass
9148 11:44:59.189759 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
9149 11:44:59.189919 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
9150 11:44:59.190072 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
9151 11:44:59.190229 arm64_sve-ptrace_Set_SVE_VL_1248 pass
9152 11:44:59.190385 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
9153 11:44:59.190538 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
9154 11:44:59.190691 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
9155 11:44:59.190843 arm64_sve-ptrace_Set_SVE_VL_1264 pass
9156 11:44:59.190996 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
9157 11:44:59.191359 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
9158 11:44:59.191502 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
9159 11:44:59.191654 arm64_sve-ptrace_Set_SVE_VL_1280 pass
9160 11:44:59.199856 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
9161 11:44:59.200499 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
9162 11:44:59.200754 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
9163 11:44:59.200978 arm64_sve-ptrace_Set_SVE_VL_1296 pass
9164 11:44:59.201202 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
9165 11:44:59.201532 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
9166 11:44:59.201779 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
9167 11:44:59.202048 arm64_sve-ptrace_Set_SVE_VL_1312 pass
9168 11:44:59.202281 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
9169 11:44:59.202492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
9170 11:44:59.202700 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
9171 11:44:59.202881 arm64_sve-ptrace_Set_SVE_VL_1328 pass
9172 11:44:59.203084 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
9173 11:44:59.203304 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
9174 11:44:59.203449 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
9175 11:44:59.203617 arm64_sve-ptrace_Set_SVE_VL_1344 pass
9176 11:44:59.203781 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
9177 11:44:59.203906 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
9178 11:44:59.204022 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
9179 11:44:59.204141 arm64_sve-ptrace_Set_SVE_VL_1360 pass
9180 11:44:59.204256 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
9181 11:44:59.204371 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
9182 11:44:59.204486 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
9183 11:44:59.204601 arm64_sve-ptrace_Set_SVE_VL_1376 pass
9184 11:44:59.204716 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
9185 11:44:59.204830 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
9186 11:44:59.204973 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
9187 11:44:59.205098 arm64_sve-ptrace_Set_SVE_VL_1392 pass
9188 11:44:59.207830 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
9189 11:44:59.208103 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
9190 11:44:59.208579 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
9191 11:44:59.208822 arm64_sve-ptrace_Set_SVE_VL_1408 pass
9192 11:44:59.209044 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
9193 11:44:59.209278 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9194 11:44:59.209566 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9195 11:44:59.209813 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9196 11:44:59.209991 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9197 11:44:59.210190 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9198 11:44:59.210393 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9199 11:44:59.210585 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9200 11:44:59.210786 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9201 11:44:59.210962 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9202 11:44:59.211132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9203 11:44:59.211296 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9204 11:44:59.211512 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9205 11:44:59.211668 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9206 11:44:59.211788 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9207 11:44:59.211903 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9208 11:44:59.212018 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9209 11:44:59.212163 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9210 11:44:59.212284 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9211 11:44:59.212399 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9212 11:44:59.212513 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9213 11:44:59.212627 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9214 11:44:59.212740 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9215 11:44:59.215894 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9216 11:44:59.216195 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9217 11:44:59.216690 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9218 11:44:59.216889 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9219 11:44:59.217104 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9220 11:44:59.217309 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9221 11:44:59.217506 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9222 11:44:59.217770 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9223 11:44:59.217963 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9224 11:44:59.218152 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9225 11:44:59.218317 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9226 11:44:59.218468 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9227 11:44:59.218630 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9228 11:44:59.218788 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9229 11:44:59.218933 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9230 11:44:59.219119 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9231 11:44:59.219409 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9232 11:44:59.219568 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9233 11:44:59.219719 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9234 11:44:59.219878 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9235 11:44:59.220028 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9236 11:44:59.220177 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9237 11:44:59.220323 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9238 11:44:59.220468 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9239 11:44:59.220643 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9240 11:44:59.220797 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9241 11:44:59.220956 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9242 11:44:59.221102 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9243 11:44:59.221899 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9244 11:44:59.222010 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9245 11:44:59.222106 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9246 11:44:59.222211 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9247 11:44:59.222297 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9248 11:44:59.222386 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9249 11:44:59.222489 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9250 11:44:59.222585 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9251 11:44:59.222676 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9252 11:44:59.222774 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9253 11:44:59.222885 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9254 11:44:59.222991 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9255 11:44:59.223091 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9256 11:44:59.223185 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9257 11:44:59.223279 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9258 11:44:59.223369 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9259 11:44:59.223447 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9260 11:44:59.223715 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9261 11:44:59.223809 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9262 11:44:59.223877 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9263 11:44:59.223945 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9264 11:44:59.224006 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9265 11:44:59.224067 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9266 11:44:59.224134 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9267 11:44:59.224194 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9268 11:44:59.224256 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9269 11:44:59.224315 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9270 11:44:59.231941 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9271 11:44:59.232176 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9272 11:44:59.232462 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9273 11:44:59.232567 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9274 11:44:59.232655 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9275 11:44:59.232743 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9276 11:44:59.255341 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9277 11:44:59.255574 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9278 11:44:59.255901 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9279 11:44:59.256006 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9280 11:44:59.256094 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9281 11:44:59.256196 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9282 11:44:59.256302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9283 11:44:59.256404 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9284 11:44:59.256706 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9285 11:44:59.256812 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9286 11:44:59.256918 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9287 11:44:59.257008 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9288 11:44:59.257107 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9289 11:44:59.257409 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9290 11:44:59.257514 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9291 11:44:59.257612 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9292 11:44:59.257709 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9293 11:44:59.257806 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9294 11:44:59.258122 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9295 11:44:59.258233 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9296 11:44:59.258352 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9297 11:44:59.258459 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9298 11:44:59.258554 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9299 11:44:59.258663 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9300 11:44:59.258772 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9301 11:44:59.259081 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9302 11:44:59.259184 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9303 11:44:59.259286 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9304 11:44:59.259387 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9305 11:44:59.259479 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9306 11:44:59.264013 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9307 11:44:59.264207 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9308 11:44:59.264321 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9309 11:44:59.264421 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9310 11:44:59.264636 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9311 11:44:59.264757 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9312 11:44:59.264875 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9313 11:44:59.264997 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9314 11:44:59.265151 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9315 11:44:59.265267 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9316 11:44:59.265384 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9317 11:44:59.265509 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9318 11:44:59.265614 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9319 11:44:59.265720 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9320 11:44:59.265823 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9321 11:44:59.265913 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9322 11:44:59.266188 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9323 11:44:59.266285 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9324 11:44:59.266376 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9325 11:44:59.266477 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9326 11:44:59.266579 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9327 11:44:59.266668 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9328 11:44:59.266769 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9329 11:44:59.266872 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9330 11:44:59.267173 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9331 11:44:59.267281 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9332 11:44:59.267384 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9333 11:44:59.267473 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9334 11:44:59.267580 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9335 11:44:59.271902 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9336 11:44:59.272109 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9337 11:44:59.272232 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9338 11:44:59.272341 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9339 11:44:59.272463 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9340 11:44:59.272775 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9341 11:44:59.272879 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9342 11:44:59.272980 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9343 11:44:59.273079 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9344 11:44:59.273175 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9345 11:44:59.273282 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9346 11:44:59.273581 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9347 11:44:59.273700 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9348 11:44:59.273820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9349 11:44:59.273930 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9350 11:44:59.274031 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9351 11:44:59.274117 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9352 11:44:59.274407 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9353 11:44:59.274526 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9354 11:44:59.274627 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9355 11:44:59.274918 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9356 11:44:59.275024 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9357 11:44:59.275124 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9358 11:44:59.275226 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9359 11:44:59.275328 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9360 11:44:59.275433 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9361 11:44:59.279836 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9362 11:44:59.280268 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9363 11:44:59.280366 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9364 11:44:59.280443 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9365 11:44:59.280519 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9366 11:44:59.280606 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9367 11:44:59.280887 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9368 11:44:59.280995 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9369 11:44:59.281127 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9370 11:44:59.281243 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9371 11:44:59.281322 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9372 11:44:59.281413 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9373 11:44:59.281490 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9374 11:44:59.281564 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9375 11:44:59.281640 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9376 11:44:59.281722 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9377 11:44:59.281810 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9378 11:44:59.281885 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9379 11:44:59.281957 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9380 11:44:59.282029 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9381 11:44:59.282119 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9382 11:44:59.282195 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9383 11:44:59.282290 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9384 11:44:59.282369 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9385 11:44:59.282657 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9386 11:44:59.282751 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9387 11:44:59.282826 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9388 11:44:59.282922 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9389 11:44:59.283001 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9390 11:44:59.283078 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9391 11:44:59.283180 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9392 11:44:59.283267 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9393 11:44:59.283350 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9394 11:44:59.283451 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9395 11:44:59.283538 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9396 11:44:59.283645 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9397 11:44:59.283731 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9398 11:44:59.283815 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9399 11:44:59.283913 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9400 11:44:59.287877 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9401 11:44:59.288274 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9402 11:44:59.288376 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9403 11:44:59.288476 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9404 11:44:59.288575 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9405 11:44:59.288934 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9406 11:44:59.289038 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9407 11:44:59.289136 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9408 11:44:59.289222 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9409 11:44:59.289316 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9410 11:44:59.289404 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9411 11:44:59.289490 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9412 11:44:59.289769 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9413 11:44:59.289875 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9414 11:44:59.290156 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9415 11:44:59.290251 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9416 11:44:59.290346 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9417 11:44:59.290437 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9418 11:44:59.290719 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9419 11:44:59.290824 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9420 11:44:59.290927 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9421 11:44:59.291013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9422 11:44:59.291109 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9423 11:44:59.291192 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9424 11:44:59.291290 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9425 11:44:59.291389 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9426 11:44:59.295727 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9427 11:44:59.296125 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9428 11:44:59.296229 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9429 11:44:59.296317 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9430 11:44:59.296416 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9431 11:44:59.296496 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9432 11:44:59.296576 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9433 11:44:59.296668 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9434 11:44:59.296762 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9435 11:44:59.296851 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9436 11:44:59.312571 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9437 11:44:59.312818 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9438 11:44:59.313119 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9439 11:44:59.313219 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9440 11:44:59.313302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9441 11:44:59.313376 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9442 11:44:59.313469 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9443 11:44:59.313545 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9444 11:44:59.313616 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9445 11:44:59.313710 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9446 11:44:59.313786 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9447 11:44:59.313863 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9448 11:44:59.313947 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9449 11:44:59.314033 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9450 11:44:59.314317 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9451 11:44:59.314413 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9452 11:44:59.314503 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9453 11:44:59.314880 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9454 11:44:59.315108 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9455 11:44:59.315296 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9456 11:44:59.315487 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9457 11:44:59.315645 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9458 11:44:59.315827 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9459 11:44:59.315976 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9460 11:44:59.316096 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9461 11:44:59.319848 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9462 11:44:59.320264 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9463 11:44:59.320372 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9464 11:44:59.320455 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9465 11:44:59.320539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9466 11:44:59.320636 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9467 11:44:59.320720 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9468 11:44:59.320814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9469 11:44:59.320897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9470 11:44:59.321457 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9471 11:44:59.321680 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9472 11:44:59.321818 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9473 11:44:59.321976 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9474 11:44:59.322345 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9475 11:44:59.322512 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9476 11:44:59.322651 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9477 11:44:59.322826 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9478 11:44:59.322973 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9479 11:44:59.323116 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9480 11:44:59.323259 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9481 11:44:59.323441 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9482 11:44:59.323597 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9483 11:44:59.323753 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9484 11:44:59.323917 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9485 11:44:59.324045 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9486 11:44:59.324162 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9487 11:44:59.324278 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9488 11:44:59.324424 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9489 11:44:59.327778 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9490 11:44:59.328264 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9491 11:44:59.328446 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9492 11:44:59.328619 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9493 11:44:59.328764 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9494 11:44:59.328955 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9495 11:44:59.329145 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9496 11:44:59.329311 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9497 11:44:59.329475 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9498 11:44:59.329635 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9499 11:44:59.329842 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9500 11:44:59.330005 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9501 11:44:59.330163 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9502 11:44:59.330310 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9503 11:44:59.330432 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9504 11:44:59.330560 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9505 11:44:59.330713 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9506 11:44:59.330863 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9507 11:44:59.331002 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9508 11:44:59.331166 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9509 11:44:59.331337 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9510 11:44:59.331501 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9511 11:44:59.331666 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9512 11:44:59.331842 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9513 11:44:59.331969 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9514 11:44:59.332087 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9515 11:44:59.332205 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9516 11:44:59.332324 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9517 11:44:59.332441 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9518 11:44:59.332557 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9519 11:44:59.335742 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9520 11:44:59.336164 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9521 11:44:59.336269 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9522 11:44:59.336361 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9523 11:44:59.336443 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9524 11:44:59.336542 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9525 11:44:59.336624 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9526 11:44:59.336707 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9527 11:44:59.336807 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9528 11:44:59.337093 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9529 11:44:59.337195 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9530 11:44:59.337405 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9531 11:44:59.337497 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9532 11:44:59.337581 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9533 11:44:59.337689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9534 11:44:59.337773 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9535 11:44:59.337870 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9536 11:44:59.337966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9537 11:44:59.338113 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9538 11:44:59.338223 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9539 11:44:59.338325 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9540 11:44:59.338430 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9541 11:44:59.338527 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9542 11:44:59.338626 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9543 11:44:59.338723 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9544 11:44:59.339045 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9545 11:44:59.339152 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9546 11:44:59.339252 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9547 11:44:59.339339 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9548 11:44:59.339442 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9549 11:44:59.339541 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9550 11:44:59.343890 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9551 11:44:59.344108 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9552 11:44:59.344191 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9553 11:44:59.344485 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9554 11:44:59.344588 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9555 11:44:59.344667 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9556 11:44:59.344743 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9557 11:44:59.344820 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9558 11:44:59.344915 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9559 11:44:59.344998 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9560 11:44:59.345081 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9561 11:44:59.345166 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9562 11:44:59.345265 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9563 11:44:59.345342 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9564 11:44:59.345414 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9565 11:44:59.345698 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9566 11:44:59.345793 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9567 11:44:59.345881 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9568 11:44:59.345956 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9569 11:44:59.346042 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9570 11:44:59.346138 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9571 11:44:59.346227 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9572 11:44:59.346548 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9573 11:44:59.346696 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9574 11:44:59.346798 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9575 11:44:59.346885 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9576 11:44:59.347112 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9577 11:44:59.347209 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9578 11:44:59.347309 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9579 11:44:59.347400 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9580 11:44:59.347499 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9581 11:44:59.351723 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9582 11:44:59.352172 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9583 11:44:59.352276 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9584 11:44:59.352369 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9585 11:44:59.352474 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9586 11:44:59.352564 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9587 11:44:59.352664 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9588 11:44:59.352753 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9589 11:44:59.352851 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9590 11:44:59.352935 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9591 11:44:59.353032 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9592 11:44:59.353130 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9593 11:44:59.353434 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9594 11:44:59.353539 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9595 11:44:59.353641 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9596 11:44:59.367524 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9597 11:44:59.367763 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9598 11:44:59.368062 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9599 11:44:59.368163 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9600 11:44:59.368252 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9601 11:44:59.368338 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9602 11:44:59.368445 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9603 11:44:59.368531 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9604 11:44:59.368614 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9605 11:44:59.368714 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9606 11:44:59.368799 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9607 11:44:59.368896 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9608 11:44:59.368981 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9609 11:44:59.369078 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9610 11:44:59.369175 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9611 11:44:59.369472 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9612 11:44:59.369603 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9613 11:44:59.369712 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9614 11:44:59.369800 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9615 11:44:59.369975 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9616 11:44:59.370080 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9617 11:44:59.370174 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9618 11:44:59.370464 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9619 11:44:59.370560 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9620 11:44:59.370647 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9621 11:44:59.370724 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9622 11:44:59.370818 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9623 11:44:59.370905 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9624 11:44:59.370996 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9625 11:44:59.371319 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9626 11:44:59.373669 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9627 11:44:59.373799 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9628 11:44:59.373898 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9629 11:44:59.375681 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9630 11:44:59.376033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9631 11:44:59.376132 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9632 11:44:59.376226 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9633 11:44:59.376328 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9634 11:44:59.376414 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9635 11:44:59.376508 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9636 11:44:59.376604 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9637 11:44:59.376699 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9638 11:44:59.376795 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9639 11:44:59.376890 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9640 11:44:59.376987 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9641 11:44:59.377277 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9642 11:44:59.377419 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9643 11:44:59.377502 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9644 11:44:59.377596 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9645 11:44:59.377689 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9646 11:44:59.377794 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9647 11:44:59.377880 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9648 11:44:59.377976 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9649 11:44:59.378073 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9650 11:44:59.378377 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9651 11:44:59.378544 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9652 11:44:59.378702 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9653 11:44:59.378840 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9654 11:44:59.378931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9655 11:44:59.379030 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9656 11:44:59.379115 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9657 11:44:59.379194 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9658 11:44:59.379288 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9659 11:44:59.379373 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9660 11:44:59.379474 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9661 11:44:59.383940 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9662 11:44:59.384192 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9663 11:44:59.384505 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9664 11:44:59.384609 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9665 11:44:59.384698 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9666 11:44:59.384784 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9667 11:44:59.384871 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9668 11:44:59.384973 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9669 11:44:59.385061 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9670 11:44:59.385146 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9671 11:44:59.385248 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9672 11:44:59.385336 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9673 11:44:59.385437 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9674 11:44:59.385539 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9675 11:44:59.385987 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9676 11:44:59.386084 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9677 11:44:59.386360 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9678 11:44:59.386452 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9679 11:44:59.386534 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9680 11:44:59.386630 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9681 11:44:59.386713 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9682 11:44:59.386800 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9683 11:44:59.386889 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9684 11:44:59.387160 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9685 11:44:59.387429 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9686 11:44:59.387511 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9687 11:44:59.387590 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9688 11:44:59.391864 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9689 11:44:59.392338 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9690 11:44:59.392445 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9691 11:44:59.392533 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9692 11:44:59.392614 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9693 11:44:59.392712 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9694 11:44:59.392795 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9695 11:44:59.392902 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9696 11:44:59.393003 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9697 11:44:59.393291 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9698 11:44:59.393392 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9699 11:44:59.393488 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9700 11:44:59.393595 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9701 11:44:59.393922 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9702 11:44:59.394202 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9703 11:44:59.394485 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9704 11:44:59.394574 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9705 11:44:59.394656 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9706 11:44:59.394751 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9707 11:44:59.394850 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9708 11:44:59.394946 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9709 11:44:59.395045 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9710 11:44:59.395329 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9711 11:44:59.395421 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9712 11:44:59.395521 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9713 11:44:59.395621 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9714 11:44:59.399926 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9715 11:44:59.400139 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9716 11:44:59.400422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9717 11:44:59.400521 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9718 11:44:59.400599 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9719 11:44:59.400675 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9720 11:44:59.400764 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9721 11:44:59.400852 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9722 11:44:59.400939 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9723 11:44:59.401209 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9724 11:44:59.401289 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9725 11:44:59.401560 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9726 11:44:59.401640 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9727 11:44:59.401737 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9728 11:44:59.401825 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9729 11:44:59.402096 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9730 11:44:59.402177 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9731 11:44:59.402264 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9732 11:44:59.402340 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9733 11:44:59.402606 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9734 11:44:59.402685 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9735 11:44:59.402772 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9736 11:44:59.403016 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9737 11:44:59.403111 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9738 11:44:59.403177 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9739 11:44:59.403255 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9740 11:44:59.403351 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9741 11:44:59.403447 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9742 11:44:59.407968 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9743 11:44:59.408144 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9744 11:44:59.408245 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9745 11:44:59.408330 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9746 11:44:59.408820 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9747 11:44:59.409208 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9748 11:44:59.409301 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9749 11:44:59.409386 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9750 11:44:59.409675 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9751 11:44:59.409776 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9752 11:44:59.409860 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9753 11:44:59.409940 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9754 11:44:59.410019 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9755 11:44:59.410100 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9756 11:44:59.424259 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9757 11:44:59.424499 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9758 11:44:59.424754 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9759 11:44:59.424866 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9760 11:44:59.424940 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9761 11:44:59.425038 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9762 11:44:59.425156 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9763 11:44:59.425259 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9764 11:44:59.425338 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9765 11:44:59.425420 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9766 11:44:59.425530 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9767 11:44:59.425626 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9768 11:44:59.425741 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9769 11:44:59.425849 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9770 11:44:59.425955 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9771 11:44:59.426056 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9772 11:44:59.426353 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9773 11:44:59.426459 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9774 11:44:59.426583 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9775 11:44:59.426884 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9776 11:44:59.426995 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9777 11:44:59.427127 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9778 11:44:59.427235 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9779 11:44:59.427363 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9780 11:44:59.427457 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9781 11:44:59.427563 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9782 11:44:59.431761 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9783 11:44:59.432210 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9784 11:44:59.432355 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9785 11:44:59.432472 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9786 11:44:59.432577 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9787 11:44:59.432697 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9788 11:44:59.432791 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9789 11:44:59.432899 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9790 11:44:59.433022 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9791 11:44:59.433116 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9792 11:44:59.433225 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9793 11:44:59.433488 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9794 11:44:59.433576 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9795 11:44:59.433665 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9796 11:44:59.433739 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9797 11:44:59.433819 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9798 11:44:59.433883 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9799 11:44:59.433961 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9800 11:44:59.434055 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9801 11:44:59.434322 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9802 11:44:59.434423 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9803 11:44:59.434518 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9804 11:44:59.434611 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9805 11:44:59.434871 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9806 11:44:59.434955 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9807 11:44:59.435208 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9808 11:44:59.435289 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9809 11:44:59.435544 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9810 11:44:59.439701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9811 11:44:59.440054 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9812 11:44:59.440160 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9813 11:44:59.440247 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9814 11:44:59.440345 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9815 11:44:59.440430 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9816 11:44:59.440527 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9817 11:44:59.440834 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9818 11:44:59.440978 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9819 11:44:59.441096 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9820 11:44:59.441189 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9821 11:44:59.441292 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9822 11:44:59.441377 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9823 11:44:59.441477 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9824 11:44:59.441834 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9825 11:44:59.441941 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9826 11:44:59.442031 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9827 11:44:59.442113 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9828 11:44:59.442198 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9829 11:44:59.442299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9830 11:44:59.442384 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9831 11:44:59.442466 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9832 11:44:59.442567 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9833 11:44:59.442659 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9834 11:44:59.442743 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9835 11:44:59.442827 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9836 11:44:59.442927 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9837 11:44:59.443013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9838 11:44:59.443113 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9839 11:44:59.443214 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9840 11:44:59.443313 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9841 11:44:59.443412 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9842 11:44:59.447758 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9843 11:44:59.448194 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9844 11:44:59.448295 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9845 11:44:59.448379 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9846 11:44:59.448459 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9847 11:44:59.448554 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9848 11:44:59.448634 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9849 11:44:59.448711 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9850 11:44:59.448803 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9851 11:44:59.448880 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9852 11:44:59.448972 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9853 11:44:59.449068 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9854 11:44:59.449357 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9855 11:44:59.449470 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9856 11:44:59.449589 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9857 11:44:59.449699 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9858 11:44:59.450017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9859 11:44:59.450119 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9860 11:44:59.450211 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9861 11:44:59.450313 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9862 11:44:59.450430 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9863 11:44:59.450534 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9864 11:44:59.450636 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9865 11:44:59.450754 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9866 11:44:59.450859 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9867 11:44:59.450960 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9868 11:44:59.451059 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9869 11:44:59.451165 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9870 11:44:59.451247 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9871 11:44:59.451325 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9872 11:44:59.451417 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9873 11:44:59.451489 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9874 11:44:59.451555 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9875 11:44:59.455758 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9876 11:44:59.456184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9877 11:44:59.456289 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9878 11:44:59.456377 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9879 11:44:59.456472 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9880 11:44:59.456556 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9881 11:44:59.456653 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9882 11:44:59.456740 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9883 11:44:59.456842 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9884 11:44:59.456946 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9885 11:44:59.457048 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9886 11:44:59.457150 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9887 11:44:59.457261 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9888 11:44:59.457364 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9889 11:44:59.457472 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9890 11:44:59.457839 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9891 11:44:59.457952 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9892 11:44:59.458057 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9893 11:44:59.458148 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9894 11:44:59.458285 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9895 11:44:59.458375 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9896 11:44:59.458698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9897 11:44:59.458860 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9898 11:44:59.458956 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9899 11:44:59.459058 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9900 11:44:59.459158 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9901 11:44:59.459243 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9902 11:44:59.459348 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9903 11:44:59.459420 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9904 11:44:59.459509 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9905 11:44:59.463681 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9906 11:44:59.464054 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9907 11:44:59.464177 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9908 11:44:59.464302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9909 11:44:59.464448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9910 11:44:59.464575 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9911 11:44:59.464705 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9912 11:44:59.464808 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9913 11:44:59.464891 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9914 11:44:59.464956 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9915 11:44:59.465018 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9916 11:44:59.478429 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9917 11:44:59.478674 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9918 11:44:59.478986 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9919 11:44:59.479081 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9920 11:44:59.479158 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9921 11:44:59.479229 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9922 11:44:59.479307 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9923 11:44:59.479409 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9924 11:44:59.479495 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9925 11:44:59.479584 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9926 11:44:59.479689 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9927 11:44:59.479795 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9928 11:44:59.479902 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9929 11:44:59.480287 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9930 11:44:59.480392 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9931 11:44:59.480676 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9932 11:44:59.480781 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9933 11:44:59.480860 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9934 11:44:59.481235 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9935 11:44:59.481445 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9936 11:44:59.481589 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9937 11:44:59.481764 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9938 11:44:59.481910 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9939 11:44:59.482059 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9940 11:44:59.482488 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9941 11:44:59.482692 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9942 11:44:59.482864 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9943 11:44:59.483011 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9944 11:44:59.483157 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9945 11:44:59.483359 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9946 11:44:59.483580 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9947 11:44:59.483773 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9948 11:44:59.483936 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
9949 11:44:59.484055 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
9950 11:44:59.484169 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
9951 11:44:59.484280 arm64_sve-ptrace_Set_SVE_VL_4448 pass
9952 11:44:59.484424 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
9953 11:44:59.484544 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
9954 11:44:59.484658 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
9955 11:44:59.484776 arm64_sve-ptrace_Set_SVE_VL_4464 pass
9956 11:44:59.484890 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
9957 11:44:59.485003 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
9958 11:44:59.485116 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
9959 11:44:59.485230 arm64_sve-ptrace_Set_SVE_VL_4480 pass
9960 11:44:59.485342 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
9961 11:44:59.487888 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
9962 11:44:59.488413 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
9963 11:44:59.488640 arm64_sve-ptrace_Set_SVE_VL_4496 pass
9964 11:44:59.488845 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
9965 11:44:59.489016 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
9966 11:44:59.489188 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
9967 11:44:59.489408 arm64_sve-ptrace_Set_SVE_VL_4512 pass
9968 11:44:59.489621 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
9969 11:44:59.489843 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
9970 11:44:59.490062 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
9971 11:44:59.490315 arm64_sve-ptrace_Set_SVE_VL_4528 pass
9972 11:44:59.490515 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
9973 11:44:59.490694 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
9974 11:44:59.490935 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
9975 11:44:59.491165 arm64_sve-ptrace_Set_SVE_VL_4544 pass
9976 11:44:59.491458 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
9977 11:44:59.491633 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
9978 11:44:59.491767 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
9979 11:44:59.491890 arm64_sve-ptrace_Set_SVE_VL_4560 pass
9980 11:44:59.492010 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
9981 11:44:59.492127 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
9982 11:44:59.492243 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
9983 11:44:59.492359 arm64_sve-ptrace_Set_SVE_VL_4576 pass
9984 11:44:59.492474 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
9985 11:44:59.492590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
9986 11:44:59.492706 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
9987 11:44:59.492819 arm64_sve-ptrace_Set_SVE_VL_4592 pass
9988 11:44:59.492933 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
9989 11:44:59.493079 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
9990 11:44:59.493201 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
9991 11:44:59.493318 arm64_sve-ptrace_Set_SVE_VL_4608 pass
9992 11:44:59.493434 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
9993 11:44:59.493549 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
9994 11:44:59.495816 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
9995 11:44:59.496168 arm64_sve-ptrace_Set_SVE_VL_4624 pass
9996 11:44:59.496264 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
9997 11:44:59.496357 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
9998 11:44:59.496444 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
9999 11:44:59.496544 arm64_sve-ptrace_Set_SVE_VL_4640 pass
10000 11:44:59.496645 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
10001 11:44:59.496938 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
10002 11:44:59.497035 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
10003 11:44:59.497137 arm64_sve-ptrace_Set_SVE_VL_4656 pass
10004 11:44:59.497249 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
10005 11:44:59.497355 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
10006 11:44:59.497674 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
10007 11:44:59.497766 arm64_sve-ptrace_Set_SVE_VL_4672 pass
10008 11:44:59.497851 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
10009 11:44:59.497936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
10010 11:44:59.498023 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
10011 11:44:59.498300 arm64_sve-ptrace_Set_SVE_VL_4688 pass
10012 11:44:59.498594 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
10013 11:44:59.498692 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
10014 11:44:59.498783 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
10015 11:44:59.498860 arm64_sve-ptrace_Set_SVE_VL_4704 pass
10016 11:44:59.499144 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
10017 11:44:59.499236 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
10018 11:44:59.499323 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
10019 11:44:59.499401 arm64_sve-ptrace_Set_SVE_VL_4720 pass
10020 11:44:59.499487 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
10021 11:44:59.503785 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
10022 11:44:59.504220 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
10023 11:44:59.504331 arm64_sve-ptrace_Set_SVE_VL_4736 pass
10024 11:44:59.504420 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
10025 11:44:59.504523 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
10026 11:44:59.504611 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
10027 11:44:59.504712 arm64_sve-ptrace_Set_SVE_VL_4752 pass
10028 11:44:59.504800 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
10029 11:44:59.505132 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
10030 11:44:59.505242 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
10031 11:44:59.505344 arm64_sve-ptrace_Set_SVE_VL_4768 pass
10032 11:44:59.505431 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
10033 11:44:59.505530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
10034 11:44:59.505630 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
10035 11:44:59.505734 arm64_sve-ptrace_Set_SVE_VL_4784 pass
10036 11:44:59.505829 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
10037 11:44:59.506048 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
10038 11:44:59.506155 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
10039 11:44:59.506247 arm64_sve-ptrace_Set_SVE_VL_4800 pass
10040 11:44:59.506525 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
10041 11:44:59.506825 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
10042 11:44:59.506918 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
10043 11:44:59.506992 arm64_sve-ptrace_Set_SVE_VL_4816 pass
10044 11:44:59.507077 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
10045 11:44:59.507165 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
10046 11:44:59.507252 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
10047 11:44:59.507340 arm64_sve-ptrace_Set_SVE_VL_4832 pass
10048 11:44:59.507634 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
10049 11:44:59.511890 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
10050 11:44:59.512001 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
10051 11:44:59.512290 arm64_sve-ptrace_Set_SVE_VL_4848 pass
10052 11:44:59.512396 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
10053 11:44:59.512499 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
10054 11:44:59.512589 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
10055 11:44:59.512674 arm64_sve-ptrace_Set_SVE_VL_4864 pass
10056 11:44:59.512773 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
10057 11:44:59.512859 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
10058 11:44:59.513155 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
10059 11:44:59.513254 arm64_sve-ptrace_Set_SVE_VL_4880 pass
10060 11:44:59.513348 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
10061 11:44:59.513426 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
10062 11:44:59.513728 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
10063 11:44:59.513822 arm64_sve-ptrace_Set_SVE_VL_4896 pass
10064 11:44:59.513899 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
10065 11:44:59.513988 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
10066 11:44:59.514079 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
10067 11:44:59.514354 arm64_sve-ptrace_Set_SVE_VL_4912 pass
10068 11:44:59.514460 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
10069 11:44:59.514563 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
10070 11:44:59.514665 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
10071 11:44:59.514771 arm64_sve-ptrace_Set_SVE_VL_4928 pass
10072 11:44:59.514858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
10073 11:44:59.514959 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
10074 11:44:59.515062 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
10075 11:44:59.515162 arm64_sve-ptrace_Set_SVE_VL_4944 pass
10076 11:44:59.540074 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
10077 11:44:59.540591 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
10078 11:44:59.540702 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
10079 11:44:59.540795 arm64_sve-ptrace_Set_SVE_VL_4960 pass
10080 11:44:59.540886 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
10081 11:44:59.540972 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
10082 11:44:59.541075 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
10083 11:44:59.541164 arm64_sve-ptrace_Set_SVE_VL_4976 pass
10084 11:44:59.541245 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
10085 11:44:59.541334 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
10086 11:44:59.541411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
10087 11:44:59.541496 arm64_sve-ptrace_Set_SVE_VL_4992 pass
10088 11:44:59.541583 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
10089 11:44:59.541680 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
10090 11:44:59.541986 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
10091 11:44:59.542084 arm64_sve-ptrace_Set_SVE_VL_5008 pass
10092 11:44:59.542175 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
10093 11:44:59.542450 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
10094 11:44:59.542559 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
10095 11:44:59.542646 arm64_sve-ptrace_Set_SVE_VL_5024 pass
10096 11:44:59.542745 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
10097 11:44:59.542832 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
10098 11:44:59.542930 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
10099 11:44:59.543046 arm64_sve-ptrace_Set_SVE_VL_5040 pass
10100 11:44:59.543152 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
10101 11:44:59.543441 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
10102 11:44:59.543535 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
10103 11:44:59.547762 arm64_sve-ptrace_Set_SVE_VL_5056 pass
10104 11:44:59.548198 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
10105 11:44:59.548296 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
10106 11:44:59.548386 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
10107 11:44:59.548474 arm64_sve-ptrace_Set_SVE_VL_5072 pass
10108 11:44:59.548578 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
10109 11:44:59.548667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
10110 11:44:59.548759 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
10111 11:44:59.548865 arm64_sve-ptrace_Set_SVE_VL_5088 pass
10112 11:44:59.548954 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
10113 11:44:59.549038 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
10114 11:44:59.549138 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
10115 11:44:59.549221 arm64_sve-ptrace_Set_SVE_VL_5104 pass
10116 11:44:59.549310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
10117 11:44:59.549398 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
10118 11:44:59.549632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
10119 11:44:59.549724 arm64_sve-ptrace_Set_SVE_VL_5120 pass
10120 11:44:59.549817 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
10121 11:44:59.549905 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
10122 11:44:59.550185 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
10123 11:44:59.550282 arm64_sve-ptrace_Set_SVE_VL_5136 pass
10124 11:44:59.550380 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
10125 11:44:59.550481 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
10126 11:44:59.550580 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
10127 11:44:59.550680 arm64_sve-ptrace_Set_SVE_VL_5152 pass
10128 11:44:59.550784 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
10129 11:44:59.550883 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
10130 11:44:59.551196 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
10131 11:44:59.551301 arm64_sve-ptrace_Set_SVE_VL_5168 pass
10132 11:44:59.551405 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
10133 11:44:59.551493 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
10134 11:44:59.555805 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
10135 11:44:59.556191 arm64_sve-ptrace_Set_SVE_VL_5184 pass
10136 11:44:59.556332 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
10137 11:44:59.556433 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
10138 11:44:59.556536 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
10139 11:44:59.556624 arm64_sve-ptrace_Set_SVE_VL_5200 pass
10140 11:44:59.556714 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
10141 11:44:59.556819 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
10142 11:44:59.556919 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
10143 11:44:59.557019 arm64_sve-ptrace_Set_SVE_VL_5216 pass
10144 11:44:59.557126 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
10145 11:44:59.557224 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
10146 11:44:59.557507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
10147 11:44:59.557600 arm64_sve-ptrace_Set_SVE_VL_5232 pass
10148 11:44:59.557892 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
10149 11:44:59.557983 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
10150 11:44:59.558067 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
10151 11:44:59.558151 arm64_sve-ptrace_Set_SVE_VL_5248 pass
10152 11:44:59.558425 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
10153 11:44:59.558516 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
10154 11:44:59.558599 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
10155 11:44:59.558689 arm64_sve-ptrace_Set_SVE_VL_5264 pass
10156 11:44:59.558981 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
10157 11:44:59.559084 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
10158 11:44:59.559171 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
10159 11:44:59.559255 arm64_sve-ptrace_Set_SVE_VL_5280 pass
10160 11:44:59.559536 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
10161 11:44:59.563826 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
10162 11:44:59.564185 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
10163 11:44:59.564288 arm64_sve-ptrace_Set_SVE_VL_5296 pass
10164 11:44:59.564372 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
10165 11:44:59.564468 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
10166 11:44:59.564553 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
10167 11:44:59.564649 arm64_sve-ptrace_Set_SVE_VL_5312 pass
10168 11:44:59.564749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
10169 11:44:59.564848 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
10170 11:44:59.565143 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
10171 11:44:59.565285 arm64_sve-ptrace_Set_SVE_VL_5328 pass
10172 11:44:59.565390 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
10173 11:44:59.565490 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
10174 11:44:59.565591 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
10175 11:44:59.565701 arm64_sve-ptrace_Set_SVE_VL_5344 pass
10176 11:44:59.566014 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
10177 11:44:59.566200 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
10178 11:44:59.566403 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
10179 11:44:59.566562 arm64_sve-ptrace_Set_SVE_VL_5360 pass
10180 11:44:59.566721 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
10181 11:44:59.566941 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
10182 11:44:59.567123 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
10183 11:44:59.567247 arm64_sve-ptrace_Set_SVE_VL_5376 pass
10184 11:44:59.567364 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
10185 11:44:59.567529 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
10186 11:44:59.567691 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
10187 11:44:59.567864 arm64_sve-ptrace_Set_SVE_VL_5392 pass
10188 11:44:59.568002 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
10189 11:44:59.571764 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
10190 11:44:59.572222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
10191 11:44:59.572456 arm64_sve-ptrace_Set_SVE_VL_5408 pass
10192 11:44:59.572691 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
10193 11:44:59.572896 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10194 11:44:59.573063 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10195 11:44:59.573223 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10196 11:44:59.573414 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10197 11:44:59.573581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10198 11:44:59.573751 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10199 11:44:59.573905 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10200 11:44:59.574052 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10201 11:44:59.574178 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10202 11:44:59.574295 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10203 11:44:59.574410 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10204 11:44:59.574526 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10205 11:44:59.574671 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10206 11:44:59.574791 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10207 11:44:59.574906 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10208 11:44:59.575023 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10209 11:44:59.575172 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10210 11:44:59.575325 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10211 11:44:59.575446 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10212 11:44:59.575573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10213 11:44:59.575732 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10214 11:44:59.575881 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10215 11:44:59.579802 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10216 11:44:59.580196 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10217 11:44:59.580299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10218 11:44:59.580384 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10219 11:44:59.580482 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10220 11:44:59.580579 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10221 11:44:59.580663 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10222 11:44:59.580767 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10223 11:44:59.581011 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10224 11:44:59.581131 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10225 11:44:59.581227 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10226 11:44:59.581414 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10227 11:44:59.581516 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10228 11:44:59.581618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10229 11:44:59.581727 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10230 11:44:59.582016 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10231 11:44:59.582110 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10232 11:44:59.582209 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10233 11:44:59.582309 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10234 11:44:59.582607 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10235 11:44:59.582713 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10236 11:44:59.603403 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10237 11:44:59.603880 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10238 11:44:59.603986 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10239 11:44:59.604070 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10240 11:44:59.604165 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10241 11:44:59.604253 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10242 11:44:59.607672 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10243 11:44:59.607859 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10244 11:44:59.607953 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10245 11:44:59.608024 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10246 11:44:59.608089 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10247 11:44:59.608154 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10248 11:44:59.608218 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10249 11:44:59.608282 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10250 11:44:59.608347 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10251 11:44:59.608410 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10252 11:44:59.608473 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10253 11:44:59.608537 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10254 11:44:59.608599 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10255 11:44:59.608664 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10256 11:44:59.608724 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10257 11:44:59.608785 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10258 11:44:59.608847 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10259 11:44:59.608915 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10260 11:44:59.608976 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10261 11:44:59.609036 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10262 11:44:59.609097 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10263 11:44:59.609159 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10264 11:44:59.609252 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10265 11:44:59.609324 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10266 11:44:59.609386 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10267 11:44:59.611780 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10268 11:44:59.611909 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10269 11:44:59.612198 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10270 11:44:59.612289 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10271 11:44:59.612388 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10272 11:44:59.612476 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10273 11:44:59.612556 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10274 11:44:59.612641 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10275 11:44:59.612705 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10276 11:44:59.612993 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10277 11:44:59.613095 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10278 11:44:59.613219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10279 11:44:59.613340 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10280 11:44:59.613433 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10281 11:44:59.613555 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10282 11:44:59.613634 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10283 11:44:59.613719 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10284 11:44:59.613818 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10285 11:44:59.613948 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10286 11:44:59.614051 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10287 11:44:59.614339 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10288 11:44:59.614441 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10289 11:44:59.614589 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10290 11:44:59.614682 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10291 11:44:59.614754 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10292 11:44:59.614826 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10293 11:44:59.614958 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10294 11:44:59.615132 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10295 11:44:59.615303 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10296 11:44:59.615500 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10297 11:44:59.615628 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10298 11:44:59.615744 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10299 11:44:59.619737 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10300 11:44:59.620115 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10301 11:44:59.620214 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10302 11:44:59.620311 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10303 11:44:59.620400 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10304 11:44:59.620488 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10305 11:44:59.620555 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10306 11:44:59.620632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10307 11:44:59.620732 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10308 11:44:59.620832 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10309 11:44:59.620950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10310 11:44:59.621056 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10311 11:44:59.621190 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10312 11:44:59.621288 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10313 11:44:59.621407 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10314 11:44:59.621528 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10315 11:44:59.621625 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10316 11:44:59.621758 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10317 11:44:59.621887 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10318 11:44:59.622301 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10319 11:44:59.622400 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10320 11:44:59.622481 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10321 11:44:59.622560 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10322 11:44:59.622656 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10323 11:44:59.622744 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10324 11:44:59.622830 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10325 11:44:59.622933 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10326 11:44:59.623015 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10327 11:44:59.623097 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10328 11:44:59.623192 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10329 11:44:59.623278 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10330 11:44:59.623379 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10331 11:44:59.623465 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10332 11:44:59.623549 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10333 11:44:59.627791 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10334 11:44:59.628254 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10335 11:44:59.628358 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10336 11:44:59.628447 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10337 11:44:59.628530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10338 11:44:59.628629 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10339 11:44:59.628714 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10340 11:44:59.628799 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10341 11:44:59.628897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10342 11:44:59.628982 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10343 11:44:59.629084 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10344 11:44:59.629169 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10345 11:44:59.629253 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10346 11:44:59.629351 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10347 11:44:59.629436 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10348 11:44:59.629532 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10349 11:44:59.629628 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10350 11:44:59.629736 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10351 11:44:59.630140 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10352 11:44:59.630244 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10353 11:44:59.630336 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10354 11:44:59.630413 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10355 11:44:59.630501 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10356 11:44:59.630578 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10357 11:44:59.630665 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10358 11:44:59.630949 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10359 11:44:59.631059 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10360 11:44:59.631138 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10361 11:44:59.631224 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10362 11:44:59.631312 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10363 11:44:59.631399 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10364 11:44:59.635688 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10365 11:44:59.636099 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10366 11:44:59.636206 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10367 11:44:59.636293 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10368 11:44:59.636397 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10369 11:44:59.636486 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10370 11:44:59.636572 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10371 11:44:59.636673 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10372 11:44:59.636760 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10373 11:44:59.636861 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10374 11:44:59.636966 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10375 11:44:59.637066 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10376 11:44:59.637372 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10377 11:44:59.637493 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10378 11:44:59.637599 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10379 11:44:59.637778 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10380 11:44:59.637900 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10381 11:44:59.638010 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10382 11:44:59.638112 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10383 11:44:59.638199 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10384 11:44:59.638299 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10385 11:44:59.638408 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10386 11:44:59.638510 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10387 11:44:59.638611 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10388 11:44:59.638928 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10389 11:44:59.639038 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10390 11:44:59.639142 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10391 11:44:59.639231 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10392 11:44:59.639327 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10393 11:44:59.639412 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10394 11:44:59.643759 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10395 11:44:59.643957 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10396 11:44:59.657083 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10397 11:44:59.657553 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10398 11:44:59.657690 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10399 11:44:59.657853 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10400 11:44:59.658012 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10401 11:44:59.658125 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10402 11:44:59.658201 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10403 11:44:59.658273 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10404 11:44:59.658344 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10405 11:44:59.658429 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10406 11:44:59.658500 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10407 11:44:59.658571 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10408 11:44:59.658654 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10409 11:44:59.658738 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10410 11:44:59.658811 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10411 11:44:59.659114 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10412 11:44:59.659206 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10413 11:44:59.659293 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10414 11:44:59.659366 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10415 11:44:59.659450 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10416 11:44:59.659525 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10417 11:44:59.659804 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10418 11:44:59.660203 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10419 11:44:59.660302 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10420 11:44:59.660475 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10421 11:44:59.660556 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10422 11:44:59.660650 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10423 11:44:59.660730 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10424 11:44:59.660802 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10425 11:44:59.660902 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10426 11:44:59.661001 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10427 11:44:59.661075 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10428 11:44:59.661145 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10429 11:44:59.661230 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10430 11:44:59.661303 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10431 11:44:59.661374 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10432 11:44:59.661457 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10433 11:44:59.661529 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10434 11:44:59.661612 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10435 11:44:59.661705 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10436 11:44:59.662168 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10437 11:44:59.662263 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10438 11:44:59.662341 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10439 11:44:59.662413 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10440 11:44:59.662679 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10441 11:44:59.662773 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10442 11:44:59.662847 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10443 11:44:59.662919 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10444 11:44:59.663007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10445 11:44:59.663078 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10446 11:44:59.663166 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10447 11:44:59.663251 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10448 11:44:59.663539 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10449 11:44:59.663632 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10450 11:44:59.668018 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10451 11:44:59.668283 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10452 11:44:59.668422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10453 11:44:59.668583 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10454 11:44:59.669039 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10455 11:44:59.669256 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10456 11:44:59.669423 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10457 11:44:59.669567 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10458 11:44:59.669733 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10459 11:44:59.669856 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10460 11:44:59.669977 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10461 11:44:59.670105 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10462 11:44:59.670293 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10463 11:44:59.670446 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10464 11:44:59.670600 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10465 11:44:59.670741 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10466 11:44:59.670871 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10467 11:44:59.671012 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10468 11:44:59.671168 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10469 11:44:59.671334 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10470 11:44:59.671494 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10471 11:44:59.671621 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10472 11:44:59.671741 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10473 11:44:59.671946 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10474 11:44:59.672085 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10475 11:44:59.672290 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10476 11:44:59.672458 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10477 11:44:59.672649 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10478 11:44:59.672824 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10479 11:44:59.672957 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10480 11:44:59.673105 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10481 11:44:59.673230 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10482 11:44:59.679855 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10483 11:44:59.680163 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10484 11:44:59.680593 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10485 11:44:59.680788 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10486 11:44:59.680979 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10487 11:44:59.681135 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10488 11:44:59.681292 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10489 11:44:59.681458 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10490 11:44:59.681602 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10491 11:44:59.681797 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10492 11:44:59.681938 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10493 11:44:59.682081 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10494 11:44:59.682241 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10495 11:44:59.682445 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10496 11:44:59.682612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10497 11:44:59.682771 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10498 11:44:59.682931 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10499 11:44:59.683161 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10500 11:44:59.683392 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10501 11:44:59.683587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10502 11:44:59.683719 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10503 11:44:59.683847 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10504 11:44:59.683962 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10505 11:44:59.684079 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10506 11:44:59.684193 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10507 11:44:59.684307 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10508 11:44:59.684419 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10509 11:44:59.684565 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10510 11:44:59.684688 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10511 11:44:59.684804 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10512 11:44:59.687882 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10513 11:44:59.688109 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10514 11:44:59.688454 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10515 11:44:59.688648 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10516 11:44:59.688862 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10517 11:44:59.689090 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10518 11:44:59.689253 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10519 11:44:59.689401 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10520 11:44:59.689546 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10521 11:44:59.689703 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10522 11:44:59.689849 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10523 11:44:59.689993 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10524 11:44:59.690176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10525 11:44:59.690312 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10526 11:44:59.690454 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10527 11:44:59.690597 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10528 11:44:59.690737 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10529 11:44:59.690878 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10530 11:44:59.691020 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10531 11:44:59.691161 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10532 11:44:59.691303 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10533 11:44:59.691484 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10534 11:44:59.691621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10535 11:44:59.691764 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10536 11:44:59.691906 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10537 11:44:59.692048 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10538 11:44:59.692191 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10539 11:44:59.692331 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10540 11:44:59.692475 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10541 11:44:59.692618 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10542 11:44:59.692760 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10543 11:44:59.692934 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10544 11:44:59.695934 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10545 11:44:59.696155 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10546 11:44:59.696612 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10547 11:44:59.696803 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10548 11:44:59.696975 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10549 11:44:59.697124 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10550 11:44:59.697268 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10551 11:44:59.697409 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10552 11:44:59.697551 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10553 11:44:59.697743 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10554 11:44:59.697884 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10555 11:44:59.698028 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10556 11:44:59.712015 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10557 11:44:59.712629 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10558 11:44:59.712800 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10559 11:44:59.712997 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10560 11:44:59.713111 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10561 11:44:59.713200 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10562 11:44:59.713307 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10563 11:44:59.713397 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10564 11:44:59.713482 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10565 11:44:59.713568 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10566 11:44:59.713660 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10567 11:44:59.713745 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10568 11:44:59.713829 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10569 11:44:59.713913 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10570 11:44:59.714017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10571 11:44:59.714104 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10572 11:44:59.714187 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10573 11:44:59.714268 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10574 11:44:59.714349 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10575 11:44:59.714434 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10576 11:44:59.714534 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10577 11:44:59.714618 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10578 11:44:59.714701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10579 11:44:59.714799 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10580 11:44:59.714886 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10581 11:44:59.714987 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10582 11:44:59.715073 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10583 11:44:59.715156 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10584 11:44:59.715240 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10585 11:44:59.715603 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10586 11:44:59.715706 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10587 11:44:59.715784 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10588 11:44:59.715859 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10589 11:44:59.715935 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10590 11:44:59.719788 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10591 11:44:59.720285 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10592 11:44:59.720472 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10593 11:44:59.720625 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10594 11:44:59.720779 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10595 11:44:59.720912 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10596 11:44:59.721057 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10597 11:44:59.721180 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10598 11:44:59.721300 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10599 11:44:59.721418 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10600 11:44:59.721535 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10601 11:44:59.721707 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10602 11:44:59.721916 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10603 11:44:59.722109 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10604 11:44:59.722256 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10605 11:44:59.722401 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10606 11:44:59.722544 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10607 11:44:59.722686 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10608 11:44:59.722868 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10609 11:44:59.723004 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10610 11:44:59.723152 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10611 11:44:59.723292 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10612 11:44:59.723434 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10613 11:44:59.723583 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10614 11:44:59.723725 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10615 11:44:59.723873 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10616 11:44:59.724053 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10617 11:44:59.724189 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10618 11:44:59.724332 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10619 11:44:59.724474 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10620 11:44:59.724617 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10621 11:44:59.727730 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10622 11:44:59.728159 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10623 11:44:59.728354 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10624 11:44:59.728519 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10625 11:44:59.728701 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10626 11:44:59.728863 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10627 11:44:59.728986 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10628 11:44:59.729103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10629 11:44:59.729274 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10630 11:44:59.729431 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10631 11:44:59.729580 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10632 11:44:59.729746 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10633 11:44:59.729900 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10634 11:44:59.730084 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10635 11:44:59.730237 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10636 11:44:59.730388 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10637 11:44:59.730536 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10638 11:44:59.730687 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10639 11:44:59.730837 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10640 11:44:59.731023 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10641 11:44:59.731186 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10642 11:44:59.731343 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10643 11:44:59.731498 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10644 11:44:59.731662 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10645 11:44:59.731805 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10646 11:44:59.731953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10647 11:44:59.732076 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10648 11:44:59.732192 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10649 11:44:59.732306 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10650 11:44:59.735712 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10651 11:44:59.736238 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10652 11:44:59.736417 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10653 11:44:59.736507 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10654 11:44:59.736609 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10655 11:44:59.736697 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10656 11:44:59.736781 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10657 11:44:59.736865 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10658 11:44:59.736949 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10659 11:44:59.737033 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10660 11:44:59.737174 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10661 11:44:59.737270 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10662 11:44:59.737344 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10663 11:44:59.737430 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10664 11:44:59.737503 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10665 11:44:59.737586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10666 11:44:59.737669 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10667 11:44:59.737752 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10668 11:44:59.738030 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10669 11:44:59.738136 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10670 11:44:59.738219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10671 11:44:59.738302 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10672 11:44:59.738671 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10673 11:44:59.738781 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10674 11:44:59.738861 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10675 11:44:59.739118 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10676 11:44:59.741450 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10677 11:44:59.741637 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10678 11:44:59.741780 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10679 11:44:59.741894 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10680 11:44:59.742009 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10681 11:44:59.743842 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10682 11:44:59.744360 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10683 11:44:59.744531 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10684 11:44:59.744683 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10685 11:44:59.744826 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10686 11:44:59.744998 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10687 11:44:59.745161 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10688 11:44:59.745314 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10689 11:44:59.745495 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10690 11:44:59.745732 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10691 11:44:59.745913 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10692 11:44:59.746078 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10693 11:44:59.746246 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10694 11:44:59.746463 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10695 11:44:59.746725 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10696 11:44:59.746949 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10697 11:44:59.747156 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10698 11:44:59.747333 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10699 11:44:59.747507 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10700 11:44:59.747696 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10701 11:44:59.747896 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10702 11:44:59.748039 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10703 11:44:59.748160 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10704 11:44:59.748276 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10705 11:44:59.748390 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10706 11:44:59.748502 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10707 11:44:59.748615 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10708 11:44:59.748728 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10709 11:44:59.748841 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10710 11:44:59.752225 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10711 11:44:59.752473 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10712 11:44:59.752594 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10713 11:44:59.752779 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10714 11:44:59.752906 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10715 11:44:59.753020 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10716 11:44:59.766413 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10717 11:44:59.766653 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10718 11:44:59.766952 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10719 11:44:59.767056 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10720 11:44:59.767144 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10721 11:44:59.767229 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10722 11:44:59.767313 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10723 11:44:59.767414 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10724 11:44:59.767501 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10725 11:44:59.767591 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10726 11:44:59.767691 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10727 11:44:59.767790 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10728 11:44:59.767890 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10729 11:44:59.768231 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10730 11:44:59.768421 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10731 11:44:59.768638 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10732 11:44:59.768795 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10733 11:44:59.768935 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10734 11:44:59.769108 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10735 11:44:59.769274 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10736 11:44:59.769444 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10737 11:44:59.769663 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10738 11:44:59.769817 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10739 11:44:59.769958 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10740 11:44:59.773236 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10741 11:44:59.773361 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10742 11:44:59.773453 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10743 11:44:59.773542 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10744 11:44:59.773629 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10745 11:44:59.773734 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10746 11:44:59.773822 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10747 11:44:59.773911 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10748 11:44:59.773998 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10749 11:44:59.774085 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10750 11:44:59.774172 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10751 11:44:59.774238 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10752 11:44:59.774298 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10753 11:44:59.774358 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10754 11:44:59.775738 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10755 11:44:59.776116 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10756 11:44:59.776223 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10757 11:44:59.776292 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10758 11:44:59.776513 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10759 11:44:59.776593 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10760 11:44:59.776655 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10761 11:44:59.776734 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10762 11:44:59.776974 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10763 11:44:59.777057 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10764 11:44:59.777143 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10765 11:44:59.777433 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10766 11:44:59.777532 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10767 11:44:59.777622 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10768 11:44:59.777728 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10769 11:44:59.777821 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10770 11:44:59.777927 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10771 11:44:59.778024 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10772 11:44:59.778119 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10773 11:44:59.778212 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10774 11:44:59.778491 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10775 11:44:59.778564 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10776 11:44:59.778847 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10777 11:44:59.778945 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10778 11:44:59.779047 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10779 11:44:59.779129 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10780 11:44:59.779228 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10781 11:44:59.779325 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10782 11:44:59.779613 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10783 11:44:59.779693 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10784 11:44:59.783741 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10785 11:44:59.784157 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10786 11:44:59.784261 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10787 11:44:59.784347 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10788 11:44:59.784446 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10789 11:44:59.784532 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10790 11:44:59.784630 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10791 11:44:59.784730 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10792 11:44:59.784829 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10793 11:44:59.784928 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10794 11:44:59.785218 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10795 11:44:59.785321 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10796 11:44:59.785407 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10797 11:44:59.785722 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10798 11:44:59.785812 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10799 11:44:59.785895 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10800 11:44:59.785978 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10801 11:44:59.786267 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10802 11:44:59.786356 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10803 11:44:59.786637 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10804 11:44:59.786727 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10805 11:44:59.786798 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10806 11:44:59.787066 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10807 11:44:59.787155 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10808 11:44:59.787230 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10809 11:44:59.787312 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10810 11:44:59.787397 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10811 11:44:59.787481 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10812 11:44:59.791933 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10813 11:44:59.792357 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10814 11:44:59.792459 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10815 11:44:59.792545 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10816 11:44:59.792637 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10817 11:44:59.792719 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10818 11:44:59.792815 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10819 11:44:59.792894 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10820 11:44:59.792989 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10821 11:44:59.793086 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10822 11:44:59.793398 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10823 11:44:59.793489 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10824 11:44:59.793580 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10825 11:44:59.793681 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10826 11:44:59.793996 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10827 11:44:59.794088 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10828 11:44:59.794168 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10829 11:44:59.794259 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10830 11:44:59.794358 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10831 11:44:59.794637 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10832 11:44:59.794732 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10833 11:44:59.794829 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10834 11:44:59.795120 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10835 11:44:59.795218 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10836 11:44:59.795313 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10837 11:44:59.795406 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10838 11:44:59.799980 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10839 11:44:59.800173 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10840 11:44:59.800477 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10841 11:44:59.800567 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10842 11:44:59.800632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10843 11:44:59.800705 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10844 11:44:59.800766 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10845 11:44:59.800838 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10846 11:44:59.801107 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10847 11:44:59.801216 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10848 11:44:59.801331 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10849 11:44:59.801413 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10850 11:44:59.801507 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10851 11:44:59.801609 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10852 11:44:59.801891 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10853 11:44:59.801996 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10854 11:44:59.802326 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10855 11:44:59.802404 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10856 11:44:59.802475 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10857 11:44:59.802545 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10858 11:44:59.802620 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10859 11:44:59.802912 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10860 11:44:59.803008 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10861 11:44:59.803103 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10862 11:44:59.803184 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10863 11:44:59.803278 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10864 11:44:59.803379 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10865 11:44:59.807987 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10866 11:44:59.808417 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10867 11:44:59.808501 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10868 11:44:59.808580 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10869 11:44:59.808657 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10870 11:44:59.808754 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10871 11:44:59.808840 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10872 11:44:59.808937 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10873 11:44:59.809017 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10874 11:44:59.809300 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10875 11:44:59.809380 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10876 11:44:59.822811 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10877 11:44:59.823052 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10878 11:44:59.823358 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10879 11:44:59.823455 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10880 11:44:59.823556 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10881 11:44:59.823631 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10882 11:44:59.823746 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10883 11:44:59.823865 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10884 11:44:59.823975 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10885 11:44:59.824272 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10886 11:44:59.824379 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10887 11:44:59.824471 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10888 11:44:59.824548 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10889 11:44:59.824646 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10890 11:44:59.824785 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10891 11:44:59.824897 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10892 11:44:59.825010 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10893 11:44:59.825117 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10894 11:44:59.825235 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10895 11:44:59.825357 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10896 11:44:59.825660 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10897 11:44:59.825762 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10898 11:44:59.826058 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10899 11:44:59.826155 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10900 11:44:59.826254 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10901 11:44:59.826573 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10902 11:44:59.826667 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10903 11:44:59.826742 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10904 11:44:59.827009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10905 11:44:59.827122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10906 11:44:59.827384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10907 11:44:59.827662 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10908 11:44:59.831979 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10909 11:44:59.832358 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10910 11:44:59.832466 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10911 11:44:59.832571 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10912 11:44:59.832863 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10913 11:44:59.832959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10914 11:44:59.833061 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10915 11:44:59.833160 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10916 11:44:59.833451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10917 11:44:59.833562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10918 11:44:59.833866 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10919 11:44:59.833969 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10920 11:44:59.834070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10921 11:44:59.834365 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10922 11:44:59.834473 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10923 11:44:59.834583 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10924 11:44:59.834884 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10925 11:44:59.835177 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10926 11:44:59.835284 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10927 11:44:59.835589 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10928 11:44:59.839912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10929 11:44:59.840326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10930 11:44:59.840424 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10931 11:44:59.840528 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10932 11:44:59.840613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10933 11:44:59.840898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10934 11:44:59.840998 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10935 11:44:59.841081 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10936 11:44:59.841175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10937 11:44:59.841274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10938 11:44:59.841554 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10939 11:44:59.841722 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10940 11:44:59.841827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10941 11:44:59.841969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10942 11:44:59.842060 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10943 11:44:59.842134 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10944 11:44:59.842217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10945 11:44:59.842653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10946 11:44:59.842748 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10947 11:44:59.842827 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10948 11:44:59.842917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
10949 11:44:59.843001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
10950 11:44:59.843272 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
10951 11:44:59.843394 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
10952 11:44:59.843495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
10953 11:44:59.847868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
10954 11:44:59.848318 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
10955 11:44:59.848421 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
10956 11:44:59.848509 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
10957 11:44:59.848608 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
10958 11:44:59.848693 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
10959 11:44:59.848796 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
10960 11:44:59.848898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
10961 11:44:59.849000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
10962 11:44:59.849097 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
10963 11:44:59.849396 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
10964 11:44:59.849489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
10965 11:44:59.849829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
10966 11:44:59.849922 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
10967 11:44:59.849996 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
10968 11:44:59.850081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
10969 11:44:59.850171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
10970 11:44:59.850468 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
10971 11:44:59.850583 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
10972 11:44:59.850682 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
10973 11:44:59.850959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
10974 11:44:59.851063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
10975 11:44:59.851363 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
10976 11:44:59.851453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
10977 11:44:59.855755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
10978 11:44:59.856204 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
10979 11:44:59.856304 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
10980 11:44:59.856389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
10981 11:44:59.856486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
10982 11:44:59.856570 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
10983 11:44:59.856666 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
10984 11:44:59.856762 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
10985 11:44:59.856875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
10986 11:44:59.857186 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
10987 11:44:59.857289 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
10988 11:44:59.857392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
10989 11:44:59.857488 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
10990 11:44:59.857785 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
10991 11:44:59.857887 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
10992 11:44:59.857996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
10993 11:44:59.858263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
10994 11:44:59.858366 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
10995 11:44:59.858653 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
10996 11:44:59.858749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
10997 11:44:59.858836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
10998 11:44:59.858920 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
10999 11:44:59.859002 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
11000 11:44:59.859284 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
11001 11:44:59.859400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
11002 11:44:59.859500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
11003 11:44:59.863951 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
11004 11:44:59.864170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
11005 11:44:59.864260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
11006 11:44:59.864364 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
11007 11:44:59.864465 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
11008 11:44:59.864566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
11009 11:44:59.864866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
11010 11:44:59.865169 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
11011 11:44:59.865271 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
11012 11:44:59.865358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
11013 11:44:59.877626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
11014 11:44:59.877926 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
11015 11:44:59.878054 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
11016 11:44:59.878407 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
11017 11:44:59.878507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
11018 11:44:59.878609 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
11019 11:44:59.878713 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
11020 11:44:59.878810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
11021 11:44:59.878934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
11022 11:44:59.879030 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
11023 11:44:59.879106 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
11024 11:44:59.879194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
11025 11:44:59.879304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
11026 11:44:59.879414 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
11027 11:44:59.879504 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
11028 11:44:59.879791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
11029 11:44:59.879917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
11030 11:44:59.880223 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
11031 11:44:59.880333 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
11032 11:44:59.880445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
11033 11:44:59.880551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
11034 11:44:59.880866 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
11035 11:44:59.880981 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
11036 11:44:59.881093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
11037 11:44:59.881194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
11038 11:44:59.881495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
11039 11:44:59.881596 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
11040 11:44:59.881731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
11041 11:44:59.882018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
11042 11:44:59.882114 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
11043 11:44:59.882244 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
11044 11:44:59.882344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
11045 11:44:59.882471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
11046 11:44:59.882599 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
11047 11:44:59.882883 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
11048 11:44:59.883187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
11049 11:44:59.883297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
11050 11:44:59.883601 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
11051 11:44:59.883705 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
11052 11:44:59.887683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
11053 11:44:59.888015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
11054 11:44:59.888112 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
11055 11:44:59.888426 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
11056 11:44:59.888533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
11057 11:44:59.888622 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
11058 11:44:59.888726 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
11059 11:44:59.888816 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
11060 11:44:59.888916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
11061 11:44:59.889218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
11062 11:44:59.889326 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
11063 11:44:59.889447 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
11064 11:44:59.889542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
11065 11:44:59.889868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
11066 11:44:59.889960 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
11067 11:44:59.890056 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
11068 11:44:59.890142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
11069 11:44:59.890233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
11070 11:44:59.890510 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
11071 11:44:59.890605 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
11072 11:44:59.890694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
11073 11:44:59.890969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
11074 11:44:59.891065 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
11075 11:44:59.891140 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
11076 11:44:59.891229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
11077 11:44:59.891315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
11078 11:44:59.891575 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
11079 11:44:59.895838 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
11080 11:44:59.895936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
11081 11:44:59.896269 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
11082 11:44:59.896396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
11083 11:44:59.896489 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
11084 11:44:59.896614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
11085 11:44:59.896703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
11086 11:44:59.896802 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
11087 11:44:59.896887 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
11088 11:44:59.896975 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
11089 11:44:59.897278 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
11090 11:44:59.897409 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
11091 11:44:59.897519 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
11092 11:44:59.897627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
11093 11:44:59.897960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
11094 11:44:59.898236 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
11095 11:44:59.898343 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
11096 11:44:59.898432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
11097 11:44:59.898532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
11098 11:44:59.898618 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
11099 11:44:59.898916 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
11100 11:44:59.899022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
11101 11:44:59.899126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
11102 11:44:59.899230 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
11103 11:44:59.899318 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
11104 11:44:59.899428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
11105 11:44:59.903798 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
11106 11:44:59.904129 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
11107 11:44:59.904230 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
11108 11:44:59.904319 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
11109 11:44:59.904403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
11110 11:44:59.904500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
11111 11:44:59.904584 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
11112 11:44:59.904666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
11113 11:44:59.904764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
11114 11:44:59.904847 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
11115 11:44:59.905147 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
11116 11:44:59.905248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
11117 11:44:59.905338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
11118 11:44:59.905407 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
11119 11:44:59.905483 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
11120 11:44:59.905560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
11121 11:44:59.905819 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
11122 11:44:59.905890 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
11123 11:44:59.905970 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
11124 11:44:59.906035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
11125 11:44:59.906278 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
11126 11:44:59.906361 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
11127 11:44:59.906432 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
11128 11:44:59.906513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
11129 11:44:59.906767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
11130 11:44:59.906836 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
11131 11:44:59.906912 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
11132 11:44:59.906979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
11133 11:44:59.907225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
11134 11:44:59.907295 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
11135 11:44:59.907372 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
11136 11:44:59.907464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
11137 11:44:59.915834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
11138 11:44:59.915989 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
11139 11:44:59.916297 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
11140 11:44:59.916400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
11141 11:44:59.916489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
11142 11:44:59.916563 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
11143 11:44:59.916626 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
11144 11:44:59.916706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
11145 11:44:59.916775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
11146 11:44:59.916841 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
11147 11:44:59.916904 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
11148 11:44:59.916978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
11149 11:44:59.928114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
11150 11:44:59.928323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
11151 11:44:59.928463 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
11152 11:44:59.928772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
11153 11:44:59.928877 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
11154 11:44:59.928965 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
11155 11:44:59.929062 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
11156 11:44:59.929141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
11157 11:44:59.929244 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
11158 11:44:59.929364 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
11159 11:44:59.929481 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
11160 11:44:59.929771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
11161 11:44:59.929870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
11162 11:44:59.929949 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
11163 11:44:59.930231 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
11164 11:44:59.930337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
11165 11:44:59.930451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
11166 11:44:59.930774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
11167 11:44:59.930881 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
11168 11:44:59.930983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
11169 11:44:59.931086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
11170 11:44:59.931373 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
11171 11:44:59.931475 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
11172 11:44:59.935891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
11173 11:44:59.936018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
11174 11:44:59.936309 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
11175 11:44:59.936413 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
11176 11:44:59.936503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
11177 11:44:59.936607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
11178 11:44:59.936697 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
11179 11:44:59.936803 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
11180 11:44:59.937085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
11181 11:44:59.937181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
11182 11:44:59.937284 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
11183 11:44:59.937387 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
11184 11:44:59.937688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
11185 11:44:59.937811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
11186 11:44:59.937917 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
11187 11:44:59.938225 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
11188 11:44:59.938333 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
11189 11:44:59.938642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
11190 11:44:59.938745 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
11191 11:44:59.938854 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
11192 11:44:59.938953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
11193 11:44:59.939251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11194 11:44:59.939582 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11195 11:44:59.939687 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11196 11:44:59.943751 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11197 11:44:59.944042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11198 11:44:59.944162 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11199 11:44:59.944457 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11200 11:44:59.944563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11201 11:44:59.944666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11202 11:44:59.944956 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11203 11:44:59.945060 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11204 11:44:59.945159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11205 11:44:59.945259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11206 11:44:59.945360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11207 11:44:59.945461 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11208 11:44:59.945772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11209 11:44:59.945889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11210 11:44:59.946193 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11211 11:44:59.946297 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11212 11:44:59.946396 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11213 11:44:59.946493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11214 11:44:59.946849 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11215 11:44:59.947034 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11216 11:44:59.947226 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11217 11:44:59.947385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11218 11:44:59.947620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11219 11:44:59.947768 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11220 11:44:59.952043 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11221 11:44:59.952199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11222 11:44:59.952349 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11223 11:44:59.952497 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11224 11:44:59.952597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11225 11:44:59.952878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11226 11:44:59.952983 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11227 11:44:59.953257 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11228 11:44:59.953340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11229 11:44:59.953448 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11230 11:44:59.953684 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11231 11:44:59.953784 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11232 11:44:59.953892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11233 11:44:59.954180 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11234 11:44:59.954286 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11235 11:44:59.954407 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11236 11:44:59.954509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11237 11:44:59.954805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11238 11:44:59.954907 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11239 11:44:59.955018 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11240 11:44:59.955128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11241 11:44:59.955435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11242 11:44:59.955553 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11243 11:44:59.960063 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11244 11:44:59.960285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11245 11:44:59.960540 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11246 11:44:59.960740 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11247 11:44:59.960924 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11248 11:44:59.961145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11249 11:44:59.961293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11250 11:44:59.961423 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11251 11:44:59.961574 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11252 11:44:59.961761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11253 11:44:59.961997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11254 11:44:59.962168 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11255 11:44:59.962353 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11256 11:44:59.962553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11257 11:44:59.962727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11258 11:44:59.962878 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11259 11:44:59.963060 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11260 11:44:59.963224 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11261 11:44:59.963385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11262 11:44:59.963552 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11263 11:44:59.963724 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11264 11:44:59.963872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11265 11:44:59.963991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11266 11:44:59.967805 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11267 11:44:59.968209 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11268 11:44:59.968384 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11269 11:44:59.968612 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11270 11:44:59.968813 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11271 11:44:59.969023 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11272 11:44:59.969240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11273 11:44:59.969456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11274 11:44:59.969675 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11275 11:44:59.969879 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11276 11:44:59.970026 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11277 11:44:59.970174 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11278 11:44:59.970341 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11279 11:44:59.970511 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11280 11:44:59.970666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11281 11:44:59.970787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11282 11:44:59.970903 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11283 11:44:59.990388 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11284 11:44:59.990964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11285 11:44:59.991178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11286 11:44:59.991392 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11287 11:44:59.991594 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11288 11:44:59.991763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11289 11:44:59.991995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11290 11:44:59.992185 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11291 11:44:59.992331 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11292 11:44:59.992479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11293 11:44:59.992699 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11294 11:44:59.992966 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11295 11:44:59.993176 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11296 11:44:59.993388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11297 11:44:59.993589 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11298 11:44:59.993785 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11299 11:44:59.993948 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11300 11:44:59.994110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11301 11:44:59.994317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11302 11:44:59.994492 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11303 11:44:59.994689 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11304 11:44:59.994896 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11305 11:44:59.995096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11306 11:44:59.995308 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11307 11:44:59.995486 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11308 11:44:59.995644 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11309 11:44:59.995775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11310 11:44:59.995920 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11311 11:44:59.996042 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11312 11:44:59.996159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11313 11:44:59.996275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11314 11:44:59.996391 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11315 11:44:59.996721 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11316 11:44:59.996835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11317 11:44:59.999734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11318 11:45:00.000052 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11319 11:45:00.000158 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11320 11:45:00.000264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11321 11:45:00.000364 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11322 11:45:00.000544 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11323 11:45:00.000666 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11324 11:45:00.000761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11325 11:45:00.000866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11326 11:45:00.000968 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11327 11:45:00.001069 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11328 11:45:00.001169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11329 11:45:00.001482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11330 11:45:00.001592 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11331 11:45:00.001709 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11332 11:45:00.001811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11333 11:45:00.001910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11334 11:45:00.002009 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11335 11:45:00.002108 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11336 11:45:00.002218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11337 11:45:00.002472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11338 11:45:00.002597 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11339 11:45:00.002699 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11340 11:45:00.002888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11341 11:45:00.003222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11342 11:45:00.003325 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11343 11:45:00.003430 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11344 11:45:00.003616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11345 11:45:00.007902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11346 11:45:00.008044 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11347 11:45:00.008151 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11348 11:45:00.008456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11349 11:45:00.008564 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11350 11:45:00.008663 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11351 11:45:00.009000 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11352 11:45:00.009225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11353 11:45:00.009490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11354 11:45:00.009720 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11355 11:45:00.009893 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11356 11:45:00.010146 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11357 11:45:00.010368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11358 11:45:00.010576 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11359 11:45:00.010784 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11360 11:45:00.010935 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11361 11:45:00.011084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11362 11:45:00.011205 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11363 11:45:00.011319 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11364 11:45:00.011432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11365 11:45:00.011544 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11366 11:45:00.011659 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11367 11:45:00.011771 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11368 11:45:00.011882 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11369 11:45:00.012019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11370 11:45:00.012137 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11371 11:45:00.012251 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11372 11:45:00.015728 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11373 11:45:00.016058 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11374 11:45:00.016165 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11375 11:45:00.016253 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11376 11:45:00.016350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11377 11:45:00.016453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11378 11:45:00.016750 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11379 11:45:00.016866 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11380 11:45:00.016968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11381 11:45:00.017260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11382 11:45:00.017377 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11383 11:45:00.017674 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11384 11:45:00.017790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11385 11:45:00.018091 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11386 11:45:00.018193 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11387 11:45:00.018295 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11388 11:45:00.018590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11389 11:45:00.018712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11390 11:45:00.018993 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11391 11:45:00.019113 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11392 11:45:00.019405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11393 11:45:00.019508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11394 11:45:00.019613 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11395 11:45:00.023984 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11396 11:45:00.024253 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11397 11:45:00.024497 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11398 11:45:00.024691 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11399 11:45:00.024866 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11400 11:45:00.025114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11401 11:45:00.025328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11402 11:45:00.025528 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11403 11:45:00.025754 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11404 11:45:00.026008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11405 11:45:00.026200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11406 11:45:00.026370 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11407 11:45:00.026585 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11408 11:45:00.026800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11409 11:45:00.026942 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11410 11:45:00.027090 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11411 11:45:00.027224 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11412 11:45:00.027397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11413 11:45:00.027524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11414 11:45:00.027641 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11415 11:45:00.027756 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11416 11:45:00.027870 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11417 11:45:00.041662 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11418 11:45:00.041897 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11419 11:45:00.041986 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11420 11:45:00.042072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11421 11:45:00.042155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11422 11:45:00.042445 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11423 11:45:00.042538 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11424 11:45:00.042623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11425 11:45:00.042712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11426 11:45:00.042795 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11427 11:45:00.042878 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11428 11:45:00.042978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11429 11:45:00.043063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11430 11:45:00.043146 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11431 11:45:00.043246 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11432 11:45:00.043331 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11433 11:45:00.043430 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11434 11:45:00.043981 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11435 11:45:00.044088 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11436 11:45:00.044192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11437 11:45:00.044291 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11438 11:45:00.044387 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11439 11:45:00.044723 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11440 11:45:00.044904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11441 11:45:00.045086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11442 11:45:00.045219 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11443 11:45:00.045380 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11444 11:45:00.045578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11445 11:45:00.045790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11446 11:45:00.046031 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11447 11:45:00.046230 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11448 11:45:00.046429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11449 11:45:00.046625 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11450 11:45:00.046818 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11451 11:45:00.047043 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11452 11:45:00.047234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11453 11:45:00.047425 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11454 11:45:00.047621 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11455 11:45:00.047777 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11456 11:45:00.047900 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11457 11:45:00.048015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11458 11:45:00.048129 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11459 11:45:00.048273 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11460 11:45:00.048395 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11461 11:45:00.048510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11462 11:45:00.048625 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11463 11:45:00.051993 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11464 11:45:00.052112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11465 11:45:00.052202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11466 11:45:00.052535 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11467 11:45:00.052720 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11468 11:45:00.052879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11469 11:45:00.053097 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11470 11:45:00.053315 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11471 11:45:00.053488 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11472 11:45:00.053668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11473 11:45:00.053838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11474 11:45:00.054008 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11475 11:45:00.054175 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11476 11:45:00.054371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11477 11:45:00.054539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11478 11:45:00.054704 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11479 11:45:00.054903 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11480 11:45:00.055076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11481 11:45:00.055240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11482 11:45:00.055442 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11483 11:45:00.055600 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11484 11:45:00.055723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11485 11:45:00.055839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11486 11:45:00.055955 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11487 11:45:00.056088 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11488 11:45:00.056239 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11489 11:45:00.063708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11490 11:45:00.064128 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11491 11:45:00.064240 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11492 11:45:00.064329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11493 11:45:00.064416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11494 11:45:00.064517 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11495 11:45:00.064609 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11496 11:45:00.064696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11497 11:45:00.064804 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11498 11:45:00.064908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11499 11:45:00.065008 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11500 11:45:00.065330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11501 11:45:00.065438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11502 11:45:00.065541 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11503 11:45:00.065643 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11504 11:45:00.065761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11505 11:45:00.066061 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11506 11:45:00.066165 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11507 11:45:00.066266 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11508 11:45:00.066365 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11509 11:45:00.066464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11510 11:45:00.066564 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11511 11:45:00.066861 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11512 11:45:00.066970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11513 11:45:00.067076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11514 11:45:00.067178 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11515 11:45:00.067390 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11516 11:45:00.067708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11517 11:45:00.071765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11518 11:45:00.072138 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11519 11:45:00.072341 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11520 11:45:00.072542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11521 11:45:00.072708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11522 11:45:00.072924 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11523 11:45:00.073131 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11524 11:45:00.073294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11525 11:45:00.073424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11526 11:45:00.073554 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11527 11:45:00.073724 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11528 11:45:00.073863 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11529 11:45:00.073993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11530 11:45:00.074130 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11531 11:45:00.074267 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11532 11:45:00.074424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11533 11:45:00.074557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11534 11:45:00.074686 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11535 11:45:00.074813 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11536 11:45:00.074939 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11537 11:45:00.075090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11538 11:45:00.075217 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11539 11:45:00.075343 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11540 11:45:00.075477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11541 11:45:00.075662 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11542 11:45:00.075835 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11543 11:45:00.075960 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11544 11:45:00.076077 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11545 11:45:00.079799 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11546 11:45:00.080255 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11547 11:45:00.080434 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11548 11:45:00.080608 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11549 11:45:00.080756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11550 11:45:00.080967 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11551 11:45:00.091568 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11552 11:45:00.092125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11553 11:45:00.092311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11554 11:45:00.092507 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11555 11:45:00.092705 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11556 11:45:00.093133 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11557 11:45:00.093342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11558 11:45:00.093823 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11559 11:45:00.094047 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11560 11:45:00.094250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11561 11:45:00.094679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11562 11:45:00.095086 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11563 11:45:00.095253 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11564 11:45:00.095402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11565 11:45:00.099794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11566 11:45:00.099923 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11567 11:45:00.100250 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11568 11:45:00.100460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11569 11:45:00.100671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11570 11:45:00.100847 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11571 11:45:00.101018 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11572 11:45:00.101191 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11573 11:45:00.101392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11574 11:45:00.101555 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11575 11:45:00.101733 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11576 11:45:00.101897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11577 11:45:00.102093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11578 11:45:00.102264 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11579 11:45:00.102430 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11580 11:45:00.102597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11581 11:45:00.102796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11582 11:45:00.102998 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11583 11:45:00.103211 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11584 11:45:00.103402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11585 11:45:00.103635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11586 11:45:00.103832 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11587 11:45:00.103969 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11588 11:45:00.104086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11589 11:45:00.107750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11590 11:45:00.108211 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11591 11:45:00.108439 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11592 11:45:00.108652 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11593 11:45:00.108915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11594 11:45:00.109107 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11595 11:45:00.109274 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11596 11:45:00.109486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11597 11:45:00.109742 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11598 11:45:00.109928 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11599 11:45:00.110138 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11600 11:45:00.110346 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11601 11:45:00.110551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11602 11:45:00.110725 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11603 11:45:00.110929 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11604 11:45:00.111108 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11605 11:45:00.111317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11606 11:45:00.111524 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11607 11:45:00.111693 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11608 11:45:00.111825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11609 11:45:00.111943 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11610 11:45:00.112085 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11611 11:45:00.112205 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11612 11:45:00.112318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11613 11:45:00.112431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11614 11:45:00.115710 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11615 11:45:00.116022 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11616 11:45:00.116134 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11617 11:45:00.116240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11618 11:45:00.116331 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11619 11:45:00.116431 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11620 11:45:00.116531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11621 11:45:00.116634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11622 11:45:00.116934 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11623 11:45:00.117041 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11624 11:45:00.117141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11625 11:45:00.117432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11626 11:45:00.117529 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11627 11:45:00.117631 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11628 11:45:00.117731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11629 11:45:00.117838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11630 11:45:00.118096 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11631 11:45:00.118250 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11632 11:45:00.118403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11633 11:45:00.118714 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11634 11:45:00.118818 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11635 11:45:00.118923 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11636 11:45:00.119024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11637 11:45:00.119134 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11638 11:45:00.119467 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11639 11:45:00.119608 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11640 11:45:00.123761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11641 11:45:00.124203 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11642 11:45:00.124416 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11643 11:45:00.124581 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11644 11:45:00.124766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11645 11:45:00.124930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11646 11:45:00.125087 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11647 11:45:00.125242 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11648 11:45:00.125426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11649 11:45:00.125588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11650 11:45:00.125763 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11651 11:45:00.125947 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11652 11:45:00.126107 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11653 11:45:00.126288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11654 11:45:00.126450 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11655 11:45:00.126633 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11656 11:45:00.126793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11657 11:45:00.126975 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11658 11:45:00.127165 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11659 11:45:00.127327 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11660 11:45:00.127518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11661 11:45:00.127678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11662 11:45:00.131789 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11663 11:45:00.132286 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11664 11:45:00.132475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11665 11:45:00.132625 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11666 11:45:00.132797 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11667 11:45:00.132944 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11668 11:45:00.133086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11669 11:45:00.133228 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11670 11:45:00.133397 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11671 11:45:00.133544 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11672 11:45:00.133719 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11673 11:45:00.133900 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11674 11:45:00.134107 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11675 11:45:00.134255 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11676 11:45:00.134409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11677 11:45:00.134576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11678 11:45:00.134786 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11679 11:45:00.134966 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11680 11:45:00.135142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11681 11:45:00.135357 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11682 11:45:00.135534 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11683 11:45:00.135685 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11684 11:45:00.135829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11685 11:45:00.148161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11686 11:45:00.148418 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11687 11:45:00.148747 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11688 11:45:00.149000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11689 11:45:00.149123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11690 11:45:00.149247 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11691 11:45:00.149382 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11692 11:45:00.149476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11693 11:45:00.149577 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11694 11:45:00.149670 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11695 11:45:00.149754 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11696 11:45:00.149835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11697 11:45:00.149940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11698 11:45:00.150025 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11699 11:45:00.150107 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11700 11:45:00.150207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11701 11:45:00.150294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11702 11:45:00.150379 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11703 11:45:00.150480 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11704 11:45:00.150568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11705 11:45:00.150653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11706 11:45:00.150754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11707 11:45:00.150841 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11708 11:45:00.150944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11709 11:45:00.151045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11710 11:45:00.151145 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11711 11:45:00.151245 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11712 11:45:00.151344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11713 11:45:00.151441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11714 11:45:00.155880 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11715 11:45:00.156041 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11716 11:45:00.156438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11717 11:45:00.156650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11718 11:45:00.156820 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11719 11:45:00.157013 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11720 11:45:00.157178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11721 11:45:00.157326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11722 11:45:00.157476 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11723 11:45:00.157645 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11724 11:45:00.157847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11725 11:45:00.157998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11726 11:45:00.158153 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11727 11:45:00.158306 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11728 11:45:00.158462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11729 11:45:00.158625 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11730 11:45:00.158842 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11731 11:45:00.159015 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11732 11:45:00.159182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11733 11:45:00.159360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11734 11:45:00.159534 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11735 11:45:00.159710 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11736 11:45:00.159919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11737 11:45:00.160093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11738 11:45:00.160268 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11739 11:45:00.160442 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11740 11:45:00.163912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11741 11:45:00.165054 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11742 11:45:00.165276 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11743 11:45:00.165458 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11744 11:45:00.165635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11745 11:45:00.165826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11746 11:45:00.165998 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11747 11:45:00.166209 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11748 11:45:00.166389 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11749 11:45:00.166562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11750 11:45:00.166737 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11751 11:45:00.166914 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11752 11:45:00.167087 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11753 11:45:00.167250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11754 11:45:00.167449 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11755 11:45:00.167627 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11756 11:45:00.167799 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11757 11:45:00.167969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11758 11:45:00.168142 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11759 11:45:00.168316 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11760 11:45:00.168488 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11761 11:45:00.168660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11762 11:45:00.171832 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11763 11:45:00.172222 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11764 11:45:00.172325 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11765 11:45:00.172671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11766 11:45:00.173194 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11767 11:45:00.173298 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11768 11:45:00.173387 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11769 11:45:00.173473 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11770 11:45:00.173559 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11771 11:45:00.173642 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11772 11:45:00.173750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11773 11:45:00.173851 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11774 11:45:00.173935 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11775 11:45:00.174019 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11776 11:45:00.174119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11777 11:45:00.174408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11778 11:45:00.174515 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11779 11:45:00.174801 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11780 11:45:00.174902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11781 11:45:00.175235 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11782 11:45:00.175336 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11783 11:45:00.175491 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11784 11:45:00.179819 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11785 11:45:00.180567 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11786 11:45:00.180785 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11787 11:45:00.180968 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11788 11:45:00.181184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11789 11:45:00.181367 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11790 11:45:00.181540 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11791 11:45:00.181730 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11792 11:45:00.181907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11793 11:45:00.182085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11794 11:45:00.182288 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11795 11:45:00.182468 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11796 11:45:00.182678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11797 11:45:00.182859 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11798 11:45:00.183037 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11799 11:45:00.183209 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11800 11:45:00.183372 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11801 11:45:00.183668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11802 11:45:00.183852 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11803 11:45:00.184065 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11804 11:45:00.184249 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11805 11:45:00.184426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11806 11:45:00.184601 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11807 11:45:00.184770 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11808 11:45:00.188027 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11809 11:45:00.188467 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11810 11:45:00.188564 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11811 11:45:00.188647 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11812 11:45:00.188740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11813 11:45:00.188840 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11814 11:45:00.188962 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11815 11:45:00.189155 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11816 11:45:00.189364 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11817 11:45:00.189805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11818 11:45:00.190016 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11819 11:45:00.208429 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11820 11:45:00.208775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11821 11:45:00.209171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11822 11:45:00.209281 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11823 11:45:00.209376 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11824 11:45:00.209486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11825 11:45:00.209580 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11826 11:45:00.209931 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11827 11:45:00.210049 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11828 11:45:00.210143 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11829 11:45:00.210234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11830 11:45:00.210342 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11831 11:45:00.210436 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11832 11:45:00.210543 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11833 11:45:00.210652 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11834 11:45:00.210761 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11835 11:45:00.211053 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11836 11:45:00.211154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11837 11:45:00.211253 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11838 11:45:00.211588 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11839 11:45:00.215880 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11840 11:45:00.216200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11841 11:45:00.216291 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11842 11:45:00.216376 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11843 11:45:00.216454 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11844 11:45:00.216535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11845 11:45:00.216796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11846 11:45:00.217054 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11847 11:45:00.217145 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11848 11:45:00.217224 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11849 11:45:00.217479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11850 11:45:00.217731 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11851 11:45:00.217801 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11852 11:45:00.217878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11853 11:45:00.218130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11854 11:45:00.218386 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11855 11:45:00.218455 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11856 11:45:00.218707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11857 11:45:00.218788 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11858 11:45:00.219042 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11859 11:45:00.219111 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11860 11:45:00.219439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11861 11:45:00.219614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11862 11:45:00.223843 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11863 11:45:00.224064 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11864 11:45:00.224490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11865 11:45:00.224683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11866 11:45:00.224837 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11867 11:45:00.225096 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11868 11:45:00.225300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11869 11:45:00.225486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11870 11:45:00.225643 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11871 11:45:00.225868 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11872 11:45:00.226042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11873 11:45:00.226215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11874 11:45:00.226389 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11875 11:45:00.226554 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11876 11:45:00.226786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11877 11:45:00.226954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11878 11:45:00.227108 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11879 11:45:00.227242 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11880 11:45:00.227400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11881 11:45:00.227558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11882 11:45:00.227684 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11883 11:45:00.227805 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11884 11:45:00.227944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11885 11:45:00.231767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11886 11:45:00.232074 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11887 11:45:00.232160 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11888 11:45:00.232238 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11889 11:45:00.232495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11890 11:45:00.232582 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11891 11:45:00.232836 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11892 11:45:00.232917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11893 11:45:00.233170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11894 11:45:00.233425 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11895 11:45:00.233495 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11896 11:45:00.233748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11897 11:45:00.233829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11898 11:45:00.234079 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11899 11:45:00.234150 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11900 11:45:00.234227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11901 11:45:00.234478 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11902 11:45:00.234735 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11903 11:45:00.234806 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11904 11:45:00.235059 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11905 11:45:00.235138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11906 11:45:00.235391 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11907 11:45:00.235667 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11908 11:45:00.239735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11909 11:45:00.240021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11910 11:45:00.240131 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11911 11:45:00.240237 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11912 11:45:00.240530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11913 11:45:00.240717 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11914 11:45:00.240890 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11915 11:45:00.241031 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11916 11:45:00.241207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11917 11:45:00.241371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11918 11:45:00.241537 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11919 11:45:00.241716 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11920 11:45:00.241886 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11921 11:45:00.242055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11922 11:45:00.242427 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11923 11:45:00.242563 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11924 11:45:00.242737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11925 11:45:00.242875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11926 11:45:00.243047 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11927 11:45:00.243184 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11928 11:45:00.243356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11929 11:45:00.243548 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11930 11:45:00.243791 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11931 11:45:00.247855 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11932 11:45:00.248261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11933 11:45:00.248423 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11934 11:45:00.248576 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11935 11:45:00.248673 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11936 11:45:00.248795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11937 11:45:00.248985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11938 11:45:00.249093 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11939 11:45:00.249405 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11940 11:45:00.249512 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11941 11:45:00.249615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11942 11:45:00.249742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11943 11:45:00.249842 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11944 11:45:00.250147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11945 11:45:00.250256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11946 11:45:00.250360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11947 11:45:00.250470 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11948 11:45:00.250570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
11949 11:45:00.250857 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
11950 11:45:00.251134 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
11951 11:45:00.251216 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
11952 11:45:00.251323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
11953 11:45:00.269866 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
11954 11:45:00.270314 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
11955 11:45:00.270422 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
11956 11:45:00.270511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
11957 11:45:00.270614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
11958 11:45:00.270702 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
11959 11:45:00.270801 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
11960 11:45:00.270904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
11961 11:45:00.271203 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
11962 11:45:00.271321 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
11963 11:45:00.271423 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
11964 11:45:00.271912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
11965 11:45:00.272128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
11966 11:45:00.272346 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
11967 11:45:00.272523 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
11968 11:45:00.272767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
11969 11:45:00.273007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
11970 11:45:00.273225 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
11971 11:45:00.273457 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
11972 11:45:00.273660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
11973 11:45:00.273862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
11974 11:45:00.274032 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
11975 11:45:00.274219 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
11976 11:45:00.274461 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
11977 11:45:00.274656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
11978 11:45:00.274827 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
11979 11:45:00.274976 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
11980 11:45:00.275137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
11981 11:45:00.275342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
11982 11:45:00.275553 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
11983 11:45:00.275698 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
11984 11:45:00.275815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
11985 11:45:00.275931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
11986 11:45:00.276046 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
11987 11:45:00.276212 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
11988 11:45:00.276421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
11989 11:45:00.279935 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
11990 11:45:00.280073 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
11991 11:45:00.280185 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
11992 11:45:00.280286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
11993 11:45:00.280585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
11994 11:45:00.280710 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
11995 11:45:00.281001 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
11996 11:45:00.281108 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
11997 11:45:00.281208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
11998 11:45:00.281508 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
11999 11:45:00.281615 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
12000 11:45:00.281723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
12001 11:45:00.282017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
12002 11:45:00.282126 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
12003 11:45:00.282224 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
12004 11:45:00.282308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
12005 11:45:00.282403 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
12006 11:45:00.282743 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
12007 11:45:00.282956 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
12008 11:45:00.283200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
12009 11:45:00.283631 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
12010 11:45:00.283809 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
12011 11:45:00.284005 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
12012 11:45:00.284141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
12013 11:45:00.284257 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
12014 11:45:00.287774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
12015 11:45:00.288375 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
12016 11:45:00.288595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
12017 11:45:00.288798 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
12018 11:45:00.289008 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
12019 11:45:00.289187 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
12020 11:45:00.289385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
12021 11:45:00.289558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
12022 11:45:00.289739 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
12023 11:45:00.289907 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
12024 11:45:00.290081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
12025 11:45:00.290284 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
12026 11:45:00.290499 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
12027 11:45:00.290712 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
12028 11:45:00.290922 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
12029 11:45:00.291096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
12030 11:45:00.291299 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
12031 11:45:00.291978 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
12032 11:45:00.292170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
12033 11:45:00.292337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
12034 11:45:00.292462 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
12035 11:45:00.292580 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
12036 11:45:00.292696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
12037 11:45:00.292812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
12038 11:45:00.292929 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
12039 11:45:00.293045 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
12040 11:45:00.296064 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
12041 11:45:00.296275 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
12042 11:45:00.296491 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
12043 11:45:00.296662 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
12044 11:45:00.296822 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
12045 11:45:00.297027 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
12046 11:45:00.297215 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
12047 11:45:00.297380 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
12048 11:45:00.297557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
12049 11:45:00.297801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
12050 11:45:00.297946 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
12051 11:45:00.298073 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
12052 11:45:00.298195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
12053 11:45:00.298404 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
12054 11:45:00.298588 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
12055 11:45:00.298776 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
12056 11:45:00.298972 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
12057 11:45:00.299180 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
12058 11:45:00.299398 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
12059 11:45:00.299559 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
12060 11:45:00.299724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
12061 11:45:00.299855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
12062 11:45:00.299972 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
12063 11:45:00.300112 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
12064 11:45:00.303753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
12065 11:45:00.304092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
12066 11:45:00.304219 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
12067 11:45:00.304337 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
12068 11:45:00.304629 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
12069 11:45:00.304726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
12070 11:45:00.305035 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
12071 11:45:00.305148 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
12072 11:45:00.305273 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
12073 11:45:00.305391 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
12074 11:45:00.305504 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
12075 11:45:00.305783 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
12076 11:45:00.305895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
12077 11:45:00.305997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
12078 11:45:00.306360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
12079 11:45:00.306585 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
12080 11:45:00.306828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
12081 11:45:00.307003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
12082 11:45:00.307212 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
12083 11:45:00.307399 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
12084 11:45:00.307633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
12085 11:45:00.307802 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
12086 11:45:00.311735 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
12087 11:45:00.329631 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
12088 11:45:00.330206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
12089 11:45:00.330404 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
12090 11:45:00.330602 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
12091 11:45:00.330782 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
12092 11:45:00.330986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
12093 11:45:00.331160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
12094 11:45:00.331446 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
12095 11:45:00.331655 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
12096 11:45:00.331909 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
12097 11:45:00.332084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
12098 11:45:00.332281 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
12099 11:45:00.332433 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
12100 11:45:00.332603 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
12101 11:45:00.332817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
12102 11:45:00.333064 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
12103 11:45:00.333320 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
12104 11:45:00.333539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
12105 11:45:00.333831 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
12106 11:45:00.334069 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
12107 11:45:00.334271 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
12108 11:45:00.334476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
12109 11:45:00.334690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
12110 11:45:00.334908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
12111 11:45:00.335134 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
12112 11:45:00.335334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
12113 11:45:00.335498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
12114 11:45:00.335626 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
12115 11:45:00.335744 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
12116 11:45:00.335912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
12117 11:45:00.336042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
12118 11:45:00.336230 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
12119 11:45:00.336394 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
12120 11:45:00.336754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
12121 11:45:00.336911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
12122 11:45:00.337033 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
12123 11:45:00.337150 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
12124 11:45:00.337270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
12125 11:45:00.337384 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
12126 11:45:00.337500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
12127 11:45:00.337616 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
12128 11:45:00.337747 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
12129 11:45:00.337863 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
12130 11:45:00.337978 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
12131 11:45:00.338093 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
12132 11:45:00.339843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
12133 11:45:00.340025 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
12134 11:45:00.340400 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
12135 11:45:00.340507 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
12136 11:45:00.340597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
12137 11:45:00.340685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
12138 11:45:00.340791 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
12139 11:45:00.340880 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
12140 11:45:00.340965 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
12141 11:45:00.341264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
12142 11:45:00.341368 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
12143 11:45:00.341468 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
12144 11:45:00.341765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
12145 11:45:00.341869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
12146 11:45:00.341972 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
12147 11:45:00.342074 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
12148 11:45:00.342422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
12149 11:45:00.342536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
12150 11:45:00.342644 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
12151 11:45:00.342748 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
12152 11:45:00.343055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
12153 11:45:00.343161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
12154 11:45:00.343272 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
12155 11:45:00.343377 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
12156 11:45:00.343480 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
12157 11:45:00.347772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
12158 11:45:00.348154 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
12159 11:45:00.348261 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
12160 11:45:00.348347 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
12161 11:45:00.348447 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
12162 11:45:00.348546 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
12163 11:45:00.348649 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
12164 11:45:00.348984 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
12165 11:45:00.349215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
12166 11:45:00.349394 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
12167 11:45:00.349595 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
12168 11:45:00.349790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
12169 11:45:00.349996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
12170 11:45:00.350185 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
12171 11:45:00.350440 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
12172 11:45:00.350633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
12173 11:45:00.351291 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
12174 11:45:00.351519 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
12175 11:45:00.351674 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
12176 11:45:00.351794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
12177 11:45:00.351912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
12178 11:45:00.352026 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
12179 11:45:00.352140 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
12180 11:45:00.352297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
12181 11:45:00.352471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
12182 11:45:00.355799 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
12183 11:45:00.356247 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
12184 11:45:00.356354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
12185 11:45:00.356443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
12186 11:45:00.356542 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
12187 11:45:00.356630 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
12188 11:45:00.356731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
12189 11:45:00.356834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
12190 11:45:00.357134 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
12191 11:45:00.357239 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
12192 11:45:00.357341 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
12193 11:45:00.357656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12194 11:45:00.357760 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12195 11:45:00.357863 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12196 11:45:00.357965 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12197 11:45:00.358299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12198 11:45:00.358544 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12199 11:45:00.358749 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12200 11:45:00.358906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12201 11:45:00.359116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12202 11:45:00.359305 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12203 11:45:00.359500 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12204 11:45:00.359708 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12205 11:45:00.359839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12206 11:45:00.359957 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12207 11:45:00.360073 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12208 11:45:00.367687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12209 11:45:00.368034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12210 11:45:00.368139 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12211 11:45:00.368242 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12212 11:45:00.368342 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12213 11:45:00.368441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12214 11:45:00.368735 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12215 11:45:00.368850 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12216 11:45:00.368955 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12217 11:45:00.369261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12218 11:45:00.369364 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12219 11:45:00.369467 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12220 11:45:00.369558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12221 11:45:00.380602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12222 11:45:00.381052 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12223 11:45:00.381282 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12224 11:45:00.381437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12225 11:45:00.381556 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12226 11:45:00.381651 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12227 11:45:00.381736 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12228 11:45:00.381818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12229 11:45:00.381913 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12230 11:45:00.382011 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12231 11:45:00.382096 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12232 11:45:00.382193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12233 11:45:00.382503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12234 11:45:00.382622 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12235 11:45:00.382709 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12236 11:45:00.382805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12237 11:45:00.382901 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12238 11:45:00.383239 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12239 11:45:00.383432 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12240 11:45:00.383587 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12241 11:45:00.383711 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12242 11:45:00.387774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12243 11:45:00.388164 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12244 11:45:00.388308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12245 11:45:00.388442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12246 11:45:00.388569 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12247 11:45:00.388724 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12248 11:45:00.388854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12249 11:45:00.388978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12250 11:45:00.389157 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12251 11:45:00.389341 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12252 11:45:00.389503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12253 11:45:00.389728 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12254 11:45:00.389929 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12255 11:45:00.390106 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12256 11:45:00.390254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12257 11:45:00.390402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12258 11:45:00.390546 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12259 11:45:00.390689 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12260 11:45:00.390874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12261 11:45:00.391011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12262 11:45:00.391154 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12263 11:45:00.391298 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12264 11:45:00.391443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12265 11:45:00.391585 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12266 11:45:00.391726 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12267 11:45:00.391868 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12268 11:45:00.392010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12269 11:45:00.392187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12270 11:45:00.392325 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12271 11:45:00.392467 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12272 11:45:00.392608 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12273 11:45:00.392750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12274 11:45:00.393106 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12275 11:45:00.395720 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12276 11:45:00.396144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12277 11:45:00.396356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12278 11:45:00.396560 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12279 11:45:00.396718 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12280 11:45:00.396872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12281 11:45:00.397057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12282 11:45:00.397291 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12283 11:45:00.397494 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12284 11:45:00.397720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12285 11:45:00.397947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12286 11:45:00.398142 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12287 11:45:00.398338 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12288 11:45:00.398618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12289 11:45:00.398818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12290 11:45:00.398999 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12291 11:45:00.399173 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12292 11:45:00.399340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12293 11:45:00.399521 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12294 11:45:00.399660 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12295 11:45:00.399777 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12296 11:45:00.399921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12297 11:45:00.400058 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12298 11:45:00.400243 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12299 11:45:00.400366 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12300 11:45:00.400479 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12301 11:45:00.400592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12302 11:45:00.403978 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12303 11:45:00.404094 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12304 11:45:00.404200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12305 11:45:00.404302 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12306 11:45:00.404513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12307 11:45:00.404829 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12308 11:45:00.404946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12309 11:45:00.405034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12310 11:45:00.405373 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12311 11:45:00.405477 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12312 11:45:00.405576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12313 11:45:00.405891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12314 11:45:00.406198 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12315 11:45:00.406300 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12316 11:45:00.406390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12317 11:45:00.406492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12318 11:45:00.406788 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12319 11:45:00.406894 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12320 11:45:00.406996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12321 11:45:00.407327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12322 11:45:00.407539 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12323 11:45:00.407708 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12324 11:45:00.411805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12325 11:45:00.412248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12326 11:45:00.412354 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12327 11:45:00.412445 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12328 11:45:00.412533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12329 11:45:00.412636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12330 11:45:00.412724 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12331 11:45:00.412827 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12332 11:45:00.412927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12333 11:45:00.413214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12334 11:45:00.413320 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12335 11:45:00.413422 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12336 11:45:00.413535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12337 11:45:00.413812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12338 11:45:00.413917 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12339 11:45:00.414019 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12340 11:45:00.414344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12341 11:45:00.414515 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12342 11:45:00.414674 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12343 11:45:00.414813 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12344 11:45:00.414966 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12345 11:45:00.415100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12346 11:45:00.415256 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12347 11:45:00.415393 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12348 11:45:00.415571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12349 11:45:00.415779 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12350 11:45:00.415946 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12351 11:45:00.419769 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12352 11:45:00.420170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12353 11:45:00.420334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12354 11:45:00.420461 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12355 11:45:00.431105 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12356 11:45:00.431582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12357 11:45:00.431791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12358 11:45:00.431976 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12359 11:45:00.432143 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12360 11:45:00.432341 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12361 11:45:00.432493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12362 11:45:00.432656 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12363 11:45:00.432808 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12364 11:45:00.432962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12365 11:45:00.433131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12366 11:45:00.433281 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12367 11:45:00.433400 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12368 11:45:00.433516 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12369 11:45:00.433633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12370 11:45:00.433873 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12371 11:45:00.434041 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12372 11:45:00.434254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12373 11:45:00.434503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12374 11:45:00.434693 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12375 11:45:00.434901 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12376 11:45:00.435116 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12377 11:45:00.435322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12378 11:45:00.435546 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12379 11:45:00.435712 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12380 11:45:00.435894 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12381 11:45:00.436052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12382 11:45:00.436199 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12383 11:45:00.436342 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12384 11:45:00.436487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12385 11:45:00.436629 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12386 11:45:00.436771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12387 11:45:00.436913 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12388 11:45:00.437273 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12389 11:45:00.437410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12390 11:45:00.437559 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12391 11:45:00.439781 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12392 11:45:00.440284 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12393 11:45:00.440392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12394 11:45:00.440503 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12395 11:45:00.440590 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12396 11:45:00.440676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12397 11:45:00.440776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12398 11:45:00.440881 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12399 11:45:00.440983 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12400 11:45:00.441270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12401 11:45:00.441374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12402 11:45:00.441477 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12403 11:45:00.441872 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12404 11:45:00.442109 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12405 11:45:00.442326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12406 11:45:00.442586 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12407 11:45:00.442805 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12408 11:45:00.443017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12409 11:45:00.443244 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12410 11:45:00.443472 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12411 11:45:00.443653 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12412 11:45:00.443816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12413 11:45:00.443943 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12414 11:45:00.444058 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12415 11:45:00.444173 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12416 11:45:00.444313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12417 11:45:00.447887 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12418 11:45:00.448257 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12419 11:45:00.448364 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12420 11:45:00.448457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12421 11:45:00.448791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12422 11:45:00.448894 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12423 11:45:00.448983 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12424 11:45:00.449069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12425 11:45:00.449322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12426 11:45:00.449426 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12427 11:45:00.449513 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12428 11:45:00.449599 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12429 11:45:00.449711 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12430 11:45:00.449800 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12431 11:45:00.449885 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12432 11:45:00.450178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12433 11:45:00.450281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12434 11:45:00.450366 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12435 11:45:00.450450 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12436 11:45:00.450537 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12437 11:45:00.450635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12438 11:45:00.450719 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12439 11:45:00.451043 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12440 11:45:00.451152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12441 11:45:00.451238 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12442 11:45:00.451325 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12443 11:45:00.451411 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12444 11:45:00.451494 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12445 11:45:00.451593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12446 11:45:00.451908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12447 11:45:00.452015 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12448 11:45:00.452100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12449 11:45:00.452181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12450 11:45:00.452261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12451 11:45:00.455793 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12452 11:45:00.456286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12453 11:45:00.456391 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12454 11:45:00.456481 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12455 11:45:00.456579 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12456 11:45:00.456664 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12457 11:45:00.456761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12458 11:45:00.457050 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12459 11:45:00.457155 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12460 11:45:00.457240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12461 11:45:00.457335 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12462 11:45:00.457422 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12463 11:45:00.457522 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12464 11:45:00.457606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12465 11:45:00.457712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12466 11:45:00.457814 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12467 11:45:00.457917 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12468 11:45:00.458017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12469 11:45:00.458305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12470 11:45:00.458399 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12471 11:45:00.458486 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12472 11:45:00.458588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12473 11:45:00.458676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12474 11:45:00.458966 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12475 11:45:00.459059 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12476 11:45:00.459147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12477 11:45:00.459247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12478 11:45:00.459335 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12479 11:45:00.459425 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12480 11:45:00.459530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12481 11:45:00.459615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12482 11:45:00.459699 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12483 11:45:00.463883 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12484 11:45:00.464251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12485 11:45:00.464421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12486 11:45:00.464609 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12487 11:45:00.464785 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12488 11:45:00.464978 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12489 11:45:00.480555 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12490 11:45:00.480994 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12491 11:45:00.481104 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12492 11:45:00.481194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12493 11:45:00.481522 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12494 11:45:00.481752 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12495 11:45:00.481927 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12496 11:45:00.482128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12497 11:45:00.482302 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12498 11:45:00.482478 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12499 11:45:00.482694 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12500 11:45:00.482873 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12501 11:45:00.483050 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12502 11:45:00.483251 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12503 11:45:00.483475 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12504 11:45:00.483655 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12505 11:45:00.483790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12506 11:45:00.483908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12507 11:45:00.484024 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12508 11:45:00.487763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12509 11:45:00.488089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12510 11:45:00.488196 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12511 11:45:00.488331 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12512 11:45:00.488429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12513 11:45:00.488844 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12514 11:45:00.488950 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12515 11:45:00.489042 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12516 11:45:00.489128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12517 11:45:00.489230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12518 11:45:00.489317 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12519 11:45:00.489418 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12520 11:45:00.489509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12521 11:45:00.489997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12522 11:45:00.490113 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12523 11:45:00.490453 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12524 11:45:00.490559 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12525 11:45:00.490646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12526 11:45:00.490731 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12527 11:45:00.490834 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12528 11:45:00.490925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12529 11:45:00.491009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12530 11:45:00.491113 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12531 11:45:00.491204 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12532 11:45:00.491308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12533 11:45:00.491638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12534 11:45:00.495993 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12535 11:45:00.496138 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12536 11:45:00.496229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12537 11:45:00.496527 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12538 11:45:00.496647 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12539 11:45:00.496754 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12540 11:45:00.496856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12541 11:45:00.497154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12542 11:45:00.497309 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12543 11:45:00.497428 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12544 11:45:00.497536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12545 11:45:00.497847 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12546 11:45:00.497967 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12547 11:45:00.498281 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12548 11:45:00.498385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12549 11:45:00.498490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12550 11:45:00.498790 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12551 11:45:00.498909 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12552 11:45:00.499012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12553 11:45:00.499317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12554 11:45:00.499433 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12555 11:45:00.499535 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12556 11:45:00.503769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12557 11:45:00.504218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12558 11:45:00.504327 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12559 11:45:00.504417 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12560 11:45:00.504520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12561 11:45:00.504610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12562 11:45:00.504712 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12563 11:45:00.504813 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12564 11:45:00.505109 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12565 11:45:00.505230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12566 11:45:00.505319 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12567 11:45:00.505421 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12568 11:45:00.505523 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12569 11:45:00.505624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12570 11:45:00.505924 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12571 11:45:00.506047 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12572 11:45:00.506517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12573 11:45:00.506622 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12574 11:45:00.506712 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12575 11:45:00.506803 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12576 11:45:00.507082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12577 11:45:00.507175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12578 11:45:00.507261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12579 11:45:00.507346 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12580 11:45:00.507573 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12581 11:45:00.507735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12582 11:45:00.507833 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12583 11:45:00.507922 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12584 11:45:00.511791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12585 11:45:00.512154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12586 11:45:00.512259 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12587 11:45:00.512349 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12588 11:45:00.512451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12589 11:45:00.512536 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12590 11:45:00.512642 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12591 11:45:00.512740 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12592 11:45:00.512838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12593 11:45:00.513155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12594 11:45:00.513260 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12595 11:45:00.513365 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12596 11:45:00.513453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12597 11:45:00.513553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12598 11:45:00.513664 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12599 11:45:00.513766 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12600 11:45:00.513867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12601 11:45:00.513968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12602 11:45:00.514269 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12603 11:45:00.514372 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12604 11:45:00.514473 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12605 11:45:00.514579 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12606 11:45:00.514874 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12607 11:45:00.514994 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12608 11:45:00.515105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12609 11:45:00.515439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12610 11:45:00.515634 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12611 11:45:00.519705 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12612 11:45:00.520110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12613 11:45:00.520216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12614 11:45:00.520323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12615 11:45:00.520413 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12616 11:45:00.520513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12617 11:45:00.520721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12618 11:45:00.521030 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12619 11:45:00.521127 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12620 11:45:00.521230 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12621 11:45:00.521332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12622 11:45:00.521622 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12623 11:45:00.532522 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12624 11:45:00.532696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12625 11:45:00.533021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12626 11:45:00.533194 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12627 11:45:00.533355 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12628 11:45:00.533545 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12629 11:45:00.533729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12630 11:45:00.533886 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12631 11:45:00.534041 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12632 11:45:00.534212 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12633 11:45:00.534366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12634 11:45:00.534529 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12635 11:45:00.534666 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12636 11:45:00.534846 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12637 11:45:00.535007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12638 11:45:00.535166 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12639 11:45:00.535310 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12640 11:45:00.535476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12641 11:45:00.535648 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12642 11:45:00.535783 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12643 11:45:00.535902 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12644 11:45:00.536018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12645 11:45:00.536132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12646 11:45:00.539749 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12647 11:45:00.540161 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12648 11:45:00.540344 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12649 11:45:00.540499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12650 11:45:00.540684 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12651 11:45:00.540849 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12652 11:45:00.541005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12653 11:45:00.541164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12654 11:45:00.541357 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12655 11:45:00.541523 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12656 11:45:00.541690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12657 11:45:00.541838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12658 11:45:00.542004 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12659 11:45:00.542144 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12660 11:45:00.542290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12661 11:45:00.542449 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12662 11:45:00.542638 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12663 11:45:00.542790 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12664 11:45:00.542950 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12665 11:45:00.543096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12666 11:45:00.543258 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12667 11:45:00.543460 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12668 11:45:00.543633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12669 11:45:00.543763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12670 11:45:00.543880 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12671 11:45:00.543996 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12672 11:45:00.544110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12673 11:45:00.547810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12674 11:45:00.548013 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12675 11:45:00.548407 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12676 11:45:00.548575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12677 11:45:00.548724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12678 11:45:00.548871 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12679 11:45:00.549049 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12680 11:45:00.549206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12681 11:45:00.549360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12682 11:45:00.549512 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12683 11:45:00.549674 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12684 11:45:00.549858 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12685 11:45:00.550013 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12686 11:45:00.550164 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12687 11:45:00.550314 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12688 11:45:00.550462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12689 11:45:00.550613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12690 11:45:00.550799 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12691 11:45:00.550960 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12692 11:45:00.551123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12693 11:45:00.551259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12694 11:45:00.551414 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12695 11:45:00.551603 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12696 11:45:00.551776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12697 11:45:00.551959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12698 11:45:00.552355 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12699 11:45:00.552555 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12700 11:45:00.552733 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12701 11:45:00.552929 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12702 11:45:00.553109 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12703 11:45:00.553277 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12704 11:45:00.553444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12705 11:45:00.555828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12706 11:45:00.556038 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12707 11:45:00.556436 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12708 11:45:00.556578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12709 11:45:00.556697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12710 11:45:00.561823 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12711 11:45:00.561960 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12712 11:45:00.562076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12713 11:45:00.562190 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12714 11:45:00.562304 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12715 11:45:00.562416 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12716 11:45:00.562528 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12717 11:45:00.562640 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12718 11:45:00.562752 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12719 11:45:00.562865 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12720 11:45:00.562980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12721 11:45:00.563094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12722 11:45:00.563207 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12723 11:45:00.563320 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12724 11:45:00.563432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12725 11:45:00.563544 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12726 11:45:00.563656 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12727 11:45:00.563768 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12728 11:45:00.563880 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12729 11:45:00.563992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12730 11:45:00.564104 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12731 11:45:00.564216 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12732 11:45:00.564328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12733 11:45:00.564439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12734 11:45:00.564552 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12735 11:45:00.564664 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12736 11:45:00.564782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12737 11:45:00.564894 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12738 11:45:00.565007 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12739 11:45:00.565120 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12740 11:45:00.565452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12741 11:45:00.565576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12742 11:45:00.565707 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12743 11:45:00.565823 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12744 11:45:00.565935 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12745 11:45:00.566047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12746 11:45:00.566160 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12747 11:45:00.566273 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12748 11:45:00.566386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12749 11:45:00.566498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12750 11:45:00.566610 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12751 11:45:00.566724 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12752 11:45:00.566837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12753 11:45:00.566949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12754 11:45:00.567062 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12755 11:45:00.567174 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12756 11:45:00.567287 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12757 11:45:00.580510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12758 11:45:00.580965 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12759 11:45:00.581096 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12760 11:45:00.581216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12761 11:45:00.581335 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12762 11:45:00.581452 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12763 11:45:00.581570 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12764 11:45:00.581743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12765 11:45:00.581918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12766 11:45:00.582084 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12767 11:45:00.582243 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12768 11:45:00.582401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12769 11:45:00.582557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12770 11:45:00.582707 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12771 11:45:00.582897 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12772 11:45:00.583058 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12773 11:45:00.583246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12774 11:45:00.583451 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12775 11:45:00.583654 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12776 11:45:00.583790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12777 11:45:00.583905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12778 11:45:00.584018 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12779 11:45:00.584161 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12780 11:45:00.584305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12781 11:45:00.584469 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12782 11:45:00.584630 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12783 11:45:00.584772 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12784 11:45:00.587808 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12785 11:45:00.588206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12786 11:45:00.588313 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12787 11:45:00.588403 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12788 11:45:00.588491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12789 11:45:00.588593 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12790 11:45:00.588695 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12791 11:45:00.588796 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12792 11:45:00.588882 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12793 11:45:00.588979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12794 11:45:00.589078 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12795 11:45:00.589383 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12796 11:45:00.589564 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12797 11:45:00.589743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12798 11:45:00.589837 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12799 11:45:00.590285 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12800 11:45:00.590388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12801 11:45:00.590473 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12802 11:45:00.590556 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12803 11:45:00.590833 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12804 11:45:00.590928 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12805 11:45:00.591015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12806 11:45:00.591101 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12807 11:45:00.591204 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12808 11:45:00.591294 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12809 11:45:00.591379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12810 11:45:00.591486 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12811 11:45:00.591573 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12812 11:45:00.591658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12813 11:45:00.595751 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12814 11:45:00.596187 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12815 11:45:00.596344 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12816 11:45:00.596498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12817 11:45:00.596685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12818 11:45:00.596843 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12819 11:45:00.596991 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12820 11:45:00.597139 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12821 11:45:00.597337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12822 11:45:00.597505 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12823 11:45:00.597681 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12824 11:45:00.597849 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12825 11:45:00.597985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12826 11:45:00.598131 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12827 11:45:00.598278 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12828 11:45:00.598410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12829 11:45:00.598571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12830 11:45:00.598726 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12831 11:45:00.598883 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12832 11:45:00.599048 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12833 11:45:00.599210 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12834 11:45:00.599335 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12835 11:45:00.599492 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12836 11:45:00.599678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12837 11:45:00.599815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12838 11:45:00.599962 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12839 11:45:00.600083 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12840 11:45:00.600251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12841 11:45:00.600426 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12842 11:45:00.600584 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12843 11:45:00.603832 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12844 11:45:00.604009 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12845 11:45:00.604354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12846 11:45:00.604490 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12847 11:45:00.604614 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12848 11:45:00.604777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12849 11:45:00.604906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12850 11:45:00.605057 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12851 11:45:00.605219 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12852 11:45:00.605411 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12853 11:45:00.605573 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12854 11:45:00.605749 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12855 11:45:00.605944 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12856 11:45:00.606110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12857 11:45:00.606296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12858 11:45:00.606469 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12859 11:45:00.606630 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12860 11:45:00.606820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12861 11:45:00.606979 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12862 11:45:00.607136 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12863 11:45:00.607291 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12864 11:45:00.607444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12865 11:45:00.607634 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12866 11:45:00.607788 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12867 11:45:00.607931 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12868 11:45:00.608077 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12869 11:45:00.608221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12870 11:45:00.608361 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12871 11:45:00.608502 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12872 11:45:00.608646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12873 11:45:00.611826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12874 11:45:00.612298 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12875 11:45:00.612493 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12876 11:45:00.612705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12877 11:45:00.612879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12878 11:45:00.613074 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12879 11:45:00.613246 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12880 11:45:00.613415 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12881 11:45:00.613565 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12882 11:45:00.613738 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12883 11:45:00.613900 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12884 11:45:00.614094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12885 11:45:00.614234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12886 11:45:00.614352 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12887 11:45:00.614469 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12888 11:45:00.614596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12889 11:45:00.614727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12890 11:45:00.614872 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12891 11:45:00.634090 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12892 11:45:00.634419 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12893 11:45:00.634867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12894 11:45:00.634977 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12895 11:45:00.635069 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12896 11:45:00.635157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12897 11:45:00.635261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12898 11:45:00.635349 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12899 11:45:00.635433 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12900 11:45:00.635532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12901 11:45:00.635619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12902 11:45:00.635926 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12903 11:45:00.636047 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12904 11:45:00.636149 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12905 11:45:00.636458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12906 11:45:00.636562 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12907 11:45:00.636664 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12908 11:45:00.636752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12909 11:45:00.636856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12910 11:45:00.637169 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12911 11:45:00.637546 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12912 11:45:00.637656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12913 11:45:00.638012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12914 11:45:00.638129 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12915 11:45:00.638230 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12916 11:45:00.638328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12917 11:45:00.638632 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12918 11:45:00.638748 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12919 11:45:00.638853 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12920 11:45:00.639038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12921 11:45:00.639357 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12922 11:45:00.639475 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12923 11:45:00.643746 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12924 11:45:00.644093 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12925 11:45:00.644200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12926 11:45:00.644309 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12927 11:45:00.644419 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12928 11:45:00.644785 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12929 11:45:00.644990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12930 11:45:00.645198 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12931 11:45:00.645371 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12932 11:45:00.645576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12933 11:45:00.645817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12934 11:45:00.645993 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12935 11:45:00.646163 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12936 11:45:00.646331 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12937 11:45:00.646497 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12938 11:45:00.646695 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12939 11:45:00.646866 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12940 11:45:00.647037 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12941 11:45:00.647209 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12942 11:45:00.647376 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12943 11:45:00.647606 arm64_sve-ptrace pass
12944 11:45:00.647754 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12945 11:45:00.647878 arm64_sve-probe-vls_All_vector_lengths_valid pass
12946 11:45:00.647995 arm64_sve-probe-vls pass
12947 11:45:00.648110 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12948 11:45:00.648223 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
12949 11:45:00.651792 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
12950 11:45:00.651945 arm64_vec-syscfg_SVE_current_VL_is_64 pass
12951 11:45:00.652247 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
12952 11:45:00.652379 arm64_vec-syscfg_SVE_prctl_set_min_max pass
12953 11:45:00.652471 arm64_vec-syscfg_SVE_vector_length_used_default pass
12954 11:45:00.652574 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
12955 11:45:00.652665 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
12956 11:45:00.652764 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
12957 11:45:00.652864 arm64_vec-syscfg_SME_default_vector_length_32 pass
12958 11:45:00.652968 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
12959 11:45:00.653354 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
12960 11:45:00.653459 arm64_vec-syscfg_SME_current_VL_is_32 pass
12961 11:45:00.653558 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
12962 11:45:00.653666 arm64_vec-syscfg_SME_prctl_set_min_max pass
12963 11:45:00.653986 arm64_vec-syscfg_SME_vector_length_used_default pass
12964 11:45:00.654093 arm64_vec-syscfg_SME_vector_length_was_inherited pass
12965 11:45:00.654184 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
12966 11:45:00.654473 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
12967 11:45:00.654577 arm64_vec-syscfg pass
12968 11:45:00.654662 arm64_za-fork_fork_test pass
12969 11:45:00.654747 arm64_za-fork pass
12970 11:45:00.654833 arm64_za-ptrace_Set_VL_16 pass
12971 11:45:00.654931 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
12972 11:45:00.655017 arm64_za-ptrace_Data_match_for_VL_16 pass
12973 11:45:00.655100 arm64_za-ptrace_Set_VL_32 pass
12974 11:45:00.655184 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
12975 11:45:00.655285 arm64_za-ptrace_Data_match_for_VL_32 pass
12976 11:45:00.655372 arm64_za-ptrace_Set_VL_48 pass
12977 11:45:00.655456 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
12978 11:45:00.655557 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
12979 11:45:00.655645 arm64_za-ptrace_Set_VL_64 pass
12980 11:45:00.659737 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
12981 11:45:00.660178 arm64_za-ptrace_Data_match_for_VL_64 pass
12982 11:45:00.660284 arm64_za-ptrace_Set_VL_80 pass
12983 11:45:00.660373 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
12984 11:45:00.660458 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
12985 11:45:00.660544 arm64_za-ptrace_Set_VL_96 pass
12986 11:45:00.660642 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
12987 11:45:00.660729 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
12988 11:45:00.660813 arm64_za-ptrace_Set_VL_112 pass
12989 11:45:00.660898 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
12990 11:45:00.660997 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
12991 11:45:00.661082 arm64_za-ptrace_Set_VL_128 pass
12992 11:45:00.661179 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
12993 11:45:00.661263 arm64_za-ptrace_Data_match_for_VL_128 pass
12994 11:45:00.661361 arm64_za-ptrace_Set_VL_144 pass
12995 11:45:00.661447 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
12996 11:45:00.661545 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
12997 11:45:00.661645 arm64_za-ptrace_Set_VL_160 pass
12998 11:45:00.661753 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
12999 11:45:00.662054 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
13000 11:45:00.662174 arm64_za-ptrace_Set_VL_176 pass
13001 11:45:00.662281 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
13002 11:45:00.662383 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
13003 11:45:00.662485 arm64_za-ptrace_Set_VL_192 pass
13004 11:45:00.662575 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
13005 11:45:00.662675 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
13006 11:45:00.662762 arm64_za-ptrace_Set_VL_208 pass
13007 11:45:00.662861 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
13008 11:45:00.663147 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
13009 11:45:00.663253 arm64_za-ptrace_Set_VL_224 pass
13010 11:45:00.663339 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
13011 11:45:00.663439 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
13012 11:45:00.663529 arm64_za-ptrace_Set_VL_240 pass
13013 11:45:00.663631 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
13014 11:45:00.667972 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
13015 11:45:00.668096 arm64_za-ptrace_Set_VL_256 pass
13016 11:45:00.668205 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
13017 11:45:00.668294 arm64_za-ptrace_Data_match_for_VL_256 pass
13018 11:45:00.668379 arm64_za-ptrace_Set_VL_272 pass
13019 11:45:00.668477 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
13020 11:45:00.668562 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
13021 11:45:00.668645 arm64_za-ptrace_Set_VL_288 pass
13022 11:45:00.668740 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
13023 11:45:00.668838 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
13024 11:45:00.668924 arm64_za-ptrace_Set_VL_304 pass
13025 11:45:00.669022 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
13026 11:45:00.669121 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
13027 11:45:00.669219 arm64_za-ptrace_Set_VL_320 pass
13028 11:45:00.669305 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
13029 11:45:00.669746 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
13030 11:45:00.669961 arm64_za-ptrace_Set_VL_336 pass
13031 11:45:00.670124 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
13032 11:45:00.670325 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
13033 11:45:00.670499 arm64_za-ptrace_Set_VL_352 pass
13034 11:45:00.670667 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
13035 11:45:00.670832 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
13036 11:45:00.671000 arm64_za-ptrace_Set_VL_368 pass
13037 11:45:00.671168 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
13038 11:45:00.671357 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
13039 11:45:00.671491 arm64_za-ptrace_Set_VL_384 pass
13040 11:45:00.671608 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
13041 11:45:00.671722 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
13042 11:45:00.671835 arm64_za-ptrace_Set_VL_400 pass
13043 11:45:00.671949 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
13044 11:45:00.672061 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
13045 11:45:00.672174 arm64_za-ptrace_Set_VL_416 pass
13046 11:45:00.672285 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
13047 11:45:00.672396 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
13048 11:45:00.672532 arm64_za-ptrace_Set_VL_432 pass
13049 11:45:00.675745 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
13050 11:45:00.676058 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
13051 11:45:00.676164 arm64_za-ptrace_Set_VL_448 pass
13052 11:45:00.676268 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
13053 11:45:00.676356 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
13054 11:45:00.676440 arm64_za-ptrace_Set_VL_464 pass
13055 11:45:00.676542 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
13056 11:45:00.676630 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
13057 11:45:00.676732 arm64_za-ptrace_Set_VL_480 pass
13058 11:45:00.676834 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
13059 11:45:00.676937 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
13060 11:45:00.677217 arm64_za-ptrace_Set_VL_496 pass
13061 11:45:00.677320 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
13062 11:45:00.694430 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
13063 11:45:00.694666 arm64_za-ptrace_Set_VL_512 pass
13064 11:45:00.694975 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
13065 11:45:00.695080 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
13066 11:45:00.695170 arm64_za-ptrace_Set_VL_528 pass
13067 11:45:00.695259 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
13068 11:45:00.695346 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
13069 11:45:00.695436 arm64_za-ptrace_Set_VL_544 pass
13070 11:45:00.695541 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
13071 11:45:00.695631 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
13072 11:45:00.695717 arm64_za-ptrace_Set_VL_560 pass
13073 11:45:00.695943 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
13074 11:45:00.696036 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
13075 11:45:00.696139 arm64_za-ptrace_Set_VL_576 pass
13076 11:45:00.696323 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
13077 11:45:00.696415 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
13078 11:45:00.696499 arm64_za-ptrace_Set_VL_592 pass
13079 11:45:00.696581 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
13080 11:45:00.696689 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
13081 11:45:00.696778 arm64_za-ptrace_Set_VL_608 pass
13082 11:45:00.696862 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
13083 11:45:00.696963 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
13084 11:45:00.697050 arm64_za-ptrace_Set_VL_624 pass
13085 11:45:00.697133 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
13086 11:45:00.697217 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
13087 11:45:00.697314 arm64_za-ptrace_Set_VL_640 pass
13088 11:45:00.697397 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
13089 11:45:00.697481 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
13090 11:45:00.697562 arm64_za-ptrace_Set_VL_656 pass
13091 11:45:00.697666 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
13092 11:45:00.697753 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
13093 11:45:00.697835 arm64_za-ptrace_Set_VL_672 pass
13094 11:45:00.697934 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
13095 11:45:00.698018 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
13096 11:45:00.698101 arm64_za-ptrace_Set_VL_688 pass
13097 11:45:00.698199 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
13098 11:45:00.698285 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
13099 11:45:00.698384 arm64_za-ptrace_Set_VL_704 pass
13100 11:45:00.698470 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
13101 11:45:00.698565 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
13102 11:45:00.698648 arm64_za-ptrace_Set_VL_720 pass
13103 11:45:00.698744 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
13104 11:45:00.699303 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
13105 11:45:00.699409 arm64_za-ptrace_Set_VL_736 pass
13106 11:45:00.699497 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
13107 11:45:00.699581 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
13108 11:45:00.699663 arm64_za-ptrace_Set_VL_752 pass
13109 11:45:00.699760 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
13110 11:45:00.699846 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
13111 11:45:00.699935 arm64_za-ptrace_Set_VL_768 pass
13112 11:45:00.707843 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
13113 11:45:00.708047 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
13114 11:45:00.708137 arm64_za-ptrace_Set_VL_784 pass
13115 11:45:00.708226 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
13116 11:45:00.708314 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
13117 11:45:00.708402 arm64_za-ptrace_Set_VL_800 pass
13118 11:45:00.708489 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
13119 11:45:00.708578 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
13120 11:45:00.708668 arm64_za-ptrace_Set_VL_816 pass
13121 11:45:00.708756 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
13122 11:45:00.708843 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
13123 11:45:00.708927 arm64_za-ptrace_Set_VL_832 pass
13124 11:45:00.709014 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
13125 11:45:00.709095 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
13126 11:45:00.709177 arm64_za-ptrace_Set_VL_848 pass
13127 11:45:00.709258 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
13128 11:45:00.709339 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
13129 11:45:00.709420 arm64_za-ptrace_Set_VL_864 pass
13130 11:45:00.709502 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
13131 11:45:00.709583 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
13132 11:45:00.709674 arm64_za-ptrace_Set_VL_880 pass
13133 11:45:00.709755 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
13134 11:45:00.709834 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
13135 11:45:00.709914 arm64_za-ptrace_Set_VL_896 pass
13136 11:45:00.709994 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
13137 11:45:00.710074 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
13138 11:45:00.710157 arm64_za-ptrace_Set_VL_912 pass
13139 11:45:00.710236 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
13140 11:45:00.710319 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
13141 11:45:00.710402 arm64_za-ptrace_Set_VL_928 pass
13142 11:45:00.710483 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
13143 11:45:00.710565 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
13144 11:45:00.710648 arm64_za-ptrace_Set_VL_944 pass
13145 11:45:00.710734 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
13146 11:45:00.710818 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
13147 11:45:00.711966 arm64_za-ptrace_Set_VL_960 pass
13148 11:45:00.712077 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
13149 11:45:00.712183 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
13150 11:45:00.712268 arm64_za-ptrace_Set_VL_976 pass
13151 11:45:00.712354 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
13152 11:45:00.712451 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
13153 11:45:00.712551 arm64_za-ptrace_Set_VL_992 pass
13154 11:45:00.712637 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
13155 11:45:00.712736 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
13156 11:45:00.712837 arm64_za-ptrace_Set_VL_1008 pass
13157 11:45:00.713163 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
13158 11:45:00.713269 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
13159 11:45:00.713359 arm64_za-ptrace_Set_VL_1024 pass
13160 11:45:00.713465 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
13161 11:45:00.713567 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
13162 11:45:00.713677 arm64_za-ptrace_Set_VL_1040 pass
13163 11:45:00.713777 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
13164 11:45:00.714074 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
13165 11:45:00.714180 arm64_za-ptrace_Set_VL_1056 pass
13166 11:45:00.714286 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
13167 11:45:00.714389 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
13168 11:45:00.714488 arm64_za-ptrace_Set_VL_1072 pass
13169 11:45:00.714785 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
13170 11:45:00.714888 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
13171 11:45:00.714992 arm64_za-ptrace_Set_VL_1088 pass
13172 11:45:00.715094 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
13173 11:45:00.715182 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
13174 11:45:00.715280 arm64_za-ptrace_Set_VL_1104 pass
13175 11:45:00.715577 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
13176 11:45:00.719714 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
13177 11:45:00.720033 arm64_za-ptrace_Set_VL_1120 pass
13178 11:45:00.720137 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
13179 11:45:00.720226 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
13180 11:45:00.720327 arm64_za-ptrace_Set_VL_1136 pass
13181 11:45:00.720414 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
13182 11:45:00.720516 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
13183 11:45:00.720606 arm64_za-ptrace_Set_VL_1152 pass
13184 11:45:00.720709 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
13185 11:45:00.721206 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
13186 11:45:00.721543 arm64_za-ptrace_Set_VL_1168 pass
13187 11:45:00.721655 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
13188 11:45:00.721745 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
13189 11:45:00.721831 arm64_za-ptrace_Set_VL_1184 pass
13190 11:45:00.721915 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
13191 11:45:00.722018 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
13192 11:45:00.722107 arm64_za-ptrace_Set_VL_1200 pass
13193 11:45:00.722193 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13194 11:45:00.722276 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13195 11:45:00.722360 arm64_za-ptrace_Set_VL_1216 pass
13196 11:45:00.722460 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13197 11:45:00.722545 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13198 11:45:00.722629 arm64_za-ptrace_Set_VL_1232 pass
13199 11:45:00.722727 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13200 11:45:00.722814 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13201 11:45:00.722913 arm64_za-ptrace_Set_VL_1248 pass
13202 11:45:00.723015 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13203 11:45:00.723114 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13204 11:45:00.723492 arm64_za-ptrace_Set_VL_1264 pass
13205 11:45:00.723598 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13206 11:45:00.723706 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13207 11:45:00.727745 arm64_za-ptrace_Set_VL_1280 pass
13208 11:45:00.728076 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13209 11:45:00.728187 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13210 11:45:00.728277 arm64_za-ptrace_Set_VL_1296 pass
13211 11:45:00.728434 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13212 11:45:00.728555 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13213 11:45:00.728647 arm64_za-ptrace_Set_VL_1312 pass
13214 11:45:00.728748 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13215 11:45:00.728835 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13216 11:45:00.728936 arm64_za-ptrace_Set_VL_1328 pass
13217 11:45:00.729026 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13218 11:45:00.729124 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13219 11:45:00.729388 arm64_za-ptrace_Set_VL_1344 pass
13220 11:45:00.729479 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13221 11:45:00.729578 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13222 11:45:00.729673 arm64_za-ptrace_Set_VL_1360 pass
13223 11:45:00.729772 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13224 11:45:00.729871 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13225 11:45:00.729971 arm64_za-ptrace_Set_VL_1376 pass
13226 11:45:00.730278 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13227 11:45:00.730381 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13228 11:45:00.730480 arm64_za-ptrace_Set_VL_1392 pass
13229 11:45:00.730584 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13230 11:45:00.730688 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13231 11:45:00.730787 arm64_za-ptrace_Set_VL_1408 pass
13232 11:45:00.730888 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13233 11:45:00.731099 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13234 11:45:00.731216 arm64_za-ptrace_Set_VL_1424 pass
13235 11:45:00.731315 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13236 11:45:00.731609 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13237 11:45:00.735766 arm64_za-ptrace_Set_VL_1440 pass
13238 11:45:00.736296 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13239 11:45:00.736487 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13240 11:45:00.736706 arm64_za-ptrace_Set_VL_1456 pass
13241 11:45:00.736905 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13242 11:45:00.737135 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13243 11:45:00.737348 arm64_za-ptrace_Set_VL_1472 pass
13244 11:45:00.737566 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13245 11:45:00.737738 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13246 11:45:00.737862 arm64_za-ptrace_Set_VL_1488 pass
13247 11:45:00.737979 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13248 11:45:00.738101 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13249 11:45:00.738245 arm64_za-ptrace_Set_VL_1504 pass
13250 11:45:00.738365 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13251 11:45:00.738508 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13252 11:45:00.738631 arm64_za-ptrace_Set_VL_1520 pass
13253 11:45:00.738746 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13254 11:45:00.738860 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13255 11:45:00.738974 arm64_za-ptrace_Set_VL_1536 pass
13256 11:45:00.739091 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13257 11:45:00.754188 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13258 11:45:00.754503 arm64_za-ptrace_Set_VL_1552 pass
13259 11:45:00.754685 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13260 11:45:00.755154 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13261 11:45:00.755358 arm64_za-ptrace_Set_VL_1568 pass
13262 11:45:00.755576 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13263 11:45:00.755792 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13264 11:45:00.755998 arm64_za-ptrace_Set_VL_1584 pass
13265 11:45:00.756184 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13266 11:45:00.756347 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13267 11:45:00.756501 arm64_za-ptrace_Set_VL_1600 pass
13268 11:45:00.756663 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13269 11:45:00.756787 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13270 11:45:00.756903 arm64_za-ptrace_Set_VL_1616 pass
13271 11:45:00.757015 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13272 11:45:00.757130 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13273 11:45:00.757243 arm64_za-ptrace_Set_VL_1632 pass
13274 11:45:00.757356 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13275 11:45:00.757469 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13276 11:45:00.757581 arm64_za-ptrace_Set_VL_1648 pass
13277 11:45:00.757743 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13278 11:45:00.757952 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13279 11:45:00.758182 arm64_za-ptrace_Set_VL_1664 pass
13280 11:45:00.758354 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13281 11:45:00.758499 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13282 11:45:00.758642 arm64_za-ptrace_Set_VL_1680 pass
13283 11:45:00.758785 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13284 11:45:00.758927 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13285 11:45:00.759071 arm64_za-ptrace_Set_VL_1696 pass
13286 11:45:00.759217 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13287 11:45:00.759358 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13288 11:45:00.759501 arm64_za-ptrace_Set_VL_1712 pass
13289 11:45:00.759641 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13290 11:45:00.759782 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13291 11:45:00.759924 arm64_za-ptrace_Set_VL_1728 pass
13292 11:45:00.760106 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13293 11:45:00.760242 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13294 11:45:00.760384 arm64_za-ptrace_Set_VL_1744 pass
13295 11:45:00.760525 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13296 11:45:00.760665 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13297 11:45:00.760805 arm64_za-ptrace_Set_VL_1760 pass
13298 11:45:00.760944 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13299 11:45:00.761087 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13300 11:45:00.761231 arm64_za-ptrace_Set_VL_1776 pass
13301 11:45:00.761372 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13302 11:45:00.763956 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13303 11:45:00.764069 arm64_za-ptrace_Set_VL_1792 pass
13304 11:45:00.764177 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13305 11:45:00.764281 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13306 11:45:00.764380 arm64_za-ptrace_Set_VL_1808 pass
13307 11:45:00.764480 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13308 11:45:00.765264 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13309 11:45:00.765371 arm64_za-ptrace_Set_VL_1824 pass
13310 11:45:00.765459 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13311 11:45:00.765544 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13312 11:45:00.765627 arm64_za-ptrace_Set_VL_1840 pass
13313 11:45:00.765722 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13314 11:45:00.765806 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13315 11:45:00.766098 arm64_za-ptrace_Set_VL_1856 pass
13316 11:45:00.766205 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13317 11:45:00.766290 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13318 11:45:00.766373 arm64_za-ptrace_Set_VL_1872 pass
13319 11:45:00.766454 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13320 11:45:00.766538 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13321 11:45:00.766621 arm64_za-ptrace_Set_VL_1888 pass
13322 11:45:00.766719 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13323 11:45:00.766805 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13324 11:45:00.766888 arm64_za-ptrace_Set_VL_1904 pass
13325 11:45:00.766971 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13326 11:45:00.767057 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13327 11:45:00.767168 arm64_za-ptrace_Set_VL_1920 pass
13328 11:45:00.767257 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13329 11:45:00.767346 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13330 11:45:00.767447 arm64_za-ptrace_Set_VL_1936 pass
13331 11:45:00.767537 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13332 11:45:00.771758 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13333 11:45:00.771968 arm64_za-ptrace_Set_VL_1952 pass
13334 11:45:00.772407 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13335 11:45:00.772621 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13336 11:45:00.772811 arm64_za-ptrace_Set_VL_1968 pass
13337 11:45:00.772982 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13338 11:45:00.773193 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13339 11:45:00.773376 arm64_za-ptrace_Set_VL_1984 pass
13340 11:45:00.773620 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13341 11:45:00.773837 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13342 11:45:00.774053 arm64_za-ptrace_Set_VL_2000 pass
13343 11:45:00.774205 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13344 11:45:00.774353 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13345 11:45:00.774506 arm64_za-ptrace_Set_VL_2016 pass
13346 11:45:00.774640 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13347 11:45:00.774793 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13348 11:45:00.774951 arm64_za-ptrace_Set_VL_2032 pass
13349 11:45:00.775106 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13350 11:45:00.775307 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13351 11:45:00.775460 arm64_za-ptrace_Set_VL_2048 pass
13352 11:45:00.775589 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13353 11:45:00.775704 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13354 11:45:00.775815 arm64_za-ptrace_Set_VL_2064 pass
13355 11:45:00.775926 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13356 11:45:00.776037 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13357 11:45:00.776152 arm64_za-ptrace_Set_VL_2080 pass
13358 11:45:00.776265 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13359 11:45:00.776377 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13360 11:45:00.776488 arm64_za-ptrace_Set_VL_2096 pass
13361 11:45:00.776599 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13362 11:45:00.776710 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13363 11:45:00.776823 arm64_za-ptrace_Set_VL_2112 pass
13364 11:45:00.776934 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13365 11:45:00.777075 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13366 11:45:00.779771 arm64_za-ptrace_Set_VL_2128 pass
13367 11:45:00.780248 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13368 11:45:00.780451 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13369 11:45:00.780642 arm64_za-ptrace_Set_VL_2144 pass
13370 11:45:00.780868 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13371 11:45:00.781109 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13372 11:45:00.781333 arm64_za-ptrace_Set_VL_2160 pass
13373 11:45:00.781549 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13374 11:45:00.781787 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13375 11:45:00.781992 arm64_za-ptrace_Set_VL_2176 pass
13376 11:45:00.782201 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13377 11:45:00.782393 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13378 11:45:00.782557 arm64_za-ptrace_Set_VL_2192 pass
13379 11:45:00.782716 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13380 11:45:00.782914 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13381 11:45:00.783081 arm64_za-ptrace_Set_VL_2208 pass
13382 11:45:00.783241 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13383 11:45:00.783401 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13384 11:45:00.783579 arm64_za-ptrace_Set_VL_2224 pass
13385 11:45:00.783767 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13386 11:45:00.783977 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13387 11:45:00.784142 arm64_za-ptrace_Set_VL_2240 pass
13388 11:45:00.784271 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13389 11:45:00.784394 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13390 11:45:00.784518 arm64_za-ptrace_Set_VL_2256 pass
13391 11:45:00.784672 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13392 11:45:00.784855 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13393 11:45:00.785055 arm64_za-ptrace_Set_VL_2272 pass
13394 11:45:00.785245 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13395 11:45:00.785434 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13396 11:45:00.785637 arm64_za-ptrace_Set_VL_2288 pass
13397 11:45:00.786666 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13398 11:45:00.786833 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13399 11:45:00.786979 arm64_za-ptrace_Set_VL_2304 pass
13400 11:45:00.787903 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13401 11:45:00.788210 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13402 11:45:00.788316 arm64_za-ptrace_Set_VL_2320 pass
13403 11:45:00.788421 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13404 11:45:00.788510 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13405 11:45:00.788597 arm64_za-ptrace_Set_VL_2336 pass
13406 11:45:00.788699 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13407 11:45:00.788790 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13408 11:45:00.788887 arm64_za-ptrace_Set_VL_2352 pass
13409 11:45:00.788969 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13410 11:45:00.789064 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13411 11:45:00.789148 arm64_za-ptrace_Set_VL_2368 pass
13412 11:45:00.789246 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13413 11:45:00.789330 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13414 11:45:00.789428 arm64_za-ptrace_Set_VL_2384 pass
13415 11:45:00.789529 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13416 11:45:00.789629 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13417 11:45:00.789736 arm64_za-ptrace_Set_VL_2400 pass
13418 11:45:00.789835 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13419 11:45:00.790248 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13420 11:45:00.790353 arm64_za-ptrace_Set_VL_2416 pass
13421 11:45:00.790437 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13422 11:45:00.790534 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13423 11:45:00.790621 arm64_za-ptrace_Set_VL_2432 pass
13424 11:45:00.790721 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13425 11:45:00.790806 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13426 11:45:00.791177 arm64_za-ptrace_Set_VL_2448 pass
13427 11:45:00.791302 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13428 11:45:00.791394 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13429 11:45:00.791474 arm64_za-ptrace_Set_VL_2464 pass
13430 11:45:00.791542 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13431 11:45:00.791614 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13432 11:45:00.791675 arm64_za-ptrace_Set_VL_2480 pass
13433 11:45:00.796044 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13434 11:45:00.796417 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13435 11:45:00.796529 arm64_za-ptrace_Set_VL_2496 pass
13436 11:45:00.796636 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13437 11:45:00.796745 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13438 11:45:00.796820 arm64_za-ptrace_Set_VL_2512 pass
13439 11:45:00.796896 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13440 11:45:00.796970 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13441 11:45:00.797242 arm64_za-ptrace_Set_VL_2528 pass
13442 11:45:00.797340 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13443 11:45:00.797432 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13444 11:45:00.797509 arm64_za-ptrace_Set_VL_2544 pass
13445 11:45:00.797583 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13446 11:45:00.797668 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13447 11:45:00.797744 arm64_za-ptrace_Set_VL_2560 pass
13448 11:45:00.797835 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13449 11:45:00.797922 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13450 11:45:00.816798 arm64_za-ptrace_Set_VL_2576 pass
13451 11:45:00.817371 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13452 11:45:00.817572 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13453 11:45:00.817753 arm64_za-ptrace_Set_VL_2592 pass
13454 11:45:00.817912 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13455 11:45:00.818073 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13456 11:45:00.818232 arm64_za-ptrace_Set_VL_2608 pass
13457 11:45:00.818393 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13458 11:45:00.818589 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13459 11:45:00.818803 arm64_za-ptrace_Set_VL_2624 pass
13460 11:45:00.819000 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13461 11:45:00.819215 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13462 11:45:00.819428 arm64_za-ptrace_Set_VL_2640 pass
13463 11:45:00.819596 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13464 11:45:00.819723 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13465 11:45:00.819849 arm64_za-ptrace_Set_VL_2656 pass
13466 11:45:00.820010 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13467 11:45:00.820148 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13468 11:45:00.820275 arm64_za-ptrace_Set_VL_2672 pass
13469 11:45:00.820431 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13470 11:45:00.820564 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13471 11:45:00.820688 arm64_za-ptrace_Set_VL_2688 pass
13472 11:45:00.820811 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13473 11:45:00.820930 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13474 11:45:00.821051 arm64_za-ptrace_Set_VL_2704 pass
13475 11:45:00.821170 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13476 11:45:00.821287 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13477 11:45:00.821408 arm64_za-ptrace_Set_VL_2720 pass
13478 11:45:00.821523 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13479 11:45:00.821637 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13480 11:45:00.823688 arm64_za-ptrace_Set_VL_2736 pass
13481 11:45:00.823800 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13482 11:45:00.824090 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13483 11:45:00.824197 arm64_za-ptrace_Set_VL_2752 pass
13484 11:45:00.824300 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13485 11:45:00.824389 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13486 11:45:00.824476 arm64_za-ptrace_Set_VL_2768 pass
13487 11:45:00.824581 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13488 11:45:00.824672 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13489 11:45:00.824776 arm64_za-ptrace_Set_VL_2784 pass
13490 11:45:00.824865 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13491 11:45:00.824963 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13492 11:45:00.825048 arm64_za-ptrace_Set_VL_2800 pass
13493 11:45:00.825135 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13494 11:45:00.825237 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13495 11:45:00.825323 arm64_za-ptrace_Set_VL_2816 pass
13496 11:45:00.825411 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13497 11:45:00.825497 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13498 11:45:00.825601 arm64_za-ptrace_Set_VL_2832 pass
13499 11:45:00.825698 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13500 11:45:00.825786 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13501 11:45:00.825872 arm64_za-ptrace_Set_VL_2848 pass
13502 11:45:00.825971 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13503 11:45:00.826056 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13504 11:45:00.826144 arm64_za-ptrace_Set_VL_2864 pass
13505 11:45:00.826234 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13506 11:45:00.826316 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13507 11:45:00.826415 arm64_za-ptrace_Set_VL_2880 pass
13508 11:45:00.826503 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13509 11:45:00.826590 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13510 11:45:00.826672 arm64_za-ptrace_Set_VL_2896 pass
13511 11:45:00.826754 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13512 11:45:00.826855 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13513 11:45:00.826942 arm64_za-ptrace_Set_VL_2912 pass
13514 11:45:00.827024 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13515 11:45:00.827109 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13516 11:45:00.827201 arm64_za-ptrace_Set_VL_2928 pass
13517 11:45:00.827287 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13518 11:45:00.827396 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13519 11:45:00.827486 arm64_za-ptrace_Set_VL_2944 pass
13520 11:45:00.827572 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13521 11:45:00.827656 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13522 11:45:00.827740 arm64_za-ptrace_Set_VL_2960 pass
13523 11:45:00.827830 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13524 11:45:00.827918 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13525 11:45:00.828018 arm64_za-ptrace_Set_VL_2976 pass
13526 11:45:00.831794 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13527 11:45:00.831906 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13528 11:45:00.832189 arm64_za-ptrace_Set_VL_2992 pass
13529 11:45:00.832284 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13530 11:45:00.832368 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13531 11:45:00.832450 arm64_za-ptrace_Set_VL_3008 pass
13532 11:45:00.832533 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13533 11:45:00.832631 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13534 11:45:00.832714 arm64_za-ptrace_Set_VL_3024 pass
13535 11:45:00.832797 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13536 11:45:00.832880 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13537 11:45:00.832978 arm64_za-ptrace_Set_VL_3040 pass
13538 11:45:00.833304 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13539 11:45:00.833523 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13540 11:45:00.833737 arm64_za-ptrace_Set_VL_3056 pass
13541 11:45:00.833945 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13542 11:45:00.834117 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13543 11:45:00.834255 arm64_za-ptrace_Set_VL_3072 pass
13544 11:45:00.834432 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13545 11:45:00.834668 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13546 11:45:00.834875 arm64_za-ptrace_Set_VL_3088 pass
13547 11:45:00.835107 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13548 11:45:00.835334 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13549 11:45:00.835517 arm64_za-ptrace_Set_VL_3104 pass
13550 11:45:00.835692 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13551 11:45:00.835861 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13552 11:45:00.835999 arm64_za-ptrace_Set_VL_3120 pass
13553 11:45:00.836117 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13554 11:45:00.836233 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13555 11:45:00.836378 arm64_za-ptrace_Set_VL_3136 pass
13556 11:45:00.836500 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13557 11:45:00.836615 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13558 11:45:00.836730 arm64_za-ptrace_Set_VL_3152 pass
13559 11:45:00.836846 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13560 11:45:00.836960 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13561 11:45:00.837072 arm64_za-ptrace_Set_VL_3168 pass
13562 11:45:00.837190 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13563 11:45:00.837304 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13564 11:45:00.839736 arm64_za-ptrace_Set_VL_3184 pass
13565 11:45:00.840171 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13566 11:45:00.840389 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13567 11:45:00.840596 arm64_za-ptrace_Set_VL_3200 pass
13568 11:45:00.840764 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13569 11:45:00.840930 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13570 11:45:00.841173 arm64_za-ptrace_Set_VL_3216 pass
13571 11:45:00.841330 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13572 11:45:00.841460 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13573 11:45:00.841587 arm64_za-ptrace_Set_VL_3232 pass
13574 11:45:00.841814 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13575 11:45:00.842018 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13576 11:45:00.842210 arm64_za-ptrace_Set_VL_3248 pass
13577 11:45:00.842419 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13578 11:45:00.842637 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13579 11:45:00.842871 arm64_za-ptrace_Set_VL_3264 pass
13580 11:45:00.843033 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13581 11:45:00.843246 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13582 11:45:00.843508 arm64_za-ptrace_Set_VL_3280 pass
13583 11:45:00.843659 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13584 11:45:00.843783 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13585 11:45:00.843902 arm64_za-ptrace_Set_VL_3296 pass
13586 11:45:00.844019 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13587 11:45:00.844136 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13588 11:45:00.844257 arm64_za-ptrace_Set_VL_3312 pass
13589 11:45:00.844373 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13590 11:45:00.844491 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13591 11:45:00.844608 arm64_za-ptrace_Set_VL_3328 pass
13592 11:45:00.844724 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13593 11:45:00.844840 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13594 11:45:00.844957 arm64_za-ptrace_Set_VL_3344 pass
13595 11:45:00.845072 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13596 11:45:00.845190 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13597 11:45:00.845315 arm64_za-ptrace_Set_VL_3360 pass
13598 11:45:00.845511 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13599 11:45:00.845673 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13600 11:45:00.845821 arm64_za-ptrace_Set_VL_3376 pass
13601 11:45:00.845966 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13602 11:45:00.846107 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13603 11:45:00.846249 arm64_za-ptrace_Set_VL_3392 pass
13604 11:45:00.846391 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13605 11:45:00.846533 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13606 11:45:00.846674 arm64_za-ptrace_Set_VL_3408 pass
13607 11:45:00.846815 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13608 11:45:00.847753 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13609 11:45:00.848253 arm64_za-ptrace_Set_VL_3424 pass
13610 11:45:00.848464 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13611 11:45:00.848660 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13612 11:45:00.848865 arm64_za-ptrace_Set_VL_3440 pass
13613 11:45:00.849089 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13614 11:45:00.849324 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13615 11:45:00.849590 arm64_za-ptrace_Set_VL_3456 pass
13616 11:45:00.849792 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13617 11:45:00.849983 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13618 11:45:00.850153 arm64_za-ptrace_Set_VL_3472 pass
13619 11:45:00.850321 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13620 11:45:00.850486 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13621 11:45:00.850662 arm64_za-ptrace_Set_VL_3488 pass
13622 11:45:00.850800 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13623 11:45:00.850920 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13624 11:45:00.851039 arm64_za-ptrace_Set_VL_3504 pass
13625 11:45:00.851232 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13626 11:45:00.851369 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13627 11:45:00.851485 arm64_za-ptrace_Set_VL_3520 pass
13628 11:45:00.851600 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13629 11:45:00.851748 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13630 11:45:00.851915 arm64_za-ptrace_Set_VL_3536 pass
13631 11:45:00.852043 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13632 11:45:00.852158 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13633 11:45:00.852276 arm64_za-ptrace_Set_VL_3552 pass
13634 11:45:00.852388 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13635 11:45:00.852501 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13636 11:45:00.852616 arm64_za-ptrace_Set_VL_3568 pass
13637 11:45:00.852728 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13638 11:45:00.852840 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13639 11:45:00.852954 arm64_za-ptrace_Set_VL_3584 pass
13640 11:45:00.853067 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13641 11:45:00.853178 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13642 11:45:00.871486 arm64_za-ptrace_Set_VL_3600 pass
13643 11:45:00.871723 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13644 11:45:00.871849 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13645 11:45:00.872207 arm64_za-ptrace_Set_VL_3616 pass
13646 11:45:00.872311 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13647 11:45:00.872398 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13648 11:45:00.872483 arm64_za-ptrace_Set_VL_3632 pass
13649 11:45:00.872568 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13650 11:45:00.872669 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13651 11:45:00.872755 arm64_za-ptrace_Set_VL_3648 pass
13652 11:45:00.872839 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13653 11:45:00.872921 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13654 11:45:00.873023 arm64_za-ptrace_Set_VL_3664 pass
13655 11:45:00.873111 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13656 11:45:00.873212 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13657 11:45:00.873302 arm64_za-ptrace_Set_VL_3680 pass
13658 11:45:00.873400 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13659 11:45:00.873485 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13660 11:45:00.873584 arm64_za-ptrace_Set_VL_3696 pass
13661 11:45:00.873694 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13662 11:45:00.873793 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13663 11:45:00.874080 arm64_za-ptrace_Set_VL_3712 pass
13664 11:45:00.874201 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13665 11:45:00.874294 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13666 11:45:00.874396 arm64_za-ptrace_Set_VL_3728 pass
13667 11:45:00.874498 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13668 11:45:00.874601 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13669 11:45:00.874703 arm64_za-ptrace_Set_VL_3744 pass
13670 11:45:00.874803 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13671 11:45:00.874903 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13672 11:45:00.875005 arm64_za-ptrace_Set_VL_3760 pass
13673 11:45:00.875113 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13674 11:45:00.875404 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13675 11:45:00.875518 arm64_za-ptrace_Set_VL_3776 pass
13676 11:45:00.875608 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13677 11:45:00.879820 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13678 11:45:00.879930 arm64_za-ptrace_Set_VL_3792 pass
13679 11:45:00.880206 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13680 11:45:00.880301 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13681 11:45:00.880386 arm64_za-ptrace_Set_VL_3808 pass
13682 11:45:00.880484 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13683 11:45:00.880570 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13684 11:45:00.880653 arm64_za-ptrace_Set_VL_3824 pass
13685 11:45:00.880737 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13686 11:45:00.880834 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13687 11:45:00.880920 arm64_za-ptrace_Set_VL_3840 pass
13688 11:45:00.881003 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13689 11:45:00.881101 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13690 11:45:00.881185 arm64_za-ptrace_Set_VL_3856 pass
13691 11:45:00.881281 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13692 11:45:00.881548 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13693 11:45:00.881867 arm64_za-ptrace_Set_VL_3872 pass
13694 11:45:00.881956 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13695 11:45:00.882052 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13696 11:45:00.882168 arm64_za-ptrace_Set_VL_3888 pass
13697 11:45:00.882281 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13698 11:45:00.882367 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13699 11:45:00.882466 arm64_za-ptrace_Set_VL_3904 pass
13700 11:45:00.882817 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13701 11:45:00.882936 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13702 11:45:00.883045 arm64_za-ptrace_Set_VL_3920 pass
13703 11:45:00.883158 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13704 11:45:00.883278 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13705 11:45:00.883387 arm64_za-ptrace_Set_VL_3936 pass
13706 11:45:00.883496 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13707 11:45:00.883566 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13708 11:45:00.883642 arm64_za-ptrace_Set_VL_3952 pass
13709 11:45:00.883705 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13710 11:45:00.883775 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13711 11:45:00.883852 arm64_za-ptrace_Set_VL_3968 pass
13712 11:45:00.883917 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13713 11:45:00.883977 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13714 11:45:00.884036 arm64_za-ptrace_Set_VL_3984 pass
13715 11:45:00.884095 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13716 11:45:00.884153 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13717 11:45:00.887707 arm64_za-ptrace_Set_VL_4000 pass
13718 11:45:00.888032 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13719 11:45:00.888156 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13720 11:45:00.888287 arm64_za-ptrace_Set_VL_4016 pass
13721 11:45:00.888421 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13722 11:45:00.888527 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13723 11:45:00.888631 arm64_za-ptrace_Set_VL_4032 pass
13724 11:45:00.888751 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13725 11:45:00.888862 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13726 11:45:00.888974 arm64_za-ptrace_Set_VL_4048 pass
13727 11:45:00.889077 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13728 11:45:00.889202 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13729 11:45:00.889314 arm64_za-ptrace_Set_VL_4064 pass
13730 11:45:00.889416 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13731 11:45:00.889515 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13732 11:45:00.889617 arm64_za-ptrace_Set_VL_4080 pass
13733 11:45:00.889728 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13734 11:45:00.889848 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13735 11:45:00.889955 arm64_za-ptrace_Set_VL_4096 pass
13736 11:45:00.890055 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13737 11:45:00.890158 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13738 11:45:00.890268 arm64_za-ptrace_Set_VL_4112 pass
13739 11:45:00.890372 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13740 11:45:00.890476 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13741 11:45:00.890605 arm64_za-ptrace_Set_VL_4128 pass
13742 11:45:00.890715 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13743 11:45:00.890822 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13744 11:45:00.890922 arm64_za-ptrace_Set_VL_4144 pass
13745 11:45:00.891016 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13746 11:45:00.891124 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13747 11:45:00.891232 arm64_za-ptrace_Set_VL_4160 pass
13748 11:45:00.891326 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13749 11:45:00.891423 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13750 11:45:00.891534 arm64_za-ptrace_Set_VL_4176 pass
13751 11:45:00.891626 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13752 11:45:00.891692 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13753 11:45:00.891753 arm64_za-ptrace_Set_VL_4192 pass
13754 11:45:00.891835 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13755 11:45:00.891903 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13756 11:45:00.891962 arm64_za-ptrace_Set_VL_4208 pass
13757 11:45:00.892021 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13758 11:45:00.892079 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13759 11:45:00.892137 arm64_za-ptrace_Set_VL_4224 pass
13760 11:45:00.892195 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13761 11:45:00.895842 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13762 11:45:00.895950 arm64_za-ptrace_Set_VL_4240 pass
13763 11:45:00.896038 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13764 11:45:00.896400 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13765 11:45:00.896503 arm64_za-ptrace_Set_VL_4256 pass
13766 11:45:00.896592 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13767 11:45:00.896679 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13768 11:45:00.896765 arm64_za-ptrace_Set_VL_4272 pass
13769 11:45:00.896867 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13770 11:45:00.896954 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13771 11:45:00.897039 arm64_za-ptrace_Set_VL_4288 pass
13772 11:45:00.897136 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13773 11:45:00.897221 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13774 11:45:00.897308 arm64_za-ptrace_Set_VL_4304 pass
13775 11:45:00.897410 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13776 11:45:00.897496 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13777 11:45:00.897593 arm64_za-ptrace_Set_VL_4320 pass
13778 11:45:00.897701 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13779 11:45:00.897801 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13780 11:45:00.897901 arm64_za-ptrace_Set_VL_4336 pass
13781 11:45:00.898196 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13782 11:45:00.898302 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13783 11:45:00.898406 arm64_za-ptrace_Set_VL_4352 pass
13784 11:45:00.898510 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13785 11:45:00.898611 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13786 11:45:00.898714 arm64_za-ptrace_Set_VL_4368 pass
13787 11:45:00.899002 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13788 11:45:00.899104 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13789 11:45:00.899191 arm64_za-ptrace_Set_VL_4384 pass
13790 11:45:00.899295 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13791 11:45:00.899384 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13792 11:45:00.899502 arm64_za-ptrace_Set_VL_4400 pass
13793 11:45:00.903873 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13794 11:45:00.904019 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13795 11:45:00.904372 arm64_za-ptrace_Set_VL_4416 pass
13796 11:45:00.904484 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13797 11:45:00.904585 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13798 11:45:00.904690 arm64_za-ptrace_Set_VL_4432 pass
13799 11:45:00.904796 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13800 11:45:00.904892 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13801 11:45:00.904994 arm64_za-ptrace_Set_VL_4448 pass
13802 11:45:00.905114 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13803 11:45:00.905204 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13804 11:45:00.905301 arm64_za-ptrace_Set_VL_4464 pass
13805 11:45:00.905405 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13806 11:45:00.905499 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13807 11:45:00.905599 arm64_za-ptrace_Set_VL_4480 pass
13808 11:45:00.905727 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13809 11:45:00.905820 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13810 11:45:00.905922 arm64_za-ptrace_Set_VL_4496 pass
13811 11:45:00.906047 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13812 11:45:00.906164 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13813 11:45:00.906263 arm64_za-ptrace_Set_VL_4512 pass
13814 11:45:00.906376 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13815 11:45:00.906471 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13816 11:45:00.906559 arm64_za-ptrace_Set_VL_4528 pass
13817 11:45:00.906654 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13818 11:45:00.906786 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13819 11:45:00.906875 arm64_za-ptrace_Set_VL_4544 pass
13820 11:45:00.906977 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13821 11:45:00.907060 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13822 11:45:00.907142 arm64_za-ptrace_Set_VL_4560 pass
13823 11:45:00.907206 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13824 11:45:00.907266 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13825 11:45:00.907330 arm64_za-ptrace_Set_VL_4576 pass
13826 11:45:00.907392 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13827 11:45:00.907451 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13828 11:45:00.907509 arm64_za-ptrace_Set_VL_4592 pass
13829 11:45:00.907568 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13830 11:45:00.907627 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13831 11:45:00.907685 arm64_za-ptrace_Set_VL_4608 pass
13832 11:45:00.907744 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13833 11:45:00.907803 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13834 11:45:00.911829 arm64_za-ptrace_Set_VL_4624 pass
13835 11:45:00.928390 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13836 11:45:00.928690 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13837 11:45:00.928782 arm64_za-ptrace_Set_VL_4640 pass
13838 11:45:00.928866 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13839 11:45:00.928970 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13840 11:45:00.929058 arm64_za-ptrace_Set_VL_4656 pass
13841 11:45:00.929141 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13842 11:45:00.929222 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13843 11:45:00.929322 arm64_za-ptrace_Set_VL_4672 pass
13844 11:45:00.929406 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13845 11:45:00.929488 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13846 11:45:00.929569 arm64_za-ptrace_Set_VL_4688 pass
13847 11:45:00.929658 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13848 11:45:00.929743 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13849 11:45:00.929830 arm64_za-ptrace_Set_VL_4704 pass
13850 11:45:00.929930 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13851 11:45:00.930017 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13852 11:45:00.930102 arm64_za-ptrace_Set_VL_4720 pass
13853 11:45:00.930186 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13854 11:45:00.930288 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13855 11:45:00.930382 arm64_za-ptrace_Set_VL_4736 pass
13856 11:45:00.930469 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13857 11:45:00.930555 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13858 11:45:00.930638 arm64_za-ptrace_Set_VL_4752 pass
13859 11:45:00.930722 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13860 11:45:00.930806 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13861 11:45:00.930888 arm64_za-ptrace_Set_VL_4768 pass
13862 11:45:00.930987 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13863 11:45:00.931074 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13864 11:45:00.931177 arm64_za-ptrace_Set_VL_4784 pass
13865 11:45:00.931264 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13866 11:45:00.931350 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13867 11:45:00.931443 arm64_za-ptrace_Set_VL_4800 pass
13868 11:45:00.931529 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13869 11:45:00.931612 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13870 11:45:00.931696 arm64_za-ptrace_Set_VL_4816 pass
13871 11:45:00.931786 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13872 11:45:00.931889 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13873 11:45:00.931977 arm64_za-ptrace_Set_VL_4832 pass
13874 11:45:00.932061 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13875 11:45:00.932146 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13876 11:45:00.935900 arm64_za-ptrace_Set_VL_4848 pass
13877 11:45:00.936197 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13878 11:45:00.936293 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13879 11:45:00.936382 arm64_za-ptrace_Set_VL_4864 pass
13880 11:45:00.936463 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13881 11:45:00.936548 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13882 11:45:00.936635 arm64_za-ptrace_Set_VL_4880 pass
13883 11:45:00.936718 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13884 11:45:00.936820 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13885 11:45:00.936907 arm64_za-ptrace_Set_VL_4896 pass
13886 11:45:00.936996 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13887 11:45:00.937081 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13888 11:45:00.937165 arm64_za-ptrace_Set_VL_4912 pass
13889 11:45:00.937245 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13890 11:45:00.937344 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13891 11:45:00.937434 arm64_za-ptrace_Set_VL_4928 pass
13892 11:45:00.937516 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13893 11:45:00.937597 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13894 11:45:00.937687 arm64_za-ptrace_Set_VL_4944 pass
13895 11:45:00.937788 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13896 11:45:00.937876 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13897 11:45:00.937962 arm64_za-ptrace_Set_VL_4960 pass
13898 11:45:00.938058 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13899 11:45:00.938138 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13900 11:45:00.938227 arm64_za-ptrace_Set_VL_4976 pass
13901 11:45:00.938312 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13902 11:45:00.938402 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13903 11:45:00.938487 arm64_za-ptrace_Set_VL_4992 pass
13904 11:45:00.938590 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13905 11:45:00.938679 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13906 11:45:00.938764 arm64_za-ptrace_Set_VL_5008 pass
13907 11:45:00.938848 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13908 11:45:00.938933 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13909 11:45:00.939017 arm64_za-ptrace_Set_VL_5024 pass
13910 11:45:00.939118 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13911 11:45:00.939206 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13912 11:45:00.939288 arm64_za-ptrace_Set_VL_5040 pass
13913 11:45:00.939373 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13914 11:45:00.939458 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13915 11:45:00.939558 arm64_za-ptrace_Set_VL_5056 pass
13916 11:45:00.939645 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13917 11:45:00.939729 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13918 11:45:00.939814 arm64_za-ptrace_Set_VL_5072 pass
13919 11:45:00.943743 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13920 11:45:00.944069 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13921 11:45:00.944171 arm64_za-ptrace_Set_VL_5088 pass
13922 11:45:00.944259 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13923 11:45:00.944345 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13924 11:45:00.944447 arm64_za-ptrace_Set_VL_5104 pass
13925 11:45:00.944534 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13926 11:45:00.944618 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13927 11:45:00.944719 arm64_za-ptrace_Set_VL_5120 pass
13928 11:45:00.944807 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13929 11:45:00.944908 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13930 11:45:00.944995 arm64_za-ptrace_Set_VL_5136 pass
13931 11:45:00.945095 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13932 11:45:00.945224 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13933 11:45:00.945841 arm64_za-ptrace_Set_VL_5152 pass
13934 11:45:00.946010 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13935 11:45:00.946096 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13936 11:45:00.946383 arm64_za-ptrace_Set_VL_5168 pass
13937 11:45:00.946490 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13938 11:45:00.946578 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13939 11:45:00.946665 arm64_za-ptrace_Set_VL_5184 pass
13940 11:45:00.946750 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13941 11:45:00.946834 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13942 11:45:00.946919 arm64_za-ptrace_Set_VL_5200 pass
13943 11:45:00.947019 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13944 11:45:00.947107 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13945 11:45:00.947193 arm64_za-ptrace_Set_VL_5216 pass
13946 11:45:00.947276 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13947 11:45:00.947359 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13948 11:45:00.947449 arm64_za-ptrace_Set_VL_5232 pass
13949 11:45:00.947546 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
13950 11:45:00.947630 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
13951 11:45:00.947711 arm64_za-ptrace_Set_VL_5248 pass
13952 11:45:00.947796 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
13953 11:45:00.955824 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
13954 11:45:00.955955 arm64_za-ptrace_Set_VL_5264 pass
13955 11:45:00.956022 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
13956 11:45:00.956083 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
13957 11:45:00.956143 arm64_za-ptrace_Set_VL_5280 pass
13958 11:45:00.956204 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
13959 11:45:00.956265 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
13960 11:45:00.956327 arm64_za-ptrace_Set_VL_5296 pass
13961 11:45:00.956387 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
13962 11:45:00.956448 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
13963 11:45:00.956509 arm64_za-ptrace_Set_VL_5312 pass
13964 11:45:00.956568 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
13965 11:45:00.956627 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
13966 11:45:00.956686 arm64_za-ptrace_Set_VL_5328 pass
13967 11:45:00.956745 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
13968 11:45:00.956803 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
13969 11:45:00.956863 arm64_za-ptrace_Set_VL_5344 pass
13970 11:45:00.956922 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
13971 11:45:00.956981 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
13972 11:45:00.957041 arm64_za-ptrace_Set_VL_5360 pass
13973 11:45:00.957100 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
13974 11:45:00.957158 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
13975 11:45:00.957217 arm64_za-ptrace_Set_VL_5376 pass
13976 11:45:00.957276 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
13977 11:45:00.957334 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
13978 11:45:00.957393 arm64_za-ptrace_Set_VL_5392 pass
13979 11:45:00.957452 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
13980 11:45:00.957512 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
13981 11:45:00.957571 arm64_za-ptrace_Set_VL_5408 pass
13982 11:45:00.957630 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
13983 11:45:00.957701 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
13984 11:45:00.957761 arm64_za-ptrace_Set_VL_5424 pass
13985 11:45:00.957820 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
13986 11:45:00.957880 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
13987 11:45:00.959746 arm64_za-ptrace_Set_VL_5440 pass
13988 11:45:00.959856 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
13989 11:45:00.960196 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
13990 11:45:00.960293 arm64_za-ptrace_Set_VL_5456 pass
13991 11:45:00.960370 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
13992 11:45:00.960444 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
13993 11:45:00.960505 arm64_za-ptrace_Set_VL_5472 pass
13994 11:45:00.960576 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
13995 11:45:00.960638 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
13996 11:45:00.960697 arm64_za-ptrace_Set_VL_5488 pass
13997 11:45:00.960769 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
13998 11:45:00.960831 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
13999 11:45:00.960911 arm64_za-ptrace_Set_VL_5504 pass
14000 11:45:00.960978 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
14001 11:45:00.961051 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
14002 11:45:00.961130 arm64_za-ptrace_Set_VL_5520 pass
14003 11:45:00.961219 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
14004 11:45:00.961304 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
14005 11:45:00.961388 arm64_za-ptrace_Set_VL_5536 pass
14006 11:45:00.961668 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
14007 11:45:00.961763 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
14008 11:45:00.961855 arm64_za-ptrace_Set_VL_5552 pass
14009 11:45:00.961932 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
14010 11:45:00.962023 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
14011 11:45:00.962119 arm64_za-ptrace_Set_VL_5568 pass
14012 11:45:00.962214 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
14013 11:45:00.962464 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
14014 11:45:00.962573 arm64_za-ptrace_Set_VL_5584 pass
14015 11:45:00.962677 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
14016 11:45:00.962765 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
14017 11:45:00.962848 arm64_za-ptrace_Set_VL_5600 pass
14018 11:45:00.962964 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
14019 11:45:00.963051 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
14020 11:45:00.963136 arm64_za-ptrace_Set_VL_5616 pass
14021 11:45:00.963234 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
14022 11:45:00.963321 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
14023 11:45:00.963421 arm64_za-ptrace_Set_VL_5632 pass
14024 11:45:00.963514 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
14025 11:45:00.967701 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
14026 11:45:00.968012 arm64_za-ptrace_Set_VL_5648 pass
14027 11:45:00.984071 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
14028 11:45:00.984344 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
14029 11:45:00.984906 arm64_za-ptrace_Set_VL_5664 pass
14030 11:45:00.986387 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
14031 11:45:00.986510 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
14032 11:45:00.986600 arm64_za-ptrace_Set_VL_5680 pass
14033 11:45:00.986684 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
14034 11:45:00.986769 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
14035 11:45:00.986855 arm64_za-ptrace_Set_VL_5696 pass
14036 11:45:00.986941 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
14037 11:45:00.987026 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
14038 11:45:00.987110 arm64_za-ptrace_Set_VL_5712 pass
14039 11:45:00.987196 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
14040 11:45:00.987283 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
14041 11:45:00.987368 arm64_za-ptrace_Set_VL_5728 pass
14042 11:45:00.987455 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
14043 11:45:00.987541 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
14044 11:45:00.987626 arm64_za-ptrace_Set_VL_5744 pass
14045 11:45:00.987708 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
14046 11:45:00.987790 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
14047 11:45:00.987873 arm64_za-ptrace_Set_VL_5760 pass
14048 11:45:00.988153 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
14049 11:45:00.988247 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
14050 11:45:00.988331 arm64_za-ptrace_Set_VL_5776 pass
14051 11:45:00.988411 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
14052 11:45:00.988499 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
14053 11:45:00.988580 arm64_za-ptrace_Set_VL_5792 pass
14054 11:45:00.988663 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
14055 11:45:00.988748 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
14056 11:45:00.988830 arm64_za-ptrace_Set_VL_5808 pass
14057 11:45:00.988912 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
14058 11:45:00.988993 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
14059 11:45:00.991807 arm64_za-ptrace_Set_VL_5824 pass
14060 11:45:00.992073 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
14061 11:45:00.992580 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
14062 11:45:00.992774 arm64_za-ptrace_Set_VL_5840 pass
14063 11:45:00.992948 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
14064 11:45:00.993094 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
14065 11:45:00.993234 arm64_za-ptrace_Set_VL_5856 pass
14066 11:45:00.993365 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
14067 11:45:00.993491 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
14068 11:45:00.993676 arm64_za-ptrace_Set_VL_5872 pass
14069 11:45:00.993887 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
14070 11:45:00.994086 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
14071 11:45:00.994285 arm64_za-ptrace_Set_VL_5888 pass
14072 11:45:00.994485 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
14073 11:45:00.994682 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
14074 11:45:00.994896 arm64_za-ptrace_Set_VL_5904 pass
14075 11:45:00.995113 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
14076 11:45:00.995286 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
14077 11:45:00.995418 arm64_za-ptrace_Set_VL_5920 pass
14078 11:45:00.995542 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
14079 11:45:00.995658 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
14080 11:45:00.995800 arm64_za-ptrace_Set_VL_5936 pass
14081 11:45:00.995953 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
14082 11:45:00.996072 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
14083 11:45:00.996193 arm64_za-ptrace_Set_VL_5952 pass
14084 11:45:00.996316 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
14085 11:45:00.996432 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
14086 11:45:00.996576 arm64_za-ptrace_Set_VL_5968 pass
14087 11:45:00.996700 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
14088 11:45:00.996817 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
14089 11:45:00.996933 arm64_za-ptrace_Set_VL_5984 pass
14090 11:45:00.997049 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
14091 11:45:00.999712 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
14092 11:45:00.999823 arm64_za-ptrace_Set_VL_6000 pass
14093 11:45:01.000110 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
14094 11:45:01.000213 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
14095 11:45:01.000315 arm64_za-ptrace_Set_VL_6016 pass
14096 11:45:01.000401 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
14097 11:45:01.000500 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
14098 11:45:01.000607 arm64_za-ptrace_Set_VL_6032 pass
14099 11:45:01.001013 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
14100 11:45:01.001120 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
14101 11:45:01.001206 arm64_za-ptrace_Set_VL_6048 pass
14102 11:45:01.001486 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
14103 11:45:01.001590 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
14104 11:45:01.001684 arm64_za-ptrace_Set_VL_6064 pass
14105 11:45:01.001768 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
14106 11:45:01.001868 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
14107 11:45:01.001970 arm64_za-ptrace_Set_VL_6080 pass
14108 11:45:01.002058 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
14109 11:45:01.002157 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
14110 11:45:01.002257 arm64_za-ptrace_Set_VL_6096 pass
14111 11:45:01.002359 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
14112 11:45:01.002460 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
14113 11:45:01.002781 arm64_za-ptrace_Set_VL_6112 pass
14114 11:45:01.002884 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
14115 11:45:01.002987 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
14116 11:45:01.003075 arm64_za-ptrace_Set_VL_6128 pass
14117 11:45:01.003176 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
14118 11:45:01.003286 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
14119 11:45:01.003535 arm64_za-ptrace_Set_VL_6144 pass
14120 11:45:01.007777 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
14121 11:45:01.008276 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
14122 11:45:01.008408 arm64_za-ptrace_Set_VL_6160 pass
14123 11:45:01.008587 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
14124 11:45:01.008682 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
14125 11:45:01.008769 arm64_za-ptrace_Set_VL_6176 pass
14126 11:45:01.008870 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
14127 11:45:01.008964 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
14128 11:45:01.009051 arm64_za-ptrace_Set_VL_6192 pass
14129 11:45:01.009135 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
14130 11:45:01.009237 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
14131 11:45:01.009324 arm64_za-ptrace_Set_VL_6208 pass
14132 11:45:01.009411 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
14133 11:45:01.009512 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
14134 11:45:01.009605 arm64_za-ptrace_Set_VL_6224 pass
14135 11:45:01.009714 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
14136 11:45:01.009818 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
14137 11:45:01.009915 arm64_za-ptrace_Set_VL_6240 pass
14138 11:45:01.010215 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
14139 11:45:01.010323 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
14140 11:45:01.010425 arm64_za-ptrace_Set_VL_6256 pass
14141 11:45:01.010527 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
14142 11:45:01.010632 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
14143 11:45:01.010732 arm64_za-ptrace_Set_VL_6272 pass
14144 11:45:01.011029 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
14145 11:45:01.011147 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
14146 11:45:01.011251 arm64_za-ptrace_Set_VL_6288 pass
14147 11:45:01.011353 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
14148 11:45:01.011682 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
14149 11:45:01.011983 arm64_za-ptrace_Set_VL_6304 pass
14150 11:45:01.012079 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
14151 11:45:01.016971 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
14152 11:45:01.017211 arm64_za-ptrace_Set_VL_6320 pass
14153 11:45:01.017318 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
14154 11:45:01.017412 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
14155 11:45:01.017516 arm64_za-ptrace_Set_VL_6336 pass
14156 11:45:01.017627 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
14157 11:45:01.017755 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
14158 11:45:01.017860 arm64_za-ptrace_Set_VL_6352 pass
14159 11:45:01.017961 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
14160 11:45:01.018049 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
14161 11:45:01.018127 arm64_za-ptrace_Set_VL_6368 pass
14162 11:45:01.018204 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
14163 11:45:01.018507 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
14164 11:45:01.018621 arm64_za-ptrace_Set_VL_6384 pass
14165 11:45:01.018710 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
14166 11:45:01.018795 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
14167 11:45:01.018879 arm64_za-ptrace_Set_VL_6400 pass
14168 11:45:01.018961 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
14169 11:45:01.019044 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
14170 11:45:01.019125 arm64_za-ptrace_Set_VL_6416 pass
14171 11:45:01.019205 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
14172 11:45:01.019289 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
14173 11:45:01.019371 arm64_za-ptrace_Set_VL_6432 pass
14174 11:45:01.019454 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
14175 11:45:01.019539 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
14176 11:45:01.019625 arm64_za-ptrace_Set_VL_6448 pass
14177 11:45:01.019705 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
14178 11:45:01.019788 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
14179 11:45:01.019893 arm64_za-ptrace_Set_VL_6464 pass
14180 11:45:01.019973 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
14181 11:45:01.020047 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
14182 11:45:01.020120 arm64_za-ptrace_Set_VL_6480 pass
14183 11:45:01.020194 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
14184 11:45:01.020267 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
14185 11:45:01.020340 arm64_za-ptrace_Set_VL_6496 pass
14186 11:45:01.020413 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
14187 11:45:01.020485 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
14188 11:45:01.023746 arm64_za-ptrace_Set_VL_6512 pass
14189 11:45:01.024117 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
14190 11:45:01.024263 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
14191 11:45:01.024393 arm64_za-ptrace_Set_VL_6528 pass
14192 11:45:01.024530 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
14193 11:45:01.024631 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14194 11:45:01.024710 arm64_za-ptrace_Set_VL_6544 pass
14195 11:45:01.024811 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14196 11:45:01.024909 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14197 11:45:01.025019 arm64_za-ptrace_Set_VL_6560 pass
14198 11:45:01.025100 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14199 11:45:01.025376 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14200 11:45:01.025474 arm64_za-ptrace_Set_VL_6576 pass
14201 11:45:01.025563 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14202 11:45:01.025639 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14203 11:45:01.025731 arm64_za-ptrace_Set_VL_6592 pass
14204 11:45:01.025983 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14205 11:45:01.026064 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14206 11:45:01.026170 arm64_za-ptrace_Set_VL_6608 pass
14207 11:45:01.026288 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14208 11:45:01.026405 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14209 11:45:01.026505 arm64_za-ptrace_Set_VL_6624 pass
14210 11:45:01.026783 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14211 11:45:01.026865 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14212 11:45:01.026944 arm64_za-ptrace_Set_VL_6640 pass
14213 11:45:01.027197 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14214 11:45:01.027280 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14215 11:45:01.027359 arm64_za-ptrace_Set_VL_6656 pass
14216 11:45:01.027436 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14217 11:45:01.031699 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14218 11:45:01.032107 arm64_za-ptrace_Set_VL_6672 pass
14219 11:45:01.032399 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14220 11:45:01.045567 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14221 11:45:01.045812 arm64_za-ptrace_Set_VL_6688 pass
14222 11:45:01.045921 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14223 11:45:01.046012 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14224 11:45:01.046099 arm64_za-ptrace_Set_VL_6704 pass
14225 11:45:01.046198 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14226 11:45:01.046287 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14227 11:45:01.046372 arm64_za-ptrace_Set_VL_6720 pass
14228 11:45:01.046470 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14229 11:45:01.046555 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14230 11:45:01.046659 arm64_za-ptrace_Set_VL_6736 pass
14231 11:45:01.046748 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14232 11:45:01.046846 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14233 11:45:01.046931 arm64_za-ptrace_Set_VL_6752 pass
14234 11:45:01.047028 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14235 11:45:01.047130 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14236 11:45:01.047228 arm64_za-ptrace_Set_VL_6768 pass
14237 11:45:01.047525 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14238 11:45:01.047815 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14239 11:45:01.047909 arm64_za-ptrace_Set_VL_6784 pass
14240 11:45:01.048009 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14241 11:45:01.048105 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14242 11:45:01.048205 arm64_za-ptrace_Set_VL_6800 pass
14243 11:45:01.048305 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14244 11:45:01.048403 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14245 11:45:01.048692 arm64_za-ptrace_Set_VL_6816 pass
14246 11:45:01.048787 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14247 11:45:01.048885 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14248 11:45:01.048971 arm64_za-ptrace_Set_VL_6832 pass
14249 11:45:01.049073 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14250 11:45:01.049414 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14251 11:45:01.049519 arm64_za-ptrace_Set_VL_6848 pass
14252 11:45:01.049605 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14253 11:45:01.049717 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14254 11:45:01.050009 arm64_za-ptrace_Set_VL_6864 pass
14255 11:45:01.050112 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14256 11:45:01.050198 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14257 11:45:01.050278 arm64_za-ptrace_Set_VL_6880 pass
14258 11:45:01.050359 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14259 11:45:01.050441 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14260 11:45:01.050542 arm64_za-ptrace_Set_VL_6896 pass
14261 11:45:01.050626 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14262 11:45:01.050709 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14263 11:45:01.050798 arm64_za-ptrace_Set_VL_6912 pass
14264 11:45:01.050896 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14265 11:45:01.050980 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14266 11:45:01.051056 arm64_za-ptrace_Set_VL_6928 pass
14267 11:45:01.051142 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14268 11:45:01.051218 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14269 11:45:01.051305 arm64_za-ptrace_Set_VL_6944 pass
14270 11:45:01.051381 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14271 11:45:01.051466 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14272 11:45:01.051542 arm64_za-ptrace_Set_VL_6960 pass
14273 11:45:01.056320 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14274 11:45:01.056794 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14275 11:45:01.056895 arm64_za-ptrace_Set_VL_6976 pass
14276 11:45:01.056991 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14277 11:45:01.057086 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14278 11:45:01.057172 arm64_za-ptrace_Set_VL_6992 pass
14279 11:45:01.057255 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14280 11:45:01.057333 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14281 11:45:01.057413 arm64_za-ptrace_Set_VL_7008 pass
14282 11:45:01.057493 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14283 11:45:01.057593 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14284 11:45:01.057694 arm64_za-ptrace_Set_VL_7024 pass
14285 11:45:01.057809 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14286 11:45:01.057942 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14287 11:45:01.058052 arm64_za-ptrace_Set_VL_7040 pass
14288 11:45:01.058148 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14289 11:45:01.058241 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14290 11:45:01.058340 arm64_za-ptrace_Set_VL_7056 pass
14291 11:45:01.058441 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14292 11:45:01.058528 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14293 11:45:01.058608 arm64_za-ptrace_Set_VL_7072 pass
14294 11:45:01.058683 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14295 11:45:01.058765 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14296 11:45:01.058847 arm64_za-ptrace_Set_VL_7088 pass
14297 11:45:01.058940 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14298 11:45:01.059259 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14299 11:45:01.059362 arm64_za-ptrace_Set_VL_7104 pass
14300 11:45:01.059451 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14301 11:45:01.059539 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14302 11:45:01.059630 arm64_za-ptrace_Set_VL_7120 pass
14303 11:45:01.059720 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14304 11:45:01.059999 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14305 11:45:01.060092 arm64_za-ptrace_Set_VL_7136 pass
14306 11:45:01.063832 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14307 11:45:01.064233 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14308 11:45:01.064332 arm64_za-ptrace_Set_VL_7152 pass
14309 11:45:01.064420 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14310 11:45:01.064505 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14311 11:45:01.064606 arm64_za-ptrace_Set_VL_7168 pass
14312 11:45:01.064896 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14313 11:45:01.064999 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14314 11:45:01.065077 arm64_za-ptrace_Set_VL_7184 pass
14315 11:45:01.065150 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14316 11:45:01.065419 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14317 11:45:01.065512 arm64_za-ptrace_Set_VL_7200 pass
14318 11:45:01.065585 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14319 11:45:01.065667 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14320 11:45:01.065741 arm64_za-ptrace_Set_VL_7216 pass
14321 11:45:01.065811 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14322 11:45:01.065896 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14323 11:45:01.065970 arm64_za-ptrace_Set_VL_7232 pass
14324 11:45:01.066041 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14325 11:45:01.066111 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14326 11:45:01.066195 arm64_za-ptrace_Set_VL_7248 pass
14327 11:45:01.066268 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14328 11:45:01.066349 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14329 11:45:01.066618 arm64_za-ptrace_Set_VL_7264 pass
14330 11:45:01.066714 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14331 11:45:01.066800 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14332 11:45:01.066876 arm64_za-ptrace_Set_VL_7280 pass
14333 11:45:01.066961 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14334 11:45:01.067247 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14335 11:45:01.067348 arm64_za-ptrace_Set_VL_7296 pass
14336 11:45:01.067635 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14337 11:45:01.067720 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14338 11:45:01.071740 arm64_za-ptrace_Set_VL_7312 pass
14339 11:45:01.072081 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14340 11:45:01.072179 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14341 11:45:01.072305 arm64_za-ptrace_Set_VL_7328 pass
14342 11:45:01.072424 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14343 11:45:01.072544 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14344 11:45:01.072640 arm64_za-ptrace_Set_VL_7344 pass
14345 11:45:01.072738 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14346 11:45:01.072842 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14347 11:45:01.072941 arm64_za-ptrace_Set_VL_7360 pass
14348 11:45:01.073044 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14349 11:45:01.073145 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14350 11:45:01.073241 arm64_za-ptrace_Set_VL_7376 pass
14351 11:45:01.073335 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14352 11:45:01.073655 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14353 11:45:01.073751 arm64_za-ptrace_Set_VL_7392 pass
14354 11:45:01.073826 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14355 11:45:01.074106 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14356 11:45:01.074201 arm64_za-ptrace_Set_VL_7408 pass
14357 11:45:01.074275 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14358 11:45:01.074348 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14359 11:45:01.074437 arm64_za-ptrace_Set_VL_7424 pass
14360 11:45:01.074512 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14361 11:45:01.074582 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14362 11:45:01.074652 arm64_za-ptrace_Set_VL_7440 pass
14363 11:45:01.074736 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14364 11:45:01.074809 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14365 11:45:01.074892 arm64_za-ptrace_Set_VL_7456 pass
14366 11:45:01.074975 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14367 11:45:01.075059 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14368 11:45:01.075142 arm64_za-ptrace_Set_VL_7472 pass
14369 11:45:01.075461 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14370 11:45:01.075606 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14371 11:45:01.075698 arm64_za-ptrace_Set_VL_7488 pass
14372 11:45:01.075798 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14373 11:45:01.083802 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14374 11:45:01.084031 arm64_za-ptrace_Set_VL_7504 pass
14375 11:45:01.084334 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14376 11:45:01.084438 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14377 11:45:01.084526 arm64_za-ptrace_Set_VL_7520 pass
14378 11:45:01.084597 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14379 11:45:01.084679 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14380 11:45:01.084747 arm64_za-ptrace_Set_VL_7536 pass
14381 11:45:01.084818 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14382 11:45:01.084902 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14383 11:45:01.084979 arm64_za-ptrace_Set_VL_7552 pass
14384 11:45:01.085070 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14385 11:45:01.085168 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14386 11:45:01.085261 arm64_za-ptrace_Set_VL_7568 pass
14387 11:45:01.085350 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14388 11:45:01.085638 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14389 11:45:01.085742 arm64_za-ptrace_Set_VL_7584 pass
14390 11:45:01.085827 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14391 11:45:01.085911 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14392 11:45:01.085995 arm64_za-ptrace_Set_VL_7600 pass
14393 11:45:01.086091 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14394 11:45:01.086172 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14395 11:45:01.086272 arm64_za-ptrace_Set_VL_7616 pass
14396 11:45:01.086357 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14397 11:45:01.086453 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14398 11:45:01.086757 arm64_za-ptrace_Set_VL_7632 pass
14399 11:45:01.087046 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14400 11:45:01.087141 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14401 11:45:01.087217 arm64_za-ptrace_Set_VL_7648 pass
14402 11:45:01.087293 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14403 11:45:01.087368 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14404 11:45:01.087443 arm64_za-ptrace_Set_VL_7664 pass
14405 11:45:01.087518 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14406 11:45:01.087607 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14407 11:45:01.087684 arm64_za-ptrace_Set_VL_7680 pass
14408 11:45:01.087764 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14409 11:45:01.087838 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14410 11:45:01.091845 arm64_za-ptrace_Set_VL_7696 pass
14411 11:45:01.092238 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14412 11:45:01.115118 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14413 11:45:01.115369 arm64_za-ptrace_Set_VL_7712 pass
14414 11:45:01.115701 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14415 11:45:01.115809 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14416 11:45:01.115923 arm64_za-ptrace_Set_VL_7728 pass
14417 11:45:01.116026 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14418 11:45:01.116172 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14419 11:45:01.116296 arm64_za-ptrace_Set_VL_7744 pass
14420 11:45:01.116400 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14421 11:45:01.116509 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14422 11:45:01.116625 arm64_za-ptrace_Set_VL_7760 pass
14423 11:45:01.116744 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14424 11:45:01.116882 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14425 11:45:01.116989 arm64_za-ptrace_Set_VL_7776 pass
14426 11:45:01.117104 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14427 11:45:01.117210 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14428 11:45:01.117303 arm64_za-ptrace_Set_VL_7792 pass
14429 11:45:01.117379 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14430 11:45:01.117453 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14431 11:45:01.117517 arm64_za-ptrace_Set_VL_7808 pass
14432 11:45:01.117614 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14433 11:45:01.117747 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14434 11:45:01.117844 arm64_za-ptrace_Set_VL_7824 pass
14435 11:45:01.117949 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14436 11:45:01.118042 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14437 11:45:01.118110 arm64_za-ptrace_Set_VL_7840 pass
14438 11:45:01.118175 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14439 11:45:01.118264 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14440 11:45:01.118345 arm64_za-ptrace_Set_VL_7856 pass
14441 11:45:01.118422 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14442 11:45:01.118493 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14443 11:45:01.118572 arm64_za-ptrace_Set_VL_7872 pass
14444 11:45:01.118650 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14445 11:45:01.118730 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14446 11:45:01.118826 arm64_za-ptrace_Set_VL_7888 pass
14447 11:45:01.118908 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14448 11:45:01.118989 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14449 11:45:01.119062 arm64_za-ptrace_Set_VL_7904 pass
14450 11:45:01.119122 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14451 11:45:01.119206 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14452 11:45:01.119282 arm64_za-ptrace_Set_VL_7920 pass
14453 11:45:01.119360 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14454 11:45:01.119427 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14455 11:45:01.119489 arm64_za-ptrace_Set_VL_7936 pass
14456 11:45:01.119561 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14457 11:45:01.119624 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14458 11:45:01.123777 arm64_za-ptrace_Set_VL_7952 pass
14459 11:45:01.124221 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14460 11:45:01.124319 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14461 11:45:01.124396 arm64_za-ptrace_Set_VL_7968 pass
14462 11:45:01.124473 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14463 11:45:01.124564 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14464 11:45:01.124644 arm64_za-ptrace_Set_VL_7984 pass
14465 11:45:01.124739 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14466 11:45:01.124818 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14467 11:45:01.124899 arm64_za-ptrace_Set_VL_8000 pass
14468 11:45:01.125142 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14469 11:45:01.125244 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14470 11:45:01.125321 arm64_za-ptrace_Set_VL_8016 pass
14471 11:45:01.125396 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14472 11:45:01.125470 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14473 11:45:01.125548 arm64_za-ptrace_Set_VL_8032 pass
14474 11:45:01.125636 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14475 11:45:01.125807 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14476 11:45:01.125907 arm64_za-ptrace_Set_VL_8048 pass
14477 11:45:01.125986 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14478 11:45:01.126059 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14479 11:45:01.126130 arm64_za-ptrace_Set_VL_8064 pass
14480 11:45:01.126220 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14481 11:45:01.126301 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14482 11:45:01.126376 arm64_za-ptrace_Set_VL_8080 pass
14483 11:45:01.126451 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14484 11:45:01.126523 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14485 11:45:01.126597 arm64_za-ptrace_Set_VL_8096 pass
14486 11:45:01.126687 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14487 11:45:01.126764 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14488 11:45:01.126839 arm64_za-ptrace_Set_VL_8112 pass
14489 11:45:01.126915 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14490 11:45:01.126992 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14491 11:45:01.127068 arm64_za-ptrace_Set_VL_8128 pass
14492 11:45:01.127160 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14493 11:45:01.127239 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14494 11:45:01.127315 arm64_za-ptrace_Set_VL_8144 pass
14495 11:45:01.127388 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14496 11:45:01.127476 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14497 11:45:01.127551 arm64_za-ptrace_Set_VL_8160 pass
14498 11:45:01.127622 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14499 11:45:01.127693 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14500 11:45:01.131772 arm64_za-ptrace_Set_VL_8176 pass
14501 11:45:01.132194 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14502 11:45:01.132304 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14503 11:45:01.132424 arm64_za-ptrace_Set_VL_8192 pass
14504 11:45:01.132540 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14505 11:45:01.132661 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14506 11:45:01.132762 arm64_za-ptrace pass
14507 11:45:01.132857 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14508 11:45:01.132944 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14509 11:45:01.133304 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14510 11:45:01.133408 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14511 11:45:01.133703 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14512 11:45:01.133805 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14513 11:45:01.134111 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14514 11:45:01.134436 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14515 11:45:01.134557 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14516 11:45:01.134873 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14517 11:45:01.135187 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14518 11:45:01.135495 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14519 11:45:01.139762 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14520 11:45:01.140159 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14521 11:45:01.140275 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14522 11:45:01.140567 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14523 11:45:01.140691 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14524 11:45:01.140999 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14525 11:45:01.141123 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14526 11:45:01.141432 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14527 11:45:01.141539 arm64_check_buffer_fill fail
14528 11:45:01.141863 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14529 11:45:01.141985 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14530 11:45:01.142309 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14531 11:45:01.142654 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14532 11:45:01.143169 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14533 11:45:01.143271 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14534 11:45:01.143352 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14535 11:45:01.143623 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14536 11:45:01.147814 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14537 11:45:01.148149 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14538 11:45:01.148266 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14539 11:45:01.148678 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14540 11:45:01.148792 arm64_check_child_memory fail
14541 11:45:01.148916 arm64_check_gcr_el1_cswitch fail
14542 11:45:01.149116 arm64_check_ksm_options fail
14543 11:45:01.149241 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14544 11:45:01.149564 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14545 11:45:01.149691 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14546 11:45:01.149998 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14547 11:45:01.150106 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14548 11:45:01.158922 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14549 11:45:01.159389 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14550 11:45:01.159499 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14551 11:45:01.159608 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14552 11:45:01.159912 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14553 11:45:01.160221 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14554 11:45:01.160529 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14555 11:45:01.160885 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14556 11:45:01.161205 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14557 11:45:01.161352 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14558 11:45:01.161718 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14559 11:45:01.161839 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14560 11:45:01.162131 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14561 11:45:01.162250 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14562 11:45:01.162552 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14563 11:45:01.162917 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14564 11:45:01.163031 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14565 11:45:01.163167 arm64_check_mmap_options fail
14566 11:45:01.163270 arm64_check_prctl_check_basic_read pass
14567 11:45:01.163434 arm64_check_prctl_NONE pass
14568 11:45:01.163546 arm64_check_prctl_SYNC pass
14569 11:45:01.163643 arm64_check_prctl_ASYNC pass
14570 11:45:01.163730 arm64_check_prctl_SYNC_ASYNC pass
14571 11:45:01.163799 arm64_check_prctl pass
14572 11:45:01.163876 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14573 11:45:01.167778 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14574 11:45:01.168176 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14575 11:45:01.168273 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14576 11:45:01.168354 arm64_check_tags_inclusion fail
14577 11:45:01.168448 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14578 11:45:01.168580 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14579 11:45:01.168868 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14580 11:45:01.169153 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14581 11:45:01.169248 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14582 11:45:01.169517 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14583 11:45:01.169589 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14584 11:45:01.169920 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14585 11:45:01.170043 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14586 11:45:01.170363 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14587 11:45:01.170728 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14588 11:45:01.170825 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14589 11:45:01.171120 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14590 11:45:01.171226 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14591 11:45:01.171331 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14592 11:45:01.171440 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14593 11:45:01.175807 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14594 11:45:01.176168 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14595 11:45:01.176291 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14596 11:45:01.176591 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14597 11:45:01.176710 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14598 11:45:01.176812 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14599 11:45:01.177133 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14600 11:45:01.177439 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14601 11:45:01.177560 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14602 11:45:01.177865 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14603 11:45:01.177993 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14604 11:45:01.178316 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14605 11:45:01.178639 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14606 11:45:01.178762 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14607 11:45:01.179077 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14608 11:45:01.179369 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14609 11:45:01.179491 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14610 11:45:01.183854 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14611 11:45:01.184311 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14612 11:45:01.184405 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14613 11:45:01.184494 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14614 11:45:01.184821 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14615 11:45:01.185134 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14616 11:45:01.185262 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14617 11:45:01.185769 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14618 11:45:01.185892 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14619 11:45:01.186000 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14620 11:45:01.186486 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14621 11:45:01.186788 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14622 11:45:01.186903 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14623 11:45:01.187218 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14624 11:45:01.188006 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14625 11:45:01.191763 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14626 11:45:01.192137 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14627 11:45:01.192254 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14628 11:45:01.192553 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14629 11:45:01.192862 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14630 11:45:01.192976 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14631 11:45:01.193278 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14632 11:45:01.193421 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14633 11:45:01.193719 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14634 11:45:01.193811 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14635 11:45:01.194083 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14636 11:45:01.194170 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14637 11:45:01.194265 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14638 11:45:01.194544 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14639 11:45:01.214084 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14640 11:45:01.214440 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14641 11:45:01.214742 arm64_check_user_mem pass
14642 11:45:01.214832 arm64_btitest_nohint_func_call_using_br_x0 pass
14643 11:45:01.214907 arm64_btitest_nohint_func_call_using_br_x16 pass
14644 11:45:01.214976 arm64_btitest_nohint_func_call_using_blr pass
14645 11:45:01.215046 arm64_btitest_bti_none_func_call_using_br_x0 pass
14646 11:45:01.215115 arm64_btitest_bti_none_func_call_using_br_x16 pass
14647 11:45:01.215185 arm64_btitest_bti_none_func_call_using_blr pass
14648 11:45:01.215270 arm64_btitest_bti_c_func_call_using_br_x0 pass
14649 11:45:01.215345 arm64_btitest_bti_c_func_call_using_br_x16 pass
14650 11:45:01.215417 arm64_btitest_bti_c_func_call_using_blr pass
14651 11:45:01.215515 arm64_btitest_bti_j_func_call_using_br_x0 pass
14652 11:45:01.215603 arm64_btitest_bti_j_func_call_using_br_x16 pass
14653 11:45:01.215703 arm64_btitest_bti_j_func_call_using_blr pass
14654 11:45:01.215998 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14655 11:45:01.216104 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14656 11:45:01.216190 arm64_btitest_bti_jc_func_call_using_blr pass
14657 11:45:01.216292 arm64_btitest_paciasp_func_call_using_br_x0 pass
14658 11:45:01.216393 arm64_btitest_paciasp_func_call_using_br_x16 pass
14659 11:45:01.216682 arm64_btitest_paciasp_func_call_using_blr pass
14660 11:45:01.216773 arm64_btitest pass
14661 11:45:01.216872 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14662 11:45:01.217177 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14663 11:45:01.217285 arm64_nobtitest_nohint_func_call_using_blr pass
14664 11:45:01.217365 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14665 11:45:01.217457 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14666 11:45:01.217536 arm64_nobtitest_bti_none_func_call_using_blr pass
14667 11:45:01.217626 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14668 11:45:01.217738 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14669 11:45:01.217829 arm64_nobtitest_bti_c_func_call_using_blr pass
14670 11:45:01.218105 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14671 11:45:01.218200 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14672 11:45:01.218486 arm64_nobtitest_bti_j_func_call_using_blr pass
14673 11:45:01.218570 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14674 11:45:01.218826 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14675 11:45:01.218896 arm64_nobtitest_bti_jc_func_call_using_blr pass
14676 11:45:01.218970 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14677 11:45:01.219035 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14678 11:45:01.219110 arm64_nobtitest_paciasp_func_call_using_blr pass
14679 11:45:01.219179 arm64_nobtitest pass
14680 11:45:01.219272 arm64_hwcap_cpuinfo_match_RNG pass
14681 11:45:01.219350 arm64_hwcap_sigill_RNG pass
14682 11:45:01.219613 arm64_hwcap_cpuinfo_match_SME pass
14683 11:45:01.219752 arm64_hwcap_sigill_SME pass
14684 11:45:01.219868 arm64_hwcap_cpuinfo_match_SVE pass
14685 11:45:01.223898 arm64_hwcap_sigill_SVE pass
14686 11:45:01.224136 arm64_hwcap_cpuinfo_match_SVE_2 pass
14687 11:45:01.224997 arm64_hwcap_sigill_SVE_2 pass
14688 11:45:01.225094 arm64_hwcap_cpuinfo_match_SVE_AES pass
14689 11:45:01.225169 arm64_hwcap_sigill_SVE_AES pass
14690 11:45:01.225241 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14691 11:45:01.225312 arm64_hwcap_sigill_SVE2_PMULL pass
14692 11:45:01.225383 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14693 11:45:01.225452 arm64_hwcap_sigill_SVE2_BITPERM pass
14694 11:45:01.225527 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14695 11:45:01.225596 arm64_hwcap_sigill_SVE2_SHA3 pass
14696 11:45:01.225676 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14697 11:45:01.225746 arm64_hwcap_sigill_SVE2_SM4 pass
14698 11:45:01.225815 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14699 11:45:01.225885 arm64_hwcap_sigill_SVE2_I8MM pass
14700 11:45:01.225972 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14701 11:45:01.226045 arm64_hwcap_sigill_SVE2_F32MM pass
14702 11:45:01.226115 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14703 11:45:01.226184 arm64_hwcap_sigill_SVE2_F64MM pass
14704 11:45:01.226253 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14705 11:45:01.226321 arm64_hwcap_sigill_SVE2_BF16 pass
14706 11:45:01.226391 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14707 11:45:01.226461 arm64_hwcap_sigill_SVE2_EBF16 skip
14708 11:45:01.226530 arm64_hwcap pass
14709 11:45:01.226614 arm64_ptrace_read_tpidr_one pass
14710 11:45:01.226688 arm64_ptrace_write_tpidr_one pass
14711 11:45:01.226759 arm64_ptrace_verify_tpidr_one pass
14712 11:45:01.226829 arm64_ptrace_count_tpidrs pass
14713 11:45:01.226901 arm64_ptrace_tpidr2_write pass
14714 11:45:01.226971 arm64_ptrace_tpidr2_read pass
14715 11:45:01.227056 arm64_ptrace_write_tpidr_only pass
14716 11:45:01.227129 arm64_ptrace pass
14717 11:45:01.227199 arm64_syscall-abi_getpid_FPSIMD pass
14718 11:45:01.227268 arm64_syscall-abi_getpid_SVE_VL_256 pass
14719 11:45:01.227352 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14720 11:45:01.227427 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14721 11:45:01.227519 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14722 11:45:01.231754 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14723 11:45:01.232223 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14724 11:45:01.232316 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14725 11:45:01.232403 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14726 11:45:01.232504 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14727 11:45:01.232593 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14728 11:45:01.232692 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14729 11:45:01.232997 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14730 11:45:01.233114 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14731 11:45:01.233218 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14732 11:45:01.233320 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14733 11:45:01.233621 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14734 11:45:01.233753 arm64_syscall-abi_getpid_SVE_VL_240 pass
14735 11:45:01.233864 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14736 11:45:01.234173 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14737 11:45:01.234272 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14738 11:45:01.234367 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14739 11:45:01.234659 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14740 11:45:01.234771 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14741 11:45:01.234862 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14742 11:45:01.235141 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14743 11:45:01.235237 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14744 11:45:01.235317 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14745 11:45:01.235587 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14746 11:45:01.239673 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14747 11:45:01.240129 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14748 11:45:01.240229 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14749 11:45:01.240312 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14750 11:45:01.240411 arm64_syscall-abi_getpid_SVE_VL_224 pass
14751 11:45:01.240494 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14752 11:45:01.240589 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14753 11:45:01.240687 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14754 11:45:01.241005 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14755 11:45:01.241104 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14756 11:45:01.241203 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14757 11:45:01.241288 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14758 11:45:01.241383 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14759 11:45:01.241471 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14760 11:45:01.241599 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14761 11:45:01.241729 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14762 11:45:01.241851 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14763 11:45:01.241953 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14764 11:45:01.242073 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14765 11:45:01.242195 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14766 11:45:01.242316 arm64_syscall-abi_getpid_SVE_VL_208 pass
14767 11:45:01.242439 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14768 11:45:01.242750 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14769 11:45:01.242862 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14770 11:45:01.242950 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14771 11:45:01.243077 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14772 11:45:01.243175 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14773 11:45:01.243285 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14774 11:45:01.243382 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14775 11:45:01.243499 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14776 11:45:01.243584 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14777 11:45:01.248095 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14778 11:45:01.248326 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14779 11:45:01.248431 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14780 11:45:01.248556 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14781 11:45:01.248661 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14782 11:45:01.248763 arm64_syscall-abi_getpid_SVE_VL_192 pass
14783 11:45:01.248875 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14784 11:45:01.248999 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14785 11:45:01.249091 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14786 11:45:01.249194 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14787 11:45:01.249311 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14788 11:45:01.249433 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14789 11:45:01.249552 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14790 11:45:01.249685 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14791 11:45:01.249809 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14792 11:45:01.249947 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14793 11:45:01.250085 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14794 11:45:01.250225 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14795 11:45:01.251266 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14796 11:45:01.251408 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14797 11:45:01.251521 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14798 11:45:01.251613 arm64_syscall-abi_getpid_SVE_VL_176 pass
14799 11:45:01.251687 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14800 11:45:01.251772 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14801 11:45:01.251849 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14802 11:45:01.251913 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14803 11:45:01.251998 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14804 11:45:01.252088 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14805 11:45:01.252384 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14806 11:45:01.259849 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14807 11:45:01.260076 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14808 11:45:01.260369 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14809 11:45:01.268571 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14810 11:45:01.268806 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14811 11:45:01.268921 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14812 11:45:01.269019 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14813 11:45:01.269121 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14814 11:45:01.269192 arm64_syscall-abi_getpid_SVE_VL_160 pass
14815 11:45:01.269472 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14816 11:45:01.269576 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14817 11:45:01.269688 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14818 11:45:01.269813 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14819 11:45:01.270155 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14820 11:45:01.270257 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14821 11:45:01.270358 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14822 11:45:01.270662 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14823 11:45:01.270779 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14824 11:45:01.270889 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14825 11:45:01.270987 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14826 11:45:01.271245 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14827 11:45:01.271525 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14828 11:45:01.271784 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14829 11:45:01.275790 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14830 11:45:01.276216 arm64_syscall-abi_getpid_SVE_VL_144 pass
14831 11:45:01.276302 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14832 11:45:01.276388 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14833 11:45:01.276481 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14834 11:45:01.276569 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14835 11:45:01.276869 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14836 11:45:01.277011 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14837 11:45:01.277144 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14838 11:45:01.277256 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14839 11:45:01.277381 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14840 11:45:01.277681 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14841 11:45:01.277788 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14842 11:45:01.278046 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14843 11:45:01.278139 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14844 11:45:01.278399 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14845 11:45:01.278520 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14846 11:45:01.278636 arm64_syscall-abi_getpid_SVE_VL_128 pass
14847 11:45:01.278957 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14848 11:45:01.279040 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14849 11:45:01.279114 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14850 11:45:01.279427 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14851 11:45:01.279529 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14852 11:45:01.283921 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14853 11:45:01.284388 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14854 11:45:01.284496 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14855 11:45:01.284583 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14856 11:45:01.284684 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14857 11:45:01.284773 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14858 11:45:01.284874 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14859 11:45:01.284989 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14860 11:45:01.285104 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14861 11:45:01.285410 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14862 11:45:01.285542 arm64_syscall-abi_getpid_SVE_VL_112 pass
14863 11:45:01.285637 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14864 11:45:01.285927 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14865 11:45:01.286017 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14866 11:45:01.286103 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14867 11:45:01.286360 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14868 11:45:01.286500 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14869 11:45:01.286593 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14870 11:45:01.286873 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14871 11:45:01.286969 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14872 11:45:01.287227 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14873 11:45:01.287313 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14874 11:45:01.287625 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14875 11:45:01.291825 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14876 11:45:01.292234 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14877 11:45:01.292334 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14878 11:45:01.292421 arm64_syscall-abi_getpid_SVE_VL_96 pass
14879 11:45:01.292521 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14880 11:45:01.292607 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14881 11:45:01.292703 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14882 11:45:01.292993 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14883 11:45:01.293084 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14884 11:45:01.293200 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14885 11:45:01.293484 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14886 11:45:01.293580 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14887 11:45:01.293844 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14888 11:45:01.293926 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14889 11:45:01.294178 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14890 11:45:01.294443 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14891 11:45:01.294539 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14892 11:45:01.294631 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14893 11:45:01.294710 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14894 11:45:01.294964 arm64_syscall-abi_getpid_SVE_VL_80 pass
14895 11:45:01.295045 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14896 11:45:01.295302 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14897 11:45:01.295393 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14898 11:45:01.295687 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14899 11:45:01.299844 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14900 11:45:01.300278 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14901 11:45:01.300389 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14902 11:45:01.300478 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14903 11:45:01.300579 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14904 11:45:01.300667 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14905 11:45:01.300766 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14906 11:45:01.300873 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14907 11:45:01.301126 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14908 11:45:01.301257 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14909 11:45:01.301385 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14910 11:45:01.301497 arm64_syscall-abi_getpid_SVE_VL_64 pass
14911 11:45:01.301606 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14912 11:45:01.301898 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14913 11:45:01.301987 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14914 11:45:01.302074 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14915 11:45:01.302353 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14916 11:45:01.302446 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14917 11:45:01.302531 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14918 11:45:01.302617 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14919 11:45:01.302915 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14920 11:45:01.303004 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14921 11:45:01.303089 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14922 11:45:01.303373 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14923 11:45:01.303474 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14924 11:45:01.307899 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14925 11:45:01.308369 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14926 11:45:01.308466 arm64_syscall-abi_getpid_SVE_VL_48 pass
14927 11:45:01.308547 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14928 11:45:01.308624 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14929 11:45:01.308705 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14930 11:45:01.308801 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14931 11:45:01.308883 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14932 11:45:01.308964 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14933 11:45:01.309060 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14934 11:45:01.309147 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14935 11:45:01.309244 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14936 11:45:01.309338 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14937 11:45:01.309424 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14938 11:45:01.309514 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14939 11:45:01.309588 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14940 11:45:01.309673 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14941 11:45:01.309758 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14942 11:45:01.310094 arm64_syscall-abi_getpid_SVE_VL_32 pass
14943 11:45:01.310192 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14944 11:45:01.310269 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14945 11:45:01.310341 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14946 11:45:01.310427 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14947 11:45:01.310499 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14948 11:45:01.310581 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
14949 11:45:01.310664 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
14950 11:45:01.310739 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
14951 11:45:01.310823 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
14952 11:45:01.310920 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
14953 11:45:01.311232 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
14954 11:45:01.311375 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
14955 11:45:01.311537 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
14956 11:45:01.311664 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
14957 11:45:01.315897 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
14958 11:45:01.316350 arm64_syscall-abi_getpid_SVE_VL_16 pass
14959 11:45:01.316453 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
14960 11:45:01.316556 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
14961 11:45:01.332175 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
14962 11:45:01.332694 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
14963 11:45:01.332891 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
14964 11:45:01.332994 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
14965 11:45:01.333096 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
14966 11:45:01.333200 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
14967 11:45:01.333277 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
14968 11:45:01.333349 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
14969 11:45:01.333421 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
14970 11:45:01.333505 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
14971 11:45:01.333585 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
14972 11:45:01.333683 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
14973 11:45:01.333977 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
14974 11:45:01.334072 arm64_syscall-abi_sched_yield_FPSIMD pass
14975 11:45:01.334160 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
14976 11:45:01.334247 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
14977 11:45:01.334322 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
14978 11:45:01.334407 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
14979 11:45:01.334494 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
14980 11:45:01.334582 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
14981 11:45:01.334952 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
14982 11:45:01.335046 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
14983 11:45:01.335120 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
14984 11:45:01.335196 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
14985 11:45:01.335282 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
14986 11:45:01.335364 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
14987 11:45:01.335466 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
14988 11:45:01.335553 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
14989 11:45:01.335638 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
14990 11:45:01.335743 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
14991 11:45:01.339804 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
14992 11:45:01.340302 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
14993 11:45:01.340439 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
14994 11:45:01.340672 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
14995 11:45:01.340791 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
14996 11:45:01.340872 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
14997 11:45:01.340976 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
14998 11:45:01.341060 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
14999 11:45:01.341138 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
15000 11:45:01.341212 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
15001 11:45:01.341293 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
15002 11:45:01.341380 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
15003 11:45:01.341454 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
15004 11:45:01.341528 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
15005 11:45:01.341617 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
15006 11:45:01.341889 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
15007 11:45:01.341989 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
15008 11:45:01.342065 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
15009 11:45:01.342138 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
15010 11:45:01.342212 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
15011 11:45:01.342299 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
15012 11:45:01.342376 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
15013 11:45:01.342465 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
15014 11:45:01.342545 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
15015 11:45:01.342623 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
15016 11:45:01.342716 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
15017 11:45:01.342806 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
15018 11:45:01.342882 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
15019 11:45:01.342968 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
15020 11:45:01.343058 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
15021 11:45:01.343354 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
15022 11:45:01.343464 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
15023 11:45:01.343565 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
15024 11:45:01.347840 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
15025 11:45:01.348294 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
15026 11:45:01.348393 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
15027 11:45:01.348475 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
15028 11:45:01.348565 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
15029 11:45:01.348654 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
15030 11:45:01.348809 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
15031 11:45:01.348917 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
15032 11:45:01.349201 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
15033 11:45:01.349318 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
15034 11:45:01.349633 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
15035 11:45:01.349745 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
15036 11:45:01.349845 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
15037 11:45:01.350144 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
15038 11:45:01.350254 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
15039 11:45:01.350560 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
15040 11:45:01.350667 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
15041 11:45:01.350771 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
15042 11:45:01.350859 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
15043 11:45:01.350958 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
15044 11:45:01.351249 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
15045 11:45:01.351360 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
15046 11:45:01.351451 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
15047 11:45:01.356126 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
15048 11:45:01.356393 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
15049 11:45:01.356690 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
15050 11:45:01.356803 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
15051 11:45:01.356895 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
15052 11:45:01.356989 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
15053 11:45:01.357093 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
15054 11:45:01.357178 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
15055 11:45:01.357280 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
15056 11:45:01.357382 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
15057 11:45:01.357983 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
15058 11:45:01.358105 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
15059 11:45:01.358192 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
15060 11:45:01.358488 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
15061 11:45:01.358593 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
15062 11:45:01.358679 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
15063 11:45:01.358777 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
15064 11:45:01.358865 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
15065 11:45:01.358964 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
15066 11:45:01.359188 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
15067 11:45:01.359309 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
15068 11:45:01.359408 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
15069 11:45:01.364158 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
15070 11:45:01.364631 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
15071 11:45:01.364736 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
15072 11:45:01.364815 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
15073 11:45:01.364891 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
15074 11:45:01.364966 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
15075 11:45:01.365056 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
15076 11:45:01.365133 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
15077 11:45:01.365222 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
15078 11:45:01.365514 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
15079 11:45:01.365616 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
15080 11:45:01.365718 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
15081 11:45:01.366015 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
15082 11:45:01.366130 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
15083 11:45:01.366226 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
15084 11:45:01.366530 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
15085 11:45:01.366696 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
15086 11:45:01.366844 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
15087 11:45:01.367013 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
15088 11:45:01.367178 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
15089 11:45:01.367337 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
15090 11:45:01.367515 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
15091 11:45:01.367684 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
15092 11:45:01.367878 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
15093 11:45:01.368052 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
15094 11:45:01.368211 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
15095 11:45:01.368389 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
15096 11:45:01.368558 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
15097 11:45:01.368713 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
15098 11:45:01.369004 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
15099 11:45:01.369163 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
15100 11:45:01.369308 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
15101 11:45:01.395424 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
15102 11:45:01.395687 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
15103 11:45:01.395991 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
15104 11:45:01.396088 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
15105 11:45:01.396189 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
15106 11:45:01.396470 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
15107 11:45:01.396582 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
15108 11:45:01.396682 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
15109 11:45:01.397030 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
15110 11:45:01.397316 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
15111 11:45:01.397409 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
15112 11:45:01.397496 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
15113 11:45:01.397599 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
15114 11:45:01.397887 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
15115 11:45:01.397997 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
15116 11:45:01.398098 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
15117 11:45:01.398199 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
15118 11:45:01.398489 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
15119 11:45:01.398601 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
15120 11:45:01.398689 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
15121 11:45:01.398792 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
15122 11:45:01.399085 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
15123 11:45:01.399369 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
15124 11:45:01.399476 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
15125 11:45:01.399562 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
15126 11:45:01.403932 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
15127 11:45:01.404339 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
15128 11:45:01.404450 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
15129 11:45:01.404557 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
15130 11:45:01.404661 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
15131 11:45:01.404983 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
15132 11:45:01.405089 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
15133 11:45:01.405192 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
15134 11:45:01.405281 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
15135 11:45:01.405381 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
15136 11:45:01.405680 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
15137 11:45:01.405787 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
15138 11:45:01.405890 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
15139 11:45:01.406175 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
15140 11:45:01.406266 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
15141 11:45:01.406371 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
15142 11:45:01.406646 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
15143 11:45:01.406751 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
15144 11:45:01.407027 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
15145 11:45:01.407131 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
15146 11:45:01.407406 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
15147 11:45:01.407497 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
15148 11:45:01.407598 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
15149 11:45:01.411961 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
15150 11:45:01.412408 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
15151 11:45:01.412503 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
15152 11:45:01.412605 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
15153 11:45:01.412694 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
15154 11:45:01.412796 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
15155 11:45:01.413085 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
15156 11:45:01.413187 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
15157 11:45:01.413422 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
15158 11:45:01.413537 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
15159 11:45:01.413619 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
15160 11:45:01.414128 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
15161 11:45:01.414225 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
15162 11:45:01.414304 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
15163 11:45:01.414572 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
15164 11:45:01.414653 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
15165 11:45:01.414730 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
15166 11:45:01.414819 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
15167 11:45:01.414910 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
15168 11:45:01.414988 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
15169 11:45:01.415276 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
15170 11:45:01.415377 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
15171 11:45:01.415481 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
15172 11:45:01.419876 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
15173 11:45:01.420305 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
15174 11:45:01.420393 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
15175 11:45:01.420507 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
15176 11:45:01.420594 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
15177 11:45:01.420866 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
15178 11:45:01.420941 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
15179 11:45:01.421025 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
15180 11:45:01.421302 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
15181 11:45:01.421394 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
15182 11:45:01.421663 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
15183 11:45:01.421758 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
15184 11:45:01.421827 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
15185 11:45:01.422082 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
15186 11:45:01.422167 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
15187 11:45:01.422272 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
15188 11:45:01.422563 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
15189 11:45:01.422654 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
15190 11:45:01.422935 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
15191 11:45:01.423038 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
15192 11:45:01.423148 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
15193 11:45:01.423251 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15194 11:45:01.423508 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15195 11:45:01.427902 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15196 11:45:01.428281 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15197 11:45:01.428397 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15198 11:45:01.428477 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15199 11:45:01.428582 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15200 11:45:01.428669 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15201 11:45:01.428921 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15202 11:45:01.429170 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15203 11:45:01.429251 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15204 11:45:01.429509 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15205 11:45:01.429613 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15206 11:45:01.429758 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15207 11:45:01.430050 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15208 11:45:01.430168 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15209 11:45:01.430267 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15210 11:45:01.430390 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15211 11:45:01.430503 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15212 11:45:01.430625 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15213 11:45:01.431100 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15214 11:45:01.431195 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15215 11:45:01.431315 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15216 11:45:01.431446 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15217 11:45:01.431551 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15218 11:45:01.436061 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15219 11:45:01.436459 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15220 11:45:01.436721 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15221 11:45:01.436835 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15222 11:45:01.436943 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15223 11:45:01.437036 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15224 11:45:01.437119 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15225 11:45:01.437417 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15226 11:45:01.437521 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15227 11:45:01.437660 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15228 11:45:01.437787 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15229 11:45:01.437874 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15230 11:45:01.437974 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15231 11:45:01.438057 arm64_syscall-abi pass
15232 11:45:01.438154 arm64_tpidr2_default_value pass
15233 11:45:01.438239 arm64_tpidr2_write_read pass
15234 11:45:01.438334 arm64_tpidr2_write_sleep_read pass
15235 11:45:01.438418 arm64_tpidr2_write_fork_read pass
15236 11:45:01.438514 arm64_tpidr2_write_clone_read pass
15237 11:45:01.438598 arm64_tpidr2 pass
15238 11:45:01.465734 + ../../utils/send-to-lava.sh ./output/result.txt
15239 11:45:01.536594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15240 11:45:01.537627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15242 11:45:01.577325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15243 11:45:01.577890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15245 11:45:01.613599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15246 11:45:01.614005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15248 11:45:01.648937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15250 11:45:01.649369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15251 11:45:01.683565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15252 11:45:01.684010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15254 11:45:01.719318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15255 11:45:01.719775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15257 11:45:01.754660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15258 11:45:01.755058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15260 11:45:01.788650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15261 11:45:01.789046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15263 11:45:01.822705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15265 11:45:01.823072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15266 11:45:01.855902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15268 11:45:01.856377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15269 11:45:01.890906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15270 11:45:01.891327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15272 11:45:01.926403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15274 11:45:01.926792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15275 11:45:01.963894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15277 11:45:01.964448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15278 11:45:02.000429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15279 11:45:02.000929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15281 11:45:02.033587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15282 11:45:02.034027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15284 11:45:02.066475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15285 11:45:02.066904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15287 11:45:02.100247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15289 11:45:02.100746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15290 11:45:02.133338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15292 11:45:02.133802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15293 11:45:02.167003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15294 11:45:02.167450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15296 11:45:02.201218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15297 11:45:02.201676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15299 11:45:02.235274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15300 11:45:02.235730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15302 11:45:02.270090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15303 11:45:02.270526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15305 11:45:02.305508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15306 11:45:02.305930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15308 11:45:02.340357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15309 11:45:02.340793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15311 11:45:02.373626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15312 11:45:02.374106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15314 11:45:02.406866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15315 11:45:02.407315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15317 11:45:02.440885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15318 11:45:02.441337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15320 11:45:02.474529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15321 11:45:02.474973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15323 11:45:02.508437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15325 11:45:02.509081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15326 11:45:02.554247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15328 11:45:02.554905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15329 11:45:02.592564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15331 11:45:02.593205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15332 11:45:02.630011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15333 11:45:02.630529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15335 11:45:02.664572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15337 11:45:02.665221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15338 11:45:02.698227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15340 11:45:02.698684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15341 11:45:02.737273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15342 11:45:02.737715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15344 11:45:02.776949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15346 11:45:02.777425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15347 11:45:02.812780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15349 11:45:02.813163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15350 11:45:02.847437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15352 11:45:02.847852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15353 11:45:02.883159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15355 11:45:02.883809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15356 11:45:02.918341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15357 11:45:02.918807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15359 11:45:02.952891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15360 11:45:02.953385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15362 11:45:02.986443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15363 11:45:02.986829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15365 11:45:03.023181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15366 11:45:03.023595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15368 11:45:03.060285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15369 11:45:03.060736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15371 11:45:03.098740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15373 11:45:03.099208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15374 11:45:03.132898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15375 11:45:03.133329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15377 11:45:03.167057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15378 11:45:03.167477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15380 11:45:03.201089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15381 11:45:03.201521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15383 11:45:03.234173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15385 11:45:03.234632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15386 11:45:03.269706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15387 11:45:03.270143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15389 11:45:03.305960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15391 11:45:03.306378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15392 11:45:03.341498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15393 11:45:03.342039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15395 11:45:03.377088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15397 11:45:03.377704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15398 11:45:03.412813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15400 11:45:03.413277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15401 11:45:03.447406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15402 11:45:03.447831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15404 11:45:03.483566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15405 11:45:03.484056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15407 11:45:03.518991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15408 11:45:03.519435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15410 11:45:03.553359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15411 11:45:03.553793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15413 11:45:03.590779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15414 11:45:03.591224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15416 11:45:03.626252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15417 11:45:03.626656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15419 11:45:03.661351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15420 11:45:03.661785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15422 11:45:03.697146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15424 11:45:03.697758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15425 11:45:03.730339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15426 11:45:03.730789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15428 11:45:03.763932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15430 11:45:03.764411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15431 11:45:03.798436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15433 11:45:03.798887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15434 11:45:03.834243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15436 11:45:03.834747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15437 11:45:03.869034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15438 11:45:03.869457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15440 11:45:03.904437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15441 11:45:03.904899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15443 11:45:03.939160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15444 11:45:03.939584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15446 11:45:03.977513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15448 11:45:03.977961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15449 11:45:04.014280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15450 11:45:04.014721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15452 11:45:04.052744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15454 11:45:04.053190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15455 11:45:04.087209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15456 11:45:04.087625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15458 11:45:04.120774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15459 11:45:04.121204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15461 11:45:04.155388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15462 11:45:04.155802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15464 11:45:04.189217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15466 11:45:04.189679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15467 11:45:04.225132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15468 11:45:04.225541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15470 11:45:04.260595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15471 11:45:04.261010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15473 11:45:04.294992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15475 11:45:04.295418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15476 11:45:04.328707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15478 11:45:04.329152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15479 11:45:04.361845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15481 11:45:04.362288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15482 11:45:04.394783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15483 11:45:04.395248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15485 11:45:04.429295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15486 11:45:04.429745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15488 11:45:04.463183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15490 11:45:04.463653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15491 11:45:04.496679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15492 11:45:04.497090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15494 11:45:04.529555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15495 11:45:04.530008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15497 11:45:04.562929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15498 11:45:04.563344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15500 11:45:04.596411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15501 11:45:04.596833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15503 11:45:04.634116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15504 11:45:04.634528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15506 11:45:04.669520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15507 11:45:04.670040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15509 11:45:04.704916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15511 11:45:04.705561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15512 11:45:04.739320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15514 11:45:04.740011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15515 11:45:04.773960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15516 11:45:04.774439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15518 11:45:04.809487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15519 11:45:04.810026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15521 11:45:04.844672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15522 11:45:04.845104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15524 11:45:04.879022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15525 11:45:04.879465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15527 11:45:04.914038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15528 11:45:04.914487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15530 11:45:04.948911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15531 11:45:04.949345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15533 11:45:04.985810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15535 11:45:04.986222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15536 11:45:05.021317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15537 11:45:05.021756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15539 11:45:05.057155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15540 11:45:05.057557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15542 11:45:05.095195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15543 11:45:05.095587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15545 11:45:05.132556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15546 11:45:05.132938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15548 11:45:05.168593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15550 11:45:05.168960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15551 11:45:05.205197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15552 11:45:05.205587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15554 11:45:05.241868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15555 11:45:05.242262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15557 11:45:05.280305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15559 11:45:05.280738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15560 11:45:05.330522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15561 11:45:05.330970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15563 11:45:05.368091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15565 11:45:05.368582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15566 11:45:05.405143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15568 11:45:05.405621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15569 11:45:05.442305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15571 11:45:05.442750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15572 11:45:05.477592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15573 11:45:05.478098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15575 11:45:05.513756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15576 11:45:05.514248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15578 11:45:05.551433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15580 11:45:05.552162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15581 11:45:05.588606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15582 11:45:05.589081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15584 11:45:05.627966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15586 11:45:05.628627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15587 11:45:05.672549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15589 11:45:05.673257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15590 11:45:05.708386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15591 11:45:05.708855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15593 11:45:05.743983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15595 11:45:05.744564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15596 11:45:05.779414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15598 11:45:05.780038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15599 11:45:05.817235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15601 11:45:05.817879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15602 11:45:05.853385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15603 11:45:05.853839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15605 11:45:05.897982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15606 11:45:05.898414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15608 11:45:05.934652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15609 11:45:05.935083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15611 11:45:05.970553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15613 11:45:05.971022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15614 11:45:06.006384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15615 11:45:06.006815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15617 11:45:06.043531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15619 11:45:06.043998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15620 11:45:06.094127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15622 11:45:06.094696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15623 11:45:06.132970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15624 11:45:06.133471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15626 11:45:06.175328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15627 11:45:06.175823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15629 11:45:06.226119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15630 11:45:06.226573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15632 11:45:06.265637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15634 11:45:06.266140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15635 11:45:06.311546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15636 11:45:06.311983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15638 11:45:06.348786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15639 11:45:06.349199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15641 11:45:06.386525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15643 11:45:06.386921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15644 11:45:06.421154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15645 11:45:06.421547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15647 11:45:06.457132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15648 11:45:06.457600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15650 11:45:06.491811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15652 11:45:06.492510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15653 11:45:06.539575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15655 11:45:06.540242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15656 11:45:06.589366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15658 11:45:06.589863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15659 11:45:06.629238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15661 11:45:06.629753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15662 11:45:06.669991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15663 11:45:06.670449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15665 11:45:06.707808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15667 11:45:06.708293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15668 11:45:06.744940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15669 11:45:06.745353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15671 11:45:06.782278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15673 11:45:06.782760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15674 11:45:06.820542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15676 11:45:06.821030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15677 11:45:06.857894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15678 11:45:06.858319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15680 11:45:06.895799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15682 11:45:06.896296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15683 11:45:06.933463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15684 11:45:06.933955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15686 11:45:06.972458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15687 11:45:06.972919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15689 11:45:07.007909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15691 11:45:07.008425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15692 11:45:07.042789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15693 11:45:07.043231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15695 11:45:07.078062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15696 11:45:07.078531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15698 11:45:07.113398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15699 11:45:07.113857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15701 11:45:07.146711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15702 11:45:07.147151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15704 11:45:07.179167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15705 11:45:07.179607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15707 11:45:07.214698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15708 11:45:07.215118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15710 11:45:07.249935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15712 11:45:07.250404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15713 11:45:07.284817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15715 11:45:07.285308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15716 11:45:07.320544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15717 11:45:07.320989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15719 11:45:07.354451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15720 11:45:07.354854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15722 11:45:07.386604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15724 11:45:07.386959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15725 11:45:07.419043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15726 11:45:07.419519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15728 11:45:07.450254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15729 11:45:07.450744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15731 11:45:07.487148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15732 11:45:07.487644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15734 11:45:07.530682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15735 11:45:07.531080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15737 11:45:07.575631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15738 11:45:07.576057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15740 11:45:07.612820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15742 11:45:07.613273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15743 11:45:07.646802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15744 11:45:07.647233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15746 11:45:07.682011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15747 11:45:07.682589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15749 11:45:07.719228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15750 11:45:07.719706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15752 11:45:07.755317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15753 11:45:07.755706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15755 11:45:07.792109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15756 11:45:07.792572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15758 11:45:07.825210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15759 11:45:07.825641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15761 11:45:07.857196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15762 11:45:07.857658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15764 11:45:07.890209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15766 11:45:07.890579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15767 11:45:07.924614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15769 11:45:07.925049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15770 11:45:07.958842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15771 11:45:07.959300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15773 11:45:07.994321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15774 11:45:07.994786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15776 11:45:08.030009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15777 11:45:08.030473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15779 11:45:08.064640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15781 11:45:08.065029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15782 11:45:08.098909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15784 11:45:08.099485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15785 11:45:08.132846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15787 11:45:08.133434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15788 11:45:08.166152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15790 11:45:08.166614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15791 11:45:08.200013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15793 11:45:08.200488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15794 11:45:08.232745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15796 11:45:08.233556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15797 11:45:08.264826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15798 11:45:08.265243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15800 11:45:08.297110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15801 11:45:08.297543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15803 11:45:08.328780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15804 11:45:08.329263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15806 11:45:08.359526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15807 11:45:08.359976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15809 11:45:08.390146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15810 11:45:08.390648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15812 11:45:08.422815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15814 11:45:08.423406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15815 11:45:08.456560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15817 11:45:08.457027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15818 11:45:08.487808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15820 11:45:08.488268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15821 11:45:08.520226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15822 11:45:08.520716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15824 11:45:08.551305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15826 11:45:08.551705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15827 11:45:08.582073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15829 11:45:08.582444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15830 11:45:08.614366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15832 11:45:08.614750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15833 11:45:08.646259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15835 11:45:08.646627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15836 11:45:08.679372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15837 11:45:08.679784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15839 11:45:08.713262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15840 11:45:08.713677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15842 11:45:08.748753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15843 11:45:08.749181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15845 11:45:08.782161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15846 11:45:08.782649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15848 11:45:08.813114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15849 11:45:08.813601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15851 11:45:08.844783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15852 11:45:08.845270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15854 11:45:08.875463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15855 11:45:08.875934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15857 11:45:08.906431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15858 11:45:08.906889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15860 11:45:08.937762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15861 11:45:08.938178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15863 11:45:08.970231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15864 11:45:08.970644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15866 11:45:09.001751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15867 11:45:09.002234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15869 11:45:09.034300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15871 11:45:09.034883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15872 11:45:09.067466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15873 11:45:09.067907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15875 11:45:09.102758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15876 11:45:09.103206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15878 11:45:09.138283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15879 11:45:09.138737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15881 11:45:09.173466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15883 11:45:09.174093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15884 11:45:09.204834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15885 11:45:09.205411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15887 11:45:09.235113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15889 11:45:09.235585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15890 11:45:09.265236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15891 11:45:09.265639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15893 11:45:09.296869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15894 11:45:09.297355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15896 11:45:09.327186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15898 11:45:09.327755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15899 11:45:09.358307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15900 11:45:09.358812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15902 11:45:09.390185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15903 11:45:09.390654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15905 11:45:09.422246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15906 11:45:09.422684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15908 11:45:09.455515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15909 11:45:09.456015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15911 11:45:09.489941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15913 11:45:09.490609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15914 11:45:09.525338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15915 11:45:09.525805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15917 11:45:09.562886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15918 11:45:09.563349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15920 11:45:09.597357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15921 11:45:09.597798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15923 11:45:09.631144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15924 11:45:09.631521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15926 11:45:09.677906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15927 11:45:09.678465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15929 11:45:09.711217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15930 11:45:09.711695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15932 11:45:09.745102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15933 11:45:09.745579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15935 11:45:09.779359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15936 11:45:09.779849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15938 11:45:09.813329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15940 11:45:09.813812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15941 11:45:09.848290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15943 11:45:09.848792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15944 11:45:09.881831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15945 11:45:09.882328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15947 11:45:09.917282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15948 11:45:09.917811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
15950 11:45:09.952209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
15952 11:45:09.952813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
15953 11:45:09.986737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
15954 11:45:09.987166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
15956 11:45:10.021200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
15958 11:45:10.021684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
15959 11:45:10.055039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
15961 11:45:10.055517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
15962 11:45:10.088822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
15963 11:45:10.089269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
15965 11:45:10.124558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
15966 11:45:10.124986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
15968 11:45:10.158730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
15969 11:45:10.159170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
15971 11:45:10.199395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
15972 11:45:10.199814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
15974 11:45:10.251856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
15976 11:45:10.252278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
15977 11:45:10.287604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
15979 11:45:10.288037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
15980 11:45:10.326741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
15981 11:45:10.327128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
15983 11:45:10.368531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
15985 11:45:10.368961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
15986 11:45:10.404623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
15987 11:45:10.405066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
15989 11:45:10.441791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
15991 11:45:10.442158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
15992 11:45:10.481977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
15993 11:45:10.482404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
15995 11:45:10.519392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
15996 11:45:10.519797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
15998 11:45:10.559327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
15999 11:45:10.559793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
16001 11:45:10.594398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
16002 11:45:10.594813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
16004 11:45:10.629667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
16005 11:45:10.630148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
16007 11:45:10.665409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
16008 11:45:10.665902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
16010 11:45:10.702913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
16011 11:45:10.703298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
16013 11:45:10.739240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
16015 11:45:10.739760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
16016 11:45:10.775170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
16018 11:45:10.775667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
16019 11:45:10.810223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
16021 11:45:10.810872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
16022 11:45:10.846004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
16023 11:45:10.846425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
16025 11:45:10.881563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
16026 11:45:10.881986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
16028 11:45:10.917318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
16030 11:45:10.917774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
16031 11:45:10.953634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
16032 11:45:10.954081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
16034 11:45:10.990831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
16036 11:45:10.991317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
16037 11:45:11.027547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
16038 11:45:11.028023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
16040 11:45:11.063684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
16042 11:45:11.064146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
16043 11:45:11.099631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
16044 11:45:11.100119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
16046 11:45:11.134823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
16047 11:45:11.135316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
16049 11:45:11.171696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
16051 11:45:11.172156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
16052 11:45:11.207553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
16054 11:45:11.208009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
16055 11:45:11.244819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
16057 11:45:11.245246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
16058 11:45:11.282534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
16059 11:45:11.282977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
16061 11:45:11.319855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
16063 11:45:11.320235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
16064 11:45:11.355406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
16065 11:45:11.355823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
16067 11:45:11.395146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
16068 11:45:11.395556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
16070 11:45:11.429388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
16072 11:45:11.429982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
16073 11:45:11.462385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
16075 11:45:11.462766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
16076 11:45:11.496553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
16078 11:45:11.497213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
16079 11:45:11.530002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
16081 11:45:11.530459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
16082 11:45:11.562369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
16083 11:45:11.562791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
16085 11:45:11.596131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
16087 11:45:11.596736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
16088 11:45:11.627811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
16090 11:45:11.628564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
16091 11:45:11.658834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
16093 11:45:11.659419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
16094 11:45:11.689717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
16096 11:45:11.690266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
16097 11:45:11.721693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
16099 11:45:11.722430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
16100 11:45:11.757697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
16102 11:45:11.758174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
16103 11:45:11.791305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
16104 11:45:11.791731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
16106 11:45:11.825013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
16107 11:45:11.825436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
16109 11:45:11.859387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
16111 11:45:11.859869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
16112 11:45:11.893435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
16114 11:45:11.894044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
16115 11:45:11.926649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
16116 11:45:11.927070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
16118 11:45:11.959239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
16119 11:45:11.959800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
16121 11:45:11.990516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
16123 11:45:11.990972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
16124 11:45:12.021265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
16126 11:45:12.021757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
16127 11:45:12.052614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
16128 11:45:12.053074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
16130 11:45:12.087815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
16132 11:45:12.088279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
16133 11:45:12.120425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
16135 11:45:12.120781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
16136 11:45:12.151535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
16137 11:45:12.151987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
16139 11:45:12.182177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
16141 11:45:12.182725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
16142 11:45:12.253181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
16144 11:45:12.253641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
16145 11:45:12.286091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
16146 11:45:12.286568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
16148 11:45:12.319106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
16149 11:45:12.319592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
16151 11:45:12.350110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
16153 11:45:12.350758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
16154 11:45:12.381032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
16156 11:45:12.381661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
16157 11:45:12.411218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
16159 11:45:12.411805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
16160 11:45:12.441962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
16162 11:45:12.442509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
16163 11:45:12.472753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
16164 11:45:12.473207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
16166 11:45:12.503234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
16167 11:45:12.503706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
16169 11:45:12.534004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
16170 11:45:12.534468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
16172 11:45:12.564817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
16173 11:45:12.565295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
16175 11:45:12.595191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
16176 11:45:12.595666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
16178 11:45:12.626478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
16180 11:45:12.627030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
16181 11:45:12.657006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
16182 11:45:12.657482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
16184 11:45:12.689306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
16185 11:45:12.689784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
16187 11:45:12.720380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
16188 11:45:12.720843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
16190 11:45:12.751104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
16192 11:45:12.751713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
16193 11:45:12.782087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16195 11:45:12.782635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16196 11:45:12.813204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16198 11:45:12.813769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16199 11:45:12.844373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16200 11:45:12.844771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16202 11:45:12.876332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16203 11:45:12.876819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16205 11:45:12.907061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16206 11:45:12.907519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16208 11:45:12.938134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16209 11:45:12.938586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16211 11:45:12.969030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16213 11:45:12.969572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16214 11:45:13.000713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16215 11:45:13.001187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16217 11:45:13.031343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16218 11:45:13.031773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16220 11:45:13.061611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16221 11:45:13.062040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16223 11:45:13.092848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16224 11:45:13.093258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16226 11:45:13.123825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16228 11:45:13.124281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16229 11:45:13.154383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16231 11:45:13.154832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16232 11:45:13.186363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16233 11:45:13.186845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16235 11:45:13.217615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16236 11:45:13.218087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16238 11:45:13.247925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16240 11:45:13.248526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16241 11:45:13.279323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16242 11:45:13.279736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16244 11:45:13.309756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16245 11:45:13.310192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16247 11:45:13.340509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16249 11:45:13.340930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16250 11:45:13.371521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16251 11:45:13.371935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16253 11:45:13.402716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16254 11:45:13.403143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16256 11:45:13.434308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16257 11:45:13.434736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16259 11:45:13.465792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16260 11:45:13.466209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16262 11:45:13.496946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16263 11:45:13.497341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16265 11:45:13.528009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16267 11:45:13.528438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16268 11:45:13.559178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16270 11:45:13.559632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16271 11:45:13.590016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16272 11:45:13.590433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16274 11:45:13.621738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16275 11:45:13.622199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16277 11:45:13.653456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16278 11:45:13.653934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16280 11:45:13.685885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16281 11:45:13.686334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16283 11:45:13.717538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16284 11:45:13.718011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16286 11:45:13.748904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16287 11:45:13.749360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16289 11:45:13.780547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16291 11:45:13.781116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16292 11:45:13.811473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16293 11:45:13.811955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16295 11:45:13.842855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16297 11:45:13.843294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16298 11:45:13.874718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16299 11:45:13.875147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16301 11:45:13.905422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16302 11:45:13.905924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16304 11:45:13.937329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16305 11:45:13.937924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16307 11:45:13.969643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16308 11:45:13.970138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16310 11:45:14.001226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16311 11:45:14.001692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16313 11:45:14.031627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16314 11:45:14.032046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16316 11:45:14.062627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16318 11:45:14.063247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16319 11:45:14.093231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16321 11:45:14.093828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16322 11:45:14.123593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16323 11:45:14.124066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16325 11:45:14.155052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16327 11:45:14.155603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16328 11:45:14.186559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16329 11:45:14.186920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16331 11:45:14.218190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16333 11:45:14.218746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16334 11:45:14.249677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16336 11:45:14.250224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16337 11:45:14.280111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16338 11:45:14.280551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16340 11:45:14.310339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16341 11:45:14.310810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16343 11:45:14.341745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16344 11:45:14.342221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16346 11:45:14.374199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16348 11:45:14.374639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16349 11:45:14.407643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16351 11:45:14.408229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16352 11:45:14.440022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16353 11:45:14.440521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16355 11:45:14.470915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16356 11:45:14.471412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16358 11:45:14.502706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16359 11:45:14.503182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16361 11:45:14.533722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16362 11:45:14.534169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16364 11:45:14.564801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16365 11:45:14.565265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16367 11:45:14.595031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16368 11:45:14.595504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16370 11:45:14.626145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16372 11:45:14.626703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16373 11:45:14.657556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16375 11:45:14.658130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16376 11:45:14.689977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16377 11:45:14.690433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16379 11:45:14.721251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16380 11:45:14.721683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16382 11:45:14.751615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16384 11:45:14.752155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16385 11:45:14.782949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16387 11:45:14.783572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16388 11:45:14.813138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16389 11:45:14.813594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16391 11:45:14.843647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16392 11:45:14.844111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16394 11:45:14.874759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16396 11:45:14.875366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16397 11:45:14.904971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16399 11:45:14.905393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16400 11:45:14.935160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16401 11:45:14.935576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16403 11:45:14.966066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16405 11:45:14.966619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16406 11:45:14.996763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16408 11:45:14.997296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16409 11:45:15.027035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16410 11:45:15.027489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16412 11:45:15.058069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16414 11:45:15.058685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16415 11:45:15.089118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16417 11:45:15.089742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16418 11:45:15.119632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16419 11:45:15.120087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16421 11:45:15.152568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16423 11:45:15.153136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16424 11:45:15.185950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16425 11:45:15.186439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16427 11:45:15.217264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16429 11:45:15.217837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16430 11:45:15.247679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16432 11:45:15.248220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16433 11:45:15.278176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16435 11:45:15.278685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16436 11:45:15.308548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16437 11:45:15.308991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16439 11:45:15.338617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16441 11:45:15.339148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16442 11:45:15.369643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16444 11:45:15.370237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16445 11:45:15.399500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16446 11:45:15.399933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16448 11:45:15.430934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16450 11:45:15.431528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16451 11:45:15.462179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16453 11:45:15.462728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16454 11:45:15.493609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16455 11:45:15.494075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16457 11:45:15.524801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16458 11:45:15.525236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16460 11:45:15.556028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16462 11:45:15.556459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16463 11:45:15.587090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16464 11:45:15.587521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16466 11:45:15.618423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16468 11:45:15.618871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16469 11:45:15.649429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16470 11:45:15.649851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16472 11:45:15.681610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16474 11:45:15.682044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16475 11:45:15.712717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16477 11:45:15.713135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16478 11:45:15.743501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16479 11:45:15.743957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16481 11:45:15.775127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16482 11:45:15.775557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16484 11:45:15.806808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16486 11:45:15.807389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16487 11:45:15.837889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16489 11:45:15.838321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16490 11:45:15.869947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16491 11:45:15.870352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16493 11:45:15.902043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16494 11:45:15.902441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16496 11:45:15.933707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16498 11:45:15.934145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16499 11:45:15.965238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16501 11:45:15.965682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16502 11:45:15.996723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16503 11:45:15.997161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16505 11:45:16.027421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16506 11:45:16.027872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16508 11:45:16.058617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16510 11:45:16.059159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16511 11:45:16.089979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16512 11:45:16.090379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16514 11:45:16.121458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16515 11:45:16.121879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16517 11:45:16.153035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16519 11:45:16.153465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16520 11:45:16.186669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16521 11:45:16.187102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16523 11:45:16.219870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16525 11:45:16.220345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16526 11:45:16.253131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16527 11:45:16.253556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16529 11:45:16.290152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16531 11:45:16.290596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16532 11:45:16.326554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16533 11:45:16.326953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16535 11:45:16.359835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16537 11:45:16.360304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16538 11:45:16.393991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16540 11:45:16.394408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16541 11:45:16.428560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16542 11:45:16.428977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16544 11:45:16.462352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16546 11:45:16.462790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16547 11:45:16.495165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16548 11:45:16.495610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16550 11:45:16.529310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16551 11:45:16.529727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16553 11:45:16.562737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16554 11:45:16.563199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16556 11:45:16.596833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16557 11:45:16.597306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16559 11:45:16.630011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16561 11:45:16.630465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16562 11:45:16.664732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16563 11:45:16.665180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16565 11:45:16.698863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16567 11:45:16.699451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16568 11:45:16.732764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16569 11:45:16.733236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16571 11:45:16.766087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16572 11:45:16.766539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16574 11:45:16.799623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16576 11:45:16.800102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16577 11:45:16.831936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16579 11:45:16.832408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16580 11:45:16.864550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16581 11:45:16.864974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16583 11:45:16.898919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16584 11:45:16.899367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16586 11:45:16.933119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16587 11:45:16.933586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16589 11:45:16.966694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16590 11:45:16.967181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16592 11:45:17.000838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16593 11:45:17.001306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16595 11:45:17.034657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16596 11:45:17.035141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16598 11:45:17.068483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16599 11:45:17.068967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16601 11:45:17.102169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16602 11:45:17.102640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16604 11:45:17.137062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16605 11:45:17.137530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16607 11:45:17.171829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16609 11:45:17.172439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16610 11:45:17.207400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16611 11:45:17.207885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16613 11:45:17.241548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16614 11:45:17.242037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16616 11:45:17.276462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16617 11:45:17.276935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16619 11:45:17.310031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16620 11:45:17.310469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16622 11:45:17.344525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16623 11:45:17.344939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16625 11:45:17.378633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16626 11:45:17.379067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16628 11:45:17.412890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16629 11:45:17.413362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16631 11:45:17.447018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16632 11:45:17.447476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16634 11:45:17.481346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16635 11:45:17.481783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16637 11:45:17.515858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16639 11:45:17.516498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16640 11:45:17.551146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16642 11:45:17.551706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16643 11:45:17.585049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16644 11:45:17.585521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16646 11:45:17.619593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16647 11:45:17.620046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16649 11:45:17.653551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16650 11:45:17.653986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16652 11:45:17.687995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16654 11:45:17.688602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16655 11:45:17.722166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16656 11:45:17.722630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16658 11:45:17.756522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16660 11:45:17.757169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16661 11:45:17.796792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16662 11:45:17.797291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16664 11:45:17.830908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16666 11:45:17.831469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16667 11:45:17.864897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16668 11:45:17.865350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16670 11:45:17.898434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16671 11:45:17.898865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16673 11:45:17.932484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16675 11:45:17.933081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16676 11:45:17.966103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16678 11:45:17.966686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16679 11:45:18.000123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16681 11:45:18.000588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16682 11:45:18.035848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16684 11:45:18.036322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16685 11:45:18.070460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16687 11:45:18.070916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16688 11:45:18.105011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16689 11:45:18.105455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16691 11:45:18.139235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16693 11:45:18.139692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16694 11:45:18.173712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16696 11:45:18.174172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16697 11:45:18.208121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16699 11:45:18.208578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16700 11:45:18.242505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16702 11:45:18.242963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16703 11:45:18.276703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16705 11:45:18.277140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16706 11:45:18.311240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16708 11:45:18.311975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16709 11:45:18.345410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16711 11:45:18.346072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16712 11:45:18.380010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16714 11:45:18.380448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16715 11:45:18.415198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16716 11:45:18.415580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16718 11:45:18.450020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16720 11:45:18.450596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16721 11:45:18.484845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16723 11:45:18.485488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16724 11:45:18.519249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16725 11:45:18.519723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16727 11:45:18.554222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16729 11:45:18.554851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16730 11:45:18.589183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16731 11:45:18.589701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16733 11:45:18.625044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16735 11:45:18.625450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16736 11:45:18.660285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16737 11:45:18.660782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16739 11:45:18.695111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16740 11:45:18.695585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16742 11:45:18.729945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16744 11:45:18.730589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16745 11:45:18.764883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16746 11:45:18.765339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16748 11:45:18.800071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16750 11:45:18.800837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16751 11:45:18.834245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16753 11:45:18.834807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16754 11:45:18.869164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16756 11:45:18.869745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16757 11:45:18.902825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16758 11:45:18.903242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16760 11:45:18.937359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16761 11:45:18.937784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16763 11:45:18.971362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16764 11:45:18.971854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16766 11:45:19.005673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16768 11:45:19.006246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16769 11:45:19.039579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16770 11:45:19.040014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16772 11:45:19.074585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16774 11:45:19.075047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16775 11:45:19.109359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16777 11:45:19.109936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16778 11:45:19.147129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16779 11:45:19.147618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16781 11:45:19.182203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16782 11:45:19.182664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16784 11:45:19.217077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16786 11:45:19.217660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16787 11:45:19.251238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16788 11:45:19.251726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16790 11:45:19.285604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16792 11:45:19.286188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16793 11:45:19.320112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16795 11:45:19.320690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16796 11:45:19.354803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16798 11:45:19.355351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16799 11:45:19.388853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16801 11:45:19.389414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16802 11:45:19.422854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16804 11:45:19.423435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16805 11:45:19.457025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16807 11:45:19.457666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16808 11:45:19.491620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16810 11:45:19.492244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16811 11:45:19.526046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16813 11:45:19.526686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16814 11:45:19.559824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16816 11:45:19.560450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16817 11:45:19.594104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16819 11:45:19.594571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16820 11:45:19.628359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16821 11:45:19.628807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16823 11:45:19.663049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16824 11:45:19.663461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16826 11:45:19.697848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16827 11:45:19.698319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16829 11:45:19.733047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16831 11:45:19.733601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16832 11:45:19.767655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16834 11:45:19.768207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16835 11:45:19.802519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16837 11:45:19.802978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16838 11:45:19.837267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16840 11:45:19.837857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16841 11:45:19.872017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16843 11:45:19.872574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16844 11:45:19.906465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16846 11:45:19.906985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16847 11:45:19.941140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16849 11:45:19.941613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16850 11:45:19.975556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16852 11:45:19.976148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16853 11:45:20.010405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16855 11:45:20.010992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16856 11:45:20.045152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16857 11:45:20.045640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16859 11:45:20.078871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16861 11:45:20.079426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16862 11:45:20.112893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16863 11:45:20.113355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16865 11:45:20.146103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16866 11:45:20.146565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16868 11:45:20.179360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16869 11:45:20.179833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16871 11:45:20.213670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16872 11:45:20.214117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16874 11:45:20.248971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16875 11:45:20.249420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16877 11:45:20.283263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16878 11:45:20.283705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16880 11:45:20.318412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16881 11:45:20.318844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16883 11:45:20.353674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16885 11:45:20.354146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16886 11:45:20.389009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16887 11:45:20.389445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16889 11:45:20.424861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16891 11:45:20.425318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16892 11:45:20.459476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16893 11:45:20.459953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16895 11:45:20.495174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16897 11:45:20.495806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16898 11:45:20.530194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16899 11:45:20.530659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16901 11:45:20.567813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16903 11:45:20.568289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16904 11:45:20.603395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16906 11:45:20.603868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16907 11:45:20.638632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16908 11:45:20.639107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16910 11:45:20.673152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16911 11:45:20.673617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16913 11:45:20.707470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16914 11:45:20.707930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16916 11:45:20.741614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16917 11:45:20.742089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16919 11:45:20.776837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16920 11:45:20.777295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16922 11:45:20.811266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16924 11:45:20.811848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16925 11:45:20.845655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16927 11:45:20.846224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16928 11:45:20.884690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16930 11:45:20.885333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16931 11:45:20.919143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16933 11:45:20.919713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16934 11:45:20.952988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16935 11:45:20.953480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16937 11:45:20.987580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16939 11:45:20.988130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16940 11:45:21.021784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16941 11:45:21.022267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16943 11:45:21.056435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16945 11:45:21.056990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16946 11:45:21.090573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
16948 11:45:21.091030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16949 11:45:21.125375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
16951 11:45:21.125968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
16952 11:45:21.160449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
16954 11:45:21.161141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
16955 11:45:21.197426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
16957 11:45:21.197867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
16958 11:45:21.239695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
16960 11:45:21.240311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
16961 11:45:21.278390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
16963 11:45:21.278851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
16964 11:45:21.315577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
16966 11:45:21.316174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
16967 11:45:21.352437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
16968 11:45:21.352813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
16970 11:45:21.388924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
16972 11:45:21.389403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
16973 11:45:21.424445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
16975 11:45:21.425083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
16976 11:45:21.459396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
16977 11:45:21.459875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
16979 11:45:21.494939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
16980 11:45:21.495406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
16982 11:45:21.530046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
16983 11:45:21.530500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
16985 11:45:21.564878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
16987 11:45:21.565349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
16988 11:45:21.599620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
16989 11:45:21.600106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
16991 11:45:21.635219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
16993 11:45:21.635884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
16994 11:45:21.670731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
16996 11:45:21.671282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
16997 11:45:21.705964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
16999 11:45:21.706509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
17000 11:45:21.742465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
17001 11:45:21.742938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
17003 11:45:21.777468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
17005 11:45:21.778034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
17006 11:45:21.812508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
17007 11:45:21.812965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
17009 11:45:21.847372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
17011 11:45:21.847913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
17012 11:45:21.882253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
17013 11:45:21.882723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
17015 11:45:21.917517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
17017 11:45:21.918138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
17018 11:45:21.952480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
17020 11:45:21.953041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
17021 11:45:21.989039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
17023 11:45:21.989616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
17024 11:45:22.025644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
17025 11:45:22.026131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
17027 11:45:22.061089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
17029 11:45:22.061536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
17030 11:45:22.095990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
17032 11:45:22.096476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
17033 11:45:22.133431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
17035 11:45:22.133912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
17036 11:45:22.168356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
17038 11:45:22.168790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
17039 11:45:22.203383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
17040 11:45:22.203804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
17042 11:45:22.239263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
17044 11:45:22.239948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
17045 11:45:22.273813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
17046 11:45:22.274315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
17048 11:45:22.310484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
17050 11:45:22.311128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
17051 11:45:22.346993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
17052 11:45:22.347428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
17054 11:45:22.383628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
17056 11:45:22.384099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
17057 11:45:22.427685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
17059 11:45:22.428308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
17060 11:45:22.462781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
17061 11:45:22.463228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
17063 11:45:22.497024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
17064 11:45:22.497464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
17066 11:45:22.534380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
17068 11:45:22.534849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
17069 11:45:22.569683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
17070 11:45:22.570143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
17072 11:45:22.605867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
17074 11:45:22.606340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
17075 11:45:22.640896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
17077 11:45:22.641370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
17078 11:45:22.676422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
17080 11:45:22.676898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
17081 11:45:22.711215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
17082 11:45:22.711654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
17084 11:45:22.746886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
17085 11:45:22.747326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
17087 11:45:22.781921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
17089 11:45:22.782575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
17090 11:45:22.817041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
17091 11:45:22.817485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
17093 11:45:22.852808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
17094 11:45:22.853239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
17096 11:45:22.888715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
17097 11:45:22.889177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
17099 11:45:22.923977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
17101 11:45:22.924814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
17102 11:45:22.960765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
17103 11:45:22.961217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
17105 11:45:22.998256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
17106 11:45:22.998711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
17108 11:45:23.035057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
17110 11:45:23.035525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
17111 11:45:23.070993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
17112 11:45:23.071460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
17114 11:45:23.106906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
17116 11:45:23.107469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
17117 11:45:23.142568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
17118 11:45:23.143040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
17120 11:45:23.179044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
17122 11:45:23.179496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
17123 11:45:23.215906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
17125 11:45:23.216388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
17126 11:45:23.251321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
17127 11:45:23.251776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
17129 11:45:23.287507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
17130 11:45:23.287957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
17132 11:45:23.323366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
17134 11:45:23.324035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
17135 11:45:23.357423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
17136 11:45:23.357873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
17138 11:45:23.393193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
17140 11:45:23.393856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
17141 11:45:23.429146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
17142 11:45:23.429637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
17144 11:45:23.465587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
17145 11:45:23.466037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
17147 11:45:23.500201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
17148 11:45:23.500650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
17150 11:45:23.534977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
17151 11:45:23.535457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
17153 11:45:23.570990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
17154 11:45:23.571473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
17156 11:45:23.605054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
17157 11:45:23.605527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
17159 11:45:23.640219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
17161 11:45:23.640714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
17162 11:45:23.675007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
17163 11:45:23.675463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
17165 11:45:23.710349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
17167 11:45:23.710908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
17168 11:45:23.744959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
17169 11:45:23.745436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
17171 11:45:23.779134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
17172 11:45:23.779545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
17174 11:45:23.814188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
17175 11:45:23.814602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
17177 11:45:23.849074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
17179 11:45:23.849527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
17180 11:45:23.884020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
17182 11:45:23.884435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
17183 11:45:23.919517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
17185 11:45:23.919981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
17186 11:45:23.954439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
17187 11:45:23.954912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
17189 11:45:23.989170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
17190 11:45:23.989674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
17192 11:45:24.024222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
17193 11:45:24.024721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17195 11:45:24.058904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17196 11:45:24.059392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17198 11:45:24.093296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17199 11:45:24.093681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17201 11:45:24.128775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17203 11:45:24.129202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17204 11:45:24.163607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17205 11:45:24.164068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17207 11:45:24.198495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17208 11:45:24.198911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17210 11:45:24.233118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17211 11:45:24.233554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17213 11:45:24.268467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17215 11:45:24.269056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17216 11:45:24.303486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17217 11:45:24.303938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17219 11:45:24.338332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17220 11:45:24.338742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17222 11:45:24.373317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17223 11:45:24.373737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17225 11:45:24.408335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17226 11:45:24.408742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17228 11:45:24.443757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17229 11:45:24.444178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17231 11:45:24.479303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17232 11:45:24.479724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17234 11:45:24.514506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17235 11:45:24.514921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17237 11:45:24.550146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17239 11:45:24.550571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17240 11:45:24.585722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17242 11:45:24.586186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17243 11:45:24.620943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17245 11:45:24.621584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17246 11:45:24.655557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17248 11:45:24.656229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17249 11:45:24.690856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17251 11:45:24.691496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17252 11:45:24.724987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17253 11:45:24.725474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17255 11:45:24.760267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17257 11:45:24.760782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17258 11:45:24.796645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17259 11:45:24.797072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17261 11:45:24.831385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17263 11:45:24.832040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17264 11:45:24.866937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17265 11:45:24.867416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17267 11:45:24.904828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17268 11:45:24.905290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17270 11:45:24.938939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17271 11:45:24.939430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17273 11:45:24.973422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17275 11:45:24.974011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17276 11:45:25.007336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17277 11:45:25.007801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17279 11:45:25.041942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17281 11:45:25.042493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17282 11:45:25.079045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17284 11:45:25.079602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17285 11:45:25.113804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17287 11:45:25.114289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17288 11:45:25.149715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17289 11:45:25.150145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17291 11:45:25.185289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17292 11:45:25.185775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17294 11:45:25.220758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17296 11:45:25.221218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17297 11:45:25.256309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17298 11:45:25.256747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17300 11:45:25.291286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17301 11:45:25.291731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17303 11:45:25.326090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17304 11:45:25.326582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17306 11:45:25.361070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17307 11:45:25.361539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17309 11:45:25.395639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17311 11:45:25.396198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17312 11:45:25.430477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17313 11:45:25.430943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17315 11:45:25.464836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17316 11:45:25.465311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17318 11:45:25.500062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17320 11:45:25.500626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17321 11:45:25.534485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17322 11:45:25.534929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17324 11:45:25.569234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17325 11:45:25.569681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17327 11:45:25.605407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17329 11:45:25.606050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17330 11:45:25.641678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17331 11:45:25.642115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17333 11:45:25.678078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17334 11:45:25.678574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17336 11:45:25.714936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17337 11:45:25.715403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17339 11:45:25.752892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17341 11:45:25.753362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17342 11:45:25.789804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17343 11:45:25.790294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17345 11:45:25.826606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17346 11:45:25.827080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17348 11:45:25.861733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17349 11:45:25.862195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17351 11:45:25.896628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17353 11:45:25.897186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17354 11:45:25.931134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17356 11:45:25.931709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17357 11:45:25.965901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17358 11:45:25.966360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17360 11:45:26.000710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17361 11:45:26.001160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17363 11:45:26.036522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17364 11:45:26.036931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17366 11:45:26.070537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17367 11:45:26.070980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17369 11:45:26.105101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17370 11:45:26.105554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17372 11:45:26.140065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17374 11:45:26.140698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17375 11:45:26.174990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17376 11:45:26.175415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17378 11:45:26.210244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17379 11:45:26.210732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17381 11:45:26.245706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17382 11:45:26.246122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17384 11:45:26.282782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17386 11:45:26.283250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17387 11:45:26.318759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17388 11:45:26.319220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17390 11:45:26.354441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17391 11:45:26.354906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17393 11:45:26.389432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17395 11:45:26.389968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17396 11:45:26.424992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17398 11:45:26.425552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17399 11:45:26.459970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17401 11:45:26.460528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17402 11:45:26.495701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17404 11:45:26.496248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17405 11:45:26.530928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17406 11:45:26.531345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17408 11:45:26.567338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17409 11:45:26.567782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17411 11:45:26.602053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17413 11:45:26.602508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17414 11:45:26.637385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17416 11:45:26.637854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17417 11:45:26.673414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17419 11:45:26.674059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17420 11:45:26.709199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17421 11:45:26.709705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17423 11:45:26.745141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17424 11:45:26.745615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17426 11:45:26.779892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17428 11:45:26.780452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17429 11:45:26.815325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17430 11:45:26.815762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17432 11:45:26.849678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17434 11:45:26.850121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17435 11:45:26.885012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17436 11:45:26.885431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17438 11:45:26.920049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17440 11:45:26.920471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17441 11:45:26.955111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17442 11:45:26.955590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17444 11:45:26.989881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17446 11:45:26.990523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17447 11:45:27.025347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17448 11:45:27.025772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17450 11:45:27.061594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17452 11:45:27.062035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17453 11:45:27.097102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17455 11:45:27.097560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17456 11:45:27.132568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17457 11:45:27.133055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17459 11:45:27.167510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17460 11:45:27.167961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17462 11:45:27.202375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17463 11:45:27.202823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17465 11:45:27.237672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17466 11:45:27.238095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17468 11:45:27.272864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17470 11:45:27.273423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17471 11:45:27.307975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17473 11:45:27.308506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17474 11:45:27.343143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17476 11:45:27.343746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17477 11:45:27.378257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17479 11:45:27.378753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17480 11:45:27.414693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17482 11:45:27.415255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17483 11:45:27.449187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17484 11:45:27.449594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17486 11:45:27.484455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17488 11:45:27.484874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17489 11:45:27.519498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17491 11:45:27.519978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17492 11:45:27.557135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17494 11:45:27.557592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17495 11:45:27.598818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17497 11:45:27.599279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17498 11:45:27.640973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17499 11:45:27.641432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17501 11:45:27.678333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17502 11:45:27.678710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17504 11:45:27.716251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17505 11:45:27.716652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17507 11:45:27.752968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17508 11:45:27.753443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17510 11:45:27.787490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17511 11:45:27.787945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17513 11:45:27.823093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17514 11:45:27.823495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17516 11:45:27.860855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17517 11:45:27.861354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17519 11:45:27.897273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17520 11:45:27.897751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17522 11:45:27.931819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17524 11:45:27.932333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17525 11:45:27.967817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17527 11:45:27.968216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17528 11:45:28.003869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17530 11:45:28.004497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17531 11:45:28.039596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17533 11:45:28.040220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17534 11:45:28.074335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17536 11:45:28.074801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17537 11:45:28.109165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17539 11:45:28.109614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17540 11:45:28.144313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17541 11:45:28.144730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17543 11:45:28.179559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17544 11:45:28.179980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17546 11:45:28.215443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17547 11:45:28.215863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17549 11:45:28.251234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17550 11:45:28.251712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17552 11:45:28.287046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17553 11:45:28.287521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17555 11:45:28.321947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17556 11:45:28.322366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17558 11:45:28.356544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17560 11:45:28.356965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17561 11:45:28.390770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17563 11:45:28.391229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17564 11:45:28.425621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17566 11:45:28.426275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17567 11:45:28.460824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17569 11:45:28.461471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17570 11:45:28.495235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17571 11:45:28.495710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17573 11:45:28.529888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17574 11:45:28.530364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17576 11:45:28.564534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17577 11:45:28.565019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17579 11:45:28.600639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17581 11:45:28.601290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17582 11:45:28.635692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17584 11:45:28.636234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17585 11:45:28.669957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17586 11:45:28.670432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17588 11:45:28.704592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17589 11:45:28.705063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17591 11:45:28.738793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17592 11:45:28.739195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17594 11:45:28.773719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17595 11:45:28.774138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17597 11:45:28.809212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17598 11:45:28.809690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17600 11:45:28.845000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17601 11:45:28.845480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17603 11:45:28.880431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17604 11:45:28.880862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17606 11:45:28.915382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17608 11:45:28.915810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17609 11:45:28.950934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17611 11:45:28.951524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17612 11:45:28.986010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17613 11:45:28.986502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17615 11:45:29.021135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17616 11:45:29.021601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17618 11:45:29.056464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17620 11:45:29.057016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17621 11:45:29.090005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17622 11:45:29.090487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17624 11:45:29.125371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17625 11:45:29.125826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17627 11:45:29.160845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17629 11:45:29.161358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17630 11:45:29.196763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17631 11:45:29.197169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17633 11:45:29.232255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17635 11:45:29.232776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17636 11:45:29.268532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17637 11:45:29.268985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17639 11:45:29.304514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17640 11:45:29.304960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17642 11:45:29.341158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17644 11:45:29.341640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17645 11:45:29.377166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17646 11:45:29.377594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17648 11:45:29.412442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17650 11:45:29.412913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17651 11:45:29.447506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17653 11:45:29.447976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17654 11:45:29.482634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17655 11:45:29.483113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17657 11:45:29.517149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17658 11:45:29.517620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17660 11:45:29.552116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17662 11:45:29.552675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17663 11:45:29.587382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17664 11:45:29.587845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17666 11:45:29.622436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17667 11:45:29.622891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17669 11:45:29.657451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17671 11:45:29.657935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17672 11:45:29.693229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17673 11:45:29.693689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17675 11:45:29.728813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17676 11:45:29.729263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17678 11:45:29.763793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17680 11:45:29.764282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17681 11:45:29.798921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17682 11:45:29.799361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17684 11:45:29.834197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17685 11:45:29.834684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17687 11:45:29.869036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17689 11:45:29.869612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17690 11:45:29.904297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17691 11:45:29.904674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17693 11:45:29.939479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17695 11:45:29.939861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17696 11:45:29.974371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17697 11:45:29.974781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17699 11:45:30.010171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17701 11:45:30.010548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17702 11:45:30.045305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17703 11:45:30.045675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17705 11:45:30.080514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17706 11:45:30.080966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17708 11:45:30.115449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17709 11:45:30.115891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17711 11:45:30.151143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17713 11:45:30.151610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17714 11:45:30.185427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17716 11:45:30.186070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17717 11:45:30.220700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17719 11:45:30.221350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17720 11:45:30.255317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17721 11:45:30.255796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17723 11:45:30.290407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17725 11:45:30.290965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17726 11:45:30.325303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17728 11:45:30.325876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17729 11:45:30.359441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17730 11:45:30.359890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17732 11:45:30.394774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17733 11:45:30.395235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17735 11:45:30.430452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17737 11:45:30.430920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17738 11:45:30.466168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17739 11:45:30.466592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17741 11:45:30.501437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17743 11:45:30.501911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17744 11:45:30.536475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17745 11:45:30.536923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17747 11:45:30.572410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17749 11:45:30.572838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17750 11:45:30.607298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17752 11:45:30.607768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17753 11:45:30.642934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17755 11:45:30.643394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17756 11:45:30.678474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17758 11:45:30.678952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17759 11:45:30.713127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17761 11:45:30.713590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17762 11:45:30.748029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17764 11:45:30.748493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17765 11:45:30.785281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17767 11:45:30.785753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17768 11:45:30.821891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17769 11:45:30.822334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17771 11:45:30.857670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17772 11:45:30.858090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17774 11:45:30.893543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17775 11:45:30.893970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17777 11:45:30.929116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17779 11:45:30.929585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17780 11:45:30.963556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17781 11:45:30.963998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17783 11:45:30.998918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17785 11:45:30.999395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17786 11:45:31.033838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17788 11:45:31.034307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17789 11:45:31.069186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17790 11:45:31.069610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17792 11:45:31.105371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17794 11:45:31.105850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17795 11:45:31.141502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17797 11:45:31.141991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17798 11:45:31.177122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17799 11:45:31.177564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17801 11:45:31.213126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17802 11:45:31.213625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17804 11:45:31.250113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17806 11:45:31.250672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17807 11:45:31.286570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17808 11:45:31.287104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17810 11:45:31.323483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17811 11:45:31.323959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17813 11:45:31.362056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17815 11:45:31.362432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17816 11:45:31.398774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17817 11:45:31.399215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17819 11:45:31.434921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17820 11:45:31.435369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17822 11:45:31.471067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17824 11:45:31.471533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17825 11:45:31.507182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17827 11:45:31.507751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17828 11:45:31.543257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17829 11:45:31.543731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17831 11:45:31.578992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17833 11:45:31.579540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17834 11:45:31.615154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17836 11:45:31.615710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17837 11:45:31.650598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17838 11:45:31.651050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17840 11:45:31.685499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17841 11:45:31.685984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17843 11:45:31.721108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17844 11:45:31.721600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17846 11:45:31.756732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17847 11:45:31.757174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17849 11:45:31.791260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17851 11:45:31.791784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17852 11:45:31.826167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17854 11:45:31.826680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17855 11:45:31.860807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17856 11:45:31.861214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17858 11:45:31.895893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17860 11:45:31.896434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17861 11:45:31.931106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17862 11:45:31.931520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17864 11:45:31.966882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17866 11:45:31.967393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17867 11:45:32.002054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17869 11:45:32.002588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17870 11:45:32.036445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17872 11:45:32.037039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17873 11:45:32.072872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17874 11:45:32.073342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17876 11:45:32.107119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17877 11:45:32.107605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17879 11:45:32.142191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17880 11:45:32.142651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17882 11:45:32.178159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17884 11:45:32.178627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17885 11:45:32.213293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17887 11:45:32.213736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17888 11:45:32.249621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17889 11:45:32.250058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17891 11:45:32.284709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17892 11:45:32.285132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17894 11:45:32.319265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17895 11:45:32.319687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17897 11:45:32.353926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17899 11:45:32.354382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17900 11:45:32.389287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17902 11:45:32.389867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17903 11:45:32.425372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17905 11:45:32.425805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17906 11:45:32.460545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17907 11:45:32.460947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17909 11:45:32.495632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17910 11:45:32.496107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17912 11:45:32.531282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17914 11:45:32.531731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17915 11:45:32.565791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17917 11:45:32.566351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17918 11:45:32.601169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17919 11:45:32.601545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17921 11:45:32.636801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17922 11:45:32.637192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17924 11:45:32.671819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17926 11:45:32.672267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17927 11:45:32.707139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17928 11:45:32.707508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17930 11:45:32.742481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17931 11:45:32.742888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17933 11:45:32.777321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17934 11:45:32.777754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17936 11:45:32.811756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17938 11:45:32.812329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17939 11:45:32.847340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17940 11:45:32.847790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17942 11:45:32.883240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17943 11:45:32.883657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17945 11:45:32.918016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17946 11:45:32.918431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17948 11:45:32.952865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
17949 11:45:32.953304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
17951 11:45:32.988409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
17953 11:45:32.988936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
17954 11:45:33.023134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
17955 11:45:33.023552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
17957 11:45:33.058694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
17959 11:45:33.059232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
17960 11:45:33.094002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
17962 11:45:33.094570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
17963 11:45:33.130304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
17965 11:45:33.130887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
17966 11:45:33.169049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
17968 11:45:33.169711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
17969 11:45:33.204577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
17971 11:45:33.205199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
17972 11:45:33.239928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
17974 11:45:33.240489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
17975 11:45:33.274271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
17976 11:45:33.274658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
17978 11:45:33.309678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
17979 11:45:33.310123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
17981 11:45:33.345460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
17982 11:45:33.345891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
17984 11:45:33.382257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
17985 11:45:33.382704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
17987 11:45:33.416509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
17988 11:45:33.416945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
17990 11:45:33.451692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
17992 11:45:33.452339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
17993 11:45:33.487576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
17994 11:45:33.488050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
17996 11:45:33.524709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
17998 11:45:33.525167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
17999 11:45:33.560425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
18000 11:45:33.560910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
18002 11:45:33.595751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
18004 11:45:33.596360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
18005 11:45:33.632040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
18007 11:45:33.632590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
18008 11:45:33.669404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
18010 11:45:33.669892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
18011 11:45:33.703801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
18013 11:45:33.704433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
18014 11:45:33.738367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
18015 11:45:33.738834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
18017 11:45:33.772849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
18019 11:45:33.773426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
18020 11:45:33.807002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
18021 11:45:33.807467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
18023 11:45:33.841395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
18024 11:45:33.841906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
18026 11:45:33.877171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
18028 11:45:33.877723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
18029 11:45:33.912343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
18030 11:45:33.912812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
18032 11:45:33.946878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
18034 11:45:33.947437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
18035 11:45:33.981684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
18037 11:45:33.982252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
18038 11:45:34.017076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
18040 11:45:34.017639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
18041 11:45:34.051618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
18042 11:45:34.052068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
18044 11:45:34.086226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
18046 11:45:34.086766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
18047 11:45:34.120924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
18049 11:45:34.121475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
18050 11:45:34.157172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
18052 11:45:34.157785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
18053 11:45:34.193114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
18055 11:45:34.193582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
18056 11:45:34.228853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
18057 11:45:34.229291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
18059 11:45:34.264358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
18060 11:45:34.264849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
18062 11:45:34.299892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
18064 11:45:34.300382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
18065 11:45:34.335037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
18067 11:45:34.335492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
18068 11:45:34.370195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
18070 11:45:34.370675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
18071 11:45:34.406797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
18073 11:45:34.407273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
18074 11:45:34.442287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
18075 11:45:34.442784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
18077 11:45:34.477038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
18078 11:45:34.477498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
18080 11:45:34.513550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
18081 11:45:34.514043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
18083 11:45:34.548537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
18084 11:45:34.549017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
18086 11:45:34.583113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
18087 11:45:34.583581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
18089 11:45:34.617752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
18090 11:45:34.618241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
18092 11:45:34.652793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
18093 11:45:34.653273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
18095 11:45:34.687545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
18096 11:45:34.688017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
18098 11:45:34.723151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
18100 11:45:34.723781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
18101 11:45:34.758513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
18102 11:45:34.758967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
18104 11:45:34.794345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
18105 11:45:34.794796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
18107 11:45:34.830311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
18109 11:45:34.830774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
18110 11:45:34.868879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
18112 11:45:34.869354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
18113 11:45:34.906949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
18114 11:45:34.907373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
18116 11:45:34.946214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
18117 11:45:34.946653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
18119 11:45:34.981250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
18120 11:45:34.981694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
18122 11:45:35.017466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
18123 11:45:35.017920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
18125 11:45:35.052717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
18126 11:45:35.053207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
18128 11:45:35.087433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
18130 11:45:35.088013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
18131 11:45:35.122517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
18132 11:45:35.123000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
18134 11:45:35.158148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
18136 11:45:35.158604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
18137 11:45:35.195130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
18138 11:45:35.195548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
18140 11:45:35.244518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
18142 11:45:35.244983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
18143 11:45:35.281003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
18144 11:45:35.281431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
18146 11:45:35.316374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
18147 11:45:35.316820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
18149 11:45:35.350838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
18151 11:45:35.351306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
18152 11:45:35.385716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
18154 11:45:35.386177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
18155 11:45:35.419965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
18157 11:45:35.420436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
18158 11:45:35.454560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
18159 11:45:35.455002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
18161 11:45:35.489387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
18163 11:45:35.489871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
18164 11:45:35.524675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
18165 11:45:35.525152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
18167 11:45:35.560195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
18168 11:45:35.560659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
18170 11:45:35.597014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
18171 11:45:35.597483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
18173 11:45:35.637592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
18174 11:45:35.638087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
18176 11:45:35.674395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
18177 11:45:35.674876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
18179 11:45:35.709479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
18181 11:45:35.709945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
18182 11:45:35.744622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
18184 11:45:35.745105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
18185 11:45:35.779186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
18186 11:45:35.779609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
18188 11:45:35.813655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
18190 11:45:35.814114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
18191 11:45:35.848348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18192 11:45:35.848810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
18194 11:45:35.882677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18195 11:45:35.883123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18197 11:45:35.917272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18198 11:45:35.917699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18200 11:45:35.952893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18202 11:45:35.953523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18203 11:45:35.987497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18204 11:45:35.987958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18206 11:45:36.022627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18208 11:45:36.023177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18209 11:45:36.057302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18211 11:45:36.057876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18212 11:45:36.092284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18213 11:45:36.092756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18215 11:45:36.126297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18216 11:45:36.126760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18218 11:45:36.161687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18219 11:45:36.162134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18221 11:45:36.196467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18223 11:45:36.197166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18224 11:45:36.232406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18225 11:45:36.232817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18227 11:45:36.268513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18228 11:45:36.268930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18230 11:45:36.307705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18232 11:45:36.308154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18233 11:45:36.351941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18235 11:45:36.352369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18236 11:45:36.403135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18237 11:45:36.403578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18239 11:45:36.440283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18240 11:45:36.440748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18242 11:45:36.474534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18243 11:45:36.475003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18245 11:45:36.509316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18247 11:45:36.509884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18248 11:45:36.543891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18250 11:45:36.544320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18251 11:45:36.578852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18252 11:45:36.579329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18254 11:45:36.613579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18255 11:45:36.614015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18257 11:45:36.648341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18259 11:45:36.648903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18260 11:45:36.682253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18262 11:45:36.682816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18263 11:45:36.716691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18264 11:45:36.717127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18266 11:45:36.751292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18267 11:45:36.751699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18269 11:45:36.785728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18271 11:45:36.786310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18272 11:45:36.820827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18273 11:45:36.821305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18275 11:45:36.855309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18276 11:45:36.855778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18278 11:45:36.889788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18280 11:45:36.890359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18281 11:45:36.924412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18282 11:45:36.924891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18284 11:45:36.958737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18285 11:45:36.959202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18287 11:45:36.993197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18289 11:45:36.993572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18290 11:45:37.027779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18292 11:45:37.028255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18293 11:45:37.062564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18295 11:45:37.063020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18296 11:45:37.097643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18297 11:45:37.098090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18299 11:45:37.132655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18301 11:45:37.133129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18302 11:45:37.167000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18303 11:45:37.167434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18305 11:45:37.201640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18306 11:45:37.202066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18308 11:45:37.236441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18309 11:45:37.236871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18311 11:45:37.270609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18312 11:45:37.271065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18314 11:45:37.307370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18315 11:45:37.307820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18317 11:45:37.343533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18318 11:45:37.344026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18320 11:45:37.378556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18322 11:45:37.379014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18323 11:45:37.413314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18324 11:45:37.413749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18326 11:45:37.449090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18327 11:45:37.449514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18329 11:45:37.484343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18330 11:45:37.484763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18332 11:45:37.518803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18333 11:45:37.519227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18335 11:45:37.553733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18336 11:45:37.554172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18338 11:45:37.589067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18339 11:45:37.589510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18341 11:45:37.624779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18343 11:45:37.625260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18344 11:45:37.660511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18345 11:45:37.660954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18347 11:45:37.695468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18348 11:45:37.695902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18350 11:45:37.730711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18351 11:45:37.731146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18353 11:45:37.765327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18355 11:45:37.765933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18356 11:45:37.800844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18358 11:45:37.801485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18359 11:45:37.835472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18360 11:45:37.835952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18362 11:45:37.870561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18364 11:45:37.871113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18365 11:45:37.905432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18367 11:45:37.906000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18368 11:45:37.940387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18369 11:45:37.940852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18371 11:45:37.975102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18373 11:45:37.975641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18374 11:45:38.009248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18376 11:45:38.009822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18377 11:45:38.043915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18379 11:45:38.044561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18380 11:45:38.078149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18382 11:45:38.078777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18383 11:45:38.113240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18385 11:45:38.113711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18386 11:45:38.147691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18388 11:45:38.148130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18389 11:45:38.182529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18390 11:45:38.182982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18392 11:45:38.218039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18393 11:45:38.218516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18395 11:45:38.251740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18396 11:45:38.252223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18398 11:45:38.285939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18400 11:45:38.286511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18401 11:45:38.320994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18402 11:45:38.321478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18404 11:45:38.356254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18405 11:45:38.356729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18407 11:45:38.390548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18409 11:45:38.391012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18410 11:45:38.425973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18411 11:45:38.426360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18413 11:45:38.461121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18415 11:45:38.461561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18416 11:45:38.496562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18417 11:45:38.497038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18419 11:45:38.531270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18421 11:45:38.531710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18422 11:45:38.566078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18424 11:45:38.566638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18425 11:45:38.601064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18427 11:45:38.601506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18428 11:45:38.636261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18429 11:45:38.636689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18431 11:45:38.671144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18432 11:45:38.671572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18434 11:45:38.706248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18435 11:45:38.706681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18437 11:45:38.741269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18438 11:45:38.741678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18440 11:45:38.777667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18441 11:45:38.778102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18443 11:45:38.813253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18445 11:45:38.813831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18446 11:45:38.848475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18448 11:45:38.849050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18449 11:45:38.883484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18450 11:45:38.883926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18452 11:45:38.918499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18453 11:45:38.918936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18455 11:45:38.953071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18456 11:45:38.953517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18458 11:45:38.988477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18459 11:45:38.988915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18461 11:45:39.022900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18462 11:45:39.023341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18464 11:45:39.058419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18466 11:45:39.058880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18467 11:45:39.093054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18469 11:45:39.093518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18470 11:45:39.127557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18471 11:45:39.127983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18473 11:45:39.162524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18475 11:45:39.162982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18476 11:45:39.197355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18477 11:45:39.197826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18479 11:45:39.231698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18481 11:45:39.232147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18482 11:45:39.266919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18484 11:45:39.267362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18485 11:45:39.302134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18487 11:45:39.302702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18488 11:45:39.337718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18490 11:45:39.338284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18491 11:45:39.372888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18492 11:45:39.373358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18494 11:45:39.409080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18496 11:45:39.409640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18497 11:45:39.444848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18499 11:45:39.445275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18500 11:45:39.479701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18502 11:45:39.480126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18503 11:45:39.514897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18504 11:45:39.515343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18506 11:45:39.550695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18508 11:45:39.551137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18509 11:45:39.585268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18510 11:45:39.585690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18512 11:45:39.620554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18514 11:45:39.621111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18515 11:45:39.655236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18517 11:45:39.655822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18518 11:45:39.689916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18520 11:45:39.690490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18521 11:45:39.724899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18522 11:45:39.725369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18524 11:45:39.759228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18525 11:45:39.759697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18527 11:45:39.794254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18529 11:45:39.794717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18530 11:45:39.829060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18531 11:45:39.829480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18533 11:45:39.864097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18535 11:45:39.864557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18536 11:45:39.898849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18537 11:45:39.899282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18539 11:45:39.933781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18541 11:45:39.934357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18542 11:45:39.970359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18543 11:45:39.970802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18545 11:45:40.006510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18546 11:45:40.006898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18548 11:45:40.047549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18550 11:45:40.048017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18551 11:45:40.086609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18552 11:45:40.087005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18554 11:45:40.125674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18555 11:45:40.126090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18557 11:45:40.164761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18558 11:45:40.165176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18560 11:45:40.203527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18561 11:45:40.203921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18563 11:45:40.239061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18564 11:45:40.239468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18566 11:45:40.274091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18567 11:45:40.274527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18569 11:45:40.309610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18570 11:45:40.310080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18572 11:45:40.345280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18573 11:45:40.345760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18575 11:45:40.381129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18577 11:45:40.381610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18578 11:45:40.416839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18580 11:45:40.417304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18581 11:45:40.452876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18582 11:45:40.453322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18584 11:45:40.489695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18585 11:45:40.490115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18587 11:45:40.524647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18588 11:45:40.525072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18590 11:45:40.558681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18591 11:45:40.559156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18593 11:45:40.592760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18594 11:45:40.593244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18596 11:45:40.626805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18597 11:45:40.627294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18599 11:45:40.661438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18600 11:45:40.661937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18602 11:45:40.697070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18603 11:45:40.697480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18605 11:45:40.732469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18606 11:45:40.732972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18608 11:45:40.767310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18609 11:45:40.767798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18611 11:45:40.802568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18613 11:45:40.803189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18614 11:45:40.837377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18616 11:45:40.838049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18617 11:45:40.872789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18619 11:45:40.873415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18620 11:45:40.906846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18622 11:45:40.907464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18623 11:45:40.940886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18624 11:45:40.941353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18626 11:45:40.975946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18628 11:45:40.976601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18629 11:45:41.010179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18631 11:45:41.010803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18632 11:45:41.044830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18633 11:45:41.045320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18635 11:45:41.079907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18637 11:45:41.080550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18638 11:45:41.114891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18640 11:45:41.115348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18641 11:45:41.149516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18642 11:45:41.149947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18644 11:45:41.185147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18646 11:45:41.185602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18647 11:45:41.220625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18649 11:45:41.221080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18650 11:45:41.256916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18651 11:45:41.257328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18653 11:45:41.292954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18654 11:45:41.293369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18656 11:45:41.329282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18657 11:45:41.329689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18659 11:45:41.365336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18661 11:45:41.365954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18662 11:45:41.402154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18664 11:45:41.402606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18665 11:45:41.436871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18666 11:45:41.437311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18668 11:45:41.472524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18669 11:45:41.472988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18671 11:45:41.508143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18672 11:45:41.508623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18674 11:45:41.543444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18676 11:45:41.544023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18677 11:45:41.578867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18678 11:45:41.579342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18680 11:45:41.614993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18681 11:45:41.615485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18683 11:45:41.650089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18685 11:45:41.650671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18686 11:45:41.685346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18688 11:45:41.685918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18689 11:45:41.720682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18690 11:45:41.721173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18692 11:45:41.755514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18693 11:45:41.755998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18695 11:45:41.790880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18696 11:45:41.791378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18698 11:45:41.826677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18700 11:45:41.827299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18701 11:45:41.861273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18702 11:45:41.861773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18704 11:45:41.896875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18705 11:45:41.897361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18707 11:45:41.931760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18709 11:45:41.932403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18710 11:45:41.966820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18712 11:45:41.967381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18713 11:45:42.001855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18714 11:45:42.002332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18716 11:45:42.037253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18717 11:45:42.037671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18719 11:45:42.074228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18721 11:45:42.074678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18722 11:45:42.109359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18723 11:45:42.109786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18725 11:45:42.144211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18726 11:45:42.144685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18728 11:45:42.178793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18729 11:45:42.179249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18731 11:45:42.213554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18732 11:45:42.214037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18734 11:45:42.248452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18736 11:45:42.249026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18737 11:45:42.282483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18739 11:45:42.283061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18740 11:45:42.316947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18741 11:45:42.317410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18743 11:45:42.351181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18744 11:45:42.351657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18746 11:45:42.385878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18748 11:45:42.386453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18749 11:45:42.421075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18751 11:45:42.421521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18752 11:45:42.456577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18753 11:45:42.457064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18755 11:45:42.491170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18756 11:45:42.491624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18758 11:45:42.525675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18760 11:45:42.526137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18761 11:45:42.560455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18763 11:45:42.561018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18764 11:45:42.594540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18765 11:45:42.594973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18767 11:45:42.629287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18769 11:45:42.629928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18770 11:45:42.664272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18771 11:45:42.664748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18773 11:45:42.698707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18774 11:45:42.699188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18776 11:45:42.734387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18777 11:45:42.734874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18779 11:45:42.769153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18780 11:45:42.769633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18782 11:45:42.803618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18784 11:45:42.804244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18785 11:45:42.838060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18786 11:45:42.838540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18788 11:45:42.872670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18789 11:45:42.873135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18791 11:45:42.906828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18792 11:45:42.907314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18794 11:45:42.949467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18796 11:45:42.949942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18797 11:45:42.984694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18799 11:45:42.985173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18800 11:45:43.020210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18801 11:45:43.020658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18803 11:45:43.055089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18804 11:45:43.055473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18806 11:45:43.090821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18808 11:45:43.091277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18809 11:45:43.126432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18811 11:45:43.126882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18812 11:45:43.161898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18814 11:45:43.162343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18815 11:45:43.197478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18817 11:45:43.197951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18818 11:45:43.234102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18820 11:45:43.234554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18821 11:45:43.270176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18822 11:45:43.270631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18824 11:45:43.306678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18825 11:45:43.307158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18827 11:45:43.341896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18829 11:45:43.342506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18830 11:45:43.376300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18831 11:45:43.376728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18833 11:45:43.410926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18835 11:45:43.411399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18836 11:45:43.445942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18837 11:45:43.446440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18839 11:45:43.481060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18841 11:45:43.481517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18842 11:45:43.516817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18844 11:45:43.517382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18845 11:45:43.551795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18847 11:45:43.552401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18848 11:45:43.586860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18849 11:45:43.587360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18851 11:45:43.621263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18852 11:45:43.621708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18854 11:45:43.656379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18855 11:45:43.656861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18857 11:45:43.690710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18858 11:45:43.691185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18860 11:45:43.724837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18861 11:45:43.725311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18863 11:45:43.759976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18865 11:45:43.760451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18866 11:45:43.796120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18868 11:45:43.796594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18869 11:45:43.831043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18871 11:45:43.831502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18872 11:45:43.866534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18874 11:45:43.866984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18875 11:45:43.901996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18877 11:45:43.902444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18878 11:45:43.936922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18879 11:45:43.937340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18881 11:45:43.971877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18883 11:45:43.972329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18884 11:45:44.006169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18885 11:45:44.006610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18887 11:45:44.040720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18889 11:45:44.041170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18890 11:45:44.076742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18891 11:45:44.077159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18893 11:45:44.110913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18894 11:45:44.111336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18896 11:45:44.145255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18897 11:45:44.145677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18899 11:45:44.180977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18901 11:45:44.181432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18902 11:45:44.215686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18903 11:45:44.216107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18905 11:45:44.250222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18906 11:45:44.250642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18908 11:45:44.284468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18909 11:45:44.284901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18911 11:45:44.318336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18912 11:45:44.318776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18914 11:45:44.352496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18915 11:45:44.352978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18917 11:45:44.386437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18919 11:45:44.387007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18920 11:45:44.421111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18922 11:45:44.421589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18923 11:45:44.455625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18925 11:45:44.456101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18926 11:45:44.490571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18928 11:45:44.491150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18929 11:45:44.524947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18930 11:45:44.525396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18932 11:45:44.559258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18933 11:45:44.559613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18935 11:45:44.593810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18936 11:45:44.594235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18938 11:45:44.628449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18939 11:45:44.628871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18941 11:45:44.662894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18942 11:45:44.663310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18944 11:45:44.698020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18946 11:45:44.698494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18947 11:45:44.733151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18948 11:45:44.733573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
18950 11:45:44.767918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
18952 11:45:44.768399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
18953 11:45:44.804131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
18955 11:45:44.804708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
18956 11:45:44.839214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
18957 11:45:44.839660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
18959 11:45:44.874762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
18960 11:45:44.875235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
18962 11:45:44.910291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
18964 11:45:44.910857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
18965 11:45:44.945622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
18966 11:45:44.946087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
18968 11:45:44.981661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
18969 11:45:44.982086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
18971 11:45:45.017488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
18973 11:45:45.018044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
18974 11:45:45.053327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
18975 11:45:45.053786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
18977 11:45:45.088804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
18978 11:45:45.089255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
18980 11:45:45.125089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
18981 11:45:45.125537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
18983 11:45:45.160558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
18984 11:45:45.160971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
18986 11:45:45.196909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
18987 11:45:45.197327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
18989 11:45:45.232793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
18991 11:45:45.233255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
18992 11:45:45.267851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
18994 11:45:45.268311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
18995 11:45:45.303511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
18997 11:45:45.304155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
18998 11:45:45.336628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
19000 11:45:45.337095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
19001 11:45:45.368489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
19003 11:45:45.368909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
19004 11:45:45.400766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
19006 11:45:45.401228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
19007 11:45:45.433800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
19009 11:45:45.434445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
19010 11:45:45.467253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
19011 11:45:45.467741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
19013 11:45:45.498916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
19015 11:45:45.499545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
19016 11:45:45.530939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
19018 11:45:45.531571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
19019 11:45:45.564419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
19021 11:45:45.565047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
19022 11:45:45.598364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
19023 11:45:45.598828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
19025 11:45:45.634545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
19026 11:45:45.635008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
19028 11:45:45.666873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
19030 11:45:45.667391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
19031 11:45:45.698519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
19033 11:45:45.699020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
19034 11:45:45.732051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
19036 11:45:45.732649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
19037 11:45:45.765083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
19038 11:45:45.765524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
19040 11:45:45.797760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
19042 11:45:45.798290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
19043 11:45:45.831017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
19044 11:45:45.831435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
19046 11:45:45.863383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
19048 11:45:45.863898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
19049 11:45:45.895550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
19050 11:45:45.896031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
19052 11:45:45.928396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
19054 11:45:45.929026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
19055 11:45:45.961441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
19057 11:45:45.961917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
19058 11:45:45.993576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
19060 11:45:45.994038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
19061 11:45:46.025556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
19062 11:45:46.025976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
19064 11:45:46.059289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
19065 11:45:46.059734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
19067 11:45:46.092484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
19069 11:45:46.092970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
19070 11:45:46.123475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
19071 11:45:46.123895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
19073 11:45:46.155132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
19074 11:45:46.155542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
19076 11:45:46.187377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
19078 11:45:46.187910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
19079 11:45:46.220283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
19080 11:45:46.220702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
19082 11:45:46.255309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
19084 11:45:46.255775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
19085 11:45:46.288873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
19086 11:45:46.289285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
19088 11:45:46.323412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
19089 11:45:46.323832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
19091 11:45:46.358549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
19092 11:45:46.358972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
19094 11:45:46.390727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
19095 11:45:46.391147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
19097 11:45:46.422067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
19098 11:45:46.422477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
19100 11:45:46.454304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
19101 11:45:46.454711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
19103 11:45:46.487389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
19104 11:45:46.487846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
19106 11:45:46.519305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
19108 11:45:46.519855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
19109 11:45:46.550404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
19110 11:45:46.550836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
19112 11:45:46.583306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
19113 11:45:46.583744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
19115 11:45:46.616416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
19116 11:45:46.616887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
19118 11:45:46.648102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
19120 11:45:46.648678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
19121 11:45:46.679683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
19122 11:45:46.680135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
19124 11:45:46.712737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
19126 11:45:46.713273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
19127 11:45:46.744605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
19129 11:45:46.745245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
19130 11:45:46.776438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
19132 11:45:46.777032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
19133 11:45:46.807957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
19135 11:45:46.808499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
19136 11:45:46.840326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
19137 11:45:46.840773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
19139 11:45:46.872036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
19141 11:45:46.872628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
19142 11:45:46.904905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
19144 11:45:46.905478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
19145 11:45:46.936651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
19146 11:45:46.937093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
19148 11:45:46.967971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
19150 11:45:46.968493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
19151 11:45:47.000960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
19153 11:45:47.001464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
19154 11:45:47.033196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
19155 11:45:47.033590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
19157 11:45:47.066592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
19158 11:45:47.066967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
19160 11:45:47.098575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
19162 11:45:47.098985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
19163 11:45:47.130585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
19164 11:45:47.130965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
19166 11:45:47.162412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
19167 11:45:47.162830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
19169 11:45:47.194964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
19170 11:45:47.195327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
19172 11:45:47.227770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
19174 11:45:47.228216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
19175 11:45:47.259129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
19176 11:45:47.259573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
19178 11:45:47.292885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
19179 11:45:47.293371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
19181 11:45:47.326341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
19182 11:45:47.326782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
19184 11:45:47.358403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
19186 11:45:47.358770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
19187 11:45:47.390622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
19189 11:45:47.390974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
19190 11:45:47.422230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
19191 11:45:47.422556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
19193 11:45:47.453703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19195 11:45:47.454122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19196 11:45:47.485828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19197 11:45:47.486283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19199 11:45:47.518558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19201 11:45:47.519150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19202 11:45:47.551769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19204 11:45:47.552248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19205 11:45:47.583857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19207 11:45:47.584573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19208 11:45:47.617329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19210 11:45:47.617895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19211 11:45:47.650775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19212 11:45:47.651243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19214 11:45:47.682988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19216 11:45:47.683540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19217 11:45:47.717030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19218 11:45:47.717447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19220 11:45:47.749829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19222 11:45:47.750294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19223 11:45:47.784270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19224 11:45:47.784852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19226 11:45:47.818827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19228 11:45:47.819597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19229 11:45:47.852887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19231 11:45:47.853352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19232 11:45:47.887626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19233 11:45:47.888087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19235 11:45:47.920567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19236 11:45:47.921038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19238 11:45:47.953047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19239 11:45:47.953457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19241 11:45:47.986280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19242 11:45:47.986748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19244 11:45:48.019406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19245 11:45:48.019880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19247 11:45:48.074112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19249 11:45:48.074699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19250 11:45:48.106242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19251 11:45:48.106699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19253 11:45:48.140383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19255 11:45:48.140956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19256 11:45:48.173073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19258 11:45:48.173592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19259 11:45:48.206486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19260 11:45:48.206953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19262 11:45:48.239047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19264 11:45:48.239673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19265 11:45:48.271029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19266 11:45:48.271488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19268 11:45:48.303585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19269 11:45:48.304021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19271 11:45:48.335850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19273 11:45:48.336378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19274 11:45:48.369430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19275 11:45:48.369853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19277 11:45:48.401544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19279 11:45:48.402075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19280 11:45:48.433990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19281 11:45:48.434396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19283 11:45:48.466378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19284 11:45:48.466758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19286 11:45:48.499181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19287 11:45:48.499562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19289 11:45:48.531532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19290 11:45:48.531889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19292 11:45:48.563394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19293 11:45:48.563849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19295 11:45:48.596662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19296 11:45:48.597096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19298 11:45:48.630411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19299 11:45:48.630819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19301 11:45:48.662709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19302 11:45:48.663123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19304 11:45:48.695334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19306 11:45:48.695791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19307 11:45:48.727814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19309 11:45:48.728291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19310 11:45:48.760031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19312 11:45:48.760438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19313 11:45:48.793614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19315 11:45:48.794096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19316 11:45:48.831306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19318 11:45:48.831880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19319 11:45:48.869124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19320 11:45:48.869598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19322 11:45:48.901173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19323 11:45:48.901603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19325 11:45:48.932937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19327 11:45:48.933513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19328 11:45:48.964483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19329 11:45:48.964918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19331 11:45:48.996733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19333 11:45:48.997255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19334 11:45:49.027902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19336 11:45:49.028448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19337 11:45:49.061540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19339 11:45:49.061988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19340 11:45:49.094563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19341 11:45:49.094952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19343 11:45:49.126899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19345 11:45:49.127429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19346 11:45:49.159490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19348 11:45:49.159977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19349 11:45:49.192774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19350 11:45:49.193202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19352 11:45:49.225513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19354 11:45:49.226052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19355 11:45:49.257970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19357 11:45:49.258533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19358 11:45:49.292686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19359 11:45:49.293150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19361 11:45:49.325955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19363 11:45:49.326415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19364 11:45:49.358524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19365 11:45:49.358946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19367 11:45:49.390362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19368 11:45:49.390778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19370 11:45:49.423033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19371 11:45:49.423458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19373 11:45:49.455443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19374 11:45:49.455944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19376 11:45:49.487089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19377 11:45:49.487547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19379 11:45:49.519900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19381 11:45:49.520475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19382 11:45:49.553086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19384 11:45:49.553676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19385 11:45:49.585663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19387 11:45:49.586238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19388 11:45:49.620014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19390 11:45:49.620594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19391 11:45:49.652896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19393 11:45:49.653471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19394 11:45:49.686614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19395 11:45:49.687078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19397 11:45:49.720583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19398 11:45:49.721011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19400 11:45:49.755330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19401 11:45:49.755902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19403 11:45:49.789798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19404 11:45:49.790255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19406 11:45:49.823213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19408 11:45:49.823775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19409 11:45:49.854963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19411 11:45:49.855426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19412 11:45:49.887603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19413 11:45:49.888007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19415 11:45:49.919339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19416 11:45:49.919790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19418 11:45:49.950566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19420 11:45:49.951112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19421 11:45:49.984680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19422 11:45:49.985129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19424 11:45:50.017474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19425 11:45:50.017935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19427 11:45:50.050679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19429 11:45:50.051233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19430 11:45:50.082418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19431 11:45:50.082867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19433 11:45:50.114073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19435 11:45:50.114611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19436 11:45:50.146345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19438 11:45:50.146845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19439 11:45:50.178553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19440 11:45:50.179001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19442 11:45:50.210507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19443 11:45:50.210919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19445 11:45:50.243951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19447 11:45:50.244577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19448 11:45:50.276281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19450 11:45:50.276908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19451 11:45:50.309155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19453 11:45:50.309721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19454 11:45:50.343587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19455 11:45:50.344012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19457 11:45:50.375442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19459 11:45:50.376054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19460 11:45:50.409259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19462 11:45:50.409788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19463 11:45:50.444729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19464 11:45:50.445210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19466 11:45:50.477285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19467 11:45:50.477760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19469 11:45:50.510395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19470 11:45:50.510817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19472 11:45:50.541796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19473 11:45:50.542170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19475 11:45:50.573115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19476 11:45:50.573561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19478 11:45:50.606797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19479 11:45:50.607253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19481 11:45:50.642643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19482 11:45:50.643082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19484 11:45:50.674987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19485 11:45:50.675400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19487 11:45:50.707728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19489 11:45:50.708195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19490 11:45:50.740252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19491 11:45:50.740685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19493 11:45:50.773194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19495 11:45:50.773645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19496 11:45:50.805596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19497 11:45:50.806036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19499 11:45:50.837515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19500 11:45:50.837956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19502 11:45:50.870996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19504 11:45:50.871456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19505 11:45:50.903117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19506 11:45:50.903541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19508 11:45:50.934909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19509 11:45:50.935273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19511 11:45:50.966359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19513 11:45:50.966795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19514 11:45:50.998153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19515 11:45:50.998537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19517 11:45:51.029806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19518 11:45:51.030235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19520 11:45:51.063452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19522 11:45:51.063920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19523 11:45:51.097054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19524 11:45:51.097448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19526 11:45:51.130828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19527 11:45:51.131229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19529 11:45:51.162949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19531 11:45:51.163410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19532 11:45:51.198089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19533 11:45:51.198396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19535 11:45:51.229906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19537 11:45:51.230373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19538 11:45:51.264556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19539 11:45:51.264994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19541 11:45:51.296943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19542 11:45:51.297394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19544 11:45:51.330146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19545 11:45:51.330568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19547 11:45:51.361768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19548 11:45:51.362214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19550 11:45:51.394215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19551 11:45:51.394649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19553 11:45:51.429706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19555 11:45:51.430074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19556 11:45:51.466712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19557 11:45:51.467110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19559 11:45:51.498506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19560 11:45:51.498924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19562 11:45:51.530026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19563 11:45:51.530436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19565 11:45:51.561979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19566 11:45:51.562387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19568 11:45:51.595022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19570 11:45:51.595626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19571 11:45:51.626380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19572 11:45:51.626815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19574 11:45:51.657722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19575 11:45:51.658145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19577 11:45:51.690109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19579 11:45:51.690614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19580 11:45:51.721714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19582 11:45:51.722232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19583 11:45:51.753356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19584 11:45:51.753765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19586 11:45:51.784773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19587 11:45:51.785150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19589 11:45:51.816582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19590 11:45:51.816971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19592 11:45:51.848646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19593 11:45:51.849078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19595 11:45:51.881701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19596 11:45:51.882083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19598 11:45:51.913140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19600 11:45:51.913536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19601 11:45:51.943929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19603 11:45:51.944469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19604 11:45:51.976468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19606 11:45:51.977055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19607 11:45:52.007590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19608 11:45:52.008002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19610 11:45:52.041030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19611 11:45:52.041471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19613 11:45:52.072719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19614 11:45:52.073168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19616 11:45:52.104922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19618 11:45:52.105497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19619 11:45:52.137717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19620 11:45:52.138164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19622 11:45:52.169239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19624 11:45:52.169806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19625 11:45:52.203918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19627 11:45:52.204373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19628 11:45:52.235471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19629 11:45:52.235939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19631 11:45:52.267142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19633 11:45:52.267605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19634 11:45:52.300812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19635 11:45:52.301311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19637 11:45:52.333823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19639 11:45:52.334396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19640 11:45:52.367488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19642 11:45:52.367948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19643 11:45:52.399562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19645 11:45:52.400144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19646 11:45:52.432012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19648 11:45:52.432462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19649 11:45:52.465212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19651 11:45:52.465678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19652 11:45:52.497171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19654 11:45:52.497740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19655 11:45:52.529750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19656 11:45:52.530210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19658 11:45:52.562361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19659 11:45:52.562829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19661 11:45:52.594214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19662 11:45:52.594683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19664 11:45:52.626699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19666 11:45:52.627179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19667 11:45:52.658995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19669 11:45:52.659551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19670 11:45:52.690917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19672 11:45:52.691376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19673 11:45:52.730005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19674 11:45:52.730416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19676 11:45:52.761217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19677 11:45:52.761629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19679 11:45:52.793101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19680 11:45:52.793563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19682 11:45:52.826214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19683 11:45:52.826646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19685 11:45:52.857395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19686 11:45:52.857830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19688 11:45:52.891038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19689 11:45:52.891460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19691 11:45:52.922376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19693 11:45:52.922999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19694 11:45:52.954321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19695 11:45:52.954775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19697 11:45:52.986779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19698 11:45:52.987198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19700 11:45:53.017838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19702 11:45:53.018340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19703 11:45:53.050626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19704 11:45:53.051037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19706 11:45:53.081780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19708 11:45:53.082319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19709 11:45:53.113452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19710 11:45:53.113870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19712 11:45:53.146548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19713 11:45:53.146993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19715 11:45:53.197427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19716 11:45:53.197915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19718 11:45:53.229860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19719 11:45:53.230291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19721 11:45:53.261578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19723 11:45:53.262107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19724 11:45:53.292742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19726 11:45:53.293242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19727 11:45:53.324812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19728 11:45:53.325214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19730 11:45:53.356575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19731 11:45:53.357054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19733 11:45:53.388768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19734 11:45:53.389180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19736 11:45:53.421065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19737 11:45:53.421546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19739 11:45:53.453831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19741 11:45:53.454383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19742 11:45:53.485446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19743 11:45:53.485859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19745 11:45:53.518148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19746 11:45:53.518564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19748 11:45:53.549712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19750 11:45:53.550164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19751 11:45:53.581207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19753 11:45:53.581666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19754 11:45:53.613810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19755 11:45:53.614225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19757 11:45:53.645851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19759 11:45:53.646316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19760 11:45:53.677550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19762 11:45:53.678011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19763 11:45:53.708762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19764 11:45:53.709168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19766 11:45:53.740973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19767 11:45:53.741394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19769 11:45:53.772790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19771 11:45:53.773247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19772 11:45:53.805094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19773 11:45:53.805526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19775 11:45:53.836426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19776 11:45:53.836852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19778 11:45:53.867848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19780 11:45:53.868295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19781 11:45:53.900325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19782 11:45:53.900760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19784 11:45:53.933186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19785 11:45:53.933617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19787 11:45:53.965461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19788 11:45:53.965895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19790 11:45:53.996643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19791 11:45:53.997093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19793 11:45:54.028829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19794 11:45:54.029248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19796 11:45:54.060816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19797 11:45:54.061289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19799 11:45:54.093506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19800 11:45:54.093966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19802 11:45:54.125391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19803 11:45:54.125794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19805 11:45:54.157515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19807 11:45:54.157976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19808 11:45:54.190493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19809 11:45:54.190910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19811 11:45:54.223015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19813 11:45:54.223476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19814 11:45:54.254869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19815 11:45:54.255334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19817 11:45:54.286922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19818 11:45:54.287392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19820 11:45:54.319021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19821 11:45:54.319501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19823 11:45:54.350171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19824 11:45:54.350587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19826 11:45:54.388931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19828 11:45:54.389588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19829 11:45:54.425939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19830 11:45:54.426431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19832 11:45:54.462970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19833 11:45:54.463429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19835 11:45:54.499523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19836 11:45:54.499959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19838 11:45:54.536912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19840 11:45:54.537459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19841 11:45:54.573158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19842 11:45:54.573644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19844 11:45:54.609948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19845 11:45:54.610425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19847 11:45:54.646536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19849 11:45:54.647179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19850 11:45:54.682549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19851 11:45:54.683022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19853 11:45:54.717843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19855 11:45:54.718435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19856 11:45:54.754429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19858 11:45:54.754974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19859 11:45:54.790771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19860 11:45:54.791194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19862 11:45:54.826638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19863 11:45:54.827057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19865 11:45:54.862898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19866 11:45:54.863315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19868 11:45:54.899084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19869 11:45:54.899539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19871 11:45:54.935558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19872 11:45:54.935948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19874 11:45:54.972553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19875 11:45:54.972948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19877 11:45:55.009847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19878 11:45:55.010334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19880 11:45:55.047898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19882 11:45:55.048379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19883 11:45:55.084899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19885 11:45:55.085535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19886 11:45:55.121559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19887 11:45:55.122039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19889 11:45:55.158183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19891 11:45:55.158819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19892 11:45:55.194280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19894 11:45:55.194907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19895 11:45:55.230421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19897 11:45:55.231050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19898 11:45:55.266345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19899 11:45:55.266762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19901 11:45:55.302512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19902 11:45:55.302911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19904 11:45:55.339700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19906 11:45:55.340167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19907 11:45:55.376642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19909 11:45:55.377101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19910 11:45:55.413534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19911 11:45:55.414040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19913 11:45:55.450250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19915 11:45:55.450763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19916 11:45:55.486206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19918 11:45:55.486711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19919 11:45:55.522387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19921 11:45:55.522984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19922 11:45:55.558426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19923 11:45:55.558897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19925 11:45:55.595580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19926 11:45:55.596146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19928 11:45:55.633391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19929 11:45:55.633920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19931 11:45:55.669850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19932 11:45:55.670341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19934 11:45:55.707169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19935 11:45:55.707648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19937 11:45:55.745415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19939 11:45:55.745901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19940 11:45:55.782937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19941 11:45:55.783377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19943 11:45:55.820767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19944 11:45:55.821256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19946 11:45:55.858977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19947 11:45:55.859472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
19949 11:45:55.897016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
19950 11:45:55.897475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
19952 11:45:55.934604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
19954 11:45:55.935073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
19955 11:45:55.972655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
19956 11:45:55.973138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
19958 11:45:56.010406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
19960 11:45:56.010868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
19961 11:45:56.043409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
19962 11:45:56.043854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
19964 11:45:56.076437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
19965 11:45:56.077018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
19967 11:45:56.109242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
19968 11:45:56.109695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
19970 11:45:56.142621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
19971 11:45:56.143047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
19973 11:45:56.175317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
19974 11:45:56.175901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
19976 11:45:56.208611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
19977 11:45:56.209250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
19979 11:45:56.242319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
19981 11:45:56.242916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
19982 11:45:56.277466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
19983 11:45:56.278047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
19985 11:45:56.309973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
19986 11:45:56.310353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
19988 11:45:56.342989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
19990 11:45:56.343471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
19991 11:45:56.375553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
19993 11:45:56.376110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
19994 11:45:56.408542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
19995 11:45:56.408995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
19997 11:45:56.441080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
19998 11:45:56.441427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
20000 11:45:56.473855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
20002 11:45:56.474144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
20003 11:45:56.506507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
20004 11:45:56.506915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
20006 11:45:56.539021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
20007 11:45:56.539429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
20009 11:45:56.572108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
20011 11:45:56.572743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
20012 11:45:56.605058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
20013 11:45:56.605531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
20015 11:45:56.637709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
20016 11:45:56.638118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
20018 11:45:56.670783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
20020 11:45:56.671236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
20021 11:45:56.703431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
20023 11:45:56.703898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
20024 11:45:56.736301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
20025 11:45:56.736730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
20027 11:45:56.768461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
20029 11:45:56.768905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
20030 11:45:56.799887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
20032 11:45:56.800349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
20033 11:45:56.831606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
20034 11:45:56.832040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
20036 11:45:56.863074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
20037 11:45:56.863544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
20039 11:45:56.894535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
20040 11:45:56.894983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
20042 11:45:56.926791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
20043 11:45:56.927246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
20045 11:45:56.958103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
20046 11:45:56.958551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
20048 11:45:56.989712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
20050 11:45:56.990166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
20051 11:45:57.021905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
20053 11:45:57.022358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
20054 11:45:57.053986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
20055 11:45:57.054443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
20057 11:45:57.086319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
20058 11:45:57.086737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
20060 11:45:57.117629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
20061 11:45:57.118039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
20063 11:45:57.149942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
20064 11:45:57.150351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
20066 11:45:57.181788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
20068 11:45:57.182238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
20069 11:45:57.213763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
20071 11:45:57.214211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
20072 11:45:57.246303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
20073 11:45:57.246727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
20075 11:45:57.278150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
20077 11:45:57.278777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
20078 11:45:57.310143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
20079 11:45:57.310623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
20081 11:45:57.341802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
20082 11:45:57.342223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
20084 11:45:57.372848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
20086 11:45:57.373324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
20087 11:45:57.404931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
20089 11:45:57.405402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
20090 11:45:57.436742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
20091 11:45:57.437115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
20093 11:45:57.468802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
20094 11:45:57.469193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
20096 11:45:57.501241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
20097 11:45:57.501612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
20099 11:45:57.533552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
20100 11:45:57.533931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
20102 11:45:57.565710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
20104 11:45:57.566151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
20105 11:45:57.598365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
20107 11:45:57.598929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
20108 11:45:57.629848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
20109 11:45:57.630311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
20111 11:45:57.662206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
20112 11:45:57.662642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
20114 11:45:57.693784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
20115 11:45:57.694201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
20117 11:45:57.726635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
20118 11:45:57.727048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
20120 11:45:57.759528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
20122 11:45:57.760160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
20123 11:45:57.792233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
20125 11:45:57.792708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
20126 11:45:57.823618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
20128 11:45:57.824044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
20129 11:45:57.855960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
20131 11:45:57.856365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
20132 11:45:57.887572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
20134 11:45:57.888012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
20135 11:45:57.919187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
20136 11:45:57.919673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
20138 11:45:57.951344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
20139 11:45:57.951751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
20141 11:45:57.982868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
20143 11:45:57.983303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
20144 11:45:58.014270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
20145 11:45:58.014697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
20147 11:45:58.045990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
20148 11:45:58.046415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
20150 11:45:58.077675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
20151 11:45:58.078082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
20153 11:45:58.109695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
20154 11:45:58.110122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
20156 11:45:58.141306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
20157 11:45:58.141679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
20159 11:45:58.173469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
20161 11:45:58.173908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
20162 11:45:58.205200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
20164 11:45:58.205638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
20165 11:45:58.237257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
20166 11:45:58.237639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
20168 11:45:58.278756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
20169 11:45:58.279151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
20171 11:45:58.333211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
20172 11:45:58.333698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
20174 11:45:58.365961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
20175 11:45:58.366455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
20177 11:45:58.399131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
20178 11:45:58.399615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
20180 11:45:58.433014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
20182 11:45:58.433487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
20183 11:45:58.465405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
20184 11:45:58.465886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
20186 11:45:58.499130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
20187 11:45:58.499660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
20189 11:45:58.532950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
20190 11:45:58.533434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
20192 11:45:58.574004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
20193 11:45:58.574491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20195 11:45:58.608059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20197 11:45:58.608688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20198 11:45:58.640797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20199 11:45:58.641268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20201 11:45:58.673398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20202 11:45:58.673880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20204 11:45:58.705423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20205 11:45:58.705926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20207 11:45:58.738766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20209 11:45:58.739413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20210 11:45:58.772042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20212 11:45:58.772490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20213 11:45:58.804921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20214 11:45:58.805331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20216 11:45:58.838212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20218 11:45:58.838682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20219 11:45:58.870894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20220 11:45:58.871318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20222 11:45:58.903026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20223 11:45:58.903449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20225 11:45:58.935987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20227 11:45:58.936448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20228 11:45:58.968428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20229 11:45:58.968862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20231 11:45:59.001208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20233 11:45:59.001695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20234 11:45:59.034742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20236 11:45:59.035309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20237 11:45:59.067630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20239 11:45:59.068201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20240 11:45:59.099461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20241 11:45:59.099942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20243 11:45:59.132141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20245 11:45:59.132708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20246 11:45:59.165432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20247 11:45:59.165943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20249 11:45:59.197909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20250 11:45:59.198368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20252 11:45:59.229917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20254 11:45:59.230466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20255 11:45:59.261292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20256 11:45:59.261778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20258 11:45:59.293838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20259 11:45:59.294305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20261 11:45:59.325476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20262 11:45:59.325908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20264 11:45:59.357037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20265 11:45:59.357482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20267 11:45:59.389506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20268 11:45:59.389934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20270 11:45:59.421561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20271 11:45:59.421993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20273 11:45:59.453638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20275 11:45:59.454113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20276 11:45:59.484973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20277 11:45:59.485409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20279 11:45:59.516806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20280 11:45:59.517238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20282 11:45:59.548332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20283 11:45:59.548771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20285 11:45:59.580506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20287 11:45:59.580979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20288 11:45:59.621104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20289 11:45:59.621546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20291 11:45:59.652719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20292 11:45:59.653171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20294 11:45:59.684745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20295 11:45:59.685190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20297 11:45:59.716953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20299 11:45:59.717410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20300 11:45:59.749031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20301 11:45:59.749516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20303 11:45:59.781450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20305 11:45:59.782143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20306 11:45:59.813861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20307 11:45:59.814344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20309 11:45:59.846579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20310 11:45:59.847054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20312 11:45:59.878407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20313 11:45:59.878847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20315 11:45:59.910645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20317 11:45:59.911108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20318 11:45:59.942062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20319 11:45:59.942487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20321 11:45:59.974818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20323 11:45:59.975281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20324 11:46:00.007132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20325 11:46:00.007576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20327 11:46:00.040637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20328 11:46:00.041081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20330 11:46:00.073729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20331 11:46:00.074219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20333 11:46:00.105895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20335 11:46:00.106465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20336 11:46:00.137704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20338 11:46:00.138251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20339 11:46:00.169778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20341 11:46:00.170326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20342 11:46:00.201727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20344 11:46:00.202287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20345 11:46:00.234914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20347 11:46:00.235466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20348 11:46:00.266066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20349 11:46:00.266482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20351 11:46:00.298517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20353 11:46:00.299078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20354 11:46:00.330514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20356 11:46:00.331066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20357 11:46:00.362707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20359 11:46:00.363151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20360 11:46:00.395549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20361 11:46:00.396025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20363 11:46:00.427304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20364 11:46:00.427773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20366 11:46:00.459533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20367 11:46:00.460006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20369 11:46:00.491977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20371 11:46:00.492534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20372 11:46:00.524378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20373 11:46:00.524828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20375 11:46:00.557178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20376 11:46:00.557632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20378 11:46:00.591299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20380 11:46:00.591873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20381 11:46:00.624620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20383 11:46:00.625198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20384 11:46:00.656891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20385 11:46:00.657337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20387 11:46:00.688808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20388 11:46:00.689227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20390 11:46:00.720959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20392 11:46:00.721598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20393 11:46:00.753335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20395 11:46:00.753989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20396 11:46:00.785557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20398 11:46:00.786254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20399 11:46:00.818303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20400 11:46:00.818767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20402 11:46:00.850075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20403 11:46:00.850570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20405 11:46:00.884057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20407 11:46:00.884525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20408 11:46:00.919266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20409 11:46:00.919716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20411 11:46:00.952368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20412 11:46:00.952811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20414 11:46:00.983852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20416 11:46:00.984463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20417 11:46:01.016463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20418 11:46:01.016927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20420 11:46:01.048770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20421 11:46:01.049244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20423 11:46:01.083531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20424 11:46:01.083930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20426 11:46:01.120535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20428 11:46:01.120998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20429 11:46:01.152401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20430 11:46:01.152881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20432 11:46:01.183653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20433 11:46:01.184077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20435 11:46:01.215323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20436 11:46:01.215760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20438 11:46:01.248149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20440 11:46:01.248861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20441 11:46:01.283415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20442 11:46:01.283960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20444 11:46:01.315450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20446 11:46:01.315825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20447 11:46:01.348326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20448 11:46:01.348817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20450 11:46:01.380545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20452 11:46:01.381336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20453 11:46:01.411928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20455 11:46:01.412417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20456 11:46:01.445189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20457 11:46:01.445545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20459 11:46:01.480720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20460 11:46:01.481063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20462 11:46:01.513666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20464 11:46:01.513946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20465 11:46:01.546017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20467 11:46:01.546252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20468 11:46:01.577806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20469 11:46:01.578097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20471 11:46:01.610575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20473 11:46:01.610895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20474 11:46:01.642962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20476 11:46:01.643287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20477 11:46:01.674874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20478 11:46:01.675219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20480 11:46:01.707331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20481 11:46:01.707686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20483 11:46:01.739021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20485 11:46:01.739573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20486 11:46:01.771237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20487 11:46:01.771641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20489 11:46:01.803203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20490 11:46:01.803596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20492 11:46:01.835888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20494 11:46:01.836343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20495 11:46:01.867906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20497 11:46:01.868353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20498 11:46:01.900788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20499 11:46:01.901156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20501 11:46:01.932686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20502 11:46:01.933047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20504 11:46:01.965440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20505 11:46:01.965853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20507 11:46:01.997080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20508 11:46:01.997488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20510 11:46:02.028893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20511 11:46:02.029297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20513 11:46:02.060828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20514 11:46:02.061232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20516 11:46:02.092711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20518 11:46:02.093142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20519 11:46:02.124585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20520 11:46:02.125007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20522 11:46:02.157278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20523 11:46:02.157678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20525 11:46:02.189045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20526 11:46:02.189449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20528 11:46:02.220998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20530 11:46:02.221636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20531 11:46:02.252546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20532 11:46:02.253019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20534 11:46:02.285097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20535 11:46:02.285510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20537 11:46:02.317676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20538 11:46:02.318088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20540 11:46:02.349305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20542 11:46:02.349760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20543 11:46:02.381953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20544 11:46:02.382367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20546 11:46:02.413781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20547 11:46:02.414178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20549 11:46:02.445266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20551 11:46:02.445699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20552 11:46:02.477011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20553 11:46:02.477482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20555 11:46:02.508948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20557 11:46:02.509398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20558 11:46:02.540947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20559 11:46:02.541356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20561 11:46:02.572697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20562 11:46:02.573107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20564 11:46:02.605356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20566 11:46:02.605821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20567 11:46:02.637915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20568 11:46:02.638319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20570 11:46:02.669710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20571 11:46:02.670127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20573 11:46:02.701679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20574 11:46:02.702160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20576 11:46:02.733930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20577 11:46:02.734412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20579 11:46:02.765887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20581 11:46:02.766502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20582 11:46:02.797534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20583 11:46:02.798008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20585 11:46:02.829092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20586 11:46:02.829522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20588 11:46:02.860833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20590 11:46:02.861296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20591 11:46:02.893095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20592 11:46:02.893575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20594 11:46:02.924726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20595 11:46:02.925164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20597 11:46:02.957063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20599 11:46:02.957590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20600 11:46:02.989446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20602 11:46:02.989909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20603 11:46:03.021211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20605 11:46:03.021869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20606 11:46:03.052779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20608 11:46:03.053344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20609 11:46:03.084445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20610 11:46:03.084830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20612 11:46:03.116251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20613 11:46:03.116634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20615 11:46:03.147794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20616 11:46:03.148221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20618 11:46:03.180636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20620 11:46:03.181089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20621 11:46:03.212870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20622 11:46:03.213342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20624 11:46:03.244537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20625 11:46:03.245010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20627 11:46:03.276444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20628 11:46:03.276926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20630 11:46:03.308948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20632 11:46:03.309580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20633 11:46:03.341634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20634 11:46:03.342109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20636 11:46:03.377347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20637 11:46:03.377948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20639 11:46:03.430188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20640 11:46:03.430629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20642 11:46:03.461510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20643 11:46:03.462009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20645 11:46:03.493460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20647 11:46:03.494061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20648 11:46:03.524899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20649 11:46:03.525387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20651 11:46:03.556752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20652 11:46:03.557172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20654 11:46:03.589101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20655 11:46:03.589500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20657 11:46:03.620896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20658 11:46:03.621319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20660 11:46:03.653194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20661 11:46:03.653602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20663 11:46:03.685528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20665 11:46:03.685961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20666 11:46:03.717527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20667 11:46:03.717902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20669 11:46:03.749147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20671 11:46:03.749558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20672 11:46:03.781508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20674 11:46:03.781920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20675 11:46:03.812319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20676 11:46:03.812673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20678 11:46:03.843377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20679 11:46:03.843843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20681 11:46:03.874832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20682 11:46:03.875250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20684 11:46:03.906366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20685 11:46:03.906801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20687 11:46:03.937958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20689 11:46:03.938421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20690 11:46:03.969235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20692 11:46:03.969703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20693 11:46:04.000932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20695 11:46:04.001408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20696 11:46:04.032699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20697 11:46:04.033142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20699 11:46:04.064872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20700 11:46:04.065295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20702 11:46:04.096617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20703 11:46:04.097039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20705 11:46:04.128703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20706 11:46:04.129123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20708 11:46:04.160457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20709 11:46:04.160900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20711 11:46:04.192750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20712 11:46:04.193257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20714 11:46:04.225533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20715 11:46:04.226032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20717 11:46:04.257131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20719 11:46:04.257870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20720 11:46:04.289729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20721 11:46:04.290210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20723 11:46:04.321509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20724 11:46:04.321982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20726 11:46:04.353855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20727 11:46:04.354314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20729 11:46:04.385982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20730 11:46:04.386408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20732 11:46:04.417759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20733 11:46:04.418218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20735 11:46:04.450635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20736 11:46:04.451095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20738 11:46:04.482861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20739 11:46:04.483286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20741 11:46:04.514187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20743 11:46:04.514604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20744 11:46:04.545548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20746 11:46:04.545962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20747 11:46:04.577238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20748 11:46:04.577602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20750 11:46:04.608944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20752 11:46:04.609355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20753 11:46:04.640942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20755 11:46:04.641478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20756 11:46:04.672761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20758 11:46:04.673268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20759 11:46:04.704654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20760 11:46:04.705113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20762 11:46:04.736786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20764 11:46:04.737297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20765 11:46:04.768516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20767 11:46:04.769024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20768 11:46:04.800800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20770 11:46:04.801302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20771 11:46:04.832100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20773 11:46:04.832593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20774 11:46:04.863612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20775 11:46:04.864032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20777 11:46:04.895167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20778 11:46:04.895581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20780 11:46:04.926628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20782 11:46:04.927206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20783 11:46:04.958118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20785 11:46:04.958616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20786 11:46:04.989878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20788 11:46:04.990381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20789 11:46:05.021266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20791 11:46:05.021808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20792 11:46:05.053267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20794 11:46:05.053722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20795 11:46:05.085417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20796 11:46:05.085815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20798 11:46:05.117000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20800 11:46:05.117519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20801 11:46:05.148813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20803 11:46:05.149308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20804 11:46:05.180711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20806 11:46:05.181194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20807 11:46:05.212622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20809 11:46:05.213214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20810 11:46:05.244588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20811 11:46:05.245045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20813 11:46:05.276531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20815 11:46:05.277111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20816 11:46:05.307863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20818 11:46:05.308495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20819 11:46:05.339391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20821 11:46:05.339999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20822 11:46:05.370878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20823 11:46:05.371313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20825 11:46:05.406158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20826 11:46:05.406682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20828 11:46:05.448742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20830 11:46:05.449370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20831 11:46:05.480805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20833 11:46:05.481211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20834 11:46:05.512723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20835 11:46:05.513088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20837 11:46:05.544865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20838 11:46:05.545335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20840 11:46:05.576849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20842 11:46:05.577394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20843 11:46:05.609010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20844 11:46:05.609465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20846 11:46:05.640739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20847 11:46:05.641188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20849 11:46:05.672963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20851 11:46:05.673509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20852 11:46:05.705007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20854 11:46:05.705550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20855 11:46:05.736990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20856 11:46:05.737400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20858 11:46:05.768903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20859 11:46:05.769304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20861 11:46:05.800961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20862 11:46:05.801358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20864 11:46:05.833517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20866 11:46:05.833978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20867 11:46:05.865245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20869 11:46:05.865813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20870 11:46:05.897272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20872 11:46:05.897877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20873 11:46:05.929105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20875 11:46:05.929616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20876 11:46:05.960705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20878 11:46:05.961110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20879 11:46:05.992177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20881 11:46:05.992641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20882 11:46:06.025435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20883 11:46:06.025813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20885 11:46:06.057602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20886 11:46:06.057979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20888 11:46:06.089458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20890 11:46:06.089865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20891 11:46:06.121062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20893 11:46:06.121480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20894 11:46:06.152271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20895 11:46:06.152644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20897 11:46:06.184314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20899 11:46:06.184841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20900 11:46:06.216068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20902 11:46:06.216571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20903 11:46:06.248495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20904 11:46:06.248922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20906 11:46:06.283577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20907 11:46:06.284057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20909 11:46:06.317062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20910 11:46:06.317489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20912 11:46:06.350456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20914 11:46:06.350992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20915 11:46:06.384069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20917 11:46:06.384701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20918 11:46:06.421781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20919 11:46:06.422278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20921 11:46:06.458541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20922 11:46:06.458954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20924 11:46:06.494199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20926 11:46:06.494640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20927 11:46:06.529918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20928 11:46:06.530336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20930 11:46:06.565928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20931 11:46:06.566346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20933 11:46:06.601500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20935 11:46:06.601955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20936 11:46:06.637447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20938 11:46:06.637916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20939 11:46:06.673204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20941 11:46:06.673786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20942 11:46:06.709025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20943 11:46:06.709379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20945 11:46:06.745002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20946 11:46:06.745374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20948 11:46:06.780799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
20949 11:46:06.781169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
20951 11:46:06.816815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
20952 11:46:06.817179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
20954 11:46:06.852883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
20956 11:46:06.853335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
20957 11:46:06.888828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
20958 11:46:06.889198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
20960 11:46:06.925337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
20962 11:46:06.925851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
20963 11:46:06.961080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
20964 11:46:06.961454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
20966 11:46:06.997187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
20967 11:46:06.997552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
20969 11:46:07.033001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
20970 11:46:07.033368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
20972 11:46:07.068692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
20974 11:46:07.069162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
20975 11:46:07.104538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
20976 11:46:07.104933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
20978 11:46:07.140061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
20980 11:46:07.140752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
20981 11:46:07.176379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
20982 11:46:07.176838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
20984 11:46:07.213079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
20986 11:46:07.213542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
20987 11:46:07.249000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
20988 11:46:07.249419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
20990 11:46:07.286124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
20991 11:46:07.286659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
20993 11:46:07.323026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
20994 11:46:07.323451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
20996 11:46:07.357612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
20997 11:46:07.358105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
20999 11:46:07.391554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
21000 11:46:07.392031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
21002 11:46:07.426653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
21003 11:46:07.427067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
21005 11:46:07.461002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
21006 11:46:07.461416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
21008 11:46:07.494775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
21009 11:46:07.495217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
21011 11:46:07.539176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
21013 11:46:07.539638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
21014 11:46:07.575187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
21016 11:46:07.575649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
21017 11:46:07.613360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
21018 11:46:07.613789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
21020 11:46:07.651015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
21021 11:46:07.651474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
21023 11:46:07.694444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
21025 11:46:07.695096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
21026 11:46:07.733606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
21028 11:46:07.734061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
21029 11:46:07.774614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
21030 11:46:07.775042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
21032 11:46:07.781754 <47>[ 194.889581] systemd-journald[105]: Sent WATCHDOG=1 notification.
21033 11:46:07.824950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
21034 11:46:07.825455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
21036 11:46:07.862624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
21037 11:46:07.863071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
21039 11:46:07.899632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
21040 11:46:07.900056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
21042 11:46:07.935369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
21043 11:46:07.935859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
21045 11:46:07.969069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
21046 11:46:07.969540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
21048 11:46:08.001109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
21049 11:46:08.001523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
21051 11:46:08.033244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
21053 11:46:08.033720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
21054 11:46:08.066640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
21056 11:46:08.067215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
21057 11:46:08.098655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
21058 11:46:08.099133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
21060 11:46:08.130554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
21062 11:46:08.131120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
21063 11:46:08.162910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
21064 11:46:08.163700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
21066 11:46:08.197017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
21068 11:46:08.197588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
21069 11:46:08.231155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
21070 11:46:08.231612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
21072 11:46:08.263508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
21073 11:46:08.263973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
21075 11:46:08.296791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
21076 11:46:08.297259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
21078 11:46:08.329078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
21080 11:46:08.329668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
21081 11:46:08.360947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
21082 11:46:08.361426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
21084 11:46:08.393012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
21085 11:46:08.393474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
21087 11:46:08.427348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
21088 11:46:08.427822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
21090 11:46:08.460863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
21091 11:46:08.461321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
21093 11:46:08.492690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
21094 11:46:08.493139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
21096 11:46:08.548845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
21097 11:46:08.549279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
21099 11:46:08.580652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
21100 11:46:08.581079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
21102 11:46:08.612724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
21104 11:46:08.613182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
21105 11:46:08.645340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
21106 11:46:08.645841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
21108 11:46:08.676484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
21110 11:46:08.677060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
21111 11:46:08.707284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
21112 11:46:08.707728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
21114 11:46:08.739454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
21116 11:46:08.740064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
21117 11:46:08.770740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
21118 11:46:08.771208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
21120 11:46:08.802587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
21121 11:46:08.803074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
21123 11:46:08.834458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
21125 11:46:08.835045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
21126 11:46:08.866017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
21127 11:46:08.866488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
21129 11:46:08.897465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
21131 11:46:08.897930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
21132 11:46:08.928851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
21134 11:46:08.929324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
21135 11:46:08.960522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
21136 11:46:08.961021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
21138 11:46:08.997905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
21139 11:46:08.998437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
21141 11:46:09.033502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
21142 11:46:09.034035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
21144 11:46:09.070907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
21145 11:46:09.071376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
21147 11:46:09.108964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
21149 11:46:09.109402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
21150 11:46:09.145040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
21152 11:46:09.145484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
21153 11:46:09.179681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
21154 11:46:09.180205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
21156 11:46:09.218562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
21157 11:46:09.219030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
21159 11:46:09.254547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
21160 11:46:09.255017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
21162 11:46:09.305630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
21163 11:46:09.306028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
21165 11:46:09.346491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
21167 11:46:09.346952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
21168 11:46:09.385680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
21169 11:46:09.386079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
21171 11:46:09.421395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
21172 11:46:09.421860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
21174 11:46:09.456940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
21175 11:46:09.457349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
21177 11:46:09.495300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
21179 11:46:09.495916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
21180 11:46:09.531549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
21181 11:46:09.532013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
21183 11:46:09.566993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
21185 11:46:09.567438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
21186 11:46:09.609451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
21188 11:46:09.609886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
21189 11:46:09.647534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
21190 11:46:09.647939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
21192 11:46:09.685246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21194 11:46:09.685682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
21195 11:46:09.724904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21196 11:46:09.725363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21198 11:46:09.760945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21199 11:46:09.761355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21201 11:46:09.796493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21202 11:46:09.797021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21204 11:46:09.834550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21205 11:46:09.834929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21207 11:46:09.872764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21208 11:46:09.873198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21210 11:46:09.913545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21211 11:46:09.914001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21213 11:46:09.946633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21214 11:46:09.947176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21216 11:46:09.982420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21217 11:46:09.982930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21219 11:46:10.020731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21221 11:46:10.021333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21222 11:46:10.059404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21223 11:46:10.059787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21225 11:46:10.096509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21226 11:46:10.096911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21228 11:46:10.136834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21229 11:46:10.137253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21231 11:46:10.174529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21232 11:46:10.174975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21234 11:46:10.213684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21235 11:46:10.214148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21237 11:46:10.261457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21238 11:46:10.261946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21240 11:46:10.307608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21241 11:46:10.308097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21243 11:46:10.346480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21244 11:46:10.346953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21246 11:46:10.385100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21247 11:46:10.385579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21249 11:46:10.426235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21250 11:46:10.426769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21252 11:46:10.469156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21254 11:46:10.469563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21255 11:46:10.507682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21257 11:46:10.508154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21258 11:46:10.544783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21259 11:46:10.545174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21261 11:46:10.582047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21263 11:46:10.582616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21264 11:46:10.619685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21265 11:46:10.620164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21267 11:46:10.657956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21268 11:46:10.658328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21270 11:46:10.705635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21272 11:46:10.706102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21273 11:46:10.761436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21275 11:46:10.761959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21276 11:46:10.818794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21277 11:46:10.819262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21279 11:46:10.878050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21281 11:46:10.878608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21282 11:46:10.935978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21284 11:46:10.936438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21285 11:46:10.987232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21287 11:46:10.987803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21288 11:46:11.025719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21290 11:46:11.026381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21291 11:46:11.078853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21292 11:46:11.079402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21294 11:46:11.132553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21295 11:46:11.133575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21297 11:46:11.183547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21299 11:46:11.183989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21300 11:46:11.237692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21301 11:46:11.238079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21303 11:46:11.282258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21304 11:46:11.282623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21306 11:46:11.326692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21307 11:46:11.327256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21309 11:46:11.364527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21310 11:46:11.364977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21312 11:46:11.402456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21313 11:46:11.402897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21315 11:46:11.438222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21316 11:46:11.438650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21318 11:46:11.473383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21319 11:46:11.473826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21321 11:46:11.507615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21322 11:46:11.508060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21324 11:46:11.543457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21326 11:46:11.543898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21327 11:46:11.577247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21328 11:46:11.577645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21330 11:46:11.611413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21331 11:46:11.611895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21333 11:46:11.644503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21334 11:46:11.644987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21336 11:46:11.678404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21337 11:46:11.678894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21339 11:46:11.712383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21340 11:46:11.712850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21342 11:46:11.746174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21343 11:46:11.746602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21345 11:46:11.780448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21346 11:46:11.780892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21348 11:46:11.814368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21349 11:46:11.814796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21351 11:46:11.848610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21352 11:46:11.849022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21354 11:46:11.882928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21356 11:46:11.883398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21357 11:46:11.917084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21359 11:46:11.917540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21360 11:46:11.950866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21361 11:46:11.951353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21363 11:46:11.985448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21365 11:46:11.986078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21366 11:46:12.019423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21368 11:46:12.020008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21369 11:46:12.054374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21370 11:46:12.054832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21372 11:46:12.089023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21374 11:46:12.089473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21375 11:46:12.124753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21376 11:46:12.125119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21378 11:46:12.161900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21379 11:46:12.162259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21381 11:46:12.198266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21383 11:46:12.198718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21384 11:46:12.233032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21386 11:46:12.233476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21387 11:46:12.268950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21388 11:46:12.269350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21390 11:46:12.303055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21391 11:46:12.303398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21393 11:46:12.338135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21395 11:46:12.338572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21396 11:46:12.372831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21398 11:46:12.373402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21399 11:46:12.406537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21400 11:46:12.406965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21402 11:46:12.441773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21403 11:46:12.442204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21405 11:46:12.475564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21407 11:46:12.476091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21408 11:46:12.509744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21409 11:46:12.510274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21411 11:46:12.543997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21413 11:46:12.544675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21414 11:46:12.578103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21416 11:46:12.578720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21417 11:46:12.611884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21419 11:46:12.612374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21420 11:46:12.646141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21421 11:46:12.646627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21423 11:46:12.679480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21425 11:46:12.680170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21426 11:46:12.712866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21427 11:46:12.713396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21429 11:46:12.746164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21430 11:46:12.746668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21432 11:46:12.779497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21434 11:46:12.780172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21435 11:46:12.812978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21436 11:46:12.813479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21438 11:46:12.846323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21439 11:46:12.846786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21441 11:46:12.880451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21442 11:46:12.880926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21444 11:46:12.913739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21445 11:46:12.914206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21447 11:46:12.947329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21448 11:46:12.947795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21450 11:46:12.981000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21452 11:46:12.981482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21453 11:46:13.013984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21454 11:46:13.014446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21456 11:46:13.046220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21457 11:46:13.046772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21459 11:46:13.077935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21460 11:46:13.078439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21462 11:46:13.108904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21463 11:46:13.109338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21465 11:46:13.140996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21466 11:46:13.141428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21468 11:46:13.172606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21469 11:46:13.173019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21471 11:46:13.203926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21473 11:46:13.204415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21474 11:46:13.235659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21475 11:46:13.236118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21477 11:46:13.267571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21478 11:46:13.268053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21480 11:46:13.301141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21481 11:46:13.301582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21483 11:46:13.333216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21484 11:46:13.333653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21486 11:46:13.364275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21487 11:46:13.364706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21489 11:46:13.395098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21491 11:46:13.395642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21492 11:46:13.426079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21493 11:46:13.426531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21495 11:46:13.457681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21496 11:46:13.458154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21498 11:46:13.490166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21499 11:46:13.490622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21501 11:46:13.523271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21502 11:46:13.523716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21504 11:46:13.555032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21506 11:46:13.555512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21507 11:46:13.591164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21508 11:46:13.591633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21510 11:46:13.626629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21511 11:46:13.627185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21513 11:46:13.691555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21514 11:46:13.692053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21516 11:46:13.728467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21517 11:46:13.728921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21519 11:46:13.763690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21521 11:46:13.764453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21522 11:46:13.796502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21523 11:46:13.796919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21525 11:46:13.827615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21526 11:46:13.828003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21528 11:46:13.858937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21529 11:46:13.859358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21531 11:46:13.890049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21533 11:46:13.890416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21534 11:46:13.921166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21535 11:46:13.921659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21537 11:46:13.953288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21539 11:46:13.953781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21540 11:46:13.984663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21541 11:46:13.985080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21543 11:46:14.015695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21544 11:46:14.016115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21546 11:46:14.047346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21547 11:46:14.047823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21549 11:46:14.078982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21550 11:46:14.079396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21552 11:46:14.110324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21554 11:46:14.110949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21555 11:46:14.142169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21557 11:46:14.142617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21558 11:46:14.174246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21559 11:46:14.174647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21561 11:46:14.206764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21562 11:46:14.207194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21564 11:46:14.238914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21566 11:46:14.239362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21567 11:46:14.270916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21568 11:46:14.271322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21570 11:46:14.302782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21571 11:46:14.303225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21573 11:46:14.333705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21574 11:46:14.334161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21576 11:46:14.365233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21578 11:46:14.365791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21579 11:46:14.397369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21580 11:46:14.397862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21582 11:46:14.434708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21583 11:46:14.435135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21585 11:46:14.466466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21586 11:46:14.466933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21588 11:46:14.499172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21590 11:46:14.499743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21591 11:46:14.530600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21592 11:46:14.531093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21594 11:46:14.562972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21596 11:46:14.563593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21597 11:46:14.594955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21598 11:46:14.595412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21600 11:46:14.626713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21601 11:46:14.627142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21603 11:46:14.658922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21605 11:46:14.659400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21606 11:46:14.692927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21607 11:46:14.693347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21609 11:46:14.725047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21610 11:46:14.725471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21612 11:46:14.757111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21613 11:46:14.757529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21615 11:46:14.788501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21616 11:46:14.788968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21618 11:46:14.819673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21619 11:46:14.820149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21621 11:46:14.851229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21622 11:46:14.851708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21624 11:46:14.882789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21625 11:46:14.883214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21627 11:46:14.914660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21628 11:46:14.915122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21630 11:46:14.946051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21631 11:46:14.946513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21633 11:46:14.977740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21634 11:46:14.978209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21636 11:46:15.009268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21637 11:46:15.009707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21639 11:46:15.042370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21640 11:46:15.042786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21642 11:46:15.075391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21644 11:46:15.075993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21645 11:46:15.109086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21647 11:46:15.109705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21648 11:46:15.142637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21649 11:46:15.143058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21651 11:46:15.176619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21652 11:46:15.177038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21654 11:46:15.210233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21655 11:46:15.210660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21657 11:46:15.245372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21658 11:46:15.245804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21660 11:46:15.279455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21661 11:46:15.279882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21663 11:46:15.314050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21664 11:46:15.314527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21666 11:46:15.348485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21667 11:46:15.348906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21669 11:46:15.382629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21671 11:46:15.383103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21672 11:46:15.415358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21674 11:46:15.415919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21675 11:46:15.448895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21677 11:46:15.449449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21678 11:46:15.481232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21679 11:46:15.481658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21681 11:46:15.513368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21683 11:46:15.513853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21684 11:46:15.545486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21685 11:46:15.545969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21687 11:46:15.577865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21688 11:46:15.578339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21690 11:46:15.610995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21691 11:46:15.611417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21693 11:46:15.643112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21695 11:46:15.643574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21696 11:46:15.675164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21697 11:46:15.675587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21699 11:46:15.707806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21701 11:46:15.708451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21702 11:46:15.741416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21703 11:46:15.741905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21705 11:46:15.773862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21707 11:46:15.774429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21708 11:46:15.806034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21709 11:46:15.806458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21711 11:46:15.837980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21713 11:46:15.838613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21714 11:46:15.870350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21715 11:46:15.870826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21717 11:46:15.902446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21719 11:46:15.902919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21720 11:46:15.934009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21721 11:46:15.934460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21723 11:46:15.966209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21725 11:46:15.966897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21726 11:46:15.998163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21728 11:46:15.998807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21729 11:46:16.030741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21730 11:46:16.031172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21732 11:46:16.062864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21733 11:46:16.063241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21735 11:46:16.094949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21736 11:46:16.095392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21738 11:46:16.127333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21739 11:46:16.127761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21741 11:46:16.159296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21742 11:46:16.159720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21744 11:46:16.191623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21745 11:46:16.192048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21747 11:46:16.224096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21749 11:46:16.224565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21750 11:46:16.256992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21752 11:46:16.257455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21753 11:46:16.289899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21754 11:46:16.290316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21756 11:46:16.323015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21757 11:46:16.323464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21759 11:46:16.355914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21761 11:46:16.356389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21762 11:46:16.391044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21763 11:46:16.391458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21765 11:46:16.427676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21766 11:46:16.428095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21768 11:46:16.463586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21770 11:46:16.464042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21771 11:46:16.499226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21772 11:46:16.499588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21774 11:46:16.534992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21775 11:46:16.535416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21777 11:46:16.569936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21779 11:46:16.570352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21780 11:46:16.605304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21781 11:46:16.605680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21783 11:46:16.641195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21784 11:46:16.641578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21786 11:46:16.677068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21788 11:46:16.677666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21789 11:46:16.711777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21791 11:46:16.712382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21792 11:46:16.746902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21794 11:46:16.747476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21795 11:46:16.781796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21796 11:46:16.782194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21798 11:46:16.817725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21799 11:46:16.818202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21801 11:46:16.853451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21803 11:46:16.854001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21804 11:46:16.889048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21805 11:46:16.889450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21807 11:46:16.924523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21808 11:46:16.924941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21810 11:46:16.959414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21811 11:46:16.959817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21813 11:46:16.994984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21814 11:46:16.995377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21816 11:46:17.030492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21817 11:46:17.030918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21819 11:46:17.065944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21820 11:46:17.066365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21822 11:46:17.101314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21823 11:46:17.101741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21825 11:46:17.137380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21826 11:46:17.137798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21828 11:46:17.173064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21829 11:46:17.173523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21831 11:46:17.208983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21832 11:46:17.209378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21834 11:46:17.245050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21835 11:46:17.245446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21837 11:46:17.281134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21838 11:46:17.281580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21840 11:46:17.316374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21841 11:46:17.316832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21843 11:46:17.351031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21845 11:46:17.351492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21846 11:46:17.385840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21847 11:46:17.386256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21849 11:46:17.421184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21850 11:46:17.421616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21852 11:46:17.458237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21853 11:46:17.458655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21855 11:46:17.493818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21856 11:46:17.494254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21858 11:46:17.529133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21860 11:46:17.529594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21861 11:46:17.565019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21862 11:46:17.565455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21864 11:46:17.600882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21866 11:46:17.601338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21867 11:46:17.637038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21868 11:46:17.637539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21870 11:46:17.672608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21871 11:46:17.673035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21873 11:46:17.707689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21875 11:46:17.708212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21876 11:46:17.742675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21878 11:46:17.743311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21879 11:46:17.777299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21880 11:46:17.777687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21882 11:46:17.813797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21883 11:46:17.814223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21885 11:46:17.849168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21886 11:46:17.849589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21888 11:46:17.884398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21890 11:46:17.884812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21891 11:46:17.919087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21892 11:46:17.919454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21894 11:46:17.953901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21895 11:46:17.954274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21897 11:46:17.989089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21898 11:46:17.989483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21900 11:46:18.024930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21901 11:46:18.025348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21903 11:46:18.060345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21904 11:46:18.060721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21906 11:46:18.094719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21907 11:46:18.095104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21909 11:46:18.129405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21910 11:46:18.129831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21912 11:46:18.164645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21914 11:46:18.165156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21915 11:46:18.199594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21916 11:46:18.200033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21918 11:46:18.235110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21920 11:46:18.235680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21921 11:46:18.270815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21923 11:46:18.271510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21924 11:46:18.305833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21926 11:46:18.306399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21927 11:46:18.341189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21929 11:46:18.341959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21930 11:46:18.377949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21931 11:46:18.378430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21933 11:46:18.413402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21934 11:46:18.413841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21936 11:46:18.449206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21937 11:46:18.449658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21939 11:46:18.484572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21940 11:46:18.485016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21942 11:46:18.519706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21943 11:46:18.520162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21945 11:46:18.555168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21947 11:46:18.555637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21948 11:46:18.589914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
21949 11:46:18.590395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
21951 11:46:18.624931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
21952 11:46:18.625382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
21954 11:46:18.660495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
21955 11:46:18.660946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
21957 11:46:18.695444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
21958 11:46:18.695890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
21960 11:46:18.732039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
21962 11:46:18.732717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
21963 11:46:18.788462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
21964 11:46:18.788955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
21966 11:46:18.824033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
21968 11:46:18.824738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
21969 11:46:18.859323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
21970 11:46:18.859799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
21972 11:46:18.895326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
21973 11:46:18.895801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
21975 11:46:18.931134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
21976 11:46:18.931585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
21978 11:46:18.967692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
21979 11:46:18.968174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
21981 11:46:19.003012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
21982 11:46:19.003472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
21984 11:46:19.038860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
21985 11:46:19.039301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
21987 11:46:19.074380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
21989 11:46:19.074921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
21990 11:46:19.109572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
21991 11:46:19.110026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
21993 11:46:19.145165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
21995 11:46:19.145638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
21996 11:46:19.181341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
21997 11:46:19.181769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
21999 11:46:19.217453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
22000 11:46:19.217855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
22002 11:46:19.253123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
22003 11:46:19.253568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
22005 11:46:19.289095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
22006 11:46:19.289565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
22008 11:46:19.324868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
22009 11:46:19.325346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
22011 11:46:19.360371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
22012 11:46:19.360837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
22014 11:46:19.395979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
22016 11:46:19.396580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
22017 11:46:19.432285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
22018 11:46:19.432727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
22020 11:46:19.467318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
22022 11:46:19.467792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
22023 11:46:19.502321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
22025 11:46:19.502963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
22026 11:46:19.537254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
22027 11:46:19.537723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
22029 11:46:19.572558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
22031 11:46:19.573193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
22032 11:46:19.607432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
22034 11:46:19.608065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
22035 11:46:19.642516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
22036 11:46:19.642988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
22038 11:46:19.677563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
22040 11:46:19.678049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
22041 11:46:19.713325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
22043 11:46:19.713779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
22044 11:46:19.748375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
22045 11:46:19.748784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
22047 11:46:19.783348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
22048 11:46:19.783745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
22050 11:46:19.819194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
22051 11:46:19.819582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
22053 11:46:19.854749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
22055 11:46:19.855204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
22056 11:46:19.889104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
22058 11:46:19.889543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
22059 11:46:19.924455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
22060 11:46:19.924826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
22062 11:46:19.958764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
22063 11:46:19.959223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
22065 11:46:19.993342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
22067 11:46:19.993993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
22068 11:46:20.028068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
22070 11:46:20.028644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
22071 11:46:20.062589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
22072 11:46:20.063013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
22074 11:46:20.097486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
22075 11:46:20.097913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
22077 11:46:20.132501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
22078 11:46:20.132978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
22080 11:46:20.167004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
22082 11:46:20.167462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
22083 11:46:20.201889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
22085 11:46:20.202340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
22086 11:46:20.237058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
22087 11:46:20.237619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
22089 11:46:20.271860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
22091 11:46:20.272521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
22092 11:46:20.306975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
22094 11:46:20.307619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
22095 11:46:20.341475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
22096 11:46:20.341905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
22098 11:46:20.376720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
22099 11:46:20.377144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
22101 11:46:20.412351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
22103 11:46:20.412916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
22104 11:46:20.447095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
22105 11:46:20.447533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
22107 11:46:20.481964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
22108 11:46:20.482423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
22110 11:46:20.517028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
22111 11:46:20.517549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
22113 11:46:20.553193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
22114 11:46:20.553663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
22116 11:46:20.588693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
22117 11:46:20.589115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
22119 11:46:20.624561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
22121 11:46:20.624999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
22122 11:46:20.659871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
22124 11:46:20.660307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
22125 11:46:20.694310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
22126 11:46:20.694768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
22128 11:46:20.729351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
22129 11:46:20.729747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
22131 11:46:20.765105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
22132 11:46:20.765518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
22134 11:46:20.800273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
22136 11:46:20.800720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
22137 11:46:20.836075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
22139 11:46:20.836633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
22140 11:46:20.870266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
22141 11:46:20.870682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
22143 11:46:20.904866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
22144 11:46:20.905283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
22146 11:46:20.939501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
22147 11:46:20.940005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
22149 11:46:20.974710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
22150 11:46:20.975190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
22152 11:46:21.009479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
22153 11:46:21.009908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
22155 11:46:21.045355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
22156 11:46:21.045759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
22158 11:46:21.079985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
22160 11:46:21.080460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
22161 11:46:21.114799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
22162 11:46:21.115189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
22164 11:46:21.149480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
22165 11:46:21.149860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
22167 11:46:21.184852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
22168 11:46:21.185284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
22170 11:46:21.220689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
22171 11:46:21.221117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
22173 11:46:21.255266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
22175 11:46:21.255725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
22176 11:46:21.290429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
22177 11:46:21.290914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
22179 11:46:21.325905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
22180 11:46:21.326373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
22182 11:46:21.361370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
22183 11:46:21.361822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
22185 11:46:21.395939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
22187 11:46:21.396492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
22188 11:46:21.432715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
22189 11:46:21.433140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
22191 11:46:21.468939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22192 11:46:21.469335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
22194 11:46:21.504054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22196 11:46:21.504666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22197 11:46:21.539433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22198 11:46:21.539867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22200 11:46:21.574399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22201 11:46:21.574836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22203 11:46:21.609390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22204 11:46:21.609830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22206 11:46:21.645272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22208 11:46:21.645830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22209 11:46:21.681117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22211 11:46:21.681717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22212 11:46:21.715657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22214 11:46:21.716232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22215 11:46:21.750590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22216 11:46:21.751037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22218 11:46:21.785488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22220 11:46:21.786055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22221 11:46:21.820858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22223 11:46:21.821412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22224 11:46:21.855614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22225 11:46:21.856069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22227 11:46:21.890606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22228 11:46:21.891066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22230 11:46:21.925253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22231 11:46:21.925797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22233 11:46:21.960601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22235 11:46:21.961272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22236 11:46:21.995058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22237 11:46:21.995499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22239 11:46:22.029259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22240 11:46:22.029771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22242 11:46:22.064021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22244 11:46:22.064744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22245 11:46:22.098441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22246 11:46:22.098865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22248 11:46:22.132931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22249 11:46:22.133376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22251 11:46:22.168669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22252 11:46:22.169100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22254 11:46:22.203317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22255 11:46:22.203784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22257 11:46:22.237782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22258 11:46:22.238205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22260 11:46:22.272533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22262 11:46:22.272994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22263 11:46:22.306700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22264 11:46:22.307149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22266 11:46:22.344104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22268 11:46:22.344564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22269 11:46:22.379152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22270 11:46:22.379543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22272 11:46:22.413965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22273 11:46:22.414383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22275 11:46:22.449033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22276 11:46:22.449450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22278 11:46:22.483944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22280 11:46:22.484533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22281 11:46:22.519384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22282 11:46:22.519807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22284 11:46:22.554019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22285 11:46:22.554445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22287 11:46:22.589504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22288 11:46:22.589957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22290 11:46:22.624932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22291 11:46:22.625376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22293 11:46:22.660314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22295 11:46:22.660867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22296 11:46:22.694353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22298 11:46:22.694896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22299 11:46:22.728968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22300 11:46:22.729419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22302 11:46:22.764283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22303 11:46:22.764714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22305 11:46:22.799402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22306 11:46:22.799859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22308 11:46:22.834454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22309 11:46:22.834878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22311 11:46:22.870283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22312 11:46:22.870732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22314 11:46:22.904856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22315 11:46:22.905307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22317 11:46:22.939253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22319 11:46:22.939797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22320 11:46:22.974721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22322 11:46:22.975176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22323 11:46:23.010341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22324 11:46:23.010758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22326 11:46:23.046020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22327 11:46:23.046433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22329 11:46:23.082307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22330 11:46:23.082765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22332 11:46:23.117713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22333 11:46:23.118137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22335 11:46:23.153008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22336 11:46:23.153431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22338 11:46:23.187505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22339 11:46:23.187959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22341 11:46:23.222162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22342 11:46:23.222610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22344 11:46:23.257342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22345 11:46:23.257804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22347 11:46:23.293192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22348 11:46:23.293681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22350 11:46:23.328459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22352 11:46:23.328923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22353 11:46:23.362789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22354 11:46:23.363232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22356 11:46:23.398375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22358 11:46:23.398844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22359 11:46:23.433712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22360 11:46:23.434121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22362 11:46:23.470299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22364 11:46:23.470754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22365 11:46:23.505686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22367 11:46:23.506140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22368 11:46:23.541324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22369 11:46:23.541791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22371 11:46:23.577050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22373 11:46:23.577488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22374 11:46:23.612629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22375 11:46:23.613008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22377 11:46:23.648463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22378 11:46:23.648844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22380 11:46:23.684442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22382 11:46:23.684863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22383 11:46:23.719948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22385 11:46:23.720401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22386 11:46:23.754894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22387 11:46:23.755368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22389 11:46:23.789711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22390 11:46:23.790165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22392 11:46:23.824451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22393 11:46:23.824842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22395 11:46:23.859055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22397 11:46:23.859662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22398 11:46:23.914970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22399 11:46:23.915454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22401 11:46:23.950224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22402 11:46:23.950719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22404 11:46:23.986375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22406 11:46:23.986981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22407 11:46:24.021036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22408 11:46:24.021473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22410 11:46:24.055658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22411 11:46:24.056083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22413 11:46:24.092984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22414 11:46:24.093424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22416 11:46:24.128761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22417 11:46:24.129218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22419 11:46:24.164408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22420 11:46:24.164840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22422 11:46:24.200293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22423 11:46:24.200724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22425 11:46:24.235954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22427 11:46:24.236635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22428 11:46:24.271460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22430 11:46:24.272035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22431 11:46:24.306584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22432 11:46:24.307029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22434 11:46:24.342013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22435 11:46:24.342446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22437 11:46:24.377174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22438 11:46:24.377637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22440 11:46:24.412791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22441 11:46:24.413227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22443 11:46:24.449000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22444 11:46:24.449440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22446 11:46:24.484499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22447 11:46:24.484948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22449 11:46:24.520021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22451 11:46:24.520659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22452 11:46:24.555171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22453 11:46:24.555604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22455 11:46:24.590695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22456 11:46:24.591143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22458 11:46:24.626984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22459 11:46:24.627369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22461 11:46:24.662192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22462 11:46:24.662667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22464 11:46:24.697745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22465 11:46:24.698241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22467 11:46:24.733362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22468 11:46:24.733817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22470 11:46:24.768854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22471 11:46:24.769302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22473 11:46:24.804553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22474 11:46:24.804949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22476 11:46:24.840583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22477 11:46:24.841037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22479 11:46:24.875671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22480 11:46:24.876120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22482 11:46:24.910422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22484 11:46:24.911027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22485 11:46:24.945036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22487 11:46:24.945595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22488 11:46:24.979995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22490 11:46:24.980518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22491 11:46:25.014229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22492 11:46:25.014648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22494 11:46:25.049071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22495 11:46:25.049453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22497 11:46:25.085146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22499 11:46:25.085721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22500 11:46:25.120080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22502 11:46:25.120683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22503 11:46:25.155192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22504 11:46:25.155645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22506 11:46:25.189899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22507 11:46:25.190352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22509 11:46:25.224781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22510 11:46:25.225232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22512 11:46:25.259943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22514 11:46:25.260518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22515 11:46:25.296806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22516 11:46:25.297273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22518 11:46:25.331458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22519 11:46:25.331908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22521 11:46:25.366637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22522 11:46:25.367078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22524 11:46:25.401450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22526 11:46:25.402001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22527 11:46:25.436081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22529 11:46:25.436647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22530 11:46:25.470368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22531 11:46:25.470816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22533 11:46:25.505088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22534 11:46:25.505470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22536 11:46:25.539630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22537 11:46:25.540053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22539 11:46:25.574866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22540 11:46:25.575248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22542 11:46:25.609399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22544 11:46:25.609819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22545 11:46:25.644464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22546 11:46:25.644832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22548 11:46:25.679382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22549 11:46:25.679769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22551 11:46:25.717583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22552 11:46:25.718064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22554 11:46:25.754033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22555 11:46:25.754455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22557 11:46:25.789553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22559 11:46:25.790111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22560 11:46:25.825325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22562 11:46:25.825872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22563 11:46:25.861268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22565 11:46:25.861706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22566 11:46:25.897169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22567 11:46:25.897574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22569 11:46:25.932047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22571 11:46:25.932495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22572 11:46:25.967079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22573 11:46:25.967466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22575 11:46:26.002085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22576 11:46:26.002592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22578 11:46:26.037968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22580 11:46:26.038448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22581 11:46:26.073330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22583 11:46:26.073812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22584 11:46:26.109368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22585 11:46:26.109790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22587 11:46:26.145787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22588 11:46:26.146194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22590 11:46:26.181540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22592 11:46:26.182015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22593 11:46:26.217619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22594 11:46:26.218006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22596 11:46:26.252645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22597 11:46:26.253100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22599 11:46:26.287413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22600 11:46:26.287859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22602 11:46:26.322167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22603 11:46:26.322574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22605 11:46:26.357717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22606 11:46:26.358129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22608 11:46:26.393094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22610 11:46:26.393669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22611 11:46:26.428494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22612 11:46:26.429060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22614 11:46:26.464080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22616 11:46:26.464537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22617 11:46:26.499316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22619 11:46:26.499888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22620 11:46:26.534508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22621 11:46:26.534966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22623 11:46:26.569904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22624 11:46:26.570285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22626 11:46:26.604883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22628 11:46:26.605215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22629 11:46:26.640408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22631 11:46:26.640950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22632 11:46:26.675940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22634 11:46:26.676412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22635 11:46:26.712411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22636 11:46:26.712830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22638 11:46:26.747314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22639 11:46:26.747734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22641 11:46:26.783225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22643 11:46:26.783861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22644 11:46:26.817999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22645 11:46:26.818411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22647 11:46:26.853301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22648 11:46:26.853777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22650 11:46:26.888979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22651 11:46:26.889453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22653 11:46:26.923660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22654 11:46:26.924121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22656 11:46:26.959110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22657 11:46:26.959524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22659 11:46:26.994800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22660 11:46:26.995213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22662 11:46:27.029849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22663 11:46:27.030307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22665 11:46:27.064583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22667 11:46:27.065147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22668 11:46:27.098797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22670 11:46:27.099350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22671 11:46:27.133461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22672 11:46:27.133947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22674 11:46:27.169303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22675 11:46:27.169760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22677 11:46:27.203700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22679 11:46:27.204229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22680 11:46:27.238512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22681 11:46:27.238947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22683 11:46:27.273428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22684 11:46:27.273868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22686 11:46:27.307952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22688 11:46:27.308575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22689 11:46:27.342864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22690 11:46:27.343311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22692 11:46:27.377691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22694 11:46:27.378112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22695 11:46:27.413257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22697 11:46:27.413874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22698 11:46:27.447968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22700 11:46:27.448580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22701 11:46:27.482817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22703 11:46:27.483372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22704 11:46:27.517273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22705 11:46:27.517684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22707 11:46:27.552734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22709 11:46:27.553205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22710 11:46:27.589700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22712 11:46:27.590165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22713 11:46:27.628669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22715 11:46:27.629137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22716 11:46:27.670131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22717 11:46:27.670575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22719 11:46:27.712908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22721 11:46:27.713376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22722 11:46:27.754239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22723 11:46:27.754658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22725 11:46:27.790728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22727 11:46:27.791191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22728 11:46:27.826579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22729 11:46:27.826997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22731 11:46:27.862585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22733 11:46:27.863168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22734 11:46:27.897725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22736 11:46:27.898298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22737 11:46:27.932504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22738 11:46:27.932934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22740 11:46:27.968026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22742 11:46:27.968653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22743 11:46:28.004516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22744 11:46:28.004937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22746 11:46:28.041272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22747 11:46:28.041692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22749 11:46:28.078623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22750 11:46:28.079101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22752 11:46:28.114804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22753 11:46:28.115285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22755 11:46:28.150214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22756 11:46:28.150669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22758 11:46:28.185294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22759 11:46:28.185690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22761 11:46:28.220644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22763 11:46:28.221210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22764 11:46:28.257579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22765 11:46:28.258063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22767 11:46:28.293417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22768 11:46:28.293886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22770 11:46:28.329427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22771 11:46:28.329912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22773 11:46:28.364773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22775 11:46:28.365237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22776 11:46:28.400354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22777 11:46:28.400774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22779 11:46:28.438284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22781 11:46:28.438765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22782 11:46:28.486261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22784 11:46:28.486834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22785 11:46:28.521965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22786 11:46:28.522399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22788 11:46:28.556758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22790 11:46:28.557299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22791 11:46:28.591568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22792 11:46:28.592006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22794 11:46:28.626745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22795 11:46:28.627166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22797 11:46:28.661522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22798 11:46:28.661953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22800 11:46:28.696568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22801 11:46:28.696999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22803 11:46:28.731522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22804 11:46:28.731983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22806 11:46:28.766625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22807 11:46:28.767063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22809 11:46:28.802190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22810 11:46:28.802642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22812 11:46:28.837370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22814 11:46:28.837920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22815 11:46:28.872157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22817 11:46:28.872692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22818 11:46:28.907315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22820 11:46:28.907876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22821 11:46:28.942187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22822 11:46:28.942631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22824 11:46:28.978112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22825 11:46:28.978579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22827 11:46:29.034503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22829 11:46:29.035037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22830 11:46:29.069254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22831 11:46:29.069693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22833 11:46:29.103864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22835 11:46:29.104304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22836 11:46:29.138498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22837 11:46:29.138955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22839 11:46:29.175242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22841 11:46:29.175802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22842 11:46:29.211708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22844 11:46:29.212294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22845 11:46:29.246328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22847 11:46:29.246868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22848 11:46:29.281347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22850 11:46:29.281790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22851 11:46:29.316657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22852 11:46:29.317128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22854 11:46:29.352301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22855 11:46:29.352763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22857 11:46:29.386783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22859 11:46:29.387346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22860 11:46:29.421521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22861 11:46:29.421940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22863 11:46:29.457045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22865 11:46:29.457499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22866 11:46:29.492512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22867 11:46:29.492926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22869 11:46:29.527221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22871 11:46:29.527672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22872 11:46:29.563815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22874 11:46:29.564285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22875 11:46:29.599270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22877 11:46:29.599726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22878 11:46:29.634005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22879 11:46:29.634434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22881 11:46:29.669440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22882 11:46:29.669884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22884 11:46:29.704722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22886 11:46:29.705175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22887 11:46:29.739469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22888 11:46:29.739905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22890 11:46:29.774128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22891 11:46:29.774551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22893 11:46:29.810510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22895 11:46:29.811149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22896 11:46:29.845398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22897 11:46:29.845751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22899 11:46:29.881103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22900 11:46:29.881449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22902 11:46:29.915953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22904 11:46:29.916299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22905 11:46:29.952112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22907 11:46:29.952488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22908 11:46:29.987562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22909 11:46:29.987934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22911 11:46:30.022386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22912 11:46:30.022745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22914 11:46:30.057326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22915 11:46:30.057674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22917 11:46:30.091977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22919 11:46:30.092370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22920 11:46:30.127022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22921 11:46:30.127378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22923 11:46:30.162916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22924 11:46:30.163331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22926 11:46:30.198391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22927 11:46:30.198845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22929 11:46:30.234406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22931 11:46:30.235001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22932 11:46:30.269830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22933 11:46:30.270263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22935 11:46:30.305059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22936 11:46:30.305500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22938 11:46:30.341046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22939 11:46:30.341489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22941 11:46:30.377802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22942 11:46:30.378229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22944 11:46:30.411421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22945 11:46:30.411856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22947 11:46:30.447116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22948 11:46:30.447545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
22950 11:46:30.482256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
22951 11:46:30.482675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
22953 11:46:30.517289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
22954 11:46:30.517685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
22956 11:46:30.552611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
22957 11:46:30.553031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
22959 11:46:30.587999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
22961 11:46:30.588458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
22962 11:46:30.622881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
22963 11:46:30.623315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
22965 11:46:30.657696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
22966 11:46:30.658147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
22968 11:46:30.692861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
22969 11:46:30.693302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
22971 11:46:30.727658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
22973 11:46:30.728300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
22974 11:46:30.762310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
22975 11:46:30.762786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
22977 11:46:30.797628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
22978 11:46:30.798079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
22980 11:46:30.832478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
22981 11:46:30.832952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
22983 11:46:30.866839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
22985 11:46:30.867412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
22986 11:46:30.901246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
22987 11:46:30.901701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
22989 11:46:30.936761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
22991 11:46:30.937416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
22992 11:46:30.971818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
22994 11:46:30.972386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
22995 11:46:31.007184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
22996 11:46:31.007701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
22998 11:46:31.042883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
23000 11:46:31.043447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
23001 11:46:31.078538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
23002 11:46:31.079014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
23004 11:46:31.114052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
23006 11:46:31.114517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
23007 11:46:31.149158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
23008 11:46:31.149626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
23010 11:46:31.185186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
23011 11:46:31.185574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
23013 11:46:31.220777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
23014 11:46:31.221125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
23016 11:46:31.256401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
23017 11:46:31.256788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
23019 11:46:31.292886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
23020 11:46:31.293341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
23022 11:46:31.327347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
23023 11:46:31.327788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
23025 11:46:31.362647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
23027 11:46:31.363256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
23028 11:46:31.397428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
23029 11:46:31.397911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
23031 11:46:31.434253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
23033 11:46:31.434807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
23034 11:46:31.470254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
23035 11:46:31.470705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
23037 11:46:31.505640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
23039 11:46:31.506043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
23040 11:46:31.541217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
23041 11:46:31.541571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
23043 11:46:31.576629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
23044 11:46:31.577074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
23046 11:46:31.611031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
23047 11:46:31.611473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
23049 11:46:31.645411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
23050 11:46:31.645859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
23052 11:46:31.680655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
23053 11:46:31.681088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
23055 11:46:31.715277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
23056 11:46:31.715720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
23058 11:46:31.750253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
23059 11:46:31.750689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
23061 11:46:31.784993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
23062 11:46:31.785410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
23064 11:46:31.821124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
23065 11:46:31.821560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
23067 11:46:31.856665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
23069 11:46:31.857277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
23070 11:46:31.892087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
23072 11:46:31.892738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
23073 11:46:31.928816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
23074 11:46:31.929273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
23076 11:46:31.963222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
23077 11:46:31.963669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
23079 11:46:31.997958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
23080 11:46:31.998344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
23082 11:46:32.033024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
23083 11:46:32.033411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
23085 11:46:32.067635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
23086 11:46:32.068080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
23088 11:46:32.102158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
23089 11:46:32.102583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
23091 11:46:32.137115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
23092 11:46:32.137529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
23094 11:46:32.172153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
23096 11:46:32.172734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
23097 11:46:32.207035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
23098 11:46:32.207465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
23100 11:46:32.242202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
23101 11:46:32.242639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
23103 11:46:32.277373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
23104 11:46:32.277820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
23106 11:46:32.313079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
23107 11:46:32.313527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
23109 11:46:32.348298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
23110 11:46:32.348725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
23112 11:46:32.382919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
23113 11:46:32.383375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
23115 11:46:32.418382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
23116 11:46:32.418836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
23118 11:46:32.453165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
23119 11:46:32.453614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
23121 11:46:32.488025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
23123 11:46:32.488484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
23124 11:46:32.523133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
23125 11:46:32.523590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
23127 11:46:32.558291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
23128 11:46:32.558766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
23130 11:46:32.593582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
23131 11:46:32.594035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
23133 11:46:32.628252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
23134 11:46:32.628703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
23136 11:46:32.662754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
23137 11:46:32.663210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
23139 11:46:32.697401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
23140 11:46:32.697787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
23142 11:46:32.732420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
23143 11:46:32.732852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
23145 11:46:32.766754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
23146 11:46:32.767158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
23148 11:46:32.801198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
23149 11:46:32.801609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
23151 11:46:32.836077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
23153 11:46:32.836540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
23154 11:46:32.870399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
23155 11:46:32.870809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
23157 11:46:32.905432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
23159 11:46:32.906036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
23160 11:46:32.941097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
23161 11:46:32.941556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
23163 11:46:32.975941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
23165 11:46:32.976408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
23166 11:46:33.011215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
23167 11:46:33.011635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
23169 11:46:33.046499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
23171 11:46:33.046961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
23172 11:46:33.081844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
23173 11:46:33.082300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
23175 11:46:33.116992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
23177 11:46:33.117459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
23178 11:46:33.152690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
23179 11:46:33.153128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
23181 11:46:33.188060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
23183 11:46:33.188517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
23184 11:46:33.223475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
23185 11:46:33.223896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
23187 11:46:33.259252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
23188 11:46:33.259681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
23190 11:46:33.294439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
23192 11:46:33.294996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
23193 11:46:33.329456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23194 11:46:33.329941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23196 11:46:33.364512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23197 11:46:33.364939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23199 11:46:33.399346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23200 11:46:33.399836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23202 11:46:33.434301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23203 11:46:33.434719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23205 11:46:33.469228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23207 11:46:33.469695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23208 11:46:33.504441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23209 11:46:33.504853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23211 11:46:33.539921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23213 11:46:33.540388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23214 11:46:33.574702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23215 11:46:33.575160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23217 11:46:33.609695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23219 11:46:33.610262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23220 11:46:33.645219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23222 11:46:33.645817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23223 11:46:33.680706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23225 11:46:33.681260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23226 11:46:33.716519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23227 11:46:33.716974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23229 11:46:33.750758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23231 11:46:33.751308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23232 11:46:33.785278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23233 11:46:33.785742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23235 11:46:33.820932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23237 11:46:33.821478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23238 11:46:33.856089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23240 11:46:33.856641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23241 11:46:33.890744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23242 11:46:33.891205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23244 11:46:33.925441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23246 11:46:33.926000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23247 11:46:33.960462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23248 11:46:33.960912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23250 11:46:33.995015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23251 11:46:33.995468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23253 11:46:34.030630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23255 11:46:34.031262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23256 11:46:34.066272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23257 11:46:34.066713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23259 11:46:34.101772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23261 11:46:34.102328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23262 11:46:34.168573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23263 11:46:34.169017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23265 11:46:34.203427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23266 11:46:34.203850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23268 11:46:34.238812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23269 11:46:34.239269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23271 11:46:34.273662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23272 11:46:34.274107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23274 11:46:34.309006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23275 11:46:34.309446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23277 11:46:34.343578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23279 11:46:34.344127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23280 11:46:34.378311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23281 11:46:34.378762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23283 11:46:34.414624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23284 11:46:34.415069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23286 11:46:34.453832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23287 11:46:34.454260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23289 11:46:34.489546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23291 11:46:34.490013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23292 11:46:34.524012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23294 11:46:34.524473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23295 11:46:34.558812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23296 11:46:34.559265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23298 11:46:34.593392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23299 11:46:34.593822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23301 11:46:34.628505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23302 11:46:34.628917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23304 11:46:34.663267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23305 11:46:34.663722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23307 11:46:34.698722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23309 11:46:34.699278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23310 11:46:34.733382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23311 11:46:34.733785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23313 11:46:34.768310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23314 11:46:34.768741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23316 11:46:34.802814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23317 11:46:34.803224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23319 11:46:34.837728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23320 11:46:34.838157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23322 11:46:34.873637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23324 11:46:34.874202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23325 11:46:34.911972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23327 11:46:34.912590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23328 11:46:34.949183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23329 11:46:34.949616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23331 11:46:34.985022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23333 11:46:34.985447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23334 11:46:35.020824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23335 11:46:35.021251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23337 11:46:35.056021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23339 11:46:35.056564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23340 11:46:35.090908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23341 11:46:35.091335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23343 11:46:35.126128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23345 11:46:35.126667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23346 11:46:35.161069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23347 11:46:35.161496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23349 11:46:35.196478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23351 11:46:35.197005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23352 11:46:35.231179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23353 11:46:35.231609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23355 11:46:35.266166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23356 11:46:35.266585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23358 11:46:35.306161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23360 11:46:35.306690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23361 11:46:35.341409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23363 11:46:35.341966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23364 11:46:35.377141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23365 11:46:35.377569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23367 11:46:35.413088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23368 11:46:35.413508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23370 11:46:35.448849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23371 11:46:35.449277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23373 11:46:35.484081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23375 11:46:35.484622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23376 11:46:35.519260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23377 11:46:35.519649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23379 11:46:35.554793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23380 11:46:35.555201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23382 11:46:35.590252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23383 11:46:35.590643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23385 11:46:35.625785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23386 11:46:35.626196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23388 11:46:35.661338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23389 11:46:35.661773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23391 11:46:35.696949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23392 11:46:35.697384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23394 11:46:35.732838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23395 11:46:35.733255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23397 11:46:35.769088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23399 11:46:35.769545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23400 11:46:35.805475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23402 11:46:35.806129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23403 11:46:35.841098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23404 11:46:35.841528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23406 11:46:35.879557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23407 11:46:35.879943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23409 11:46:35.915318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23410 11:46:35.915707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23412 11:46:35.950814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23413 11:46:35.951199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23415 11:46:35.987290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23416 11:46:35.987688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23418 11:46:36.024832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23419 11:46:36.025255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23421 11:46:36.060983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23423 11:46:36.061592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23424 11:46:36.097403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23426 11:46:36.097992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23427 11:46:36.133297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23428 11:46:36.133757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23430 11:46:36.169655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23432 11:46:36.170286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23433 11:46:36.205405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23434 11:46:36.205871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23436 11:46:36.241422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23437 11:46:36.241905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23439 11:46:36.277141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23440 11:46:36.277607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23442 11:46:36.312704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23443 11:46:36.313157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23445 11:46:36.347840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23447 11:46:36.348421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23448 11:46:36.384883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23449 11:46:36.385334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23451 11:46:36.421335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23452 11:46:36.421768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23454 11:46:36.457701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23455 11:46:36.458169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23457 11:46:36.494524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23459 11:46:36.494978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23460 11:46:36.530621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23461 11:46:36.530993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23463 11:46:36.566700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23465 11:46:36.567254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23466 11:46:36.602468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23468 11:46:36.602945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23469 11:46:36.637980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23471 11:46:36.638437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23472 11:46:36.674142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23473 11:46:36.674611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23475 11:46:36.710464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23476 11:46:36.710934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23478 11:46:36.746259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23479 11:46:36.746721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23481 11:46:36.783107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23482 11:46:36.783584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23484 11:46:36.818955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23485 11:46:36.819443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23487 11:46:36.855119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23489 11:46:36.855570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23490 11:46:36.891378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23491 11:46:36.891803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23493 11:46:36.928697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23495 11:46:36.929155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23496 11:46:36.965005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23497 11:46:36.965426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23499 11:46:37.002538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23500 11:46:37.002966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23502 11:46:37.037553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23503 11:46:37.037962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23505 11:46:37.073708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23506 11:46:37.074094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23508 11:46:37.109317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23509 11:46:37.109786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23511 11:46:37.145360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23512 11:46:37.145826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23514 11:46:37.181821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23515 11:46:37.182278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23517 11:46:37.217595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23519 11:46:37.218238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23520 11:46:37.253738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23521 11:46:37.254212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23523 11:46:37.289349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23524 11:46:37.289815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23526 11:46:37.325284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23527 11:46:37.325684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23529 11:46:37.360829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23530 11:46:37.361273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23532 11:46:37.397437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23534 11:46:37.397896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23535 11:46:37.434018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23537 11:46:37.434471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23538 11:46:37.470501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23539 11:46:37.470918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23541 11:46:37.506751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23542 11:46:37.507134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23544 11:46:37.544012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23546 11:46:37.544573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23547 11:46:37.580773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23548 11:46:37.581228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23550 11:46:37.616494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23551 11:46:37.616953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23553 11:46:37.651408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23554 11:46:37.651848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23556 11:46:37.687845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23558 11:46:37.688315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23559 11:46:37.724938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23560 11:46:37.725358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23562 11:46:37.761008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23564 11:46:37.761439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23565 11:46:37.797211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23567 11:46:37.797657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23568 11:46:37.833394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23570 11:46:37.833847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23571 11:46:37.869564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23573 11:46:37.870162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23574 11:46:37.905715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23575 11:46:37.906167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23577 11:46:37.942735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23579 11:46:37.943278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23580 11:46:37.978698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23581 11:46:37.979136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23583 11:46:38.014248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23584 11:46:38.014712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23586 11:46:38.049811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23587 11:46:38.050248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23589 11:46:38.085570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23590 11:46:38.086044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23592 11:46:38.121529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23593 11:46:38.122001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23595 11:46:38.158778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23596 11:46:38.159245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23598 11:46:38.194930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23600 11:46:38.195527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23601 11:46:38.231482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23602 11:46:38.232010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23604 11:46:38.270254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23605 11:46:38.270701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23607 11:46:38.306685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23609 11:46:38.307259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23610 11:46:38.343919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23612 11:46:38.344604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23613 11:46:38.379461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23615 11:46:38.380128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23616 11:46:38.417539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23618 11:46:38.418130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23619 11:46:38.455900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23621 11:46:38.456512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23622 11:46:38.493300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23623 11:46:38.493741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23625 11:46:38.533479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23627 11:46:38.534041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23628 11:46:38.569350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23629 11:46:38.569773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23631 11:46:38.606392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23632 11:46:38.606859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23634 11:46:38.642428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23635 11:46:38.642890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23637 11:46:38.677537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23639 11:46:38.678098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23640 11:46:38.713140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23642 11:46:38.713677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23643 11:46:38.748370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23644 11:46:38.748791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23646 11:46:38.783485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23647 11:46:38.783882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23649 11:46:38.819235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23651 11:46:38.819677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23652 11:46:38.853248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23653 11:46:38.853703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23655 11:46:38.889264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23656 11:46:38.889693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23658 11:46:38.925122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23660 11:46:38.925673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23661 11:46:38.960789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23662 11:46:38.961236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23664 11:46:38.996937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23665 11:46:38.997374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23667 11:46:39.032603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23669 11:46:39.033166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23670 11:46:39.068994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23672 11:46:39.069554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23673 11:46:39.105607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23674 11:46:39.106054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23676 11:46:39.141697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23678 11:46:39.142151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23679 11:46:39.177560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23680 11:46:39.178008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23682 11:46:39.213898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23683 11:46:39.214357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23685 11:46:39.276610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23687 11:46:39.277192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23688 11:46:39.313103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23689 11:46:39.313580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23691 11:46:39.350182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23692 11:46:39.350591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23694 11:46:39.385823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23696 11:46:39.386437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23697 11:46:39.421715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23699 11:46:39.422258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23700 11:46:39.457527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23701 11:46:39.457966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23703 11:46:39.493332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23704 11:46:39.493767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23706 11:46:39.529274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23707 11:46:39.529670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23709 11:46:39.564389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23710 11:46:39.564780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23712 11:46:39.598942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23714 11:46:39.599387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23715 11:46:39.633766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23717 11:46:39.634226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23718 11:46:39.668827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23720 11:46:39.669384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23721 11:46:39.703330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23723 11:46:39.703879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23724 11:46:39.739206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23725 11:46:39.739653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23727 11:46:39.774498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23728 11:46:39.774950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23730 11:46:39.810183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23731 11:46:39.810602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23733 11:46:39.845824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23734 11:46:39.846223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23736 11:46:39.881418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23738 11:46:39.882046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23739 11:46:39.917826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23741 11:46:39.918394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23742 11:46:39.953483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23744 11:46:39.954058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23745 11:46:39.990132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23747 11:46:39.990597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23748 11:46:40.026888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23750 11:46:40.027351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23751 11:46:40.063579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23752 11:46:40.063980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23754 11:46:40.100915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23755 11:46:40.101326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23757 11:46:40.137170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23759 11:46:40.137622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23760 11:46:40.173290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23762 11:46:40.173749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23763 11:46:40.209456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23765 11:46:40.209912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23766 11:46:40.245992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23768 11:46:40.246552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23769 11:46:40.282981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23771 11:46:40.283528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23772 11:46:40.318190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23774 11:46:40.318655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23775 11:46:40.353410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23776 11:46:40.353880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23778 11:46:40.389230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23780 11:46:40.389932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23781 11:46:40.425531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23782 11:46:40.425993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23784 11:46:40.461471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23785 11:46:40.461941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23787 11:46:40.498246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23789 11:46:40.498796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23790 11:46:40.533893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23792 11:46:40.534504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23793 11:46:40.569714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23795 11:46:40.570255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23796 11:46:40.605686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23797 11:46:40.606109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23799 11:46:40.640862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23800 11:46:40.641286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23802 11:46:40.677147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23803 11:46:40.677569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23805 11:46:40.712799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23806 11:46:40.713266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23808 11:46:40.748732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23809 11:46:40.749157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23811 11:46:40.784874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23813 11:46:40.785299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23814 11:46:40.820969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23815 11:46:40.821383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23817 11:46:40.857069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23819 11:46:40.857530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23820 11:46:40.893596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23822 11:46:40.894065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23823 11:46:40.930167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23824 11:46:40.930643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23826 11:46:40.965821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23827 11:46:40.966294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23829 11:46:41.002852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23831 11:46:41.003437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23832 11:46:41.039582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23833 11:46:41.040050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23835 11:46:41.077167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23837 11:46:41.077874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23838 11:46:41.114844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23839 11:46:41.115262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23841 11:46:41.154649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23843 11:46:41.155121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23844 11:46:41.192574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23846 11:46:41.192942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23847 11:46:41.228553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23848 11:46:41.228922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23850 11:46:41.265069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23851 11:46:41.265470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23853 11:46:41.302784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23855 11:46:41.303270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23856 11:46:41.338093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23857 11:46:41.338562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23859 11:46:41.373293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23860 11:46:41.373762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23862 11:46:41.408973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23864 11:46:41.409535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23865 11:46:41.445114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23867 11:46:41.445695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23868 11:46:41.480850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23869 11:46:41.481278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23871 11:46:41.516421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23872 11:46:41.516890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23874 11:46:41.552074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23876 11:46:41.552650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23877 11:46:41.587533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23879 11:46:41.588015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23880 11:46:41.623169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23881 11:46:41.623589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23883 11:46:41.659310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23884 11:46:41.659813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23886 11:46:41.695460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23887 11:46:41.695916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23889 11:46:41.732141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23891 11:46:41.732697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23892 11:46:41.768608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23893 11:46:41.769035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23895 11:46:41.806666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23896 11:46:41.807099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23898 11:46:41.844940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23899 11:46:41.845362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23901 11:46:41.881270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23902 11:46:41.881683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23904 11:46:41.917004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23905 11:46:41.917417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23907 11:46:41.952938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23909 11:46:41.953389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23910 11:46:41.988866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23912 11:46:41.989446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23913 11:46:42.024077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23915 11:46:42.024462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23916 11:46:42.060638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23917 11:46:42.061037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23919 11:46:42.097089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23920 11:46:42.097550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23922 11:46:42.132702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23923 11:46:42.133178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23925 11:46:42.168076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23927 11:46:42.168719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23928 11:46:42.204349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23929 11:46:42.204790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23931 11:46:42.239962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23933 11:46:42.240513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23934 11:46:42.275386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23935 11:46:42.275854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23937 11:46:42.311744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23938 11:46:42.312228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23940 11:46:42.346750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23941 11:46:42.347209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23943 11:46:42.381661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23944 11:46:42.382079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23946 11:46:42.417235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23947 11:46:42.417674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
23949 11:46:42.453098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
23951 11:46:42.453563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
23952 11:46:42.488842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
23953 11:46:42.489305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
23955 11:46:42.524151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
23957 11:46:42.524736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
23958 11:46:42.559068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
23959 11:46:42.559492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
23961 11:46:42.594707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
23962 11:46:42.595128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
23964 11:46:42.629960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
23965 11:46:42.630385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
23967 11:46:42.665442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
23968 11:46:42.665996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
23970 11:46:42.702417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
23972 11:46:42.703066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
23973 11:46:42.737748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
23974 11:46:42.738253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
23976 11:46:42.773462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
23977 11:46:42.773936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
23979 11:46:42.810328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
23981 11:46:42.810800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
23982 11:46:42.846336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
23983 11:46:42.846786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
23985 11:46:42.882081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
23987 11:46:42.882555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
23988 11:46:42.917800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
23989 11:46:42.918240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
23991 11:46:42.953949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
23992 11:46:42.954375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
23994 11:46:42.990641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
23996 11:46:42.991220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
23997 11:46:43.025811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
23998 11:46:43.026250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
24000 11:46:43.061475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
24001 11:46:43.061956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
24003 11:46:43.097377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
24005 11:46:43.097854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
24006 11:46:43.132733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
24008 11:46:43.133210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
24009 11:46:43.168148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
24011 11:46:43.168812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
24012 11:46:43.203644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
24014 11:46:43.204295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
24015 11:46:43.239574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
24017 11:46:43.240262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
24018 11:46:43.275538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
24019 11:46:43.276002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
24021 11:46:43.311709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
24023 11:46:43.312280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
24024 11:46:43.348145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
24026 11:46:43.348613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
24027 11:46:43.384655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
24029 11:46:43.385249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
24030 11:46:43.420664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
24031 11:46:43.421134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
24033 11:46:43.457090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
24034 11:46:43.457571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
24036 11:46:43.493105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
24038 11:46:43.493758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
24039 11:46:43.529482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
24040 11:46:43.529967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
24042 11:46:43.565577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
24043 11:46:43.566085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
24045 11:46:43.601294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
24047 11:46:43.601953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
24048 11:46:43.636925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
24050 11:46:43.637563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
24051 11:46:43.672793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
24052 11:46:43.673256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
24054 11:46:43.708053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
24056 11:46:43.708649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
24057 11:46:43.744634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
24058 11:46:43.745116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
24060 11:46:43.781132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
24061 11:46:43.781560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
24063 11:46:43.818470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
24064 11:46:43.818890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
24066 11:46:43.854516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
24067 11:46:43.855003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
24069 11:46:43.890684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
24070 11:46:43.891168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
24072 11:46:43.926491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
24073 11:46:43.926917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
24075 11:46:43.962609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
24076 11:46:43.963028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
24078 11:46:43.998589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
24079 11:46:43.998977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
24081 11:46:44.035190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
24082 11:46:44.035576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
24084 11:46:44.072973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
24085 11:46:44.073362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
24087 11:46:44.109224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
24088 11:46:44.109698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
24090 11:46:44.144932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
24091 11:46:44.145327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
24093 11:46:44.180933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
24094 11:46:44.181334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
24096 11:46:44.216451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
24097 11:46:44.216874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
24099 11:46:44.251043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
24100 11:46:44.251458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
24102 11:46:44.285995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
24103 11:46:44.286389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
24105 11:46:44.321291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
24106 11:46:44.321680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
24108 11:46:44.377594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
24109 11:46:44.378069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
24111 11:46:44.422378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
24113 11:46:44.422843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
24114 11:46:44.457398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
24115 11:46:44.457822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
24117 11:46:44.492766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
24118 11:46:44.493177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
24120 11:46:44.527554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
24121 11:46:44.528037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
24123 11:46:44.562626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
24125 11:46:44.563169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
24126 11:46:44.597968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
24127 11:46:44.598353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
24129 11:46:44.634081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
24130 11:46:44.634470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
24132 11:46:44.669257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
24134 11:46:44.669693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
24135 11:46:44.704856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
24136 11:46:44.705307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
24138 11:46:44.740810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
24139 11:46:44.741228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
24141 11:46:44.775994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
24143 11:46:44.776451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
24144 11:46:44.812361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
24145 11:46:44.812837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
24147 11:46:44.846705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
24148 11:46:44.847146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
24150 11:46:44.882118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
24151 11:46:44.882526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
24153 11:46:44.918902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
24155 11:46:44.919473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
24156 11:46:44.954829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
24157 11:46:44.955259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
24159 11:46:44.990613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
24160 11:46:44.991039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
24162 11:46:45.026033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
24163 11:46:45.026452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
24165 11:46:45.061331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
24167 11:46:45.061814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
24168 11:46:45.097329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
24169 11:46:45.097754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
24171 11:46:45.134138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
24173 11:46:45.134599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
24174 11:46:45.169878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
24176 11:46:45.170434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
24177 11:46:45.205702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
24178 11:46:45.206236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
24180 11:46:45.256137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
24182 11:46:45.256879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
24183 11:46:45.294222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
24184 11:46:45.294696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
24186 11:46:45.332661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
24187 11:46:45.333136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
24189 11:46:45.368746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
24190 11:46:45.369210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
24192 11:46:45.404845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
24193 11:46:45.405217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24195 11:46:45.440904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24196 11:46:45.441244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24198 11:46:45.477085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24199 11:46:45.477519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24201 11:46:45.512951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24202 11:46:45.513386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24204 11:46:45.549255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24205 11:46:45.549692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24207 11:46:45.585211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24209 11:46:45.585752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24210 11:46:45.620798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24211 11:46:45.621223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24213 11:46:45.656873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24214 11:46:45.657286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24216 11:46:45.693014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24217 11:46:45.693442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24219 11:46:45.728844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24220 11:46:45.729265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24222 11:46:45.764714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24223 11:46:45.765098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24225 11:46:45.801156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24227 11:46:45.801685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24228 11:46:45.836684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24229 11:46:45.837106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24231 11:46:45.872515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24232 11:46:45.872937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24234 11:46:45.910601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24235 11:46:45.911043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24237 11:46:45.947312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24238 11:46:45.947789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24240 11:46:45.982742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24241 11:46:45.983171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24243 11:46:46.017729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24244 11:46:46.018169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24246 11:46:46.053330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24247 11:46:46.053795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24249 11:46:46.090977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24251 11:46:46.091523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24252 11:46:46.130741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24253 11:46:46.131182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24255 11:46:46.167792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24257 11:46:46.168375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24258 11:46:46.205817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24259 11:46:46.206254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24261 11:46:46.242504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24262 11:46:46.243030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24264 11:46:46.278244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24266 11:46:46.278692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24267 11:46:46.313818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24268 11:46:46.314266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24270 11:46:46.348676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24272 11:46:46.349243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24273 11:46:46.384224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24274 11:46:46.384688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24276 11:46:46.420447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24277 11:46:46.420899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24279 11:46:46.456618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24281 11:46:46.457068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24282 11:46:46.495316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24284 11:46:46.495886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24285 11:46:46.530961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24286 11:46:46.531416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24288 11:46:46.566239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24289 11:46:46.566654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24291 11:46:46.601439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24292 11:46:46.601821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24294 11:46:46.637169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24295 11:46:46.637628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24297 11:46:46.672931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24299 11:46:46.673484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24300 11:46:46.707725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24302 11:46:46.708319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24303 11:46:46.742788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24304 11:46:46.743209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24306 11:46:46.777729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24307 11:46:46.778190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24309 11:46:46.812894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24311 11:46:46.813355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24312 11:46:46.847895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24314 11:46:46.848346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24315 11:46:46.882687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24316 11:46:46.883158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24318 11:46:46.917686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24319 11:46:46.918134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24321 11:46:46.953208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24323 11:46:46.953831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24324 11:46:46.988074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24326 11:46:46.988683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24327 11:46:47.023092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24328 11:46:47.023555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24330 11:46:47.058270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24331 11:46:47.058708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24333 11:46:47.093198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24335 11:46:47.093720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24336 11:46:47.128509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24338 11:46:47.129059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24339 11:46:47.163238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24340 11:46:47.163688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24342 11:46:47.198321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24343 11:46:47.198826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24345 11:46:47.234078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24347 11:46:47.234643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24348 11:46:47.269042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24350 11:46:47.269690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24351 11:46:47.304145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24353 11:46:47.304719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24354 11:46:47.339199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24356 11:46:47.339787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24357 11:46:47.373814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24358 11:46:47.374243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24360 11:46:47.409030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24361 11:46:47.409475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24363 11:46:47.445128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24365 11:46:47.445665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24366 11:46:47.480739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24367 11:46:47.481162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24369 11:46:47.515972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24371 11:46:47.516519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24372 11:46:47.550308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24373 11:46:47.550770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24375 11:46:47.584867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24376 11:46:47.585324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24378 11:46:47.620865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24380 11:46:47.621446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24381 11:46:47.655161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24383 11:46:47.655774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24384 11:46:47.689865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24385 11:46:47.690320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24387 11:46:47.724740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24388 11:46:47.725162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24390 11:46:47.760016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24392 11:46:47.760604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24393 11:46:47.794600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24394 11:46:47.795079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24396 11:46:47.829869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24398 11:46:47.830580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24399 11:46:47.865299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24401 11:46:47.866011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24402 11:46:47.902655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24403 11:46:47.903125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24405 11:46:47.938409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24406 11:46:47.938917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24408 11:46:47.975043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24409 11:46:47.975498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24411 11:46:48.011591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24412 11:46:48.012036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24414 11:46:48.049856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24415 11:46:48.050284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24417 11:46:48.086125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24418 11:46:48.086573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24420 11:46:48.122143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24422 11:46:48.122609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24423 11:46:48.158348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24424 11:46:48.158794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24426 11:46:48.194265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24427 11:46:48.194678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24429 11:46:48.230665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24430 11:46:48.231164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24432 11:46:48.266614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24433 11:46:48.267030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24435 11:46:48.304431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24436 11:46:48.304915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24438 11:46:48.340107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24440 11:46:48.340689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24441 11:46:48.376718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24442 11:46:48.377171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24444 11:46:48.413097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24445 11:46:48.413565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24447 11:46:48.449148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24449 11:46:48.449741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24450 11:46:48.485172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24451 11:46:48.485603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24453 11:46:48.521470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24454 11:46:48.521926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24456 11:46:48.557444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24457 11:46:48.557908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24459 11:46:48.594003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24461 11:46:48.594557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24462 11:46:48.629828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24464 11:46:48.630375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24465 11:46:48.665298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24466 11:46:48.665761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24468 11:46:48.701068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24470 11:46:48.701524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24471 11:46:48.737219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24472 11:46:48.737632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24474 11:46:48.773986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24476 11:46:48.774634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24477 11:46:48.809467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24478 11:46:48.809956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24480 11:46:48.845556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24482 11:46:48.846198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24483 11:46:48.881323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24485 11:46:48.881877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24486 11:46:48.917361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24487 11:46:48.917819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24489 11:46:48.953244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24490 11:46:48.953686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24492 11:46:48.988808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24493 11:46:48.989230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24495 11:46:49.024810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24496 11:46:49.025259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24498 11:46:49.061282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24499 11:46:49.061690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24501 11:46:49.097142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24503 11:46:49.097785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24504 11:46:49.133304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24506 11:46:49.133879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24507 11:46:49.169370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24509 11:46:49.169976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24510 11:46:49.205660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24511 11:46:49.206121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24513 11:46:49.242317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24514 11:46:49.242772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24516 11:46:49.277447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24517 11:46:49.277941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24519 11:46:49.313460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24521 11:46:49.314119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24522 11:46:49.349301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24523 11:46:49.349783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24525 11:46:49.385267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24527 11:46:49.385751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24528 11:46:49.420658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24529 11:46:49.421091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24531 11:46:49.456818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24532 11:46:49.457289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24534 11:46:49.525528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24535 11:46:49.526047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24537 11:46:49.580075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24539 11:46:49.580607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24540 11:46:49.615228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24541 11:46:49.615673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24543 11:46:49.650418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24545 11:46:49.650976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24546 11:46:49.685848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24547 11:46:49.686303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24549 11:46:49.721475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24551 11:46:49.722031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24552 11:46:49.757246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24553 11:46:49.757698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24555 11:46:49.794378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24557 11:46:49.794918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24558 11:46:49.830407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24559 11:46:49.830834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24561 11:46:49.866085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24563 11:46:49.866624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24564 11:46:49.901458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24565 11:46:49.901900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24567 11:46:49.937395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24568 11:46:49.937850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24570 11:46:49.974771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24571 11:46:49.975194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24573 11:46:50.009919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24575 11:46:50.010461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24576 11:46:50.045128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24577 11:46:50.045591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24579 11:46:50.080470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24580 11:46:50.080935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24582 11:46:50.116892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24583 11:46:50.117318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24585 11:46:50.152892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24587 11:46:50.153430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24588 11:46:50.188884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24590 11:46:50.189429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24591 11:46:50.224975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24593 11:46:50.225530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24594 11:46:50.261117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24595 11:46:50.261568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24597 11:46:50.296779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24599 11:46:50.297417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24600 11:46:50.332390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24601 11:46:50.332850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24603 11:46:50.368636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24604 11:46:50.369083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24606 11:46:50.404738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24608 11:46:50.405302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24609 11:46:50.441325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24610 11:46:50.441802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24612 11:46:50.477676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24613 11:46:50.478129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24615 11:46:50.514177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24617 11:46:50.514656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24618 11:46:50.550052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24620 11:46:50.550809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24621 11:46:50.585705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24623 11:46:50.586349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24624 11:46:50.621504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24625 11:46:50.621927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24627 11:46:50.657813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24628 11:46:50.658244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24630 11:46:50.693908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24632 11:46:50.694442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24633 11:46:50.730442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24635 11:46:50.730984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24636 11:46:50.766469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24637 11:46:50.766915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24639 11:46:50.801670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24640 11:46:50.802119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24642 11:46:50.836902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24644 11:46:50.837627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24645 11:46:50.872599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24646 11:46:50.873076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24648 11:46:50.907950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24650 11:46:50.908541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24651 11:46:50.944549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24653 11:46:50.945134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24654 11:46:50.980637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24655 11:46:50.981106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24657 11:46:51.016976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24659 11:46:51.017559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24660 11:46:51.053341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24661 11:46:51.053810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24663 11:46:51.090217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24665 11:46:51.090812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24666 11:46:51.127019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24668 11:46:51.127512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24669 11:46:51.162862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24670 11:46:51.163355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24672 11:46:51.201225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24673 11:46:51.201709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24675 11:46:51.237539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24676 11:46:51.238049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24678 11:46:51.273739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24679 11:46:51.274204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24681 11:46:51.310001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24682 11:46:51.310475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24684 11:46:51.346161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24685 11:46:51.346624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24687 11:46:51.382240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24688 11:46:51.382706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24690 11:46:51.418137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24691 11:46:51.418595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24693 11:46:51.454032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24694 11:46:51.454514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24696 11:46:51.490637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24697 11:46:51.491103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24699 11:46:51.525817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24700 11:46:51.526277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24702 11:46:51.561984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24703 11:46:51.562365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24705 11:46:51.599361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24706 11:46:51.599822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24708 11:46:51.636626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24709 11:46:51.637043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24711 11:46:51.672736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24712 11:46:51.673150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24714 11:46:51.708143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24716 11:46:51.708607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24717 11:46:51.744321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24719 11:46:51.744867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24720 11:46:51.780135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24722 11:46:51.780691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24723 11:46:51.815383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24725 11:46:51.815934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24726 11:46:51.851341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24727 11:46:51.851816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24729 11:46:51.888381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24730 11:46:51.888881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24732 11:46:51.923131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24733 11:46:51.923523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24735 11:46:51.958346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24737 11:46:51.958888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24738 11:46:51.994084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24739 11:46:51.994550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24741 11:46:52.030213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24742 11:46:52.030677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24744 11:46:52.066355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24746 11:46:52.066936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24747 11:46:52.102863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24749 11:46:52.103323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24750 11:46:52.138708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24751 11:46:52.139188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24753 11:46:52.174228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24754 11:46:52.174693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24756 11:46:52.210144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24757 11:46:52.210605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24759 11:46:52.245860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24760 11:46:52.246345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24762 11:46:52.282668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24763 11:46:52.283118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24765 11:46:52.318143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24766 11:46:52.318605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24768 11:46:52.353387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24769 11:46:52.353808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24771 11:46:52.390064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24772 11:46:52.390449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24774 11:46:52.426421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24775 11:46:52.426887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24777 11:46:52.461880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24778 11:46:52.462361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24780 11:46:52.497495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24781 11:46:52.497976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24783 11:46:52.534101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24785 11:46:52.534560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24786 11:46:52.570192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24787 11:46:52.570608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24789 11:46:52.606520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24791 11:46:52.607105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24792 11:46:52.645378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24793 11:46:52.645771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24795 11:46:52.685940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24796 11:46:52.686366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24798 11:46:52.717722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24799 11:46:52.718152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24801 11:46:52.749560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24803 11:46:52.750032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24804 11:46:52.781198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24805 11:46:52.781623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24807 11:46:52.813098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24809 11:46:52.813565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24810 11:46:52.844532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24811 11:46:52.844953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24813 11:46:52.876811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24814 11:46:52.877241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24816 11:46:52.908042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24818 11:46:52.908603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24819 11:46:52.938928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24820 11:46:52.939370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24822 11:46:52.969781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24823 11:46:52.970210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24825 11:46:53.001610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24827 11:46:53.002249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24828 11:46:53.033108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24830 11:46:53.033740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24831 11:46:53.065253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24833 11:46:53.065912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24834 11:46:53.098015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24835 11:46:53.098488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24837 11:46:53.129256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24839 11:46:53.129886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24840 11:46:53.160947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24842 11:46:53.161577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24843 11:46:53.193481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24844 11:46:53.193942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24846 11:46:53.225146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24847 11:46:53.225586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24849 11:46:53.257071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24851 11:46:53.257627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24852 11:46:53.288594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24853 11:46:53.289075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24855 11:46:53.320456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24856 11:46:53.320922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24858 11:46:53.352899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24860 11:46:53.353502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24861 11:46:53.384738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24863 11:46:53.385388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24864 11:46:53.415931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24866 11:46:53.416518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24867 11:46:53.448389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24868 11:46:53.448857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24870 11:46:53.479878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24872 11:46:53.480564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24873 11:46:53.511228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24874 11:46:53.511693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24876 11:46:53.542817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24877 11:46:53.543270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24879 11:46:53.574768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24880 11:46:53.575228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24882 11:46:53.606663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24883 11:46:53.607115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24885 11:46:53.637637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24887 11:46:53.638197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24888 11:46:53.669667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24889 11:46:53.670120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24891 11:46:53.701179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24893 11:46:53.701737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24894 11:46:53.732572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24895 11:46:53.733023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24897 11:46:53.764953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24899 11:46:53.765420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24900 11:46:53.796881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24901 11:46:53.797304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24903 11:46:53.828235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24904 11:46:53.828661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24906 11:46:53.859308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24907 11:46:53.859689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24909 11:46:53.890421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24910 11:46:53.890850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24912 11:46:53.922420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24913 11:46:53.922879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24915 11:46:53.954149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24916 11:46:53.954600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24918 11:46:53.986194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24919 11:46:53.986634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24921 11:46:54.018913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24923 11:46:54.019384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24924 11:46:54.052889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24925 11:46:54.053325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24927 11:46:54.085553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24928 11:46:54.086018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24930 11:46:54.117694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24932 11:46:54.118252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24933 11:46:54.149505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24934 11:46:54.149988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24936 11:46:54.181066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24938 11:46:54.181526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24939 11:46:54.213220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24941 11:46:54.213873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24942 11:46:54.244575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24943 11:46:54.245025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24945 11:46:54.276118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24946 11:46:54.276584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24948 11:46:54.308292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
24950 11:46:54.308924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
24951 11:46:54.339504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
24952 11:46:54.340007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
24954 11:46:54.371851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
24956 11:46:54.372527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
24957 11:46:54.402789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
24958 11:46:54.403208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
24960 11:46:54.439219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
24961 11:46:54.439666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
24963 11:46:54.472515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
24964 11:46:54.472936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
24966 11:46:54.503880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
24968 11:46:54.504346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
24969 11:46:54.536016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
24971 11:46:54.536497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
24972 11:46:54.567942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
24974 11:46:54.568345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
24975 11:46:54.622854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
24976 11:46:54.623308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
24978 11:46:54.654278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
24979 11:46:54.654720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
24981 11:46:54.685773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
24982 11:46:54.686252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
24984 11:46:54.716977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
24985 11:46:54.717467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
24987 11:46:54.748775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
24988 11:46:54.749256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
24990 11:46:54.780530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
24991 11:46:54.780991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
24993 11:46:54.813711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
24994 11:46:54.814177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
24996 11:46:54.845383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
24997 11:46:54.845831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
24999 11:46:54.876579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
25000 11:46:54.877031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
25002 11:46:54.907697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
25003 11:46:54.908167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
25005 11:46:54.939701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
25007 11:46:54.940329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
25008 11:46:54.972981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
25010 11:46:54.973562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
25011 11:46:55.004944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
25013 11:46:55.005548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
25014 11:46:55.037117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
25015 11:46:55.037546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
25017 11:46:55.069770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
25018 11:46:55.070209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
25020 11:46:55.102156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
25022 11:46:55.102622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
25023 11:46:55.133443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
25024 11:46:55.133869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
25026 11:46:55.165039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
25028 11:46:55.165605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
25029 11:46:55.197126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
25030 11:46:55.197546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
25032 11:46:55.228746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
25033 11:46:55.229198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
25035 11:46:55.262054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
25036 11:46:55.262488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
25038 11:46:55.294158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
25039 11:46:55.294613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
25041 11:46:55.326877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
25042 11:46:55.327312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
25044 11:46:55.359071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
25045 11:46:55.359503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
25047 11:46:55.391855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
25049 11:46:55.392428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
25050 11:46:55.424597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
25051 11:46:55.425064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
25053 11:46:55.457016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
25055 11:46:55.457569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
25056 11:46:55.489873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
25057 11:46:55.490321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
25059 11:46:55.522525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
25061 11:46:55.523076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
25062 11:46:55.554749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
25063 11:46:55.555190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
25065 11:46:55.586428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
25066 11:46:55.586813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
25068 11:46:55.618143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
25069 11:46:55.618530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
25071 11:46:55.650311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
25072 11:46:55.650766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
25074 11:46:55.682366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
25076 11:46:55.682985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
25077 11:46:55.714257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
25079 11:46:55.714875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
25080 11:46:55.746609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
25081 11:46:55.747082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
25083 11:46:55.778613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
25084 11:46:55.779088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
25086 11:46:55.810852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
25088 11:46:55.811469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
25089 11:46:55.843508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
25091 11:46:55.844133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
25092 11:46:55.875312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
25093 11:46:55.875781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
25095 11:46:55.906935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
25096 11:46:55.907361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
25098 11:46:55.938623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
25099 11:46:55.939072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
25101 11:46:55.969740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
25102 11:46:55.970210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
25104 11:46:56.001643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
25105 11:46:56.002053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
25107 11:46:56.033491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
25108 11:46:56.033957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
25110 11:46:56.065389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
25112 11:46:56.065962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
25113 11:46:56.098811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
25114 11:46:56.099260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
25116 11:46:56.133424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
25118 11:46:56.134014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
25119 11:46:56.170641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
25121 11:46:56.171052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
25122 11:46:56.205204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
25124 11:46:56.205693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
25125 11:46:56.242678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
25126 11:46:56.243157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
25128 11:46:56.278275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
25129 11:46:56.278664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
25131 11:46:56.311617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
25133 11:46:56.312097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
25134 11:46:56.342697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
25135 11:46:56.343142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
25137 11:46:56.374322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
25139 11:46:56.374790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
25140 11:46:56.405317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
25141 11:46:56.405792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
25143 11:46:56.436576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
25144 11:46:56.437040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
25146 11:46:56.469524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
25148 11:46:56.469999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
25149 11:46:56.501154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
25150 11:46:56.501569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
25152 11:46:56.533619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
25153 11:46:56.534028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
25155 11:46:56.566744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
25156 11:46:56.567189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
25158 11:46:56.598882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
25159 11:46:56.599267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
25161 11:46:56.631250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
25162 11:46:56.631693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
25164 11:46:56.663711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
25165 11:46:56.664188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
25167 11:46:56.695532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
25168 11:46:56.695996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
25170 11:46:56.728033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
25172 11:46:56.728588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
25173 11:46:56.759409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
25174 11:46:56.759866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
25176 11:46:56.791225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
25177 11:46:56.791667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
25179 11:46:56.824743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
25180 11:46:56.825221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
25182 11:46:56.857126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
25183 11:46:56.857574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
25185 11:46:56.889930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
25186 11:46:56.890374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
25188 11:46:56.921880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
25189 11:46:56.922391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
25191 11:46:56.954168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25192 11:46:56.954570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
25194 11:46:56.986557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25196 11:46:56.987005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25197 11:46:57.018318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25198 11:46:57.018745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25200 11:46:57.050099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25201 11:46:57.050561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25203 11:46:57.082927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25205 11:46:57.083490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25206 11:46:57.114839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25207 11:46:57.115330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25209 11:46:57.147068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25211 11:46:57.147528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25212 11:46:57.178709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25213 11:46:57.179105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25215 11:46:57.210258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25216 11:46:57.210717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25218 11:46:57.241569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25219 11:46:57.242082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25221 11:46:57.273526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25222 11:46:57.273966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25224 11:46:57.304920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25225 11:46:57.305346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25227 11:46:57.341155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25229 11:46:57.341630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25230 11:46:57.375140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25232 11:46:57.375767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25233 11:46:57.406990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25235 11:46:57.407605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25236 11:46:57.438035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25237 11:46:57.438463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25239 11:46:57.469247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25240 11:46:57.469697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25242 11:46:57.501678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25243 11:46:57.502169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25245 11:46:57.533248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25246 11:46:57.533699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25248 11:46:57.565357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25250 11:46:57.565920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25251 11:46:57.597243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25253 11:46:57.597820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25254 11:46:57.628768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25256 11:46:57.629211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25257 11:46:57.660712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25258 11:46:57.661188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25260 11:46:57.693025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25261 11:46:57.693485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25263 11:46:57.725726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25265 11:46:57.726303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25266 11:46:57.758825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25267 11:46:57.759295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25269 11:46:57.790474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25271 11:46:57.791103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25272 11:46:57.821208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25273 11:46:57.821657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25275 11:46:57.853020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25277 11:46:57.853460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25278 11:46:57.884653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25280 11:46:57.885131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25281 11:46:57.916361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25282 11:46:57.916802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25284 11:46:57.947631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25285 11:46:57.948052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25287 11:46:57.978722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25288 11:46:57.979186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25290 11:46:58.010131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25291 11:46:58.010589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25293 11:46:58.041457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25295 11:46:58.042030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25296 11:46:58.073084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25297 11:46:58.073529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25299 11:46:58.104762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25300 11:46:58.105241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25302 11:46:58.135993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25304 11:46:58.136661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25305 11:46:58.168338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25307 11:46:58.168975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25308 11:46:58.200373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25309 11:46:58.200856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25311 11:46:58.232424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25313 11:46:58.233058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25314 11:46:58.265472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25315 11:46:58.265900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25317 11:46:58.297728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25318 11:46:58.298168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25320 11:46:58.329422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25321 11:46:58.329845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25323 11:46:58.361490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25324 11:46:58.361989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25326 11:46:58.393516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25328 11:46:58.393998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25329 11:46:58.424745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25330 11:46:58.425190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25332 11:46:58.455940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25334 11:46:58.456415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25335 11:46:58.487095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25336 11:46:58.487522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25338 11:46:58.521645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25340 11:46:58.522211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25341 11:46:58.555024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25342 11:46:58.555449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25344 11:46:58.587099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25346 11:46:58.587584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25347 11:46:58.621332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25348 11:46:58.621789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25350 11:46:58.653733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25351 11:46:58.654186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25353 11:46:58.685790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25354 11:46:58.686194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25356 11:46:58.718965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25357 11:46:58.719411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25359 11:46:58.750827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25360 11:46:58.751250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25362 11:46:58.782851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25363 11:46:58.783275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25365 11:46:58.813861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25366 11:46:58.814307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25368 11:46:58.845979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25369 11:46:58.846405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25371 11:46:58.877475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25372 11:46:58.877905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25374 11:46:58.910952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25375 11:46:58.911372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25377 11:46:58.945536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25378 11:46:58.945972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25380 11:46:58.978323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25382 11:46:58.979044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25383 11:46:59.013523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25384 11:46:59.014008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25386 11:46:59.045490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25388 11:46:59.046069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25389 11:46:59.077302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25390 11:46:59.077741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25392 11:46:59.108964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25394 11:46:59.109399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25395 11:46:59.141004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25397 11:46:59.141654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25398 11:46:59.172579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25399 11:46:59.173033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25401 11:46:59.207087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25402 11:46:59.207559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25404 11:46:59.238475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25406 11:46:59.239104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25407 11:46:59.269357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25408 11:46:59.269857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25410 11:46:59.300773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25411 11:46:59.301259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25413 11:46:59.332046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25414 11:46:59.332536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25416 11:46:59.363164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25417 11:46:59.363586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25419 11:46:59.397716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25420 11:46:59.398135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25422 11:46:59.431446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25423 11:46:59.431878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25425 11:46:59.464321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25427 11:46:59.464886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25428 11:46:59.496684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25429 11:46:59.497142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25431 11:46:59.528128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25433 11:46:59.528697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25434 11:46:59.560857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25435 11:46:59.561301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25437 11:46:59.591930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25439 11:46:59.592595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25440 11:46:59.623673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25441 11:46:59.624129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25443 11:46:59.656102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25445 11:46:59.656683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25446 11:46:59.688442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25447 11:46:59.688857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25449 11:46:59.738353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25450 11:46:59.738766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25452 11:46:59.769762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25453 11:46:59.770184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25455 11:46:59.801325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25456 11:46:59.801750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25458 11:46:59.833319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25459 11:46:59.833730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25461 11:46:59.864691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25463 11:46:59.865138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25464 11:46:59.896087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25466 11:46:59.896540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25467 11:46:59.927645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25469 11:46:59.928114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25470 11:46:59.959247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25471 11:46:59.959713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25473 11:46:59.991143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25475 11:46:59.991894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25476 11:47:00.023037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25477 11:47:00.023488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25479 11:47:00.054213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25480 11:47:00.054656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25482 11:47:00.085502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25483 11:47:00.085988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25485 11:47:00.116895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25487 11:47:00.117514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25488 11:47:00.147944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25490 11:47:00.148580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25491 11:47:00.179444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25492 11:47:00.179861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25494 11:47:00.211261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25495 11:47:00.211684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25497 11:47:00.242895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25499 11:47:00.243339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25500 11:47:00.274254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25501 11:47:00.274726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25503 11:47:00.305414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25504 11:47:00.305899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25506 11:47:00.336785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25508 11:47:00.337362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25509 11:47:00.368301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25510 11:47:00.368743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25512 11:47:00.400036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25514 11:47:00.400582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25515 11:47:00.433083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25516 11:47:00.433539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25518 11:47:00.465339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25519 11:47:00.465794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25521 11:47:00.497736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25523 11:47:00.498443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25524 11:47:00.530944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25525 11:47:00.531386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25527 11:47:00.562336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25528 11:47:00.562813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25530 11:47:00.594527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25531 11:47:00.594985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25533 11:47:00.625785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25535 11:47:00.626330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25536 11:47:00.656990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25537 11:47:00.657457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25539 11:47:00.688517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25540 11:47:00.688948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25542 11:47:00.719524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25543 11:47:00.719965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25545 11:47:00.750633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25546 11:47:00.751066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25548 11:47:00.781595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25549 11:47:00.782051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25551 11:47:00.813390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25552 11:47:00.813861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25554 11:47:00.845385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25556 11:47:00.845918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25557 11:47:00.876645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25558 11:47:00.877073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25560 11:47:00.908291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25561 11:47:00.908758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25563 11:47:00.939627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25565 11:47:00.940179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25566 11:47:00.970945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25568 11:47:00.971486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25569 11:47:01.002788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25571 11:47:01.003419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25572 11:47:01.034146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25573 11:47:01.034608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25575 11:47:01.066078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25577 11:47:01.066532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25578 11:47:01.097787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25580 11:47:01.098254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25581 11:47:01.131726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25583 11:47:01.132196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25584 11:47:01.164085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25586 11:47:01.164543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25587 11:47:01.196359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25588 11:47:01.196774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25590 11:47:01.229399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25592 11:47:01.230069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25593 11:47:01.264117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25595 11:47:01.264598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25596 11:47:01.298620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25598 11:47:01.299097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25599 11:47:01.332692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25600 11:47:01.333192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25602 11:47:01.365934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25603 11:47:01.366474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25605 11:47:01.398162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25606 11:47:01.398676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25608 11:47:01.431020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25609 11:47:01.431436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25611 11:47:01.463680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25613 11:47:01.464157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25614 11:47:01.497666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25616 11:47:01.498228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25617 11:47:01.530578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25618 11:47:01.531047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25620 11:47:01.565038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25621 11:47:01.565474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25623 11:47:01.599740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25625 11:47:01.600209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25626 11:47:01.635494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25627 11:47:01.635930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25629 11:47:01.670093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25630 11:47:01.670472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25632 11:47:01.701986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25633 11:47:01.702382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25635 11:47:01.734068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25637 11:47:01.734514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25638 11:47:01.766139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25640 11:47:01.766644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25641 11:47:01.797818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25642 11:47:01.798197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25644 11:47:01.829371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25646 11:47:01.830017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25647 11:47:01.861148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25649 11:47:01.861720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25650 11:47:01.892776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25652 11:47:01.893326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25653 11:47:01.923639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25655 11:47:01.924194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25656 11:47:01.954876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25657 11:47:01.955339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25659 11:47:01.985977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25660 11:47:01.986438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25662 11:47:02.016924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25663 11:47:02.017375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25665 11:47:02.048435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25666 11:47:02.048922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25668 11:47:02.080033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25670 11:47:02.080637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25671 11:47:02.112770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25673 11:47:02.113340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25674 11:47:02.144438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25676 11:47:02.144992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25677 11:47:02.176513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25678 11:47:02.176989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25680 11:47:02.208810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25681 11:47:02.209262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25683 11:47:02.240184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25685 11:47:02.240736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25686 11:47:02.272872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25687 11:47:02.273349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25689 11:47:02.305540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25691 11:47:02.306140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25692 11:47:02.337210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25694 11:47:02.337795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25695 11:47:02.368817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25696 11:47:02.369214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25698 11:47:02.400695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25699 11:47:02.401124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25701 11:47:02.431998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25703 11:47:02.432467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25704 11:47:02.463484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25705 11:47:02.463912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25707 11:47:02.495715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25708 11:47:02.496207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25710 11:47:02.527549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25711 11:47:02.528013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25713 11:47:02.558950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25715 11:47:02.559415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25716 11:47:02.590483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25718 11:47:02.590953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25719 11:47:02.622621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25720 11:47:02.623054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25722 11:47:02.655924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25724 11:47:02.656390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25725 11:47:02.687413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25726 11:47:02.687797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25728 11:47:02.719422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25730 11:47:02.719985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25731 11:47:02.753133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25732 11:47:02.753623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25734 11:47:02.785305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25735 11:47:02.785779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25737 11:47:02.817438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25739 11:47:02.817923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25740 11:47:02.849440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25742 11:47:02.849916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25743 11:47:02.881804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25744 11:47:02.882230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25746 11:47:02.914058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25747 11:47:02.914506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25749 11:47:02.945358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25751 11:47:02.945851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25752 11:47:02.977426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25754 11:47:02.977903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25755 11:47:03.009446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25756 11:47:03.009880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25758 11:47:03.041716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25759 11:47:03.042141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25761 11:47:03.074238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25762 11:47:03.074680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25764 11:47:03.107256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25765 11:47:03.107682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25767 11:47:03.141102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25768 11:47:03.141525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25770 11:47:03.173535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25771 11:47:03.173966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25773 11:47:03.205559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25775 11:47:03.206032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25776 11:47:03.237571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25777 11:47:03.238031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25779 11:47:03.269786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25780 11:47:03.270244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25782 11:47:03.301349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25784 11:47:03.301949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25785 11:47:03.333830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25787 11:47:03.334258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25788 11:47:03.365593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25789 11:47:03.366021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25791 11:47:03.396902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25792 11:47:03.397338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25794 11:47:03.432207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25795 11:47:03.432681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25797 11:47:03.463619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25799 11:47:03.464183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25800 11:47:03.494986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25801 11:47:03.495454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25803 11:47:03.527553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25804 11:47:03.528036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25806 11:47:03.559470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25807 11:47:03.559875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25809 11:47:03.590772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25810 11:47:03.591169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25812 11:47:03.622703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25813 11:47:03.623156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25815 11:47:03.654934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25816 11:47:03.655378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25818 11:47:03.687257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25820 11:47:03.687883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25821 11:47:03.718103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25822 11:47:03.718578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25824 11:47:03.749501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25825 11:47:03.749959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25827 11:47:03.781420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25829 11:47:03.781898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25830 11:47:03.812855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25831 11:47:03.813322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25833 11:47:03.843433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25834 11:47:03.843913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25836 11:47:03.874913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25838 11:47:03.875527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25839 11:47:03.906456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25841 11:47:03.907022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25842 11:47:03.939174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25843 11:47:03.939561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25845 11:47:03.971198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25846 11:47:03.971640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25848 11:47:04.003639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25850 11:47:04.004211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25851 11:47:04.035881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25853 11:47:04.036455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25854 11:47:04.068628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25855 11:47:04.069091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25857 11:47:04.101396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25858 11:47:04.101921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25860 11:47:04.135201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25862 11:47:04.135854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25863 11:47:04.167764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25865 11:47:04.168432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25866 11:47:04.199426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25867 11:47:04.199905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25869 11:47:04.230964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25871 11:47:04.231601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25872 11:47:04.262626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25873 11:47:04.263038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25875 11:47:04.294748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25876 11:47:04.295172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25878 11:47:04.326482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25879 11:47:04.326891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25881 11:47:04.360428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25882 11:47:04.360848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25884 11:47:04.391985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25886 11:47:04.392565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25887 11:47:04.426220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25889 11:47:04.426772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25890 11:47:04.458379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25891 11:47:04.458835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25893 11:47:04.490820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25894 11:47:04.491303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25896 11:47:04.522755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25898 11:47:04.523225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25899 11:47:04.554884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25900 11:47:04.555359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25902 11:47:04.587232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25904 11:47:04.587686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25905 11:47:04.618982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25907 11:47:04.619454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25908 11:47:04.650388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25909 11:47:04.650793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25911 11:47:04.682207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25912 11:47:04.682677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25914 11:47:04.714328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25916 11:47:04.714894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25917 11:47:04.746184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25919 11:47:04.746741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25920 11:47:04.778125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25921 11:47:04.778582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25923 11:47:04.810191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25924 11:47:04.810665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25926 11:47:04.863851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25928 11:47:04.864314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25929 11:47:04.895047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25930 11:47:04.895511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25932 11:47:04.926830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25933 11:47:04.927339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25935 11:47:04.958256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25937 11:47:04.958734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25938 11:47:04.989807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25939 11:47:04.990265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25941 11:47:05.020967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25943 11:47:05.021535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25944 11:47:05.052487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25945 11:47:05.052895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25947 11:47:05.085160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
25949 11:47:05.085611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25950 11:47:05.117577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
25952 11:47:05.118156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
25953 11:47:05.149871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
25954 11:47:05.150282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
25956 11:47:05.181896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
25957 11:47:05.182315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
25959 11:47:05.214141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
25960 11:47:05.214558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
25962 11:47:05.246184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
25963 11:47:05.246588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
25965 11:47:05.278088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
25966 11:47:05.278477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
25968 11:47:05.310265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
25969 11:47:05.310688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
25971 11:47:05.342280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
25973 11:47:05.342851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
25974 11:47:05.374208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
25975 11:47:05.374617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
25977 11:47:05.409721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
25979 11:47:05.410362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
25980 11:47:05.442540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
25982 11:47:05.443174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
25983 11:47:05.474310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
25984 11:47:05.474790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
25986 11:47:05.506602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
25988 11:47:05.507229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
25989 11:47:05.538995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
25991 11:47:05.539614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
25992 11:47:05.570704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
25993 11:47:05.571177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
25995 11:47:05.602969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
25996 11:47:05.603443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
25998 11:47:05.635090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
26000 11:47:05.635721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
26001 11:47:05.667670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
26002 11:47:05.668131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
26004 11:47:05.700370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
26005 11:47:05.700826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
26007 11:47:05.732622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
26008 11:47:05.733047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
26010 11:47:05.764620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
26011 11:47:05.765085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
26013 11:47:05.796810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
26014 11:47:05.797275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
26016 11:47:05.828959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
26017 11:47:05.829435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
26019 11:47:05.861319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
26021 11:47:05.861949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
26022 11:47:05.893437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
26023 11:47:05.893931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
26025 11:47:05.925828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
26027 11:47:05.926448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
26028 11:47:05.957804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
26029 11:47:05.958209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
26031 11:47:05.989772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
26032 11:47:05.990238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
26034 11:47:06.022379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
26035 11:47:06.022824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
26037 11:47:06.054176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
26039 11:47:06.054744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
26040 11:47:06.085999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
26041 11:47:06.086452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
26043 11:47:06.118101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
26044 11:47:06.118555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
26046 11:47:06.162455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
26047 11:47:06.162921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
26049 11:47:06.208946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
26050 11:47:06.209421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
26052 11:47:06.243466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
26054 11:47:06.244080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
26055 11:47:06.278383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
26057 11:47:06.278761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
26058 11:47:06.312658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
26059 11:47:06.313033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
26061 11:47:06.344884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
26063 11:47:06.345436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
26064 11:47:06.376705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
26065 11:47:06.377161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
26067 11:47:06.408679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
26068 11:47:06.409118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
26070 11:47:06.440462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
26071 11:47:06.440913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
26073 11:47:06.473188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
26074 11:47:06.473637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
26076 11:47:06.509640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
26077 11:47:06.510256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
26079 11:47:06.543995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
26081 11:47:06.544547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
26082 11:47:06.586315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
26084 11:47:06.586875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
26085 11:47:06.622981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
26086 11:47:06.623446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
26088 11:47:06.659581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
26090 11:47:06.660041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
26091 11:47:06.697468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
26093 11:47:06.697842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
26094 11:47:06.731168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
26095 11:47:06.731539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
26097 11:47:06.763699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
26099 11:47:06.764396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
26100 11:47:06.797173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
26101 11:47:06.797618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
26103 11:47:06.828718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
26104 11:47:06.829143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
26106 11:47:06.861105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
26107 11:47:06.861531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
26109 11:47:06.892727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
26110 11:47:06.893201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
26112 11:47:06.924486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
26113 11:47:06.924970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
26115 11:47:06.956934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
26116 11:47:06.957343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
26118 11:47:06.988787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
26119 11:47:06.989214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
26121 11:47:07.022223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
26122 11:47:07.022664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
26124 11:47:07.058001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
26125 11:47:07.058457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
26127 11:47:07.093251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
26128 11:47:07.093698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
26130 11:47:07.128743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
26131 11:47:07.129193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
26133 11:47:07.166154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
26135 11:47:07.166621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
26136 11:47:07.202203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
26137 11:47:07.202666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
26139 11:47:07.237203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
26140 11:47:07.237618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
26142 11:47:07.273806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
26143 11:47:07.274199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
26145 11:47:07.308756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
26146 11:47:07.309205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
26148 11:47:07.344949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
26149 11:47:07.345398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
26151 11:47:07.380958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
26153 11:47:07.381425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
26154 11:47:07.416677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
26156 11:47:07.417142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
26157 11:47:07.452456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
26159 11:47:07.452898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
26160 11:47:07.487469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
26161 11:47:07.487888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
26163 11:47:07.522861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
26164 11:47:07.523298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
26166 11:47:07.558161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
26168 11:47:07.558809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
26169 11:47:07.594187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
26171 11:47:07.594647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
26172 11:47:07.629063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
26173 11:47:07.629501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
26175 11:47:07.664862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
26176 11:47:07.665277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
26178 11:47:07.700785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
26180 11:47:07.701350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
26181 11:47:07.736628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
26183 11:47:07.737192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
26184 11:47:07.772952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
26185 11:47:07.773373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
26187 11:47:07.809473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
26188 11:47:07.809898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
26190 11:47:07.845528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
26191 11:47:07.845967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26193 11:47:07.882114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26194 11:47:07.882540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26196 11:47:07.918607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26197 11:47:07.919090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26199 11:47:07.954487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26201 11:47:07.955123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26202 11:47:07.990951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26203 11:47:07.991375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26205 11:47:08.026065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26206 11:47:08.026500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26208 11:47:08.061572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26209 11:47:08.062026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26211 11:47:08.097449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26213 11:47:08.097933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26214 11:47:08.134410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26215 11:47:08.134883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26217 11:47:08.170389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26219 11:47:08.170848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26220 11:47:08.206152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26221 11:47:08.206567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26223 11:47:08.242137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26225 11:47:08.242692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26226 11:47:08.278092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26227 11:47:08.278545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26229 11:47:08.315314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26231 11:47:08.315866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26232 11:47:08.351200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26233 11:47:08.351626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26235 11:47:08.387388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26236 11:47:08.387833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26238 11:47:08.424045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26240 11:47:08.424623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26241 11:47:08.461208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26242 11:47:08.461681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26244 11:47:08.497278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26245 11:47:08.497760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26247 11:47:08.533038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26248 11:47:08.533469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26250 11:47:08.569215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26251 11:47:08.569640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26253 11:47:08.604829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26254 11:47:08.605264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26256 11:47:08.640740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26258 11:47:08.641221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26259 11:47:08.676932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26260 11:47:08.677391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26262 11:47:08.712853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26263 11:47:08.713270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26265 11:47:08.749180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26266 11:47:08.749625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26268 11:47:08.785102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26269 11:47:08.785526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26271 11:47:08.821020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26273 11:47:08.821480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26274 11:47:08.855963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26276 11:47:08.856437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26277 11:47:08.891266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26278 11:47:08.891746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26280 11:47:08.926122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26281 11:47:08.926597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26283 11:47:08.961725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26284 11:47:08.962195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26286 11:47:08.996788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26287 11:47:08.997252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26289 11:47:09.032317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26291 11:47:09.032780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26292 11:47:09.067058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26294 11:47:09.067524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26295 11:47:09.102592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26297 11:47:09.103067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26298 11:47:09.139489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26300 11:47:09.140070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26301 11:47:09.177164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26303 11:47:09.177827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26304 11:47:09.213015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26306 11:47:09.213479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26307 11:47:09.249066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26309 11:47:09.249630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26310 11:47:09.285027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26311 11:47:09.285396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26313 11:47:09.320717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26314 11:47:09.321105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26316 11:47:09.357156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26317 11:47:09.357525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26319 11:47:09.395370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26320 11:47:09.395775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26322 11:47:09.433402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26324 11:47:09.433983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26325 11:47:09.470385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26327 11:47:09.470957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26328 11:47:09.509845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26329 11:47:09.510324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26331 11:47:09.545521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26332 11:47:09.545983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26334 11:47:09.580831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26335 11:47:09.581216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26337 11:47:09.616494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26338 11:47:09.616885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26340 11:47:09.653796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26342 11:47:09.654261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26343 11:47:09.691516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26344 11:47:09.691984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26346 11:47:09.726972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26348 11:47:09.727523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26349 11:47:09.761928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26350 11:47:09.762355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26352 11:47:09.797158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26354 11:47:09.797802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26355 11:47:09.832746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26356 11:47:09.833216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26358 11:47:09.869113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26360 11:47:09.869879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26361 11:47:09.905063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26362 11:47:09.905511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26364 11:47:09.940059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26366 11:47:09.940705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26367 11:47:09.994695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26368 11:47:09.995175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26370 11:47:10.029914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26371 11:47:10.030406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26373 11:47:10.064846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26374 11:47:10.065285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26376 11:47:10.100074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26378 11:47:10.100630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26379 11:47:10.135294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26381 11:47:10.135912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26382 11:47:10.170544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26384 11:47:10.171097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26385 11:47:10.205241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26387 11:47:10.205894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26388 11:47:10.240320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26389 11:47:10.240784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26391 11:47:10.275639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26393 11:47:10.276277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26394 11:47:10.311727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26396 11:47:10.312284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26397 11:47:10.346805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26398 11:47:10.347259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26400 11:47:10.381495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26401 11:47:10.381964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26403 11:47:10.416567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26404 11:47:10.417038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26406 11:47:10.451265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26408 11:47:10.451851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26409 11:47:10.485716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26411 11:47:10.486278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26412 11:47:10.520765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26414 11:47:10.521319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26415 11:47:10.556112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26417 11:47:10.556664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26418 11:47:10.591362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26419 11:47:10.591825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26421 11:47:10.626384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26423 11:47:10.626949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26424 11:47:10.661619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26425 11:47:10.662063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26427 11:47:10.698018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26429 11:47:10.698591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26430 11:47:10.733409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26432 11:47:10.733977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26433 11:47:10.769237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26434 11:47:10.769708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26436 11:47:10.805202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26437 11:47:10.805669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26439 11:47:10.840756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26441 11:47:10.841235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26442 11:47:10.875836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26444 11:47:10.876309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26445 11:47:10.910817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26447 11:47:10.911429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26448 11:47:10.945465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26449 11:47:10.945920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26451 11:47:10.981323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26452 11:47:10.981757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26454 11:47:11.016715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26455 11:47:11.017142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26457 11:47:11.052304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26459 11:47:11.052842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26460 11:47:11.087355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26461 11:47:11.087762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26463 11:47:11.122445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26464 11:47:11.122852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26466 11:47:11.159500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26468 11:47:11.160103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26469 11:47:11.210894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26471 11:47:11.211464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26472 11:47:11.247488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26473 11:47:11.247940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26475 11:47:11.282765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26476 11:47:11.283264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26478 11:47:11.317568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26480 11:47:11.318155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26481 11:47:11.351487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26483 11:47:11.352087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26484 11:47:11.385959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26485 11:47:11.386421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26487 11:47:11.418262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26488 11:47:11.418632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26490 11:47:11.451240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26491 11:47:11.451688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26493 11:47:11.483294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26494 11:47:11.483798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26496 11:47:11.520496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26497 11:47:11.520968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26499 11:47:11.557336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26500 11:47:11.557892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26502 11:47:11.594451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26503 11:47:11.594911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26505 11:47:11.629008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26506 11:47:11.629490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26508 11:47:11.664573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26509 11:47:11.665007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26511 11:47:11.696831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26513 11:47:11.697409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26514 11:47:11.729161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26515 11:47:11.729620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26517 11:47:11.761009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26518 11:47:11.761491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26520 11:47:11.794744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26521 11:47:11.795166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26523 11:47:11.828551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26525 11:47:11.829021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26526 11:47:11.861785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26528 11:47:11.862257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26529 11:47:11.895530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26531 11:47:11.895990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26532 11:47:11.927924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26534 11:47:11.928392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26535 11:47:11.960392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26536 11:47:11.960812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26538 11:47:11.992853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26539 11:47:11.993270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26541 11:47:12.025027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26543 11:47:12.025577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26544 11:47:12.057511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26545 11:47:12.057961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26547 11:47:12.090041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26548 11:47:12.090504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26550 11:47:12.121718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26551 11:47:12.122155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26553 11:47:12.153991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26554 11:47:12.154456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26556 11:47:12.185603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26557 11:47:12.186023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26559 11:47:12.217459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26561 11:47:12.217917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26562 11:47:12.250081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26563 11:47:12.250506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26565 11:47:12.282314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26567 11:47:12.282779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26568 11:47:12.317252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26569 11:47:12.317694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26571 11:47:12.350344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26572 11:47:12.350825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26574 11:47:12.382045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26575 11:47:12.382492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26577 11:47:12.413323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26579 11:47:12.413781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26580 11:47:12.445179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26581 11:47:12.445585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26583 11:47:12.477018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26584 11:47:12.477430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26586 11:47:12.510077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26587 11:47:12.510485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26589 11:47:12.543637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26590 11:47:12.544059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26592 11:47:12.578096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26594 11:47:12.578562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26595 11:47:12.610532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26597 11:47:12.610985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26598 11:47:12.642572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26600 11:47:12.643019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26601 11:47:12.674632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26603 11:47:12.675186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26604 11:47:12.706573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26606 11:47:12.707123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26607 11:47:12.739182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26608 11:47:12.739633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26610 11:47:12.771570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26612 11:47:12.772125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26613 11:47:12.803002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26614 11:47:12.803446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26616 11:47:12.834815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26617 11:47:12.835267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26619 11:47:12.866785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26620 11:47:12.867221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26622 11:47:12.898452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26623 11:47:12.898869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26625 11:47:12.930285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26626 11:47:12.930729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26628 11:47:12.962415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26630 11:47:12.962888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26631 11:47:12.994180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26633 11:47:12.994646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26634 11:47:13.025416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26636 11:47:13.025895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26637 11:47:13.057170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26638 11:47:13.057586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26640 11:47:13.089633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26642 11:47:13.090206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26643 11:47:13.121692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26644 11:47:13.122120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26646 11:47:13.153711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26647 11:47:13.154136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26649 11:47:13.185686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26650 11:47:13.186086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26652 11:47:13.216974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26654 11:47:13.217688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26655 11:47:13.248751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26657 11:47:13.249387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26658 11:47:13.280726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26659 11:47:13.281210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26661 11:47:13.312360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26662 11:47:13.312846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26664 11:47:13.344009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26666 11:47:13.344484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26667 11:47:13.376922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26668 11:47:13.377348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26670 11:47:13.408729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26671 11:47:13.409152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26673 11:47:13.440282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26674 11:47:13.440745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26676 11:47:13.472386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26677 11:47:13.472837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26679 11:47:13.504253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26680 11:47:13.504643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26682 11:47:13.536587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26684 11:47:13.537070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26685 11:47:13.568192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26686 11:47:13.568625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26688 11:47:13.600745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26690 11:47:13.601398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26691 11:47:13.632905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26693 11:47:13.633536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26694 11:47:13.665202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26696 11:47:13.665685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26697 11:47:13.697396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26698 11:47:13.697822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26700 11:47:13.729776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26702 11:47:13.730220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26703 11:47:13.761740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26704 11:47:13.762203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26706 11:47:13.796569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26707 11:47:13.797136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26709 11:47:13.830807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26710 11:47:13.831282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26712 11:47:13.862736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26713 11:47:13.863181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26715 11:47:13.894643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26716 11:47:13.895101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26718 11:47:13.925736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26719 11:47:13.926218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26721 11:47:13.958179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26723 11:47:13.958650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26724 11:47:13.990070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26725 11:47:13.990492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26727 11:47:14.025037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26729 11:47:14.025507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26730 11:47:14.061605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26731 11:47:14.062032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26733 11:47:14.097634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26734 11:47:14.098133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26736 11:47:14.133587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26738 11:47:14.134238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26739 11:47:14.169191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26740 11:47:14.169631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26742 11:47:14.205195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26743 11:47:14.205640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26745 11:47:14.241365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26747 11:47:14.241832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26748 11:47:14.277024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26749 11:47:14.277446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26751 11:47:14.312718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26753 11:47:14.313282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26754 11:47:14.348150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26756 11:47:14.348622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26757 11:47:14.384455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26758 11:47:14.384870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26760 11:47:14.420912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26761 11:47:14.421326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26763 11:47:14.458564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26765 11:47:14.459206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26766 11:47:14.494442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26767 11:47:14.494862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26769 11:47:14.530509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26771 11:47:14.531074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26772 11:47:14.570182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26773 11:47:14.570634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26775 11:47:14.605908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26776 11:47:14.606323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26778 11:47:14.641746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26779 11:47:14.642195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26781 11:47:14.680874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26782 11:47:14.681354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26784 11:47:14.718793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26786 11:47:14.719225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26787 11:47:14.754933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26788 11:47:14.755336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26790 11:47:14.790964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26791 11:47:14.791381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26793 11:47:14.826174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26794 11:47:14.826614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26796 11:47:14.861403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26797 11:47:14.861821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26799 11:47:14.896753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26801 11:47:14.897212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26802 11:47:14.932792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26803 11:47:14.933232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26805 11:47:14.968610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26807 11:47:14.969083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26808 11:47:15.003757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26810 11:47:15.004340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26811 11:47:15.038679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26812 11:47:15.039142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26814 11:47:15.089722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26815 11:47:15.090147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26817 11:47:15.139923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26819 11:47:15.140399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26820 11:47:15.175765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26822 11:47:15.176227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26823 11:47:15.211274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26825 11:47:15.211732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26826 11:47:15.246741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26828 11:47:15.247194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26829 11:47:15.281890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26831 11:47:15.282464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26832 11:47:15.317237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26833 11:47:15.317677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26835 11:47:15.352492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26836 11:47:15.352921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26838 11:47:15.387741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26840 11:47:15.388382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26841 11:47:15.423684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26842 11:47:15.424165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26844 11:47:15.459599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26845 11:47:15.460068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26847 11:47:15.497536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26849 11:47:15.498108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26850 11:47:15.533505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26852 11:47:15.534075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26853 11:47:15.569307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26855 11:47:15.569953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26856 11:47:15.605343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26857 11:47:15.605790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26859 11:47:15.641383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26860 11:47:15.641832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26862 11:47:15.677464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26863 11:47:15.677942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26865 11:47:15.713549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26866 11:47:15.714005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26868 11:47:15.749192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26869 11:47:15.749642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26871 11:47:15.785253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26872 11:47:15.785680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26874 11:47:15.821456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26875 11:47:15.821887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26877 11:47:15.857237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26878 11:47:15.857694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26880 11:47:15.892931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26881 11:47:15.893390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26883 11:47:15.928762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26884 11:47:15.929222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26886 11:47:15.964917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26887 11:47:15.965330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26889 11:47:16.000945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26890 11:47:16.001339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26892 11:47:16.037257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26893 11:47:16.037680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26895 11:47:16.074404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26896 11:47:16.074816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26898 11:47:16.114107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26899 11:47:16.114527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26901 11:47:16.149506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26902 11:47:16.149928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26904 11:47:16.193160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26905 11:47:16.193557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26907 11:47:16.237922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26909 11:47:16.238559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26910 11:47:16.274803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26912 11:47:16.275306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26913 11:47:16.313350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26914 11:47:16.313782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26916 11:47:16.352037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26918 11:47:16.352511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26919 11:47:16.388235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26920 11:47:16.388610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26922 11:47:16.422991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26923 11:47:16.423463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26925 11:47:16.457989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26927 11:47:16.458527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26928 11:47:16.497771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26929 11:47:16.498242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26931 11:47:16.534824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26932 11:47:16.535318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26934 11:47:16.570273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26935 11:47:16.570738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26937 11:47:16.606514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26938 11:47:16.606978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26940 11:47:16.642309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26941 11:47:16.642717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26943 11:47:16.678497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26944 11:47:16.678843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26946 11:47:16.714162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26947 11:47:16.714514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
26949 11:47:16.750325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
26951 11:47:16.750863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
26952 11:47:16.786029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
26953 11:47:16.786471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
26955 11:47:16.822770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
26956 11:47:16.823229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
26958 11:47:16.858674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
26960 11:47:16.859230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
26961 11:47:16.894282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
26962 11:47:16.894731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
26964 11:47:16.929949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
26966 11:47:16.930494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
26967 11:47:16.965690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
26968 11:47:16.966161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
26970 11:47:17.002258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
26971 11:47:17.002715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
26973 11:47:17.037392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
26974 11:47:17.037808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
26976 11:47:17.073301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
26977 11:47:17.073681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
26979 11:47:17.109642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
26981 11:47:17.110106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
26982 11:47:17.146202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
26983 11:47:17.146621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
26985 11:47:17.182903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
26986 11:47:17.183474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
26988 11:47:17.219519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
26989 11:47:17.219948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
26991 11:47:17.254844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
26992 11:47:17.255241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
26994 11:47:17.290179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
26996 11:47:17.290745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
26997 11:47:17.325708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
26998 11:47:17.326190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
27000 11:47:17.361178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
27002 11:47:17.361782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
27003 11:47:17.395576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
27004 11:47:17.396073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
27006 11:47:17.430947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
27007 11:47:17.431433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
27009 11:47:17.467563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
27010 11:47:17.468041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
27012 11:47:17.505170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
27014 11:47:17.505849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
27015 11:47:17.541095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
27016 11:47:17.541589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
27018 11:47:17.576663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
27020 11:47:17.577225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
27021 11:47:17.610755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
27022 11:47:17.611222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
27024 11:47:17.645575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
27025 11:47:17.646059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
27027 11:47:17.680668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
27028 11:47:17.681124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
27030 11:47:17.715531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
27031 11:47:17.715952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
27033 11:47:17.750881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
27035 11:47:17.751519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
27036 11:47:17.793736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
27037 11:47:17.794217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
27039 11:47:17.829163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
27041 11:47:17.829630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
27042 11:47:17.863426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
27043 11:47:17.863842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
27045 11:47:17.897780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
27046 11:47:17.898197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
27048 11:47:17.932771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
27050 11:47:17.933244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
27051 11:47:17.967633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
27053 11:47:17.968189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
27054 11:47:18.002182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
27056 11:47:18.002779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
27057 11:47:18.036655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
27059 11:47:18.037131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
27060 11:47:18.070522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
27061 11:47:18.070993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
27063 11:47:18.104923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
27065 11:47:18.105558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
27066 11:47:18.141373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
27067 11:47:18.141798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
27069 11:47:18.177238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
27070 11:47:18.177687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
27072 11:47:18.213072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
27074 11:47:18.213724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
27075 11:47:18.249263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
27076 11:47:18.249700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
27078 11:47:18.285990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
27079 11:47:18.286523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
27081 11:47:18.321998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
27083 11:47:18.322570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
27084 11:47:18.357979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
27085 11:47:18.358428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
27087 11:47:18.395297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
27089 11:47:18.395866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
27090 11:47:18.431409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
27091 11:47:18.431868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
27093 11:47:18.467920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
27095 11:47:18.468536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
27096 11:47:18.504332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
27097 11:47:18.504749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
27099 11:47:18.539687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
27100 11:47:18.540106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
27102 11:47:18.583249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
27103 11:47:18.583733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
27105 11:47:18.630045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
27107 11:47:18.630501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
27108 11:47:18.666349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
27109 11:47:18.666807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
27111 11:47:18.702578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
27112 11:47:18.703032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
27114 11:47:18.739026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
27115 11:47:18.739488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
27117 11:47:18.774491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
27118 11:47:18.774963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
27120 11:47:18.810529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
27121 11:47:18.810961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
27123 11:47:18.846147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
27124 11:47:18.846598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
27126 11:47:18.882137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
27127 11:47:18.882583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
27129 11:47:18.918470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
27131 11:47:18.919016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
27132 11:47:18.956686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
27133 11:47:18.957098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
27135 11:47:18.992581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
27136 11:47:18.992997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
27138 11:47:19.027933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
27140 11:47:19.028567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
27141 11:47:19.063233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
27142 11:47:19.063693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
27144 11:47:19.098596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
27145 11:47:19.099055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
27147 11:47:19.133846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
27149 11:47:19.134396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
27150 11:47:19.169328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
27151 11:47:19.169804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
27153 11:47:19.205027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
27154 11:47:19.205427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
27156 11:47:19.241255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
27157 11:47:19.241691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
27159 11:47:19.277353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
27161 11:47:19.277924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
27162 11:47:19.313712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
27163 11:47:19.314169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
27165 11:47:19.348856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
27166 11:47:19.349302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
27168 11:47:19.385026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
27170 11:47:19.385490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
27171 11:47:19.420535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
27172 11:47:19.420957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
27174 11:47:19.455435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
27176 11:47:19.456061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
27177 11:47:19.490524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
27178 11:47:19.490917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
27180 11:47:19.525811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
27181 11:47:19.526299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
27183 11:47:19.561665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
27185 11:47:19.562233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
27186 11:47:19.597554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
27187 11:47:19.597977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
27189 11:47:19.633043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
27190 11:47:19.633546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
27192 11:47:19.668519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27194 11:47:19.669104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27195 11:47:19.704649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27196 11:47:19.705112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27198 11:47:19.741057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27199 11:47:19.741469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27201 11:47:19.777677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27203 11:47:19.778321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27204 11:47:19.813856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27206 11:47:19.814418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27207 11:47:19.849987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27208 11:47:19.850451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27210 11:47:19.885986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27212 11:47:19.886450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27213 11:47:19.922062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27215 11:47:19.922628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27216 11:47:19.957787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27217 11:47:19.958246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27219 11:47:19.994683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27221 11:47:19.995269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27222 11:47:20.028511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27223 11:47:20.028930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27225 11:47:20.061547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27227 11:47:20.062016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27228 11:47:20.095889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27230 11:47:20.096520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27231 11:47:20.127449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27232 11:47:20.127931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27234 11:47:20.158644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27235 11:47:20.159138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27237 11:47:20.197940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27239 11:47:20.198574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27240 11:47:20.243452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27241 11:47:20.243868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27243 11:47:20.275006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27244 11:47:20.275418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27246 11:47:20.306373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27247 11:47:20.306829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27249 11:47:20.338046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27250 11:47:20.338500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27252 11:47:20.369374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27253 11:47:20.369882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27255 11:47:20.401390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27257 11:47:20.401965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27258 11:47:20.433685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27259 11:47:20.434142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27261 11:47:20.465185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27263 11:47:20.465741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27264 11:47:20.496799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27265 11:47:20.497230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27267 11:47:20.528303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27269 11:47:20.528745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27270 11:47:20.559585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27271 11:47:20.560044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27273 11:47:20.590468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27275 11:47:20.590905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27276 11:47:20.621898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27277 11:47:20.622348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27279 11:47:20.654040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27280 11:47:20.654486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27282 11:47:20.685578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27284 11:47:20.686138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27285 11:47:20.716965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27287 11:47:20.717528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27288 11:47:20.748572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27289 11:47:20.749031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27291 11:47:20.779959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27293 11:47:20.780410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27294 11:47:20.811396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27295 11:47:20.811815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27297 11:47:20.842946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27298 11:47:20.843426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27300 11:47:20.874707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27302 11:47:20.875337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27303 11:47:20.906349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27304 11:47:20.906807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27306 11:47:20.938036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27307 11:47:20.938492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27309 11:47:20.970132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27310 11:47:20.970587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27312 11:47:21.001598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27313 11:47:21.002065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27315 11:47:21.033801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27316 11:47:21.034325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27318 11:47:21.066689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27319 11:47:21.067152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27321 11:47:21.099119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27323 11:47:21.099726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27324 11:47:21.130401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27325 11:47:21.130867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27327 11:47:21.163249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27328 11:47:21.163738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27330 11:47:21.198574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27332 11:47:21.199324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27333 11:47:21.250253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27335 11:47:21.250723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27336 11:47:21.284608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27337 11:47:21.285132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27339 11:47:21.320900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27341 11:47:21.321354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27342 11:47:21.355425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27343 11:47:21.355986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27345 11:47:21.388710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27346 11:47:21.389251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27348 11:47:21.420826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27350 11:47:21.421402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27351 11:47:21.453406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27352 11:47:21.453879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27354 11:47:21.486295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27355 11:47:21.486722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27357 11:47:21.518114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27358 11:47:21.518536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27360 11:47:21.553194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27361 11:47:21.553621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27363 11:47:21.585032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27364 11:47:21.585462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27366 11:47:21.617567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27368 11:47:21.618164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27369 11:47:21.650435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27370 11:47:21.650899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27372 11:47:21.682807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27373 11:47:21.683271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27375 11:47:21.715998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27377 11:47:21.716469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27378 11:47:21.748358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27379 11:47:21.748788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27381 11:47:21.780059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27383 11:47:21.780526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27384 11:47:21.811608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27385 11:47:21.812028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27387 11:47:21.843274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27388 11:47:21.843670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27390 11:47:21.874895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27391 11:47:21.875325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27393 11:47:21.907147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27395 11:47:21.907617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27396 11:47:21.938369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27397 11:47:21.938788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27399 11:47:21.969882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27400 11:47:21.970308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27402 11:47:22.001876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27403 11:47:22.002295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27405 11:47:22.032908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27406 11:47:22.033393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27408 11:47:22.064060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27410 11:47:22.064617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27411 11:47:22.095625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27412 11:47:22.096093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27414 11:47:22.126934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27415 11:47:22.127370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27417 11:47:22.159275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27419 11:47:22.159917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27420 11:47:22.191737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27422 11:47:22.192402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27423 11:47:22.223667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27425 11:47:22.224253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27426 11:47:22.256041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27428 11:47:22.256602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27429 11:47:22.287880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27431 11:47:22.288512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27432 11:47:22.320860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27434 11:47:22.321413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27435 11:47:22.353147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27436 11:47:22.353556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27438 11:47:22.385659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27439 11:47:22.386070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27441 11:47:22.419176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27443 11:47:22.419638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27444 11:47:22.457188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27446 11:47:22.457665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27447 11:47:22.489088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27449 11:47:22.489551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27450 11:47:22.521904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27451 11:47:22.522380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27453 11:47:22.554004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27454 11:47:22.554489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27456 11:47:22.586044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27458 11:47:22.586509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27459 11:47:22.618049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27461 11:47:22.618515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27462 11:47:22.650023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27463 11:47:22.650448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27465 11:47:22.681705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27467 11:47:22.682173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27468 11:47:22.713537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27469 11:47:22.713957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27471 11:47:22.745621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27472 11:47:22.746047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27474 11:47:22.777933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27475 11:47:22.778355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27477 11:47:22.810319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27479 11:47:22.810773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27480 11:47:22.842566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27481 11:47:22.842981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27483 11:47:22.875127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27484 11:47:22.875581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27486 11:47:22.907119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27487 11:47:22.907535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27489 11:47:22.939476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27490 11:47:22.939949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27492 11:47:22.971556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27493 11:47:22.971987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27495 11:47:23.003552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27496 11:47:23.003996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27498 11:47:23.035569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27499 11:47:23.035998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27501 11:47:23.067418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27503 11:47:23.068011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27504 11:47:23.099565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27505 11:47:23.099978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27507 11:47:23.132393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27508 11:47:23.132803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27510 11:47:23.164876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27511 11:47:23.165279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27513 11:47:23.198174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27514 11:47:23.198576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27516 11:47:23.230929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27517 11:47:23.231343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27519 11:47:23.262910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27520 11:47:23.263361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27522 11:47:23.294462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27523 11:47:23.294884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27525 11:47:23.326101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27526 11:47:23.326528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27528 11:47:23.357770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27530 11:47:23.358241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27531 11:47:23.398028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27532 11:47:23.398487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27534 11:47:23.431668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27536 11:47:23.432266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27537 11:47:23.465373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27539 11:47:23.466020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27540 11:47:23.499555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27541 11:47:23.499976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27543 11:47:23.533571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27544 11:47:23.534054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27546 11:47:23.567977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27548 11:47:23.568610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27549 11:47:23.601081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27551 11:47:23.601564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27552 11:47:23.633922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27553 11:47:23.634339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27555 11:47:23.667376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27557 11:47:23.667852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27558 11:47:23.701156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27559 11:47:23.701600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27561 11:47:23.733515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27563 11:47:23.733939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27564 11:47:23.765339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27565 11:47:23.765793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27567 11:47:23.797250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27568 11:47:23.797722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27570 11:47:23.829474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27572 11:47:23.830035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27573 11:47:23.861142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27575 11:47:23.861719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27576 11:47:23.893099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27577 11:47:23.893569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27579 11:47:23.924921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27580 11:47:23.925373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27582 11:47:23.959224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27584 11:47:23.959845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27585 11:47:23.993382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27586 11:47:23.993884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27588 11:47:24.025290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27589 11:47:24.025743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27591 11:47:24.061196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27593 11:47:24.061783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27594 11:47:24.093543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27595 11:47:24.094014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27597 11:47:24.125066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27599 11:47:24.125619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27600 11:47:24.156398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27601 11:47:24.156861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27603 11:47:24.187666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27604 11:47:24.188086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27606 11:47:24.219958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27608 11:47:24.220407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27609 11:47:24.253094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27611 11:47:24.253548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27612 11:47:24.285459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27614 11:47:24.285923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27615 11:47:24.317890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27617 11:47:24.318459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27618 11:47:24.353638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27619 11:47:24.354109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27621 11:47:24.385926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27622 11:47:24.386379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27624 11:47:24.417639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27625 11:47:24.418097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27627 11:47:24.450590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27628 11:47:24.451024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27630 11:47:24.482840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27631 11:47:24.483299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27633 11:47:24.515026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27634 11:47:24.515481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27636 11:47:24.546949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27637 11:47:24.547407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27639 11:47:24.578862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27640 11:47:24.579324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27642 11:47:24.611525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27643 11:47:24.611988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27645 11:47:24.643688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27646 11:47:24.644177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27648 11:47:24.675566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27649 11:47:24.676039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27651 11:47:24.707480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27652 11:47:24.707947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27654 11:47:24.739563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27655 11:47:24.740012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27657 11:47:24.770972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27658 11:47:24.771400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27660 11:47:24.803127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27662 11:47:24.803676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27663 11:47:24.834962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27664 11:47:24.835421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27666 11:47:24.866835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27667 11:47:24.867298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27669 11:47:24.898765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27670 11:47:24.899227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27672 11:47:24.930868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27674 11:47:24.931435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27675 11:47:24.963070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27677 11:47:24.963632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27678 11:47:24.995199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27679 11:47:24.995625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27681 11:47:25.027331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27683 11:47:25.027800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27684 11:47:25.058521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27685 11:47:25.058937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27687 11:47:25.089882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27688 11:47:25.090311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27690 11:47:25.121329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27691 11:47:25.121771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27693 11:47:25.153005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27695 11:47:25.153467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27696 11:47:25.183996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27698 11:47:25.184567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27699 11:47:25.217499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27701 11:47:25.218189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27702 11:47:25.251431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27703 11:47:25.251901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27705 11:47:25.285017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27706 11:47:25.285437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27708 11:47:25.344516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27709 11:47:25.344924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27711 11:47:25.380422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27712 11:47:25.380809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27714 11:47:25.412531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27715 11:47:25.412950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27717 11:47:25.443487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27719 11:47:25.444096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27720 11:47:25.474737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27722 11:47:25.475292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27723 11:47:25.506684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27725 11:47:25.507232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27726 11:47:25.538062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27727 11:47:25.538508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27729 11:47:25.570045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27731 11:47:25.570601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27732 11:47:25.601690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27733 11:47:25.602130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27735 11:47:25.633202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27736 11:47:25.633635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27738 11:47:25.665490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27739 11:47:25.665969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27741 11:47:25.696377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27742 11:47:25.696789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27744 11:47:25.741119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27746 11:47:25.741843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27747 11:47:25.773556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27748 11:47:25.774030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27750 11:47:25.805902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27751 11:47:25.806370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27753 11:47:25.839341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27755 11:47:25.839909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27756 11:47:25.873210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27757 11:47:25.873698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27759 11:47:25.906536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27760 11:47:25.907024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27762 11:47:25.940763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27763 11:47:25.941244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27765 11:47:25.975163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27766 11:47:25.975657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27768 11:47:26.013576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27769 11:47:26.014016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27771 11:47:26.051821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27773 11:47:26.052295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27774 11:47:26.087360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27776 11:47:26.087830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27777 11:47:26.123393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27779 11:47:26.123859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27780 11:47:26.158088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27781 11:47:26.158516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27783 11:47:26.192252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27785 11:47:26.192715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27786 11:47:26.227242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27788 11:47:26.227710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27789 11:47:26.263535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27790 11:47:26.263965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27792 11:47:26.301083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27794 11:47:26.301563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27795 11:47:26.337361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27796 11:47:26.337770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27798 11:47:26.374415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27800 11:47:26.374830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27801 11:47:26.408347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27803 11:47:26.408711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27804 11:47:26.440327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27806 11:47:26.440869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27807 11:47:26.472370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27808 11:47:26.472796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27810 11:47:26.504589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27812 11:47:26.505158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27813 11:47:26.535754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27815 11:47:26.536417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27816 11:47:26.580062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27818 11:47:26.580667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27819 11:47:26.623281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27821 11:47:26.623836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27822 11:47:26.657899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27823 11:47:26.658375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27825 11:47:26.694737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27826 11:47:26.695205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27828 11:47:26.727715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27830 11:47:26.728300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27831 11:47:26.759678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27833 11:47:26.760148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27834 11:47:26.792171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27835 11:47:26.792607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27837 11:47:26.823974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27839 11:47:26.824597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27840 11:47:26.856324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27842 11:47:26.856779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27843 11:47:26.890673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27844 11:47:26.891107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27846 11:47:26.922375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27847 11:47:26.922799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27849 11:47:26.953726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27850 11:47:26.954147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27852 11:47:26.985371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27853 11:47:26.985811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27855 11:47:27.016409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27856 11:47:27.016889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27858 11:47:27.047305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27859 11:47:27.047781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27861 11:47:27.078403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27862 11:47:27.078843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27864 11:47:27.109697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27865 11:47:27.110170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27867 11:47:27.141397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27869 11:47:27.141991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27870 11:47:27.175075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27872 11:47:27.175672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27873 11:47:27.208083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27875 11:47:27.208652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27876 11:47:27.240202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27877 11:47:27.240629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27879 11:47:27.271896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27881 11:47:27.272353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27882 11:47:27.303680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27884 11:47:27.304137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27885 11:47:27.336071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27886 11:47:27.336561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27888 11:47:27.368194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27889 11:47:27.368680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27891 11:47:27.400287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27892 11:47:27.400766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27894 11:47:27.432521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27896 11:47:27.432961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27897 11:47:27.465347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27899 11:47:27.465936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27900 11:47:27.496971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27901 11:47:27.497421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27903 11:47:27.527590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27904 11:47:27.528002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27906 11:47:27.558951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27907 11:47:27.559448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27909 11:47:27.592816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27911 11:47:27.593390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27912 11:47:27.624672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27913 11:47:27.625153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27915 11:47:27.657231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27916 11:47:27.657692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27918 11:47:27.691270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27919 11:47:27.691767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27921 11:47:27.723545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27922 11:47:27.723992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27924 11:47:27.755866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27926 11:47:27.756494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27927 11:47:27.790373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27929 11:47:27.790994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27930 11:47:27.823582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27932 11:47:27.824187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27933 11:47:27.856510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27934 11:47:27.856879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27936 11:47:27.892858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27937 11:47:27.893293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27939 11:47:27.929117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27940 11:47:27.929607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27942 11:47:27.965036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27944 11:47:27.965492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27945 11:47:28.001085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27946 11:47:28.001497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
27948 11:47:28.037022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
27949 11:47:28.037463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
27951 11:47:28.073245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
27952 11:47:28.073699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
27954 11:47:28.109326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
27955 11:47:28.109782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
27957 11:47:28.144970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
27958 11:47:28.145456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
27960 11:47:28.180777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
27961 11:47:28.181219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
27963 11:47:28.216925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
27965 11:47:28.217468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
27966 11:47:28.252726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
27968 11:47:28.253290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
27969 11:47:28.289010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
27970 11:47:28.289476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
27972 11:47:28.324350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
27974 11:47:28.324897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
27975 11:47:28.359196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
27976 11:47:28.359697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
27978 11:47:28.395128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
27979 11:47:28.395616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
27981 11:47:28.430694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
27983 11:47:28.431241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
27984 11:47:28.465889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
27986 11:47:28.466415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
27987 11:47:28.501489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
27988 11:47:28.501947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
27990 11:47:28.537453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
27991 11:47:28.537861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
27993 11:47:28.574120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
27994 11:47:28.574538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
27996 11:47:28.609772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
27997 11:47:28.610187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
27999 11:47:28.645823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
28001 11:47:28.646456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
28002 11:47:28.681497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
28004 11:47:28.682063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
28005 11:47:28.717709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
28006 11:47:28.718098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
28008 11:47:28.753805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
28009 11:47:28.754265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
28011 11:47:28.790606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
28012 11:47:28.791021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
28014 11:47:28.826199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
28015 11:47:28.826637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
28017 11:47:28.862670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
28019 11:47:28.863315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
28020 11:47:28.898250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
28021 11:47:28.898727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
28023 11:47:28.934142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
28025 11:47:28.934689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
28026 11:47:28.970572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
28027 11:47:28.971040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
28029 11:47:29.006321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
28030 11:47:29.006798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
28032 11:47:29.042182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
28034 11:47:29.042647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
28035 11:47:29.077933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
28037 11:47:29.078396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
28038 11:47:29.113450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
28040 11:47:29.114008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
28041 11:47:29.149264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
28043 11:47:29.149904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
28044 11:47:29.185058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
28046 11:47:29.185704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
28047 11:47:29.220607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
28048 11:47:29.221067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
28050 11:47:29.255904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
28052 11:47:29.256510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
28053 11:47:29.291592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
28054 11:47:29.292083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
28056 11:47:29.327070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
28058 11:47:29.327535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
28059 11:47:29.362335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
28060 11:47:29.362729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
28062 11:47:29.398278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
28063 11:47:29.398735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
28065 11:47:29.434436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
28067 11:47:29.434990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
28068 11:47:29.469720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
28070 11:47:29.470268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
28071 11:47:29.505324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
28073 11:47:29.505892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
28074 11:47:29.540834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
28075 11:47:29.541305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
28077 11:47:29.576571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
28079 11:47:29.577034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
28080 11:47:29.611509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
28081 11:47:29.611984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
28083 11:47:29.646620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
28085 11:47:29.647070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
28086 11:47:29.681854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
28087 11:47:29.682328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
28089 11:47:29.717324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
28091 11:47:29.717965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
28092 11:47:29.752899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
28093 11:47:29.753371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
28095 11:47:29.788547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
28097 11:47:29.789175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
28098 11:47:29.823098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
28100 11:47:29.823736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
28101 11:47:29.858064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
28103 11:47:29.858531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
28104 11:47:29.893559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
28105 11:47:29.893982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
28107 11:47:29.930270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
28108 11:47:29.930679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
28110 11:47:29.965578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
28112 11:47:29.966031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
28113 11:47:30.001436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
28115 11:47:30.001907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
28116 11:47:30.037421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
28118 11:47:30.037907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
28119 11:47:30.072399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
28121 11:47:30.072857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
28122 11:47:30.107321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
28124 11:47:30.107963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
28125 11:47:30.142307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
28126 11:47:30.142791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
28128 11:47:30.176860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
28129 11:47:30.177342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
28131 11:47:30.211274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
28132 11:47:30.211782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
28134 11:47:30.246665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
28135 11:47:30.247084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
28137 11:47:30.281539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
28138 11:47:30.281980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
28140 11:47:30.317399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
28142 11:47:30.318052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
28143 11:47:30.352658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
28144 11:47:30.353054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
28146 11:47:30.387403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
28148 11:47:30.387896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
28149 11:47:30.423070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
28150 11:47:30.423484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
28152 11:47:30.481937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
28153 11:47:30.482415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
28155 11:47:30.517041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
28156 11:47:30.517518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
28158 11:47:30.552834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
28160 11:47:30.553404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
28161 11:47:30.588568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
28162 11:47:30.589041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
28164 11:47:30.624409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
28165 11:47:30.624893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
28167 11:47:30.660375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
28168 11:47:30.660861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
28170 11:47:30.695148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
28171 11:47:30.695565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
28173 11:47:30.730201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
28174 11:47:30.730631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
28176 11:47:30.765942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
28177 11:47:30.766357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
28179 11:47:30.801688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
28181 11:47:30.802140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
28182 11:47:30.837349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
28183 11:47:30.837777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
28185 11:47:30.873803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
28187 11:47:30.874255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
28188 11:47:30.909347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
28189 11:47:30.909786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
28191 11:47:30.945783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28193 11:47:30.946257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28194 11:47:30.980920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28195 11:47:30.981400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28197 11:47:31.015395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28199 11:47:31.015965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28200 11:47:31.049317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28201 11:47:31.049749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28203 11:47:31.084969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28205 11:47:31.085426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28206 11:47:31.118814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28208 11:47:31.119411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28209 11:47:31.153094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28210 11:47:31.153586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28212 11:47:31.188514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28213 11:47:31.188962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28215 11:47:31.223452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28216 11:47:31.223883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28218 11:47:31.260630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28220 11:47:31.261418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28221 11:47:31.295043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28222 11:47:31.295605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28224 11:47:31.331175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28225 11:47:31.331597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28227 11:47:31.369704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28228 11:47:31.370146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28230 11:47:31.409846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28231 11:47:31.410241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28233 11:47:31.445598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28234 11:47:31.446029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28236 11:47:31.480874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28237 11:47:31.481317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28239 11:47:31.515589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28241 11:47:31.516272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28242 11:47:31.550767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28244 11:47:31.551469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28245 11:47:31.585185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28246 11:47:31.585686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28248 11:47:31.620706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28250 11:47:31.621167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28251 11:47:31.655424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28252 11:47:31.655872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28254 11:47:31.690210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28256 11:47:31.690670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28257 11:47:31.726581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28259 11:47:31.727043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28260 11:47:31.761938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28262 11:47:31.762412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28263 11:47:31.797211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28264 11:47:31.797650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28266 11:47:31.832827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28268 11:47:31.833387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28269 11:47:31.868908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28271 11:47:31.869551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28272 11:47:31.904246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28273 11:47:31.904792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28275 11:47:31.940660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28277 11:47:31.941237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28278 11:47:31.975621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28279 11:47:31.976087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28281 11:47:32.012612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28282 11:47:32.013034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28284 11:47:32.047782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28286 11:47:32.048257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28287 11:47:32.083734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28289 11:47:32.084300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28290 11:47:32.119359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28291 11:47:32.119836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28293 11:47:32.155321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28294 11:47:32.155773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28296 11:47:32.191245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28297 11:47:32.191698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28299 11:47:32.227473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28301 11:47:32.228025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28302 11:47:32.262993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28303 11:47:32.263406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28305 11:47:32.298354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28306 11:47:32.298789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28308 11:47:32.333721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28310 11:47:32.334354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28311 11:47:32.369267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28312 11:47:32.369691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28314 11:47:32.405213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28315 11:47:32.405691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28317 11:47:32.440382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28318 11:47:32.440851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28320 11:47:32.475443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28321 11:47:32.475927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28323 11:47:32.511256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28324 11:47:32.511712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28326 11:47:32.545758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28328 11:47:32.546300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28329 11:47:32.580760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28331 11:47:32.581213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28332 11:47:32.615891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28334 11:47:32.616470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28335 11:47:32.651659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28336 11:47:32.652074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28338 11:47:32.687458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28340 11:47:32.688047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28341 11:47:32.723723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28342 11:47:32.724164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28344 11:47:32.759111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28345 11:47:32.759547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28347 11:47:32.794311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28348 11:47:32.794743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28350 11:47:32.829611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28352 11:47:32.830076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28353 11:47:32.865390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28355 11:47:32.866007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28356 11:47:32.901110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28358 11:47:32.901685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28359 11:47:32.936777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28360 11:47:32.937304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28362 11:47:32.972280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28364 11:47:32.972718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28365 11:47:33.008022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28367 11:47:33.008480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28368 11:47:33.043883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28370 11:47:33.044345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28371 11:47:33.079176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28372 11:47:33.079613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28374 11:47:33.114362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28376 11:47:33.114817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28377 11:47:33.149963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28379 11:47:33.150430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28380 11:47:33.185026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28382 11:47:33.185485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28383 11:47:33.219450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28384 11:47:33.219865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28386 11:47:33.254574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28387 11:47:33.255007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28389 11:47:33.289360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28391 11:47:33.289814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28392 11:47:33.325046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28394 11:47:33.325630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28395 11:47:33.360848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28397 11:47:33.361318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28398 11:47:33.396651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28399 11:47:33.397070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28401 11:47:33.432534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28402 11:47:33.432993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28404 11:47:33.468381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28405 11:47:33.468828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28407 11:47:33.503380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28409 11:47:33.503856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28410 11:47:33.538939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28412 11:47:33.539488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28413 11:47:33.574644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28415 11:47:33.575206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28416 11:47:33.610138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28417 11:47:33.610521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28419 11:47:33.645493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28420 11:47:33.645909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28422 11:47:33.680990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28424 11:47:33.681445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28425 11:47:33.716325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28426 11:47:33.716764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28428 11:47:33.751526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28430 11:47:33.752006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28431 11:47:33.786821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28432 11:47:33.787314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28434 11:47:33.825602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28435 11:47:33.826095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28437 11:47:33.860850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28439 11:47:33.861438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28440 11:47:33.895949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28442 11:47:33.896500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28443 11:47:33.931189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28444 11:47:33.931642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28446 11:47:33.966899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28447 11:47:33.967360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28449 11:47:34.003289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28450 11:47:34.003720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28452 11:47:34.038415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28453 11:47:34.038878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28455 11:47:34.073603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28456 11:47:34.074074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28458 11:47:34.108766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28460 11:47:34.109227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28461 11:47:34.143154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28462 11:47:34.143642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28464 11:47:34.178464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28465 11:47:34.178912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28467 11:47:34.213404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28469 11:47:34.213882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28470 11:47:34.248648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28471 11:47:34.249060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28473 11:47:34.284889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28474 11:47:34.285328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28476 11:47:34.320321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28477 11:47:34.320763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28479 11:47:34.357829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28480 11:47:34.358319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28482 11:47:34.393348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28484 11:47:34.393916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28485 11:47:34.429056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28486 11:47:34.429504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28488 11:47:34.470429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28490 11:47:34.471013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28491 11:47:34.508311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28493 11:47:34.508892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28494 11:47:34.543435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28495 11:47:34.543910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28497 11:47:34.578863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28498 11:47:34.579309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28500 11:47:34.614347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28501 11:47:34.614788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28503 11:47:34.649968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28505 11:47:34.650554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28506 11:47:34.685842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28508 11:47:34.686300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28509 11:47:34.722198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28510 11:47:34.722589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28512 11:47:34.758288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28513 11:47:34.758762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28515 11:47:34.793625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28516 11:47:34.794073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28518 11:47:34.829348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28520 11:47:34.829829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28521 11:47:34.865194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28522 11:47:34.865581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28524 11:47:34.900345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28525 11:47:34.900819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28527 11:47:34.935278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28529 11:47:34.935856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28530 11:47:34.970718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28532 11:47:34.971254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28533 11:47:35.006068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28534 11:47:35.006474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28536 11:47:35.041249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28537 11:47:35.041707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28539 11:47:35.077031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28541 11:47:35.077663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28542 11:47:35.112117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28543 11:47:35.112601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28545 11:47:35.148338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28546 11:47:35.148812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28548 11:47:35.189860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28549 11:47:35.190307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28551 11:47:35.238753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28552 11:47:35.239229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28554 11:47:35.274419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28556 11:47:35.274977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28557 11:47:35.308872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28559 11:47:35.309524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28560 11:47:35.343229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28562 11:47:35.343762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28563 11:47:35.378007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28564 11:47:35.378441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28566 11:47:35.412860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28567 11:47:35.413295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28569 11:47:35.448572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28571 11:47:35.449131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28572 11:47:35.483364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28574 11:47:35.483930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28575 11:47:35.518558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28576 11:47:35.519001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28578 11:47:35.569995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28580 11:47:35.570535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28581 11:47:35.613579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28582 11:47:35.614052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28584 11:47:35.649029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28585 11:47:35.649450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28587 11:47:35.684655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28589 11:47:35.685121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28590 11:47:35.719503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28591 11:47:35.719934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28593 11:47:35.755041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28595 11:47:35.755514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28596 11:47:35.790264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28597 11:47:35.790654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28599 11:47:35.826109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28601 11:47:35.826558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28602 11:47:35.862513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28603 11:47:35.862931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28605 11:47:35.898219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28606 11:47:35.898685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28608 11:47:35.934077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28609 11:47:35.934558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28611 11:47:35.969930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28612 11:47:35.970413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28614 11:47:36.006392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28616 11:47:36.006998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28617 11:47:36.046548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28619 11:47:36.047008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28620 11:47:36.081736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28621 11:47:36.082153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28623 11:47:36.116833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28625 11:47:36.117279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28626 11:47:36.150756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28627 11:47:36.151170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28629 11:47:36.185414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28630 11:47:36.185866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28632 11:47:36.220363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28634 11:47:36.220830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28635 11:47:36.254491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28636 11:47:36.254935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28638 11:47:36.289767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28639 11:47:36.290251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28641 11:47:36.325337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28642 11:47:36.325838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28644 11:47:36.361136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28645 11:47:36.361557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28647 11:47:36.397309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28649 11:47:36.397787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28650 11:47:36.431877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28652 11:47:36.432356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28653 11:47:36.468440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28654 11:47:36.468867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28656 11:47:36.504572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28658 11:47:36.505216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28659 11:47:36.539389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28661 11:47:36.540077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28662 11:47:36.575391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28663 11:47:36.575917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28665 11:47:36.613495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28667 11:47:36.614074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28668 11:47:36.649243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28669 11:47:36.649703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28671 11:47:36.685236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28672 11:47:36.685704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28674 11:47:36.721703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28676 11:47:36.722176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28677 11:47:36.757907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28678 11:47:36.758315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28680 11:47:36.793371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28682 11:47:36.793815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28683 11:47:36.829906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28685 11:47:36.830442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28686 11:47:36.865365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28688 11:47:36.866014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28689 11:47:36.901375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28691 11:47:36.902014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28692 11:47:36.937195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28693 11:47:36.937678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28695 11:47:36.972312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28696 11:47:36.972792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28698 11:47:37.008509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28700 11:47:37.008977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28701 11:47:37.044262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28702 11:47:37.044715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28704 11:47:37.080854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28706 11:47:37.081292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28707 11:47:37.116582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28708 11:47:37.116998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28710 11:47:37.152348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28712 11:47:37.152929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28713 11:47:37.187075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28714 11:47:37.187534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28716 11:47:37.222249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28717 11:47:37.222663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28719 11:47:37.257382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28720 11:47:37.257847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28722 11:47:37.293128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28723 11:47:37.293582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28725 11:47:37.329311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28727 11:47:37.329879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28728 11:47:37.365337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28729 11:47:37.365774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28731 11:47:37.401107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28733 11:47:37.401637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28734 11:47:37.437329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28735 11:47:37.437806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28737 11:47:37.474329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28738 11:47:37.474789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28740 11:47:37.510245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28742 11:47:37.510709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28743 11:47:37.546110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28744 11:47:37.546554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28746 11:47:37.583237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28747 11:47:37.583672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28749 11:47:37.619981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28751 11:47:37.620436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28752 11:47:37.656718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28754 11:47:37.657293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28755 11:47:37.692305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28756 11:47:37.692726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28758 11:47:37.727371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28759 11:47:37.727796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28761 11:47:37.764298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28762 11:47:37.764737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28764 11:47:37.801134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28766 11:47:37.801591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28767 11:47:37.837292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28768 11:47:37.837787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28770 11:47:37.873318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28771 11:47:37.873825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28773 11:47:37.909888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28775 11:47:37.910487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28776 11:47:37.945706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28777 11:47:37.946172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28779 11:47:37.982789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28781 11:47:37.983243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28782 11:47:38.019202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28783 11:47:38.019645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28785 11:47:38.055372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28786 11:47:38.055811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28788 11:47:38.091175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28790 11:47:38.091637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28791 11:47:38.127713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28792 11:47:38.128084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28794 11:47:38.164749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28795 11:47:38.165200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28797 11:47:38.200686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28799 11:47:38.201244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28800 11:47:38.236604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28802 11:47:38.237161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28803 11:47:38.272389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28804 11:47:38.272861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28806 11:47:38.308138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28808 11:47:38.308722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28809 11:47:38.343542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28810 11:47:38.343977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28812 11:47:38.378964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28814 11:47:38.379426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28815 11:47:38.414493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28817 11:47:38.415045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28818 11:47:38.449712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28819 11:47:38.450153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28821 11:47:38.485370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28822 11:47:38.485756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28824 11:47:38.521247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28826 11:47:38.521708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28827 11:47:38.557041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28829 11:47:38.557518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28830 11:47:38.592352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28831 11:47:38.592823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28833 11:47:38.628433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28834 11:47:38.628872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28836 11:47:38.664376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28837 11:47:38.664841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28839 11:47:38.699172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28840 11:47:38.699631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28842 11:47:38.734669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28844 11:47:38.735133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28845 11:47:38.769709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28847 11:47:38.770163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28848 11:47:38.805141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28849 11:47:38.805528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28851 11:47:38.840469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28853 11:47:38.840925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28854 11:47:38.875379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28855 11:47:38.875806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28857 11:47:38.911188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28858 11:47:38.911624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28860 11:47:38.947166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28861 11:47:38.947607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28863 11:47:38.983451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28864 11:47:38.983971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28866 11:47:39.019194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28867 11:47:39.019668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28869 11:47:39.054545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28871 11:47:39.055011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28872 11:47:39.090178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28874 11:47:39.090909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28875 11:47:39.126661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28876 11:47:39.127138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28878 11:47:39.161019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28879 11:47:39.161485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28881 11:47:39.195895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28883 11:47:39.196441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28884 11:47:39.231026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28885 11:47:39.231497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28887 11:47:39.265351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28888 11:47:39.265783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28890 11:47:39.300968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28891 11:47:39.301430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28893 11:47:39.335336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28894 11:47:39.335825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28896 11:47:39.371258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28898 11:47:39.371821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28899 11:47:39.406871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28900 11:47:39.407331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28902 11:47:39.441926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28903 11:47:39.442366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28905 11:47:39.477347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28907 11:47:39.477821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28908 11:47:39.512701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28910 11:47:39.513176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28911 11:47:39.547552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28913 11:47:39.548139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28914 11:47:39.582541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28915 11:47:39.582963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28917 11:47:39.618520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28919 11:47:39.619104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28920 11:47:39.653513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28922 11:47:39.654051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28923 11:47:39.688809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28925 11:47:39.689269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28926 11:47:39.724488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28927 11:47:39.724901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28929 11:47:39.760789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28930 11:47:39.761250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28932 11:47:39.795592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28934 11:47:39.796124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28935 11:47:39.831417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28937 11:47:39.831994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28938 11:47:39.866542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28940 11:47:39.867184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28941 11:47:39.901515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28942 11:47:39.902015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28944 11:47:39.937675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28946 11:47:39.938306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28947 11:47:39.973290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
28948 11:47:39.973691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
28950 11:47:40.008957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
28951 11:47:40.009373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
28953 11:47:40.045581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
28954 11:47:40.046005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
28956 11:47:40.080676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
28957 11:47:40.081097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
28959 11:47:40.116303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
28960 11:47:40.116727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
28962 11:47:40.152707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
28964 11:47:40.153141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
28965 11:47:40.187649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
28967 11:47:40.188079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
28968 11:47:40.222667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
28969 11:47:40.223054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
28971 11:47:40.258744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
28973 11:47:40.259376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
28974 11:47:40.293826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
28975 11:47:40.294308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
28977 11:47:40.329098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
28978 11:47:40.329585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
28980 11:47:40.364260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
28981 11:47:40.364733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
28983 11:47:40.398861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
28984 11:47:40.399302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
28986 11:47:40.435075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
28987 11:47:40.435557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
28989 11:47:40.475499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
28990 11:47:40.475947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
28992 11:47:40.524747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
28993 11:47:40.525214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
28995 11:47:40.564462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
28996 11:47:40.564950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
28998 11:47:40.602245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
28999 11:47:40.602697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
29001 11:47:40.638406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
29003 11:47:40.639040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
29004 11:47:40.693133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
29005 11:47:40.693627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
29007 11:47:40.729078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
29008 11:47:40.729554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
29010 11:47:40.764318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
29012 11:47:40.764756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
29013 11:47:40.799728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
29015 11:47:40.800304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
29016 11:47:40.834875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
29018 11:47:40.835452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
29019 11:47:40.869613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
29020 11:47:40.870082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
29022 11:47:40.904727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
29023 11:47:40.905189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
29025 11:47:40.943292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
29026 11:47:40.943735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
29028 11:47:40.978807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
29029 11:47:40.979239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
29031 11:47:41.015052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
29032 11:47:41.015490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
29034 11:47:41.050738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
29035 11:47:41.051149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
29037 11:47:41.086480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
29039 11:47:41.087059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
29040 11:47:41.121661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
29042 11:47:41.122215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
29043 11:47:41.157641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
29044 11:47:41.158056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
29046 11:47:41.193320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
29048 11:47:41.193789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
29049 11:47:41.229813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
29050 11:47:41.230350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
29052 11:47:41.265832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
29053 11:47:41.266306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
29055 11:47:41.303460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
29057 11:47:41.304127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
29058 11:47:41.343513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
29059 11:47:41.343986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
29061 11:47:41.383532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
29062 11:47:41.383986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
29064 11:47:41.421970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
29066 11:47:41.422429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
29067 11:47:41.460954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
29069 11:47:41.461527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
29070 11:47:41.496772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
29071 11:47:41.497179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
29073 11:47:41.531522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
29075 11:47:41.532067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
29076 11:47:41.566110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
29077 11:47:41.566569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
29079 11:47:41.601460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
29081 11:47:41.602027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
29082 11:47:41.645482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
29083 11:47:41.645979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
29085 11:47:41.684846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
29086 11:47:41.685325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
29088 11:47:41.721916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
29090 11:47:41.722495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
29091 11:47:41.758702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
29092 11:47:41.759142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
29094 11:47:41.797377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
29096 11:47:41.797761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
29097 11:47:41.834066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
29098 11:47:41.834443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
29100 11:47:41.869104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
29102 11:47:41.869675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
29103 11:47:41.904493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
29105 11:47:41.905125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
29106 11:47:41.939466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
29107 11:47:41.939989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
29109 11:47:41.974591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
29111 11:47:41.975057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
29112 11:47:42.011283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
29113 11:47:42.011708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
29115 11:47:42.047049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
29117 11:47:42.047513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
29118 11:47:42.081929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
29119 11:47:42.082363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
29121 11:47:42.118195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
29123 11:47:42.118644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
29124 11:47:42.153689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
29126 11:47:42.154139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
29127 11:47:42.189203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
29129 11:47:42.189787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
29130 11:47:42.224247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
29131 11:47:42.224722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
29133 11:47:42.259399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
29135 11:47:42.259866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
29136 11:47:42.294140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
29137 11:47:42.294550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
29139 11:47:42.329059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
29141 11:47:42.329512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
29142 11:47:42.364243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
29143 11:47:42.364681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
29145 11:47:42.399848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
29147 11:47:42.400320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
29148 11:47:42.434808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
29150 11:47:42.435266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
29151 11:47:42.469736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
29152 11:47:42.470224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
29154 11:47:42.504819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
29155 11:47:42.505308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
29157 11:47:42.540764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
29159 11:47:42.541386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
29160 11:47:42.575509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
29161 11:47:42.575989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
29163 11:47:42.611390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
29165 11:47:42.611962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
29166 11:47:42.646081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
29168 11:47:42.646628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
29169 11:47:42.681143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
29170 11:47:42.681591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
29172 11:47:42.715920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
29174 11:47:42.716506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
29175 11:47:42.751536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
29176 11:47:42.752003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
29178 11:47:42.787411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
29179 11:47:42.787899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
29181 11:47:42.822622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
29183 11:47:42.823235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
29184 11:47:42.856783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
29186 11:47:42.857221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
29187 11:47:42.890192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
29188 11:47:42.890592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
29190 11:47:42.923958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29192 11:47:42.924396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
29193 11:47:42.958004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29195 11:47:42.958534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29196 11:47:42.992872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29197 11:47:42.993321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29199 11:47:43.026613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29200 11:47:43.027054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29202 11:47:43.061241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29204 11:47:43.061879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29205 11:47:43.095943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29207 11:47:43.096628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29208 11:47:43.130333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29210 11:47:43.130801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29211 11:47:43.165122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29213 11:47:43.165700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29214 11:47:43.200414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29215 11:47:43.200861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29217 11:47:43.239743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29219 11:47:43.240366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29220 11:47:43.275602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29221 11:47:43.276060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29223 11:47:43.310152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29225 11:47:43.310761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29226 11:47:43.344323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29228 11:47:43.344929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29229 11:47:43.378382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29230 11:47:43.378807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29232 11:47:43.412880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29233 11:47:43.413357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29235 11:47:43.447295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29237 11:47:43.447845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29238 11:47:43.481944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29239 11:47:43.482404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29241 11:47:43.517129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29242 11:47:43.517608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29244 11:47:43.551534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29245 11:47:43.551977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29247 11:47:43.586269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29248 11:47:43.586709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29250 11:47:43.621942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29251 11:47:43.622326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29253 11:47:43.657017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29254 11:47:43.657490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29256 11:47:43.691708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29258 11:47:43.692167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29259 11:47:43.727348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29260 11:47:43.727773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29262 11:47:43.761970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29263 11:47:43.762407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29265 11:47:43.801216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29267 11:47:43.801806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29268 11:47:43.837322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29270 11:47:43.837973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29271 11:47:43.872334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29272 11:47:43.872803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29274 11:47:43.907302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29276 11:47:43.907867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29277 11:47:43.941429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29279 11:47:43.941991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29280 11:47:43.976467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29281 11:47:43.976898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29283 11:47:44.011074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29284 11:47:44.011548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29286 11:47:44.045699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29288 11:47:44.046235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29289 11:47:44.080913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29290 11:47:44.081371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29292 11:47:44.116738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29293 11:47:44.117187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29295 11:47:44.151517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29296 11:47:44.151984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29298 11:47:44.186678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29300 11:47:44.187220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29301 11:47:44.221098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29302 11:47:44.221555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29304 11:47:44.256089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29306 11:47:44.256654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29307 11:47:44.290354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29308 11:47:44.290775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29310 11:47:44.324812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29311 11:47:44.325249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29313 11:47:44.360549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29314 11:47:44.360999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29316 11:47:44.394779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29317 11:47:44.395231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29319 11:47:44.429087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29321 11:47:44.429705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29322 11:47:44.463965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29324 11:47:44.464592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29325 11:47:44.498832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29327 11:47:44.499503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29328 11:47:44.533757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29329 11:47:44.534230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29331 11:47:44.569015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29332 11:47:44.569461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29334 11:47:44.604189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29336 11:47:44.604949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29337 11:47:44.640206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29338 11:47:44.640687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29340 11:47:44.675040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29342 11:47:44.675610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29343 11:47:44.709636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29344 11:47:44.710134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29346 11:47:44.745279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29348 11:47:44.745855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29349 11:47:44.780552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29350 11:47:44.780986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29352 11:47:44.815311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29353 11:47:44.815724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29355 11:47:44.851019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29357 11:47:44.851555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29358 11:47:44.885617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29359 11:47:44.886073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29361 11:47:44.920843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29363 11:47:44.921275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29364 11:47:44.955428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29366 11:47:44.955883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29367 11:47:44.989812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29368 11:47:44.990271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29370 11:47:45.025464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29371 11:47:45.025919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29373 11:47:45.060412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29374 11:47:45.060848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29376 11:47:45.097456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29377 11:47:45.097789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29379 11:47:45.134461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29380 11:47:45.134804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29382 11:47:45.171435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29383 11:47:45.171788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29385 11:47:45.209055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29386 11:47:45.209398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29388 11:47:45.246449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29389 11:47:45.246825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29391 11:47:45.282508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29392 11:47:45.282924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29394 11:47:45.318305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29395 11:47:45.318708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29397 11:47:45.353393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29399 11:47:45.353851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29400 11:47:45.388840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29401 11:47:45.389272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29403 11:47:45.423778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29404 11:47:45.424204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29406 11:47:45.459439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29407 11:47:45.459882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29409 11:47:45.495348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29410 11:47:45.495796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29412 11:47:45.530821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29413 11:47:45.531231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29415 11:47:45.565808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29416 11:47:45.566239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29418 11:47:45.600870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29420 11:47:45.601316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29421 11:47:45.636986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29423 11:47:45.637555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29424 11:47:45.672578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29426 11:47:45.673130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29427 11:47:45.707216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29429 11:47:45.707668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29430 11:47:45.742455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29432 11:47:45.743045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29433 11:47:45.778314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29434 11:47:45.778767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29436 11:47:45.841598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29438 11:47:45.842078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29439 11:47:45.877598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29441 11:47:45.878197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29442 11:47:45.912628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29444 11:47:45.913373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29445 11:47:45.948491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29446 11:47:45.948893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29448 11:47:45.984547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29449 11:47:45.984962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29451 11:47:46.020592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29452 11:47:46.021023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29454 11:47:46.055610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29455 11:47:46.056036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29457 11:47:46.091431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29459 11:47:46.091909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29460 11:47:46.126442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29461 11:47:46.126890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29463 11:47:46.161621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29464 11:47:46.162117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29466 11:47:46.197711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29467 11:47:46.198128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29469 11:47:46.232462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29470 11:47:46.232868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29472 11:47:46.270760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29473 11:47:46.271209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29475 11:47:46.306180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29477 11:47:46.306638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29478 11:47:46.342717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29480 11:47:46.343178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29481 11:47:46.381462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29483 11:47:46.381928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29484 11:47:46.418918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29485 11:47:46.419360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29487 11:47:46.456610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29489 11:47:46.457167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29490 11:47:46.493013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29492 11:47:46.493570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29493 11:47:46.530340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29495 11:47:46.530961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29496 11:47:46.565669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29498 11:47:46.566108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29499 11:47:46.601338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29501 11:47:46.601787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29502 11:47:46.638404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29503 11:47:46.638797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29505 11:47:46.676512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29507 11:47:46.676968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29508 11:47:46.714519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29510 11:47:46.714983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29511 11:47:46.753112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29513 11:47:46.753564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29514 11:47:46.790434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29515 11:47:46.790826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29517 11:47:46.826611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29519 11:47:46.827041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29520 11:47:46.862294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29522 11:47:46.862940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29523 11:47:46.898066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29525 11:47:46.898623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29526 11:47:46.933218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29527 11:47:46.933710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29529 11:47:46.969909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29530 11:47:46.970345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29532 11:47:47.005321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29533 11:47:47.005779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29535 11:47:47.041551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29537 11:47:47.042185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29538 11:47:47.076666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29539 11:47:47.077157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29541 11:47:47.111412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29542 11:47:47.111845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29544 11:47:47.147044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29546 11:47:47.147676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29547 11:47:47.182906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29548 11:47:47.183285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29550 11:47:47.217996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29551 11:47:47.218488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29553 11:47:47.253335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29554 11:47:47.253827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29556 11:47:47.289095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29558 11:47:47.289740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29559 11:47:47.323890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29561 11:47:47.324485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29562 11:47:47.359412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29563 11:47:47.359873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29565 11:47:47.394026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29566 11:47:47.394484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29568 11:47:47.429037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29570 11:47:47.429578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29571 11:47:47.462952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29572 11:47:47.463372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29574 11:47:47.497671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29576 11:47:47.498159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29577 11:47:47.533072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29579 11:47:47.533537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29580 11:47:47.567202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29581 11:47:47.567638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29583 11:47:47.601293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29585 11:47:47.601891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29586 11:47:47.636272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29587 11:47:47.636750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29589 11:47:47.670928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29590 11:47:47.671399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29592 11:47:47.707915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29594 11:47:47.708355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29595 11:47:47.745416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29596 11:47:47.745841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29598 11:47:47.783010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29600 11:47:47.783641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29601 11:47:47.821053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29602 11:47:47.821546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29604 11:47:47.857918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29605 11:47:47.858392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29607 11:47:47.897167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29609 11:47:47.897833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29610 11:47:47.931087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29612 11:47:47.931650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29613 11:47:47.964919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29614 11:47:47.965359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29616 11:47:48.000803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29617 11:47:48.001203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29619 11:47:48.035430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29621 11:47:48.035895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29622 11:47:48.070056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29624 11:47:48.070514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29625 11:47:48.106902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29627 11:47:48.107359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29628 11:47:48.142128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29630 11:47:48.142581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29631 11:47:48.176891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29632 11:47:48.177322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29634 11:47:48.212580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29635 11:47:48.213042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29637 11:47:48.246873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29638 11:47:48.247332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29640 11:47:48.280949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29641 11:47:48.281420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29643 11:47:48.316817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29644 11:47:48.317273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29646 11:47:48.350973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29648 11:47:48.351530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29649 11:47:48.385700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29650 11:47:48.386180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29652 11:47:48.419129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29653 11:47:48.419662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29655 11:47:48.453295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29657 11:47:48.453864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29658 11:47:48.487145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29660 11:47:48.487689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29661 11:47:48.520994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29663 11:47:48.521563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29664 11:47:48.554496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29665 11:47:48.554909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29667 11:47:48.588943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29669 11:47:48.589384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29670 11:47:48.622575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29671 11:47:48.622967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29673 11:47:48.656693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29675 11:47:48.657126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29676 11:47:48.690518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29678 11:47:48.690965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29679 11:47:48.724592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29680 11:47:48.725045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29682 11:47:48.759073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29683 11:47:48.759532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29685 11:47:48.793119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29686 11:47:48.793588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29688 11:47:48.827542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29689 11:47:48.828006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29691 11:47:48.861886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29692 11:47:48.862357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29694 11:47:48.895664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29695 11:47:48.896129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29697 11:47:48.930629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29699 11:47:48.931183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29700 11:47:48.964555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29701 11:47:48.964950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29703 11:47:48.998455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29705 11:47:48.998898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29706 11:47:49.033423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29708 11:47:49.033998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29709 11:47:49.068256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29711 11:47:49.068876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29712 11:47:49.102391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29714 11:47:49.103004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29715 11:47:49.136977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29716 11:47:49.137455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29718 11:47:49.171449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29719 11:47:49.171937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29721 11:47:49.206989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29722 11:47:49.207426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29724 11:47:49.242023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29726 11:47:49.242499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29727 11:47:49.277925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29728 11:47:49.278370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29730 11:47:49.313180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29732 11:47:49.313797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29733 11:47:49.348124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29735 11:47:49.348688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29736 11:47:49.383458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29738 11:47:49.383989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29739 11:47:49.418619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29741 11:47:49.419161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29742 11:47:49.452901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29743 11:47:49.453335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29745 11:47:49.487232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29746 11:47:49.487670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29748 11:47:49.521481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29749 11:47:49.521979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29751 11:47:49.556263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29752 11:47:49.556695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29754 11:47:49.590526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29755 11:47:49.590994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29757 11:47:49.624127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29758 11:47:49.624610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29760 11:47:49.658145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29762 11:47:49.658773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29763 11:47:49.692383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29764 11:47:49.692853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29766 11:47:49.726344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29768 11:47:49.726805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29769 11:47:49.761172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29771 11:47:49.761629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29772 11:47:49.796506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29773 11:47:49.796892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29775 11:47:49.830318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29777 11:47:49.830909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29778 11:47:49.864584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29779 11:47:49.865035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29781 11:47:49.899151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29783 11:47:49.899690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29784 11:47:49.933661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29785 11:47:49.934111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29787 11:47:49.968789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29789 11:47:49.969337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29790 11:47:50.003660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29792 11:47:50.004215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29793 11:47:50.038737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29795 11:47:50.039275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29796 11:47:50.073242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29797 11:47:50.073675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29799 11:47:50.107689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29800 11:47:50.108108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29802 11:47:50.141873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29803 11:47:50.142314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29805 11:47:50.176996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29807 11:47:50.177459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29808 11:47:50.212688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29810 11:47:50.213144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29811 11:47:50.247066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29812 11:47:50.247475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29814 11:47:50.281881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29815 11:47:50.282368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29817 11:47:50.317973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29819 11:47:50.318611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29820 11:47:50.352317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29821 11:47:50.352798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29823 11:47:50.387008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29824 11:47:50.387508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29826 11:47:50.422296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29828 11:47:50.422938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29829 11:47:50.457657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29831 11:47:50.458281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29832 11:47:50.492874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29833 11:47:50.493356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29835 11:47:50.529277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29836 11:47:50.529689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29838 11:47:50.564388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29839 11:47:50.564826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29841 11:47:50.599357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29843 11:47:50.599826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29844 11:47:50.634370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29846 11:47:50.634831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29847 11:47:50.669168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29848 11:47:50.669659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29850 11:47:50.705020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29852 11:47:50.705591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29853 11:47:50.740493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29855 11:47:50.741055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29856 11:47:50.774282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29857 11:47:50.774753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29859 11:47:50.809193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29861 11:47:50.809861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29862 11:47:50.845076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29864 11:47:50.845679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29865 11:47:50.879226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29867 11:47:50.879789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29868 11:47:50.925685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29870 11:47:50.926057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29871 11:47:50.969183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29873 11:47:50.969709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29874 11:47:51.004416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29876 11:47:51.004778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29877 11:47:51.039230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29878 11:47:51.039671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29880 11:47:51.074380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29881 11:47:51.074794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29883 11:47:51.108756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29885 11:47:51.109187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29886 11:47:51.143252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29888 11:47:51.143705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29889 11:47:51.178712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29890 11:47:51.179213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29892 11:47:51.214910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29894 11:47:51.215489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29895 11:47:51.249816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29896 11:47:51.250232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29898 11:47:51.285314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29900 11:47:51.285779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29901 11:47:51.321334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29903 11:47:51.321807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29904 11:47:51.358855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29906 11:47:51.359302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29907 11:47:51.397389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29908 11:47:51.397883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29910 11:47:51.434453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29912 11:47:51.435084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29913 11:47:51.472566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29915 11:47:51.473031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29916 11:47:51.509870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29918 11:47:51.510342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29919 11:47:51.545026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29921 11:47:51.545596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29922 11:47:51.580591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29923 11:47:51.581058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29925 11:47:51.619649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29926 11:47:51.620132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29928 11:47:51.655385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29930 11:47:51.655956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29931 11:47:51.693120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29932 11:47:51.693566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29934 11:47:51.737311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29936 11:47:51.737878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29937 11:47:51.771943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29939 11:47:51.772410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29940 11:47:51.806463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29942 11:47:51.807105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29943 11:47:51.840892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29945 11:47:51.841337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29946 11:47:51.875427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
29948 11:47:51.876074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29949 11:47:51.910115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
29950 11:47:51.910594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
29952 11:47:51.944544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
29954 11:47:51.945101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
29955 11:47:51.978338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
29957 11:47:51.978900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
29958 11:47:52.012620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
29959 11:47:52.013091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
29961 11:47:52.046235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
29963 11:47:52.046801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
29964 11:47:52.079901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
29966 11:47:52.080526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
29967 11:47:52.113863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
29968 11:47:52.114254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
29970 11:47:52.148452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
29971 11:47:52.148876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
29973 11:47:52.181793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
29974 11:47:52.182265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
29976 11:47:52.216281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
29977 11:47:52.216731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
29979 11:47:52.250141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
29980 11:47:52.250619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
29982 11:47:52.284991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
29983 11:47:52.285441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
29985 11:47:52.319539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
29986 11:47:52.319983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
29988 11:47:52.354234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
29990 11:47:52.354828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
29991 11:47:52.387841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
29993 11:47:52.388428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
29994 11:47:52.422840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
29996 11:47:52.423424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
29997 11:47:52.457252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
29998 11:47:52.457691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
30000 11:47:52.490465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
30001 11:47:52.490947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
30003 11:47:52.524318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
30004 11:47:52.524834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
30006 11:47:52.558257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
30008 11:47:52.558712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
30009 11:47:52.592888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
30010 11:47:52.593279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
30012 11:47:52.626395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
30013 11:47:52.626816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
30015 11:47:52.661097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
30016 11:47:52.661517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
30018 11:47:52.694621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
30019 11:47:52.695036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
30021 11:47:52.729425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
30022 11:47:52.729869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
30024 11:47:52.763744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
30026 11:47:52.764210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
30027 11:47:52.798506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
30028 11:47:52.798944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
30030 11:47:52.832250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
30031 11:47:52.832679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
30033 11:47:52.867312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
30035 11:47:52.867785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
30036 11:47:52.902110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
30037 11:47:52.902555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
30039 11:47:52.936935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
30040 11:47:52.937477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
30042 11:47:52.971510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
30043 11:47:52.971955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
30045 11:47:53.005955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
30047 11:47:53.006390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
30048 11:47:53.040407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
30050 11:47:53.040861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
30051 11:47:53.074692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
30052 11:47:53.075101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
30054 11:47:53.109296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
30055 11:47:53.109687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
30057 11:47:53.144416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
30059 11:47:53.144860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
30060 11:47:53.178363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
30061 11:47:53.178793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
30063 11:47:53.212639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
30064 11:47:53.213119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
30066 11:47:53.246783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
30068 11:47:53.247338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
30069 11:47:53.281016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
30070 11:47:53.281458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
30072 11:47:53.315331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
30073 11:47:53.315748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
30075 11:47:53.349789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
30077 11:47:53.350267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
30078 11:47:53.384338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
30079 11:47:53.384807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
30081 11:47:53.419071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
30082 11:47:53.419507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
30084 11:47:53.454129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
30085 11:47:53.454571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
30087 11:47:53.489088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
30089 11:47:53.489575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
30090 11:47:53.523027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
30091 11:47:53.523471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
30093 11:47:53.558181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
30095 11:47:53.558666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
30096 11:47:53.592489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
30097 11:47:53.592932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
30099 11:47:53.626295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
30100 11:47:53.626728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
30102 11:47:53.660822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
30103 11:47:53.661354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
30105 11:47:53.695120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
30106 11:47:53.695588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
30108 11:47:53.729245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
30109 11:47:53.729691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
30111 11:47:53.763242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
30113 11:47:53.763828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
30114 11:47:53.798005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
30116 11:47:53.798453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
30117 11:47:53.832501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
30119 11:47:53.833068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
30120 11:47:53.866357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
30122 11:47:53.866811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
30123 11:47:53.901520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
30125 11:47:53.902101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
30126 11:47:53.935963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
30128 11:47:53.936541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
30129 11:47:53.971171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
30131 11:47:53.971651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
30132 11:47:54.005171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
30133 11:47:54.005617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
30135 11:47:54.040231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
30136 11:47:54.040675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
30138 11:47:54.075538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
30139 11:47:54.075982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
30141 11:47:54.109857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
30142 11:47:54.110236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
30144 11:47:54.143870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
30146 11:47:54.144532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
30147 11:47:54.178077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
30148 11:47:54.178517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
30150 11:47:54.212433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
30151 11:47:54.212907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
30153 11:47:54.246121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
30154 11:47:54.246606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
30156 11:47:54.280410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
30157 11:47:54.280888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
30159 11:47:54.314184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
30160 11:47:54.314642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
30162 11:47:54.348732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
30163 11:47:54.349173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
30165 11:47:54.382731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
30167 11:47:54.383187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
30168 11:47:54.416897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
30170 11:47:54.417386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
30171 11:47:54.450493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
30173 11:47:54.450951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
30174 11:47:54.485503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
30175 11:47:54.485976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
30177 11:47:54.525550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
30178 11:47:54.525980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
30180 11:47:54.559862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
30182 11:47:54.560330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
30183 11:47:54.593795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
30185 11:47:54.594257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
30186 11:47:54.627786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
30188 11:47:54.628250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
30189 11:47:54.661515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
30190 11:47:54.661967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
30192 11:47:54.695680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30194 11:47:54.696142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30195 11:47:54.729273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30196 11:47:54.729683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30198 11:47:54.762988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30199 11:47:54.763428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30201 11:47:54.797786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30202 11:47:54.798232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30204 11:47:54.832436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30206 11:47:54.832913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30207 11:47:54.866479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30208 11:47:54.866912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30210 11:47:54.900950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30211 11:47:54.901394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30213 11:47:54.935945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30215 11:47:54.936385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30216 11:47:54.970618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30217 11:47:54.971042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30219 11:47:55.006009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30220 11:47:55.006425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30222 11:47:55.040971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30224 11:47:55.041435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30225 11:47:55.074663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30227 11:47:55.075113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30228 11:47:55.109314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30229 11:47:55.109767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30231 11:47:55.144844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30232 11:47:55.145330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30234 11:47:55.179290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30235 11:47:55.179810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30237 11:47:55.213748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30238 11:47:55.214225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30240 11:47:55.248638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30241 11:47:55.249115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30243 11:47:55.282765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30244 11:47:55.283238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30246 11:47:55.318382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30247 11:47:55.318878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30249 11:47:55.353134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30250 11:47:55.353583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30252 11:47:55.387856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30254 11:47:55.388469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30255 11:47:55.422120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30256 11:47:55.422584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30258 11:47:55.456148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30259 11:47:55.456584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30261 11:47:55.490247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30263 11:47:55.490879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30264 11:47:55.524702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30266 11:47:55.525283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30267 11:47:55.558500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30268 11:47:55.558955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30270 11:47:55.592727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30272 11:47:55.593277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30273 11:47:55.627959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30275 11:47:55.628418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30276 11:47:55.662771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30277 11:47:55.663180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30279 11:47:55.697498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30281 11:47:55.698075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30282 11:47:55.732646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30284 11:47:55.733199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30285 11:47:55.767129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30287 11:47:55.767595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30288 11:47:55.801854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30290 11:47:55.802425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30291 11:47:55.837289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30293 11:47:55.837763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30294 11:47:55.872489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30295 11:47:55.872923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30297 11:47:55.907846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30299 11:47:55.908308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30300 11:47:55.942405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30301 11:47:55.942816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30303 11:47:55.977562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30305 11:47:55.978019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30306 11:47:56.013047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30307 11:47:56.013484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30309 11:47:56.078978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30310 11:47:56.079369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30312 11:47:56.114793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30314 11:47:56.115247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30315 11:47:56.150101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30316 11:47:56.150526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30318 11:47:56.184061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30319 11:47:56.184538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30321 11:47:56.217830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30323 11:47:56.218396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30324 11:47:56.252585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30326 11:47:56.253175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30327 11:47:56.285888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30329 11:47:56.286448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30330 11:47:56.321023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30332 11:47:56.321518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30333 11:47:56.355273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30334 11:47:56.355748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30336 11:47:56.390094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30337 11:47:56.390514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30339 11:47:56.424591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30340 11:47:56.424938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30342 11:47:56.458401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30343 11:47:56.458817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30345 11:47:56.493339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30346 11:47:56.493821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30348 11:47:56.528487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30350 11:47:56.528916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30351 11:47:56.563479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30353 11:47:56.564161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30354 11:47:56.598794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30355 11:47:56.599240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30357 11:47:56.633333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30358 11:47:56.633784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30360 11:47:56.672580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30361 11:47:56.673024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30363 11:47:56.708517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30365 11:47:56.709085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30366 11:47:56.743012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30368 11:47:56.743663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30369 11:47:56.777513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30370 11:47:56.777962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30372 11:47:56.812661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30373 11:47:56.813104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30375 11:47:56.848390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30377 11:47:56.848848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30378 11:47:56.882333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30379 11:47:56.882749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30381 11:47:56.916988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30383 11:47:56.917448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30384 11:47:56.950134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30385 11:47:56.950585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30387 11:47:56.983784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30389 11:47:56.984413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30390 11:47:57.017729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30391 11:47:57.018199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30393 11:47:57.052755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30395 11:47:57.053216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30396 11:47:57.086335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30397 11:47:57.086773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30399 11:47:57.120895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30401 11:47:57.121392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30402 11:47:57.154716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30404 11:47:57.155176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30405 11:47:57.189174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30406 11:47:57.189636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30408 11:47:57.223960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30410 11:47:57.224585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30411 11:47:57.258672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30413 11:47:57.259287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30414 11:47:57.292529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30415 11:47:57.292997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30417 11:47:57.326206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30419 11:47:57.326764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30420 11:47:57.360505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30421 11:47:57.360996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30423 11:47:57.394653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30424 11:47:57.395112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30426 11:47:57.429643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30427 11:47:57.430106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30429 11:47:57.463796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30431 11:47:57.464363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30432 11:47:57.499720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30434 11:47:57.500277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30435 11:47:57.534796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30436 11:47:57.535277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30438 11:47:57.569334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30440 11:47:57.569912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30441 11:47:57.604646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30443 11:47:57.605230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30444 11:47:57.639185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30445 11:47:57.639649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30447 11:47:57.673448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30449 11:47:57.674082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30450 11:47:57.708567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30452 11:47:57.709189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30453 11:47:57.742267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30455 11:47:57.742850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30456 11:47:57.776089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30457 11:47:57.776532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30459 11:47:57.779072 <47>[ 304.886943] systemd-journald[105]: Sent WATCHDOG=1 notification.
30460 11:47:57.815395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30462 11:47:57.815862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30463 11:47:57.849451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30464 11:47:57.849888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30466 11:47:57.884718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30467 11:47:57.885217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30469 11:47:57.918316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30470 11:47:57.918783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30472 11:47:57.952321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30473 11:47:57.952791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30475 11:47:57.986262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30476 11:47:57.986711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30478 11:47:58.020166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30479 11:47:58.020671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30481 11:47:58.054557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30482 11:47:58.054942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30484 11:47:58.089063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30485 11:47:58.089520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30487 11:47:58.122884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30489 11:47:58.123454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30490 11:47:58.157585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30491 11:47:58.158036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30493 11:47:58.192778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30494 11:47:58.193177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30496 11:47:58.227235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30498 11:47:58.227801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30499 11:47:58.261363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30500 11:47:58.261817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30502 11:47:58.295205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30503 11:47:58.295645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30505 11:47:58.332893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30506 11:47:58.333327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30508 11:47:58.369454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30509 11:47:58.369839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30511 11:47:58.404857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30513 11:47:58.405223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30514 11:47:58.441170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30516 11:47:58.441526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30517 11:47:58.476539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30519 11:47:58.477028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30520 11:47:58.510963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30521 11:47:58.511454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30523 11:47:58.546326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30524 11:47:58.546806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30526 11:47:58.581285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30528 11:47:58.581849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30529 11:47:58.616008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30531 11:47:58.616487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30532 11:47:58.650650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30533 11:47:58.651118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30535 11:47:58.685401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30537 11:47:58.685887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30538 11:47:58.720386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30540 11:47:58.720940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30541 11:47:58.754704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30543 11:47:58.755262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30544 11:47:58.788865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30546 11:47:58.789427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30547 11:47:58.822714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30549 11:47:58.823287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30550 11:47:58.856818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30551 11:47:58.857253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30553 11:47:58.890544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30554 11:47:58.890983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30556 11:47:58.924514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30557 11:47:58.924955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30559 11:47:58.958424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30561 11:47:58.959063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30562 11:47:58.993134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30563 11:47:58.993622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30565 11:47:59.027250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30566 11:47:59.027753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30568 11:47:59.062029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30570 11:47:59.062657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30571 11:47:59.097086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30573 11:47:59.097544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30574 11:47:59.132550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30576 11:47:59.132996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30577 11:47:59.167020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30578 11:47:59.167438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30580 11:47:59.201722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30582 11:47:59.202349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30583 11:47:59.236815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30585 11:47:59.237453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30586 11:47:59.272680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30588 11:47:59.273139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30589 11:47:59.307338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30590 11:47:59.307828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30592 11:47:59.341814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30594 11:47:59.342374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30595 11:47:59.377150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30596 11:47:59.377626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30598 11:47:59.411945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30600 11:47:59.412534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30601 11:47:59.446091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30603 11:47:59.446723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30604 11:47:59.480999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30606 11:47:59.481463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30607 11:47:59.514492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30608 11:47:59.514963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30610 11:47:59.548845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30611 11:47:59.549318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30613 11:47:59.582586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30615 11:47:59.583224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30616 11:47:59.617228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30617 11:47:59.617703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30619 11:47:59.651922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30621 11:47:59.652601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30622 11:47:59.686517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30624 11:47:59.687149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30625 11:47:59.721569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30627 11:47:59.722035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30628 11:47:59.757146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30629 11:47:59.757603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30631 11:47:59.791015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30633 11:47:59.791572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30634 11:47:59.824846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30636 11:47:59.825407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30637 11:47:59.858274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30638 11:47:59.858733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30640 11:47:59.892495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30642 11:47:59.892927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30643 11:47:59.926108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30644 11:47:59.926541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30646 11:47:59.960402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30647 11:47:59.960852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30649 11:47:59.995122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30651 11:47:59.995665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30652 11:48:00.028833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30653 11:48:00.029307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30655 11:48:00.063113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30656 11:48:00.063522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30658 11:48:00.098711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30659 11:48:00.099173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30661 11:48:00.132568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30662 11:48:00.133044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30664 11:48:00.166472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30665 11:48:00.166938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30667 11:48:00.200784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30669 11:48:00.201246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30670 11:48:00.234684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30671 11:48:00.235151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30673 11:48:00.269083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30674 11:48:00.269553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30676 11:48:00.302619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30678 11:48:00.303244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30679 11:48:00.336266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30680 11:48:00.336732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30682 11:48:00.370995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30683 11:48:00.371448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30685 11:48:00.405058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30686 11:48:00.405495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30688 11:48:00.440439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30690 11:48:00.441005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30691 11:48:00.475271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30693 11:48:00.475825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30694 11:48:00.509972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30696 11:48:00.510535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30697 11:48:00.544775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30699 11:48:00.545342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30700 11:48:00.579598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30701 11:48:00.580039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30703 11:48:00.614419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30705 11:48:00.614959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30706 11:48:00.649511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30708 11:48:00.650144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30709 11:48:00.684727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30711 11:48:00.685354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30712 11:48:00.718405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30713 11:48:00.718867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30715 11:48:00.753432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30716 11:48:00.753914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30718 11:48:00.788363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30719 11:48:00.788814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30721 11:48:00.822750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30722 11:48:00.823222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30724 11:48:00.857198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30726 11:48:00.857847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30727 11:48:00.891579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30728 11:48:00.892005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30730 11:48:00.926265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30731 11:48:00.926660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30733 11:48:00.961071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30734 11:48:00.961503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30736 11:48:00.996012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30738 11:48:00.996472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30739 11:48:01.029941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30741 11:48:01.030477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30742 11:48:01.064183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30743 11:48:01.064641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30745 11:48:01.099084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30746 11:48:01.099525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30748 11:48:01.133804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30749 11:48:01.134289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30751 11:48:01.191356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30752 11:48:01.191916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30754 11:48:01.226357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30756 11:48:01.226819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30757 11:48:01.260673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30759 11:48:01.261242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30760 11:48:01.294663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30761 11:48:01.295128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30763 11:48:01.330628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30765 11:48:01.331273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30766 11:48:01.366055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30768 11:48:01.366510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30769 11:48:01.403816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30771 11:48:01.404299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30772 11:48:01.438909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30773 11:48:01.439393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30775 11:48:01.474061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30776 11:48:01.474532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30778 11:48:01.510050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30779 11:48:01.510521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30781 11:48:01.545844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30783 11:48:01.546323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30784 11:48:01.581181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30786 11:48:01.581653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30787 11:48:01.616381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30789 11:48:01.616842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30790 11:48:01.653355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30791 11:48:01.653771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30793 11:48:01.689397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30794 11:48:01.689806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30796 11:48:01.726584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30798 11:48:01.727039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30799 11:48:01.763527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30801 11:48:01.763992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30802 11:48:01.800564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30803 11:48:01.801002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30805 11:48:01.836627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30806 11:48:01.837045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30808 11:48:01.871022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30809 11:48:01.871441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30811 11:48:01.905831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30812 11:48:01.906308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30814 11:48:01.940634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30815 11:48:01.941089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30817 11:48:01.974475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30818 11:48:01.974899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30820 11:48:02.009415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30822 11:48:02.009879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30823 11:48:02.043448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30824 11:48:02.043839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30826 11:48:02.077550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30827 11:48:02.078009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30829 11:48:02.112524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30830 11:48:02.112987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30832 11:48:02.146940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30834 11:48:02.147537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30835 11:48:02.182048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30836 11:48:02.182487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30838 11:48:02.216530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30840 11:48:02.216993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30841 11:48:02.250819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30842 11:48:02.251277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30844 11:48:02.285109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30846 11:48:02.285677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30847 11:48:02.319161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30848 11:48:02.319635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30850 11:48:02.354704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30851 11:48:02.355173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30853 11:48:02.389587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30855 11:48:02.390150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30856 11:48:02.424671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30857 11:48:02.425147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30859 11:48:02.459204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30861 11:48:02.459772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30862 11:48:02.493950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30863 11:48:02.494383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30865 11:48:02.528639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30866 11:48:02.529097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30868 11:48:02.563209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30870 11:48:02.563836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30871 11:48:02.597711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30873 11:48:02.598175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30874 11:48:02.632892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30875 11:48:02.633340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30877 11:48:02.668420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30879 11:48:02.669065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30880 11:48:02.703987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30882 11:48:02.704464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30883 11:48:02.739723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30885 11:48:02.740210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30886 11:48:02.775335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30887 11:48:02.775779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30889 11:48:02.810936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30890 11:48:02.811360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30892 11:48:02.846207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30894 11:48:02.846665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30895 11:48:02.881355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30896 11:48:02.881769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30898 11:48:02.917007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30899 11:48:02.917417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30901 11:48:02.952335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30903 11:48:02.952795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30904 11:48:02.989533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30905 11:48:02.989949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30907 11:48:03.025848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30908 11:48:03.026256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30910 11:48:03.060819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30912 11:48:03.061264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30913 11:48:03.096385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30915 11:48:03.096837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30916 11:48:03.131450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30917 11:48:03.131869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30919 11:48:03.166876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30921 11:48:03.167346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30922 11:48:03.201876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30923 11:48:03.202288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30925 11:48:03.237173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30927 11:48:03.237843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30928 11:48:03.271782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30930 11:48:03.272420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30931 11:48:03.306976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30933 11:48:03.307449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30934 11:48:03.342112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30935 11:48:03.342533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30937 11:48:03.376539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30938 11:48:03.376977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30940 11:48:03.411236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30942 11:48:03.411831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30943 11:48:03.445700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30945 11:48:03.446132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30946 11:48:03.485516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
30947 11:48:03.485923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30949 11:48:03.526443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
30951 11:48:03.526915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
30952 11:48:03.561885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
30954 11:48:03.562352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
30955 11:48:03.596605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
30956 11:48:03.597074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
30958 11:48:03.631729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
30960 11:48:03.632350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
30961 11:48:03.667355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
30962 11:48:03.667846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
30964 11:48:03.701957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
30965 11:48:03.702429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
30967 11:48:03.736942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
30969 11:48:03.737528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
30970 11:48:03.772286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
30971 11:48:03.772736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
30973 11:48:03.806859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
30975 11:48:03.807431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
30976 11:48:03.841378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
30977 11:48:03.841812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
30979 11:48:03.876533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
30980 11:48:03.876937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
30982 11:48:03.911150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
30984 11:48:03.911727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
30985 11:48:03.945776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
30987 11:48:03.946266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
30988 11:48:03.981663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
30990 11:48:03.982129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
30991 11:48:04.016372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
30992 11:48:04.016818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
30994 11:48:04.051216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
30996 11:48:04.051678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
30997 11:48:04.086164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
30999 11:48:04.086634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
31000 11:48:04.121144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
31002 11:48:04.121771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
31003 11:48:04.157088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
31005 11:48:04.157723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
31006 11:48:04.192595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
31007 11:48:04.193053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
31009 11:48:04.227197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
31011 11:48:04.227732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
31012 11:48:04.262137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
31013 11:48:04.262554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
31015 11:48:04.297322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
31017 11:48:04.297786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
31018 11:48:04.332954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
31019 11:48:04.333441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
31021 11:48:04.368614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
31023 11:48:04.369251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
31024 11:48:04.403499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
31026 11:48:04.404149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
31027 11:48:04.438692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
31028 11:48:04.439151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
31030 11:48:04.473322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
31031 11:48:04.473687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
31033 11:48:04.509032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
31035 11:48:04.509484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
31036 11:48:04.543868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
31038 11:48:04.544344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
31039 11:48:04.578345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
31041 11:48:04.578809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
31042 11:48:04.613225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
31043 11:48:04.613639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
31045 11:48:04.647265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
31046 11:48:04.647707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
31048 11:48:04.682001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
31049 11:48:04.682412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
31051 11:48:04.716531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
31052 11:48:04.716969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
31054 11:48:04.750846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
31056 11:48:04.751322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
31057 11:48:04.784844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
31058 11:48:04.785275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
31060 11:48:04.819524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
31061 11:48:04.819942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
31063 11:48:04.854303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
31064 11:48:04.854761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
31066 11:48:04.889275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
31067 11:48:04.889681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
31069 11:48:04.924574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
31071 11:48:04.925023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
31072 11:48:04.959149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
31073 11:48:04.959588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
31075 11:48:04.993854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
31076 11:48:04.994286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
31078 11:48:05.028928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
31080 11:48:05.029387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
31081 11:48:05.062850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
31082 11:48:05.063283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
31084 11:48:05.097923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
31085 11:48:05.098359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
31087 11:48:05.132973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
31088 11:48:05.133410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
31090 11:48:05.167712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
31092 11:48:05.168144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
31093 11:48:05.202414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
31094 11:48:05.202834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
31096 11:48:05.237099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
31097 11:48:05.237542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
31099 11:48:05.272759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
31101 11:48:05.273392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
31102 11:48:05.306924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
31103 11:48:05.307338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
31105 11:48:05.342560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
31107 11:48:05.343211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
31108 11:48:05.376795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
31109 11:48:05.377233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
31111 11:48:05.411082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
31112 11:48:05.411535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
31114 11:48:05.445340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
31116 11:48:05.445834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
31117 11:48:05.479850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
31119 11:48:05.480301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
31120 11:48:05.515111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
31121 11:48:05.515555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
31123 11:48:05.550116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
31124 11:48:05.550554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
31126 11:48:05.585610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
31127 11:48:05.586061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
31129 11:48:05.620473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
31130 11:48:05.620918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
31132 11:48:05.655032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
31133 11:48:05.655456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
31135 11:48:05.690279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
31136 11:48:05.690733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
31138 11:48:05.726001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
31140 11:48:05.726632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
31141 11:48:05.760955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
31143 11:48:05.761593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
31144 11:48:05.796301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
31146 11:48:05.796938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
31147 11:48:05.831024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
31148 11:48:05.831498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
31150 11:48:05.869690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
31152 11:48:05.870250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
31153 11:48:05.905180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
31154 11:48:05.905659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
31156 11:48:05.940116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
31157 11:48:05.940603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
31159 11:48:05.974967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
31161 11:48:05.975675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
31162 11:48:06.010814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
31164 11:48:06.011362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
31165 11:48:06.045952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
31167 11:48:06.046499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
31168 11:48:06.081243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
31169 11:48:06.081705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
31171 11:48:06.117029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
31172 11:48:06.117509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
31174 11:48:06.151992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
31176 11:48:06.152459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
31177 11:48:06.186761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
31178 11:48:06.187237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
31180 11:48:06.222187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
31181 11:48:06.222616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
31183 11:48:06.257014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
31184 11:48:06.257489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
31186 11:48:06.319522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
31188 11:48:06.319995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
31189 11:48:06.356323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
31191 11:48:06.356862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
31192 11:48:06.391723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31194 11:48:06.392302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31195 11:48:06.428945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31196 11:48:06.429444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31198 11:48:06.465245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31199 11:48:06.465706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31201 11:48:06.502435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31202 11:48:06.502888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31204 11:48:06.538300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31206 11:48:06.538857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31207 11:48:06.574222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31208 11:48:06.574658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31210 11:48:06.609923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31211 11:48:06.610409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31213 11:48:06.646010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31214 11:48:06.646427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31216 11:48:06.681839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31217 11:48:06.682276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31219 11:48:06.717661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31220 11:48:06.718095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31222 11:48:06.753956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31224 11:48:06.754526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31225 11:48:06.789989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31227 11:48:06.790465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31228 11:48:06.825940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31230 11:48:06.826400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31231 11:48:06.861990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31232 11:48:06.862365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31234 11:48:06.898508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31235 11:48:06.898944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31237 11:48:06.934628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31238 11:48:06.935080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31240 11:48:06.970774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31241 11:48:06.971202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31243 11:48:07.005897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31244 11:48:07.006337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31246 11:48:07.041380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31247 11:48:07.041796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31249 11:48:07.077130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31250 11:48:07.077565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31252 11:48:07.112706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31254 11:48:07.113287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31255 11:48:07.148539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31257 11:48:07.149115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31258 11:48:07.184520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31259 11:48:07.184957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31261 11:48:07.219755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31262 11:48:07.220198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31264 11:48:07.255424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31265 11:48:07.255853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31267 11:48:07.291351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31268 11:48:07.291804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31270 11:48:07.326859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31271 11:48:07.327335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31273 11:48:07.362445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31275 11:48:07.363006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31276 11:48:07.398796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31278 11:48:07.399352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31279 11:48:07.433958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31280 11:48:07.434419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31282 11:48:07.469484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31284 11:48:07.470039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31285 11:48:07.504667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31287 11:48:07.505185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31288 11:48:07.539460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31290 11:48:07.539986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31291 11:48:07.574907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31293 11:48:07.575428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31294 11:48:07.609713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31296 11:48:07.610255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31297 11:48:07.644835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31299 11:48:07.645340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31300 11:48:07.679591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31301 11:48:07.680179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31303 11:48:07.715231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31304 11:48:07.715740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31306 11:48:07.751175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31307 11:48:07.751689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31309 11:48:07.787143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31311 11:48:07.787779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31312 11:48:07.822328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31314 11:48:07.822904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31315 11:48:07.858246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31317 11:48:07.858715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31318 11:48:07.894591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31319 11:48:07.895030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31321 11:48:07.935583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31322 11:48:07.936018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31324 11:48:07.971592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31326 11:48:07.972062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31327 11:48:08.007549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31328 11:48:08.007974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31330 11:48:08.045289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31331 11:48:08.045682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31333 11:48:08.080805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31335 11:48:08.081267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31336 11:48:08.115856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31338 11:48:08.116266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31339 11:48:08.151211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31340 11:48:08.151624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31342 11:48:08.187651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31343 11:48:08.188095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31345 11:48:08.223360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31346 11:48:08.223789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31348 11:48:08.258432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31349 11:48:08.258814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31351 11:48:08.294372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31352 11:48:08.294833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31354 11:48:08.330766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31356 11:48:08.331342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31357 11:48:08.366390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31358 11:48:08.366870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31360 11:48:08.402148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31362 11:48:08.402613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31363 11:48:08.438003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31364 11:48:08.438468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31366 11:48:08.473715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31367 11:48:08.474136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31369 11:48:08.509220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31370 11:48:08.509702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31372 11:48:08.545236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31374 11:48:08.545886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31375 11:48:08.580554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31376 11:48:08.581033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31378 11:48:08.615431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31380 11:48:08.616079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31381 11:48:08.650292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31382 11:48:08.650744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31384 11:48:08.685290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31386 11:48:08.685869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31387 11:48:08.720711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31388 11:48:08.721158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31390 11:48:08.759037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31391 11:48:08.759481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31393 11:48:08.793817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31394 11:48:08.794255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31396 11:48:08.828993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31398 11:48:08.829505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31399 11:48:08.863549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31401 11:48:08.864062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31402 11:48:08.898295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31403 11:48:08.898727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31405 11:48:08.933375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31407 11:48:08.933979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31408 11:48:08.968376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31410 11:48:08.968966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31411 11:48:09.003664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31412 11:48:09.004078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31414 11:48:09.039211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31415 11:48:09.039671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31417 11:48:09.074992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31418 11:48:09.075403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31420 11:48:09.111234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31421 11:48:09.111655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31423 11:48:09.147478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31424 11:48:09.147903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31426 11:48:09.183948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31428 11:48:09.184415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31429 11:48:09.218672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31431 11:48:09.219126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31432 11:48:09.253671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31434 11:48:09.254131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31435 11:48:09.289020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31437 11:48:09.289487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31438 11:48:09.324133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31439 11:48:09.324574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31441 11:48:09.361014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31443 11:48:09.361486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31444 11:48:09.397217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31446 11:48:09.397812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31447 11:48:09.432993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31448 11:48:09.433413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31450 11:48:09.469853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31452 11:48:09.470526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31453 11:48:09.505399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31454 11:48:09.505881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31456 11:48:09.541725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31457 11:48:09.542185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31459 11:48:09.576812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31460 11:48:09.577279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31462 11:48:09.612859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31463 11:48:09.613306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31465 11:48:09.648408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31466 11:48:09.648810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31468 11:48:09.684444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31470 11:48:09.684957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31471 11:48:09.719407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31473 11:48:09.719907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31474 11:48:09.754430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31476 11:48:09.754915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31477 11:48:09.789466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31478 11:48:09.789913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31480 11:48:09.824834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31482 11:48:09.825420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31483 11:48:09.861112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31484 11:48:09.861527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31486 11:48:09.896714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31487 11:48:09.897149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31489 11:48:09.932371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31490 11:48:09.932786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31492 11:48:09.968384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31493 11:48:09.968823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31495 11:48:10.003688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31496 11:48:10.004111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31498 11:48:10.039584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31499 11:48:10.040067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31501 11:48:10.076260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31502 11:48:10.076738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31504 11:48:10.111418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31505 11:48:10.111889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31507 11:48:10.147290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31509 11:48:10.147875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31510 11:48:10.183273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31511 11:48:10.183742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31513 11:48:10.218612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31514 11:48:10.219088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31516 11:48:10.254981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31517 11:48:10.255444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31519 11:48:10.291553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31521 11:48:10.292212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31522 11:48:10.328840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31524 11:48:10.329405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31525 11:48:10.365059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31526 11:48:10.365532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31528 11:48:10.401292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31529 11:48:10.401771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31531 11:48:10.437580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31532 11:48:10.438044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31534 11:48:10.473464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31535 11:48:10.473933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31537 11:48:10.509709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31538 11:48:10.510167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31540 11:48:10.545767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31542 11:48:10.546313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31543 11:48:10.582385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31545 11:48:10.582843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31546 11:48:10.619057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31547 11:48:10.619475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31549 11:48:10.655508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31551 11:48:10.655974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31552 11:48:10.702094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31553 11:48:10.702515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31555 11:48:10.739341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31556 11:48:10.739843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31558 11:48:10.775061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31559 11:48:10.775543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31561 11:48:10.810335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31562 11:48:10.810812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31564 11:48:10.847176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31565 11:48:10.847685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31567 11:48:10.882883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31568 11:48:10.883342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31570 11:48:10.918468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31571 11:48:10.918942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31573 11:48:10.954162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31575 11:48:10.954706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31576 11:48:10.989384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31577 11:48:10.989824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31579 11:48:11.025415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31581 11:48:11.025984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31582 11:48:11.060918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31583 11:48:11.061373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31585 11:48:11.096365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31587 11:48:11.096923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31588 11:48:11.131140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31589 11:48:11.131631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31591 11:48:11.166888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31592 11:48:11.167376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31594 11:48:11.202540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31595 11:48:11.202997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31597 11:48:11.238178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31598 11:48:11.238647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31600 11:48:11.273717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31601 11:48:11.274178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31603 11:48:11.309534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31605 11:48:11.310063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31606 11:48:11.345726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31607 11:48:11.346170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31609 11:48:11.381883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31610 11:48:11.382354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31612 11:48:11.438587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31614 11:48:11.439180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31615 11:48:11.473620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31616 11:48:11.474065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31618 11:48:11.512773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31619 11:48:11.513229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31621 11:48:11.548936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31622 11:48:11.549514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31624 11:48:11.589447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31626 11:48:11.590100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31627 11:48:11.630612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31628 11:48:11.630988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31630 11:48:11.666742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31631 11:48:11.667112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31633 11:48:11.702433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31634 11:48:11.702884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31636 11:48:11.741104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31637 11:48:11.741581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31639 11:48:11.776126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31640 11:48:11.776591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31642 11:48:11.812201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31643 11:48:11.812668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31645 11:48:11.847177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31647 11:48:11.847717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31648 11:48:11.881503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31649 11:48:11.881978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31651 11:48:11.916815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31652 11:48:11.917280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31654 11:48:11.952864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31655 11:48:11.953328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31657 11:48:11.988515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31659 11:48:11.988978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31660 11:48:12.023912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31662 11:48:12.024374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31663 11:48:12.059077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31664 11:48:12.059487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31666 11:48:12.093907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31667 11:48:12.094373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31669 11:48:12.129291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31670 11:48:12.129741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31672 11:48:12.165069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31673 11:48:12.165486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31675 11:48:12.201364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31676 11:48:12.201779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31678 11:48:12.236981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31680 11:48:12.237430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31681 11:48:12.272233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31682 11:48:12.272647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31684 11:48:12.306794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31685 11:48:12.307280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31687 11:48:12.341696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31689 11:48:12.342201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31690 11:48:12.376735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31691 11:48:12.377139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31693 11:48:12.411183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31694 11:48:12.411584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31696 11:48:12.446401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31698 11:48:12.446818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31699 11:48:12.481303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31701 11:48:12.481908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31702 11:48:12.516007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31704 11:48:12.516637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31705 11:48:12.561808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31707 11:48:12.562410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31708 11:48:12.597222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31710 11:48:12.597842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31711 11:48:12.633740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31712 11:48:12.634213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31714 11:48:12.670297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31716 11:48:12.670775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31717 11:48:12.705383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31719 11:48:12.705967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31720 11:48:12.740447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31721 11:48:12.740863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31723 11:48:12.775034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31725 11:48:12.775487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31726 11:48:12.810907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31727 11:48:12.811332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31729 11:48:12.845914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31731 11:48:12.846551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31732 11:48:12.881578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31733 11:48:12.882141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31735 11:48:12.916647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31736 11:48:12.917135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31738 11:48:12.954440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31739 11:48:12.954880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31741 11:48:12.989822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31742 11:48:12.990212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31744 11:48:13.026123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31746 11:48:13.026674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31747 11:48:13.061402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31749 11:48:13.061942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31750 11:48:13.097842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31752 11:48:13.098387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31753 11:48:13.133156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31754 11:48:13.133587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31756 11:48:13.169693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31758 11:48:13.170288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31759 11:48:13.204674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31760 11:48:13.205053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31762 11:48:13.240782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31764 11:48:13.241260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31765 11:48:13.275636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31767 11:48:13.276265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31768 11:48:13.312676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31770 11:48:13.313232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31771 11:48:13.352964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31773 11:48:13.353666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31774 11:48:13.388581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31776 11:48:13.389113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31777 11:48:13.423279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31778 11:48:13.423739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31780 11:48:13.459470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31782 11:48:13.460045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31783 11:48:13.494508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31784 11:48:13.494932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31786 11:48:13.530103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31787 11:48:13.530531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31789 11:48:13.565386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31790 11:48:13.565819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31792 11:48:13.600737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31793 11:48:13.601148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31795 11:48:13.636664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31796 11:48:13.637123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31798 11:48:13.672813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31799 11:48:13.673274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31801 11:48:13.707608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31802 11:48:13.708077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31804 11:48:13.743083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31805 11:48:13.743531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31807 11:48:13.778410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31808 11:48:13.778867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31810 11:48:13.814694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31811 11:48:13.815172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31813 11:48:13.849923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31814 11:48:13.850369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31816 11:48:13.885145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31817 11:48:13.885579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31819 11:48:13.919607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31821 11:48:13.920176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31822 11:48:13.954885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31823 11:48:13.955293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31825 11:48:13.989904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31826 11:48:13.990308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31828 11:48:14.025061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31830 11:48:14.025609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31831 11:48:14.059932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31833 11:48:14.060486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31834 11:48:14.097061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31835 11:48:14.097504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31837 11:48:14.132964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31839 11:48:14.133410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31840 11:48:14.169697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31841 11:48:14.170115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31843 11:48:14.205399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31844 11:48:14.205818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31846 11:48:14.241924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31848 11:48:14.242393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31849 11:48:14.277448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31851 11:48:14.277914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31852 11:48:14.314983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31853 11:48:14.315352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31855 11:48:14.350215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31856 11:48:14.350637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31858 11:48:14.386689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31859 11:48:14.387108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31861 11:48:14.422818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31862 11:48:14.423249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31864 11:48:14.458905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31865 11:48:14.459343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31867 11:48:14.495492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31869 11:48:14.496151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31870 11:48:14.532816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31871 11:48:14.533294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31873 11:48:14.567966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31875 11:48:14.568590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31876 11:48:14.604420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31877 11:48:14.604859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31879 11:48:14.639402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31880 11:48:14.639897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31882 11:48:14.676536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31884 11:48:14.677170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31885 11:48:14.712373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31886 11:48:14.712830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31888 11:48:14.748819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31889 11:48:14.749283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31891 11:48:14.785003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31893 11:48:14.785560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31894 11:48:14.822112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31895 11:48:14.822564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31897 11:48:14.858559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31899 11:48:14.859035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31900 11:48:14.894967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31902 11:48:14.895454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31903 11:48:14.929997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31904 11:48:14.930407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31906 11:48:14.966986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31907 11:48:14.967364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31909 11:48:15.002741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31911 11:48:15.003222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31912 11:48:15.037994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31913 11:48:15.038375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31915 11:48:15.074288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31916 11:48:15.074657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31918 11:48:15.110228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31919 11:48:15.110723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31921 11:48:15.145801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31922 11:48:15.146201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31924 11:48:15.181118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31925 11:48:15.181512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31927 11:48:15.217099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31928 11:48:15.217517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31930 11:48:15.253235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31932 11:48:15.253769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31933 11:48:15.288999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31934 11:48:15.289423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31936 11:48:15.324345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31938 11:48:15.324982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31939 11:48:15.359145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31940 11:48:15.359633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31942 11:48:15.394637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31943 11:48:15.395112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31945 11:48:15.429720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31946 11:48:15.430200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31948 11:48:15.466447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
31950 11:48:15.467083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
31951 11:48:15.502123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
31952 11:48:15.502595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
31954 11:48:15.538538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
31955 11:48:15.539018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
31957 11:48:15.573693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
31959 11:48:15.574329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
31960 11:48:15.610134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
31961 11:48:15.610623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
31963 11:48:15.645982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
31964 11:48:15.646420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
31966 11:48:15.682665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
31968 11:48:15.683209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
31969 11:48:15.717715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
31971 11:48:15.718277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
31972 11:48:15.753971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
31974 11:48:15.754575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
31975 11:48:15.789259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
31977 11:48:15.789831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
31978 11:48:15.822494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
31980 11:48:15.823154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
31981 11:48:15.854000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
31982 11:48:15.854470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
31984 11:48:15.885843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
31986 11:48:15.886404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
31987 11:48:15.917116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
31989 11:48:15.917689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
31990 11:48:15.948774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
31991 11:48:15.949219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
31993 11:48:15.980349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
31994 11:48:15.980774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
31996 11:48:16.012464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
31997 11:48:16.012882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
31999 11:48:16.044360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
32000 11:48:16.044779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
32002 11:48:16.077178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
32004 11:48:16.077773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
32005 11:48:16.108922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
32006 11:48:16.109370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
32008 11:48:16.140873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
32009 11:48:16.141313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
32011 11:48:16.173116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
32012 11:48:16.173566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
32014 11:48:16.205008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
32015 11:48:16.205484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
32017 11:48:16.236783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
32019 11:48:16.237249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
32020 11:48:16.269104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
32022 11:48:16.269551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
32023 11:48:16.301599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
32025 11:48:16.302069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
32026 11:48:16.334537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
32028 11:48:16.335101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
32029 11:48:16.367047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
32031 11:48:16.367690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
32032 11:48:16.399159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
32033 11:48:16.399609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
32035 11:48:16.431909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
32037 11:48:16.432574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
32038 11:48:16.465042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
32039 11:48:16.465483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
32041 11:48:16.498520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
32042 11:48:16.499005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
32044 11:48:16.557220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
32045 11:48:16.557701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
32047 11:48:16.590915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
32048 11:48:16.591381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
32050 11:48:16.624103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
32052 11:48:16.624665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
32053 11:48:16.656191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
32054 11:48:16.656637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
32056 11:48:16.688669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
32057 11:48:16.689123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
32059 11:48:16.722099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
32061 11:48:16.722669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
32062 11:48:16.769403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
32063 11:48:16.769891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
32065 11:48:16.804844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
32066 11:48:16.805284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
32068 11:48:16.839632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
32069 11:48:16.840056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
32071 11:48:16.874882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
32072 11:48:16.875317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
32074 11:48:16.909338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
32075 11:48:16.909771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
32077 11:48:16.941475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
32079 11:48:16.941918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
32080 11:48:16.973920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
32081 11:48:16.974354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
32083 11:48:17.006977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
32085 11:48:17.007418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
32086 11:48:17.040978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
32087 11:48:17.041415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
32089 11:48:17.073244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
32091 11:48:17.073709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
32092 11:48:17.105837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
32093 11:48:17.106257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
32095 11:48:17.137816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
32096 11:48:17.138270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
32098 11:48:17.169378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
32099 11:48:17.169819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
32101 11:48:17.200730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
32103 11:48:17.201211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
32104 11:48:17.232299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
32105 11:48:17.232794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
32107 11:48:17.263435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
32108 11:48:17.263929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
32110 11:48:17.294946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
32112 11:48:17.295538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
32113 11:48:17.326150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
32115 11:48:17.326723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
32116 11:48:17.357949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
32117 11:48:17.358411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
32119 11:48:17.389846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
32120 11:48:17.390297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
32122 11:48:17.422226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
32124 11:48:17.422780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
32125 11:48:17.453477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
32127 11:48:17.454049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
32128 11:48:17.484538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
32129 11:48:17.485018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
32131 11:48:17.515632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
32133 11:48:17.516275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
32134 11:48:17.547136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
32135 11:48:17.547630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
32137 11:48:17.578438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
32139 11:48:17.579069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
32140 11:48:17.612418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
32142 11:48:17.612900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
32143 11:48:17.644284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
32145 11:48:17.644911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
32146 11:48:17.676354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
32148 11:48:17.676978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
32149 11:48:17.707467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
32150 11:48:17.707936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
32152 11:48:17.738877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
32154 11:48:17.739514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
32155 11:48:17.771169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
32156 11:48:17.771652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
32158 11:48:17.807421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
32160 11:48:17.807891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
32161 11:48:17.838858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
32163 11:48:17.839322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
32164 11:48:17.870093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
32165 11:48:17.870511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
32167 11:48:17.901579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
32169 11:48:17.902037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
32170 11:48:17.932868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
32171 11:48:17.933308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
32173 11:48:17.964901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
32175 11:48:17.965540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
32176 11:48:17.996445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
32177 11:48:17.996887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
32179 11:48:18.028316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
32180 11:48:18.028763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
32182 11:48:18.061240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
32183 11:48:18.061710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
32185 11:48:18.093012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
32186 11:48:18.093434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
32188 11:48:18.125408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
32190 11:48:18.125881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
32191 11:48:18.157361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
32192 11:48:18.157777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32194 11:48:18.190215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32195 11:48:18.190616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32197 11:48:18.222115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32199 11:48:18.222547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32200 11:48:18.253933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32201 11:48:18.254357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32203 11:48:18.286780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32205 11:48:18.287256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32206 11:48:18.318837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32207 11:48:18.319313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32209 11:48:18.351035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32210 11:48:18.351498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32212 11:48:18.383359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32213 11:48:18.383830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32215 11:48:18.415222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32217 11:48:18.415772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32218 11:48:18.447645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32220 11:48:18.448256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32221 11:48:18.479979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32223 11:48:18.480560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32224 11:48:18.511872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32226 11:48:18.512510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32227 11:48:18.544250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32228 11:48:18.544672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32230 11:48:18.576767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32232 11:48:18.577237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32233 11:48:18.608541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32235 11:48:18.608994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32236 11:48:18.641915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32237 11:48:18.642368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32239 11:48:18.675162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32240 11:48:18.675649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32242 11:48:18.707081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32244 11:48:18.707563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32245 11:48:18.739167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32246 11:48:18.739644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32248 11:48:18.771043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32249 11:48:18.771455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32251 11:48:18.804609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32253 11:48:18.805212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32254 11:48:18.836816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32256 11:48:18.837382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32257 11:48:18.869704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32258 11:48:18.870177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32260 11:48:18.901783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32262 11:48:18.902420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32263 11:48:18.933207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32265 11:48:18.933875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32266 11:48:18.965359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32267 11:48:18.965823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32269 11:48:18.997130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32271 11:48:18.997597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32272 11:48:19.028645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32273 11:48:19.029106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32275 11:48:19.061121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32277 11:48:19.061743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32278 11:48:19.093136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32280 11:48:19.093778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32281 11:48:19.124766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32283 11:48:19.125321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32284 11:48:19.156071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32286 11:48:19.156671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32287 11:48:19.187946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32289 11:48:19.188418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32290 11:48:19.221595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32292 11:48:19.222070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32293 11:48:19.253786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32294 11:48:19.254206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32296 11:48:19.287031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32298 11:48:19.287503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32299 11:48:19.319158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32301 11:48:19.319635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32302 11:48:19.351675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32304 11:48:19.352321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32305 11:48:19.385334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32306 11:48:19.385810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32308 11:48:19.417157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32309 11:48:19.417609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32311 11:48:19.450147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32313 11:48:19.450820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32314 11:48:19.481948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32316 11:48:19.482415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32317 11:48:19.513989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32319 11:48:19.514447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32320 11:48:19.545354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32321 11:48:19.545839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32323 11:48:19.577481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32324 11:48:19.577977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32326 11:48:19.609460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32328 11:48:19.610043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32329 11:48:19.641107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32330 11:48:19.641515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32332 11:48:19.674950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32333 11:48:19.675381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32335 11:48:19.707519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32336 11:48:19.707974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32338 11:48:19.739630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32340 11:48:19.740075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32341 11:48:19.771955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32343 11:48:19.772386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32344 11:48:19.804643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32345 11:48:19.805046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32347 11:48:19.837715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32349 11:48:19.838298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32350 11:48:19.871136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32352 11:48:19.871714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32353 11:48:19.903333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32354 11:48:19.903827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32356 11:48:19.936917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32357 11:48:19.937345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32359 11:48:19.969006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32360 11:48:19.969461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32362 11:48:20.000869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32363 11:48:20.001330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32365 11:48:20.033214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32366 11:48:20.033681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32368 11:48:20.064806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32369 11:48:20.065273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32371 11:48:20.097208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32372 11:48:20.097682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32374 11:48:20.129011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32375 11:48:20.129476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32377 11:48:20.160854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32378 11:48:20.161327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32380 11:48:20.193854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32381 11:48:20.194334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32383 11:48:20.226117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32384 11:48:20.226582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32386 11:48:20.257499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32387 11:48:20.257979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32389 11:48:20.289458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32390 11:48:20.289937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32392 11:48:20.321853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32394 11:48:20.322473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32395 11:48:20.353624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32396 11:48:20.354109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32398 11:48:20.386119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32399 11:48:20.386582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32401 11:48:20.418530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32402 11:48:20.418959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32404 11:48:20.450604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32405 11:48:20.451052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32407 11:48:20.485458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32408 11:48:20.485852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32410 11:48:20.517506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32411 11:48:20.517908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32413 11:48:20.549788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32414 11:48:20.550172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32416 11:48:20.581935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32417 11:48:20.582341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32419 11:48:20.614331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32420 11:48:20.614789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32422 11:48:20.646452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32423 11:48:20.646918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32425 11:48:20.678561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32427 11:48:20.679116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32428 11:48:20.711682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32430 11:48:20.712233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32431 11:48:20.743459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32432 11:48:20.743932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32434 11:48:20.777339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32436 11:48:20.777910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32437 11:48:20.811508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32439 11:48:20.812139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32440 11:48:20.844419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32441 11:48:20.844886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32443 11:48:20.877784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32444 11:48:20.878197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32446 11:48:20.911718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32448 11:48:20.912188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32449 11:48:20.944659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32450 11:48:20.945072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32452 11:48:20.977065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32453 11:48:20.977474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32455 11:48:21.008892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32456 11:48:21.009300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32458 11:48:21.040608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32459 11:48:21.041079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32461 11:48:21.072357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32462 11:48:21.072813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32464 11:48:21.105008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32465 11:48:21.105465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32467 11:48:21.137744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32468 11:48:21.138216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32470 11:48:21.169973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32471 11:48:21.170433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32473 11:48:21.201972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32474 11:48:21.202383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32476 11:48:21.234618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32478 11:48:21.235217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32479 11:48:21.266318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32480 11:48:21.266749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32482 11:48:21.298249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32483 11:48:21.298680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32485 11:48:21.332296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32486 11:48:21.332727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32488 11:48:21.365124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32490 11:48:21.365599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32491 11:48:21.397016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32492 11:48:21.397488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32494 11:48:21.434368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32495 11:48:21.434854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32497 11:48:21.469046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32498 11:48:21.469470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32500 11:48:21.503671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32502 11:48:21.504138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32503 11:48:21.539004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32504 11:48:21.539487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32506 11:48:21.574502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32507 11:48:21.574984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32509 11:48:21.609180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32510 11:48:21.609654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32512 11:48:21.665019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32513 11:48:21.665395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32515 11:48:21.698297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32517 11:48:21.698773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32518 11:48:21.731665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32519 11:48:21.732164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32521 11:48:21.766181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32523 11:48:21.766650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32524 11:48:21.803413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32525 11:48:21.803855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32527 11:48:21.841001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32528 11:48:21.841431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32530 11:48:21.878225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32531 11:48:21.878637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32533 11:48:21.913170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32535 11:48:21.913635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32536 11:48:21.948875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32538 11:48:21.949337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32539 11:48:21.982959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32540 11:48:21.983375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32542 11:48:22.016696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32543 11:48:22.017090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32545 11:48:22.049581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32546 11:48:22.050007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32548 11:48:22.082392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32549 11:48:22.082859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32551 11:48:22.115077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32552 11:48:22.115594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32554 11:48:22.152859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32555 11:48:22.153416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32557 11:48:22.186876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32558 11:48:22.187333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32560 11:48:22.220388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32561 11:48:22.220799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32563 11:48:22.253003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32564 11:48:22.253453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32566 11:48:22.286050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32567 11:48:22.286503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32569 11:48:22.318671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32571 11:48:22.319257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32572 11:48:22.350723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32573 11:48:22.351187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32575 11:48:22.382974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32576 11:48:22.383429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32578 11:48:22.415141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32579 11:48:22.415601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32581 11:48:22.447966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32583 11:48:22.448594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32584 11:48:22.479863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32586 11:48:22.480331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32587 11:48:22.511807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32589 11:48:22.512257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32590 11:48:22.544343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32591 11:48:22.544773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32593 11:48:22.578990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32594 11:48:22.579404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32596 11:48:22.612464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32598 11:48:22.613047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32599 11:48:22.645391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32600 11:48:22.645813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32602 11:48:22.677561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32603 11:48:22.678046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32605 11:48:22.709168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32606 11:48:22.709600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32608 11:48:22.741340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32609 11:48:22.741792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32611 11:48:22.772790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32612 11:48:22.773269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32614 11:48:22.804723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32615 11:48:22.805210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32617 11:48:22.836945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32619 11:48:22.837499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32620 11:48:22.868605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32622 11:48:22.869153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32623 11:48:22.900342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32624 11:48:22.900824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32626 11:48:22.931083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32627 11:48:22.931567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32629 11:48:22.963093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32630 11:48:22.963564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32632 11:48:22.994776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32633 11:48:22.995172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32635 11:48:23.026301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32636 11:48:23.026768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32638 11:48:23.059108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32639 11:48:23.059586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32641 11:48:23.090900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32642 11:48:23.091383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32644 11:48:23.124451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32646 11:48:23.124905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32647 11:48:23.156891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32648 11:48:23.157319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32650 11:48:23.189158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32651 11:48:23.189568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32653 11:48:23.221613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32654 11:48:23.222031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32656 11:48:23.254009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32657 11:48:23.254421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32659 11:48:23.286064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32660 11:48:23.286515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32662 11:48:23.318144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32663 11:48:23.318606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32665 11:48:23.350332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32666 11:48:23.350759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32668 11:48:23.382626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32669 11:48:23.383088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32671 11:48:23.414823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32672 11:48:23.415298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32674 11:48:23.446902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32675 11:48:23.447319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32677 11:48:23.479057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32678 11:48:23.479531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32680 11:48:23.510725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32681 11:48:23.511212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32683 11:48:23.542623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32684 11:48:23.543100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32686 11:48:23.575025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32688 11:48:23.575660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32689 11:48:23.607105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32690 11:48:23.607566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32692 11:48:23.641661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32693 11:48:23.642076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32695 11:48:23.675495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32696 11:48:23.675919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32698 11:48:23.708694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32699 11:48:23.709101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32701 11:48:23.741276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32702 11:48:23.741741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32704 11:48:23.774134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32706 11:48:23.774601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32707 11:48:23.806969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32708 11:48:23.807394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32710 11:48:23.839795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32712 11:48:23.840253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32713 11:48:23.872460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32714 11:48:23.872944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32716 11:48:23.905012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32717 11:48:23.905488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32719 11:48:23.937161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32720 11:48:23.937602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32722 11:48:23.969363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32723 11:48:23.969787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32725 11:48:24.002016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32726 11:48:24.002496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32728 11:48:24.034253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32729 11:48:24.034706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32731 11:48:24.067084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32732 11:48:24.067533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32734 11:48:24.099080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32735 11:48:24.099569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32737 11:48:24.132782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32738 11:48:24.133235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32740 11:48:24.166373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32742 11:48:24.167012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32743 11:48:24.201614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32744 11:48:24.202111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32746 11:48:24.234931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32747 11:48:24.235399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32749 11:48:24.266880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32750 11:48:24.267319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32752 11:48:24.299033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32753 11:48:24.299477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32755 11:48:24.331130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32756 11:48:24.331575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32758 11:48:24.365287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32759 11:48:24.365756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32761 11:48:24.397468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32762 11:48:24.397943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32764 11:48:24.429357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32765 11:48:24.429810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32767 11:48:24.461426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32768 11:48:24.461821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32770 11:48:24.493982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32771 11:48:24.494375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32773 11:48:24.528017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32775 11:48:24.528599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32776 11:48:24.560769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32777 11:48:24.561203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32779 11:48:24.593527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32780 11:48:24.594037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32782 11:48:24.626259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32783 11:48:24.626714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32785 11:48:24.660418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32786 11:48:24.660900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32788 11:48:24.693045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32789 11:48:24.693461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32791 11:48:24.726546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32793 11:48:24.727008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32794 11:48:24.759283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32796 11:48:24.759749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32797 11:48:24.791347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32798 11:48:24.791775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32800 11:48:24.823644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32801 11:48:24.824073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32803 11:48:24.855963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32805 11:48:24.856355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32806 11:48:24.889709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32807 11:48:24.890133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32809 11:48:24.922301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32811 11:48:24.922854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32812 11:48:24.954906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32813 11:48:24.955360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32815 11:48:24.988624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32816 11:48:24.989075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32818 11:48:25.024926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32819 11:48:25.025393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32821 11:48:25.058325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32822 11:48:25.058773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32824 11:48:25.091066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32825 11:48:25.091520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32827 11:48:25.124051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32829 11:48:25.124519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32830 11:48:25.156802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32831 11:48:25.157229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32833 11:48:25.189283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32834 11:48:25.189683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32836 11:48:25.221713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32838 11:48:25.222182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32839 11:48:25.253531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32840 11:48:25.254030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32842 11:48:25.284855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32843 11:48:25.285339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32845 11:48:25.316508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32846 11:48:25.316981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32848 11:48:25.348293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32849 11:48:25.348782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32851 11:48:25.379981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32853 11:48:25.380653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32854 11:48:25.411936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32856 11:48:25.412576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32857 11:48:25.443563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32859 11:48:25.444039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32860 11:48:25.475225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32861 11:48:25.475642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32863 11:48:25.506570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32865 11:48:25.507138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32866 11:48:25.537924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32867 11:48:25.538340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32869 11:48:25.570253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32870 11:48:25.570695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32872 11:48:25.601481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32873 11:48:25.601923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32875 11:48:25.633449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32876 11:48:25.633930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32878 11:48:25.664938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32879 11:48:25.665397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32881 11:48:25.697287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32882 11:48:25.697756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32884 11:48:25.729684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32886 11:48:25.730235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32887 11:48:25.763614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32888 11:48:25.764098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32890 11:48:25.796511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32892 11:48:25.797148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32893 11:48:25.828373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32895 11:48:25.828822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32896 11:48:25.861203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32898 11:48:25.861778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32899 11:48:25.893329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32900 11:48:25.893782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32902 11:48:25.928974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32904 11:48:25.929535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32905 11:48:25.961320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32906 11:48:25.961791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32908 11:48:25.993765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32910 11:48:25.994297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32911 11:48:26.026532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32913 11:48:26.027080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32914 11:48:26.071548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32915 11:48:26.071954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32917 11:48:26.108749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32918 11:48:26.109211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32920 11:48:26.143565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32921 11:48:26.144070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32923 11:48:26.178778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32925 11:48:26.179347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32926 11:48:26.214408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32927 11:48:26.214882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32929 11:48:26.249484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32930 11:48:26.249976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32932 11:48:26.285721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32934 11:48:26.286307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32935 11:48:26.321414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32936 11:48:26.321847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32938 11:48:26.357563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32939 11:48:26.357996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32941 11:48:26.393113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32942 11:48:26.393535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32944 11:48:26.428831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32945 11:48:26.429304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32947 11:48:26.464729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
32949 11:48:26.465203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
32950 11:48:26.500741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
32952 11:48:26.501210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
32953 11:48:26.537039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
32955 11:48:26.537683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
32956 11:48:26.572773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
32958 11:48:26.573233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
32959 11:48:26.608602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
32960 11:48:26.609072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
32962 11:48:26.644400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
32964 11:48:26.644988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
32965 11:48:26.680193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
32966 11:48:26.680627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
32968 11:48:26.715100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
32970 11:48:26.715570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
32971 11:48:26.757901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
32972 11:48:26.758336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
32974 11:48:26.812510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
32975 11:48:26.813080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
32977 11:48:26.848415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
32978 11:48:26.848855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
32980 11:48:26.882146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
32981 11:48:26.882569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
32983 11:48:26.916964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
32984 11:48:26.917348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
32986 11:48:26.950868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
32987 11:48:26.951266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
32989 11:48:26.984691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
32990 11:48:26.985133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
32992 11:48:27.017780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
32993 11:48:27.018220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
32995 11:48:27.050334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
32996 11:48:27.050769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
32998 11:48:27.082893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
33000 11:48:27.083497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
33001 11:48:27.114485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
33002 11:48:27.114914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
33004 11:48:27.146946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
33005 11:48:27.147378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
33007 11:48:27.178610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
33008 11:48:27.179028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
33010 11:48:27.211193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
33011 11:48:27.211674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
33013 11:48:27.244890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
33014 11:48:27.245363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
33016 11:48:27.277211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
33018 11:48:27.277667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
33019 11:48:27.309205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
33020 11:48:27.309667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
33022 11:48:27.340723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
33024 11:48:27.341133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
33025 11:48:27.372248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
33026 11:48:27.372676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
33028 11:48:27.404777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
33029 11:48:27.405200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
33031 11:48:27.436980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
33033 11:48:27.437528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
33034 11:48:27.468569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
33035 11:48:27.469031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
33037 11:48:27.500913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
33038 11:48:27.501383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
33040 11:48:27.533062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
33041 11:48:27.533536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
33043 11:48:27.565194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
33044 11:48:27.565681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
33046 11:48:27.597926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
33048 11:48:27.598557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
33049 11:48:27.630070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
33051 11:48:27.630607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
33052 11:48:27.661783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
33053 11:48:27.662254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
33055 11:48:27.693899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
33056 11:48:27.694389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
33058 11:48:27.725617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
33059 11:48:27.726117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
33061 11:48:27.757982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
33062 11:48:27.758461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
33064 11:48:27.790873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
33066 11:48:27.791427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
33067 11:48:27.823330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
33068 11:48:27.823781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
33070 11:48:27.856111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33071 11:48:27.856593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33073 11:48:27.888972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33074 11:48:27.889428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
33076 11:48:27.921700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33078 11:48:27.922133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33079 11:48:27.956173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33081 11:48:27.956787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33082 11:48:27.989772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33083 11:48:27.990184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
33085 11:48:28.022507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33086 11:48:28.022903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33088 11:48:28.055287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33089 11:48:28.055744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33091 11:48:28.087325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
33093 11:48:28.087907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33094 11:48:28.119624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33096 11:48:28.120187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33097 11:48:28.152092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33099 11:48:28.152629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33100 11:48:28.183987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
33102 11:48:28.184513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33103 11:48:28.215497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33105 11:48:28.216028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33106 11:48:28.247418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33108 11:48:28.247948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33109 11:48:28.280001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
33111 11:48:28.280527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33112 11:48:28.311576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33113 11:48:28.312068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33115 11:48:28.343161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
33116 11:48:28.343613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
33118 11:48:28.374741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33119 11:48:28.375171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33121 11:48:28.407479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
33123 11:48:28.407957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33124 11:48:28.440912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33126 11:48:28.441384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33127 11:48:28.473243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33129 11:48:28.473723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33130 11:48:28.505776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
33132 11:48:28.506229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33133 11:48:28.537997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33134 11:48:28.538418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33136 11:48:28.570805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33138 11:48:28.571337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33139 11:48:28.603437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
33141 11:48:28.604011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33142 11:48:28.635918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33144 11:48:28.636269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33145 11:48:28.668905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33146 11:48:28.669343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33148 11:48:28.700290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33149 11:48:28.700728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
33151 11:48:28.731679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33153 11:48:28.732256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33154 11:48:28.762973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33156 11:48:28.763551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33157 11:48:28.795190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33158 11:48:28.795659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
33160 11:48:28.827433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33161 11:48:28.827851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33163 11:48:28.858892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
33165 11:48:28.859337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
33166 11:48:28.890992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33168 11:48:28.891562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33169 11:48:28.924072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
33171 11:48:28.924636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33172 11:48:28.957049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33173 11:48:28.957546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33175 11:48:28.989245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33177 11:48:28.989897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33178 11:48:29.021086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33179 11:48:29.021532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
33181 11:48:29.052941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33182 11:48:29.053379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33184 11:48:29.085869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33186 11:48:29.086351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33187 11:48:29.118261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
33189 11:48:29.118747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33190 11:48:29.150175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33192 11:48:29.150728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33193 11:48:29.182404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33194 11:48:29.182853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33196 11:48:29.214295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33197 11:48:29.214774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33199 11:48:29.246206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33201 11:48:29.246777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33202 11:48:29.278268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33203 11:48:29.278757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33205 11:48:29.311534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33206 11:48:29.312021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33208 11:48:29.343560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33210 11:48:29.344187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33211 11:48:29.374971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33213 11:48:29.375588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33214 11:48:29.406502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33215 11:48:29.406957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33217 11:48:29.437842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33218 11:48:29.438230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33220 11:48:29.470222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33222 11:48:29.470688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33223 11:48:29.501558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33225 11:48:29.502050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33226 11:48:29.533533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33228 11:48:29.534188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33229 11:48:29.565082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33231 11:48:29.565666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33232 11:48:29.597163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33233 11:48:29.597598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33235 11:48:29.629017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33236 11:48:29.629496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33238 11:48:29.662736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33239 11:48:29.663115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33241 11:48:29.696143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33243 11:48:29.696567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33244 11:48:29.729128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33246 11:48:29.729597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33247 11:48:29.762040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33249 11:48:29.762600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33250 11:48:29.794696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33251 11:48:29.795106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33253 11:48:29.827649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33255 11:48:29.828117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33256 11:48:29.860528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33257 11:48:29.860952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33259 11:48:29.893545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33260 11:48:29.893983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33262 11:48:29.925729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33263 11:48:29.926154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33265 11:48:29.957811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33266 11:48:29.958235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33268 11:48:29.990286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33270 11:48:29.990838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33271 11:48:30.022299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33272 11:48:30.022743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33274 11:48:30.054216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33276 11:48:30.054792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33277 11:48:30.085531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33279 11:48:30.086093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33280 11:48:30.118023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33281 11:48:30.118429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33283 11:48:30.150217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33284 11:48:30.150665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33286 11:48:30.181982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33287 11:48:30.182426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33289 11:48:30.213877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33290 11:48:30.214385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33292 11:48:30.245316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33293 11:48:30.245688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33295 11:48:30.277159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33297 11:48:30.277779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33298 11:48:30.309415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33300 11:48:30.310001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33301 11:48:30.341986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33302 11:48:30.342455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33304 11:48:30.373829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33305 11:48:30.374282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33307 11:48:30.405184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33308 11:48:30.405657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33310 11:48:30.437635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33311 11:48:30.438102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33313 11:48:30.469717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33315 11:48:30.470257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33316 11:48:30.502025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33317 11:48:30.502477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33319 11:48:30.533877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33320 11:48:30.534259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33322 11:48:30.565782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33323 11:48:30.566156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33325 11:48:30.597511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33326 11:48:30.597901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33328 11:48:30.629905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33330 11:48:30.630363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33331 11:48:30.661527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33332 11:48:30.661960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33334 11:48:30.693060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33336 11:48:30.693533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33337 11:48:30.724774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33338 11:48:30.725189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33340 11:48:30.756984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33342 11:48:30.757443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33343 11:48:30.789925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33345 11:48:30.790385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33346 11:48:30.822015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33348 11:48:30.822656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33349 11:48:30.854496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33350 11:48:30.854969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33352 11:48:30.886070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33353 11:48:30.886479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33355 11:48:30.918565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33356 11:48:30.919010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33358 11:48:30.950066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33359 11:48:30.950466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33361 11:48:30.982194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33363 11:48:30.982756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33364 11:48:31.014681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33365 11:48:31.015090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33367 11:48:31.046852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33368 11:48:31.047256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33370 11:48:31.078910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33371 11:48:31.079389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33373 11:48:31.110191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33374 11:48:31.110618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33376 11:48:31.142167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33377 11:48:31.142619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33379 11:48:31.174489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33380 11:48:31.174912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33382 11:48:31.206648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33383 11:48:31.207034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33385 11:48:31.241103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33386 11:48:31.241517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33388 11:48:31.273392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33389 11:48:31.273830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33391 11:48:31.305367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33392 11:48:31.305796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33394 11:48:31.338712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33396 11:48:31.339179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33397 11:48:31.372064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33399 11:48:31.372547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33400 11:48:31.403960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33402 11:48:31.404428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33403 11:48:31.437477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33405 11:48:31.437975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33406 11:48:31.470366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33407 11:48:31.470799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33409 11:48:31.505442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33411 11:48:31.506115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33412 11:48:31.543791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33414 11:48:31.544486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33415 11:48:31.586637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33417 11:48:31.587214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33418 11:48:31.634339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33419 11:48:31.634732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33421 11:48:31.669494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33422 11:48:31.669850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33424 11:48:31.701325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33425 11:48:31.701726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33427 11:48:31.733103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33429 11:48:31.733668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33430 11:48:31.764831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33432 11:48:31.765516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33433 11:48:31.797619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33435 11:48:31.798220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33436 11:48:31.829998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33438 11:48:31.830566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33439 11:48:31.862529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33440 11:48:31.862990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33442 11:48:31.914621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33443 11:48:31.915121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33445 11:48:31.948117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33447 11:48:31.948665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33448 11:48:31.980632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33450 11:48:31.981202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33451 11:48:32.013169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33452 11:48:32.013644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33454 11:48:32.045216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33455 11:48:32.045672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33457 11:48:32.077523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33458 11:48:32.078098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33460 11:48:32.110311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33462 11:48:32.110772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33463 11:48:32.142348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33464 11:48:32.142775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33466 11:48:32.174797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33467 11:48:32.175257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33469 11:48:32.206156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33470 11:48:32.206619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33472 11:48:32.238474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33473 11:48:32.238895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33475 11:48:32.270103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33476 11:48:32.270548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33478 11:48:32.302179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33480 11:48:32.302626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33481 11:48:32.333706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33483 11:48:32.334157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33484 11:48:32.366077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33485 11:48:32.366552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33487 11:48:32.398455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33489 11:48:32.399083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33490 11:48:32.429732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33491 11:48:32.430196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33493 11:48:32.462142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33494 11:48:32.462556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33496 11:48:32.494109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33497 11:48:32.494527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33499 11:48:32.526097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33501 11:48:32.526524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33502 11:48:32.557841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33503 11:48:32.558238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33505 11:48:32.589706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33506 11:48:32.590105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33508 11:48:32.622338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33510 11:48:32.622752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33511 11:48:32.654281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33513 11:48:32.654831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33514 11:48:32.685908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33515 11:48:32.686361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33517 11:48:32.718138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33519 11:48:32.718680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33520 11:48:32.749928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33522 11:48:32.750470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33523 11:48:32.782122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33525 11:48:32.782672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33526 11:48:32.814240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33527 11:48:32.814685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33529 11:48:32.846642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33530 11:48:32.847086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33532 11:48:32.879128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33534 11:48:32.879683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33535 11:48:32.911136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33536 11:48:32.911588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33538 11:48:32.943059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33539 11:48:32.943514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33541 11:48:32.975532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33542 11:48:32.975998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33544 11:48:33.007077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33545 11:48:33.007501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33547 11:48:33.038857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33548 11:48:33.039277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33550 11:48:33.070187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33551 11:48:33.070581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33553 11:48:33.101620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33554 11:48:33.102056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33556 11:48:33.133324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33558 11:48:33.133797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33559 11:48:33.164690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33560 11:48:33.165153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33562 11:48:33.196368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33563 11:48:33.196783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33565 11:48:33.228897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33567 11:48:33.229343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33568 11:48:33.261707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33569 11:48:33.262105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33571 11:48:33.293332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33572 11:48:33.293744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33574 11:48:33.325512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33576 11:48:33.325956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33577 11:48:33.357147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33578 11:48:33.357555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33580 11:48:33.389016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33581 11:48:33.389464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33583 11:48:33.421200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33584 11:48:33.421673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33586 11:48:33.453626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33587 11:48:33.454100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33589 11:48:33.486263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33591 11:48:33.486824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33592 11:48:33.518266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33593 11:48:33.518686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33595 11:48:33.549885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33596 11:48:33.550364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33598 11:48:33.581837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33600 11:48:33.582421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33601 11:48:33.613910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33603 11:48:33.614457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33604 11:48:33.646819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33606 11:48:33.647456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33607 11:48:33.678384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33609 11:48:33.678931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33610 11:48:33.710274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33612 11:48:33.710841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33613 11:48:33.741807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33614 11:48:33.742280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33616 11:48:33.773119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33617 11:48:33.773581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33619 11:48:33.804906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33620 11:48:33.805312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33622 11:48:33.836500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33624 11:48:33.836941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33625 11:48:33.868637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33627 11:48:33.869053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33628 11:48:33.900512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33629 11:48:33.900928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33631 11:48:33.932984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33632 11:48:33.933406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33634 11:48:33.965480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33635 11:48:33.965947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33637 11:48:33.998199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33639 11:48:33.998755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33640 11:48:34.030328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33641 11:48:34.030812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33643 11:48:34.062597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33644 11:48:34.063087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33646 11:48:34.094654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33647 11:48:34.095108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33649 11:48:34.127088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33651 11:48:34.127556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33652 11:48:34.159004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33653 11:48:34.159426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33655 11:48:34.193689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33657 11:48:34.194162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33658 11:48:34.227229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33659 11:48:34.227722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33661 11:48:34.259018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33663 11:48:34.259576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33664 11:48:34.291349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33665 11:48:34.291787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33667 11:48:34.322994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33668 11:48:34.323464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33670 11:48:34.354718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33671 11:48:34.355159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33673 11:48:34.386491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33675 11:48:34.387025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33676 11:48:34.417901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33677 11:48:34.418367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33679 11:48:34.449681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33680 11:48:34.450113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33682 11:48:34.484714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33684 11:48:34.485375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33685 11:48:34.519833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33687 11:48:34.520311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33688 11:48:34.552155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33689 11:48:34.552630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33691 11:48:34.586338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33693 11:48:34.586901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33694 11:48:34.619027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33696 11:48:34.619613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33697 11:48:34.651680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33699 11:48:34.652239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33700 11:48:34.686398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33702 11:48:34.686955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33703 11:48:34.718947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33704 11:48:34.719410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33706 11:48:34.751268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33708 11:48:34.751861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33709 11:48:34.784537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33711 11:48:34.785141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33712 11:48:34.817698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33713 11:48:34.818164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33715 11:48:34.849776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33716 11:48:34.850227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33718 11:48:34.884471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33719 11:48:34.884958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33721 11:48:34.919046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33722 11:48:34.919501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33724 11:48:34.951183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33725 11:48:34.951609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33727 11:48:34.983578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33728 11:48:34.984019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33730 11:48:35.017710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33731 11:48:35.018140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33733 11:48:35.049951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33734 11:48:35.050376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33736 11:48:35.081618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33738 11:48:35.082092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33739 11:48:35.112987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33740 11:48:35.113425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33742 11:48:35.144199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33744 11:48:35.144645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33745 11:48:35.176749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33746 11:48:35.177124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33748 11:48:35.208965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33749 11:48:35.209391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33751 11:48:35.240699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33752 11:48:35.241146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33754 11:48:35.273053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33755 11:48:35.273482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33757 11:48:35.305028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33758 11:48:35.305401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33760 11:48:35.338356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33761 11:48:35.338773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33763 11:48:35.371184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33764 11:48:35.371642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33766 11:48:35.403618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33767 11:48:35.404091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33769 11:48:35.436875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33770 11:48:35.437269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33772 11:48:35.469322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33773 11:48:35.469680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33775 11:48:35.501993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33776 11:48:35.502379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33778 11:48:35.534342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33779 11:48:35.534839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33781 11:48:35.566659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33783 11:48:35.567267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33784 11:48:35.602189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33785 11:48:35.602625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33787 11:48:35.634523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33788 11:48:35.634946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33790 11:48:35.674169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33791 11:48:35.674656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33793 11:48:35.706451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33794 11:48:35.706937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33796 11:48:35.738957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33798 11:48:35.739594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33799 11:48:35.770391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33801 11:48:35.770963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33802 11:48:35.802615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33804 11:48:35.803081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33805 11:48:35.834867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33807 11:48:35.835336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33808 11:48:35.866489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33809 11:48:35.866910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33811 11:48:35.899062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33812 11:48:35.899555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33814 11:48:35.930935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33815 11:48:35.931423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33817 11:48:35.963351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33818 11:48:35.963846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33820 11:48:35.999058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33822 11:48:35.999695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33823 11:48:36.031587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33825 11:48:36.032302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33826 11:48:36.064416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33828 11:48:36.064895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33829 11:48:36.097129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33830 11:48:36.097570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33832 11:48:36.129542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33834 11:48:36.130145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33835 11:48:36.161551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33836 11:48:36.162034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33838 11:48:36.193310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33840 11:48:36.193909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33841 11:48:36.225340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33842 11:48:36.225795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33844 11:48:36.258003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33845 11:48:36.258422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33847 11:48:36.294647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33849 11:48:36.295097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33850 11:48:36.328018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33852 11:48:36.328593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33853 11:48:36.360831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33854 11:48:36.361261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33856 11:48:36.393629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33858 11:48:36.394113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33859 11:48:36.425525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33861 11:48:36.426107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33862 11:48:36.457397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33863 11:48:36.457879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33865 11:48:36.491582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33867 11:48:36.492142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33868 11:48:36.534159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33869 11:48:36.534603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33871 11:48:36.568891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33872 11:48:36.569319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33874 11:48:36.603094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33875 11:48:36.603540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33877 11:48:36.638656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33879 11:48:36.639129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33880 11:48:36.671003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33882 11:48:36.671617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33883 11:48:36.704742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33884 11:48:36.705205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33886 11:48:36.736831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33888 11:48:36.737297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33889 11:48:36.768964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33890 11:48:36.769387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33892 11:48:36.804634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33893 11:48:36.805047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33895 11:48:36.842415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33896 11:48:36.842858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33898 11:48:36.879202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33899 11:48:36.879647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33901 11:48:36.918136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33903 11:48:36.918597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33904 11:48:36.956765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33905 11:48:36.957231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33907 11:48:37.009274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33909 11:48:37.009934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33910 11:48:37.048378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33911 11:48:37.048866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33913 11:48:37.081477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33914 11:48:37.081915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33916 11:48:37.114434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33917 11:48:37.114872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33919 11:48:37.147588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33920 11:48:37.148041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33922 11:48:37.181191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33924 11:48:37.181662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33925 11:48:37.213849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33926 11:48:37.214270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33928 11:48:37.246835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33930 11:48:37.247308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33931 11:48:37.280298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33932 11:48:37.280719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33934 11:48:37.312780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33935 11:48:37.313270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33937 11:48:37.344735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33938 11:48:37.345208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33940 11:48:37.376558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33941 11:48:37.377039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33943 11:48:37.409785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33945 11:48:37.410422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33946 11:48:37.442670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33947 11:48:37.443131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33949 11:48:37.475628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33950 11:48:37.476075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
33952 11:48:37.508816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33953 11:48:37.509227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33955 11:48:37.541000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33956 11:48:37.541425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33958 11:48:37.572672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
33960 11:48:37.573137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33961 11:48:37.604519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33963 11:48:37.604997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33964 11:48:37.636128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33966 11:48:37.636697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33967 11:48:37.668372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33968 11:48:37.668798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
33970 11:48:37.700928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33972 11:48:37.701410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33973 11:48:37.733489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33975 11:48:37.733962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33976 11:48:37.765663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33977 11:48:37.766093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
33979 11:48:37.797663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33981 11:48:37.798134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33982 11:48:37.829527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
33983 11:48:37.830022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
33985 11:48:37.861680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33986 11:48:37.862105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33988 11:48:37.895125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
33990 11:48:37.895591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33991 11:48:37.926752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33992 11:48:37.927177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33994 11:48:37.958388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33995 11:48:37.958868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33997 11:48:37.990003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33998 11:48:37.990413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
34000 11:48:38.022420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
34001 11:48:38.022903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
34003 11:48:38.053990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
34004 11:48:38.054446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
34006 11:48:38.086147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
34008 11:48:38.086701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
34009 11:48:38.118149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
34010 11:48:38.118598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
34012 11:48:38.149987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
34013 11:48:38.150395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
34015 11:48:38.182747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
34017 11:48:38.183314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
34018 11:48:38.215199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
34020 11:48:38.215755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
34021 11:48:38.247671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
34023 11:48:38.248133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
34024 11:48:38.280718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
34026 11:48:38.281170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
34027 11:48:38.314479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
34028 11:48:38.314967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
34030 11:48:38.349021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
34031 11:48:38.349496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
34033 11:48:38.382230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
34034 11:48:38.382706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
34036 11:48:38.417115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
34038 11:48:38.417718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
34039 11:48:38.450079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
34041 11:48:38.450575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
34042 11:48:38.483113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
34044 11:48:38.483592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
34045 11:48:38.517209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
34046 11:48:38.517644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
34048 11:48:38.550216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
34050 11:48:38.550684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
34051 11:48:38.583011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
34053 11:48:38.583685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
34054 11:48:38.617944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
34055 11:48:38.618416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
34057 11:48:38.650762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
34058 11:48:38.651191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
34060 11:48:38.683284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
34061 11:48:38.683701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
34063 11:48:38.715391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
34064 11:48:38.715895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
34066 11:48:38.747900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
34068 11:48:38.748537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
34069 11:48:38.781332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
34070 11:48:38.781787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
34072 11:48:38.813337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
34073 11:48:38.813757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
34075 11:48:38.849094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
34076 11:48:38.849535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
34078 11:48:38.882012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
34080 11:48:38.882575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
34081 11:48:38.914855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
34082 11:48:38.915244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
34084 11:48:38.947522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
34085 11:48:38.947917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
34087 11:48:38.979611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
34088 11:48:38.980004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
34090 11:48:39.012572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
34091 11:48:39.012953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
34093 11:48:39.045215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
34094 11:48:39.045623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
34096 11:48:39.077604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
34097 11:48:39.078020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
34099 11:48:39.110372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
34100 11:48:39.110779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
34102 11:48:39.142841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
34103 11:48:39.143293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
34105 11:48:39.176476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
34106 11:48:39.176883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
34108 11:48:39.211021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
34110 11:48:39.211834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
34111 11:48:39.246148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
34113 11:48:39.246724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
34114 11:48:39.279954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
34116 11:48:39.280567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
34117 11:48:39.313614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
34119 11:48:39.314181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
34120 11:48:39.346189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
34122 11:48:39.346731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
34123 11:48:39.378437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
34125 11:48:39.378903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
34126 11:48:39.410330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
34127 11:48:39.410794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
34129 11:48:39.442656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
34130 11:48:39.443105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
34132 11:48:39.474809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
34133 11:48:39.475270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
34135 11:48:39.506966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
34136 11:48:39.507413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
34138 11:48:39.538754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
34139 11:48:39.539215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
34141 11:48:39.570319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
34143 11:48:39.570882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
34144 11:48:39.602698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
34145 11:48:39.603107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
34147 11:48:39.634760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
34148 11:48:39.635218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
34150 11:48:39.666146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
34151 11:48:39.666600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
34153 11:48:39.697337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
34154 11:48:39.697794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
34156 11:48:39.728947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
34157 11:48:39.729402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
34159 11:48:39.760536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
34161 11:48:39.761103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
34162 11:48:39.792614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
34163 11:48:39.793065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
34165 11:48:39.824938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
34166 11:48:39.825389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
34168 11:48:39.856619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
34170 11:48:39.857170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
34171 11:48:39.888502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
34173 11:48:39.889055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
34174 11:48:39.919962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
34176 11:48:39.920418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
34177 11:48:39.952508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
34178 11:48:39.952961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
34180 11:48:39.984931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
34182 11:48:39.985485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
34183 11:48:40.016797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
34185 11:48:40.017354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
34186 11:48:40.049133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
34188 11:48:40.049698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
34189 11:48:40.081082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
34190 11:48:40.081478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
34192 11:48:40.117898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34193 11:48:40.118376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34195 11:48:40.151423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34196 11:48:40.151850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34198 11:48:40.183116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34200 11:48:40.183595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34201 11:48:40.215196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34202 11:48:40.215625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34204 11:48:40.250888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34205 11:48:40.251331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34207 11:48:40.284400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34209 11:48:40.284857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34210 11:48:40.315955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34212 11:48:40.316598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34213 11:48:40.347542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34214 11:48:40.347933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34216 11:48:40.379457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34217 11:48:40.379900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34219 11:48:40.411240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34220 11:48:40.411668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34222 11:48:40.442645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34223 11:48:40.443089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34225 11:48:40.474292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34227 11:48:40.474771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34228 11:48:40.505906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34230 11:48:40.506554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34231 11:48:40.537435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34232 11:48:40.537876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34234 11:48:40.569594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34236 11:48:40.570085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34237 11:48:40.601717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34238 11:48:40.602142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34240 11:48:40.634215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34242 11:48:40.634850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34243 11:48:40.665376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34244 11:48:40.665876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34246 11:48:40.696601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34247 11:48:40.697093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34249 11:48:40.728057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34251 11:48:40.728683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34252 11:48:40.759859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34254 11:48:40.760500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34255 11:48:40.792617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34256 11:48:40.793084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34258 11:48:40.828857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34260 11:48:40.829330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34261 11:48:40.861769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34262 11:48:40.862187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34264 11:48:40.893941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34265 11:48:40.894350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34267 11:48:40.926346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34269 11:48:40.926780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34270 11:48:40.958250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34271 11:48:40.958668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34273 11:48:40.990730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34275 11:48:40.991318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34276 11:48:41.023635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34278 11:48:41.024282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34279 11:48:41.055545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34281 11:48:41.056110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34282 11:48:41.087381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34284 11:48:41.087942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34285 11:48:41.119213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34286 11:48:41.119646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34288 11:48:41.151132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34289 11:48:41.151582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34291 11:48:41.182646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34292 11:48:41.183097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34294 11:48:41.214667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34295 11:48:41.215147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34297 11:48:41.246747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34299 11:48:41.247221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34300 11:48:41.278204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34301 11:48:41.278671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34303 11:48:41.309519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34305 11:48:41.310090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34306 11:48:41.343447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34308 11:48:41.344030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34309 11:48:41.381596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34310 11:48:41.382022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34312 11:48:41.414776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34314 11:48:41.415233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34315 11:48:41.447002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34316 11:48:41.447429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34318 11:48:41.479113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34319 11:48:41.479542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34321 11:48:41.515100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34322 11:48:41.515588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34324 11:48:41.561855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34325 11:48:41.562330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34327 11:48:41.598077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34328 11:48:41.598520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34330 11:48:41.636104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34332 11:48:41.636738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34333 11:48:41.673253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34335 11:48:41.673891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34336 11:48:41.707042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34337 11:48:41.707499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34339 11:48:41.739909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34341 11:48:41.740529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34342 11:48:41.771841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34344 11:48:41.772575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34345 11:48:41.805505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34347 11:48:41.806069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34348 11:48:41.838062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34349 11:48:41.838630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34351 11:48:41.871229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34353 11:48:41.871789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34354 11:48:41.906835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34355 11:48:41.907207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34357 11:48:41.945748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34358 11:48:41.946139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34360 11:48:41.982379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34361 11:48:41.982851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34363 11:48:42.014060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34365 11:48:42.014633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34366 11:48:42.045622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34368 11:48:42.046097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34369 11:48:42.076862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34370 11:48:42.077352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34372 11:48:42.113603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34373 11:48:42.114085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34375 11:48:42.174679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34376 11:48:42.175104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34378 11:48:42.209819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34379 11:48:42.210238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34381 11:48:42.243797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34383 11:48:42.244452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34384 11:48:42.279220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34385 11:48:42.279661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34387 11:48:42.313914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34388 11:48:42.314349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34390 11:48:42.348683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34391 11:48:42.349138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34393 11:48:42.385571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34395 11:48:42.386212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34396 11:48:42.420389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34397 11:48:42.420845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34399 11:48:42.454116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34400 11:48:42.454575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34402 11:48:42.487917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34404 11:48:42.488521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34405 11:48:42.524887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34407 11:48:42.525368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34408 11:48:42.558431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34409 11:48:42.558848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34411 11:48:42.592585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34413 11:48:42.593063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34414 11:48:42.626824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34416 11:48:42.627277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34417 11:48:42.661606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34418 11:48:42.662068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34420 11:48:42.696135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34422 11:48:42.696768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34423 11:48:42.731022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34424 11:48:42.731480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34426 11:48:42.765556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34427 11:48:42.766004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34429 11:48:42.799875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34431 11:48:42.800408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34432 11:48:42.834852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34433 11:48:42.835306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34435 11:48:42.868759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34436 11:48:42.869205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34438 11:48:42.902525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34439 11:48:42.902962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34441 11:48:42.936446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34443 11:48:42.937077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34444 11:48:42.969781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34445 11:48:42.970268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34447 11:48:43.003773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34449 11:48:43.004249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34450 11:48:43.038199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34451 11:48:43.038611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34453 11:48:43.073205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34454 11:48:43.073686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34456 11:48:43.107214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34457 11:48:43.107675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34459 11:48:43.141286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34460 11:48:43.141760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34462 11:48:43.175403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34463 11:48:43.175842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34465 11:48:43.209015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34466 11:48:43.209448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34468 11:48:43.243086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34469 11:48:43.243566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34471 11:48:43.277250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34472 11:48:43.277693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34474 11:48:43.310735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34475 11:48:43.311194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34477 11:48:43.345249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34478 11:48:43.345694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34480 11:48:43.378901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34482 11:48:43.379369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34483 11:48:43.413256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34484 11:48:43.413687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34486 11:48:43.447265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34488 11:48:43.447728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34489 11:48:43.481971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34490 11:48:43.482386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34492 11:48:43.516716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34493 11:48:43.517151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34495 11:48:43.551113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34497 11:48:43.551587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34498 11:48:43.585670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34499 11:48:43.586139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34501 11:48:43.621064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34503 11:48:43.621730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34504 11:48:43.655166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34505 11:48:43.655577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34507 11:48:43.689935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34508 11:48:43.690346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34510 11:48:43.724541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34512 11:48:43.725168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34513 11:48:43.758093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34514 11:48:43.758563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34516 11:48:43.792408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34517 11:48:43.792866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34519 11:48:43.826233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34520 11:48:43.826672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34522 11:48:43.860580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34524 11:48:43.861175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34525 11:48:43.894760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34526 11:48:43.895199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34528 11:48:43.929291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34529 11:48:43.929785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34531 11:48:43.963571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34532 11:48:43.964015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34534 11:48:43.998174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34536 11:48:43.998641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34537 11:48:44.032742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34538 11:48:44.033155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34540 11:48:44.067467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34542 11:48:44.067929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34543 11:48:44.102221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34545 11:48:44.102680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34546 11:48:44.136869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34547 11:48:44.137285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34549 11:48:44.172823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34551 11:48:44.173401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34552 11:48:44.206650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34554 11:48:44.207104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34555 11:48:44.241146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34556 11:48:44.241568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34558 11:48:44.275143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34559 11:48:44.275558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34561 11:48:44.309474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34562 11:48:44.309949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34564 11:48:44.345189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34565 11:48:44.345600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34567 11:48:44.379700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34569 11:48:44.380264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34570 11:48:44.414760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34572 11:48:44.415211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34573 11:48:44.449716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34574 11:48:44.450173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34576 11:48:44.483774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34578 11:48:44.484332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34579 11:48:44.518305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34580 11:48:44.518815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34582 11:48:44.553383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34583 11:48:44.553809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34585 11:48:44.588890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34586 11:48:44.589361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34588 11:48:44.623963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34590 11:48:44.624598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34591 11:48:44.658361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34592 11:48:44.658833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34594 11:48:44.692572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34595 11:48:44.692919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34597 11:48:44.727135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34598 11:48:44.727592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34600 11:48:44.761334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34601 11:48:44.761759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34603 11:48:44.795439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34604 11:48:44.795910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34606 11:48:44.829473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34607 11:48:44.829966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34609 11:48:44.863538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34610 11:48:44.864003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34612 11:48:44.897121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34613 11:48:44.897581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34615 11:48:44.931754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34617 11:48:44.932304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34618 11:48:44.965479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34620 11:48:44.966046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34621 11:48:44.999085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34622 11:48:44.999546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34624 11:48:45.033142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34625 11:48:45.033608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34627 11:48:45.036342 + set +x
34628 11:48:45.036550 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 615224_1.1.3.5>
34629 11:48:45.036910 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 615224_1.1.3.5
34630 11:48:45.037062 Ending use of test pattern.
34631 11:48:45.037211 Ending test lava.1_kselftest-arm64_qemu (615224_1.1.3.5), duration 330.70
34633 11:48:45.039235 <LAVA_TEST_RUNNER EXIT>
34634 11:48:45.039588 ok: lava_test_shell seems to have completed
34635 11:48:45.130610 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34636 11:48:45.133779 end: 3.1 lava-test-shell (duration 00:05:32) [common]
34637 11:48:45.133907 end: 3 lava-test-retry (duration 00:05:32) [common]
34638 11:48:45.134014 start: 4 finalize (timeout 00:03:22) [common]
34639 11:48:45.134116 start: 4.1 power-off (timeout 00:00:30) [common]
34640 11:48:45.134215 end: 4.1 power-off (duration 00:00:00) [common]
34641 11:48:45.134314 start: 4.2 read-feedback (timeout 00:03:22) [common]
34642 11:48:45.134509 Listened to connection for namespace 'common' for up to 1s
34643 11:48:45.134798 Listened to connection for namespace 'common' for up to 1s
34644 11:48:46.137748 Finalising connection for namespace 'common'
34646 11:48:46.238743 / # poweroff
34647 11:48:46.239293 Already disconnected
34648 11:48:46.239453 poweroff
34649 11:48:46.340324 end: 4.2 read-feedback (duration 00:00:01) [common]
34650 11:48:46.340610 Already disconnected
34651 11:48:46.340776 end: 4 finalize (duration 00:00:01) [common]
34652 11:48:46.340951 Cleaning after the job
34653 11:48:46.341142 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/615224/deployimages-s0kp_k2_/kernel
34654 11:48:46.348393 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/615224/deployimages-s0kp_k2_/ramdisk
34655 11:48:46.365357 Stopping the qemu container lava-docker-qemu-615224-2.1.1-m890tun4wp
34656 11:48:47.535031 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/615224
34657 11:48:47.625972 Job finished correctly