Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 24
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 25
- Warnings: 1
1 12:46:11.443197 lava-dispatcher, installed at version: 2023.05.1
2 12:46:11.443419 start: 0 validate
3 12:46:11.443554 Start time: 2023-07-20 12:46:11.443547+00:00 (UTC)
4 12:46:11.443691 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:46:11.443819 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:46:11.711224 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:46:11.711421 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:46:35.976194 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:46:35.976371 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:46:36.241853 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:46:36.242128 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.38-cip1-7-g5cff59cac977b%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:46:42.006829 validate duration: 30.56
14 12:46:42.007105 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:46:42.007208 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:46:42.007298 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:46:42.007422 Not decompressing ramdisk as can be used compressed.
18 12:46:42.007508 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 12:46:42.007574 saving as /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/ramdisk/rootfs.cpio.gz
20 12:46:42.007636 total size: 8181372 (7MB)
21 12:46:42.357910 progress 0% (0MB)
22 12:46:42.361192 progress 5% (0MB)
23 12:46:42.365644 progress 10% (0MB)
24 12:46:42.369047 progress 15% (1MB)
25 12:46:42.373941 progress 20% (1MB)
26 12:46:42.378073 progress 25% (1MB)
27 12:46:42.380992 progress 30% (2MB)
28 12:46:42.385630 progress 35% (2MB)
29 12:46:42.389604 progress 40% (3MB)
30 12:46:42.393283 progress 45% (3MB)
31 12:46:42.398099 progress 50% (3MB)
32 12:46:42.403703 progress 55% (4MB)
33 12:46:42.407178 progress 60% (4MB)
34 12:46:42.412740 progress 65% (5MB)
35 12:46:42.416095 progress 70% (5MB)
36 12:46:42.418986 progress 75% (5MB)
37 12:46:42.424775 progress 80% (6MB)
38 12:46:42.428589 progress 85% (6MB)
39 12:46:42.432186 progress 90% (7MB)
40 12:46:42.436184 progress 95% (7MB)
41 12:46:42.441015 progress 100% (7MB)
42 12:46:42.441359 7MB downloaded in 0.43s (17.99MB/s)
43 12:46:42.441612 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:46:42.442053 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:46:42.442200 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:46:42.442346 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:46:42.442532 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:46:42.442659 saving as /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/kernel/Image
50 12:46:42.442768 total size: 48564736 (46MB)
51 12:46:42.442882 No compression specified
52 12:46:42.590470 progress 0% (0MB)
53 12:46:42.773339 progress 5% (2MB)
54 12:46:42.786315 progress 10% (4MB)
55 12:46:42.799261 progress 15% (6MB)
56 12:46:42.812390 progress 20% (9MB)
57 12:46:42.825494 progress 25% (11MB)
58 12:46:42.837747 progress 30% (13MB)
59 12:46:42.850060 progress 35% (16MB)
60 12:46:42.863034 progress 40% (18MB)
61 12:46:42.875320 progress 45% (20MB)
62 12:46:42.887907 progress 50% (23MB)
63 12:46:42.900057 progress 55% (25MB)
64 12:46:42.912689 progress 60% (27MB)
65 12:46:42.927267 progress 65% (30MB)
66 12:46:42.941949 progress 70% (32MB)
67 12:46:42.956386 progress 75% (34MB)
68 12:46:43.002701 progress 80% (37MB)
69 12:46:43.016484 progress 85% (39MB)
70 12:46:43.029927 progress 90% (41MB)
71 12:46:43.043498 progress 95% (44MB)
72 12:46:43.253374 progress 100% (46MB)
73 12:46:43.253613 46MB downloaded in 0.81s (57.12MB/s)
74 12:46:43.253887 end: 1.2.1 http-download (duration 00:00:01) [common]
76 12:46:43.254310 end: 1.2 download-retry (duration 00:00:01) [common]
77 12:46:43.254460 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:46:43.254640 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:46:44.087129 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:46:44.087315 saving as /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/dtb/mt8192-asurada-spherion-r0.dtb
81 12:46:44.087437 total size: 46924 (0MB)
82 12:46:44.087509 No compression specified
83 12:46:44.109666 progress 69% (0MB)
84 12:46:44.110038 progress 100% (0MB)
85 12:46:44.110259 0MB downloaded in 0.02s (1.96MB/s)
86 12:46:44.110481 end: 1.3.1 http-download (duration 00:00:01) [common]
88 12:46:44.110898 end: 1.3 download-retry (duration 00:00:01) [common]
89 12:46:44.111045 start: 1.4 download-retry (timeout 00:09:58) [common]
90 12:46:44.111192 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 12:46:44.111397 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.38-cip1-7-g5cff59cac977b/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:46:44.111492 saving as /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/modules/modules.tar
93 12:46:44.111600 total size: 8543056 (8MB)
94 12:46:44.111692 Using unxz to decompress xz
95 12:46:44.115682 progress 0% (0MB)
96 12:46:44.138841 progress 5% (0MB)
97 12:46:44.165560 progress 10% (0MB)
98 12:46:44.191165 progress 15% (1MB)
99 12:46:44.219620 progress 20% (1MB)
100 12:46:44.246283 progress 25% (2MB)
101 12:46:44.273024 progress 30% (2MB)
102 12:46:44.299108 progress 35% (2MB)
103 12:46:44.325712 progress 40% (3MB)
104 12:46:44.351185 progress 45% (3MB)
105 12:46:44.375017 progress 50% (4MB)
106 12:46:44.400129 progress 55% (4MB)
107 12:46:44.425008 progress 60% (4MB)
108 12:46:44.450304 progress 65% (5MB)
109 12:46:44.489459 progress 70% (5MB)
110 12:46:44.526447 progress 75% (6MB)
111 12:46:44.559868 progress 80% (6MB)
112 12:46:44.588070 progress 85% (6MB)
113 12:46:44.613693 progress 90% (7MB)
114 12:46:44.639392 progress 95% (7MB)
115 12:46:44.668676 progress 100% (8MB)
116 12:46:44.676787 8MB downloaded in 0.57s (14.42MB/s)
117 12:46:44.677235 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:46:44.677643 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:46:44.677786 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 12:46:44.677928 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 12:46:44.678056 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:46:44.678187 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 12:46:44.678481 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9
125 12:46:44.678673 makedir: /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin
126 12:46:44.678828 makedir: /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/tests
127 12:46:44.678977 makedir: /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/results
128 12:46:44.679140 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-add-keys
129 12:46:44.679346 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-add-sources
130 12:46:44.679530 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-background-process-start
131 12:46:44.679715 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-background-process-stop
132 12:46:44.679896 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-common-functions
133 12:46:44.680077 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-echo-ipv4
134 12:46:44.680262 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-install-packages
135 12:46:44.680447 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-installed-packages
136 12:46:44.680630 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-os-build
137 12:46:44.680820 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-probe-channel
138 12:46:44.681002 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-probe-ip
139 12:46:44.681190 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-target-ip
140 12:46:44.681370 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-target-mac
141 12:46:44.681552 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-target-storage
142 12:46:44.681736 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-test-case
143 12:46:44.681917 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-test-event
144 12:46:44.682096 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-test-feedback
145 12:46:44.682279 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-test-raise
146 12:46:44.682460 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-test-reference
147 12:46:44.682643 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-test-runner
148 12:46:44.682822 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-test-set
149 12:46:44.683007 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-test-shell
150 12:46:44.683192 Updating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-install-packages (oe)
151 12:46:45.584917 Updating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/bin/lava-installed-packages (oe)
152 12:46:46.388625 Creating /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/environment
153 12:46:46.388886 LAVA metadata
154 12:46:46.389044 - LAVA_JOB_ID=11118917
155 12:46:46.389165 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:46:46.389360 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 12:46:46.389477 skipped lava-vland-overlay
158 12:46:46.389617 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:46:46.389759 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 12:46:46.389868 skipped lava-multinode-overlay
161 12:46:46.390000 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:46:46.390142 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 12:46:46.390269 Loading test definitions
164 12:46:46.390431 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 12:46:46.390559 Using /lava-11118917 at stage 0
166 12:46:46.391079 uuid=11118917_1.5.2.3.1 testdef=None
167 12:46:46.391246 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:46:46.391405 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 12:46:46.392313 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:46:46.392717 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 12:46:46.393813 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:46:46.394233 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 12:46:48.195401 runner path: /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/0/tests/0_dmesg test_uuid 11118917_1.5.2.3.1
176 12:46:48.195617 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:02) [common]
178 12:46:48.195876 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:54) [common]
179 12:46:48.195962 Using /lava-11118917 at stage 1
180 12:46:48.196743 uuid=11118917_1.5.2.3.5 testdef=None
181 12:46:48.196851 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 12:46:48.196940 start: 1.5.2.3.6 test-overlay (timeout 00:09:54) [common]
183 12:46:48.197445 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 12:46:48.197674 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:54) [common]
186 12:46:48.969007 end: 1.5.2.3.7 test-install-overlay (duration 00:00:01) [common]
188 12:46:48.969504 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:53) [common]
189 12:46:48.970571 runner path: /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/1/tests/1_bootrr test_uuid 11118917_1.5.2.3.5
190 12:46:48.970815 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 12:46:48.971205 Creating lava-test-runner.conf files
193 12:46:48.971323 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/0 for stage 0
194 12:46:48.971481 - 0_dmesg
195 12:46:48.971613 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11118917/lava-overlay-_r31a0m9/lava-11118917/1 for stage 1
196 12:46:48.971762 - 1_bootrr
197 12:46:48.971925 end: 1.5.2.3 test-definition (duration 00:00:03) [common]
198 12:46:48.972065 start: 1.5.2.4 compress-overlay (timeout 00:09:53) [common]
199 12:46:48.982852 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 12:46:48.983011 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
201 12:46:48.983108 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 12:46:48.983204 end: 1.5.2 lava-overlay (duration 00:00:04) [common]
203 12:46:48.983300 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
204 12:46:49.241801 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 12:46:49.242256 start: 1.5.4 extract-modules (timeout 00:09:53) [common]
206 12:46:49.242407 extracting modules file /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11118917/extract-overlay-ramdisk-1g49xbuv/ramdisk
207 12:46:49.504824 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 12:46:49.505055 start: 1.5.5 apply-overlay-tftp (timeout 00:09:53) [common]
209 12:46:49.505154 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11118917/compress-overlay-1txvmz64/overlay-1.5.2.4.tar.gz to ramdisk
210 12:46:49.505226 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11118917/compress-overlay-1txvmz64/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11118917/extract-overlay-ramdisk-1g49xbuv/ramdisk
211 12:46:49.514223 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 12:46:49.514360 start: 1.5.6 configure-preseed-file (timeout 00:09:52) [common]
213 12:46:49.514455 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 12:46:49.514548 start: 1.5.7 compress-ramdisk (timeout 00:09:52) [common]
215 12:46:49.514651 Building ramdisk /var/lib/lava/dispatcher/tmp/11118917/extract-overlay-ramdisk-1g49xbuv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11118917/extract-overlay-ramdisk-1g49xbuv/ramdisk
216 12:46:49.941282 >> 143765 blocks
217 12:46:52.339949 rename /var/lib/lava/dispatcher/tmp/11118917/extract-overlay-ramdisk-1g49xbuv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/ramdisk/ramdisk.cpio.gz
218 12:46:52.340500 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 12:46:52.340691 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
220 12:46:52.340870 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
221 12:46:52.341048 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/kernel/Image'
222 12:47:05.653184 Returned 0 in 13 seconds
223 12:47:05.753779 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/kernel/image.itb
224 12:47:06.145606 output: FIT description: Kernel Image image with one or more FDT blobs
225 12:47:06.146008 output: Created: Thu Jul 20 13:47:06 2023
226 12:47:06.146130 output: Image 0 (kernel-1)
227 12:47:06.146245 output: Description:
228 12:47:06.146343 output: Created: Thu Jul 20 13:47:06 2023
229 12:47:06.146450 output: Type: Kernel Image
230 12:47:06.146555 output: Compression: lzma compressed
231 12:47:06.146663 output: Data Size: 10808178 Bytes = 10554.86 KiB = 10.31 MiB
232 12:47:06.146772 output: Architecture: AArch64
233 12:47:06.146868 output: OS: Linux
234 12:47:06.146958 output: Load Address: 0x00000000
235 12:47:06.147046 output: Entry Point: 0x00000000
236 12:47:06.147132 output: Hash algo: crc32
237 12:47:06.147238 output: Hash value: 96f4d49d
238 12:47:06.147330 output: Image 1 (fdt-1)
239 12:47:06.147415 output: Description: mt8192-asurada-spherion-r0
240 12:47:06.147500 output: Created: Thu Jul 20 13:47:06 2023
241 12:47:06.147586 output: Type: Flat Device Tree
242 12:47:06.147671 output: Compression: uncompressed
243 12:47:06.147756 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
244 12:47:06.147842 output: Architecture: AArch64
245 12:47:06.147927 output: Hash algo: crc32
246 12:47:06.148041 output: Hash value: 1df858fa
247 12:47:06.148153 output: Image 2 (ramdisk-1)
248 12:47:06.148265 output: Description: unavailable
249 12:47:06.148367 output: Created: Thu Jul 20 13:47:06 2023
250 12:47:06.148458 output: Type: RAMDisk Image
251 12:47:06.148543 output: Compression: Unknown Compression
252 12:47:06.148627 output: Data Size: 21238782 Bytes = 20741.00 KiB = 20.25 MiB
253 12:47:06.148713 output: Architecture: AArch64
254 12:47:06.148824 output: OS: Linux
255 12:47:06.148909 output: Load Address: unavailable
256 12:47:06.148992 output: Entry Point: unavailable
257 12:47:06.149089 output: Hash algo: crc32
258 12:47:06.149146 output: Hash value: 0e0ca45e
259 12:47:06.149201 output: Default Configuration: 'conf-1'
260 12:47:06.149255 output: Configuration 0 (conf-1)
261 12:47:06.149310 output: Description: mt8192-asurada-spherion-r0
262 12:47:06.149365 output: Kernel: kernel-1
263 12:47:06.149418 output: Init Ramdisk: ramdisk-1
264 12:47:06.149472 output: FDT: fdt-1
265 12:47:06.149526 output: Loadables: kernel-1
266 12:47:06.149580 output:
267 12:47:06.149783 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 12:47:06.149884 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 12:47:06.149999 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
270 12:47:06.150142 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
271 12:47:06.150238 No LXC device requested
272 12:47:06.150323 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 12:47:06.150427 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
274 12:47:06.150521 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 12:47:06.150597 Checking files for TFTP limit of 4294967296 bytes.
276 12:47:06.151148 end: 1 tftp-deploy (duration 00:00:24) [common]
277 12:47:06.151273 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 12:47:06.151376 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 12:47:06.151520 substitutions:
280 12:47:06.151592 - {DTB}: 11118917/tftp-deploy-8e110p6p/dtb/mt8192-asurada-spherion-r0.dtb
281 12:47:06.151666 - {INITRD}: 11118917/tftp-deploy-8e110p6p/ramdisk/ramdisk.cpio.gz
282 12:47:06.151731 - {KERNEL}: 11118917/tftp-deploy-8e110p6p/kernel/Image
283 12:47:06.151791 - {LAVA_MAC}: None
284 12:47:06.151894 - {PRESEED_CONFIG}: None
285 12:47:06.152000 - {PRESEED_LOCAL}: None
286 12:47:06.152059 - {RAMDISK}: 11118917/tftp-deploy-8e110p6p/ramdisk/ramdisk.cpio.gz
287 12:47:06.152116 - {ROOT_PART}: None
288 12:47:06.152188 - {ROOT}: None
289 12:47:06.152246 - {SERVER_IP}: 192.168.201.1
290 12:47:06.152301 - {TEE}: None
291 12:47:06.152357 Parsed boot commands:
292 12:47:06.152412 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 12:47:06.152636 Parsed boot commands: tftpboot 192.168.201.1 11118917/tftp-deploy-8e110p6p/kernel/image.itb 11118917/tftp-deploy-8e110p6p/kernel/cmdline
294 12:47:06.152768 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 12:47:06.152866 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 12:47:06.153001 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 12:47:06.153128 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 12:47:06.153224 Not connected, no need to disconnect.
299 12:47:06.153331 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 12:47:06.153450 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 12:47:06.153533 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
302 12:47:06.157897 Setting prompt string to ['lava-test: # ']
303 12:47:06.158512 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 12:47:06.158626 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 12:47:06.158738 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 12:47:06.158829 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 12:47:06.159051 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
308 12:47:11.295803 >> Command sent successfully.
309 12:47:11.298123 Returned 0 in 5 seconds
310 12:47:11.398556 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 12:47:11.398906 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 12:47:11.399019 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 12:47:11.399115 Setting prompt string to 'Starting depthcharge on Spherion...'
315 12:47:11.399188 Changing prompt to 'Starting depthcharge on Spherion...'
316 12:47:11.399260 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 12:47:11.399522 [Enter `^Ec?' for help]
318 12:47:11.575046
319 12:47:11.575218
320 12:47:11.575311 F0: 102B 0000
321 12:47:11.575420
322 12:47:11.575482 F3: 1001 0000 [0200]
323 12:47:11.578081
324 12:47:11.578174 F3: 1001 0000
325 12:47:11.578243
326 12:47:11.578308 F7: 102D 0000
327 12:47:11.578370
328 12:47:11.581548 F1: 0000 0000
329 12:47:11.581655
330 12:47:11.581724 V0: 0000 0000 [0001]
331 12:47:11.581787
332 12:47:11.585280 00: 0007 8000
333 12:47:11.585376
334 12:47:11.585443 01: 0000 0000
335 12:47:11.585508
336 12:47:11.588412 BP: 0C00 0209 [0000]
337 12:47:11.588514
338 12:47:11.588585 G0: 1182 0000
339 12:47:11.588650
340 12:47:11.591872 EC: 0000 0021 [4000]
341 12:47:11.591966
342 12:47:11.592035 S7: 0000 0000 [0000]
343 12:47:11.592100
344 12:47:11.595292 CC: 0000 0000 [0001]
345 12:47:11.595401
346 12:47:11.595470 T0: 0000 0040 [010F]
347 12:47:11.595551
348 12:47:11.595627 Jump to BL
349 12:47:11.598573
350 12:47:11.622727
351 12:47:11.622933
352 12:47:11.623060
353 12:47:11.629693 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 12:47:11.633335 ARM64: Exception handlers installed.
355 12:47:11.636893 ARM64: Testing exception
356 12:47:11.639865 ARM64: Done test exception
357 12:47:11.646584 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 12:47:11.657116 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 12:47:11.664103 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 12:47:11.673667 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 12:47:11.680573 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 12:47:11.687162 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 12:47:11.699117 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 12:47:11.705940 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 12:47:11.725162 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 12:47:11.728406 WDT: Last reset was cold boot
367 12:47:11.731540 SPI1(PAD0) initialized at 2873684 Hz
368 12:47:11.734986 SPI5(PAD0) initialized at 992727 Hz
369 12:47:11.738031 VBOOT: Loading verstage.
370 12:47:11.745018 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 12:47:11.748304 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 12:47:11.751550 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 12:47:11.754752 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 12:47:11.762552 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 12:47:11.768878 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 12:47:11.780277 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
377 12:47:11.780415
378 12:47:11.780489
379 12:47:11.868404 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 12:47:11.868588 ARM64: Exception handlers installed.
381 12:47:11.868698 ARM64: Testing exception
382 12:47:11.868794 ARM64: Done test exception
383 12:47:11.868859 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 12:47:11.868922 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 12:47:11.868984 Probing TPM: . done!
386 12:47:11.869043 TPM ready after 0 ms
387 12:47:11.869101 Connected to device vid:did:rid of 1ae0:0028:00
388 12:47:11.869159 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 12:47:11.892298 Initialized TPM device CR50 revision 0
390 12:47:11.904120 tlcl_send_startup: Startup return code is 0
391 12:47:11.904310 TPM: setup succeeded
392 12:47:11.915407 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 12:47:11.924572 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 12:47:11.934497 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 12:47:11.943813 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 12:47:11.947067 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 12:47:11.953479 in-header: 03 07 00 00 08 00 00 00
398 12:47:11.956877 in-data: aa e4 47 04 13 02 00 00
399 12:47:11.960594 Chrome EC: UHEPI supported
400 12:47:11.968209 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 12:47:11.971870 in-header: 03 ad 00 00 08 00 00 00
402 12:47:11.975827 in-data: 00 20 20 08 00 00 00 00
403 12:47:11.975977 Phase 1
404 12:47:11.979077 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 12:47:11.986296 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 12:47:11.990351 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 12:47:11.994003 Recovery requested (1009000e)
408 12:47:12.002744 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 12:47:12.008763 tlcl_extend: response is 0
410 12:47:12.017973 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 12:47:12.023387 tlcl_extend: response is 0
412 12:47:12.030216 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 12:47:12.050590 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 12:47:12.057673 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 12:47:12.057863
416 12:47:12.057978
417 12:47:12.067745 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 12:47:12.071024 ARM64: Exception handlers installed.
419 12:47:12.071185 ARM64: Testing exception
420 12:47:12.074375 ARM64: Done test exception
421 12:47:12.096224 pmic_efuse_setting: Set efuses in 11 msecs
422 12:47:12.099500 pmwrap_interface_init: Select PMIF_VLD_RDY
423 12:47:12.106457 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 12:47:12.109629 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 12:47:12.113378 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 12:47:12.119852 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 12:47:12.123242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 12:47:12.130693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 12:47:12.134140 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 12:47:12.137647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 12:47:12.141490 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 12:47:12.149112 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 12:47:12.152695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 12:47:12.156407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 12:47:12.162670 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 12:47:12.169441 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 12:47:12.172796 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 12:47:12.179786 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 12:47:12.183630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 12:47:12.190998 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 12:47:12.194713 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 12:47:12.201490 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 12:47:12.208833 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 12:47:12.211959 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 12:47:12.218791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 12:47:12.225328 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 12:47:12.228684 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 12:47:12.235561 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 12:47:12.238630 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 12:47:12.245521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 12:47:12.248427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 12:47:12.255136 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 12:47:12.258779 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 12:47:12.265339 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 12:47:12.268449 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 12:47:12.275440 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 12:47:12.278737 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 12:47:12.285554 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 12:47:12.288624 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 12:47:12.295648 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 12:47:12.298761 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 12:47:12.302388 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 12:47:12.306485 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 12:47:12.313362 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 12:47:12.316708 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 12:47:12.319990 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 12:47:12.326471 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 12:47:12.330038 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 12:47:12.333802 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 12:47:12.336546 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 12:47:12.343277 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 12:47:12.346719 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 12:47:12.350012 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 12:47:12.360358 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 12:47:12.366741 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 12:47:12.369879 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 12:47:12.381175 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 12:47:12.388709 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 12:47:12.392153 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 12:47:12.395989 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 12:47:12.403582 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 12:47:12.407213 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x8
483 12:47:12.414504 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 12:47:12.418401 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 12:47:12.421986 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 12:47:12.433193 [RTC]rtc_get_frequency_meter,154: input=15, output=772
487 12:47:12.443042 [RTC]rtc_get_frequency_meter,154: input=23, output=957
488 12:47:12.451820 [RTC]rtc_get_frequency_meter,154: input=19, output=865
489 12:47:12.461442 [RTC]rtc_get_frequency_meter,154: input=17, output=820
490 12:47:12.471026 [RTC]rtc_get_frequency_meter,154: input=16, output=796
491 12:47:12.474292 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
492 12:47:12.480986 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
493 12:47:12.484302 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
494 12:47:12.487633 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
495 12:47:12.490954 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
496 12:47:12.494381 ADC[4]: Raw value=902139 ID=7
497 12:47:12.498063 ADC[3]: Raw value=213179 ID=1
498 12:47:12.498246 RAM Code: 0x71
499 12:47:12.506035 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
500 12:47:12.509866 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
501 12:47:12.517117 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
502 12:47:12.523339 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
503 12:47:12.526806 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
504 12:47:12.529927 in-header: 03 07 00 00 08 00 00 00
505 12:47:12.533621 in-data: aa e4 47 04 13 02 00 00
506 12:47:12.536961 Chrome EC: UHEPI supported
507 12:47:12.543592 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
508 12:47:12.547033 in-header: 03 ed 00 00 08 00 00 00
509 12:47:12.550020 in-data: 80 20 60 08 00 00 00 00
510 12:47:12.553481 MRC: failed to locate region type 0.
511 12:47:12.560183 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
512 12:47:12.563455 DRAM-K: Running full calibration
513 12:47:12.570021 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
514 12:47:12.570209 header.status = 0x0
515 12:47:12.573474 header.version = 0x6 (expected: 0x6)
516 12:47:12.576783 header.size = 0xd00 (expected: 0xd00)
517 12:47:12.580363 header.flags = 0x0
518 12:47:12.586635 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
519 12:47:12.603070 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
520 12:47:12.609833 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
521 12:47:12.612974 dram_init: ddr_geometry: 2
522 12:47:12.616682 [EMI] MDL number = 2
523 12:47:12.616898 [EMI] Get MDL freq = 0
524 12:47:12.619573 dram_init: ddr_type: 0
525 12:47:12.619746 is_discrete_lpddr4: 1
526 12:47:12.622966 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
527 12:47:12.623142
528 12:47:12.623266
529 12:47:12.626458 [Bian_co] ETT version 0.0.0.1
530 12:47:12.633025 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
531 12:47:12.633236
532 12:47:12.636425 dramc_set_vcore_voltage set vcore to 650000
533 12:47:12.636605 Read voltage for 800, 4
534 12:47:12.640035 Vio18 = 0
535 12:47:12.640219 Vcore = 650000
536 12:47:12.640350 Vdram = 0
537 12:47:12.643594 Vddq = 0
538 12:47:12.643725 Vmddr = 0
539 12:47:12.646607 dram_init: config_dvfs: 1
540 12:47:12.650004 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
541 12:47:12.656624 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
542 12:47:12.660032 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
543 12:47:12.663387 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
544 12:47:12.666813 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
545 12:47:12.670167 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
546 12:47:12.673282 MEM_TYPE=3, freq_sel=18
547 12:47:12.676662 sv_algorithm_assistance_LP4_1600
548 12:47:12.680399 ============ PULL DRAM RESETB DOWN ============
549 12:47:12.683386 ========== PULL DRAM RESETB DOWN end =========
550 12:47:12.690120 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
551 12:47:12.693343 ===================================
552 12:47:12.693497 LPDDR4 DRAM CONFIGURATION
553 12:47:12.696983 ===================================
554 12:47:12.700025 EX_ROW_EN[0] = 0x0
555 12:47:12.703304 EX_ROW_EN[1] = 0x0
556 12:47:12.703490 LP4Y_EN = 0x0
557 12:47:12.707133 WORK_FSP = 0x0
558 12:47:12.707331 WL = 0x2
559 12:47:12.709817 RL = 0x2
560 12:47:12.709933 BL = 0x2
561 12:47:12.713430 RPST = 0x0
562 12:47:12.713579 RD_PRE = 0x0
563 12:47:12.716532 WR_PRE = 0x1
564 12:47:12.716656 WR_PST = 0x0
565 12:47:12.719804 DBI_WR = 0x0
566 12:47:12.719933 DBI_RD = 0x0
567 12:47:12.723349 OTF = 0x1
568 12:47:12.726760 ===================================
569 12:47:12.729976 ===================================
570 12:47:12.730097 ANA top config
571 12:47:12.733291 ===================================
572 12:47:12.736973 DLL_ASYNC_EN = 0
573 12:47:12.740194 ALL_SLAVE_EN = 1
574 12:47:12.740322 NEW_RANK_MODE = 1
575 12:47:12.743177 DLL_IDLE_MODE = 1
576 12:47:12.746584 LP45_APHY_COMB_EN = 1
577 12:47:12.750173 TX_ODT_DIS = 1
578 12:47:12.753196 NEW_8X_MODE = 1
579 12:47:12.756766 ===================================
580 12:47:12.756954 ===================================
581 12:47:12.760169 data_rate = 1600
582 12:47:12.763522 CKR = 1
583 12:47:12.766769 DQ_P2S_RATIO = 8
584 12:47:12.770305 ===================================
585 12:47:12.773887 CA_P2S_RATIO = 8
586 12:47:12.777238 DQ_CA_OPEN = 0
587 12:47:12.777421 DQ_SEMI_OPEN = 0
588 12:47:12.780243 CA_SEMI_OPEN = 0
589 12:47:12.783625 CA_FULL_RATE = 0
590 12:47:12.787092 DQ_CKDIV4_EN = 1
591 12:47:12.790299 CA_CKDIV4_EN = 1
592 12:47:12.793533 CA_PREDIV_EN = 0
593 12:47:12.793734 PH8_DLY = 0
594 12:47:12.797071 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
595 12:47:12.800389 DQ_AAMCK_DIV = 4
596 12:47:12.804094 CA_AAMCK_DIV = 4
597 12:47:12.807143 CA_ADMCK_DIV = 4
598 12:47:12.810515 DQ_TRACK_CA_EN = 0
599 12:47:12.810652 CA_PICK = 800
600 12:47:12.814040 CA_MCKIO = 800
601 12:47:12.817269 MCKIO_SEMI = 0
602 12:47:12.820707 PLL_FREQ = 3068
603 12:47:12.824069 DQ_UI_PI_RATIO = 32
604 12:47:12.827403 CA_UI_PI_RATIO = 0
605 12:47:12.830712 ===================================
606 12:47:12.834019 ===================================
607 12:47:12.834138 memory_type:LPDDR4
608 12:47:12.837283 GP_NUM : 10
609 12:47:12.840733 SRAM_EN : 1
610 12:47:12.840853 MD32_EN : 0
611 12:47:12.843963 ===================================
612 12:47:12.847872 [ANA_INIT] >>>>>>>>>>>>>>
613 12:47:12.851717 <<<<<< [CONFIGURE PHASE]: ANA_TX
614 12:47:12.851911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
615 12:47:12.855394 ===================================
616 12:47:12.858920 data_rate = 1600,PCW = 0X7600
617 12:47:12.862940 ===================================
618 12:47:12.867044 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
619 12:47:12.870337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
620 12:47:12.877927 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
621 12:47:12.881585 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
622 12:47:12.884946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
623 12:47:12.888498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
624 12:47:12.891878 [ANA_INIT] flow start
625 12:47:12.892064 [ANA_INIT] PLL >>>>>>>>
626 12:47:12.895214 [ANA_INIT] PLL <<<<<<<<
627 12:47:12.898454 [ANA_INIT] MIDPI >>>>>>>>
628 12:47:12.898620 [ANA_INIT] MIDPI <<<<<<<<
629 12:47:12.901948 [ANA_INIT] DLL >>>>>>>>
630 12:47:12.905348 [ANA_INIT] flow end
631 12:47:12.909409 ============ LP4 DIFF to SE enter ============
632 12:47:12.912712 ============ LP4 DIFF to SE exit ============
633 12:47:12.912900 [ANA_INIT] <<<<<<<<<<<<<
634 12:47:12.916496 [Flow] Enable top DCM control >>>>>
635 12:47:12.920090 [Flow] Enable top DCM control <<<<<
636 12:47:12.924231 Enable DLL master slave shuffle
637 12:47:12.931089 ==============================================================
638 12:47:12.931305 Gating Mode config
639 12:47:12.938695 ==============================================================
640 12:47:12.938846 Config description:
641 12:47:12.949370 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
642 12:47:12.956674 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
643 12:47:12.960667 SELPH_MODE 0: By rank 1: By Phase
644 12:47:12.964223 ==============================================================
645 12:47:12.967949 GAT_TRACK_EN = 1
646 12:47:12.971950 RX_GATING_MODE = 2
647 12:47:12.975462 RX_GATING_TRACK_MODE = 2
648 12:47:12.979972 SELPH_MODE = 1
649 12:47:12.980152 PICG_EARLY_EN = 1
650 12:47:12.983052 VALID_LAT_VALUE = 1
651 12:47:12.990365 ==============================================================
652 12:47:12.994503 Enter into Gating configuration >>>>
653 12:47:12.994698 Exit from Gating configuration <<<<
654 12:47:12.998129 Enter into DVFS_PRE_config >>>>>
655 12:47:13.009379 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
656 12:47:13.012841 Exit from DVFS_PRE_config <<<<<
657 12:47:13.016824 Enter into PICG configuration >>>>
658 12:47:13.020979 Exit from PICG configuration <<<<
659 12:47:13.021172 [RX_INPUT] configuration >>>>>
660 12:47:13.024543 [RX_INPUT] configuration <<<<<
661 12:47:13.031878 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
662 12:47:13.035241 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
663 12:47:13.042686 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
664 12:47:13.047057 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
665 12:47:13.054050 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
666 12:47:13.061578 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
667 12:47:13.065012 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
668 12:47:13.068989 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
669 12:47:13.072847 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
670 12:47:13.076416 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
671 12:47:13.080922 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
672 12:47:13.084161 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 12:47:13.088519 ===================================
674 12:47:13.092270 LPDDR4 DRAM CONFIGURATION
675 12:47:13.096015 ===================================
676 12:47:13.096161 EX_ROW_EN[0] = 0x0
677 12:47:13.099856 EX_ROW_EN[1] = 0x0
678 12:47:13.099971 LP4Y_EN = 0x0
679 12:47:13.100042 WORK_FSP = 0x0
680 12:47:13.103088 WL = 0x2
681 12:47:13.103182 RL = 0x2
682 12:47:13.106919 BL = 0x2
683 12:47:13.107021 RPST = 0x0
684 12:47:13.111118 RD_PRE = 0x0
685 12:47:13.111214 WR_PRE = 0x1
686 12:47:13.114409 WR_PST = 0x0
687 12:47:13.114506 DBI_WR = 0x0
688 12:47:13.117923 DBI_RD = 0x0
689 12:47:13.118016 OTF = 0x1
690 12:47:13.121473 ===================================
691 12:47:13.125531 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
692 12:47:13.128996 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
693 12:47:13.133044 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 12:47:13.136672 ===================================
695 12:47:13.140179 LPDDR4 DRAM CONFIGURATION
696 12:47:13.144238 ===================================
697 12:47:13.144422 EX_ROW_EN[0] = 0x10
698 12:47:13.147665 EX_ROW_EN[1] = 0x0
699 12:47:13.147797 LP4Y_EN = 0x0
700 12:47:13.151497 WORK_FSP = 0x0
701 12:47:13.151613 WL = 0x2
702 12:47:13.154790 RL = 0x2
703 12:47:13.154915 BL = 0x2
704 12:47:13.158098 RPST = 0x0
705 12:47:13.158228 RD_PRE = 0x0
706 12:47:13.162210 WR_PRE = 0x1
707 12:47:13.162355 WR_PST = 0x0
708 12:47:13.165875 DBI_WR = 0x0
709 12:47:13.166035 DBI_RD = 0x0
710 12:47:13.169665 OTF = 0x1
711 12:47:13.173206 ===================================
712 12:47:13.176547 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
713 12:47:13.181382 nWR fixed to 40
714 12:47:13.184897 [ModeRegInit_LP4] CH0 RK0
715 12:47:13.185021 [ModeRegInit_LP4] CH0 RK1
716 12:47:13.188635 [ModeRegInit_LP4] CH1 RK0
717 12:47:13.192443 [ModeRegInit_LP4] CH1 RK1
718 12:47:13.192571 match AC timing 13
719 12:47:13.196244 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
720 12:47:13.200219 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
721 12:47:13.207554 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
722 12:47:13.210967 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
723 12:47:13.214093 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
724 12:47:13.217634 [EMI DOE] emi_dcm 0
725 12:47:13.221148 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
726 12:47:13.221280 ==
727 12:47:13.224131 Dram Type= 6, Freq= 0, CH_0, rank 0
728 12:47:13.227527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
729 12:47:13.227663 ==
730 12:47:13.234284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
731 12:47:13.240981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
732 12:47:13.248905 [CA 0] Center 38 (7~69) winsize 63
733 12:47:13.252216 [CA 1] Center 38 (7~69) winsize 63
734 12:47:13.255657 [CA 2] Center 35 (5~66) winsize 62
735 12:47:13.258966 [CA 3] Center 35 (5~66) winsize 62
736 12:47:13.262199 [CA 4] Center 34 (4~65) winsize 62
737 12:47:13.265289 [CA 5] Center 33 (3~64) winsize 62
738 12:47:13.265405
739 12:47:13.268800 [CmdBusTrainingLP45] Vref(ca) range 1: 32
740 12:47:13.268943
741 12:47:13.272440 [CATrainingPosCal] consider 1 rank data
742 12:47:13.275855 u2DelayCellTimex100 = 270/100 ps
743 12:47:13.279168 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
744 12:47:13.282158 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
745 12:47:13.288926 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
746 12:47:13.292471 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
747 12:47:13.295708 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
748 12:47:13.299173 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
749 12:47:13.299350
750 12:47:13.302673 CA PerBit enable=1, Macro0, CA PI delay=33
751 12:47:13.302816
752 12:47:13.305945 [CBTSetCACLKResult] CA Dly = 33
753 12:47:13.306086 CS Dly: 6 (0~37)
754 12:47:13.306204 ==
755 12:47:13.308921 Dram Type= 6, Freq= 0, CH_0, rank 1
756 12:47:13.315668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
757 12:47:13.315855 ==
758 12:47:13.319428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
759 12:47:13.326131 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
760 12:47:13.335416 [CA 0] Center 38 (7~69) winsize 63
761 12:47:13.338536 [CA 1] Center 38 (8~69) winsize 62
762 12:47:13.342391 [CA 2] Center 36 (6~67) winsize 62
763 12:47:13.345495 [CA 3] Center 35 (5~66) winsize 62
764 12:47:13.349045 [CA 4] Center 35 (4~66) winsize 63
765 12:47:13.352017 [CA 5] Center 34 (4~65) winsize 62
766 12:47:13.352126
767 12:47:13.355529 [CmdBusTrainingLP45] Vref(ca) range 1: 34
768 12:47:13.355675
769 12:47:13.359447 [CATrainingPosCal] consider 2 rank data
770 12:47:13.362197 u2DelayCellTimex100 = 270/100 ps
771 12:47:13.365517 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
772 12:47:13.368850 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
773 12:47:13.375894 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
774 12:47:13.378798 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
775 12:47:13.382149 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
776 12:47:13.385816 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
777 12:47:13.385975
778 12:47:13.389159 CA PerBit enable=1, Macro0, CA PI delay=34
779 12:47:13.389292
780 12:47:13.392460 [CBTSetCACLKResult] CA Dly = 34
781 12:47:13.392604 CS Dly: 6 (0~38)
782 12:47:13.392707
783 12:47:13.395692 ----->DramcWriteLeveling(PI) begin...
784 12:47:13.395822 ==
785 12:47:13.399345 Dram Type= 6, Freq= 0, CH_0, rank 0
786 12:47:13.406126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
787 12:47:13.406299 ==
788 12:47:13.409031 Write leveling (Byte 0): 30 => 30
789 12:47:13.412541 Write leveling (Byte 1): 29 => 29
790 12:47:13.412682 DramcWriteLeveling(PI) end<-----
791 12:47:13.412795
792 12:47:13.415610 ==
793 12:47:13.418820 Dram Type= 6, Freq= 0, CH_0, rank 0
794 12:47:13.422466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
795 12:47:13.422615 ==
796 12:47:13.425792 [Gating] SW mode calibration
797 12:47:13.433291 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
798 12:47:13.437306 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
799 12:47:13.441005 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
800 12:47:13.444876 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
801 12:47:13.451566 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
802 12:47:13.455126 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:47:13.458783 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:47:13.462457 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:47:13.468544 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:47:13.472276 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:47:13.475527 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:47:13.481975 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:47:13.485356 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:47:13.489002 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:47:13.495419 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:47:13.498748 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:47:13.502602 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:47:13.505381 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:47:13.512376 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
816 12:47:13.515733 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
817 12:47:13.518875 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
818 12:47:13.525798 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:47:13.528785 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:47:13.532489 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:47:13.538900 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:47:13.542426 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:47:13.545482 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:47:13.552329 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:47:13.555830 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
826 12:47:13.559241 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
827 12:47:13.565868 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
828 12:47:13.569294 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
829 12:47:13.572816 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
830 12:47:13.575967 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 12:47:13.582444 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 12:47:13.586162 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
833 12:47:13.589452 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
834 12:47:13.595835 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 12:47:13.599374 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 12:47:13.602720 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 12:47:13.609240 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 12:47:13.612794 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 12:47:13.615904 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 12:47:13.622707 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
841 12:47:13.625982 0 11 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
842 12:47:13.629472 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
843 12:47:13.635995 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
844 12:47:13.639673 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
845 12:47:13.642850 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
846 12:47:13.646125 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 12:47:13.653097 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 12:47:13.656413 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
849 12:47:13.659602 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
850 12:47:13.666162 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:47:13.669648 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:47:13.673170 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 12:47:13.679808 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 12:47:13.683175 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:47:13.686529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 12:47:13.693052 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 12:47:13.696343 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 12:47:13.699722 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 12:47:13.706372 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 12:47:13.709968 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 12:47:13.713018 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 12:47:13.716506 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 12:47:13.723762 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 12:47:13.726477 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
865 12:47:13.730259 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
866 12:47:13.733416 Total UI for P1: 0, mck2ui 16
867 12:47:13.736430 best dqsien dly found for B0: ( 0, 14, 4)
868 12:47:13.743526 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 12:47:13.743726 Total UI for P1: 0, mck2ui 16
870 12:47:13.749803 best dqsien dly found for B1: ( 0, 14, 8)
871 12:47:13.753318 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
872 12:47:13.756535 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
873 12:47:13.756691
874 12:47:13.760320 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
875 12:47:13.763331 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
876 12:47:13.766909 [Gating] SW calibration Done
877 12:47:13.767074 ==
878 12:47:13.770326 Dram Type= 6, Freq= 0, CH_0, rank 0
879 12:47:13.773419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
880 12:47:13.773529 ==
881 12:47:13.776987 RX Vref Scan: 0
882 12:47:13.777097
883 12:47:13.777168 RX Vref 0 -> 0, step: 1
884 12:47:13.777231
885 12:47:13.780125 RX Delay -130 -> 252, step: 16
886 12:47:13.783452 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
887 12:47:13.789986 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
888 12:47:13.793507 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
889 12:47:13.796720 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
890 12:47:13.800255 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
891 12:47:13.803571 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
892 12:47:13.807104 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
893 12:47:13.813503 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
894 12:47:13.817006 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
895 12:47:13.820152 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
896 12:47:13.823502 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
897 12:47:13.830295 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
898 12:47:13.833713 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
899 12:47:13.837081 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
900 12:47:13.840556 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
901 12:47:13.843576 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
902 12:47:13.843712 ==
903 12:47:13.847222 Dram Type= 6, Freq= 0, CH_0, rank 0
904 12:47:13.853563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
905 12:47:13.853731 ==
906 12:47:13.853836 DQS Delay:
907 12:47:13.856884 DQS0 = 0, DQS1 = 0
908 12:47:13.857013 DQM Delay:
909 12:47:13.857113 DQM0 = 90, DQM1 = 80
910 12:47:13.860170 DQ Delay:
911 12:47:13.863440 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
912 12:47:13.867402 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
913 12:47:13.870640 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
914 12:47:13.873448 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
915 12:47:13.873598
916 12:47:13.873709
917 12:47:13.873805 ==
918 12:47:13.877022 Dram Type= 6, Freq= 0, CH_0, rank 0
919 12:47:13.880581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 12:47:13.880725 ==
921 12:47:13.880844
922 12:47:13.880939
923 12:47:13.883810 TX Vref Scan disable
924 12:47:13.883952 == TX Byte 0 ==
925 12:47:13.890479 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
926 12:47:13.893948 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
927 12:47:13.894096 == TX Byte 1 ==
928 12:47:13.900980 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
929 12:47:13.903611 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
930 12:47:13.903742 ==
931 12:47:13.906960 Dram Type= 6, Freq= 0, CH_0, rank 0
932 12:47:13.910484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 12:47:13.910622 ==
934 12:47:13.924441 TX Vref=22, minBit 1, minWin=27, winSum=439
935 12:47:13.927693 TX Vref=24, minBit 8, minWin=26, winSum=443
936 12:47:13.931194 TX Vref=26, minBit 8, minWin=27, winSum=448
937 12:47:13.934608 TX Vref=28, minBit 6, minWin=27, winSum=452
938 12:47:13.937944 TX Vref=30, minBit 3, minWin=28, winSum=455
939 12:47:13.940949 TX Vref=32, minBit 5, minWin=28, winSum=456
940 12:47:13.947814 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 32
941 12:47:13.947987
942 12:47:13.950940 Final TX Range 1 Vref 32
943 12:47:13.951065
944 12:47:13.951168 ==
945 12:47:13.954374 Dram Type= 6, Freq= 0, CH_0, rank 0
946 12:47:13.957367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
947 12:47:13.957501 ==
948 12:47:13.961025
949 12:47:13.961159
950 12:47:13.961259 TX Vref Scan disable
951 12:47:13.964066 == TX Byte 0 ==
952 12:47:13.967653 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
953 12:47:13.970974 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
954 12:47:13.974449 == TX Byte 1 ==
955 12:47:13.977895 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
956 12:47:13.980899 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
957 12:47:13.984206
958 12:47:13.984341 [DATLAT]
959 12:47:13.984440 Freq=800, CH0 RK0
960 12:47:13.984537
961 12:47:13.987821 DATLAT Default: 0xa
962 12:47:13.987944 0, 0xFFFF, sum = 0
963 12:47:13.991032 1, 0xFFFF, sum = 0
964 12:47:13.991163 2, 0xFFFF, sum = 0
965 12:47:13.994449 3, 0xFFFF, sum = 0
966 12:47:13.994579 4, 0xFFFF, sum = 0
967 12:47:13.998067 5, 0xFFFF, sum = 0
968 12:47:13.998195 6, 0xFFFF, sum = 0
969 12:47:14.001289 7, 0xFFFF, sum = 0
970 12:47:14.001423 8, 0xFFFF, sum = 0
971 12:47:14.004838 9, 0x0, sum = 1
972 12:47:14.004975 10, 0x0, sum = 2
973 12:47:14.008079 11, 0x0, sum = 3
974 12:47:14.008204 12, 0x0, sum = 4
975 12:47:14.010959 best_step = 10
976 12:47:14.011081
977 12:47:14.011181 ==
978 12:47:14.014355 Dram Type= 6, Freq= 0, CH_0, rank 0
979 12:47:14.017888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 12:47:14.018032 ==
981 12:47:14.021165 RX Vref Scan: 1
982 12:47:14.021300
983 12:47:14.021416 Set Vref Range= 32 -> 127
984 12:47:14.021512
985 12:47:14.024457 RX Vref 32 -> 127, step: 1
986 12:47:14.024581
987 12:47:14.027842 RX Delay -95 -> 252, step: 8
988 12:47:14.027994
989 12:47:14.030991 Set Vref, RX VrefLevel [Byte0]: 32
990 12:47:14.034319 [Byte1]: 32
991 12:47:14.034470
992 12:47:14.037959 Set Vref, RX VrefLevel [Byte0]: 33
993 12:47:14.041176 [Byte1]: 33
994 12:47:14.044777
995 12:47:14.044929 Set Vref, RX VrefLevel [Byte0]: 34
996 12:47:14.047850 [Byte1]: 34
997 12:47:14.052169
998 12:47:14.052303 Set Vref, RX VrefLevel [Byte0]: 35
999 12:47:14.055601 [Byte1]: 35
1000 12:47:14.059840
1001 12:47:14.059971 Set Vref, RX VrefLevel [Byte0]: 36
1002 12:47:14.063559 [Byte1]: 36
1003 12:47:14.067548
1004 12:47:14.067681 Set Vref, RX VrefLevel [Byte0]: 37
1005 12:47:14.070769 [Byte1]: 37
1006 12:47:14.075309
1007 12:47:14.075433 Set Vref, RX VrefLevel [Byte0]: 38
1008 12:47:14.078843 [Byte1]: 38
1009 12:47:14.082579
1010 12:47:14.082739 Set Vref, RX VrefLevel [Byte0]: 39
1011 12:47:14.085940 [Byte1]: 39
1012 12:47:14.090081
1013 12:47:14.090194 Set Vref, RX VrefLevel [Byte0]: 40
1014 12:47:14.093413 [Byte1]: 40
1015 12:47:14.098113
1016 12:47:14.098247 Set Vref, RX VrefLevel [Byte0]: 41
1017 12:47:14.101588 [Byte1]: 41
1018 12:47:14.105866
1019 12:47:14.106009 Set Vref, RX VrefLevel [Byte0]: 42
1020 12:47:14.108914 [Byte1]: 42
1021 12:47:14.113211
1022 12:47:14.113338 Set Vref, RX VrefLevel [Byte0]: 43
1023 12:47:14.116439 [Byte1]: 43
1024 12:47:14.121054
1025 12:47:14.121187 Set Vref, RX VrefLevel [Byte0]: 44
1026 12:47:14.124391 [Byte1]: 44
1027 12:47:14.128845
1028 12:47:14.128975 Set Vref, RX VrefLevel [Byte0]: 45
1029 12:47:14.131824 [Byte1]: 45
1030 12:47:14.135744
1031 12:47:14.135864 Set Vref, RX VrefLevel [Byte0]: 46
1032 12:47:14.138979 [Byte1]: 46
1033 12:47:14.143244
1034 12:47:14.143366 Set Vref, RX VrefLevel [Byte0]: 47
1035 12:47:14.146622 [Byte1]: 47
1036 12:47:14.150954
1037 12:47:14.151073 Set Vref, RX VrefLevel [Byte0]: 48
1038 12:47:14.154282 [Byte1]: 48
1039 12:47:14.158849
1040 12:47:14.158978 Set Vref, RX VrefLevel [Byte0]: 49
1041 12:47:14.161888 [Byte1]: 49
1042 12:47:14.165904
1043 12:47:14.166077 Set Vref, RX VrefLevel [Byte0]: 50
1044 12:47:14.169328 [Byte1]: 50
1045 12:47:14.173855
1046 12:47:14.174013 Set Vref, RX VrefLevel [Byte0]: 51
1047 12:47:14.177143 [Byte1]: 51
1048 12:47:14.181505
1049 12:47:14.181627 Set Vref, RX VrefLevel [Byte0]: 52
1050 12:47:14.184471 [Byte1]: 52
1051 12:47:14.189147
1052 12:47:14.189265 Set Vref, RX VrefLevel [Byte0]: 53
1053 12:47:14.192352 [Byte1]: 53
1054 12:47:14.196315
1055 12:47:14.196430 Set Vref, RX VrefLevel [Byte0]: 54
1056 12:47:14.199653 [Byte1]: 54
1057 12:47:14.204005
1058 12:47:14.204165 Set Vref, RX VrefLevel [Byte0]: 55
1059 12:47:14.207397 [Byte1]: 55
1060 12:47:14.211461
1061 12:47:14.211600 Set Vref, RX VrefLevel [Byte0]: 56
1062 12:47:14.215118 [Byte1]: 56
1063 12:47:14.219266
1064 12:47:14.219423 Set Vref, RX VrefLevel [Byte0]: 57
1065 12:47:14.222761 [Byte1]: 57
1066 12:47:14.226809
1067 12:47:14.226936 Set Vref, RX VrefLevel [Byte0]: 58
1068 12:47:14.230367 [Byte1]: 58
1069 12:47:14.234675
1070 12:47:14.234850 Set Vref, RX VrefLevel [Byte0]: 59
1071 12:47:14.237873 [Byte1]: 59
1072 12:47:14.241914
1073 12:47:14.242087 Set Vref, RX VrefLevel [Byte0]: 60
1074 12:47:14.248421 [Byte1]: 60
1075 12:47:14.248601
1076 12:47:14.251879 Set Vref, RX VrefLevel [Byte0]: 61
1077 12:47:14.255077 [Byte1]: 61
1078 12:47:14.255236
1079 12:47:14.258387 Set Vref, RX VrefLevel [Byte0]: 62
1080 12:47:14.261698 [Byte1]: 62
1081 12:47:14.261841
1082 12:47:14.264968 Set Vref, RX VrefLevel [Byte0]: 63
1083 12:47:14.268301 [Byte1]: 63
1084 12:47:14.272548
1085 12:47:14.272675 Set Vref, RX VrefLevel [Byte0]: 64
1086 12:47:14.276242 [Byte1]: 64
1087 12:47:14.280295
1088 12:47:14.280461 Set Vref, RX VrefLevel [Byte0]: 65
1089 12:47:14.283263 [Byte1]: 65
1090 12:47:14.287632
1091 12:47:14.287796 Set Vref, RX VrefLevel [Byte0]: 66
1092 12:47:14.291283 [Byte1]: 66
1093 12:47:14.295261
1094 12:47:14.295437 Set Vref, RX VrefLevel [Byte0]: 67
1095 12:47:14.298377 [Byte1]: 67
1096 12:47:14.302620
1097 12:47:14.302762 Set Vref, RX VrefLevel [Byte0]: 68
1098 12:47:14.306058 [Byte1]: 68
1099 12:47:14.310327
1100 12:47:14.310431 Set Vref, RX VrefLevel [Byte0]: 69
1101 12:47:14.313495 [Byte1]: 69
1102 12:47:14.318467
1103 12:47:14.318593 Set Vref, RX VrefLevel [Byte0]: 70
1104 12:47:14.321286 [Byte1]: 70
1105 12:47:14.325847
1106 12:47:14.325988 Set Vref, RX VrefLevel [Byte0]: 71
1107 12:47:14.328900 [Byte1]: 71
1108 12:47:14.333261
1109 12:47:14.333375 Set Vref, RX VrefLevel [Byte0]: 72
1110 12:47:14.336696 [Byte1]: 72
1111 12:47:14.340717
1112 12:47:14.340842 Set Vref, RX VrefLevel [Byte0]: 73
1113 12:47:14.343999 [Byte1]: 73
1114 12:47:14.348433
1115 12:47:14.348578 Set Vref, RX VrefLevel [Byte0]: 74
1116 12:47:14.351574 [Byte1]: 74
1117 12:47:14.355851
1118 12:47:14.355994 Set Vref, RX VrefLevel [Byte0]: 75
1119 12:47:14.359642 [Byte1]: 75
1120 12:47:14.363840
1121 12:47:14.363981 Set Vref, RX VrefLevel [Byte0]: 76
1122 12:47:14.367028 [Byte1]: 76
1123 12:47:14.371382
1124 12:47:14.371535 Set Vref, RX VrefLevel [Byte0]: 77
1125 12:47:14.374274 [Byte1]: 77
1126 12:47:14.379176
1127 12:47:14.379338 Set Vref, RX VrefLevel [Byte0]: 78
1128 12:47:14.382024 [Byte1]: 78
1129 12:47:14.386607
1130 12:47:14.386762 Set Vref, RX VrefLevel [Byte0]: 79
1131 12:47:14.389510 [Byte1]: 79
1132 12:47:14.394350
1133 12:47:14.394497 Final RX Vref Byte 0 = 59 to rank0
1134 12:47:14.397345 Final RX Vref Byte 1 = 62 to rank0
1135 12:47:14.400699 Final RX Vref Byte 0 = 59 to rank1
1136 12:47:14.404175 Final RX Vref Byte 1 = 62 to rank1==
1137 12:47:14.407614 Dram Type= 6, Freq= 0, CH_0, rank 0
1138 12:47:14.410860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 12:47:14.414091 ==
1140 12:47:14.414238 DQS Delay:
1141 12:47:14.414339 DQS0 = 0, DQS1 = 0
1142 12:47:14.417291 DQM Delay:
1143 12:47:14.417411 DQM0 = 92, DQM1 = 83
1144 12:47:14.420642 DQ Delay:
1145 12:47:14.424043 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1146 12:47:14.424179 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1147 12:47:14.427286 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1148 12:47:14.430771 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1149 12:47:14.434323
1150 12:47:14.434429
1151 12:47:14.440748 [DQSOSCAuto] RK0, (LSB)MR18= 0x3934, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1152 12:47:14.444454 CH0 RK0: MR19=606, MR18=3934
1153 12:47:14.450896 CH0_RK0: MR19=0x606, MR18=0x3934, DQSOSC=395, MR23=63, INC=94, DEC=63
1154 12:47:14.451083
1155 12:47:14.454490 ----->DramcWriteLeveling(PI) begin...
1156 12:47:14.454640 ==
1157 12:47:14.457732 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 12:47:14.460929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 12:47:14.461037 ==
1160 12:47:14.464295 Write leveling (Byte 0): 32 => 32
1161 12:47:14.467524 Write leveling (Byte 1): 31 => 31
1162 12:47:14.471061 DramcWriteLeveling(PI) end<-----
1163 12:47:14.471236
1164 12:47:14.471347 ==
1165 12:47:14.474552 Dram Type= 6, Freq= 0, CH_0, rank 1
1166 12:47:14.478024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1167 12:47:14.478175 ==
1168 12:47:14.481066 [Gating] SW mode calibration
1169 12:47:14.487970 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1170 12:47:14.494282 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1171 12:47:14.497672 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1172 12:47:14.501238 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1173 12:47:14.545161 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1174 12:47:14.545580 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:47:14.546136 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:47:14.546457 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:47:14.546563 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:47:14.546855 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:47:14.547185 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:47:14.547484 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:47:14.547605 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:47:14.547953 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:47:14.570945 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:47:14.571423 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:47:14.571761 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:47:14.571896 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:47:14.572012 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1188 12:47:14.575207 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1189 12:47:14.578430 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:47:14.581874 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:47:14.585359 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:47:14.588288 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:47:14.595030 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:47:14.598187 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:47:14.601843 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:47:14.608295 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 12:47:14.611815 0 9 8 | B1->B0 | 2a2a 3232 | 1 1 | (1 1) (1 1)
1198 12:47:14.614881 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 12:47:14.622119 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 12:47:14.625258 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 12:47:14.628465 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 12:47:14.635292 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1203 12:47:14.638257 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1204 12:47:14.641920 0 10 4 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 1)
1205 12:47:14.648642 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1206 12:47:14.651795 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 12:47:14.655234 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 12:47:14.658773 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 12:47:14.665276 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 12:47:14.668634 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 12:47:14.672177 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 12:47:14.678708 0 11 4 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
1213 12:47:14.682466 0 11 8 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
1214 12:47:14.686617 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 12:47:14.690081 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 12:47:14.694147 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 12:47:14.700765 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 12:47:14.703739 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 12:47:14.707578 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 12:47:14.711375 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1221 12:47:14.717847 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1222 12:47:14.721266 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 12:47:14.724494 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 12:47:14.731562 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 12:47:14.734509 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 12:47:14.738195 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 12:47:14.744691 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 12:47:14.747985 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 12:47:14.751322 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 12:47:14.757831 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 12:47:14.761452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 12:47:14.764817 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 12:47:14.771529 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 12:47:14.774901 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 12:47:14.778340 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 12:47:14.781516 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1237 12:47:14.788314 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 12:47:14.791529 Total UI for P1: 0, mck2ui 16
1239 12:47:14.794853 best dqsien dly found for B0: ( 0, 14, 4)
1240 12:47:14.798461 Total UI for P1: 0, mck2ui 16
1241 12:47:14.801466 best dqsien dly found for B1: ( 0, 14, 4)
1242 12:47:14.804693 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1243 12:47:14.808055 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1244 12:47:14.808196
1245 12:47:14.811595 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1246 12:47:14.814977 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1247 12:47:14.818246 [Gating] SW calibration Done
1248 12:47:14.818411 ==
1249 12:47:14.821682 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 12:47:14.825030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1251 12:47:14.825183 ==
1252 12:47:14.828068 RX Vref Scan: 0
1253 12:47:14.828211
1254 12:47:14.828328 RX Vref 0 -> 0, step: 1
1255 12:47:14.828443
1256 12:47:14.831644 RX Delay -130 -> 252, step: 16
1257 12:47:14.835015 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1258 12:47:14.841646 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1259 12:47:14.844765 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1260 12:47:14.848723 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1261 12:47:14.851471 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1262 12:47:14.854791 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1263 12:47:14.861730 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1264 12:47:14.864858 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1265 12:47:14.868092 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1266 12:47:14.871517 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1267 12:47:14.874911 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1268 12:47:14.881610 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1269 12:47:14.884905 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1270 12:47:14.888185 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1271 12:47:14.891910 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1272 12:47:14.895425 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1273 12:47:14.898710 ==
1274 12:47:14.902353 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 12:47:14.905404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 12:47:14.905516 ==
1277 12:47:14.905608 DQS Delay:
1278 12:47:14.908525 DQS0 = 0, DQS1 = 0
1279 12:47:14.908623 DQM Delay:
1280 12:47:14.911652 DQM0 = 91, DQM1 = 84
1281 12:47:14.911755 DQ Delay:
1282 12:47:14.915016 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =77
1283 12:47:14.919002 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1284 12:47:14.922174 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
1285 12:47:14.925261 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
1286 12:47:14.925422
1287 12:47:14.925547
1288 12:47:14.925661 ==
1289 12:47:14.928714 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 12:47:14.931802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 12:47:14.931952 ==
1292 12:47:14.932076
1293 12:47:14.932194
1294 12:47:14.935324 TX Vref Scan disable
1295 12:47:14.938618 == TX Byte 0 ==
1296 12:47:14.941760 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1297 12:47:14.945052 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1298 12:47:14.948612 == TX Byte 1 ==
1299 12:47:14.951825 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1300 12:47:14.955272 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1301 12:47:14.955391 ==
1302 12:47:14.958761 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 12:47:14.962158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 12:47:14.962315 ==
1305 12:47:14.976401 TX Vref=22, minBit 3, minWin=27, winSum=443
1306 12:47:14.979805 TX Vref=24, minBit 8, minWin=27, winSum=450
1307 12:47:14.983359 TX Vref=26, minBit 8, minWin=27, winSum=451
1308 12:47:14.986526 TX Vref=28, minBit 4, minWin=28, winSum=455
1309 12:47:14.989774 TX Vref=30, minBit 8, minWin=27, winSum=453
1310 12:47:14.993262 TX Vref=32, minBit 8, minWin=27, winSum=453
1311 12:47:14.999653 [TxChooseVref] Worse bit 4, Min win 28, Win sum 455, Final Vref 28
1312 12:47:14.999822
1313 12:47:15.002927 Final TX Range 1 Vref 28
1314 12:47:15.003046
1315 12:47:15.003149 ==
1316 12:47:15.006681 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 12:47:15.009778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 12:47:15.009924 ==
1319 12:47:15.010073
1320 12:47:15.010177
1321 12:47:15.013311 TX Vref Scan disable
1322 12:47:15.016496 == TX Byte 0 ==
1323 12:47:15.019897 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1324 12:47:15.023306 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1325 12:47:15.026400 == TX Byte 1 ==
1326 12:47:15.029939 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1327 12:47:15.033393 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1328 12:47:15.033499
1329 12:47:15.036646 [DATLAT]
1330 12:47:15.036743 Freq=800, CH0 RK1
1331 12:47:15.036827
1332 12:47:15.039806 DATLAT Default: 0xa
1333 12:47:15.039882 0, 0xFFFF, sum = 0
1334 12:47:15.043459 1, 0xFFFF, sum = 0
1335 12:47:15.043561 2, 0xFFFF, sum = 0
1336 12:47:15.046576 3, 0xFFFF, sum = 0
1337 12:47:15.046669 4, 0xFFFF, sum = 0
1338 12:47:15.049942 5, 0xFFFF, sum = 0
1339 12:47:15.050038 6, 0xFFFF, sum = 0
1340 12:47:15.053494 7, 0xFFFF, sum = 0
1341 12:47:15.053638 8, 0xFFFF, sum = 0
1342 12:47:15.056579 9, 0x0, sum = 1
1343 12:47:15.056721 10, 0x0, sum = 2
1344 12:47:15.059977 11, 0x0, sum = 3
1345 12:47:15.060112 12, 0x0, sum = 4
1346 12:47:15.063391 best_step = 10
1347 12:47:15.063490
1348 12:47:15.063557 ==
1349 12:47:15.066954 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 12:47:15.069917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 12:47:15.070022 ==
1352 12:47:15.073488 RX Vref Scan: 0
1353 12:47:15.073643
1354 12:47:15.073755 RX Vref 0 -> 0, step: 1
1355 12:47:15.073862
1356 12:47:15.076832 RX Delay -79 -> 252, step: 8
1357 12:47:15.083710 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1358 12:47:15.086735 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1359 12:47:15.090347 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1360 12:47:15.093622 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1361 12:47:15.097095 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1362 12:47:15.099980 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1363 12:47:15.107327 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1364 12:47:15.110426 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1365 12:47:15.113689 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1366 12:47:15.117041 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1367 12:47:15.120092 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1368 12:47:15.126816 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1369 12:47:15.130539 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1370 12:47:15.133645 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1371 12:47:15.136694 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1372 12:47:15.140169 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1373 12:47:15.143499 ==
1374 12:47:15.147091 Dram Type= 6, Freq= 0, CH_0, rank 1
1375 12:47:15.150278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 12:47:15.150379 ==
1377 12:47:15.150446 DQS Delay:
1378 12:47:15.153862 DQS0 = 0, DQS1 = 0
1379 12:47:15.153977 DQM Delay:
1380 12:47:15.157279 DQM0 = 90, DQM1 = 81
1381 12:47:15.157367 DQ Delay:
1382 12:47:15.160411 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1383 12:47:15.163553 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1384 12:47:15.167215 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =76
1385 12:47:15.170650 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1386 12:47:15.170742
1387 12:47:15.170834
1388 12:47:15.177551 [DQSOSCAuto] RK1, (LSB)MR18= 0x401a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1389 12:47:15.180703 CH0 RK1: MR19=606, MR18=401A
1390 12:47:15.187536 CH0_RK1: MR19=0x606, MR18=0x401A, DQSOSC=393, MR23=63, INC=95, DEC=63
1391 12:47:15.190554 [RxdqsGatingPostProcess] freq 800
1392 12:47:15.193738 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1393 12:47:15.197139 Pre-setting of DQS Precalculation
1394 12:47:15.203623 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1395 12:47:15.203771 ==
1396 12:47:15.206921 Dram Type= 6, Freq= 0, CH_1, rank 0
1397 12:47:15.210746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 12:47:15.210879 ==
1399 12:47:15.217120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1400 12:47:15.223711 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1401 12:47:15.231694 [CA 0] Center 36 (6~67) winsize 62
1402 12:47:15.234672 [CA 1] Center 36 (6~67) winsize 62
1403 12:47:15.238304 [CA 2] Center 35 (5~65) winsize 61
1404 12:47:15.241360 [CA 3] Center 34 (3~65) winsize 63
1405 12:47:15.244748 [CA 4] Center 34 (4~65) winsize 62
1406 12:47:15.248245 [CA 5] Center 34 (3~65) winsize 63
1407 12:47:15.248371
1408 12:47:15.251740 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1409 12:47:15.251840
1410 12:47:15.254798 [CATrainingPosCal] consider 1 rank data
1411 12:47:15.258352 u2DelayCellTimex100 = 270/100 ps
1412 12:47:15.261489 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1413 12:47:15.265051 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1414 12:47:15.268332 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1415 12:47:15.274933 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1416 12:47:15.278155 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1417 12:47:15.281443 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1418 12:47:15.281578
1419 12:47:15.285036 CA PerBit enable=1, Macro0, CA PI delay=34
1420 12:47:15.285141
1421 12:47:15.288151 [CBTSetCACLKResult] CA Dly = 34
1422 12:47:15.288239 CS Dly: 5 (0~36)
1423 12:47:15.288306 ==
1424 12:47:15.291741 Dram Type= 6, Freq= 0, CH_1, rank 1
1425 12:47:15.298192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 12:47:15.298307 ==
1427 12:47:15.301598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1428 12:47:15.308062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1429 12:47:15.317607 [CA 0] Center 36 (6~67) winsize 62
1430 12:47:15.321003 [CA 1] Center 37 (6~68) winsize 63
1431 12:47:15.324324 [CA 2] Center 35 (5~66) winsize 62
1432 12:47:15.327433 [CA 3] Center 34 (4~65) winsize 62
1433 12:47:15.331174 [CA 4] Center 34 (4~65) winsize 62
1434 12:47:15.334468 [CA 5] Center 33 (3~64) winsize 62
1435 12:47:15.334585
1436 12:47:15.337639 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1437 12:47:15.337747
1438 12:47:15.340867 [CATrainingPosCal] consider 2 rank data
1439 12:47:15.345040 u2DelayCellTimex100 = 270/100 ps
1440 12:47:15.348710 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1441 12:47:15.352132 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1442 12:47:15.356100 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1443 12:47:15.359957 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1444 12:47:15.363656 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1445 12:47:15.367321 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1446 12:47:15.367477
1447 12:47:15.370938 CA PerBit enable=1, Macro0, CA PI delay=33
1448 12:47:15.371081
1449 12:47:15.374571 [CBTSetCACLKResult] CA Dly = 33
1450 12:47:15.374713 CS Dly: 6 (0~38)
1451 12:47:15.374832
1452 12:47:15.378438 ----->DramcWriteLeveling(PI) begin...
1453 12:47:15.378582 ==
1454 12:47:15.381871 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 12:47:15.385102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 12:47:15.388305 ==
1457 12:47:15.388402 Write leveling (Byte 0): 29 => 29
1458 12:47:15.392042 Write leveling (Byte 1): 30 => 30
1459 12:47:15.395068 DramcWriteLeveling(PI) end<-----
1460 12:47:15.395212
1461 12:47:15.395330 ==
1462 12:47:15.398417 Dram Type= 6, Freq= 0, CH_1, rank 0
1463 12:47:15.405370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1464 12:47:15.405550 ==
1465 12:47:15.405670 [Gating] SW mode calibration
1466 12:47:15.415293 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1467 12:47:15.418526 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1468 12:47:15.421771 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1469 12:47:15.428679 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1470 12:47:15.431895 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1471 12:47:15.435447 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:47:15.442131 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:47:15.445375 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:47:15.448846 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:47:15.455261 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:47:15.458839 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:47:15.462217 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:47:15.468686 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:47:15.472179 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:47:15.475288 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:47:15.482507 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:47:15.485766 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:47:15.489385 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:47:15.492078 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1485 12:47:15.498794 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:47:15.502332 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:47:15.505756 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:47:15.512355 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:47:15.515581 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:47:15.518913 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:47:15.525749 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:47:15.528921 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:47:15.532192 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1494 12:47:15.538874 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 12:47:15.542036 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 12:47:15.545711 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 12:47:15.552573 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 12:47:15.555704 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 12:47:15.559004 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 12:47:15.562534 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1501 12:47:15.569083 0 10 4 | B1->B0 | 2e2e 2b2b | 1 1 | (1 1) (1 0)
1502 12:47:15.572564 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1503 12:47:15.575985 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 12:47:15.582517 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 12:47:15.585888 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 12:47:15.589524 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 12:47:15.596060 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 12:47:15.599690 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 12:47:15.602775 0 11 4 | B1->B0 | 3131 3737 | 0 0 | (0 0) (0 0)
1510 12:47:15.609327 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 12:47:15.612774 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 12:47:15.616076 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 12:47:15.622533 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 12:47:15.626151 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 12:47:15.629470 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 12:47:15.632567 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1517 12:47:15.639242 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1518 12:47:15.642571 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:47:15.646149 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 12:47:15.652747 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 12:47:15.656159 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 12:47:15.659345 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 12:47:15.666407 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 12:47:15.669615 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 12:47:15.672733 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 12:47:15.679737 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 12:47:15.682830 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 12:47:15.686110 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 12:47:15.693104 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 12:47:15.696510 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 12:47:15.699465 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 12:47:15.702891 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 12:47:15.709501 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1534 12:47:15.712748 Total UI for P1: 0, mck2ui 16
1535 12:47:15.716111 best dqsien dly found for B0: ( 0, 14, 2)
1536 12:47:15.719613 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 12:47:15.723207 Total UI for P1: 0, mck2ui 16
1538 12:47:15.726059 best dqsien dly found for B1: ( 0, 14, 4)
1539 12:47:15.729801 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1540 12:47:15.732889 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1541 12:47:15.733027
1542 12:47:15.736235 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1543 12:47:15.739588 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1544 12:47:15.743166 [Gating] SW calibration Done
1545 12:47:15.743291 ==
1546 12:47:15.746687 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 12:47:15.749886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1548 12:47:15.753054 ==
1549 12:47:15.753185 RX Vref Scan: 0
1550 12:47:15.753282
1551 12:47:15.756404 RX Vref 0 -> 0, step: 1
1552 12:47:15.756531
1553 12:47:15.760016 RX Delay -130 -> 252, step: 16
1554 12:47:15.763133 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1555 12:47:15.766698 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1556 12:47:15.769762 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1557 12:47:15.773136 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1558 12:47:15.776742 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1559 12:47:15.783193 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1560 12:47:15.786792 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1561 12:47:15.790019 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1562 12:47:15.793338 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1563 12:47:15.796422 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1564 12:47:15.803370 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1565 12:47:15.807197 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1566 12:47:15.810025 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1567 12:47:15.813345 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1568 12:47:15.816632 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1569 12:47:15.823262 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1570 12:47:15.823409 ==
1571 12:47:15.827100 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 12:47:15.830044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 12:47:15.830161 ==
1574 12:47:15.830269 DQS Delay:
1575 12:47:15.833657 DQS0 = 0, DQS1 = 0
1576 12:47:15.833769 DQM Delay:
1577 12:47:15.836730 DQM0 = 90, DQM1 = 85
1578 12:47:15.836847 DQ Delay:
1579 12:47:15.840511 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1580 12:47:15.843415 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =93
1581 12:47:15.846910 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1582 12:47:15.850315 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1583 12:47:15.850445
1584 12:47:15.850546
1585 12:47:15.850632 ==
1586 12:47:15.853762 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 12:47:15.857093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 12:47:15.857211 ==
1589 12:47:15.857309
1590 12:47:15.857402
1591 12:47:15.860690 TX Vref Scan disable
1592 12:47:15.863760 == TX Byte 0 ==
1593 12:47:15.867699 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1594 12:47:15.870464 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1595 12:47:15.873843 == TX Byte 1 ==
1596 12:47:15.877126 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1597 12:47:15.880661 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1598 12:47:15.880815 ==
1599 12:47:15.883794 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 12:47:15.886999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 12:47:15.890485 ==
1602 12:47:15.901800 TX Vref=22, minBit 8, minWin=27, winSum=448
1603 12:47:15.905485 TX Vref=24, minBit 10, minWin=27, winSum=452
1604 12:47:15.908464 TX Vref=26, minBit 13, minWin=27, winSum=453
1605 12:47:15.911710 TX Vref=28, minBit 13, minWin=27, winSum=453
1606 12:47:15.915440 TX Vref=30, minBit 15, minWin=27, winSum=458
1607 12:47:15.921754 TX Vref=32, minBit 15, minWin=27, winSum=457
1608 12:47:15.924981 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 30
1609 12:47:15.925116
1610 12:47:15.929453 Final TX Range 1 Vref 30
1611 12:47:15.929568
1612 12:47:15.929662 ==
1613 12:47:15.932595 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 12:47:15.935996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 12:47:15.936162 ==
1616 12:47:15.936289
1617 12:47:15.936405
1618 12:47:15.939425 TX Vref Scan disable
1619 12:47:15.942684 == TX Byte 0 ==
1620 12:47:15.946032 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1621 12:47:15.949793 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1622 12:47:15.952697 == TX Byte 1 ==
1623 12:47:15.956263 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1624 12:47:15.959609 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1625 12:47:15.959762
1626 12:47:15.962892 [DATLAT]
1627 12:47:15.963034 Freq=800, CH1 RK0
1628 12:47:15.963159
1629 12:47:15.966466 DATLAT Default: 0xa
1630 12:47:15.966619 0, 0xFFFF, sum = 0
1631 12:47:15.969404 1, 0xFFFF, sum = 0
1632 12:47:15.969548 2, 0xFFFF, sum = 0
1633 12:47:15.972845 3, 0xFFFF, sum = 0
1634 12:47:15.972994 4, 0xFFFF, sum = 0
1635 12:47:15.975967 5, 0xFFFF, sum = 0
1636 12:47:15.976131 6, 0xFFFF, sum = 0
1637 12:47:15.979283 7, 0xFFFF, sum = 0
1638 12:47:15.979437 8, 0xFFFF, sum = 0
1639 12:47:15.982900 9, 0x0, sum = 1
1640 12:47:15.983057 10, 0x0, sum = 2
1641 12:47:15.986147 11, 0x0, sum = 3
1642 12:47:15.986290 12, 0x0, sum = 4
1643 12:47:15.989556 best_step = 10
1644 12:47:15.989703
1645 12:47:15.989820 ==
1646 12:47:15.992830 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 12:47:15.996060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 12:47:15.996202 ==
1649 12:47:15.996317 RX Vref Scan: 1
1650 12:47:15.999337
1651 12:47:15.999465 Set Vref Range= 32 -> 127
1652 12:47:15.999584
1653 12:47:16.002656 RX Vref 32 -> 127, step: 1
1654 12:47:16.002788
1655 12:47:16.006533 RX Delay -95 -> 252, step: 8
1656 12:47:16.006667
1657 12:47:16.009386 Set Vref, RX VrefLevel [Byte0]: 32
1658 12:47:16.012788 [Byte1]: 32
1659 12:47:16.012930
1660 12:47:16.015893 Set Vref, RX VrefLevel [Byte0]: 33
1661 12:47:16.019245 [Byte1]: 33
1662 12:47:16.019363
1663 12:47:16.022847 Set Vref, RX VrefLevel [Byte0]: 34
1664 12:47:16.026005 [Byte1]: 34
1665 12:47:16.029925
1666 12:47:16.030027 Set Vref, RX VrefLevel [Byte0]: 35
1667 12:47:16.033093 [Byte1]: 35
1668 12:47:16.037549
1669 12:47:16.037711 Set Vref, RX VrefLevel [Byte0]: 36
1670 12:47:16.040849 [Byte1]: 36
1671 12:47:16.045428
1672 12:47:16.045561 Set Vref, RX VrefLevel [Byte0]: 37
1673 12:47:16.048561 [Byte1]: 37
1674 12:47:16.052803
1675 12:47:16.052957 Set Vref, RX VrefLevel [Byte0]: 38
1676 12:47:16.056012 [Byte1]: 38
1677 12:47:16.060576
1678 12:47:16.060705 Set Vref, RX VrefLevel [Byte0]: 39
1679 12:47:16.063911 [Byte1]: 39
1680 12:47:16.068115
1681 12:47:16.068265 Set Vref, RX VrefLevel [Byte0]: 40
1682 12:47:16.071158 [Byte1]: 40
1683 12:47:16.075600
1684 12:47:16.075738 Set Vref, RX VrefLevel [Byte0]: 41
1685 12:47:16.078806 [Byte1]: 41
1686 12:47:16.083322
1687 12:47:16.083469 Set Vref, RX VrefLevel [Byte0]: 42
1688 12:47:16.086450 [Byte1]: 42
1689 12:47:16.090733
1690 12:47:16.090881 Set Vref, RX VrefLevel [Byte0]: 43
1691 12:47:16.094317 [Byte1]: 43
1692 12:47:16.098425
1693 12:47:16.098668 Set Vref, RX VrefLevel [Byte0]: 44
1694 12:47:16.101902 [Byte1]: 44
1695 12:47:16.106532
1696 12:47:16.106746 Set Vref, RX VrefLevel [Byte0]: 45
1697 12:47:16.109213 [Byte1]: 45
1698 12:47:16.113625
1699 12:47:16.113847 Set Vref, RX VrefLevel [Byte0]: 46
1700 12:47:16.116819 [Byte1]: 46
1701 12:47:16.121365
1702 12:47:16.121523 Set Vref, RX VrefLevel [Byte0]: 47
1703 12:47:16.124365 [Byte1]: 47
1704 12:47:16.128969
1705 12:47:16.129171 Set Vref, RX VrefLevel [Byte0]: 48
1706 12:47:16.131999 [Byte1]: 48
1707 12:47:16.136349
1708 12:47:16.136551 Set Vref, RX VrefLevel [Byte0]: 49
1709 12:47:16.139873 [Byte1]: 49
1710 12:47:16.143915
1711 12:47:16.144078 Set Vref, RX VrefLevel [Byte0]: 50
1712 12:47:16.147275 [Byte1]: 50
1713 12:47:16.151876
1714 12:47:16.152053 Set Vref, RX VrefLevel [Byte0]: 51
1715 12:47:16.154741 [Byte1]: 51
1716 12:47:16.159470
1717 12:47:16.159619 Set Vref, RX VrefLevel [Byte0]: 52
1718 12:47:16.162483 [Byte1]: 52
1719 12:47:16.166761
1720 12:47:16.166898 Set Vref, RX VrefLevel [Byte0]: 53
1721 12:47:16.170268 [Byte1]: 53
1722 12:47:16.174581
1723 12:47:16.174718 Set Vref, RX VrefLevel [Byte0]: 54
1724 12:47:16.177836 [Byte1]: 54
1725 12:47:16.182158
1726 12:47:16.182286 Set Vref, RX VrefLevel [Byte0]: 55
1727 12:47:16.185331 [Byte1]: 55
1728 12:47:16.189571
1729 12:47:16.189673 Set Vref, RX VrefLevel [Byte0]: 56
1730 12:47:16.193155 [Byte1]: 56
1731 12:47:16.197404
1732 12:47:16.197502 Set Vref, RX VrefLevel [Byte0]: 57
1733 12:47:16.200675 [Byte1]: 57
1734 12:47:16.204654
1735 12:47:16.204785 Set Vref, RX VrefLevel [Byte0]: 58
1736 12:47:16.208057 [Byte1]: 58
1737 12:47:16.212233
1738 12:47:16.212371 Set Vref, RX VrefLevel [Byte0]: 59
1739 12:47:16.215513 [Byte1]: 59
1740 12:47:16.220061
1741 12:47:16.220198 Set Vref, RX VrefLevel [Byte0]: 60
1742 12:47:16.223554 [Byte1]: 60
1743 12:47:16.227515
1744 12:47:16.227644 Set Vref, RX VrefLevel [Byte0]: 61
1745 12:47:16.230941 [Byte1]: 61
1746 12:47:16.235177
1747 12:47:16.235319 Set Vref, RX VrefLevel [Byte0]: 62
1748 12:47:16.238462 [Byte1]: 62
1749 12:47:16.242845
1750 12:47:16.242954 Set Vref, RX VrefLevel [Byte0]: 63
1751 12:47:16.246112 [Byte1]: 63
1752 12:47:16.250284
1753 12:47:16.250439 Set Vref, RX VrefLevel [Byte0]: 64
1754 12:47:16.253883 [Byte1]: 64
1755 12:47:16.257959
1756 12:47:16.258089 Set Vref, RX VrefLevel [Byte0]: 65
1757 12:47:16.261354 [Byte1]: 65
1758 12:47:16.265560
1759 12:47:16.265678 Set Vref, RX VrefLevel [Byte0]: 66
1760 12:47:16.268737 [Byte1]: 66
1761 12:47:16.272988
1762 12:47:16.273128 Set Vref, RX VrefLevel [Byte0]: 67
1763 12:47:16.276673 [Byte1]: 67
1764 12:47:16.281023
1765 12:47:16.281186 Set Vref, RX VrefLevel [Byte0]: 68
1766 12:47:16.284087 [Byte1]: 68
1767 12:47:16.288330
1768 12:47:16.288465 Set Vref, RX VrefLevel [Byte0]: 69
1769 12:47:16.291698 [Byte1]: 69
1770 12:47:16.295964
1771 12:47:16.296072 Set Vref, RX VrefLevel [Byte0]: 70
1772 12:47:16.299276 [Byte1]: 70
1773 12:47:16.303825
1774 12:47:16.303993 Set Vref, RX VrefLevel [Byte0]: 71
1775 12:47:16.306828 [Byte1]: 71
1776 12:47:16.310999
1777 12:47:16.311143 Set Vref, RX VrefLevel [Byte0]: 72
1778 12:47:16.314521 [Byte1]: 72
1779 12:47:16.318525
1780 12:47:16.318668 Set Vref, RX VrefLevel [Byte0]: 73
1781 12:47:16.322052 [Byte1]: 73
1782 12:47:16.326113
1783 12:47:16.326274 Set Vref, RX VrefLevel [Byte0]: 74
1784 12:47:16.329807 [Byte1]: 74
1785 12:47:16.333914
1786 12:47:16.334075 Set Vref, RX VrefLevel [Byte0]: 75
1787 12:47:16.337553 [Byte1]: 75
1788 12:47:16.341342
1789 12:47:16.341450 Set Vref, RX VrefLevel [Byte0]: 76
1790 12:47:16.344690 [Byte1]: 76
1791 12:47:16.349171
1792 12:47:16.349313 Set Vref, RX VrefLevel [Byte0]: 77
1793 12:47:16.352234 [Byte1]: 77
1794 12:47:16.356698
1795 12:47:16.356820 Set Vref, RX VrefLevel [Byte0]: 78
1796 12:47:16.359960 [Byte1]: 78
1797 12:47:16.364090
1798 12:47:16.364245 Final RX Vref Byte 0 = 52 to rank0
1799 12:47:16.367431 Final RX Vref Byte 1 = 63 to rank0
1800 12:47:16.371219 Final RX Vref Byte 0 = 52 to rank1
1801 12:47:16.374254 Final RX Vref Byte 1 = 63 to rank1==
1802 12:47:16.377840 Dram Type= 6, Freq= 0, CH_1, rank 0
1803 12:47:16.384081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 12:47:16.384274 ==
1805 12:47:16.384399 DQS Delay:
1806 12:47:16.384506 DQS0 = 0, DQS1 = 0
1807 12:47:16.387722 DQM Delay:
1808 12:47:16.387843 DQM0 = 93, DQM1 = 82
1809 12:47:16.390800 DQ Delay:
1810 12:47:16.394664 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1811 12:47:16.397817 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1812 12:47:16.397951 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1813 12:47:16.404108 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1814 12:47:16.404258
1815 12:47:16.404358
1816 12:47:16.411007 [DQSOSCAuto] RK0, (LSB)MR18= 0x314e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1817 12:47:16.414260 CH1 RK0: MR19=606, MR18=314E
1818 12:47:16.421073 CH1_RK0: MR19=0x606, MR18=0x314E, DQSOSC=390, MR23=63, INC=97, DEC=64
1819 12:47:16.421210
1820 12:47:16.424249 ----->DramcWriteLeveling(PI) begin...
1821 12:47:16.424340 ==
1822 12:47:16.427798 Dram Type= 6, Freq= 0, CH_1, rank 1
1823 12:47:16.431159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1824 12:47:16.431272 ==
1825 12:47:16.434748 Write leveling (Byte 0): 26 => 26
1826 12:47:16.437672 Write leveling (Byte 1): 27 => 27
1827 12:47:16.440915 DramcWriteLeveling(PI) end<-----
1828 12:47:16.441025
1829 12:47:16.441146 ==
1830 12:47:16.444448 Dram Type= 6, Freq= 0, CH_1, rank 1
1831 12:47:16.447819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1832 12:47:16.447916 ==
1833 12:47:16.451290 [Gating] SW mode calibration
1834 12:47:16.457704 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1835 12:47:16.464156 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1836 12:47:16.467551 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1837 12:47:16.470894 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1838 12:47:16.477637 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1839 12:47:16.481142 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:47:16.484447 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:47:16.490899 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:47:16.494095 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:47:16.497413 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:47:16.504295 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:47:16.507542 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:47:16.510913 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:47:16.517669 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:47:16.520502 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:47:16.524006 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:47:16.530622 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:47:16.534079 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 12:47:16.537693 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1853 12:47:16.544152 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1854 12:47:16.547543 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:47:16.551002 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:47:16.554412 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 12:47:16.560715 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:47:16.564682 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:47:16.567580 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:47:16.574140 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:47:16.577739 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:47:16.580949 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 12:47:16.587423 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 12:47:16.590897 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 12:47:16.594696 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 12:47:16.600840 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 12:47:16.604365 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 12:47:16.607349 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 12:47:16.614391 0 10 4 | B1->B0 | 2929 2e2e | 1 0 | (1 0) (0 0)
1870 12:47:16.617806 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1871 12:47:16.621195 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:47:16.624605 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:47:16.631321 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:47:16.634577 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:47:16.637990 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:47:16.644382 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1877 12:47:16.648038 0 11 4 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (0 0)
1878 12:47:16.651287 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1879 12:47:16.658151 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 12:47:16.660800 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 12:47:16.664366 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 12:47:16.671014 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 12:47:16.674501 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 12:47:16.677755 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 12:47:16.684588 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1886 12:47:16.687705 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1887 12:47:16.691066 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 12:47:16.697771 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 12:47:16.700891 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 12:47:16.704449 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 12:47:16.711218 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 12:47:16.714444 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 12:47:16.717774 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 12:47:16.721006 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 12:47:16.727779 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 12:47:16.731000 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 12:47:16.734619 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 12:47:16.741451 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 12:47:16.744501 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 12:47:16.747822 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 12:47:16.754469 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1902 12:47:16.758026 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 12:47:16.761367 Total UI for P1: 0, mck2ui 16
1904 12:47:16.764578 best dqsien dly found for B0: ( 0, 14, 4)
1905 12:47:16.767959 Total UI for P1: 0, mck2ui 16
1906 12:47:16.770933 best dqsien dly found for B1: ( 0, 14, 4)
1907 12:47:16.774395 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1908 12:47:16.777955 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1909 12:47:16.778066
1910 12:47:16.781309 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1911 12:47:17.323707 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1912 12:47:17.324140 [Gating] SW calibration Done
1913 12:47:17.324266 ==
1914 12:47:17.324365 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 12:47:17.324466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 12:47:17.324566 ==
1917 12:47:17.324664 RX Vref Scan: 0
1918 12:47:17.324769
1919 12:47:17.324868 RX Vref 0 -> 0, step: 1
1920 12:47:17.324968
1921 12:47:17.325065 RX Delay -130 -> 252, step: 16
1922 12:47:17.325164 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1923 12:47:17.325261 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1924 12:47:17.325359 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1925 12:47:17.325455 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1926 12:47:17.325553 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1927 12:47:17.325650 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1928 12:47:17.325747 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1929 12:47:17.325843 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1930 12:47:17.325940 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1931 12:47:17.326039 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1932 12:47:17.326136 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1933 12:47:17.326232 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1934 12:47:17.326328 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1935 12:47:17.326423 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1936 12:47:17.326521 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1937 12:47:17.326618 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1938 12:47:17.326717 ==
1939 12:47:17.326817 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 12:47:17.326915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 12:47:17.327015 ==
1942 12:47:17.327114 DQS Delay:
1943 12:47:17.327211 DQS0 = 0, DQS1 = 0
1944 12:47:17.327308 DQM Delay:
1945 12:47:17.327404 DQM0 = 89, DQM1 = 80
1946 12:47:17.327500 DQ Delay:
1947 12:47:17.327598 DQ0 =101, DQ1 =77, DQ2 =77, DQ3 =77
1948 12:47:17.327695 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1949 12:47:17.327791 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1950 12:47:17.327888 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1951 12:47:17.327984
1952 12:47:17.328082
1953 12:47:17.328178 ==
1954 12:47:17.328274 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 12:47:17.328370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 12:47:17.328465 ==
1957 12:47:17.328561
1958 12:47:17.328656
1959 12:47:17.328757 TX Vref Scan disable
1960 12:47:17.328880 == TX Byte 0 ==
1961 12:47:17.328976 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1962 12:47:17.329073 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1963 12:47:17.329227 == TX Byte 1 ==
1964 12:47:17.329387 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1965 12:47:17.329484 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1966 12:47:17.329613 ==
1967 12:47:17.329725 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 12:47:17.329840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 12:47:17.329995 ==
1970 12:47:17.330148 TX Vref=22, minBit 13, minWin=27, winSum=457
1971 12:47:17.330274 TX Vref=24, minBit 13, minWin=27, winSum=460
1972 12:47:17.330398 TX Vref=26, minBit 3, minWin=28, winSum=462
1973 12:47:17.330524 TX Vref=28, minBit 3, minWin=28, winSum=458
1974 12:47:17.330624 TX Vref=30, minBit 10, minWin=28, winSum=463
1975 12:47:17.330748 TX Vref=32, minBit 8, minWin=28, winSum=460
1976 12:47:17.330846 [TxChooseVref] Worse bit 10, Min win 28, Win sum 463, Final Vref 30
1977 12:47:17.330970
1978 12:47:17.331066 Final TX Range 1 Vref 30
1979 12:47:17.331164
1980 12:47:17.331260 ==
1981 12:47:17.331357 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 12:47:17.331453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 12:47:17.331549 ==
1984 12:47:17.331647
1985 12:47:17.331743
1986 12:47:17.331840 TX Vref Scan disable
1987 12:47:17.331936 == TX Byte 0 ==
1988 12:47:17.332032 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1989 12:47:17.332131 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1990 12:47:17.332229 == TX Byte 1 ==
1991 12:47:17.332325 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1992 12:47:17.332422 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1993 12:47:17.332517
1994 12:47:17.332613 [DATLAT]
1995 12:47:17.332710 Freq=800, CH1 RK1
1996 12:47:17.332836
1997 12:47:17.332956 DATLAT Default: 0xa
1998 12:47:17.333050 0, 0xFFFF, sum = 0
1999 12:47:17.333124 1, 0xFFFF, sum = 0
2000 12:47:17.333231 2, 0xFFFF, sum = 0
2001 12:47:17.333288 3, 0xFFFF, sum = 0
2002 12:47:17.333345 4, 0xFFFF, sum = 0
2003 12:47:17.333401 5, 0xFFFF, sum = 0
2004 12:47:17.333457 6, 0xFFFF, sum = 0
2005 12:47:17.333512 7, 0xFFFF, sum = 0
2006 12:47:17.333567 8, 0xFFFF, sum = 0
2007 12:47:17.333623 9, 0x0, sum = 1
2008 12:47:17.333683 10, 0x0, sum = 2
2009 12:47:17.333739 11, 0x0, sum = 3
2010 12:47:17.333794 12, 0x0, sum = 4
2011 12:47:17.333849 best_step = 10
2012 12:47:17.333903
2013 12:47:17.333957 ==
2014 12:47:17.334012 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 12:47:17.334066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 12:47:17.334121 ==
2017 12:47:17.334178 RX Vref Scan: 0
2018 12:47:17.334233
2019 12:47:17.334288 RX Vref 0 -> 0, step: 1
2020 12:47:17.334356
2021 12:47:17.334424 RX Delay -95 -> 252, step: 8
2022 12:47:17.334478 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2023 12:47:17.334532 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2024 12:47:17.334587 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2025 12:47:17.334641 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2026 12:47:17.334713 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2027 12:47:17.334796 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2028 12:47:17.334877 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2029 12:47:17.334946 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2030 12:47:17.335000 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2031 12:47:17.335059 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2032 12:47:17.335112 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2033 12:47:17.335166 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2034 12:47:17.335226 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2035 12:47:17.335280 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2036 12:47:17.335334 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2037 12:47:17.335388 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2038 12:47:17.335441 ==
2039 12:47:17.335495 Dram Type= 6, Freq= 0, CH_1, rank 1
2040 12:47:17.335549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2041 12:47:17.335603 ==
2042 12:47:17.335657 DQS Delay:
2043 12:47:17.335715 DQS0 = 0, DQS1 = 0
2044 12:47:17.335770 DQM Delay:
2045 12:47:17.335823 DQM0 = 91, DQM1 = 84
2046 12:47:17.335877 DQ Delay:
2047 12:47:17.335931 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2048 12:47:17.335986 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2049 12:47:17.336047 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2050 12:47:17.336102 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2051 12:47:17.336155
2052 12:47:17.336249
2053 12:47:17.336319 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2054 12:47:17.336566 CH1 RK1: MR19=606, MR18=3D12
2055 12:47:17.336626 CH1_RK1: MR19=0x606, MR18=0x3D12, DQSOSC=394, MR23=63, INC=95, DEC=63
2056 12:47:17.336682 [RxdqsGatingPostProcess] freq 800
2057 12:47:17.336737 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2058 12:47:17.336810 Pre-setting of DQS Precalculation
2059 12:47:17.336879 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2060 12:47:17.336950 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2061 12:47:17.337006 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2062 12:47:17.337061
2063 12:47:17.337114
2064 12:47:17.337167 [Calibration Summary] 1600 Mbps
2065 12:47:17.337221 CH 0, Rank 0
2066 12:47:17.337279 SW Impedance : PASS
2067 12:47:17.337334 DUTY Scan : NO K
2068 12:47:17.337387 ZQ Calibration : PASS
2069 12:47:17.337441 Jitter Meter : NO K
2070 12:47:17.337495 CBT Training : PASS
2071 12:47:17.337549 Write leveling : PASS
2072 12:47:17.337602 RX DQS gating : PASS
2073 12:47:17.337656 RX DQ/DQS(RDDQC) : PASS
2074 12:47:17.337709 TX DQ/DQS : PASS
2075 12:47:17.337766 RX DATLAT : PASS
2076 12:47:17.337821 RX DQ/DQS(Engine): PASS
2077 12:47:17.337875 TX OE : NO K
2078 12:47:17.337929 All Pass.
2079 12:47:17.337990
2080 12:47:17.338050 CH 0, Rank 1
2081 12:47:17.338105 SW Impedance : PASS
2082 12:47:17.338158 DUTY Scan : NO K
2083 12:47:17.338212 ZQ Calibration : PASS
2084 12:47:17.338268 Jitter Meter : NO K
2085 12:47:17.338323 CBT Training : PASS
2086 12:47:17.338376 Write leveling : PASS
2087 12:47:17.338430 RX DQS gating : PASS
2088 12:47:17.338484 RX DQ/DQS(RDDQC) : PASS
2089 12:47:17.338538 TX DQ/DQS : PASS
2090 12:47:17.338592 RX DATLAT : PASS
2091 12:47:17.338646 RX DQ/DQS(Engine): PASS
2092 12:47:17.338699 TX OE : NO K
2093 12:47:17.338753 All Pass.
2094 12:47:17.338811
2095 12:47:17.338864 CH 1, Rank 0
2096 12:47:17.338918 SW Impedance : PASS
2097 12:47:17.338972 DUTY Scan : NO K
2098 12:47:17.339026 ZQ Calibration : PASS
2099 12:47:17.339079 Jitter Meter : NO K
2100 12:47:17.339133 CBT Training : PASS
2101 12:47:17.339187 Write leveling : PASS
2102 12:47:17.339241 RX DQS gating : PASS
2103 12:47:17.339298 RX DQ/DQS(RDDQC) : PASS
2104 12:47:17.339352 TX DQ/DQS : PASS
2105 12:47:17.339406 RX DATLAT : PASS
2106 12:47:17.339459 RX DQ/DQS(Engine): PASS
2107 12:47:17.339512 TX OE : NO K
2108 12:47:17.339566 All Pass.
2109 12:47:17.339619
2110 12:47:17.339672 CH 1, Rank 1
2111 12:47:17.339725 SW Impedance : PASS
2112 12:47:17.339781 DUTY Scan : NO K
2113 12:47:17.339835 ZQ Calibration : PASS
2114 12:47:17.339888 Jitter Meter : NO K
2115 12:47:17.339942 CBT Training : PASS
2116 12:47:17.339995 Write leveling : PASS
2117 12:47:17.340048 RX DQS gating : PASS
2118 12:47:17.340101 RX DQ/DQS(RDDQC) : PASS
2119 12:47:17.340155 TX DQ/DQS : PASS
2120 12:47:17.340230 RX DATLAT : PASS
2121 12:47:17.340285 RX DQ/DQS(Engine): PASS
2122 12:47:17.340339 TX OE : NO K
2123 12:47:17.340393 All Pass.
2124 12:47:17.340447
2125 12:47:17.340500 DramC Write-DBI off
2126 12:47:17.340593 PER_BANK_REFRESH: Hybrid Mode
2127 12:47:17.340652 TX_TRACKING: ON
2128 12:47:17.340706 [GetDramInforAfterCalByMRR] Vendor 6.
2129 12:47:17.340767 [GetDramInforAfterCalByMRR] Revision 606.
2130 12:47:17.340834 [GetDramInforAfterCalByMRR] Revision 2 0.
2131 12:47:17.340886 MR0 0x3b3b
2132 12:47:17.340939 MR8 0x5151
2133 12:47:17.340991 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2134 12:47:17.341044
2135 12:47:17.341096 MR0 0x3b3b
2136 12:47:17.341148 MR8 0x5151
2137 12:47:17.341200 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2138 12:47:17.341256
2139 12:47:17.341327 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2140 12:47:17.344624 [FAST_K] Save calibration result to emmc
2141 12:47:17.347573 [FAST_K] Save calibration result to emmc
2142 12:47:17.350849 dram_init: config_dvfs: 1
2143 12:47:17.354223 dramc_set_vcore_voltage set vcore to 662500
2144 12:47:17.357816 Read voltage for 1200, 2
2145 12:47:17.357962 Vio18 = 0
2146 12:47:17.358083 Vcore = 662500
2147 12:47:17.361491 Vdram = 0
2148 12:47:17.361714 Vddq = 0
2149 12:47:17.361828 Vmddr = 0
2150 12:47:17.367846 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2151 12:47:17.371502 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2152 12:47:17.374611 MEM_TYPE=3, freq_sel=15
2153 12:47:17.377866 sv_algorithm_assistance_LP4_1600
2154 12:47:17.380913 ============ PULL DRAM RESETB DOWN ============
2155 12:47:17.385019 ========== PULL DRAM RESETB DOWN end =========
2156 12:47:17.391516 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2157 12:47:17.394314 ===================================
2158 12:47:17.394421 LPDDR4 DRAM CONFIGURATION
2159 12:47:17.398245 ===================================
2160 12:47:17.401302 EX_ROW_EN[0] = 0x0
2161 12:47:17.404352 EX_ROW_EN[1] = 0x0
2162 12:47:17.404493 LP4Y_EN = 0x0
2163 12:47:17.407845 WORK_FSP = 0x0
2164 12:47:17.407976 WL = 0x4
2165 12:47:17.411296 RL = 0x4
2166 12:47:17.411412 BL = 0x2
2167 12:47:17.414511 RPST = 0x0
2168 12:47:17.414633 RD_PRE = 0x0
2169 12:47:17.417988 WR_PRE = 0x1
2170 12:47:17.418112 WR_PST = 0x0
2171 12:47:17.421354 DBI_WR = 0x0
2172 12:47:17.421474 DBI_RD = 0x0
2173 12:47:17.424687 OTF = 0x1
2174 12:47:17.428153 ===================================
2175 12:47:17.431307 ===================================
2176 12:47:17.431427 ANA top config
2177 12:47:17.434654 ===================================
2178 12:47:17.438015 DLL_ASYNC_EN = 0
2179 12:47:17.441343 ALL_SLAVE_EN = 0
2180 12:47:17.441450 NEW_RANK_MODE = 1
2181 12:47:17.445255 DLL_IDLE_MODE = 1
2182 12:47:17.448027 LP45_APHY_COMB_EN = 1
2183 12:47:17.451621 TX_ODT_DIS = 1
2184 12:47:17.454422 NEW_8X_MODE = 1
2185 12:47:17.458300 ===================================
2186 12:47:17.458433 ===================================
2187 12:47:17.461435 data_rate = 2400
2188 12:47:17.464494 CKR = 1
2189 12:47:17.468488 DQ_P2S_RATIO = 8
2190 12:47:17.471493 ===================================
2191 12:47:17.474830 CA_P2S_RATIO = 8
2192 12:47:17.478139 DQ_CA_OPEN = 0
2193 12:47:17.478289 DQ_SEMI_OPEN = 0
2194 12:47:17.481532 CA_SEMI_OPEN = 0
2195 12:47:17.484731 CA_FULL_RATE = 0
2196 12:47:17.488367 DQ_CKDIV4_EN = 0
2197 12:47:17.491437 CA_CKDIV4_EN = 0
2198 12:47:17.495076 CA_PREDIV_EN = 0
2199 12:47:17.495181 PH8_DLY = 17
2200 12:47:17.498153 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2201 12:47:17.501759 DQ_AAMCK_DIV = 4
2202 12:47:17.504982 CA_AAMCK_DIV = 4
2203 12:47:17.508537 CA_ADMCK_DIV = 4
2204 12:47:17.511922 DQ_TRACK_CA_EN = 0
2205 12:47:17.512029 CA_PICK = 1200
2206 12:47:17.514940 CA_MCKIO = 1200
2207 12:47:17.518391 MCKIO_SEMI = 0
2208 12:47:17.521637 PLL_FREQ = 2366
2209 12:47:17.525557 DQ_UI_PI_RATIO = 32
2210 12:47:17.528561 CA_UI_PI_RATIO = 0
2211 12:47:17.531801 ===================================
2212 12:47:17.535242 ===================================
2213 12:47:17.535367 memory_type:LPDDR4
2214 12:47:17.538308 GP_NUM : 10
2215 12:47:17.542041 SRAM_EN : 1
2216 12:47:17.542202 MD32_EN : 0
2217 12:47:17.545127 ===================================
2218 12:47:17.548619 [ANA_INIT] >>>>>>>>>>>>>>
2219 12:47:17.551715 <<<<<< [CONFIGURE PHASE]: ANA_TX
2220 12:47:17.555471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2221 12:47:17.558534 ===================================
2222 12:47:17.562251 data_rate = 2400,PCW = 0X5b00
2223 12:47:17.565619 ===================================
2224 12:47:17.568960 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2225 12:47:17.571993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2226 12:47:17.578471 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2227 12:47:17.582003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2228 12:47:17.585430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2229 12:47:17.588629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2230 12:47:17.591981 [ANA_INIT] flow start
2231 12:47:17.595017 [ANA_INIT] PLL >>>>>>>>
2232 12:47:17.595158 [ANA_INIT] PLL <<<<<<<<
2233 12:47:17.598876 [ANA_INIT] MIDPI >>>>>>>>
2234 12:47:17.601995 [ANA_INIT] MIDPI <<<<<<<<
2235 12:47:17.602148 [ANA_INIT] DLL >>>>>>>>
2236 12:47:17.605428 [ANA_INIT] DLL <<<<<<<<
2237 12:47:17.608685 [ANA_INIT] flow end
2238 12:47:17.611840 ============ LP4 DIFF to SE enter ============
2239 12:47:17.615701 ============ LP4 DIFF to SE exit ============
2240 12:47:17.618620 [ANA_INIT] <<<<<<<<<<<<<
2241 12:47:17.622371 [Flow] Enable top DCM control >>>>>
2242 12:47:17.625503 [Flow] Enable top DCM control <<<<<
2243 12:47:17.628606 Enable DLL master slave shuffle
2244 12:47:17.631949 ==============================================================
2245 12:47:17.635275 Gating Mode config
2246 12:47:17.642015 ==============================================================
2247 12:47:17.642145 Config description:
2248 12:47:17.652152 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2249 12:47:17.658755 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2250 12:47:17.661829 SELPH_MODE 0: By rank 1: By Phase
2251 12:47:17.668479 ==============================================================
2252 12:47:17.671795 GAT_TRACK_EN = 1
2253 12:47:17.675455 RX_GATING_MODE = 2
2254 12:47:17.678924 RX_GATING_TRACK_MODE = 2
2255 12:47:17.682269 SELPH_MODE = 1
2256 12:47:17.685658 PICG_EARLY_EN = 1
2257 12:47:17.685805 VALID_LAT_VALUE = 1
2258 12:47:17.692642 ==============================================================
2259 12:47:17.695589 Enter into Gating configuration >>>>
2260 12:47:17.698768 Exit from Gating configuration <<<<
2261 12:47:17.701917 Enter into DVFS_PRE_config >>>>>
2262 12:47:17.712191 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2263 12:47:17.715599 Exit from DVFS_PRE_config <<<<<
2264 12:47:17.718760 Enter into PICG configuration >>>>
2265 12:47:17.722190 Exit from PICG configuration <<<<
2266 12:47:17.725873 [RX_INPUT] configuration >>>>>
2267 12:47:17.729225 [RX_INPUT] configuration <<<<<
2268 12:47:17.732071 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2269 12:47:17.738970 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2270 12:47:17.745586 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2271 12:47:17.752738 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2272 12:47:17.759383 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2273 12:47:17.762578 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2274 12:47:17.769421 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2275 12:47:17.772379 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2276 12:47:17.775544 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2277 12:47:17.778904 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2278 12:47:17.782187 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2279 12:47:17.789185 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2280 12:47:17.792524 ===================================
2281 12:47:17.795791 LPDDR4 DRAM CONFIGURATION
2282 12:47:17.798874 ===================================
2283 12:47:17.799035 EX_ROW_EN[0] = 0x0
2284 12:47:17.802690 EX_ROW_EN[1] = 0x0
2285 12:47:17.802812 LP4Y_EN = 0x0
2286 12:47:17.805695 WORK_FSP = 0x0
2287 12:47:17.805817 WL = 0x4
2288 12:47:17.809062 RL = 0x4
2289 12:47:17.809184 BL = 0x2
2290 12:47:17.812558 RPST = 0x0
2291 12:47:17.812742 RD_PRE = 0x0
2292 12:47:17.815674 WR_PRE = 0x1
2293 12:47:17.815823 WR_PST = 0x0
2294 12:47:17.819037 DBI_WR = 0x0
2295 12:47:17.819194 DBI_RD = 0x0
2296 12:47:17.822271 OTF = 0x1
2297 12:47:17.825788 ===================================
2298 12:47:17.828990 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2299 12:47:17.832455 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2300 12:47:17.839373 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2301 12:47:17.842314 ===================================
2302 12:47:17.842423 LPDDR4 DRAM CONFIGURATION
2303 12:47:17.846105 ===================================
2304 12:47:17.849122 EX_ROW_EN[0] = 0x10
2305 12:47:17.852608 EX_ROW_EN[1] = 0x0
2306 12:47:17.852737 LP4Y_EN = 0x0
2307 12:47:17.855690 WORK_FSP = 0x0
2308 12:47:17.855785 WL = 0x4
2309 12:47:17.859080 RL = 0x4
2310 12:47:17.859179 BL = 0x2
2311 12:47:17.862390 RPST = 0x0
2312 12:47:17.862521 RD_PRE = 0x0
2313 12:47:17.865982 WR_PRE = 0x1
2314 12:47:17.866081 WR_PST = 0x0
2315 12:47:17.869455 DBI_WR = 0x0
2316 12:47:17.869552 DBI_RD = 0x0
2317 12:47:17.872579 OTF = 0x1
2318 12:47:17.876134 ===================================
2319 12:47:17.882392 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2320 12:47:17.882546 ==
2321 12:47:17.886160 Dram Type= 6, Freq= 0, CH_0, rank 0
2322 12:47:17.888927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2323 12:47:17.889085 ==
2324 12:47:17.892359 [Duty_Offset_Calibration]
2325 12:47:17.892485 B0:2 B1:0 CA:1
2326 12:47:17.892602
2327 12:47:17.895735 [DutyScan_Calibration_Flow] k_type=0
2328 12:47:17.904785
2329 12:47:17.904930 ==CLK 0==
2330 12:47:17.908202 Final CLK duty delay cell = -4
2331 12:47:17.911544 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2332 12:47:17.914825 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2333 12:47:17.918447 [-4] AVG Duty = 4953%(X100)
2334 12:47:17.918542
2335 12:47:17.921758 CH0 CLK Duty spec in!! Max-Min= 156%
2336 12:47:17.925165 [DutyScan_Calibration_Flow] ====Done====
2337 12:47:17.925256
2338 12:47:17.928424 [DutyScan_Calibration_Flow] k_type=1
2339 12:47:17.943725
2340 12:47:17.943914 ==DQS 0 ==
2341 12:47:17.947183 Final DQS duty delay cell = 0
2342 12:47:17.950267 [0] MAX Duty = 5187%(X100), DQS PI = 30
2343 12:47:17.953669 [0] MIN Duty = 4938%(X100), DQS PI = 0
2344 12:47:17.953799 [0] AVG Duty = 5062%(X100)
2345 12:47:17.957019
2346 12:47:17.957150 ==DQS 1 ==
2347 12:47:17.960503 Final DQS duty delay cell = -4
2348 12:47:17.963753 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2349 12:47:17.967195 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2350 12:47:17.970503 [-4] AVG Duty = 5031%(X100)
2351 12:47:17.970632
2352 12:47:17.973761 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2353 12:47:17.973882
2354 12:47:17.977318 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2355 12:47:17.980395 [DutyScan_Calibration_Flow] ====Done====
2356 12:47:17.980525
2357 12:47:17.983722 [DutyScan_Calibration_Flow] k_type=3
2358 12:47:17.999798
2359 12:47:18.000008 ==DQM 0 ==
2360 12:47:18.002840 Final DQM duty delay cell = 0
2361 12:47:18.006472 [0] MAX Duty = 5062%(X100), DQS PI = 24
2362 12:47:18.009861 [0] MIN Duty = 4844%(X100), DQS PI = 2
2363 12:47:18.010006 [0] AVG Duty = 4953%(X100)
2364 12:47:18.010103
2365 12:47:18.013348 ==DQM 1 ==
2366 12:47:18.016490 Final DQM duty delay cell = -4
2367 12:47:18.020086 [-4] MAX Duty = 5000%(X100), DQS PI = 48
2368 12:47:18.023148 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2369 12:47:18.026613 [-4] AVG Duty = 4906%(X100)
2370 12:47:18.026732
2371 12:47:18.030006 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2372 12:47:18.030128
2373 12:47:18.033249 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2374 12:47:18.036997 [DutyScan_Calibration_Flow] ====Done====
2375 12:47:18.037148
2376 12:47:18.039871 [DutyScan_Calibration_Flow] k_type=2
2377 12:47:18.055792
2378 12:47:18.055963 ==DQ 0 ==
2379 12:47:18.059093 Final DQ duty delay cell = -4
2380 12:47:18.062262 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2381 12:47:18.065603 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2382 12:47:18.069065 [-4] AVG Duty = 4969%(X100)
2383 12:47:18.069178
2384 12:47:18.069278 ==DQ 1 ==
2385 12:47:18.072330 Final DQ duty delay cell = 0
2386 12:47:18.075777 [0] MAX Duty = 4938%(X100), DQS PI = 4
2387 12:47:18.079041 [0] MIN Duty = 4907%(X100), DQS PI = 0
2388 12:47:18.079179 [0] AVG Duty = 4922%(X100)
2389 12:47:18.079293
2390 12:47:18.082575 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2391 12:47:18.086147
2392 12:47:18.089134 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2393 12:47:18.092476 [DutyScan_Calibration_Flow] ====Done====
2394 12:47:18.092578 ==
2395 12:47:18.095797 Dram Type= 6, Freq= 0, CH_1, rank 0
2396 12:47:18.099305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2397 12:47:18.099419 ==
2398 12:47:18.102692 [Duty_Offset_Calibration]
2399 12:47:18.102776 B0:0 B1:-1 CA:2
2400 12:47:18.102841
2401 12:47:18.105736 [DutyScan_Calibration_Flow] k_type=0
2402 12:47:18.115910
2403 12:47:18.116062 ==CLK 0==
2404 12:47:18.119045 Final CLK duty delay cell = 0
2405 12:47:18.122616 [0] MAX Duty = 5156%(X100), DQS PI = 16
2406 12:47:18.125729 [0] MIN Duty = 4938%(X100), DQS PI = 44
2407 12:47:18.125811 [0] AVG Duty = 5047%(X100)
2408 12:47:18.129029
2409 12:47:18.132517 CH1 CLK Duty spec in!! Max-Min= 218%
2410 12:47:18.135726 [DutyScan_Calibration_Flow] ====Done====
2411 12:47:18.135836
2412 12:47:18.139041 [DutyScan_Calibration_Flow] k_type=1
2413 12:47:18.155069
2414 12:47:18.155243 ==DQS 0 ==
2415 12:47:18.158432 Final DQS duty delay cell = 0
2416 12:47:18.161701 [0] MAX Duty = 5093%(X100), DQS PI = 24
2417 12:47:18.165658 [0] MIN Duty = 4969%(X100), DQS PI = 0
2418 12:47:18.165784 [0] AVG Duty = 5031%(X100)
2419 12:47:18.165888
2420 12:47:18.168580 ==DQS 1 ==
2421 12:47:18.172035 Final DQS duty delay cell = 0
2422 12:47:18.175071 [0] MAX Duty = 5156%(X100), DQS PI = 0
2423 12:47:18.178454 [0] MIN Duty = 4875%(X100), DQS PI = 34
2424 12:47:18.178605 [0] AVG Duty = 5015%(X100)
2425 12:47:18.178706
2426 12:47:18.185520 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2427 12:47:18.185631
2428 12:47:18.188677 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2429 12:47:18.191776 [DutyScan_Calibration_Flow] ====Done====
2430 12:47:18.191863
2431 12:47:18.195262 [DutyScan_Calibration_Flow] k_type=3
2432 12:47:18.212766
2433 12:47:18.212896 ==DQM 0 ==
2434 12:47:18.215926 Final DQM duty delay cell = 4
2435 12:47:18.219199 [4] MAX Duty = 5124%(X100), DQS PI = 22
2436 12:47:18.222275 [4] MIN Duty = 4938%(X100), DQS PI = 48
2437 12:47:18.225788 [4] AVG Duty = 5031%(X100)
2438 12:47:18.225923
2439 12:47:18.226039 ==DQM 1 ==
2440 12:47:18.229034 Final DQM duty delay cell = 0
2441 12:47:18.232483 [0] MAX Duty = 5280%(X100), DQS PI = 62
2442 12:47:18.235527 [0] MIN Duty = 4875%(X100), DQS PI = 36
2443 12:47:18.239144 [0] AVG Duty = 5077%(X100)
2444 12:47:18.239288
2445 12:47:18.242470 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2446 12:47:18.242602
2447 12:47:18.245683 CH1 DQM 1 Duty spec in!! Max-Min= 405%
2448 12:47:18.248977 [DutyScan_Calibration_Flow] ====Done====
2449 12:47:18.249098
2450 12:47:18.252344 [DutyScan_Calibration_Flow] k_type=2
2451 12:47:18.269149
2452 12:47:18.269288 ==DQ 0 ==
2453 12:47:18.272280 Final DQ duty delay cell = 0
2454 12:47:18.275518 [0] MAX Duty = 5062%(X100), DQS PI = 18
2455 12:47:18.278824 [0] MIN Duty = 4938%(X100), DQS PI = 46
2456 12:47:18.278945 [0] AVG Duty = 5000%(X100)
2457 12:47:18.282281
2458 12:47:18.282377 ==DQ 1 ==
2459 12:47:18.285613 Final DQ duty delay cell = 0
2460 12:47:18.289123 [0] MAX Duty = 5031%(X100), DQS PI = 2
2461 12:47:18.292234 [0] MIN Duty = 4813%(X100), DQS PI = 34
2462 12:47:18.292325 [0] AVG Duty = 4922%(X100)
2463 12:47:18.292392
2464 12:47:18.295763 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2465 12:47:18.295846
2466 12:47:18.302653 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2467 12:47:18.305656 [DutyScan_Calibration_Flow] ====Done====
2468 12:47:18.308911 nWR fixed to 30
2469 12:47:18.309041 [ModeRegInit_LP4] CH0 RK0
2470 12:47:18.312639 [ModeRegInit_LP4] CH0 RK1
2471 12:47:18.315662 [ModeRegInit_LP4] CH1 RK0
2472 12:47:18.315761 [ModeRegInit_LP4] CH1 RK1
2473 12:47:18.319200 match AC timing 7
2474 12:47:18.322457 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2475 12:47:18.326150 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2476 12:47:18.332403 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2477 12:47:18.335859 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2478 12:47:18.342929 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2479 12:47:18.343109 ==
2480 12:47:18.346065 Dram Type= 6, Freq= 0, CH_0, rank 0
2481 12:47:18.349415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2482 12:47:18.349567 ==
2483 12:47:18.356131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2484 12:47:18.359496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2485 12:47:18.368944 [CA 0] Center 38 (8~69) winsize 62
2486 12:47:18.372130 [CA 1] Center 38 (7~69) winsize 63
2487 12:47:18.375513 [CA 2] Center 35 (5~66) winsize 62
2488 12:47:18.379079 [CA 3] Center 35 (4~66) winsize 63
2489 12:47:18.382344 [CA 4] Center 34 (4~65) winsize 62
2490 12:47:18.385488 [CA 5] Center 33 (3~63) winsize 61
2491 12:47:18.385622
2492 12:47:18.388915 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2493 12:47:18.389064
2494 12:47:18.392274 [CATrainingPosCal] consider 1 rank data
2495 12:47:18.395702 u2DelayCellTimex100 = 270/100 ps
2496 12:47:18.398891 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2497 12:47:18.402323 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2498 12:47:18.408878 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2499 12:47:18.412603 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2500 12:47:18.415676 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2501 12:47:18.418838 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2502 12:47:18.418992
2503 12:47:18.422422 CA PerBit enable=1, Macro0, CA PI delay=33
2504 12:47:18.422573
2505 12:47:18.425561 [CBTSetCACLKResult] CA Dly = 33
2506 12:47:18.425710 CS Dly: 6 (0~37)
2507 12:47:18.425818 ==
2508 12:47:18.428846 Dram Type= 6, Freq= 0, CH_0, rank 1
2509 12:47:18.435492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 12:47:18.435651 ==
2511 12:47:18.438980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2512 12:47:18.445774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2513 12:47:18.454573 [CA 0] Center 39 (8~70) winsize 63
2514 12:47:18.458104 [CA 1] Center 38 (8~69) winsize 62
2515 12:47:18.461248 [CA 2] Center 35 (5~66) winsize 62
2516 12:47:18.464702 [CA 3] Center 35 (5~66) winsize 62
2517 12:47:18.468037 [CA 4] Center 34 (4~65) winsize 62
2518 12:47:18.471708 [CA 5] Center 34 (4~64) winsize 61
2519 12:47:18.471831
2520 12:47:18.474666 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2521 12:47:18.474800
2522 12:47:18.478268 [CATrainingPosCal] consider 2 rank data
2523 12:47:18.481710 u2DelayCellTimex100 = 270/100 ps
2524 12:47:18.485085 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2525 12:47:18.487992 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2526 12:47:18.491488 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2527 12:47:18.498214 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2528 12:47:18.501508 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2529 12:47:18.504853 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2530 12:47:18.505005
2531 12:47:18.508494 CA PerBit enable=1, Macro0, CA PI delay=33
2532 12:47:18.508643
2533 12:47:18.511502 [CBTSetCACLKResult] CA Dly = 33
2534 12:47:18.511640 CS Dly: 7 (0~39)
2535 12:47:18.511759
2536 12:47:18.515133 ----->DramcWriteLeveling(PI) begin...
2537 12:47:18.515281 ==
2538 12:47:18.518256 Dram Type= 6, Freq= 0, CH_0, rank 0
2539 12:47:18.525164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 12:47:18.525355 ==
2541 12:47:18.528215 Write leveling (Byte 0): 36 => 36
2542 12:47:18.528353 Write leveling (Byte 1): 30 => 30
2543 12:47:18.532077 DramcWriteLeveling(PI) end<-----
2544 12:47:18.532214
2545 12:47:18.532312 ==
2546 12:47:18.535239 Dram Type= 6, Freq= 0, CH_0, rank 0
2547 12:47:18.541950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2548 12:47:18.542100 ==
2549 12:47:18.545120 [Gating] SW mode calibration
2550 12:47:18.552200 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2551 12:47:18.555884 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2552 12:47:18.562163 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2553 12:47:18.565307 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2554 12:47:18.569062 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2555 12:47:18.572061 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2556 12:47:18.578831 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2557 12:47:18.582283 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2558 12:47:18.585517 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2559 12:47:18.592118 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2560 12:47:18.595765 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2561 12:47:18.598976 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 12:47:18.605764 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2563 12:47:18.609280 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 12:47:18.612703 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 12:47:18.619347 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 12:47:18.622310 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2567 12:47:18.625518 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2568 12:47:18.632361 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
2569 12:47:18.635746 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2570 12:47:18.638968 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 12:47:18.642537 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 12:47:18.649334 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 12:47:18.652790 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 12:47:18.655593 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 12:47:18.662715 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2576 12:47:18.665724 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2577 12:47:18.669050 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 12:47:18.675732 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 12:47:18.679302 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 12:47:18.682325 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 12:47:18.689002 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 12:47:18.692235 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 12:47:18.695820 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 12:47:18.702318 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 12:47:18.705568 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 12:47:18.708973 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 12:47:18.716101 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 12:47:18.719013 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 12:47:18.722908 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 12:47:18.725960 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2591 12:47:18.732590 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2592 12:47:18.735700 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2593 12:47:18.739335 Total UI for P1: 0, mck2ui 16
2594 12:47:18.742543 best dqsien dly found for B0: ( 1, 3, 26)
2595 12:47:18.746063 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 12:47:18.749288 Total UI for P1: 0, mck2ui 16
2597 12:47:18.752581 best dqsien dly found for B1: ( 1, 3, 30)
2598 12:47:18.755908 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2599 12:47:18.759362 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2600 12:47:18.759474
2601 12:47:18.766091 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2602 12:47:18.769475 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2603 12:47:18.769578 [Gating] SW calibration Done
2604 12:47:18.772539 ==
2605 12:47:18.775967 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 12:47:18.779348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 12:47:18.779438 ==
2608 12:47:18.779508 RX Vref Scan: 0
2609 12:47:18.779573
2610 12:47:18.782734 RX Vref 0 -> 0, step: 1
2611 12:47:18.782821
2612 12:47:18.786321 RX Delay -40 -> 252, step: 8
2613 12:47:18.789223 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2614 12:47:18.792832 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2615 12:47:18.796184 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2616 12:47:18.802972 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2617 12:47:18.806090 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2618 12:47:18.809477 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2619 12:47:18.812739 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2620 12:47:18.816241 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2621 12:47:18.822731 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2622 12:47:18.826282 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2623 12:47:18.829538 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2624 12:47:18.832628 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2625 12:47:18.836119 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2626 12:47:18.843178 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2627 12:47:18.846267 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2628 12:47:18.849344 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2629 12:47:18.849421 ==
2630 12:47:18.852849 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 12:47:18.856095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 12:47:18.856222 ==
2633 12:47:18.859309 DQS Delay:
2634 12:47:18.859434 DQS0 = 0, DQS1 = 0
2635 12:47:18.863347 DQM Delay:
2636 12:47:18.863469 DQM0 = 123, DQM1 = 110
2637 12:47:18.863583 DQ Delay:
2638 12:47:18.869540 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2639 12:47:18.872662 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2640 12:47:18.876173 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2641 12:47:18.879734 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2642 12:47:18.879842
2643 12:47:18.879936
2644 12:47:18.880026 ==
2645 12:47:18.883133 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 12:47:18.886262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 12:47:18.886387 ==
2648 12:47:18.886499
2649 12:47:18.886614
2650 12:47:18.889483 TX Vref Scan disable
2651 12:47:18.892676 == TX Byte 0 ==
2652 12:47:18.896116 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2653 12:47:18.899763 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2654 12:47:18.902784 == TX Byte 1 ==
2655 12:47:18.906386 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2656 12:47:18.909667 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2657 12:47:18.909795 ==
2658 12:47:18.913186 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 12:47:18.916045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 12:47:18.916179 ==
2661 12:47:18.929670 TX Vref=22, minBit 5, minWin=24, winSum=406
2662 12:47:18.933138 TX Vref=24, minBit 0, minWin=24, winSum=407
2663 12:47:18.936573 TX Vref=26, minBit 0, minWin=25, winSum=419
2664 12:47:18.940039 TX Vref=28, minBit 1, minWin=25, winSum=423
2665 12:47:18.942971 TX Vref=30, minBit 4, minWin=25, winSum=420
2666 12:47:18.946372 TX Vref=32, minBit 2, minWin=25, winSum=422
2667 12:47:18.953453 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 28
2668 12:47:18.953580
2669 12:47:18.956725 Final TX Range 1 Vref 28
2670 12:47:18.956857
2671 12:47:18.956968 ==
2672 12:47:18.959753 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 12:47:18.963072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 12:47:18.963194 ==
2675 12:47:18.963307
2676 12:47:18.963416
2677 12:47:18.966737 TX Vref Scan disable
2678 12:47:18.969928 == TX Byte 0 ==
2679 12:47:18.972914 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2680 12:47:18.976496 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2681 12:47:18.980104 == TX Byte 1 ==
2682 12:47:18.983166 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2683 12:47:18.986316 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2684 12:47:18.986402
2685 12:47:18.989938 [DATLAT]
2686 12:47:18.990022 Freq=1200, CH0 RK0
2687 12:47:18.990088
2688 12:47:18.993204 DATLAT Default: 0xd
2689 12:47:18.993288 0, 0xFFFF, sum = 0
2690 12:47:18.996412 1, 0xFFFF, sum = 0
2691 12:47:18.996499 2, 0xFFFF, sum = 0
2692 12:47:18.999999 3, 0xFFFF, sum = 0
2693 12:47:19.000084 4, 0xFFFF, sum = 0
2694 12:47:19.003093 5, 0xFFFF, sum = 0
2695 12:47:19.003178 6, 0xFFFF, sum = 0
2696 12:47:19.006463 7, 0xFFFF, sum = 0
2697 12:47:19.006550 8, 0xFFFF, sum = 0
2698 12:47:19.009809 9, 0xFFFF, sum = 0
2699 12:47:19.013251 10, 0xFFFF, sum = 0
2700 12:47:19.013336 11, 0xFFFF, sum = 0
2701 12:47:19.016355 12, 0x0, sum = 1
2702 12:47:19.016445 13, 0x0, sum = 2
2703 12:47:19.016512 14, 0x0, sum = 3
2704 12:47:19.019799 15, 0x0, sum = 4
2705 12:47:19.019890 best_step = 13
2706 12:47:19.019958
2707 12:47:19.020021 ==
2708 12:47:19.023051 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 12:47:19.030220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 12:47:19.030299 ==
2711 12:47:19.030364 RX Vref Scan: 1
2712 12:47:19.030425
2713 12:47:19.033151 Set Vref Range= 32 -> 127
2714 12:47:19.033225
2715 12:47:19.036455 RX Vref 32 -> 127, step: 1
2716 12:47:19.036540
2717 12:47:19.039942 RX Delay -13 -> 252, step: 4
2718 12:47:19.040028
2719 12:47:19.042967 Set Vref, RX VrefLevel [Byte0]: 32
2720 12:47:19.046460 [Byte1]: 32
2721 12:47:19.046544
2722 12:47:19.049654 Set Vref, RX VrefLevel [Byte0]: 33
2723 12:47:19.053276 [Byte1]: 33
2724 12:47:19.053361
2725 12:47:19.056464 Set Vref, RX VrefLevel [Byte0]: 34
2726 12:47:19.059786 [Byte1]: 34
2727 12:47:19.063700
2728 12:47:19.063785 Set Vref, RX VrefLevel [Byte0]: 35
2729 12:47:19.067410 [Byte1]: 35
2730 12:47:19.071603
2731 12:47:19.071688 Set Vref, RX VrefLevel [Byte0]: 36
2732 12:47:19.074951 [Byte1]: 36
2733 12:47:19.079384
2734 12:47:19.079502 Set Vref, RX VrefLevel [Byte0]: 37
2735 12:47:19.082789 [Byte1]: 37
2736 12:47:19.087561
2737 12:47:19.087690 Set Vref, RX VrefLevel [Byte0]: 38
2738 12:47:19.090623 [Byte1]: 38
2739 12:47:19.095055
2740 12:47:19.095182 Set Vref, RX VrefLevel [Byte0]: 39
2741 12:47:19.098841 [Byte1]: 39
2742 12:47:19.103340
2743 12:47:19.103470 Set Vref, RX VrefLevel [Byte0]: 40
2744 12:47:19.106749 [Byte1]: 40
2745 12:47:19.111125
2746 12:47:19.111210 Set Vref, RX VrefLevel [Byte0]: 41
2747 12:47:19.114394 [Byte1]: 41
2748 12:47:19.119178
2749 12:47:19.119263 Set Vref, RX VrefLevel [Byte0]: 42
2750 12:47:19.122206 [Byte1]: 42
2751 12:47:19.127052
2752 12:47:19.127136 Set Vref, RX VrefLevel [Byte0]: 43
2753 12:47:19.130240 [Byte1]: 43
2754 12:47:19.134665
2755 12:47:19.134749 Set Vref, RX VrefLevel [Byte0]: 44
2756 12:47:19.137882 [Byte1]: 44
2757 12:47:19.142834
2758 12:47:19.142919 Set Vref, RX VrefLevel [Byte0]: 45
2759 12:47:19.145931 [Byte1]: 45
2760 12:47:19.150379
2761 12:47:19.150465 Set Vref, RX VrefLevel [Byte0]: 46
2762 12:47:19.154023 [Byte1]: 46
2763 12:47:19.158461
2764 12:47:19.158588 Set Vref, RX VrefLevel [Byte0]: 47
2765 12:47:19.161904 [Byte1]: 47
2766 12:47:19.166087
2767 12:47:19.166212 Set Vref, RX VrefLevel [Byte0]: 48
2768 12:47:19.169769 [Byte1]: 48
2769 12:47:19.174078
2770 12:47:19.174184 Set Vref, RX VrefLevel [Byte0]: 49
2771 12:47:19.177622 [Byte1]: 49
2772 12:47:19.182176
2773 12:47:19.182271 Set Vref, RX VrefLevel [Byte0]: 50
2774 12:47:19.185188 [Byte1]: 50
2775 12:47:19.190187
2776 12:47:19.190276 Set Vref, RX VrefLevel [Byte0]: 51
2777 12:47:19.193020 [Byte1]: 51
2778 12:47:19.197772
2779 12:47:19.197857 Set Vref, RX VrefLevel [Byte0]: 52
2780 12:47:19.201254 [Byte1]: 52
2781 12:47:19.205837
2782 12:47:19.205920 Set Vref, RX VrefLevel [Byte0]: 53
2783 12:47:19.209237 [Byte1]: 53
2784 12:47:19.213436
2785 12:47:19.213563 Set Vref, RX VrefLevel [Byte0]: 54
2786 12:47:19.216871 [Byte1]: 54
2787 12:47:19.221552
2788 12:47:19.221685 Set Vref, RX VrefLevel [Byte0]: 55
2789 12:47:19.224827 [Byte1]: 55
2790 12:47:19.229277
2791 12:47:19.232707 Set Vref, RX VrefLevel [Byte0]: 56
2792 12:47:19.235800 [Byte1]: 56
2793 12:47:19.235911
2794 12:47:19.239261 Set Vref, RX VrefLevel [Byte0]: 57
2795 12:47:19.242567 [Byte1]: 57
2796 12:47:19.242653
2797 12:47:19.246022 Set Vref, RX VrefLevel [Byte0]: 58
2798 12:47:19.249071 [Byte1]: 58
2799 12:47:19.252825
2800 12:47:19.252945 Set Vref, RX VrefLevel [Byte0]: 59
2801 12:47:19.256265 [Byte1]: 59
2802 12:47:19.261145
2803 12:47:19.261230 Set Vref, RX VrefLevel [Byte0]: 60
2804 12:47:19.264311 [Byte1]: 60
2805 12:47:19.268939
2806 12:47:19.269026 Set Vref, RX VrefLevel [Byte0]: 61
2807 12:47:19.272266 [Byte1]: 61
2808 12:47:19.276585
2809 12:47:19.276699 Set Vref, RX VrefLevel [Byte0]: 62
2810 12:47:19.280131 [Byte1]: 62
2811 12:47:19.284572
2812 12:47:19.284685 Set Vref, RX VrefLevel [Byte0]: 63
2813 12:47:19.287823 [Byte1]: 63
2814 12:47:19.292653
2815 12:47:19.292782 Set Vref, RX VrefLevel [Byte0]: 64
2816 12:47:19.295672 [Byte1]: 64
2817 12:47:19.300690
2818 12:47:19.300802 Set Vref, RX VrefLevel [Byte0]: 65
2819 12:47:19.303608 [Byte1]: 65
2820 12:47:19.308473
2821 12:47:19.308591 Set Vref, RX VrefLevel [Byte0]: 66
2822 12:47:19.311548 [Byte1]: 66
2823 12:47:19.316034
2824 12:47:19.316118 Set Vref, RX VrefLevel [Byte0]: 67
2825 12:47:19.319467 [Byte1]: 67
2826 12:47:19.324137
2827 12:47:19.324220 Set Vref, RX VrefLevel [Byte0]: 68
2828 12:47:19.327282 [Byte1]: 68
2829 12:47:19.332303
2830 12:47:19.332408 Set Vref, RX VrefLevel [Byte0]: 69
2831 12:47:19.335260 [Byte1]: 69
2832 12:47:19.339941
2833 12:47:19.340054 Final RX Vref Byte 0 = 58 to rank0
2834 12:47:19.343068 Final RX Vref Byte 1 = 48 to rank0
2835 12:47:19.346592 Final RX Vref Byte 0 = 58 to rank1
2836 12:47:19.350064 Final RX Vref Byte 1 = 48 to rank1==
2837 12:47:19.353208 Dram Type= 6, Freq= 0, CH_0, rank 0
2838 12:47:19.356999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2839 12:47:19.359989 ==
2840 12:47:19.360066 DQS Delay:
2841 12:47:19.360130 DQS0 = 0, DQS1 = 0
2842 12:47:19.363144 DQM Delay:
2843 12:47:19.363227 DQM0 = 123, DQM1 = 109
2844 12:47:19.366459 DQ Delay:
2845 12:47:19.369927 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2846 12:47:19.373328 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2847 12:47:19.376733 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2848 12:47:19.379907 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =118
2849 12:47:19.379981
2850 12:47:19.380058
2851 12:47:19.386656 [DQSOSCAuto] RK0, (LSB)MR18= 0xa07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2852 12:47:19.389892 CH0 RK0: MR19=404, MR18=A07
2853 12:47:19.396338 CH0_RK0: MR19=0x404, MR18=0xA07, DQSOSC=406, MR23=63, INC=39, DEC=26
2854 12:47:19.396426
2855 12:47:19.400071 ----->DramcWriteLeveling(PI) begin...
2856 12:47:19.400157 ==
2857 12:47:19.403537 Dram Type= 6, Freq= 0, CH_0, rank 1
2858 12:47:19.406639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 12:47:19.406773 ==
2860 12:47:19.410023 Write leveling (Byte 0): 35 => 35
2861 12:47:19.413436 Write leveling (Byte 1): 31 => 31
2862 12:47:19.416812 DramcWriteLeveling(PI) end<-----
2863 12:47:19.416887
2864 12:47:19.416950 ==
2865 12:47:19.419875 Dram Type= 6, Freq= 0, CH_0, rank 1
2866 12:47:19.423629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2867 12:47:19.426726 ==
2868 12:47:19.426800 [Gating] SW mode calibration
2869 12:47:19.433446 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2870 12:47:19.440130 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2871 12:47:19.443671 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2872 12:47:19.450022 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 12:47:19.453625 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2874 12:47:19.456867 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2875 12:47:19.463743 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2876 12:47:19.467232 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 12:47:19.470354 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2878 12:47:19.477054 0 15 28 | B1->B0 | 2f2f 2e2e | 1 1 | (1 0) (1 0)
2879 12:47:19.480182 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 12:47:19.483950 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 12:47:19.487009 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 12:47:19.493594 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 12:47:19.496820 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2884 12:47:19.500105 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 12:47:19.507210 1 0 24 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
2886 12:47:19.510700 1 0 28 | B1->B0 | 3938 3d3d | 1 1 | (0 0) (0 0)
2887 12:47:19.513558 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 12:47:19.520333 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 12:47:19.523827 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 12:47:19.527370 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 12:47:19.533842 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 12:47:19.537180 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 12:47:19.540651 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 12:47:19.547284 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2895 12:47:19.550406 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:47:19.553800 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 12:47:19.557599 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 12:47:19.563791 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 12:47:19.567153 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 12:47:19.570692 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 12:47:19.577343 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 12:47:19.580392 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 12:47:19.583912 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 12:47:19.590635 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 12:47:19.593834 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 12:47:19.597266 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 12:47:19.603972 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 12:47:19.607207 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 12:47:19.610960 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 12:47:19.617319 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2911 12:47:19.620766 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2912 12:47:19.623912 Total UI for P1: 0, mck2ui 16
2913 12:47:19.627720 best dqsien dly found for B1: ( 1, 3, 28)
2914 12:47:19.630862 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 12:47:19.633853 Total UI for P1: 0, mck2ui 16
2916 12:47:19.637585 best dqsien dly found for B0: ( 1, 3, 30)
2917 12:47:19.640969 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2918 12:47:19.644220 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2919 12:47:19.644341
2920 12:47:19.647830 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2921 12:47:19.650630 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2922 12:47:19.654144 [Gating] SW calibration Done
2923 12:47:19.654268 ==
2924 12:47:19.657610 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 12:47:19.664434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 12:47:19.664557 ==
2927 12:47:19.664669 RX Vref Scan: 0
2928 12:47:19.664822
2929 12:47:19.667310 RX Vref 0 -> 0, step: 1
2930 12:47:19.667428
2931 12:47:19.670714 RX Delay -40 -> 252, step: 8
2932 12:47:19.674220 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2933 12:47:19.677413 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2934 12:47:19.681071 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2935 12:47:19.684184 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2936 12:47:19.690820 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2937 12:47:19.693899 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2938 12:47:19.697477 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2939 12:47:19.700596 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2940 12:47:19.704137 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2941 12:47:19.710790 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2942 12:47:19.714046 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2943 12:47:19.717462 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2944 12:47:19.720746 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2945 12:47:19.724355 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2946 12:47:19.731007 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2947 12:47:19.734284 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2948 12:47:19.734383 ==
2949 12:47:19.737668 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 12:47:19.741007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 12:47:19.741106 ==
2952 12:47:19.741189 DQS Delay:
2953 12:47:19.744186 DQS0 = 0, DQS1 = 0
2954 12:47:19.744367 DQM Delay:
2955 12:47:19.747690 DQM0 = 120, DQM1 = 108
2956 12:47:19.747822 DQ Delay:
2957 12:47:19.750951 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2958 12:47:19.754278 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2959 12:47:19.757602 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2960 12:47:19.760996 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2961 12:47:19.761123
2962 12:47:19.764369
2963 12:47:19.764492 ==
2964 12:47:19.767374 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 12:47:19.770855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 12:47:19.770981 ==
2967 12:47:19.771100
2968 12:47:19.771209
2969 12:47:19.774108 TX Vref Scan disable
2970 12:47:19.774230 == TX Byte 0 ==
2971 12:47:19.781247 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2972 12:47:19.784328 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2973 12:47:19.784464 == TX Byte 1 ==
2974 12:47:19.790936 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2975 12:47:19.794220 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2976 12:47:19.794341 ==
2977 12:47:19.797327 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 12:47:19.800584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 12:47:19.800706 ==
2980 12:47:19.813575 TX Vref=22, minBit 5, minWin=24, winSum=408
2981 12:47:19.816777 TX Vref=24, minBit 1, minWin=24, winSum=411
2982 12:47:19.820303 TX Vref=26, minBit 1, minWin=24, winSum=413
2983 12:47:19.823592 TX Vref=28, minBit 0, minWin=25, winSum=414
2984 12:47:19.827008 TX Vref=30, minBit 3, minWin=25, winSum=417
2985 12:47:19.830004 TX Vref=32, minBit 2, minWin=25, winSum=418
2986 12:47:19.837086 [TxChooseVref] Worse bit 2, Min win 25, Win sum 418, Final Vref 32
2987 12:47:19.837210
2988 12:47:19.839930 Final TX Range 1 Vref 32
2989 12:47:19.840046
2990 12:47:19.840149 ==
2991 12:47:19.843523 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 12:47:19.846911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 12:47:19.847045 ==
2994 12:47:19.847157
2995 12:47:19.849991
2996 12:47:19.850113 TX Vref Scan disable
2997 12:47:19.853677 == TX Byte 0 ==
2998 12:47:19.856825 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2999 12:47:19.860206 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3000 12:47:19.863534 == TX Byte 1 ==
3001 12:47:19.866731 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3002 12:47:19.870242 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3003 12:47:19.870365
3004 12:47:19.873524 [DATLAT]
3005 12:47:19.873645 Freq=1200, CH0 RK1
3006 12:47:19.873758
3007 12:47:19.876812 DATLAT Default: 0xd
3008 12:47:19.876934 0, 0xFFFF, sum = 0
3009 12:47:19.880324 1, 0xFFFF, sum = 0
3010 12:47:19.880448 2, 0xFFFF, sum = 0
3011 12:47:19.883470 3, 0xFFFF, sum = 0
3012 12:47:19.883598 4, 0xFFFF, sum = 0
3013 12:47:19.886806 5, 0xFFFF, sum = 0
3014 12:47:19.886939 6, 0xFFFF, sum = 0
3015 12:47:19.890028 7, 0xFFFF, sum = 0
3016 12:47:19.890154 8, 0xFFFF, sum = 0
3017 12:47:19.893469 9, 0xFFFF, sum = 0
3018 12:47:19.896530 10, 0xFFFF, sum = 0
3019 12:47:19.896655 11, 0xFFFF, sum = 0
3020 12:47:19.900055 12, 0x0, sum = 1
3021 12:47:19.900181 13, 0x0, sum = 2
3022 12:47:19.900292 14, 0x0, sum = 3
3023 12:47:19.903380 15, 0x0, sum = 4
3024 12:47:19.903505 best_step = 13
3025 12:47:19.903613
3026 12:47:19.906841 ==
3027 12:47:19.906964 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 12:47:19.913814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 12:47:19.913947 ==
3030 12:47:19.914064 RX Vref Scan: 0
3031 12:47:19.914177
3032 12:47:19.916767 RX Vref 0 -> 0, step: 1
3033 12:47:19.916881
3034 12:47:19.920361 RX Delay -21 -> 252, step: 4
3035 12:47:19.923873 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3036 12:47:19.926857 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3037 12:47:19.933421 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3038 12:47:19.936758 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3039 12:47:19.940392 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3040 12:47:19.943401 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3041 12:47:19.946777 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3042 12:47:19.953476 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3043 12:47:19.957158 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3044 12:47:19.960416 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3045 12:47:19.963376 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3046 12:47:19.967051 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3047 12:47:19.974209 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3048 12:47:19.977202 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3049 12:47:19.980308 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3050 12:47:19.983867 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3051 12:47:19.984000 ==
3052 12:47:19.986944 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 12:47:19.990394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 12:47:19.993846 ==
3055 12:47:19.993968 DQS Delay:
3056 12:47:19.994085 DQS0 = 0, DQS1 = 0
3057 12:47:19.996896 DQM Delay:
3058 12:47:19.997008 DQM0 = 120, DQM1 = 107
3059 12:47:20.000241 DQ Delay:
3060 12:47:20.003668 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =116
3061 12:47:20.007153 DQ4 =120, DQ5 =116, DQ6 =126, DQ7 =126
3062 12:47:20.010507 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3063 12:47:20.013588 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3064 12:47:20.013695
3065 12:47:20.013798
3066 12:47:20.020608 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3067 12:47:20.023901 CH0 RK1: MR19=403, MR18=CF3
3068 12:47:20.030309 CH0_RK1: MR19=0x403, MR18=0xCF3, DQSOSC=405, MR23=63, INC=39, DEC=26
3069 12:47:20.033759 [RxdqsGatingPostProcess] freq 1200
3070 12:47:20.037338 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3071 12:47:20.040572 best DQS0 dly(2T, 0.5T) = (0, 11)
3072 12:47:20.043679 best DQS1 dly(2T, 0.5T) = (0, 11)
3073 12:47:20.047287 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3074 12:47:20.050435 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3075 12:47:20.053729 best DQS0 dly(2T, 0.5T) = (0, 11)
3076 12:47:20.057147 best DQS1 dly(2T, 0.5T) = (0, 11)
3077 12:47:20.060832 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3078 12:47:20.064063 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3079 12:47:20.067071 Pre-setting of DQS Precalculation
3080 12:47:20.070509 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3081 12:47:20.070624 ==
3082 12:47:20.073890 Dram Type= 6, Freq= 0, CH_1, rank 0
3083 12:47:20.080593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 12:47:20.080682 ==
3085 12:47:20.083861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3086 12:47:20.090740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3087 12:47:20.099398 [CA 0] Center 37 (7~68) winsize 62
3088 12:47:20.102781 [CA 1] Center 37 (7~68) winsize 62
3089 12:47:20.106471 [CA 2] Center 35 (5~65) winsize 61
3090 12:47:20.109423 [CA 3] Center 34 (4~65) winsize 62
3091 12:47:20.112458 [CA 4] Center 34 (4~65) winsize 62
3092 12:47:20.116065 [CA 5] Center 33 (3~64) winsize 62
3093 12:47:20.116178
3094 12:47:20.119441 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3095 12:47:20.119541
3096 12:47:20.122707 [CATrainingPosCal] consider 1 rank data
3097 12:47:20.126191 u2DelayCellTimex100 = 270/100 ps
3098 12:47:20.129369 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3099 12:47:20.132657 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3100 12:47:20.136298 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3101 12:47:20.143129 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3102 12:47:20.146518 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3103 12:47:20.149708 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3104 12:47:20.149849
3105 12:47:20.152841 CA PerBit enable=1, Macro0, CA PI delay=33
3106 12:47:20.152926
3107 12:47:20.156466 [CBTSetCACLKResult] CA Dly = 33
3108 12:47:20.156551 CS Dly: 5 (0~36)
3109 12:47:20.156617 ==
3110 12:47:20.159796 Dram Type= 6, Freq= 0, CH_1, rank 1
3111 12:47:20.166272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 12:47:20.166375 ==
3113 12:47:20.169449 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3114 12:47:20.176326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3115 12:47:20.185006 [CA 0] Center 38 (8~68) winsize 61
3116 12:47:20.188444 [CA 1] Center 38 (7~69) winsize 63
3117 12:47:20.191645 [CA 2] Center 35 (5~66) winsize 62
3118 12:47:20.194935 [CA 3] Center 35 (5~65) winsize 61
3119 12:47:20.198563 [CA 4] Center 34 (4~64) winsize 61
3120 12:47:20.201532 [CA 5] Center 34 (4~64) winsize 61
3121 12:47:20.201617
3122 12:47:20.205151 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3123 12:47:20.205273
3124 12:47:20.208569 [CATrainingPosCal] consider 2 rank data
3125 12:47:20.212038 u2DelayCellTimex100 = 270/100 ps
3126 12:47:20.214981 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3127 12:47:20.218569 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3128 12:47:20.225395 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3129 12:47:20.228472 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3130 12:47:20.231707 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3131 12:47:20.235080 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3132 12:47:20.235164
3133 12:47:20.238594 CA PerBit enable=1, Macro0, CA PI delay=34
3134 12:47:20.238677
3135 12:47:20.242273 [CBTSetCACLKResult] CA Dly = 34
3136 12:47:20.242372 CS Dly: 6 (0~39)
3137 12:47:20.242471
3138 12:47:20.245292 ----->DramcWriteLeveling(PI) begin...
3139 12:47:20.245377 ==
3140 12:47:20.248623 Dram Type= 6, Freq= 0, CH_1, rank 0
3141 12:47:20.255106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 12:47:20.255231 ==
3143 12:47:20.258490 Write leveling (Byte 0): 24 => 24
3144 12:47:20.261904 Write leveling (Byte 1): 27 => 27
3145 12:47:20.261990 DramcWriteLeveling(PI) end<-----
3146 12:47:20.265420
3147 12:47:20.265502 ==
3148 12:47:20.268731 Dram Type= 6, Freq= 0, CH_1, rank 0
3149 12:47:20.271875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3150 12:47:20.271957 ==
3151 12:47:20.275496 [Gating] SW mode calibration
3152 12:47:20.282151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3153 12:47:20.285320 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3154 12:47:20.291945 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 12:47:20.295199 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 12:47:20.298708 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3157 12:47:20.305376 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 12:47:20.308650 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 12:47:20.312265 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3160 12:47:20.318624 0 15 24 | B1->B0 | 2e2e 2727 | 0 0 | (0 1) (1 0)
3161 12:47:20.322313 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 12:47:20.325366 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 12:47:20.328712 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 12:47:20.335383 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 12:47:20.338944 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 12:47:20.342727 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 12:47:20.349119 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 12:47:20.352539 1 0 24 | B1->B0 | 3838 3e3e | 0 1 | (0 0) (0 0)
3169 12:47:20.355382 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 12:47:20.362289 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 12:47:20.365403 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 12:47:20.368696 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 12:47:20.375445 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 12:47:20.378740 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 12:47:20.382334 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 12:47:20.388623 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3177 12:47:20.392044 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3178 12:47:20.395628 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 12:47:20.402315 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 12:47:20.405565 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 12:47:20.408807 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 12:47:20.415396 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 12:47:20.418902 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 12:47:20.421973 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 12:47:20.428952 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 12:47:20.431801 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 12:47:20.435305 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 12:47:20.438531 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 12:47:20.445673 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 12:47:20.448572 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 12:47:20.455235 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3192 12:47:20.458482 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3193 12:47:20.461622 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 12:47:20.465400 Total UI for P1: 0, mck2ui 16
3195 12:47:20.468587 best dqsien dly found for B0: ( 1, 3, 22)
3196 12:47:20.471821 Total UI for P1: 0, mck2ui 16
3197 12:47:20.474821 best dqsien dly found for B1: ( 1, 3, 24)
3198 12:47:20.478160 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3199 12:47:20.481397 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3200 12:47:20.481479
3201 12:47:20.485173 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3202 12:47:20.491757 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3203 12:47:20.491896 [Gating] SW calibration Done
3204 12:47:20.491989 ==
3205 12:47:20.494877 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 12:47:20.501797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 12:47:20.501896 ==
3208 12:47:20.501988 RX Vref Scan: 0
3209 12:47:20.502050
3210 12:47:20.504975 RX Vref 0 -> 0, step: 1
3211 12:47:20.505057
3212 12:47:20.508288 RX Delay -40 -> 252, step: 8
3213 12:47:20.511736 iDelay=200, Bit 0, Center 119 (56 ~ 183) 128
3214 12:47:20.514977 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3215 12:47:20.518323 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3216 12:47:20.521450 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3217 12:47:20.528615 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3218 12:47:20.531963 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3219 12:47:20.535173 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3220 12:47:20.538227 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3221 12:47:20.541716 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3222 12:47:20.548661 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3223 12:47:20.551747 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3224 12:47:20.554914 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3225 12:47:20.558349 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3226 12:47:20.561792 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3227 12:47:20.568569 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3228 12:47:20.571821 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3229 12:47:20.571906 ==
3230 12:47:20.575296 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 12:47:20.578612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 12:47:20.578697 ==
3233 12:47:20.578763 DQS Delay:
3234 12:47:20.582192 DQS0 = 0, DQS1 = 0
3235 12:47:20.582307 DQM Delay:
3236 12:47:20.585466 DQM0 = 119, DQM1 = 112
3237 12:47:20.585577 DQ Delay:
3238 12:47:20.588444 DQ0 =119, DQ1 =115, DQ2 =111, DQ3 =123
3239 12:47:20.591891 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3240 12:47:20.595189 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3241 12:47:20.598827 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3242 12:47:20.601757
3243 12:47:20.601892
3244 12:47:20.602003 ==
3245 12:47:20.605147 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 12:47:20.608577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 12:47:20.608702 ==
3248 12:47:20.608828
3249 12:47:20.608944
3250 12:47:20.611893 TX Vref Scan disable
3251 12:47:20.612016 == TX Byte 0 ==
3252 12:47:20.621637 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3253 12:47:20.622096 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3254 12:47:20.622223 == TX Byte 1 ==
3255 12:47:20.625172 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3256 12:47:20.631899 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3257 12:47:20.632007 ==
3258 12:47:20.635525 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 12:47:20.638616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 12:47:20.638716 ==
3261 12:47:20.650596 TX Vref=22, minBit 10, minWin=24, winSum=404
3262 12:47:20.653891 TX Vref=24, minBit 10, minWin=24, winSum=408
3263 12:47:20.657187 TX Vref=26, minBit 8, minWin=25, winSum=415
3264 12:47:20.660656 TX Vref=28, minBit 10, minWin=25, winSum=417
3265 12:47:20.664403 TX Vref=30, minBit 10, minWin=25, winSum=423
3266 12:47:20.670913 TX Vref=32, minBit 12, minWin=25, winSum=422
3267 12:47:20.673910 [TxChooseVref] Worse bit 10, Min win 25, Win sum 423, Final Vref 30
3268 12:47:20.674039
3269 12:47:20.677545 Final TX Range 1 Vref 30
3270 12:47:20.677652
3271 12:47:20.677747 ==
3272 12:47:20.680879 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 12:47:20.684169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 12:47:20.687317 ==
3275 12:47:20.687406
3276 12:47:20.687473
3277 12:47:20.687535 TX Vref Scan disable
3278 12:47:20.690855 == TX Byte 0 ==
3279 12:47:20.694364 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3280 12:47:20.697550 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3281 12:47:20.701001 == TX Byte 1 ==
3282 12:47:20.704197 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3283 12:47:20.707715 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3284 12:47:20.711130
3285 12:47:20.711214 [DATLAT]
3286 12:47:20.711282 Freq=1200, CH1 RK0
3287 12:47:20.711346
3288 12:47:20.714288 DATLAT Default: 0xd
3289 12:47:20.714373 0, 0xFFFF, sum = 0
3290 12:47:20.717490 1, 0xFFFF, sum = 0
3291 12:47:20.717578 2, 0xFFFF, sum = 0
3292 12:47:20.721033 3, 0xFFFF, sum = 0
3293 12:47:20.721118 4, 0xFFFF, sum = 0
3294 12:47:20.724540 5, 0xFFFF, sum = 0
3295 12:47:20.727606 6, 0xFFFF, sum = 0
3296 12:47:20.727693 7, 0xFFFF, sum = 0
3297 12:47:20.730780 8, 0xFFFF, sum = 0
3298 12:47:20.730881 9, 0xFFFF, sum = 0
3299 12:47:20.734215 10, 0xFFFF, sum = 0
3300 12:47:20.734300 11, 0xFFFF, sum = 0
3301 12:47:20.737565 12, 0x0, sum = 1
3302 12:47:20.737649 13, 0x0, sum = 2
3303 12:47:20.740980 14, 0x0, sum = 3
3304 12:47:20.741065 15, 0x0, sum = 4
3305 12:47:20.741131 best_step = 13
3306 12:47:20.741192
3307 12:47:20.744351 ==
3308 12:47:20.747773 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 12:47:20.750912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 12:47:20.750995 ==
3311 12:47:20.751060 RX Vref Scan: 1
3312 12:47:20.751120
3313 12:47:20.754403 Set Vref Range= 32 -> 127
3314 12:47:20.754486
3315 12:47:20.757521 RX Vref 32 -> 127, step: 1
3316 12:47:20.757620
3317 12:47:20.760671 RX Delay -13 -> 252, step: 4
3318 12:47:20.760799
3319 12:47:20.764384 Set Vref, RX VrefLevel [Byte0]: 32
3320 12:47:20.767306 [Byte1]: 32
3321 12:47:20.767388
3322 12:47:20.770840 Set Vref, RX VrefLevel [Byte0]: 33
3323 12:47:20.774342 [Byte1]: 33
3324 12:47:20.774452
3325 12:47:20.777467 Set Vref, RX VrefLevel [Byte0]: 34
3326 12:47:20.781138 [Byte1]: 34
3327 12:47:20.785073
3328 12:47:20.785155 Set Vref, RX VrefLevel [Byte0]: 35
3329 12:47:20.788429 [Byte1]: 35
3330 12:47:20.793077
3331 12:47:20.793158 Set Vref, RX VrefLevel [Byte0]: 36
3332 12:47:20.796282 [Byte1]: 36
3333 12:47:20.801079
3334 12:47:20.801174 Set Vref, RX VrefLevel [Byte0]: 37
3335 12:47:20.804228 [Byte1]: 37
3336 12:47:20.808649
3337 12:47:20.808731 Set Vref, RX VrefLevel [Byte0]: 38
3338 12:47:20.812082 [Byte1]: 38
3339 12:47:20.816928
3340 12:47:20.817009 Set Vref, RX VrefLevel [Byte0]: 39
3341 12:47:20.820080 [Byte1]: 39
3342 12:47:20.824640
3343 12:47:20.824720 Set Vref, RX VrefLevel [Byte0]: 40
3344 12:47:20.827830 [Byte1]: 40
3345 12:47:20.832319
3346 12:47:20.832418 Set Vref, RX VrefLevel [Byte0]: 41
3347 12:47:20.835834 [Byte1]: 41
3348 12:47:20.840220
3349 12:47:20.840303 Set Vref, RX VrefLevel [Byte0]: 42
3350 12:47:20.843626 [Byte1]: 42
3351 12:47:20.848440
3352 12:47:20.851400 Set Vref, RX VrefLevel [Byte0]: 43
3353 12:47:20.851482 [Byte1]: 43
3354 12:47:20.856492
3355 12:47:20.856574 Set Vref, RX VrefLevel [Byte0]: 44
3356 12:47:20.859281 [Byte1]: 44
3357 12:47:20.864097
3358 12:47:20.864178 Set Vref, RX VrefLevel [Byte0]: 45
3359 12:47:20.867567 [Byte1]: 45
3360 12:47:20.871703
3361 12:47:20.871784 Set Vref, RX VrefLevel [Byte0]: 46
3362 12:47:20.875162 [Byte1]: 46
3363 12:47:20.879746
3364 12:47:20.879827 Set Vref, RX VrefLevel [Byte0]: 47
3365 12:47:20.882953 [Byte1]: 47
3366 12:47:20.887716
3367 12:47:20.887797 Set Vref, RX VrefLevel [Byte0]: 48
3368 12:47:20.890853 [Byte1]: 48
3369 12:47:20.895416
3370 12:47:20.895535 Set Vref, RX VrefLevel [Byte0]: 49
3371 12:47:20.899057 [Byte1]: 49
3372 12:47:20.903570
3373 12:47:20.903691 Set Vref, RX VrefLevel [Byte0]: 50
3374 12:47:20.906727 [Byte1]: 50
3375 12:47:20.911137
3376 12:47:20.911254 Set Vref, RX VrefLevel [Byte0]: 51
3377 12:47:20.917721 [Byte1]: 51
3378 12:47:20.917840
3379 12:47:20.921509 Set Vref, RX VrefLevel [Byte0]: 52
3380 12:47:20.924541 [Byte1]: 52
3381 12:47:20.924652
3382 12:47:20.927935 Set Vref, RX VrefLevel [Byte0]: 53
3383 12:47:20.931002 [Byte1]: 53
3384 12:47:20.935072
3385 12:47:20.935189 Set Vref, RX VrefLevel [Byte0]: 54
3386 12:47:20.938667 [Byte1]: 54
3387 12:47:20.943093
3388 12:47:20.943210 Set Vref, RX VrefLevel [Byte0]: 55
3389 12:47:20.946452 [Byte1]: 55
3390 12:47:20.950880
3391 12:47:20.951001 Set Vref, RX VrefLevel [Byte0]: 56
3392 12:47:20.953944 [Byte1]: 56
3393 12:47:20.958599
3394 12:47:20.958719 Set Vref, RX VrefLevel [Byte0]: 57
3395 12:47:20.962157 [Byte1]: 57
3396 12:47:20.966392
3397 12:47:20.966507 Set Vref, RX VrefLevel [Byte0]: 58
3398 12:47:20.970029 [Byte1]: 58
3399 12:47:20.974520
3400 12:47:20.974638 Set Vref, RX VrefLevel [Byte0]: 59
3401 12:47:20.977863 [Byte1]: 59
3402 12:47:20.982804
3403 12:47:20.982959 Set Vref, RX VrefLevel [Byte0]: 60
3404 12:47:20.985762 [Byte1]: 60
3405 12:47:20.990132
3406 12:47:20.990251 Set Vref, RX VrefLevel [Byte0]: 61
3407 12:47:20.993543 [Byte1]: 61
3408 12:47:20.997879
3409 12:47:20.997985 Set Vref, RX VrefLevel [Byte0]: 62
3410 12:47:21.001497 [Byte1]: 62
3411 12:47:21.006023
3412 12:47:21.006143 Set Vref, RX VrefLevel [Byte0]: 63
3413 12:47:21.009681 [Byte1]: 63
3414 12:47:21.013801
3415 12:47:21.013930 Set Vref, RX VrefLevel [Byte0]: 64
3416 12:47:21.017439 [Byte1]: 64
3417 12:47:21.022101
3418 12:47:21.022221 Set Vref, RX VrefLevel [Byte0]: 65
3419 12:47:21.025179 [Byte1]: 65
3420 12:47:21.029840
3421 12:47:21.029963 Set Vref, RX VrefLevel [Byte0]: 66
3422 12:47:21.033249 [Byte1]: 66
3423 12:47:21.037538
3424 12:47:21.037661 Final RX Vref Byte 0 = 53 to rank0
3425 12:47:21.040863 Final RX Vref Byte 1 = 53 to rank0
3426 12:47:21.044030 Final RX Vref Byte 0 = 53 to rank1
3427 12:47:21.047703 Final RX Vref Byte 1 = 53 to rank1==
3428 12:47:21.050759 Dram Type= 6, Freq= 0, CH_1, rank 0
3429 12:47:21.057846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 12:47:21.057971 ==
3431 12:47:21.058086 DQS Delay:
3432 12:47:21.058195 DQS0 = 0, DQS1 = 0
3433 12:47:21.061027 DQM Delay:
3434 12:47:21.061147 DQM0 = 119, DQM1 = 112
3435 12:47:21.064300 DQ Delay:
3436 12:47:21.067734 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3437 12:47:21.070822 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3438 12:47:21.074241 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3439 12:47:21.077488 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3440 12:47:21.077608
3441 12:47:21.077754
3442 12:47:21.084241 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3443 12:47:21.087621 CH1 RK0: MR19=404, MR18=13
3444 12:47:21.094458 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3445 12:47:21.094543
3446 12:47:21.097671 ----->DramcWriteLeveling(PI) begin...
3447 12:47:21.097768 ==
3448 12:47:21.100992 Dram Type= 6, Freq= 0, CH_1, rank 1
3449 12:47:21.104084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 12:47:21.104167 ==
3451 12:47:21.107568 Write leveling (Byte 0): 25 => 25
3452 12:47:21.111219 Write leveling (Byte 1): 28 => 28
3453 12:47:21.114411 DramcWriteLeveling(PI) end<-----
3454 12:47:21.114495
3455 12:47:21.114559 ==
3456 12:47:21.117479 Dram Type= 6, Freq= 0, CH_1, rank 1
3457 12:47:21.121319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 12:47:21.124334 ==
3459 12:47:21.124415 [Gating] SW mode calibration
3460 12:47:21.130993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3461 12:47:21.137569 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3462 12:47:21.140969 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 12:47:21.147641 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 12:47:21.151144 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 12:47:21.154260 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 12:47:21.161511 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 12:47:21.164592 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3468 12:47:21.167990 0 15 24 | B1->B0 | 2d2d 3434 | 1 1 | (1 0) (1 0)
3469 12:47:21.171519 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (1 0) (0 1)
3470 12:47:21.178015 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 12:47:21.181486 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 12:47:21.184586 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 12:47:21.190922 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 12:47:21.194523 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 12:47:21.197556 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 12:47:21.204404 1 0 24 | B1->B0 | 3c3c 2727 | 0 0 | (0 0) (0 0)
3477 12:47:21.207869 1 0 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
3478 12:47:21.211176 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 12:47:21.217866 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 12:47:21.221028 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 12:47:21.224554 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 12:47:21.231203 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 12:47:21.234689 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 12:47:21.238193 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3485 12:47:21.244866 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3486 12:47:21.247723 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 12:47:21.251330 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 12:47:21.254484 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 12:47:21.261071 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 12:47:21.264634 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 12:47:21.268008 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 12:47:21.274551 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 12:47:21.277613 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 12:47:21.281331 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 12:47:21.287798 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 12:47:21.291366 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 12:47:21.294416 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 12:47:21.300932 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 12:47:21.304359 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 12:47:21.307754 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3501 12:47:21.314247 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3502 12:47:21.318026 Total UI for P1: 0, mck2ui 16
3503 12:47:21.321040 best dqsien dly found for B0: ( 1, 3, 24)
3504 12:47:21.324360 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 12:47:21.327595 Total UI for P1: 0, mck2ui 16
3506 12:47:21.330689 best dqsien dly found for B1: ( 1, 3, 26)
3507 12:47:21.334207 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3508 12:47:21.337595 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3509 12:47:21.337726
3510 12:47:21.340735 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3511 12:47:21.344059 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3512 12:47:21.347573 [Gating] SW calibration Done
3513 12:47:21.347655 ==
3514 12:47:21.350716 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 12:47:21.353921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 12:47:21.357226 ==
3517 12:47:21.357307 RX Vref Scan: 0
3518 12:47:21.357372
3519 12:47:21.360661 RX Vref 0 -> 0, step: 1
3520 12:47:21.360764
3521 12:47:21.363881 RX Delay -40 -> 252, step: 8
3522 12:47:21.367405 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3523 12:47:21.371078 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3524 12:47:21.374039 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3525 12:47:21.377371 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3526 12:47:21.384180 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3527 12:47:21.387268 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3528 12:47:21.390765 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3529 12:47:21.393904 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3530 12:47:21.397232 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3531 12:47:21.404138 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3532 12:47:21.407278 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3533 12:47:21.410378 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3534 12:47:21.413776 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3535 12:47:21.417199 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3536 12:47:21.423886 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3537 12:47:21.427379 iDelay=200, Bit 15, Center 127 (56 ~ 199) 144
3538 12:47:21.427473 ==
3539 12:47:21.430451 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 12:47:21.433765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 12:47:21.433856 ==
3542 12:47:21.437475 DQS Delay:
3543 12:47:21.437566 DQS0 = 0, DQS1 = 0
3544 12:47:21.437654 DQM Delay:
3545 12:47:21.440345 DQM0 = 120, DQM1 = 114
3546 12:47:21.440474 DQ Delay:
3547 12:47:21.443708 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =123
3548 12:47:21.447289 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3549 12:47:21.450766 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3550 12:47:21.457049 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =127
3551 12:47:21.457136
3552 12:47:21.457251
3553 12:47:21.457331 ==
3554 12:47:21.460533 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 12:47:21.463648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 12:47:21.463765 ==
3557 12:47:21.463851
3558 12:47:21.463931
3559 12:47:21.467484 TX Vref Scan disable
3560 12:47:21.467570 == TX Byte 0 ==
3561 12:47:21.473804 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3562 12:47:21.476942 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3563 12:47:21.477029 == TX Byte 1 ==
3564 12:47:21.483500 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3565 12:47:21.486821 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3566 12:47:21.486954 ==
3567 12:47:21.490319 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 12:47:21.493464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 12:47:21.493584 ==
3570 12:47:21.506298 TX Vref=22, minBit 1, minWin=25, winSum=419
3571 12:47:21.509391 TX Vref=24, minBit 8, minWin=25, winSum=422
3572 12:47:21.513086 TX Vref=26, minBit 3, minWin=26, winSum=429
3573 12:47:21.516510 TX Vref=28, minBit 3, minWin=26, winSum=430
3574 12:47:21.519804 TX Vref=30, minBit 8, minWin=26, winSum=428
3575 12:47:21.522997 TX Vref=32, minBit 1, minWin=26, winSum=424
3576 12:47:21.529499 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 28
3577 12:47:21.529620
3578 12:47:21.533126 Final TX Range 1 Vref 28
3579 12:47:21.533246
3580 12:47:21.533353 ==
3581 12:47:21.536292 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 12:47:21.539565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 12:47:21.539685 ==
3584 12:47:21.539792
3585 12:47:21.543072
3586 12:47:21.543206 TX Vref Scan disable
3587 12:47:21.546251 == TX Byte 0 ==
3588 12:47:21.549407 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3589 12:47:21.553211 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3590 12:47:21.556257 == TX Byte 1 ==
3591 12:47:21.559668 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3592 12:47:21.562964 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3593 12:47:21.563134
3594 12:47:21.566106 [DATLAT]
3595 12:47:21.566225 Freq=1200, CH1 RK1
3596 12:47:21.566335
3597 12:47:21.569850 DATLAT Default: 0xd
3598 12:47:21.570015 0, 0xFFFF, sum = 0
3599 12:47:21.573026 1, 0xFFFF, sum = 0
3600 12:47:21.573147 2, 0xFFFF, sum = 0
3601 12:47:21.576265 3, 0xFFFF, sum = 0
3602 12:47:21.576384 4, 0xFFFF, sum = 0
3603 12:47:21.579399 5, 0xFFFF, sum = 0
3604 12:47:21.579519 6, 0xFFFF, sum = 0
3605 12:47:21.583009 7, 0xFFFF, sum = 0
3606 12:47:21.585999 8, 0xFFFF, sum = 0
3607 12:47:21.586199 9, 0xFFFF, sum = 0
3608 12:47:21.589422 10, 0xFFFF, sum = 0
3609 12:47:21.589546 11, 0xFFFF, sum = 0
3610 12:47:21.593250 12, 0x0, sum = 1
3611 12:47:21.593371 13, 0x0, sum = 2
3612 12:47:21.595954 14, 0x0, sum = 3
3613 12:47:21.596074 15, 0x0, sum = 4
3614 12:47:21.596183 best_step = 13
3615 12:47:21.596288
3616 12:47:21.599359 ==
3617 12:47:21.602610 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 12:47:21.605857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 12:47:21.606005 ==
3620 12:47:21.606118 RX Vref Scan: 0
3621 12:47:21.606283
3622 12:47:21.609353 RX Vref 0 -> 0, step: 1
3623 12:47:21.609472
3624 12:47:21.612983 RX Delay -13 -> 252, step: 4
3625 12:47:21.615977 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3626 12:47:21.622554 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3627 12:47:21.626247 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3628 12:47:21.629085 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3629 12:47:21.632668 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3630 12:47:21.636343 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3631 12:47:21.642439 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3632 12:47:21.645954 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3633 12:47:21.649432 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3634 12:47:21.652274 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3635 12:47:21.655989 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3636 12:47:21.662581 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3637 12:47:21.665791 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3638 12:47:21.668995 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3639 12:47:21.672166 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3640 12:47:21.675580 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3641 12:47:21.679156 ==
3642 12:47:21.682094 Dram Type= 6, Freq= 0, CH_1, rank 1
3643 12:47:21.685568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3644 12:47:21.685658 ==
3645 12:47:21.685744 DQS Delay:
3646 12:47:21.689256 DQS0 = 0, DQS1 = 0
3647 12:47:21.689343 DQM Delay:
3648 12:47:21.692700 DQM0 = 119, DQM1 = 113
3649 12:47:21.692813 DQ Delay:
3650 12:47:21.695923 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3651 12:47:21.698957 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3652 12:47:21.702369 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108
3653 12:47:21.705809 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3654 12:47:21.705943
3655 12:47:21.706058
3656 12:47:21.715599 [DQSOSCAuto] RK1, (LSB)MR18= 0xaef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3657 12:47:21.715728 CH1 RK1: MR19=403, MR18=AEF
3658 12:47:21.722176 CH1_RK1: MR19=0x403, MR18=0xAEF, DQSOSC=406, MR23=63, INC=39, DEC=26
3659 12:47:21.725874 [RxdqsGatingPostProcess] freq 1200
3660 12:47:21.732135 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3661 12:47:21.735629 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 12:47:21.739056 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 12:47:21.742392 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 12:47:21.745807 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 12:47:21.748993 best DQS0 dly(2T, 0.5T) = (0, 11)
3666 12:47:21.749114 best DQS1 dly(2T, 0.5T) = (0, 11)
3667 12:47:21.752130 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3668 12:47:21.755816 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3669 12:47:21.758979 Pre-setting of DQS Precalculation
3670 12:47:21.765742 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3671 12:47:21.772328 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3672 12:47:21.779154 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3673 12:47:21.779252
3674 12:47:21.779332
3675 12:47:21.782472 [Calibration Summary] 2400 Mbps
3676 12:47:21.782571 CH 0, Rank 0
3677 12:47:21.785414 SW Impedance : PASS
3678 12:47:21.788862 DUTY Scan : NO K
3679 12:47:21.788948 ZQ Calibration : PASS
3680 12:47:21.792259 Jitter Meter : NO K
3681 12:47:21.795723 CBT Training : PASS
3682 12:47:21.795851 Write leveling : PASS
3683 12:47:21.798785 RX DQS gating : PASS
3684 12:47:21.802028 RX DQ/DQS(RDDQC) : PASS
3685 12:47:21.802112 TX DQ/DQS : PASS
3686 12:47:21.805715 RX DATLAT : PASS
3687 12:47:21.808998 RX DQ/DQS(Engine): PASS
3688 12:47:21.809114 TX OE : NO K
3689 12:47:21.812331 All Pass.
3690 12:47:21.812415
3691 12:47:21.812481 CH 0, Rank 1
3692 12:47:21.815627 SW Impedance : PASS
3693 12:47:21.815710 DUTY Scan : NO K
3694 12:47:21.818842 ZQ Calibration : PASS
3695 12:47:21.822518 Jitter Meter : NO K
3696 12:47:21.822602 CBT Training : PASS
3697 12:47:21.825440 Write leveling : PASS
3698 12:47:21.828632 RX DQS gating : PASS
3699 12:47:21.828742 RX DQ/DQS(RDDQC) : PASS
3700 12:47:21.832395 TX DQ/DQS : PASS
3701 12:47:21.832499 RX DATLAT : PASS
3702 12:47:21.835251 RX DQ/DQS(Engine): PASS
3703 12:47:21.838632 TX OE : NO K
3704 12:47:21.838770 All Pass.
3705 12:47:21.838887
3706 12:47:21.838995 CH 1, Rank 0
3707 12:47:21.841914 SW Impedance : PASS
3708 12:47:21.845389 DUTY Scan : NO K
3709 12:47:21.845514 ZQ Calibration : PASS
3710 12:47:21.849049 Jitter Meter : NO K
3711 12:47:21.852208 CBT Training : PASS
3712 12:47:21.852331 Write leveling : PASS
3713 12:47:21.855227 RX DQS gating : PASS
3714 12:47:21.858834 RX DQ/DQS(RDDQC) : PASS
3715 12:47:21.858941 TX DQ/DQS : PASS
3716 12:47:21.861985 RX DATLAT : PASS
3717 12:47:21.865174 RX DQ/DQS(Engine): PASS
3718 12:47:21.865274 TX OE : NO K
3719 12:47:21.868860 All Pass.
3720 12:47:21.868945
3721 12:47:21.869012 CH 1, Rank 1
3722 12:47:21.871986 SW Impedance : PASS
3723 12:47:21.872072 DUTY Scan : NO K
3724 12:47:21.875657 ZQ Calibration : PASS
3725 12:47:21.878665 Jitter Meter : NO K
3726 12:47:21.878761 CBT Training : PASS
3727 12:47:21.882322 Write leveling : PASS
3728 12:47:21.882407 RX DQS gating : PASS
3729 12:47:21.885551 RX DQ/DQS(RDDQC) : PASS
3730 12:47:21.888741 TX DQ/DQS : PASS
3731 12:47:21.888856 RX DATLAT : PASS
3732 12:47:21.891850 RX DQ/DQS(Engine): PASS
3733 12:47:21.895279 TX OE : NO K
3734 12:47:21.895380 All Pass.
3735 12:47:21.895480
3736 12:47:21.898518 DramC Write-DBI off
3737 12:47:21.898607 PER_BANK_REFRESH: Hybrid Mode
3738 12:47:21.901741 TX_TRACKING: ON
3739 12:47:21.911882 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3740 12:47:21.915433 [FAST_K] Save calibration result to emmc
3741 12:47:21.918399 dramc_set_vcore_voltage set vcore to 650000
3742 12:47:21.918482 Read voltage for 600, 5
3743 12:47:21.922076 Vio18 = 0
3744 12:47:21.922177 Vcore = 650000
3745 12:47:21.922243 Vdram = 0
3746 12:47:21.925056 Vddq = 0
3747 12:47:21.925138 Vmddr = 0
3748 12:47:21.928486 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3749 12:47:21.935051 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3750 12:47:21.938286 MEM_TYPE=3, freq_sel=19
3751 12:47:21.941934 sv_algorithm_assistance_LP4_1600
3752 12:47:21.944951 ============ PULL DRAM RESETB DOWN ============
3753 12:47:21.948384 ========== PULL DRAM RESETB DOWN end =========
3754 12:47:21.954970 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3755 12:47:21.958230 ===================================
3756 12:47:21.958346 LPDDR4 DRAM CONFIGURATION
3757 12:47:21.961443 ===================================
3758 12:47:21.965241 EX_ROW_EN[0] = 0x0
3759 12:47:21.965358 EX_ROW_EN[1] = 0x0
3760 12:47:21.968358 LP4Y_EN = 0x0
3761 12:47:21.968476 WORK_FSP = 0x0
3762 12:47:21.971392 WL = 0x2
3763 12:47:21.974626 RL = 0x2
3764 12:47:21.974744 BL = 0x2
3765 12:47:21.978135 RPST = 0x0
3766 12:47:21.978254 RD_PRE = 0x0
3767 12:47:21.981541 WR_PRE = 0x1
3768 12:47:21.981656 WR_PST = 0x0
3769 12:47:21.984681 DBI_WR = 0x0
3770 12:47:21.984845 DBI_RD = 0x0
3771 12:47:21.988132 OTF = 0x1
3772 12:47:21.991275 ===================================
3773 12:47:21.994981 ===================================
3774 12:47:21.995067 ANA top config
3775 12:47:21.998062 ===================================
3776 12:47:22.001488 DLL_ASYNC_EN = 0
3777 12:47:22.004869 ALL_SLAVE_EN = 1
3778 12:47:22.004965 NEW_RANK_MODE = 1
3779 12:47:22.008180 DLL_IDLE_MODE = 1
3780 12:47:22.011483 LP45_APHY_COMB_EN = 1
3781 12:47:22.014483 TX_ODT_DIS = 1
3782 12:47:22.017968 NEW_8X_MODE = 1
3783 12:47:22.021290 ===================================
3784 12:47:22.021375 ===================================
3785 12:47:22.024724 data_rate = 1200
3786 12:47:22.027910 CKR = 1
3787 12:47:22.031344 DQ_P2S_RATIO = 8
3788 12:47:22.034510 ===================================
3789 12:47:22.037770 CA_P2S_RATIO = 8
3790 12:47:22.041277 DQ_CA_OPEN = 0
3791 12:47:22.044683 DQ_SEMI_OPEN = 0
3792 12:47:22.044774 CA_SEMI_OPEN = 0
3793 12:47:22.047969 CA_FULL_RATE = 0
3794 12:47:22.051439 DQ_CKDIV4_EN = 1
3795 12:47:22.054599 CA_CKDIV4_EN = 1
3796 12:47:22.057767 CA_PREDIV_EN = 0
3797 12:47:22.061543 PH8_DLY = 0
3798 12:47:22.061643 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3799 12:47:22.064517 DQ_AAMCK_DIV = 4
3800 12:47:22.067714 CA_AAMCK_DIV = 4
3801 12:47:22.071078 CA_ADMCK_DIV = 4
3802 12:47:22.074140 DQ_TRACK_CA_EN = 0
3803 12:47:22.077828 CA_PICK = 600
3804 12:47:22.077930 CA_MCKIO = 600
3805 12:47:22.081120 MCKIO_SEMI = 0
3806 12:47:22.084384 PLL_FREQ = 2288
3807 12:47:22.087747 DQ_UI_PI_RATIO = 32
3808 12:47:22.090763 CA_UI_PI_RATIO = 0
3809 12:47:22.094327 ===================================
3810 12:47:22.097529 ===================================
3811 12:47:22.100741 memory_type:LPDDR4
3812 12:47:22.100870 GP_NUM : 10
3813 12:47:22.104178 SRAM_EN : 1
3814 12:47:22.104309 MD32_EN : 0
3815 12:47:22.107394 ===================================
3816 12:47:22.110649 [ANA_INIT] >>>>>>>>>>>>>>
3817 12:47:22.114396 <<<<<< [CONFIGURE PHASE]: ANA_TX
3818 12:47:22.117412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3819 12:47:22.120983 ===================================
3820 12:47:22.124034 data_rate = 1200,PCW = 0X5800
3821 12:47:22.127148 ===================================
3822 12:47:22.130658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3823 12:47:22.137367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3824 12:47:22.140564 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3825 12:47:22.147335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3826 12:47:22.150865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3827 12:47:22.154291 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3828 12:47:22.154377 [ANA_INIT] flow start
3829 12:47:22.157096 [ANA_INIT] PLL >>>>>>>>
3830 12:47:22.160842 [ANA_INIT] PLL <<<<<<<<
3831 12:47:22.160925 [ANA_INIT] MIDPI >>>>>>>>
3832 12:47:22.163987 [ANA_INIT] MIDPI <<<<<<<<
3833 12:47:22.167096 [ANA_INIT] DLL >>>>>>>>
3834 12:47:22.167178 [ANA_INIT] flow end
3835 12:47:22.173949 ============ LP4 DIFF to SE enter ============
3836 12:47:22.177321 ============ LP4 DIFF to SE exit ============
3837 12:47:22.177431 [ANA_INIT] <<<<<<<<<<<<<
3838 12:47:22.180525 [Flow] Enable top DCM control >>>>>
3839 12:47:22.183733 [Flow] Enable top DCM control <<<<<
3840 12:47:22.187636 Enable DLL master slave shuffle
3841 12:47:22.193950 ==============================================================
3842 12:47:22.197487 Gating Mode config
3843 12:47:22.200482 ==============================================================
3844 12:47:22.203941 Config description:
3845 12:47:22.214224 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3846 12:47:22.220407 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3847 12:47:22.224104 SELPH_MODE 0: By rank 1: By Phase
3848 12:47:22.230823 ==============================================================
3849 12:47:22.233684 GAT_TRACK_EN = 1
3850 12:47:22.237151 RX_GATING_MODE = 2
3851 12:47:22.237257 RX_GATING_TRACK_MODE = 2
3852 12:47:22.240316 SELPH_MODE = 1
3853 12:47:22.243665 PICG_EARLY_EN = 1
3854 12:47:22.246997 VALID_LAT_VALUE = 1
3855 12:47:22.253687 ==============================================================
3856 12:47:22.257034 Enter into Gating configuration >>>>
3857 12:47:22.260264 Exit from Gating configuration <<<<
3858 12:47:22.263800 Enter into DVFS_PRE_config >>>>>
3859 12:47:22.274271 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3860 12:47:22.277305 Exit from DVFS_PRE_config <<<<<
3861 12:47:22.280553 Enter into PICG configuration >>>>
3862 12:47:22.284118 Exit from PICG configuration <<<<
3863 12:47:22.287321 [RX_INPUT] configuration >>>>>
3864 12:47:22.290414 [RX_INPUT] configuration <<<<<
3865 12:47:22.293847 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3866 12:47:22.300380 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3867 12:47:22.307077 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 12:47:22.313874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 12:47:22.317137 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3870 12:47:22.323785 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3871 12:47:22.327016 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3872 12:47:22.334012 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3873 12:47:22.337217 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3874 12:47:22.340269 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3875 12:47:22.343468 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3876 12:47:22.350170 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3877 12:47:22.353598 ===================================
3878 12:47:22.353729 LPDDR4 DRAM CONFIGURATION
3879 12:47:22.357094 ===================================
3880 12:47:22.360519 EX_ROW_EN[0] = 0x0
3881 12:47:22.363605 EX_ROW_EN[1] = 0x0
3882 12:47:22.363745 LP4Y_EN = 0x0
3883 12:47:22.366955 WORK_FSP = 0x0
3884 12:47:22.367093 WL = 0x2
3885 12:47:22.370234 RL = 0x2
3886 12:47:22.370362 BL = 0x2
3887 12:47:22.373534 RPST = 0x0
3888 12:47:22.373666 RD_PRE = 0x0
3889 12:47:22.376982 WR_PRE = 0x1
3890 12:47:22.377114 WR_PST = 0x0
3891 12:47:22.380296 DBI_WR = 0x0
3892 12:47:22.380434 DBI_RD = 0x0
3893 12:47:22.383725 OTF = 0x1
3894 12:47:22.386700 ===================================
3895 12:47:22.390446 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3896 12:47:22.393716 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3897 12:47:22.400267 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 12:47:22.403249 ===================================
3899 12:47:22.403366 LPDDR4 DRAM CONFIGURATION
3900 12:47:22.406740 ===================================
3901 12:47:22.410044 EX_ROW_EN[0] = 0x10
3902 12:47:22.410121 EX_ROW_EN[1] = 0x0
3903 12:47:22.413755 LP4Y_EN = 0x0
3904 12:47:22.416924 WORK_FSP = 0x0
3905 12:47:22.417014 WL = 0x2
3906 12:47:22.420028 RL = 0x2
3907 12:47:22.420113 BL = 0x2
3908 12:47:22.423359 RPST = 0x0
3909 12:47:22.423445 RD_PRE = 0x0
3910 12:47:22.426946 WR_PRE = 0x1
3911 12:47:22.427032 WR_PST = 0x0
3912 12:47:22.430629 DBI_WR = 0x0
3913 12:47:22.430714 DBI_RD = 0x0
3914 12:47:22.433366 OTF = 0x1
3915 12:47:22.436771 ===================================
3916 12:47:22.443353 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3917 12:47:22.446624 nWR fixed to 30
3918 12:47:22.446710 [ModeRegInit_LP4] CH0 RK0
3919 12:47:22.450079 [ModeRegInit_LP4] CH0 RK1
3920 12:47:22.452998 [ModeRegInit_LP4] CH1 RK0
3921 12:47:22.456381 [ModeRegInit_LP4] CH1 RK1
3922 12:47:22.456466 match AC timing 17
3923 12:47:22.459642 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3924 12:47:22.466488 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3925 12:47:22.469909 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3926 12:47:22.473379 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3927 12:47:22.480296 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3928 12:47:22.480382 ==
3929 12:47:22.483467 Dram Type= 6, Freq= 0, CH_0, rank 0
3930 12:47:22.486885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 12:47:22.486973 ==
3932 12:47:22.493026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 12:47:22.496791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3934 12:47:22.501023 [CA 0] Center 36 (5~67) winsize 63
3935 12:47:22.504105 [CA 1] Center 36 (6~67) winsize 62
3936 12:47:22.507755 [CA 2] Center 34 (4~65) winsize 62
3937 12:47:22.510817 [CA 3] Center 34 (3~65) winsize 63
3938 12:47:22.514234 [CA 4] Center 33 (3~64) winsize 62
3939 12:47:22.517874 [CA 5] Center 33 (3~64) winsize 62
3940 12:47:22.517959
3941 12:47:22.521158 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3942 12:47:22.521286
3943 12:47:22.524019 [CATrainingPosCal] consider 1 rank data
3944 12:47:22.527523 u2DelayCellTimex100 = 270/100 ps
3945 12:47:22.530991 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3946 12:47:22.537463 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3947 12:47:22.540761 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 12:47:22.544409 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3949 12:47:22.547718 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 12:47:22.550930 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3951 12:47:22.551052
3952 12:47:22.553974 CA PerBit enable=1, Macro0, CA PI delay=33
3953 12:47:22.554100
3954 12:47:22.557558 [CBTSetCACLKResult] CA Dly = 33
3955 12:47:22.557684 CS Dly: 5 (0~36)
3956 12:47:22.560894 ==
3957 12:47:22.563952 Dram Type= 6, Freq= 0, CH_0, rank 1
3958 12:47:22.567421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 12:47:22.567547 ==
3960 12:47:22.570734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3961 12:47:22.577259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3962 12:47:22.581379 [CA 0] Center 36 (6~67) winsize 62
3963 12:47:22.584408 [CA 1] Center 36 (6~67) winsize 62
3964 12:47:22.587609 [CA 2] Center 35 (4~66) winsize 63
3965 12:47:22.591279 [CA 3] Center 34 (4~65) winsize 62
3966 12:47:22.594960 [CA 4] Center 34 (3~65) winsize 63
3967 12:47:22.597953 [CA 5] Center 34 (3~65) winsize 63
3968 12:47:22.598073
3969 12:47:22.601153 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3970 12:47:22.601276
3971 12:47:22.604458 [CATrainingPosCal] consider 2 rank data
3972 12:47:22.607610 u2DelayCellTimex100 = 270/100 ps
3973 12:47:22.611166 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3974 12:47:22.617858 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3975 12:47:22.621117 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 12:47:22.624587 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3977 12:47:22.627760 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 12:47:22.631013 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 12:47:22.631137
3980 12:47:22.634199 CA PerBit enable=1, Macro0, CA PI delay=33
3981 12:47:22.634325
3982 12:47:22.637683 [CBTSetCACLKResult] CA Dly = 33
3983 12:47:22.637804 CS Dly: 5 (0~37)
3984 12:47:22.641178
3985 12:47:22.644442 ----->DramcWriteLeveling(PI) begin...
3986 12:47:22.644569 ==
3987 12:47:22.647941 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 12:47:22.650788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 12:47:22.650911 ==
3990 12:47:22.654344 Write leveling (Byte 0): 33 => 33
3991 12:47:22.657739 Write leveling (Byte 1): 29 => 29
3992 12:47:22.661032 DramcWriteLeveling(PI) end<-----
3993 12:47:22.661150
3994 12:47:22.661264 ==
3995 12:47:22.664375 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 12:47:22.667530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 12:47:22.667652 ==
3998 12:47:22.671135 [Gating] SW mode calibration
3999 12:47:22.677270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4000 12:47:22.684264 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4001 12:47:22.687420 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 12:47:22.690568 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 12:47:22.697552 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 12:47:22.700472 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
4005 12:47:22.703838 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
4006 12:47:22.707342 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 12:47:22.713839 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 12:47:22.717280 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 12:47:22.720572 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 12:47:22.727356 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 12:47:22.730390 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
4012 12:47:22.733938 0 10 12 | B1->B0 | 2929 4343 | 0 0 | (0 0) (0 0)
4013 12:47:22.740573 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4014 12:47:22.743633 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 12:47:22.747147 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 12:47:22.753757 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 12:47:22.757257 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 12:47:22.760098 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 12:47:22.766885 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4020 12:47:22.770274 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4021 12:47:22.773773 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4022 12:47:22.780341 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 12:47:22.783477 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 12:47:22.786861 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 12:47:22.793779 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 12:47:22.797149 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 12:47:22.800175 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 12:47:22.806825 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 12:47:22.810156 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 12:47:22.813490 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 12:47:22.820274 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 12:47:22.823523 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 12:47:22.826849 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 12:47:22.830396 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 12:47:22.837216 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 12:47:22.840241 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4037 12:47:22.843647 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 12:47:22.846787 Total UI for P1: 0, mck2ui 16
4039 12:47:22.850139 best dqsien dly found for B0: ( 0, 13, 12)
4040 12:47:22.853510 Total UI for P1: 0, mck2ui 16
4041 12:47:22.856689 best dqsien dly found for B1: ( 0, 13, 14)
4042 12:47:22.860297 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4043 12:47:22.866636 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4044 12:47:22.866772
4045 12:47:22.870081 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4046 12:47:22.873292 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4047 12:47:22.876994 [Gating] SW calibration Done
4048 12:47:22.877111 ==
4049 12:47:22.879792 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 12:47:22.883544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 12:47:22.883665 ==
4052 12:47:22.886824 RX Vref Scan: 0
4053 12:47:22.886914
4054 12:47:22.886980 RX Vref 0 -> 0, step: 1
4055 12:47:22.887042
4056 12:47:22.890259 RX Delay -230 -> 252, step: 16
4057 12:47:22.893209 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4058 12:47:22.899911 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4059 12:47:22.903227 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4060 12:47:22.907019 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4061 12:47:22.909994 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4062 12:47:22.913480 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4063 12:47:22.919682 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4064 12:47:22.923458 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4065 12:47:22.926316 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4066 12:47:22.930073 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4067 12:47:22.936546 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4068 12:47:22.939621 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4069 12:47:22.943335 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4070 12:47:22.946280 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4071 12:47:22.953043 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4072 12:47:22.956595 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4073 12:47:22.956715 ==
4074 12:47:22.959646 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 12:47:22.963355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 12:47:22.963441 ==
4077 12:47:22.966207 DQS Delay:
4078 12:47:22.966293 DQS0 = 0, DQS1 = 0
4079 12:47:22.966359 DQM Delay:
4080 12:47:22.969495 DQM0 = 51, DQM1 = 40
4081 12:47:22.969580 DQ Delay:
4082 12:47:22.973186 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4083 12:47:22.976339 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4084 12:47:22.979493 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4085 12:47:22.983060 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4086 12:47:22.983145
4087 12:47:22.983213
4088 12:47:22.983276 ==
4089 12:47:22.986577 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 12:47:22.993111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 12:47:22.993198 ==
4092 12:47:22.993265
4093 12:47:22.993327
4094 12:47:22.993387 TX Vref Scan disable
4095 12:47:22.996312 == TX Byte 0 ==
4096 12:47:23.000203 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4097 12:47:23.006842 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4098 12:47:23.006974 == TX Byte 1 ==
4099 12:47:23.009971 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4100 12:47:23.016379 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4101 12:47:23.016467 ==
4102 12:47:23.019714 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 12:47:23.022778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 12:47:23.022890 ==
4105 12:47:23.022994
4106 12:47:23.023088
4107 12:47:23.026206 TX Vref Scan disable
4108 12:47:23.029943 == TX Byte 0 ==
4109 12:47:23.032837 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4110 12:47:23.036571 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4111 12:47:23.039360 == TX Byte 1 ==
4112 12:47:23.042870 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4113 12:47:23.046316 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4114 12:47:23.046408
4115 12:47:23.046476 [DATLAT]
4116 12:47:23.049661 Freq=600, CH0 RK0
4117 12:47:23.049748
4118 12:47:23.049821 DATLAT Default: 0x9
4119 12:47:23.052727 0, 0xFFFF, sum = 0
4120 12:47:23.056492 1, 0xFFFF, sum = 0
4121 12:47:23.056595 2, 0xFFFF, sum = 0
4122 12:47:23.059677 3, 0xFFFF, sum = 0
4123 12:47:23.059778 4, 0xFFFF, sum = 0
4124 12:47:23.062945 5, 0xFFFF, sum = 0
4125 12:47:23.063046 6, 0xFFFF, sum = 0
4126 12:47:23.066057 7, 0xFFFF, sum = 0
4127 12:47:23.066157 8, 0x0, sum = 1
4128 12:47:23.069535 9, 0x0, sum = 2
4129 12:47:23.069656 10, 0x0, sum = 3
4130 12:47:23.069729 11, 0x0, sum = 4
4131 12:47:23.072811 best_step = 9
4132 12:47:23.072904
4133 12:47:23.072979 ==
4134 12:47:23.076058 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 12:47:23.079163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 12:47:23.079315 ==
4137 12:47:23.082579 RX Vref Scan: 1
4138 12:47:23.082718
4139 12:47:23.082840 RX Vref 0 -> 0, step: 1
4140 12:47:23.085839
4141 12:47:23.085963 RX Delay -179 -> 252, step: 8
4142 12:47:23.086079
4143 12:47:23.089283 Set Vref, RX VrefLevel [Byte0]: 58
4144 12:47:23.092457 [Byte1]: 48
4145 12:47:23.096960
4146 12:47:23.097137 Final RX Vref Byte 0 = 58 to rank0
4147 12:47:23.100484 Final RX Vref Byte 1 = 48 to rank0
4148 12:47:23.103554 Final RX Vref Byte 0 = 58 to rank1
4149 12:47:23.106754 Final RX Vref Byte 1 = 48 to rank1==
4150 12:47:23.110376 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 12:47:23.116898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 12:47:23.117044 ==
4153 12:47:23.117114 DQS Delay:
4154 12:47:23.117177 DQS0 = 0, DQS1 = 0
4155 12:47:23.120265 DQM Delay:
4156 12:47:23.120360 DQM0 = 49, DQM1 = 39
4157 12:47:23.123585 DQ Delay:
4158 12:47:23.126880 DQ0 =44, DQ1 =52, DQ2 =44, DQ3 =44
4159 12:47:23.126989 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4160 12:47:23.130285 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4161 12:47:23.137088 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4162 12:47:23.137222
4163 12:47:23.137293
4164 12:47:23.143596 [DQSOSCAuto] RK0, (LSB)MR18= 0x5954, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4165 12:47:23.146985 CH0 RK0: MR19=808, MR18=5954
4166 12:47:23.153261 CH0_RK0: MR19=0x808, MR18=0x5954, DQSOSC=393, MR23=63, INC=169, DEC=113
4167 12:47:23.153398
4168 12:47:23.156672 ----->DramcWriteLeveling(PI) begin...
4169 12:47:23.156789 ==
4170 12:47:23.160002 Dram Type= 6, Freq= 0, CH_0, rank 1
4171 12:47:23.163339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 12:47:23.163488 ==
4173 12:47:23.166760 Write leveling (Byte 0): 33 => 33
4174 12:47:23.170059 Write leveling (Byte 1): 31 => 31
4175 12:47:23.173401 DramcWriteLeveling(PI) end<-----
4176 12:47:23.173544
4177 12:47:23.173650 ==
4178 12:47:23.176536 Dram Type= 6, Freq= 0, CH_0, rank 1
4179 12:47:23.179732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 12:47:23.179868 ==
4181 12:47:23.183556 [Gating] SW mode calibration
4182 12:47:23.189937 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4183 12:47:23.196670 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4184 12:47:23.199807 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 12:47:23.203376 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 12:47:23.209862 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4187 12:47:23.213299 0 9 12 | B1->B0 | 3232 3131 | 0 0 | (0 1) (0 1)
4188 12:47:23.216488 0 9 16 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
4189 12:47:23.223460 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 12:47:23.226518 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 12:47:23.230057 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 12:47:23.236295 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 12:47:23.240080 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 12:47:23.243241 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 12:47:23.250018 0 10 12 | B1->B0 | 3131 2a29 | 0 1 | (0 0) (0 0)
4196 12:47:23.253093 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4197 12:47:23.256677 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 12:47:23.262980 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 12:47:23.266654 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 12:47:23.269861 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 12:47:23.276364 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 12:47:23.279876 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 12:47:23.282957 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4204 12:47:23.289716 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 12:47:23.292988 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 12:47:23.295827 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 12:47:23.302600 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 12:47:23.306171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 12:47:23.309445 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 12:47:23.316313 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 12:47:23.319266 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 12:47:23.322750 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 12:47:23.329078 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 12:47:23.332502 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 12:47:23.336132 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 12:47:23.342592 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 12:47:23.346127 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 12:47:23.349350 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 12:47:23.355812 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4220 12:47:23.359345 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 12:47:23.362773 Total UI for P1: 0, mck2ui 16
4222 12:47:23.365982 best dqsien dly found for B0: ( 0, 13, 12)
4223 12:47:23.369455 Total UI for P1: 0, mck2ui 16
4224 12:47:23.372578 best dqsien dly found for B1: ( 0, 13, 12)
4225 12:47:23.376122 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4226 12:47:23.379062 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4227 12:47:23.379148
4228 12:47:23.382492 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4229 12:47:23.385772 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4230 12:47:23.389002 [Gating] SW calibration Done
4231 12:47:23.389095 ==
4232 12:47:23.392510 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 12:47:23.395661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 12:47:23.395750 ==
4235 12:47:23.398981 RX Vref Scan: 0
4236 12:47:23.399067
4237 12:47:23.402365 RX Vref 0 -> 0, step: 1
4238 12:47:23.402500
4239 12:47:23.402618 RX Delay -230 -> 252, step: 16
4240 12:47:23.409010 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4241 12:47:23.412316 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4242 12:47:23.416013 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4243 12:47:23.419055 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4244 12:47:23.425866 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4245 12:47:23.429512 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4246 12:47:23.432304 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4247 12:47:23.435757 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4248 12:47:23.438830 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4249 12:47:23.445818 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4250 12:47:23.449239 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4251 12:47:23.452511 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4252 12:47:23.455655 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4253 12:47:23.462190 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4254 12:47:23.465743 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4255 12:47:23.469257 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4256 12:47:23.469403 ==
4257 12:47:23.472212 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 12:47:23.475548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 12:47:23.475678 ==
4260 12:47:23.479190 DQS Delay:
4261 12:47:23.479329 DQS0 = 0, DQS1 = 0
4262 12:47:23.482337 DQM Delay:
4263 12:47:23.482471 DQM0 = 49, DQM1 = 42
4264 12:47:23.482586 DQ Delay:
4265 12:47:23.485613 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4266 12:47:23.489295 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4267 12:47:23.492178 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4268 12:47:23.495629 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4269 12:47:23.495736
4270 12:47:23.495808
4271 12:47:23.498900 ==
4272 12:47:23.502234 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 12:47:23.505516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 12:47:23.505673 ==
4275 12:47:23.505791
4276 12:47:23.505902
4277 12:47:23.509161 TX Vref Scan disable
4278 12:47:23.509284 == TX Byte 0 ==
4279 12:47:23.515485 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4280 12:47:23.518934 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4281 12:47:23.519069 == TX Byte 1 ==
4282 12:47:23.525336 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4283 12:47:23.528863 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4284 12:47:23.529014 ==
4285 12:47:23.532160 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 12:47:23.535626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 12:47:23.535774 ==
4288 12:47:23.535892
4289 12:47:23.536006
4290 12:47:23.539195 TX Vref Scan disable
4291 12:47:23.542390 == TX Byte 0 ==
4292 12:47:23.545605 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4293 12:47:23.549191 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4294 12:47:23.552411 == TX Byte 1 ==
4295 12:47:23.555581 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4296 12:47:23.559202 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4297 12:47:23.559315
4298 12:47:23.562245 [DATLAT]
4299 12:47:23.562342 Freq=600, CH0 RK1
4300 12:47:23.562411
4301 12:47:23.566034 DATLAT Default: 0x9
4302 12:47:23.566132 0, 0xFFFF, sum = 0
4303 12:47:23.569038 1, 0xFFFF, sum = 0
4304 12:47:23.569190 2, 0xFFFF, sum = 0
4305 12:47:23.572126 3, 0xFFFF, sum = 0
4306 12:47:23.572266 4, 0xFFFF, sum = 0
4307 12:47:23.575506 5, 0xFFFF, sum = 0
4308 12:47:23.575642 6, 0xFFFF, sum = 0
4309 12:47:23.578796 7, 0xFFFF, sum = 0
4310 12:47:23.578944 8, 0x0, sum = 1
4311 12:47:23.582174 9, 0x0, sum = 2
4312 12:47:23.582326 10, 0x0, sum = 3
4313 12:47:23.585567 11, 0x0, sum = 4
4314 12:47:23.585671 best_step = 9
4315 12:47:23.585738
4316 12:47:23.585799 ==
4317 12:47:23.588763 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 12:47:23.592286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 12:47:23.595295 ==
4320 12:47:23.595433 RX Vref Scan: 0
4321 12:47:23.595538
4322 12:47:23.598890 RX Vref 0 -> 0, step: 1
4323 12:47:23.598993
4324 12:47:23.601799 RX Delay -179 -> 252, step: 8
4325 12:47:23.605384 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4326 12:47:23.608503 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4327 12:47:23.615218 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4328 12:47:23.618537 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4329 12:47:23.621783 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4330 12:47:23.625230 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4331 12:47:23.628460 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4332 12:47:23.634918 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4333 12:47:23.638574 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4334 12:47:23.641753 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4335 12:47:23.644779 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4336 12:47:23.651958 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4337 12:47:23.654931 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4338 12:47:23.658412 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4339 12:47:23.661654 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4340 12:47:23.664766 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4341 12:47:23.664924 ==
4342 12:47:23.668303 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 12:47:23.674845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 12:47:23.675024 ==
4345 12:47:23.675142 DQS Delay:
4346 12:47:23.678394 DQS0 = 0, DQS1 = 0
4347 12:47:23.678527 DQM Delay:
4348 12:47:23.681369 DQM0 = 48, DQM1 = 40
4349 12:47:23.681501 DQ Delay:
4350 12:47:23.684925 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4351 12:47:23.688184 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4352 12:47:23.691453 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4353 12:47:23.694838 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =44
4354 12:47:23.694985
4355 12:47:23.695102
4356 12:47:23.701497 [DQSOSCAuto] RK1, (LSB)MR18= 0x622f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4357 12:47:23.704633 CH0 RK1: MR19=808, MR18=622F
4358 12:47:23.711421 CH0_RK1: MR19=0x808, MR18=0x622F, DQSOSC=391, MR23=63, INC=171, DEC=114
4359 12:47:23.714642 [RxdqsGatingPostProcess] freq 600
4360 12:47:23.717939 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4361 12:47:23.721303 Pre-setting of DQS Precalculation
4362 12:47:23.727965 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4363 12:47:23.728061 ==
4364 12:47:23.731319 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 12:47:23.734872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 12:47:23.734964 ==
4367 12:47:23.741140 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4368 12:47:23.747692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4369 12:47:23.751249 [CA 0] Center 35 (5~66) winsize 62
4370 12:47:23.754407 [CA 1] Center 35 (5~66) winsize 62
4371 12:47:23.757759 [CA 2] Center 34 (4~65) winsize 62
4372 12:47:23.761250 [CA 3] Center 33 (3~64) winsize 62
4373 12:47:23.764274 [CA 4] Center 34 (3~65) winsize 63
4374 12:47:23.767715 [CA 5] Center 33 (3~64) winsize 62
4375 12:47:23.767800
4376 12:47:23.771179 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4377 12:47:23.771264
4378 12:47:23.774437 [CATrainingPosCal] consider 1 rank data
4379 12:47:23.777806 u2DelayCellTimex100 = 270/100 ps
4380 12:47:23.781545 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4381 12:47:23.784703 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4382 12:47:23.787812 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 12:47:23.790980 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4384 12:47:23.794992 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4385 12:47:23.797765 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4386 12:47:23.797860
4387 12:47:23.804248 CA PerBit enable=1, Macro0, CA PI delay=33
4388 12:47:23.804349
4389 12:47:23.804421 [CBTSetCACLKResult] CA Dly = 33
4390 12:47:23.807795 CS Dly: 5 (0~36)
4391 12:47:23.807882 ==
4392 12:47:23.810803 Dram Type= 6, Freq= 0, CH_1, rank 1
4393 12:47:23.814410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 12:47:23.814502 ==
4395 12:47:23.821217 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4396 12:47:23.827836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4397 12:47:23.830913 [CA 0] Center 35 (5~66) winsize 62
4398 12:47:23.834477 [CA 1] Center 35 (5~66) winsize 62
4399 12:47:23.837653 [CA 2] Center 34 (4~65) winsize 62
4400 12:47:23.841046 [CA 3] Center 34 (4~64) winsize 61
4401 12:47:23.844309 [CA 4] Center 34 (4~64) winsize 61
4402 12:47:23.847623 [CA 5] Center 34 (4~64) winsize 61
4403 12:47:23.847747
4404 12:47:23.850769 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4405 12:47:23.850896
4406 12:47:23.854398 [CATrainingPosCal] consider 2 rank data
4407 12:47:23.857255 u2DelayCellTimex100 = 270/100 ps
4408 12:47:23.861049 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4409 12:47:23.863836 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4410 12:47:23.867512 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4411 12:47:23.870708 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4412 12:47:23.874338 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4413 12:47:23.877207 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4414 12:47:23.877314
4415 12:47:23.884277 CA PerBit enable=1, Macro0, CA PI delay=34
4416 12:47:23.884368
4417 12:47:23.884440 [CBTSetCACLKResult] CA Dly = 34
4418 12:47:23.887329 CS Dly: 5 (0~37)
4419 12:47:23.887415
4420 12:47:23.890690 ----->DramcWriteLeveling(PI) begin...
4421 12:47:23.890834 ==
4422 12:47:23.894367 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 12:47:23.897139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 12:47:23.897231 ==
4425 12:47:23.900430 Write leveling (Byte 0): 28 => 28
4426 12:47:23.903930 Write leveling (Byte 1): 32 => 32
4427 12:47:23.907142 DramcWriteLeveling(PI) end<-----
4428 12:47:23.907231
4429 12:47:23.907300 ==
4430 12:47:23.910425 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 12:47:23.917893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 12:47:23.918006 ==
4433 12:47:23.918076 [Gating] SW mode calibration
4434 12:47:23.927008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4435 12:47:23.930560 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4436 12:47:23.933941 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 12:47:23.940589 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 12:47:23.943523 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
4439 12:47:23.947107 0 9 12 | B1->B0 | 2c2c 2a2a | 1 0 | (1 0) (1 1)
4440 12:47:23.953560 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 12:47:23.957231 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 12:47:23.960172 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 12:47:23.967122 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 12:47:23.970447 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 12:47:23.973705 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 12:47:23.980564 0 10 8 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
4447 12:47:23.983742 0 10 12 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
4448 12:47:23.986851 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 12:47:23.993540 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 12:47:23.996993 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 12:47:24.000255 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 12:47:24.006460 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 12:47:24.010352 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 12:47:24.013219 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 12:47:24.020111 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4456 12:47:24.023635 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:47:24.026457 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 12:47:24.033539 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 12:47:24.036606 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 12:47:24.039815 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 12:47:24.046658 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 12:47:24.049818 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 12:47:24.053271 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 12:47:24.056924 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 12:47:24.063382 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 12:47:24.066574 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 12:47:24.069869 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 12:47:24.076481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 12:47:24.079913 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 12:47:24.083319 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 12:47:24.089651 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 12:47:24.093106 Total UI for P1: 0, mck2ui 16
4473 12:47:24.096398 best dqsien dly found for B0: ( 0, 13, 10)
4474 12:47:24.100015 Total UI for P1: 0, mck2ui 16
4475 12:47:24.102955 best dqsien dly found for B1: ( 0, 13, 10)
4476 12:47:24.106439 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4477 12:47:24.109585 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4478 12:47:24.109716
4479 12:47:24.112927 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4480 12:47:24.116515 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4481 12:47:24.119778 [Gating] SW calibration Done
4482 12:47:24.119876 ==
4483 12:47:24.123351 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 12:47:24.126266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 12:47:24.126357 ==
4486 12:47:24.129712 RX Vref Scan: 0
4487 12:47:24.129800
4488 12:47:24.129869 RX Vref 0 -> 0, step: 1
4489 12:47:24.132981
4490 12:47:24.133072 RX Delay -230 -> 252, step: 16
4491 12:47:24.139758 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4492 12:47:24.142900 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4493 12:47:24.146367 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4494 12:47:24.149735 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4495 12:47:24.153075 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4496 12:47:24.159787 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4497 12:47:24.162840 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4498 12:47:24.166292 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4499 12:47:24.169391 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4500 12:47:24.176090 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4501 12:47:24.179397 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4502 12:47:24.182937 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4503 12:47:24.186285 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4504 12:47:24.192670 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4505 12:47:24.195990 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4506 12:47:24.199655 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4507 12:47:24.199794 ==
4508 12:47:24.203035 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 12:47:24.206300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 12:47:24.206441 ==
4511 12:47:24.209856 DQS Delay:
4512 12:47:24.209974 DQS0 = 0, DQS1 = 0
4513 12:47:24.213285 DQM Delay:
4514 12:47:24.213384 DQM0 = 50, DQM1 = 42
4515 12:47:24.213473 DQ Delay:
4516 12:47:24.216392 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4517 12:47:24.219408 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4518 12:47:24.222910 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4519 12:47:24.226446 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4520 12:47:24.226559
4521 12:47:24.226650
4522 12:47:24.229589 ==
4523 12:47:24.229684 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 12:47:24.236119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 12:47:24.236234 ==
4526 12:47:24.236326
4527 12:47:24.236409
4528 12:47:24.239239 TX Vref Scan disable
4529 12:47:24.239354 == TX Byte 0 ==
4530 12:47:24.242676 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4531 12:47:24.249688 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4532 12:47:24.249878 == TX Byte 1 ==
4533 12:47:24.255906 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4534 12:47:24.259526 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4535 12:47:24.259693 ==
4536 12:47:24.262809 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 12:47:24.265790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 12:47:24.265956 ==
4539 12:47:24.266095
4540 12:47:24.266231
4541 12:47:24.269027 TX Vref Scan disable
4542 12:47:24.272602 == TX Byte 0 ==
4543 12:47:24.275826 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4544 12:47:24.279408 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4545 12:47:24.282557 == TX Byte 1 ==
4546 12:47:24.286153 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4547 12:47:24.289347 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4548 12:47:24.289527
4549 12:47:24.292536 [DATLAT]
4550 12:47:24.292682 Freq=600, CH1 RK0
4551 12:47:24.292827
4552 12:47:24.295764 DATLAT Default: 0x9
4553 12:47:24.295906 0, 0xFFFF, sum = 0
4554 12:47:24.299354 1, 0xFFFF, sum = 0
4555 12:47:24.299497 2, 0xFFFF, sum = 0
4556 12:47:24.302259 3, 0xFFFF, sum = 0
4557 12:47:24.302406 4, 0xFFFF, sum = 0
4558 12:47:24.305888 5, 0xFFFF, sum = 0
4559 12:47:24.306031 6, 0xFFFF, sum = 0
4560 12:47:24.309186 7, 0xFFFF, sum = 0
4561 12:47:24.309331 8, 0x0, sum = 1
4562 12:47:24.312415 9, 0x0, sum = 2
4563 12:47:24.312560 10, 0x0, sum = 3
4564 12:47:24.315541 11, 0x0, sum = 4
4565 12:47:24.315684 best_step = 9
4566 12:47:24.315812
4567 12:47:24.315938 ==
4568 12:47:24.319289 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 12:47:24.322187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 12:47:24.325534 ==
4571 12:47:24.325672 RX Vref Scan: 1
4572 12:47:24.325800
4573 12:47:24.328916 RX Vref 0 -> 0, step: 1
4574 12:47:24.329059
4575 12:47:24.332580 RX Delay -179 -> 252, step: 8
4576 12:47:24.332740
4577 12:47:24.335994 Set Vref, RX VrefLevel [Byte0]: 53
4578 12:47:24.338663 [Byte1]: 53
4579 12:47:24.338815
4580 12:47:24.342195 Final RX Vref Byte 0 = 53 to rank0
4581 12:47:24.345580 Final RX Vref Byte 1 = 53 to rank0
4582 12:47:24.348712 Final RX Vref Byte 0 = 53 to rank1
4583 12:47:24.351967 Final RX Vref Byte 1 = 53 to rank1==
4584 12:47:24.355421 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 12:47:24.358690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 12:47:24.358847 ==
4587 12:47:24.362324 DQS Delay:
4588 12:47:24.362466 DQS0 = 0, DQS1 = 0
4589 12:47:24.362596 DQM Delay:
4590 12:47:24.365310 DQM0 = 48, DQM1 = 39
4591 12:47:24.365452 DQ Delay:
4592 12:47:24.368590 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4593 12:47:24.372445 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4594 12:47:24.375395 DQ8 =28, DQ9 =24, DQ10 =48, DQ11 =32
4595 12:47:24.378609 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =44
4596 12:47:24.378750
4597 12:47:24.378875
4598 12:47:24.388396 [DQSOSCAuto] RK0, (LSB)MR18= 0x466d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4599 12:47:24.388551 CH1 RK0: MR19=808, MR18=466D
4600 12:47:24.395648 CH1_RK0: MR19=0x808, MR18=0x466D, DQSOSC=389, MR23=63, INC=173, DEC=115
4601 12:47:24.395793
4602 12:47:24.398555 ----->DramcWriteLeveling(PI) begin...
4603 12:47:24.402248 ==
4604 12:47:24.402409 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 12:47:24.408634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 12:47:24.408801 ==
4607 12:47:24.411960 Write leveling (Byte 0): 29 => 29
4608 12:47:24.414999 Write leveling (Byte 1): 29 => 29
4609 12:47:24.418551 DramcWriteLeveling(PI) end<-----
4610 12:47:24.418692
4611 12:47:24.418828 ==
4612 12:47:24.421971 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 12:47:24.425166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 12:47:24.425304 ==
4615 12:47:24.428455 [Gating] SW mode calibration
4616 12:47:24.435186 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4617 12:47:24.438613 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4618 12:47:24.445095 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 12:47:24.448307 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4620 12:47:24.451852 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4621 12:47:24.458672 0 9 12 | B1->B0 | 2b2b 2f2f | 1 1 | (1 0) (1 0)
4622 12:47:24.461781 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 12:47:24.465099 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 12:47:24.471676 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 12:47:24.474846 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 12:47:24.478540 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 12:47:24.484904 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 12:47:24.488376 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4629 12:47:24.491559 0 10 12 | B1->B0 | 3838 2e2e | 1 0 | (0 0) (0 0)
4630 12:47:24.498330 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 12:47:24.501531 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 12:47:24.504687 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 12:47:24.511762 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 12:47:24.514850 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 12:47:24.518106 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 12:47:24.524836 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4637 12:47:24.528019 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4638 12:47:24.531414 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:47:24.538050 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 12:47:24.541394 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 12:47:24.544895 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 12:47:24.551589 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 12:47:24.554737 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 12:47:24.558168 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 12:47:24.561409 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 12:47:24.567866 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 12:47:24.571304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 12:47:24.574884 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 12:47:24.581026 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 12:47:24.584639 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 12:47:24.587891 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 12:47:24.594258 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 12:47:24.597998 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4654 12:47:24.601353 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 12:47:24.604395 Total UI for P1: 0, mck2ui 16
4656 12:47:24.607658 best dqsien dly found for B0: ( 0, 13, 12)
4657 12:47:24.611031 Total UI for P1: 0, mck2ui 16
4658 12:47:24.614500 best dqsien dly found for B1: ( 0, 13, 12)
4659 12:47:24.617810 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4660 12:47:24.620948 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4661 12:47:24.624582
4662 12:47:24.627745 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4663 12:47:24.631113 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4664 12:47:24.634351 [Gating] SW calibration Done
4665 12:47:24.634446 ==
4666 12:47:24.637932 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 12:47:24.641054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 12:47:24.641150 ==
4669 12:47:24.641217 RX Vref Scan: 0
4670 12:47:24.641280
4671 12:47:24.644540 RX Vref 0 -> 0, step: 1
4672 12:47:24.644630
4673 12:47:24.647696 RX Delay -230 -> 252, step: 16
4674 12:47:24.650853 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4675 12:47:24.654424 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4676 12:47:24.661048 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4677 12:47:24.664993 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4678 12:47:24.667531 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4679 12:47:24.670850 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4680 12:47:24.674702 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4681 12:47:24.681070 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4682 12:47:24.684536 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4683 12:47:24.687889 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4684 12:47:24.691085 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4685 12:47:24.697964 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4686 12:47:24.701140 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4687 12:47:24.704263 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4688 12:47:24.707734 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4689 12:47:24.714487 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4690 12:47:24.714623 ==
4691 12:47:24.717718 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 12:47:24.720922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 12:47:24.721029 ==
4694 12:47:24.721098 DQS Delay:
4695 12:47:24.723966 DQS0 = 0, DQS1 = 0
4696 12:47:24.724058 DQM Delay:
4697 12:47:24.727689 DQM0 = 52, DQM1 = 45
4698 12:47:24.727797 DQ Delay:
4699 12:47:24.730754 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4700 12:47:24.734523 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4701 12:47:24.737584 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4702 12:47:24.740958 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4703 12:47:24.741115
4704 12:47:24.741235
4705 12:47:24.741345 ==
4706 12:47:24.743944 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 12:47:24.747335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 12:47:24.747496 ==
4709 12:47:24.750526
4710 12:47:24.750645
4711 12:47:24.750744 TX Vref Scan disable
4712 12:47:24.754324 == TX Byte 0 ==
4713 12:47:24.757328 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4714 12:47:24.760558 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4715 12:47:24.764383 == TX Byte 1 ==
4716 12:47:24.767368 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4717 12:47:24.770760 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4718 12:47:24.770872 ==
4719 12:47:24.773888 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 12:47:24.780640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 12:47:24.780801 ==
4722 12:47:24.780876
4723 12:47:24.780939
4724 12:47:24.783811 TX Vref Scan disable
4725 12:47:24.783900 == TX Byte 0 ==
4726 12:47:24.790398 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4727 12:47:24.793924 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4728 12:47:24.794038 == TX Byte 1 ==
4729 12:47:24.800415 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4730 12:47:24.803647 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4731 12:47:24.803753
4732 12:47:24.803823 [DATLAT]
4733 12:47:24.807117 Freq=600, CH1 RK1
4734 12:47:24.807252
4735 12:47:24.807365 DATLAT Default: 0x9
4736 12:47:24.810781 0, 0xFFFF, sum = 0
4737 12:47:24.810918 1, 0xFFFF, sum = 0
4738 12:47:24.813762 2, 0xFFFF, sum = 0
4739 12:47:24.813852 3, 0xFFFF, sum = 0
4740 12:47:24.817302 4, 0xFFFF, sum = 0
4741 12:47:24.817395 5, 0xFFFF, sum = 0
4742 12:47:24.820495 6, 0xFFFF, sum = 0
4743 12:47:24.820611 7, 0xFFFF, sum = 0
4744 12:47:24.823613 8, 0x0, sum = 1
4745 12:47:24.823708 9, 0x0, sum = 2
4746 12:47:24.827505 10, 0x0, sum = 3
4747 12:47:24.827643 11, 0x0, sum = 4
4748 12:47:24.830462 best_step = 9
4749 12:47:24.830592
4750 12:47:24.830700 ==
4751 12:47:24.833654 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 12:47:24.837154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 12:47:24.837258 ==
4754 12:47:24.840428 RX Vref Scan: 0
4755 12:47:24.840573
4756 12:47:24.840692 RX Vref 0 -> 0, step: 1
4757 12:47:24.840817
4758 12:47:24.843614 RX Delay -179 -> 252, step: 8
4759 12:47:24.850441 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4760 12:47:24.854135 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4761 12:47:24.857292 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4762 12:47:24.860694 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4763 12:47:24.863544 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4764 12:47:24.870811 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4765 12:47:24.873856 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4766 12:47:24.877255 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4767 12:47:24.880390 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4768 12:47:24.883682 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4769 12:47:24.890323 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4770 12:47:24.893812 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4771 12:47:24.896781 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4772 12:47:24.900429 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4773 12:47:24.907229 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4774 12:47:24.910269 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4775 12:47:24.910429 ==
4776 12:47:24.913477 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 12:47:24.917219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 12:47:24.917373 ==
4779 12:47:24.920311 DQS Delay:
4780 12:47:24.920426 DQS0 = 0, DQS1 = 0
4781 12:47:24.920523 DQM Delay:
4782 12:47:24.923715 DQM0 = 49, DQM1 = 44
4783 12:47:24.923835 DQ Delay:
4784 12:47:24.926815 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4785 12:47:24.930690 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4786 12:47:24.933387 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4787 12:47:24.936946 DQ12 =48, DQ13 =52, DQ14 =48, DQ15 =56
4788 12:47:24.937091
4789 12:47:24.937210
4790 12:47:24.946984 [DQSOSCAuto] RK1, (LSB)MR18= 0x591f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4791 12:47:24.947179 CH1 RK1: MR19=808, MR18=591F
4792 12:47:24.953692 CH1_RK1: MR19=0x808, MR18=0x591F, DQSOSC=393, MR23=63, INC=169, DEC=113
4793 12:47:24.956781 [RxdqsGatingPostProcess] freq 600
4794 12:47:24.963682 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4795 12:47:24.966843 Pre-setting of DQS Precalculation
4796 12:47:24.970699 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4797 12:47:24.976669 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4798 12:47:24.987003 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4799 12:47:24.987161
4800 12:47:24.987260
4801 12:47:24.989877 [Calibration Summary] 1200 Mbps
4802 12:47:24.990014 CH 0, Rank 0
4803 12:47:24.993105 SW Impedance : PASS
4804 12:47:24.993228 DUTY Scan : NO K
4805 12:47:24.996614 ZQ Calibration : PASS
4806 12:47:24.999812 Jitter Meter : NO K
4807 12:47:24.999925 CBT Training : PASS
4808 12:47:25.003080 Write leveling : PASS
4809 12:47:25.003183 RX DQS gating : PASS
4810 12:47:25.006682 RX DQ/DQS(RDDQC) : PASS
4811 12:47:25.010194 TX DQ/DQS : PASS
4812 12:47:25.010310 RX DATLAT : PASS
4813 12:47:25.013247 RX DQ/DQS(Engine): PASS
4814 12:47:25.016768 TX OE : NO K
4815 12:47:25.016887 All Pass.
4816 12:47:25.016959
4817 12:47:25.017022 CH 0, Rank 1
4818 12:47:25.019930 SW Impedance : PASS
4819 12:47:25.023116 DUTY Scan : NO K
4820 12:47:25.023237 ZQ Calibration : PASS
4821 12:47:25.026327 Jitter Meter : NO K
4822 12:47:25.029980 CBT Training : PASS
4823 12:47:25.030094 Write leveling : PASS
4824 12:47:25.033094 RX DQS gating : PASS
4825 12:47:25.036302 RX DQ/DQS(RDDQC) : PASS
4826 12:47:25.036408 TX DQ/DQS : PASS
4827 12:47:25.039951 RX DATLAT : PASS
4828 12:47:25.043458 RX DQ/DQS(Engine): PASS
4829 12:47:25.043567 TX OE : NO K
4830 12:47:25.043637 All Pass.
4831 12:47:25.043700
4832 12:47:25.046682 CH 1, Rank 0
4833 12:47:25.046778 SW Impedance : PASS
4834 12:47:25.049737 DUTY Scan : NO K
4835 12:47:25.053127 ZQ Calibration : PASS
4836 12:47:25.053232 Jitter Meter : NO K
4837 12:47:25.056546 CBT Training : PASS
4838 12:47:25.059708 Write leveling : PASS
4839 12:47:25.059814 RX DQS gating : PASS
4840 12:47:25.063159 RX DQ/DQS(RDDQC) : PASS
4841 12:47:25.066537 TX DQ/DQS : PASS
4842 12:47:25.066641 RX DATLAT : PASS
4843 12:47:25.069799 RX DQ/DQS(Engine): PASS
4844 12:47:25.073379 TX OE : NO K
4845 12:47:25.073484 All Pass.
4846 12:47:25.073558
4847 12:47:25.073622 CH 1, Rank 1
4848 12:47:25.076396 SW Impedance : PASS
4849 12:47:25.079804 DUTY Scan : NO K
4850 12:47:25.079902 ZQ Calibration : PASS
4851 12:47:25.082973 Jitter Meter : NO K
4852 12:47:25.086775 CBT Training : PASS
4853 12:47:25.086867 Write leveling : PASS
4854 12:47:25.089757 RX DQS gating : PASS
4855 12:47:25.093221 RX DQ/DQS(RDDQC) : PASS
4856 12:47:25.093349 TX DQ/DQS : PASS
4857 12:47:25.096237 RX DATLAT : PASS
4858 12:47:25.096357 RX DQ/DQS(Engine): PASS
4859 12:47:25.099628 TX OE : NO K
4860 12:47:25.099779 All Pass.
4861 12:47:25.099909
4862 12:47:25.103239 DramC Write-DBI off
4863 12:47:25.106361 PER_BANK_REFRESH: Hybrid Mode
4864 12:47:25.106468 TX_TRACKING: ON
4865 12:47:25.116257 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4866 12:47:25.119461 [FAST_K] Save calibration result to emmc
4867 12:47:25.123095 dramc_set_vcore_voltage set vcore to 662500
4868 12:47:25.126053 Read voltage for 933, 3
4869 12:47:25.126161 Vio18 = 0
4870 12:47:25.129419 Vcore = 662500
4871 12:47:25.129519 Vdram = 0
4872 12:47:25.129589 Vddq = 0
4873 12:47:25.129652 Vmddr = 0
4874 12:47:25.136026 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4875 12:47:25.139451 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4876 12:47:25.142384 MEM_TYPE=3, freq_sel=17
4877 12:47:25.145778 sv_algorithm_assistance_LP4_1600
4878 12:47:25.149180 ============ PULL DRAM RESETB DOWN ============
4879 12:47:25.155915 ========== PULL DRAM RESETB DOWN end =========
4880 12:47:25.159660 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4881 12:47:25.162661 ===================================
4882 12:47:25.166024 LPDDR4 DRAM CONFIGURATION
4883 12:47:25.169294 ===================================
4884 12:47:25.169425 EX_ROW_EN[0] = 0x0
4885 12:47:25.172601 EX_ROW_EN[1] = 0x0
4886 12:47:25.172781 LP4Y_EN = 0x0
4887 12:47:25.175768 WORK_FSP = 0x0
4888 12:47:25.175933 WL = 0x3
4889 12:47:25.179102 RL = 0x3
4890 12:47:25.182365 BL = 0x2
4891 12:47:25.182543 RPST = 0x0
4892 12:47:25.185739 RD_PRE = 0x0
4893 12:47:25.185902 WR_PRE = 0x1
4894 12:47:25.189319 WR_PST = 0x0
4895 12:47:25.189482 DBI_WR = 0x0
4896 12:47:25.192828 DBI_RD = 0x0
4897 12:47:25.193008 OTF = 0x1
4898 12:47:25.195978 ===================================
4899 12:47:25.199076 ===================================
4900 12:47:25.202502 ANA top config
4901 12:47:25.202687 ===================================
4902 12:47:25.205534 DLL_ASYNC_EN = 0
4903 12:47:25.208673 ALL_SLAVE_EN = 1
4904 12:47:25.212497 NEW_RANK_MODE = 1
4905 12:47:25.215307 DLL_IDLE_MODE = 1
4906 12:47:25.215478 LP45_APHY_COMB_EN = 1
4907 12:47:25.218601 TX_ODT_DIS = 1
4908 12:47:25.222010 NEW_8X_MODE = 1
4909 12:47:25.225438 ===================================
4910 12:47:25.229036 ===================================
4911 12:47:25.232643 data_rate = 1866
4912 12:47:25.235502 CKR = 1
4913 12:47:25.238796 DQ_P2S_RATIO = 8
4914 12:47:25.238955 ===================================
4915 12:47:25.242108 CA_P2S_RATIO = 8
4916 12:47:25.245517 DQ_CA_OPEN = 0
4917 12:47:25.248647 DQ_SEMI_OPEN = 0
4918 12:47:25.252158 CA_SEMI_OPEN = 0
4919 12:47:25.255579 CA_FULL_RATE = 0
4920 12:47:25.255733 DQ_CKDIV4_EN = 1
4921 12:47:25.258499 CA_CKDIV4_EN = 1
4922 12:47:25.262049 CA_PREDIV_EN = 0
4923 12:47:25.265102 PH8_DLY = 0
4924 12:47:25.268789 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4925 12:47:25.271987 DQ_AAMCK_DIV = 4
4926 12:47:25.272116 CA_AAMCK_DIV = 4
4927 12:47:25.275526 CA_ADMCK_DIV = 4
4928 12:47:25.278538 DQ_TRACK_CA_EN = 0
4929 12:47:25.281760 CA_PICK = 933
4930 12:47:25.285421 CA_MCKIO = 933
4931 12:47:25.288460 MCKIO_SEMI = 0
4932 12:47:25.292011 PLL_FREQ = 3732
4933 12:47:25.292124 DQ_UI_PI_RATIO = 32
4934 12:47:25.295142 CA_UI_PI_RATIO = 0
4935 12:47:25.298430 ===================================
4936 12:47:25.301748 ===================================
4937 12:47:25.305149 memory_type:LPDDR4
4938 12:47:25.308619 GP_NUM : 10
4939 12:47:25.308764 SRAM_EN : 1
4940 12:47:25.311869 MD32_EN : 0
4941 12:47:25.315268 ===================================
4942 12:47:25.318608 [ANA_INIT] >>>>>>>>>>>>>>
4943 12:47:25.318728 <<<<<< [CONFIGURE PHASE]: ANA_TX
4944 12:47:25.321853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4945 12:47:25.325056 ===================================
4946 12:47:25.328557 data_rate = 1866,PCW = 0X8f00
4947 12:47:25.331922 ===================================
4948 12:47:25.335267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4949 12:47:25.341894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 12:47:25.348249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4951 12:47:25.351580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4952 12:47:25.355112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4953 12:47:25.358206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4954 12:47:25.361759 [ANA_INIT] flow start
4955 12:47:25.361850 [ANA_INIT] PLL >>>>>>>>
4956 12:47:25.364931 [ANA_INIT] PLL <<<<<<<<
4957 12:47:25.368520 [ANA_INIT] MIDPI >>>>>>>>
4958 12:47:25.368633 [ANA_INIT] MIDPI <<<<<<<<
4959 12:47:25.371521 [ANA_INIT] DLL >>>>>>>>
4960 12:47:25.375075 [ANA_INIT] flow end
4961 12:47:25.378432 ============ LP4 DIFF to SE enter ============
4962 12:47:25.381521 ============ LP4 DIFF to SE exit ============
4963 12:47:25.384865 [ANA_INIT] <<<<<<<<<<<<<
4964 12:47:25.388065 [Flow] Enable top DCM control >>>>>
4965 12:47:25.391766 [Flow] Enable top DCM control <<<<<
4966 12:47:25.394916 Enable DLL master slave shuffle
4967 12:47:25.398028 ==============================================================
4968 12:47:25.401546 Gating Mode config
4969 12:47:25.408036 ==============================================================
4970 12:47:25.408195 Config description:
4971 12:47:25.418347 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4972 12:47:25.424566 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4973 12:47:25.431443 SELPH_MODE 0: By rank 1: By Phase
4974 12:47:25.434846 ==============================================================
4975 12:47:25.438138 GAT_TRACK_EN = 1
4976 12:47:25.441072 RX_GATING_MODE = 2
4977 12:47:25.444629 RX_GATING_TRACK_MODE = 2
4978 12:47:25.448059 SELPH_MODE = 1
4979 12:47:25.451248 PICG_EARLY_EN = 1
4980 12:47:25.454811 VALID_LAT_VALUE = 1
4981 12:47:25.458288 ==============================================================
4982 12:47:25.461369 Enter into Gating configuration >>>>
4983 12:47:25.464595 Exit from Gating configuration <<<<
4984 12:47:25.467959 Enter into DVFS_PRE_config >>>>>
4985 12:47:25.481368 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4986 12:47:25.481560 Exit from DVFS_PRE_config <<<<<
4987 12:47:25.484757 Enter into PICG configuration >>>>
4988 12:47:25.488161 Exit from PICG configuration <<<<
4989 12:47:25.491204 [RX_INPUT] configuration >>>>>
4990 12:47:25.494830 [RX_INPUT] configuration <<<<<
4991 12:47:25.501541 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4992 12:47:25.504448 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4993 12:47:25.511497 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 12:47:25.517946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 12:47:25.524649 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 12:47:25.531212 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 12:47:25.534764 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4998 12:47:25.537840 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4999 12:47:25.541114 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5000 12:47:25.547747 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5001 12:47:25.551327 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5002 12:47:25.554424 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 12:47:25.557876 ===================================
5004 12:47:25.561191 LPDDR4 DRAM CONFIGURATION
5005 12:47:25.564366 ===================================
5006 12:47:25.564489 EX_ROW_EN[0] = 0x0
5007 12:47:25.568019 EX_ROW_EN[1] = 0x0
5008 12:47:25.571478 LP4Y_EN = 0x0
5009 12:47:25.571612 WORK_FSP = 0x0
5010 12:47:25.574416 WL = 0x3
5011 12:47:25.574535 RL = 0x3
5012 12:47:25.578021 BL = 0x2
5013 12:47:25.578143 RPST = 0x0
5014 12:47:25.581205 RD_PRE = 0x0
5015 12:47:25.581316 WR_PRE = 0x1
5016 12:47:25.584247 WR_PST = 0x0
5017 12:47:25.584370 DBI_WR = 0x0
5018 12:47:25.587683 DBI_RD = 0x0
5019 12:47:25.587816 OTF = 0x1
5020 12:47:25.591261 ===================================
5021 12:47:25.594447 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5022 12:47:25.601257 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5023 12:47:25.604415 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 12:47:25.607590 ===================================
5025 12:47:25.611330 LPDDR4 DRAM CONFIGURATION
5026 12:47:25.614555 ===================================
5027 12:47:25.614659 EX_ROW_EN[0] = 0x10
5028 12:47:25.617572 EX_ROW_EN[1] = 0x0
5029 12:47:25.617667 LP4Y_EN = 0x0
5030 12:47:25.621000 WORK_FSP = 0x0
5031 12:47:25.624298 WL = 0x3
5032 12:47:25.624422 RL = 0x3
5033 12:47:25.627555 BL = 0x2
5034 12:47:25.627692 RPST = 0x0
5035 12:47:25.630934 RD_PRE = 0x0
5036 12:47:25.631067 WR_PRE = 0x1
5037 12:47:25.634336 WR_PST = 0x0
5038 12:47:25.634460 DBI_WR = 0x0
5039 12:47:25.637630 DBI_RD = 0x0
5040 12:47:25.637761 OTF = 0x1
5041 12:47:25.641054 ===================================
5042 12:47:25.647850 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5043 12:47:25.651351 nWR fixed to 30
5044 12:47:25.654703 [ModeRegInit_LP4] CH0 RK0
5045 12:47:25.654856 [ModeRegInit_LP4] CH0 RK1
5046 12:47:25.658063 [ModeRegInit_LP4] CH1 RK0
5047 12:47:25.661400 [ModeRegInit_LP4] CH1 RK1
5048 12:47:25.661517 match AC timing 9
5049 12:47:25.668452 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5050 12:47:25.671424 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5051 12:47:25.675324 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5052 12:47:25.681915 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5053 12:47:25.684748 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5054 12:47:25.684866 ==
5055 12:47:25.688124 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 12:47:25.691441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 12:47:25.691573 ==
5058 12:47:25.697907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 12:47:25.704974 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5060 12:47:25.708066 [CA 0] Center 38 (7~69) winsize 63
5061 12:47:25.711302 [CA 1] Center 38 (8~69) winsize 62
5062 12:47:25.714645 [CA 2] Center 35 (5~66) winsize 62
5063 12:47:25.717869 [CA 3] Center 35 (5~65) winsize 61
5064 12:47:25.721211 [CA 4] Center 34 (4~65) winsize 62
5065 12:47:25.724720 [CA 5] Center 33 (3~64) winsize 62
5066 12:47:25.724875
5067 12:47:25.727992 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5068 12:47:25.728132
5069 12:47:25.731461 [CATrainingPosCal] consider 1 rank data
5070 12:47:25.734630 u2DelayCellTimex100 = 270/100 ps
5071 12:47:25.738135 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5072 12:47:25.741254 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5073 12:47:25.744573 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5074 12:47:25.748031 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5075 12:47:25.751236 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5076 12:47:25.754374 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5077 12:47:25.757925
5078 12:47:25.761064 CA PerBit enable=1, Macro0, CA PI delay=33
5079 12:47:25.761193
5080 12:47:25.764401 [CBTSetCACLKResult] CA Dly = 33
5081 12:47:25.764533 CS Dly: 7 (0~38)
5082 12:47:25.764646 ==
5083 12:47:25.767984 Dram Type= 6, Freq= 0, CH_0, rank 1
5084 12:47:25.771001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 12:47:25.771143 ==
5086 12:47:25.777935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5087 12:47:25.784302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5088 12:47:25.787716 [CA 0] Center 38 (7~69) winsize 63
5089 12:47:25.791176 [CA 1] Center 38 (8~69) winsize 62
5090 12:47:25.794670 [CA 2] Center 36 (6~66) winsize 61
5091 12:47:25.798109 [CA 3] Center 35 (5~66) winsize 62
5092 12:47:25.801197 [CA 4] Center 34 (4~65) winsize 62
5093 12:47:25.804279 [CA 5] Center 34 (4~65) winsize 62
5094 12:47:25.804431
5095 12:47:25.807922 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5096 12:47:25.808082
5097 12:47:25.811044 [CATrainingPosCal] consider 2 rank data
5098 12:47:25.814629 u2DelayCellTimex100 = 270/100 ps
5099 12:47:25.817565 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5100 12:47:25.821108 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5101 12:47:25.824228 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5102 12:47:25.827792 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5103 12:47:25.830932 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5104 12:47:25.837554 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5105 12:47:25.837697
5106 12:47:25.841267 CA PerBit enable=1, Macro0, CA PI delay=34
5107 12:47:25.841366
5108 12:47:25.844338 [CBTSetCACLKResult] CA Dly = 34
5109 12:47:25.844476 CS Dly: 7 (0~39)
5110 12:47:25.844597
5111 12:47:25.847700 ----->DramcWriteLeveling(PI) begin...
5112 12:47:25.847841 ==
5113 12:47:25.851415 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 12:47:25.854409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 12:47:25.857742 ==
5116 12:47:25.857844 Write leveling (Byte 0): 32 => 32
5117 12:47:25.861098 Write leveling (Byte 1): 29 => 29
5118 12:47:25.864368 DramcWriteLeveling(PI) end<-----
5119 12:47:25.864488
5120 12:47:25.864585 ==
5121 12:47:25.867930 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 12:47:25.874375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 12:47:25.874489 ==
5124 12:47:25.874562 [Gating] SW mode calibration
5125 12:47:25.884413 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5126 12:47:25.887740 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5127 12:47:25.890903 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
5128 12:47:25.897849 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 12:47:25.901394 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 12:47:25.904267 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 12:47:25.911303 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 12:47:25.914773 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 12:47:25.917652 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5134 12:47:25.924122 0 14 28 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
5135 12:47:25.927566 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5136 12:47:25.930949 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 12:47:25.937373 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 12:47:25.940689 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 12:47:25.944064 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 12:47:25.950797 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 12:47:25.954312 0 15 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5142 12:47:25.957740 0 15 28 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
5143 12:47:25.964208 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5144 12:47:25.967701 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 12:47:25.970598 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 12:47:25.977545 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 12:47:25.980641 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 12:47:25.984018 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 12:47:25.990679 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5150 12:47:25.993905 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5151 12:47:25.997541 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5152 12:47:26.003991 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5153 12:47:26.007312 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 12:47:26.010535 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 12:47:26.014233 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 12:47:26.020863 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 12:47:26.024021 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 12:47:26.027268 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 12:47:26.034095 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 12:47:26.037345 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 12:47:26.040611 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 12:47:26.047746 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 12:47:26.050702 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 12:47:26.054013 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 12:47:26.060642 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 12:47:26.064147 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5167 12:47:26.067224 Total UI for P1: 0, mck2ui 16
5168 12:47:26.070463 best dqsien dly found for B0: ( 1, 2, 26)
5169 12:47:26.074121 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 12:47:26.077485 Total UI for P1: 0, mck2ui 16
5171 12:47:26.080663 best dqsien dly found for B1: ( 1, 2, 28)
5172 12:47:26.084158 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5173 12:47:26.087353 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5174 12:47:26.087508
5175 12:47:26.094093 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5176 12:47:26.097048 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5177 12:47:26.097196 [Gating] SW calibration Done
5178 12:47:26.100481 ==
5179 12:47:26.103542 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 12:47:26.106970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 12:47:26.107106 ==
5182 12:47:26.107208 RX Vref Scan: 0
5183 12:47:26.107299
5184 12:47:26.110101 RX Vref 0 -> 0, step: 1
5185 12:47:26.110240
5186 12:47:26.114054 RX Delay -80 -> 252, step: 8
5187 12:47:26.117028 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5188 12:47:26.120268 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5189 12:47:26.126914 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5190 12:47:26.130542 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5191 12:47:26.133706 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5192 12:47:26.137236 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5193 12:47:26.140549 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5194 12:47:26.143540 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5195 12:47:26.150050 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5196 12:47:26.153369 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5197 12:47:26.156631 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5198 12:47:26.160119 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5199 12:47:26.163489 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5200 12:47:26.166666 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5201 12:47:26.170296 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5202 12:47:26.176814 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5203 12:47:26.176987 ==
5204 12:47:26.180023 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 12:47:26.183309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 12:47:26.183458 ==
5207 12:47:26.183579 DQS Delay:
5208 12:47:26.186837 DQS0 = 0, DQS1 = 0
5209 12:47:26.186974 DQM Delay:
5210 12:47:26.189945 DQM0 = 105, DQM1 = 90
5211 12:47:26.190077 DQ Delay:
5212 12:47:26.193221 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5213 12:47:26.196542 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5214 12:47:26.199903 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =87
5215 12:47:26.203382 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5216 12:47:26.203492
5217 12:47:26.203573
5218 12:47:26.203654 ==
5219 12:47:26.206919 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 12:47:26.213425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 12:47:26.213553 ==
5222 12:47:26.213622
5223 12:47:26.213694
5224 12:47:26.213765 TX Vref Scan disable
5225 12:47:26.216615 == TX Byte 0 ==
5226 12:47:26.219748 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5227 12:47:26.226748 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5228 12:47:26.226879 == TX Byte 1 ==
5229 12:47:26.229722 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5230 12:47:26.236684 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5231 12:47:26.236833 ==
5232 12:47:26.239931 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 12:47:26.243102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 12:47:26.243204 ==
5235 12:47:26.243275
5236 12:47:26.243339
5237 12:47:26.246426 TX Vref Scan disable
5238 12:47:26.246521 == TX Byte 0 ==
5239 12:47:26.253057 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5240 12:47:26.256644 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5241 12:47:26.256768 == TX Byte 1 ==
5242 12:47:26.263234 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5243 12:47:26.266319 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5244 12:47:26.266455
5245 12:47:26.266552 [DATLAT]
5246 12:47:26.269775 Freq=933, CH0 RK0
5247 12:47:26.269914
5248 12:47:26.270028 DATLAT Default: 0xd
5249 12:47:26.273196 0, 0xFFFF, sum = 0
5250 12:47:26.273290 1, 0xFFFF, sum = 0
5251 12:47:26.276410 2, 0xFFFF, sum = 0
5252 12:47:26.276506 3, 0xFFFF, sum = 0
5253 12:47:26.280134 4, 0xFFFF, sum = 0
5254 12:47:26.280237 5, 0xFFFF, sum = 0
5255 12:47:26.283217 6, 0xFFFF, sum = 0
5256 12:47:26.283311 7, 0xFFFF, sum = 0
5257 12:47:26.286625 8, 0xFFFF, sum = 0
5258 12:47:26.289795 9, 0xFFFF, sum = 0
5259 12:47:26.289897 10, 0x0, sum = 1
5260 12:47:26.289967 11, 0x0, sum = 2
5261 12:47:26.292926 12, 0x0, sum = 3
5262 12:47:26.293034 13, 0x0, sum = 4
5263 12:47:26.296180 best_step = 11
5264 12:47:26.296263
5265 12:47:26.296327 ==
5266 12:47:26.299761 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 12:47:26.303116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 12:47:26.303221 ==
5269 12:47:26.306172 RX Vref Scan: 1
5270 12:47:26.306267
5271 12:47:26.306335 RX Vref 0 -> 0, step: 1
5272 12:47:26.306396
5273 12:47:26.309742 RX Delay -53 -> 252, step: 4
5274 12:47:26.309879
5275 12:47:26.313043 Set Vref, RX VrefLevel [Byte0]: 58
5276 12:47:26.316168 [Byte1]: 48
5277 12:47:26.320443
5278 12:47:26.320555 Final RX Vref Byte 0 = 58 to rank0
5279 12:47:26.323854 Final RX Vref Byte 1 = 48 to rank0
5280 12:47:26.327711 Final RX Vref Byte 0 = 58 to rank1
5281 12:47:26.330485 Final RX Vref Byte 1 = 48 to rank1==
5282 12:47:26.334055 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 12:47:26.340663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 12:47:26.340807 ==
5285 12:47:26.340882 DQS Delay:
5286 12:47:26.340947 DQS0 = 0, DQS1 = 0
5287 12:47:26.343991 DQM Delay:
5288 12:47:26.344083 DQM0 = 107, DQM1 = 90
5289 12:47:26.346992 DQ Delay:
5290 12:47:26.350269 DQ0 =108, DQ1 =108, DQ2 =102, DQ3 =106
5291 12:47:26.353628 DQ4 =106, DQ5 =98, DQ6 =118, DQ7 =114
5292 12:47:26.357562 DQ8 =84, DQ9 =76, DQ10 =90, DQ11 =90
5293 12:47:26.360350 DQ12 =94, DQ13 =90, DQ14 =102, DQ15 =100
5294 12:47:26.360452
5295 12:47:26.360520
5296 12:47:26.367194 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5297 12:47:26.370720 CH0 RK0: MR19=505, MR18=2420
5298 12:47:26.377123 CH0_RK0: MR19=0x505, MR18=0x2420, DQSOSC=410, MR23=63, INC=64, DEC=42
5299 12:47:26.377285
5300 12:47:26.380082 ----->DramcWriteLeveling(PI) begin...
5301 12:47:26.380207 ==
5302 12:47:26.383588 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 12:47:26.386739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 12:47:26.386838 ==
5305 12:47:26.390185 Write leveling (Byte 0): 30 => 30
5306 12:47:26.393650 Write leveling (Byte 1): 30 => 30
5307 12:47:26.396842 DramcWriteLeveling(PI) end<-----
5308 12:47:26.396961
5309 12:47:26.397045 ==
5310 12:47:26.400191 Dram Type= 6, Freq= 0, CH_0, rank 1
5311 12:47:26.407133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 12:47:26.407257 ==
5313 12:47:26.407324 [Gating] SW mode calibration
5314 12:47:26.416644 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5315 12:47:26.419891 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5316 12:47:26.423206 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 12:47:26.429806 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 12:47:26.433256 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 12:47:26.436511 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 12:47:26.443765 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 12:47:26.447017 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 12:47:26.450100 0 14 24 | B1->B0 | 3434 3333 | 0 1 | (0 1) (0 0)
5323 12:47:26.456670 0 14 28 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (1 0)
5324 12:47:26.460352 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5325 12:47:26.463309 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 12:47:26.469795 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 12:47:26.473066 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 12:47:26.476491 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 12:47:26.483195 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 12:47:26.486501 0 15 24 | B1->B0 | 2828 2e2e | 1 1 | (0 0) (0 0)
5331 12:47:26.489796 0 15 28 | B1->B0 | 3c3c 4241 | 0 1 | (0 0) (0 0)
5332 12:47:26.496671 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 12:47:26.500015 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 12:47:26.503579 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 12:47:26.510180 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 12:47:26.513078 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 12:47:26.516407 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 12:47:26.519720 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 12:47:26.526321 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5340 12:47:26.529863 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 12:47:26.533534 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:47:26.540078 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 12:47:26.543223 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 12:47:26.546674 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 12:47:26.553288 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 12:47:26.556673 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 12:47:26.559983 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 12:47:26.566173 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 12:47:26.569821 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 12:47:26.573029 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 12:47:26.579698 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 12:47:26.583035 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 12:47:26.586446 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 12:47:26.593140 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 12:47:26.596241 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5356 12:47:26.599645 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 12:47:26.602933 Total UI for P1: 0, mck2ui 16
5358 12:47:26.606051 best dqsien dly found for B0: ( 1, 2, 28)
5359 12:47:26.609380 Total UI for P1: 0, mck2ui 16
5360 12:47:26.613250 best dqsien dly found for B1: ( 1, 2, 28)
5361 12:47:26.616083 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5362 12:47:26.619816 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5363 12:47:26.619949
5364 12:47:26.625970 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5365 12:47:26.629372 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5366 12:47:26.629497 [Gating] SW calibration Done
5367 12:47:26.633054 ==
5368 12:47:26.633179 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 12:47:26.639397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 12:47:26.639519 ==
5371 12:47:26.639640 RX Vref Scan: 0
5372 12:47:26.639750
5373 12:47:26.642838 RX Vref 0 -> 0, step: 1
5374 12:47:26.642964
5375 12:47:26.646114 RX Delay -80 -> 252, step: 8
5376 12:47:26.649398 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5377 12:47:26.652734 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5378 12:47:26.655889 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5379 12:47:26.662451 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5380 12:47:26.665858 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5381 12:47:26.669566 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5382 12:47:26.672430 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5383 12:47:26.675674 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5384 12:47:26.679375 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5385 12:47:26.685957 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5386 12:47:26.688872 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5387 12:47:26.692486 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5388 12:47:26.695734 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5389 12:47:26.699300 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5390 12:47:26.702557 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5391 12:47:26.708934 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5392 12:47:26.709045 ==
5393 12:47:26.712560 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 12:47:26.716063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 12:47:26.716168 ==
5396 12:47:26.716262 DQS Delay:
5397 12:47:26.719048 DQS0 = 0, DQS1 = 0
5398 12:47:26.719148 DQM Delay:
5399 12:47:26.722556 DQM0 = 104, DQM1 = 90
5400 12:47:26.722642 DQ Delay:
5401 12:47:26.725755 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5402 12:47:26.728807 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5403 12:47:26.732458 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5404 12:47:26.735635 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5405 12:47:26.735720
5406 12:47:26.735786
5407 12:47:26.735847 ==
5408 12:47:26.739105 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 12:47:26.742785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 12:47:26.745693 ==
5411 12:47:26.745777
5412 12:47:26.745843
5413 12:47:26.745904 TX Vref Scan disable
5414 12:47:26.749042 == TX Byte 0 ==
5415 12:47:26.752396 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5416 12:47:26.755569 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5417 12:47:26.758904 == TX Byte 1 ==
5418 12:47:26.762332 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5419 12:47:26.765793 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5420 12:47:26.768916 ==
5421 12:47:26.772121 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 12:47:26.775335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 12:47:26.775447 ==
5424 12:47:26.775552
5425 12:47:26.775651
5426 12:47:26.778943 TX Vref Scan disable
5427 12:47:26.779048 == TX Byte 0 ==
5428 12:47:26.785235 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5429 12:47:26.788679 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5430 12:47:26.788809 == TX Byte 1 ==
5431 12:47:26.795401 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5432 12:47:26.798774 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5433 12:47:26.798865
5434 12:47:26.798932 [DATLAT]
5435 12:47:26.802077 Freq=933, CH0 RK1
5436 12:47:26.802163
5437 12:47:26.802230 DATLAT Default: 0xb
5438 12:47:26.805675 0, 0xFFFF, sum = 0
5439 12:47:26.805763 1, 0xFFFF, sum = 0
5440 12:47:26.808588 2, 0xFFFF, sum = 0
5441 12:47:26.808703 3, 0xFFFF, sum = 0
5442 12:47:26.812203 4, 0xFFFF, sum = 0
5443 12:47:26.812290 5, 0xFFFF, sum = 0
5444 12:47:26.815102 6, 0xFFFF, sum = 0
5445 12:47:26.815188 7, 0xFFFF, sum = 0
5446 12:47:26.818817 8, 0xFFFF, sum = 0
5447 12:47:26.822077 9, 0xFFFF, sum = 0
5448 12:47:26.822164 10, 0x0, sum = 1
5449 12:47:26.822232 11, 0x0, sum = 2
5450 12:47:26.825349 12, 0x0, sum = 3
5451 12:47:26.825482 13, 0x0, sum = 4
5452 12:47:26.828496 best_step = 11
5453 12:47:26.828622
5454 12:47:26.828735 ==
5455 12:47:26.832138 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 12:47:26.835419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 12:47:26.835544 ==
5458 12:47:26.838909 RX Vref Scan: 0
5459 12:47:26.839029
5460 12:47:26.839145 RX Vref 0 -> 0, step: 1
5461 12:47:26.839253
5462 12:47:26.841887 RX Delay -53 -> 252, step: 4
5463 12:47:26.849170 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5464 12:47:26.852611 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5465 12:47:26.855682 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5466 12:47:26.858895 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5467 12:47:26.862170 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5468 12:47:26.869129 iDelay=203, Bit 5, Center 98 (11 ~ 186) 176
5469 12:47:26.872621 iDelay=203, Bit 6, Center 116 (31 ~ 202) 172
5470 12:47:26.875487 iDelay=203, Bit 7, Center 112 (27 ~ 198) 172
5471 12:47:26.878989 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5472 12:47:26.882208 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5473 12:47:26.885685 iDelay=203, Bit 10, Center 92 (7 ~ 178) 172
5474 12:47:26.892521 iDelay=203, Bit 11, Center 90 (7 ~ 174) 168
5475 12:47:26.895453 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5476 12:47:26.899117 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5477 12:47:26.902426 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5478 12:47:26.905809 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5479 12:47:26.908990 ==
5480 12:47:26.909102 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 12:47:26.915602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 12:47:26.915716 ==
5483 12:47:26.915822 DQS Delay:
5484 12:47:26.919277 DQS0 = 0, DQS1 = 0
5485 12:47:26.919383 DQM Delay:
5486 12:47:26.922216 DQM0 = 104, DQM1 = 91
5487 12:47:26.922319 DQ Delay:
5488 12:47:26.925802 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5489 12:47:26.929163 DQ4 =104, DQ5 =98, DQ6 =116, DQ7 =112
5490 12:47:26.932300 DQ8 =84, DQ9 =80, DQ10 =92, DQ11 =90
5491 12:47:26.935364 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5492 12:47:26.935476
5493 12:47:26.935572
5494 12:47:26.942397 [DQSOSCAuto] RK1, (LSB)MR18= 0x2809, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5495 12:47:26.945647 CH0 RK1: MR19=505, MR18=2809
5496 12:47:26.952277 CH0_RK1: MR19=0x505, MR18=0x2809, DQSOSC=409, MR23=63, INC=64, DEC=43
5497 12:47:26.955429 [RxdqsGatingPostProcess] freq 933
5498 12:47:26.961857 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5499 12:47:26.965823 best DQS0 dly(2T, 0.5T) = (0, 10)
5500 12:47:26.968458 best DQS1 dly(2T, 0.5T) = (0, 10)
5501 12:47:26.971932 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5502 12:47:26.975285 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5503 12:47:26.975425 best DQS0 dly(2T, 0.5T) = (0, 10)
5504 12:47:26.978778 best DQS1 dly(2T, 0.5T) = (0, 10)
5505 12:47:26.982179 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5506 12:47:26.985515 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5507 12:47:26.988393 Pre-setting of DQS Precalculation
5508 12:47:26.995554 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5509 12:47:26.995696 ==
5510 12:47:26.998536 Dram Type= 6, Freq= 0, CH_1, rank 0
5511 12:47:27.002264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 12:47:27.002375 ==
5513 12:47:27.008729 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5514 12:47:27.011873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5515 12:47:27.015918 [CA 0] Center 37 (7~68) winsize 62
5516 12:47:27.019591 [CA 1] Center 37 (7~68) winsize 62
5517 12:47:27.022726 [CA 2] Center 35 (5~66) winsize 62
5518 12:47:27.026317 [CA 3] Center 34 (4~65) winsize 62
5519 12:47:27.029271 [CA 4] Center 35 (5~66) winsize 62
5520 12:47:27.032583 [CA 5] Center 34 (4~64) winsize 61
5521 12:47:27.032669
5522 12:47:27.036026 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5523 12:47:27.036112
5524 12:47:27.039249 [CATrainingPosCal] consider 1 rank data
5525 12:47:27.043122 u2DelayCellTimex100 = 270/100 ps
5526 12:47:27.046059 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5527 12:47:27.049389 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5528 12:47:27.056064 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5529 12:47:27.059647 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5530 12:47:27.062707 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5531 12:47:27.066015 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5532 12:47:27.066138
5533 12:47:27.069262 CA PerBit enable=1, Macro0, CA PI delay=34
5534 12:47:27.069416
5535 12:47:27.073008 [CBTSetCACLKResult] CA Dly = 34
5536 12:47:27.073133 CS Dly: 6 (0~37)
5537 12:47:27.076036 ==
5538 12:47:27.076169 Dram Type= 6, Freq= 0, CH_1, rank 1
5539 12:47:27.082848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 12:47:27.082959 ==
5541 12:47:27.086156 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5542 12:47:27.092541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5543 12:47:27.096674 [CA 0] Center 38 (8~68) winsize 61
5544 12:47:27.099423 [CA 1] Center 38 (8~69) winsize 62
5545 12:47:27.102648 [CA 2] Center 36 (6~66) winsize 61
5546 12:47:27.106269 [CA 3] Center 35 (6~65) winsize 60
5547 12:47:27.109482 [CA 4] Center 35 (5~65) winsize 61
5548 12:47:27.113076 [CA 5] Center 35 (5~65) winsize 61
5549 12:47:27.113172
5550 12:47:27.115972 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5551 12:47:27.116046
5552 12:47:27.119389 [CATrainingPosCal] consider 2 rank data
5553 12:47:27.122770 u2DelayCellTimex100 = 270/100 ps
5554 12:47:27.126270 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5555 12:47:27.129255 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5556 12:47:27.135803 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5557 12:47:27.139323 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5558 12:47:27.142826 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5559 12:47:27.146026 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5560 12:47:27.146100
5561 12:47:27.149661 CA PerBit enable=1, Macro0, CA PI delay=34
5562 12:47:27.149741
5563 12:47:27.153133 [CBTSetCACLKResult] CA Dly = 34
5564 12:47:27.153214 CS Dly: 7 (0~39)
5565 12:47:27.153276
5566 12:47:27.155903 ----->DramcWriteLeveling(PI) begin...
5567 12:47:27.159329 ==
5568 12:47:27.162554 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 12:47:27.166049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 12:47:27.166128 ==
5571 12:47:27.169143 Write leveling (Byte 0): 26 => 26
5572 12:47:27.172565 Write leveling (Byte 1): 29 => 29
5573 12:47:27.176000 DramcWriteLeveling(PI) end<-----
5574 12:47:27.176093
5575 12:47:27.176156 ==
5576 12:47:27.179164 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 12:47:27.182911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 12:47:27.183004 ==
5579 12:47:27.185994 [Gating] SW mode calibration
5580 12:47:27.192737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5581 12:47:27.199418 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5582 12:47:27.202796 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 12:47:27.206014 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 12:47:27.209224 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 12:47:27.215759 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 12:47:27.219317 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 12:47:27.222402 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5588 12:47:27.229028 0 14 24 | B1->B0 | 3030 3030 | 1 1 | (1 1) (1 0)
5589 12:47:27.232478 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5590 12:47:27.235889 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 12:47:27.242796 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 12:47:27.245942 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 12:47:27.249088 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 12:47:27.255616 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 12:47:27.259245 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 12:47:27.262383 0 15 24 | B1->B0 | 2929 2f2f | 0 1 | (0 0) (0 0)
5597 12:47:27.268913 0 15 28 | B1->B0 | 3c3c 4545 | 0 0 | (1 1) (0 0)
5598 12:47:27.272473 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 12:47:27.275877 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 12:47:27.282511 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 12:47:27.285453 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 12:47:27.288978 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 12:47:27.295750 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 12:47:27.298899 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5605 12:47:27.302658 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:47:27.308992 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:47:27.312491 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:47:27.315610 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 12:47:27.322313 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 12:47:27.325486 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 12:47:27.329110 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 12:47:27.335690 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 12:47:27.338772 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 12:47:27.342285 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 12:47:27.345425 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 12:47:27.352321 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 12:47:27.355431 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 12:47:27.361937 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 12:47:27.365102 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 12:47:27.368907 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5621 12:47:27.371771 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5622 12:47:27.378619 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 12:47:27.381642 Total UI for P1: 0, mck2ui 16
5624 12:47:27.385191 best dqsien dly found for B0: ( 1, 2, 26)
5625 12:47:27.388254 Total UI for P1: 0, mck2ui 16
5626 12:47:27.391598 best dqsien dly found for B1: ( 1, 2, 28)
5627 12:47:27.395002 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5628 12:47:27.398149 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5629 12:47:27.398227
5630 12:47:27.401574 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5631 12:47:27.404692 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5632 12:47:27.408102 [Gating] SW calibration Done
5633 12:47:27.408177 ==
5634 12:47:27.411553 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 12:47:27.414676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 12:47:27.414756 ==
5637 12:47:27.418434 RX Vref Scan: 0
5638 12:47:27.418560
5639 12:47:27.421356 RX Vref 0 -> 0, step: 1
5640 12:47:27.421438
5641 12:47:27.421502 RX Delay -80 -> 252, step: 8
5642 12:47:27.427797 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5643 12:47:27.431176 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5644 12:47:27.434946 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5645 12:47:27.437826 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5646 12:47:27.441542 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5647 12:47:27.444978 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5648 12:47:27.451040 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5649 12:47:27.454431 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5650 12:47:27.457477 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5651 12:47:27.460886 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5652 12:47:27.464369 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5653 12:47:27.471105 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5654 12:47:27.474197 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5655 12:47:27.477665 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5656 12:47:27.480863 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5657 12:47:27.484218 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5658 12:47:27.484293 ==
5659 12:47:27.487784 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 12:47:27.494032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 12:47:27.494121 ==
5662 12:47:27.494202 DQS Delay:
5663 12:47:27.497526 DQS0 = 0, DQS1 = 0
5664 12:47:27.497601 DQM Delay:
5665 12:47:27.497664 DQM0 = 102, DQM1 = 95
5666 12:47:27.500865 DQ Delay:
5667 12:47:27.504079 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5668 12:47:27.507205 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5669 12:47:27.510864 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5670 12:47:27.514174 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5671 12:47:27.514260
5672 12:47:27.514327
5673 12:47:27.514390 ==
5674 12:47:27.517309 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 12:47:27.520992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 12:47:27.521079 ==
5677 12:47:27.521147
5678 12:47:27.521209
5679 12:47:27.523954 TX Vref Scan disable
5680 12:47:27.527273 == TX Byte 0 ==
5681 12:47:27.530694 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5682 12:47:27.533970 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5683 12:47:27.537038 == TX Byte 1 ==
5684 12:47:27.540672 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5685 12:47:27.543885 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5686 12:47:27.543986 ==
5687 12:47:27.546948 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 12:47:27.550317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 12:47:27.553591 ==
5690 12:47:27.553714
5691 12:47:27.553838
5692 12:47:27.553947 TX Vref Scan disable
5693 12:47:27.557179 == TX Byte 0 ==
5694 12:47:27.560830 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5695 12:47:27.567159 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5696 12:47:27.567298 == TX Byte 1 ==
5697 12:47:27.570624 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5698 12:47:27.577268 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5699 12:47:27.577356
5700 12:47:27.577424 [DATLAT]
5701 12:47:27.577487 Freq=933, CH1 RK0
5702 12:47:27.577548
5703 12:47:27.580447 DATLAT Default: 0xd
5704 12:47:27.580532 0, 0xFFFF, sum = 0
5705 12:47:27.583811 1, 0xFFFF, sum = 0
5706 12:47:27.583898 2, 0xFFFF, sum = 0
5707 12:47:27.587227 3, 0xFFFF, sum = 0
5708 12:47:27.587314 4, 0xFFFF, sum = 0
5709 12:47:27.590710 5, 0xFFFF, sum = 0
5710 12:47:27.593778 6, 0xFFFF, sum = 0
5711 12:47:27.593858 7, 0xFFFF, sum = 0
5712 12:47:27.597402 8, 0xFFFF, sum = 0
5713 12:47:27.597484 9, 0xFFFF, sum = 0
5714 12:47:27.600864 10, 0x0, sum = 1
5715 12:47:27.600944 11, 0x0, sum = 2
5716 12:47:27.603662 12, 0x0, sum = 3
5717 12:47:27.603740 13, 0x0, sum = 4
5718 12:47:27.603806 best_step = 11
5719 12:47:27.603867
5720 12:47:27.606950 ==
5721 12:47:27.610319 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 12:47:27.613963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 12:47:27.614050 ==
5724 12:47:27.614118 RX Vref Scan: 1
5725 12:47:27.614181
5726 12:47:27.616843 RX Vref 0 -> 0, step: 1
5727 12:47:27.616950
5728 12:47:27.620144 RX Delay -53 -> 252, step: 4
5729 12:47:27.620219
5730 12:47:27.623832 Set Vref, RX VrefLevel [Byte0]: 53
5731 12:47:27.626962 [Byte1]: 53
5732 12:47:27.627046
5733 12:47:27.630435 Final RX Vref Byte 0 = 53 to rank0
5734 12:47:27.634004 Final RX Vref Byte 1 = 53 to rank0
5735 12:47:27.637062 Final RX Vref Byte 0 = 53 to rank1
5736 12:47:27.640530 Final RX Vref Byte 1 = 53 to rank1==
5737 12:47:27.643577 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 12:47:27.647054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 12:47:27.647140 ==
5740 12:47:27.650581 DQS Delay:
5741 12:47:27.650665 DQS0 = 0, DQS1 = 0
5742 12:47:27.653718 DQM Delay:
5743 12:47:27.653863 DQM0 = 104, DQM1 = 97
5744 12:47:27.653931 DQ Delay:
5745 12:47:27.657240 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5746 12:47:27.663587 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5747 12:47:27.667025 DQ8 =90, DQ9 =86, DQ10 =100, DQ11 =92
5748 12:47:27.670587 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =102
5749 12:47:27.670671
5750 12:47:27.670743
5751 12:47:27.677002 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5752 12:47:27.680233 CH1 RK0: MR19=505, MR18=1830
5753 12:47:27.686787 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5754 12:47:27.686872
5755 12:47:27.689955 ----->DramcWriteLeveling(PI) begin...
5756 12:47:27.690041 ==
5757 12:47:27.693848 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 12:47:27.696976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 12:47:27.697059 ==
5760 12:47:27.700172 Write leveling (Byte 0): 26 => 26
5761 12:47:27.703744 Write leveling (Byte 1): 27 => 27
5762 12:47:27.706641 DramcWriteLeveling(PI) end<-----
5763 12:47:27.706726
5764 12:47:27.706792 ==
5765 12:47:27.710248 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 12:47:27.713644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 12:47:27.713734 ==
5768 12:47:27.716614 [Gating] SW mode calibration
5769 12:47:27.723261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5770 12:47:27.730081 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5771 12:47:27.733362 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5772 12:47:27.740249 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 12:47:27.743803 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 12:47:27.746462 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 12:47:27.752990 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 12:47:27.756587 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 12:47:27.759940 0 14 24 | B1->B0 | 3030 3434 | 1 0 | (1 0) (0 0)
5778 12:47:27.766372 0 14 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 0)
5779 12:47:27.770106 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5780 12:47:27.773323 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 12:47:27.779692 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 12:47:27.783222 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 12:47:27.786429 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 12:47:27.790210 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 12:47:27.796716 0 15 24 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
5786 12:47:27.799677 0 15 28 | B1->B0 | 4242 3636 | 0 1 | (0 0) (0 0)
5787 12:47:27.802938 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 12:47:27.809849 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 12:47:27.813188 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 12:47:27.816459 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 12:47:27.823380 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 12:47:27.826292 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 12:47:27.829904 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5794 12:47:27.836430 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5795 12:47:27.839911 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 12:47:27.842757 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 12:47:27.849689 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 12:47:27.853049 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 12:47:27.856209 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 12:47:27.863046 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 12:47:27.866412 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 12:47:27.869371 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 12:47:27.876327 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 12:47:27.879308 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 12:47:27.882982 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 12:47:27.889662 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 12:47:27.892791 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 12:47:27.896175 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 12:47:27.902753 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5810 12:47:27.906367 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5811 12:47:27.909416 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 12:47:27.912894 Total UI for P1: 0, mck2ui 16
5813 12:47:27.915878 best dqsien dly found for B0: ( 1, 2, 26)
5814 12:47:27.919265 Total UI for P1: 0, mck2ui 16
5815 12:47:27.922604 best dqsien dly found for B1: ( 1, 2, 26)
5816 12:47:27.925839 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5817 12:47:27.929269 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5818 12:47:27.929356
5819 12:47:27.932784 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5820 12:47:27.939618 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5821 12:47:27.939713 [Gating] SW calibration Done
5822 12:47:27.939783 ==
5823 12:47:27.942747 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 12:47:27.949389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 12:47:27.949476 ==
5826 12:47:27.949544 RX Vref Scan: 0
5827 12:47:27.949607
5828 12:47:27.952761 RX Vref 0 -> 0, step: 1
5829 12:47:27.952840
5830 12:47:27.956292 RX Delay -80 -> 252, step: 8
5831 12:47:27.959336 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5832 12:47:27.962388 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5833 12:47:27.966020 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5834 12:47:27.969229 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5835 12:47:27.975884 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5836 12:47:27.979115 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5837 12:47:27.982650 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5838 12:47:27.986170 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5839 12:47:27.989159 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5840 12:47:27.992414 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5841 12:47:27.999075 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5842 12:47:28.002876 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5843 12:47:28.006029 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5844 12:47:28.009263 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5845 12:47:28.012588 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5846 12:47:28.019122 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5847 12:47:28.019273 ==
5848 12:47:28.022182 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 12:47:28.025798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 12:47:28.025914 ==
5851 12:47:28.026013 DQS Delay:
5852 12:47:28.029200 DQS0 = 0, DQS1 = 0
5853 12:47:28.029286 DQM Delay:
5854 12:47:28.032497 DQM0 = 101, DQM1 = 96
5855 12:47:28.032583 DQ Delay:
5856 12:47:28.035820 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5857 12:47:28.038988 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =99
5858 12:47:28.042344 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5859 12:47:28.045499 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5860 12:47:28.045585
5861 12:47:28.045653
5862 12:47:28.045716 ==
5863 12:47:28.048926 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 12:47:28.052133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 12:47:28.055795 ==
5866 12:47:28.055881
5867 12:47:28.055948
5868 12:47:28.056011 TX Vref Scan disable
5869 12:47:28.058709 == TX Byte 0 ==
5870 12:47:28.062204 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5871 12:47:28.065647 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5872 12:47:28.068637 == TX Byte 1 ==
5873 12:47:28.072266 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5874 12:47:28.075365 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5875 12:47:28.078927 ==
5876 12:47:28.082289 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 12:47:28.085299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 12:47:28.085385 ==
5879 12:47:28.085453
5880 12:47:28.085516
5881 12:47:28.088489 TX Vref Scan disable
5882 12:47:28.088575 == TX Byte 0 ==
5883 12:47:28.095222 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5884 12:47:28.098497 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5885 12:47:28.098613 == TX Byte 1 ==
5886 12:47:28.105483 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5887 12:47:28.108425 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5888 12:47:28.108511
5889 12:47:28.108601 [DATLAT]
5890 12:47:28.111819 Freq=933, CH1 RK1
5891 12:47:28.111905
5892 12:47:28.111973 DATLAT Default: 0xb
5893 12:47:28.115429 0, 0xFFFF, sum = 0
5894 12:47:28.115517 1, 0xFFFF, sum = 0
5895 12:47:28.118197 2, 0xFFFF, sum = 0
5896 12:47:28.118285 3, 0xFFFF, sum = 0
5897 12:47:28.121971 4, 0xFFFF, sum = 0
5898 12:47:28.122085 5, 0xFFFF, sum = 0
5899 12:47:28.125016 6, 0xFFFF, sum = 0
5900 12:47:28.128574 7, 0xFFFF, sum = 0
5901 12:47:28.128704 8, 0xFFFF, sum = 0
5902 12:47:28.131759 9, 0xFFFF, sum = 0
5903 12:47:28.131886 10, 0x0, sum = 1
5904 12:47:28.132001 11, 0x0, sum = 2
5905 12:47:28.134968 12, 0x0, sum = 3
5906 12:47:28.135095 13, 0x0, sum = 4
5907 12:47:28.138285 best_step = 11
5908 12:47:28.138406
5909 12:47:28.138519 ==
5910 12:47:28.141532 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 12:47:28.145121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 12:47:28.145232 ==
5913 12:47:28.148373 RX Vref Scan: 0
5914 12:47:28.148475
5915 12:47:28.148567 RX Vref 0 -> 0, step: 1
5916 12:47:28.148656
5917 12:47:28.151624 RX Delay -53 -> 252, step: 4
5918 12:47:28.158797 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5919 12:47:28.162253 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5920 12:47:28.165886 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5921 12:47:28.169033 iDelay=199, Bit 3, Center 102 (23 ~ 182) 160
5922 12:47:28.172187 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5923 12:47:28.178905 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5924 12:47:28.182100 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5925 12:47:28.185466 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5926 12:47:28.189208 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5927 12:47:28.192051 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5928 12:47:28.195498 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5929 12:47:28.202559 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5930 12:47:28.205416 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5931 12:47:28.209013 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5932 12:47:28.212397 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5933 12:47:28.218843 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5934 12:47:28.218972 ==
5935 12:47:28.222263 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 12:47:28.225574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 12:47:28.225664 ==
5938 12:47:28.225731 DQS Delay:
5939 12:47:28.229024 DQS0 = 0, DQS1 = 0
5940 12:47:28.229109 DQM Delay:
5941 12:47:28.232233 DQM0 = 104, DQM1 = 97
5942 12:47:28.232316 DQ Delay:
5943 12:47:28.235829 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5944 12:47:28.238668 DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =102
5945 12:47:28.242276 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
5946 12:47:28.245513 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =106
5947 12:47:28.245641
5948 12:47:28.245755
5949 12:47:28.255598 [DQSOSCAuto] RK1, (LSB)MR18= 0x2300, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5950 12:47:28.255731 CH1 RK1: MR19=505, MR18=2300
5951 12:47:28.262121 CH1_RK1: MR19=0x505, MR18=0x2300, DQSOSC=410, MR23=63, INC=64, DEC=42
5952 12:47:28.265427 [RxdqsGatingPostProcess] freq 933
5953 12:47:28.272184 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5954 12:47:28.275418 best DQS0 dly(2T, 0.5T) = (0, 10)
5955 12:47:28.278752 best DQS1 dly(2T, 0.5T) = (0, 10)
5956 12:47:28.282040 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5957 12:47:28.285574 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5958 12:47:28.285698 best DQS0 dly(2T, 0.5T) = (0, 10)
5959 12:47:28.289194 best DQS1 dly(2T, 0.5T) = (0, 10)
5960 12:47:28.292313 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5961 12:47:28.295498 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5962 12:47:28.298789 Pre-setting of DQS Precalculation
5963 12:47:28.305401 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5964 12:47:28.311886 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5965 12:47:28.318912 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5966 12:47:28.318999
5967 12:47:28.319070
5968 12:47:28.322302 [Calibration Summary] 1866 Mbps
5969 12:47:28.322377 CH 0, Rank 0
5970 12:47:28.325663 SW Impedance : PASS
5971 12:47:28.328522 DUTY Scan : NO K
5972 12:47:28.328608 ZQ Calibration : PASS
5973 12:47:28.331948 Jitter Meter : NO K
5974 12:47:28.335473 CBT Training : PASS
5975 12:47:28.335585 Write leveling : PASS
5976 12:47:28.338454 RX DQS gating : PASS
5977 12:47:28.341906 RX DQ/DQS(RDDQC) : PASS
5978 12:47:28.342015 TX DQ/DQS : PASS
5979 12:47:28.345475 RX DATLAT : PASS
5980 12:47:28.348815 RX DQ/DQS(Engine): PASS
5981 12:47:28.348903 TX OE : NO K
5982 12:47:28.351732 All Pass.
5983 12:47:28.351820
5984 12:47:28.351906 CH 0, Rank 1
5985 12:47:28.355204 SW Impedance : PASS
5986 12:47:28.355291 DUTY Scan : NO K
5987 12:47:28.358416 ZQ Calibration : PASS
5988 12:47:28.361655 Jitter Meter : NO K
5989 12:47:28.361743 CBT Training : PASS
5990 12:47:28.365198 Write leveling : PASS
5991 12:47:28.365311 RX DQS gating : PASS
5992 12:47:28.368676 RX DQ/DQS(RDDQC) : PASS
5993 12:47:28.371859 TX DQ/DQS : PASS
5994 12:47:28.371969 RX DATLAT : PASS
5995 12:47:28.375156 RX DQ/DQS(Engine): PASS
5996 12:47:28.378351 TX OE : NO K
5997 12:47:28.378457 All Pass.
5998 12:47:28.378558
5999 12:47:28.378657 CH 1, Rank 0
6000 12:47:28.381830 SW Impedance : PASS
6001 12:47:28.385571 DUTY Scan : NO K
6002 12:47:28.385660 ZQ Calibration : PASS
6003 12:47:28.388419 Jitter Meter : NO K
6004 12:47:28.391813 CBT Training : PASS
6005 12:47:28.391900 Write leveling : PASS
6006 12:47:28.395205 RX DQS gating : PASS
6007 12:47:28.398339 RX DQ/DQS(RDDQC) : PASS
6008 12:47:28.398420 TX DQ/DQS : PASS
6009 12:47:28.401700 RX DATLAT : PASS
6010 12:47:28.404925 RX DQ/DQS(Engine): PASS
6011 12:47:28.405029 TX OE : NO K
6012 12:47:28.405126 All Pass.
6013 12:47:28.408442
6014 12:47:28.408547 CH 1, Rank 1
6015 12:47:28.411823 SW Impedance : PASS
6016 12:47:28.411900 DUTY Scan : NO K
6017 12:47:28.415393 ZQ Calibration : PASS
6018 12:47:28.415495 Jitter Meter : NO K
6019 12:47:28.418898 CBT Training : PASS
6020 12:47:28.421839 Write leveling : PASS
6021 12:47:28.421943 RX DQS gating : PASS
6022 12:47:28.425298 RX DQ/DQS(RDDQC) : PASS
6023 12:47:28.428533 TX DQ/DQS : PASS
6024 12:47:28.428644 RX DATLAT : PASS
6025 12:47:28.432047 RX DQ/DQS(Engine): PASS
6026 12:47:28.435314 TX OE : NO K
6027 12:47:28.435399 All Pass.
6028 12:47:28.435471
6029 12:47:28.435535 DramC Write-DBI off
6030 12:47:28.438433 PER_BANK_REFRESH: Hybrid Mode
6031 12:47:28.442021 TX_TRACKING: ON
6032 12:47:28.448362 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6033 12:47:28.451927 [FAST_K] Save calibration result to emmc
6034 12:47:28.458685 dramc_set_vcore_voltage set vcore to 650000
6035 12:47:28.458769 Read voltage for 400, 6
6036 12:47:28.462130 Vio18 = 0
6037 12:47:28.462232 Vcore = 650000
6038 12:47:28.462325 Vdram = 0
6039 12:47:28.465473 Vddq = 0
6040 12:47:28.465546 Vmddr = 0
6041 12:47:28.468440 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6042 12:47:28.475267 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6043 12:47:28.478315 MEM_TYPE=3, freq_sel=20
6044 12:47:28.478388 sv_algorithm_assistance_LP4_800
6045 12:47:28.484882 ============ PULL DRAM RESETB DOWN ============
6046 12:47:28.488628 ========== PULL DRAM RESETB DOWN end =========
6047 12:47:28.491602 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6048 12:47:28.494775 ===================================
6049 12:47:28.498515 LPDDR4 DRAM CONFIGURATION
6050 12:47:28.501694 ===================================
6051 12:47:28.504910 EX_ROW_EN[0] = 0x0
6052 12:47:28.505010 EX_ROW_EN[1] = 0x0
6053 12:47:28.508245 LP4Y_EN = 0x0
6054 12:47:28.508346 WORK_FSP = 0x0
6055 12:47:28.511177 WL = 0x2
6056 12:47:28.511278 RL = 0x2
6057 12:47:28.514841 BL = 0x2
6058 12:47:28.514917 RPST = 0x0
6059 12:47:28.517842 RD_PRE = 0x0
6060 12:47:28.517918 WR_PRE = 0x1
6061 12:47:28.521277 WR_PST = 0x0
6062 12:47:28.524900 DBI_WR = 0x0
6063 12:47:28.524974 DBI_RD = 0x0
6064 12:47:28.527931 OTF = 0x1
6065 12:47:28.531385 ===================================
6066 12:47:28.534692 ===================================
6067 12:47:28.534792 ANA top config
6068 12:47:28.537866 ===================================
6069 12:47:28.541144 DLL_ASYNC_EN = 0
6070 12:47:28.541243 ALL_SLAVE_EN = 1
6071 12:47:28.544796 NEW_RANK_MODE = 1
6072 12:47:28.547842 DLL_IDLE_MODE = 1
6073 12:47:28.551174 LP45_APHY_COMB_EN = 1
6074 12:47:28.554388 TX_ODT_DIS = 1
6075 12:47:28.554486 NEW_8X_MODE = 1
6076 12:47:28.557846 ===================================
6077 12:47:28.560969 ===================================
6078 12:47:28.564606 data_rate = 800
6079 12:47:28.567685 CKR = 1
6080 12:47:28.571230 DQ_P2S_RATIO = 4
6081 12:47:28.574464 ===================================
6082 12:47:28.577416 CA_P2S_RATIO = 4
6083 12:47:28.581072 DQ_CA_OPEN = 0
6084 12:47:28.581159 DQ_SEMI_OPEN = 1
6085 12:47:28.584445 CA_SEMI_OPEN = 1
6086 12:47:28.587887 CA_FULL_RATE = 0
6087 12:47:28.591222 DQ_CKDIV4_EN = 0
6088 12:47:28.594432 CA_CKDIV4_EN = 1
6089 12:47:28.597556 CA_PREDIV_EN = 0
6090 12:47:28.597645 PH8_DLY = 0
6091 12:47:28.601123 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6092 12:47:28.604427 DQ_AAMCK_DIV = 0
6093 12:47:28.607676 CA_AAMCK_DIV = 0
6094 12:47:28.610659 CA_ADMCK_DIV = 4
6095 12:47:28.614061 DQ_TRACK_CA_EN = 0
6096 12:47:28.617086 CA_PICK = 800
6097 12:47:28.617178 CA_MCKIO = 400
6098 12:47:28.620610 MCKIO_SEMI = 400
6099 12:47:28.623846 PLL_FREQ = 3016
6100 12:47:28.627687 DQ_UI_PI_RATIO = 32
6101 12:47:28.630853 CA_UI_PI_RATIO = 32
6102 12:47:28.633910 ===================================
6103 12:47:28.637485 ===================================
6104 12:47:28.640556 memory_type:LPDDR4
6105 12:47:28.640673 GP_NUM : 10
6106 12:47:28.644064 SRAM_EN : 1
6107 12:47:28.644195 MD32_EN : 0
6108 12:47:28.647133 ===================================
6109 12:47:28.650324 [ANA_INIT] >>>>>>>>>>>>>>
6110 12:47:28.653776 <<<<<< [CONFIGURE PHASE]: ANA_TX
6111 12:47:28.657337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6112 12:47:28.660514 ===================================
6113 12:47:28.664057 data_rate = 800,PCW = 0X7400
6114 12:47:28.667026 ===================================
6115 12:47:28.670387 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6116 12:47:28.676757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6117 12:47:28.686704 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 12:47:28.690311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6119 12:47:28.693533 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6120 12:47:28.696747 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6121 12:47:28.700268 [ANA_INIT] flow start
6122 12:47:28.703521 [ANA_INIT] PLL >>>>>>>>
6123 12:47:28.703653 [ANA_INIT] PLL <<<<<<<<
6124 12:47:28.706818 [ANA_INIT] MIDPI >>>>>>>>
6125 12:47:28.710396 [ANA_INIT] MIDPI <<<<<<<<
6126 12:47:28.713499 [ANA_INIT] DLL >>>>>>>>
6127 12:47:28.713580 [ANA_INIT] flow end
6128 12:47:28.717093 ============ LP4 DIFF to SE enter ============
6129 12:47:28.723516 ============ LP4 DIFF to SE exit ============
6130 12:47:28.723635 [ANA_INIT] <<<<<<<<<<<<<
6131 12:47:28.726988 [Flow] Enable top DCM control >>>>>
6132 12:47:28.730291 [Flow] Enable top DCM control <<<<<
6133 12:47:28.733616 Enable DLL master slave shuffle
6134 12:47:28.740394 ==============================================================
6135 12:47:28.740489 Gating Mode config
6136 12:47:28.746834 ==============================================================
6137 12:47:28.749849 Config description:
6138 12:47:28.759820 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6139 12:47:28.766784 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6140 12:47:28.770176 SELPH_MODE 0: By rank 1: By Phase
6141 12:47:28.776636 ==============================================================
6142 12:47:28.779947 GAT_TRACK_EN = 0
6143 12:47:28.780026 RX_GATING_MODE = 2
6144 12:47:28.783453 RX_GATING_TRACK_MODE = 2
6145 12:47:28.786719 SELPH_MODE = 1
6146 12:47:28.790239 PICG_EARLY_EN = 1
6147 12:47:28.793052 VALID_LAT_VALUE = 1
6148 12:47:28.799595 ==============================================================
6149 12:47:28.803089 Enter into Gating configuration >>>>
6150 12:47:28.806202 Exit from Gating configuration <<<<
6151 12:47:28.809567 Enter into DVFS_PRE_config >>>>>
6152 12:47:28.819556 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6153 12:47:28.822873 Exit from DVFS_PRE_config <<<<<
6154 12:47:28.826369 Enter into PICG configuration >>>>
6155 12:47:28.829990 Exit from PICG configuration <<<<
6156 12:47:28.832896 [RX_INPUT] configuration >>>>>
6157 12:47:28.836322 [RX_INPUT] configuration <<<<<
6158 12:47:28.839428 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6159 12:47:28.846103 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6160 12:47:28.852855 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 12:47:28.856428 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 12:47:28.862792 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6163 12:47:28.869367 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6164 12:47:28.872932 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6165 12:47:28.879636 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6166 12:47:28.882697 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6167 12:47:28.886325 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6168 12:47:28.889766 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6169 12:47:28.896145 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 12:47:28.899716 ===================================
6171 12:47:28.899848 LPDDR4 DRAM CONFIGURATION
6172 12:47:28.902818 ===================================
6173 12:47:28.906515 EX_ROW_EN[0] = 0x0
6174 12:47:28.909573 EX_ROW_EN[1] = 0x0
6175 12:47:28.909651 LP4Y_EN = 0x0
6176 12:47:28.912669 WORK_FSP = 0x0
6177 12:47:28.912781 WL = 0x2
6178 12:47:28.916023 RL = 0x2
6179 12:47:28.916095 BL = 0x2
6180 12:47:28.919534 RPST = 0x0
6181 12:47:28.919608 RD_PRE = 0x0
6182 12:47:28.922931 WR_PRE = 0x1
6183 12:47:28.923000 WR_PST = 0x0
6184 12:47:28.926241 DBI_WR = 0x0
6185 12:47:28.926312 DBI_RD = 0x0
6186 12:47:28.929323 OTF = 0x1
6187 12:47:28.932950 ===================================
6188 12:47:28.936131 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6189 12:47:28.939256 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6190 12:47:28.942763 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6191 12:47:28.946406 ===================================
6192 12:47:28.949326 LPDDR4 DRAM CONFIGURATION
6193 12:47:28.952540 ===================================
6194 12:47:28.956167 EX_ROW_EN[0] = 0x10
6195 12:47:28.956256 EX_ROW_EN[1] = 0x0
6196 12:47:28.959336 LP4Y_EN = 0x0
6197 12:47:28.959412 WORK_FSP = 0x0
6198 12:47:28.962532 WL = 0x2
6199 12:47:28.962625 RL = 0x2
6200 12:47:28.966058 BL = 0x2
6201 12:47:28.969643 RPST = 0x0
6202 12:47:28.969725 RD_PRE = 0x0
6203 12:47:28.972653 WR_PRE = 0x1
6204 12:47:28.972736 WR_PST = 0x0
6205 12:47:28.976056 DBI_WR = 0x0
6206 12:47:28.976138 DBI_RD = 0x0
6207 12:47:28.979497 OTF = 0x1
6208 12:47:28.982658 ===================================
6209 12:47:28.986094 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6210 12:47:28.991400 nWR fixed to 30
6211 12:47:28.994865 [ModeRegInit_LP4] CH0 RK0
6212 12:47:28.994947 [ModeRegInit_LP4] CH0 RK1
6213 12:47:28.997805 [ModeRegInit_LP4] CH1 RK0
6214 12:47:29.001606 [ModeRegInit_LP4] CH1 RK1
6215 12:47:29.001687 match AC timing 19
6216 12:47:29.008006 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6217 12:47:29.011000 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6218 12:47:29.014553 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6219 12:47:29.021037 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6220 12:47:29.024373 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6221 12:47:29.024471 ==
6222 12:47:29.027901 Dram Type= 6, Freq= 0, CH_0, rank 0
6223 12:47:29.031432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6224 12:47:29.031516 ==
6225 12:47:29.037836 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6226 12:47:29.044588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6227 12:47:29.047748 [CA 0] Center 36 (8~64) winsize 57
6228 12:47:29.050915 [CA 1] Center 36 (8~64) winsize 57
6229 12:47:29.054666 [CA 2] Center 36 (8~64) winsize 57
6230 12:47:29.054749 [CA 3] Center 36 (8~64) winsize 57
6231 12:47:29.058026 [CA 4] Center 36 (8~64) winsize 57
6232 12:47:29.061150 [CA 5] Center 36 (8~64) winsize 57
6233 12:47:29.061278
6234 12:47:29.067734 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6235 12:47:29.067835
6236 12:47:29.071032 [CATrainingPosCal] consider 1 rank data
6237 12:47:29.074497 u2DelayCellTimex100 = 270/100 ps
6238 12:47:29.077621 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 12:47:29.081461 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 12:47:29.084300 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 12:47:29.087672 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 12:47:29.091358 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 12:47:29.094529 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 12:47:29.094612
6245 12:47:29.097707 CA PerBit enable=1, Macro0, CA PI delay=36
6246 12:47:29.097807
6247 12:47:29.101213 [CBTSetCACLKResult] CA Dly = 36
6248 12:47:29.104248 CS Dly: 1 (0~32)
6249 12:47:29.104348 ==
6250 12:47:29.108102 Dram Type= 6, Freq= 0, CH_0, rank 1
6251 12:47:29.110999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6252 12:47:29.111146 ==
6253 12:47:29.117801 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6254 12:47:29.120980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6255 12:47:29.124418 [CA 0] Center 36 (8~64) winsize 57
6256 12:47:29.127593 [CA 1] Center 36 (8~64) winsize 57
6257 12:47:29.131171 [CA 2] Center 36 (8~64) winsize 57
6258 12:47:29.134324 [CA 3] Center 36 (8~64) winsize 57
6259 12:47:29.138046 [CA 4] Center 36 (8~64) winsize 57
6260 12:47:29.140943 [CA 5] Center 36 (8~64) winsize 57
6261 12:47:29.141062
6262 12:47:29.144434 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6263 12:47:29.144548
6264 12:47:29.147677 [CATrainingPosCal] consider 2 rank data
6265 12:47:29.150883 u2DelayCellTimex100 = 270/100 ps
6266 12:47:29.154053 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 12:47:29.157779 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 12:47:29.160787 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 12:47:29.167495 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 12:47:29.170869 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 12:47:29.174119 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 12:47:29.174220
6273 12:47:29.177367 CA PerBit enable=1, Macro0, CA PI delay=36
6274 12:47:29.177453
6275 12:47:29.180896 [CBTSetCACLKResult] CA Dly = 36
6276 12:47:29.180980 CS Dly: 1 (0~32)
6277 12:47:29.181045
6278 12:47:29.183996 ----->DramcWriteLeveling(PI) begin...
6279 12:47:29.184095 ==
6280 12:47:29.187685 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 12:47:29.194346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 12:47:29.194445 ==
6283 12:47:29.197387 Write leveling (Byte 0): 40 => 8
6284 12:47:29.200861 Write leveling (Byte 1): 32 => 0
6285 12:47:29.200943 DramcWriteLeveling(PI) end<-----
6286 12:47:29.201008
6287 12:47:29.204158 ==
6288 12:47:29.207400 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 12:47:29.210702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 12:47:29.210786 ==
6291 12:47:29.214277 [Gating] SW mode calibration
6292 12:47:29.220500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6293 12:47:29.224049 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6294 12:47:29.230585 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6295 12:47:29.233971 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 12:47:29.237123 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6297 12:47:29.243747 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 12:47:29.246985 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 12:47:29.250582 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 12:47:29.257194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 12:47:29.260374 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 12:47:29.263645 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 12:47:29.266935 Total UI for P1: 0, mck2ui 16
6304 12:47:29.270667 best dqsien dly found for B0: ( 0, 14, 24)
6305 12:47:29.273604 Total UI for P1: 0, mck2ui 16
6306 12:47:29.277303 best dqsien dly found for B1: ( 0, 14, 24)
6307 12:47:29.280341 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6308 12:47:29.283791 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6309 12:47:29.283886
6310 12:47:29.290351 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6311 12:47:29.293535 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 12:47:29.296820 [Gating] SW calibration Done
6313 12:47:29.296964 ==
6314 12:47:29.300015 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 12:47:29.303556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 12:47:29.303677 ==
6317 12:47:29.303741 RX Vref Scan: 0
6318 12:47:29.303800
6319 12:47:29.306838 RX Vref 0 -> 0, step: 1
6320 12:47:29.306950
6321 12:47:29.310091 RX Delay -410 -> 252, step: 16
6322 12:47:29.313599 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6323 12:47:29.320058 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6324 12:47:29.323655 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6325 12:47:29.326744 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6326 12:47:29.329869 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6327 12:47:29.336846 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6328 12:47:29.340192 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6329 12:47:29.343307 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6330 12:47:29.346695 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6331 12:47:29.349796 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6332 12:47:29.356871 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6333 12:47:29.359967 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6334 12:47:29.363439 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6335 12:47:29.370043 iDelay=230, Bit 13, Center -35 (-266 ~ 197) 464
6336 12:47:29.373586 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6337 12:47:29.376467 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6338 12:47:29.376548 ==
6339 12:47:29.379775 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 12:47:29.383083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 12:47:29.383178 ==
6342 12:47:29.386635 DQS Delay:
6343 12:47:29.386716 DQS0 = 27, DQS1 = 43
6344 12:47:29.390136 DQM Delay:
6345 12:47:29.390216 DQM0 = 12, DQM1 = 12
6346 12:47:29.393266 DQ Delay:
6347 12:47:29.393346 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6348 12:47:29.396894 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6349 12:47:29.400042 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6350 12:47:29.403042 DQ12 =16, DQ13 =8, DQ14 =24, DQ15 =16
6351 12:47:29.403122
6352 12:47:29.403185
6353 12:47:29.403244 ==
6354 12:47:29.406882 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 12:47:29.413160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 12:47:29.413279 ==
6357 12:47:29.413389
6358 12:47:29.413498
6359 12:47:29.413603 TX Vref Scan disable
6360 12:47:29.416600 == TX Byte 0 ==
6361 12:47:29.419872 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6362 12:47:29.423040 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6363 12:47:29.426688 == TX Byte 1 ==
6364 12:47:29.430112 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6365 12:47:29.433169 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6366 12:47:29.436482 ==
6367 12:47:29.436562 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 12:47:29.443077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 12:47:29.443158 ==
6370 12:47:29.443222
6371 12:47:29.443281
6372 12:47:29.446346 TX Vref Scan disable
6373 12:47:29.446446 == TX Byte 0 ==
6374 12:47:29.449698 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 12:47:29.456549 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 12:47:29.456630 == TX Byte 1 ==
6377 12:47:29.459793 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6378 12:47:29.466190 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6379 12:47:29.466296
6380 12:47:29.466387 [DATLAT]
6381 12:47:29.466475 Freq=400, CH0 RK0
6382 12:47:29.466560
6383 12:47:29.469263 DATLAT Default: 0xf
6384 12:47:29.472883 0, 0xFFFF, sum = 0
6385 12:47:29.472965 1, 0xFFFF, sum = 0
6386 12:47:29.476225 2, 0xFFFF, sum = 0
6387 12:47:29.476324 3, 0xFFFF, sum = 0
6388 12:47:29.479221 4, 0xFFFF, sum = 0
6389 12:47:29.479302 5, 0xFFFF, sum = 0
6390 12:47:29.482618 6, 0xFFFF, sum = 0
6391 12:47:29.482701 7, 0xFFFF, sum = 0
6392 12:47:29.486077 8, 0xFFFF, sum = 0
6393 12:47:29.486158 9, 0xFFFF, sum = 0
6394 12:47:29.489532 10, 0xFFFF, sum = 0
6395 12:47:29.489613 11, 0xFFFF, sum = 0
6396 12:47:29.492611 12, 0xFFFF, sum = 0
6397 12:47:29.492693 13, 0x0, sum = 1
6398 12:47:29.495967 14, 0x0, sum = 2
6399 12:47:29.496048 15, 0x0, sum = 3
6400 12:47:29.499639 16, 0x0, sum = 4
6401 12:47:29.499748 best_step = 14
6402 12:47:29.499843
6403 12:47:29.499910 ==
6404 12:47:29.502856 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 12:47:29.509158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 12:47:29.509239 ==
6407 12:47:29.509302 RX Vref Scan: 1
6408 12:47:29.509361
6409 12:47:29.512511 RX Vref 0 -> 0, step: 1
6410 12:47:29.512615
6411 12:47:29.515820 RX Delay -327 -> 252, step: 8
6412 12:47:29.515989
6413 12:47:29.519527 Set Vref, RX VrefLevel [Byte0]: 58
6414 12:47:29.522449 [Byte1]: 48
6415 12:47:29.522529
6416 12:47:29.525862 Final RX Vref Byte 0 = 58 to rank0
6417 12:47:29.529256 Final RX Vref Byte 1 = 48 to rank0
6418 12:47:29.532674 Final RX Vref Byte 0 = 58 to rank1
6419 12:47:29.535854 Final RX Vref Byte 1 = 48 to rank1==
6420 12:47:29.539050 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 12:47:29.542450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 12:47:29.542533 ==
6423 12:47:29.545471 DQS Delay:
6424 12:47:29.545553 DQS0 = 28, DQS1 = 48
6425 12:47:29.549035 DQM Delay:
6426 12:47:29.549118 DQM0 = 12, DQM1 = 14
6427 12:47:29.552507 DQ Delay:
6428 12:47:29.552589 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6429 12:47:29.555855 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6430 12:47:29.558713 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6431 12:47:29.562451 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6432 12:47:29.562534
6433 12:47:29.562598
6434 12:47:29.572166 [DQSOSCAuto] RK0, (LSB)MR18= 0xaca4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6435 12:47:29.575600 CH0 RK0: MR19=C0C, MR18=ACA4
6436 12:47:29.578946 CH0_RK0: MR19=0xC0C, MR18=0xACA4, DQSOSC=388, MR23=63, INC=392, DEC=261
6437 12:47:29.582231 ==
6438 12:47:29.582329 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 12:47:29.589045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 12:47:29.589144 ==
6441 12:47:29.592113 [Gating] SW mode calibration
6442 12:47:29.598925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6443 12:47:29.602367 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6444 12:47:29.608747 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6445 12:47:29.612083 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 12:47:29.615624 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 12:47:29.622059 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 12:47:29.625262 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 12:47:29.628736 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 12:47:29.635338 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 12:47:29.638482 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 12:47:29.642154 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 12:47:29.645574 Total UI for P1: 0, mck2ui 16
6454 12:47:29.648884 best dqsien dly found for B0: ( 0, 14, 24)
6455 12:47:29.652058 Total UI for P1: 0, mck2ui 16
6456 12:47:29.655333 best dqsien dly found for B1: ( 0, 14, 24)
6457 12:47:29.658519 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6458 12:47:29.662222 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6459 12:47:29.662309
6460 12:47:29.665341 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6461 12:47:29.672195 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 12:47:29.672300 [Gating] SW calibration Done
6463 12:47:29.672367 ==
6464 12:47:29.675196 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 12:47:29.682008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 12:47:29.682120 ==
6467 12:47:29.682245 RX Vref Scan: 0
6468 12:47:29.682308
6469 12:47:29.685367 RX Vref 0 -> 0, step: 1
6470 12:47:29.685449
6471 12:47:29.688705 RX Delay -410 -> 252, step: 16
6472 12:47:29.692247 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6473 12:47:29.695066 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6474 12:47:29.701798 iDelay=230, Bit 2, Center -11 (-234 ~ 213) 448
6475 12:47:29.705190 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6476 12:47:29.708586 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6477 12:47:29.712122 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6478 12:47:29.718408 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6479 12:47:29.721494 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6480 12:47:29.725143 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6481 12:47:29.728286 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6482 12:47:29.734996 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6483 12:47:29.738072 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6484 12:47:29.741773 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6485 12:47:29.744775 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6486 12:47:29.751980 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6487 12:47:29.755086 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6488 12:47:29.755170 ==
6489 12:47:29.758261 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 12:47:29.761448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 12:47:29.761535 ==
6492 12:47:29.764951 DQS Delay:
6493 12:47:29.765037 DQS0 = 27, DQS1 = 43
6494 12:47:29.768370 DQM Delay:
6495 12:47:29.768472 DQM0 = 14, DQM1 = 15
6496 12:47:29.768569 DQ Delay:
6497 12:47:29.771588 DQ0 =16, DQ1 =8, DQ2 =16, DQ3 =8
6498 12:47:29.774828 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6499 12:47:29.778513 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6500 12:47:29.781413 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6501 12:47:29.781491
6502 12:47:29.781555
6503 12:47:29.781620 ==
6504 12:47:29.784939 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 12:47:29.791621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 12:47:29.791726 ==
6507 12:47:29.791816
6508 12:47:29.791878
6509 12:47:29.791936 TX Vref Scan disable
6510 12:47:29.794634 == TX Byte 0 ==
6511 12:47:29.798038 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6512 12:47:29.801526 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6513 12:47:29.805019 == TX Byte 1 ==
6514 12:47:29.808366 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6515 12:47:29.811455 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6516 12:47:29.811559 ==
6517 12:47:29.815127 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 12:47:29.821821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 12:47:29.821918 ==
6520 12:47:29.821993
6521 12:47:29.822056
6522 12:47:29.822117 TX Vref Scan disable
6523 12:47:29.825164 == TX Byte 0 ==
6524 12:47:29.828132 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6525 12:47:29.831781 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6526 12:47:29.834905 == TX Byte 1 ==
6527 12:47:29.838158 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6528 12:47:29.841551 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6529 12:47:29.841691
6530 12:47:29.844838 [DATLAT]
6531 12:47:29.844970 Freq=400, CH0 RK1
6532 12:47:29.845093
6533 12:47:29.847889 DATLAT Default: 0xe
6534 12:47:29.848019 0, 0xFFFF, sum = 0
6535 12:47:29.851696 1, 0xFFFF, sum = 0
6536 12:47:29.851833 2, 0xFFFF, sum = 0
6537 12:47:29.854643 3, 0xFFFF, sum = 0
6538 12:47:29.854782 4, 0xFFFF, sum = 0
6539 12:47:29.858168 5, 0xFFFF, sum = 0
6540 12:47:29.858299 6, 0xFFFF, sum = 0
6541 12:47:29.861187 7, 0xFFFF, sum = 0
6542 12:47:29.861321 8, 0xFFFF, sum = 0
6543 12:47:29.864541 9, 0xFFFF, sum = 0
6544 12:47:29.864671 10, 0xFFFF, sum = 0
6545 12:47:29.868197 11, 0xFFFF, sum = 0
6546 12:47:29.871200 12, 0xFFFF, sum = 0
6547 12:47:29.871288 13, 0x0, sum = 1
6548 12:47:29.871356 14, 0x0, sum = 2
6549 12:47:29.874551 15, 0x0, sum = 3
6550 12:47:29.874638 16, 0x0, sum = 4
6551 12:47:29.877893 best_step = 14
6552 12:47:29.877978
6553 12:47:29.878044 ==
6554 12:47:29.881530 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 12:47:29.884869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 12:47:29.884955 ==
6557 12:47:29.888107 RX Vref Scan: 0
6558 12:47:29.888207
6559 12:47:29.888299 RX Vref 0 -> 0, step: 1
6560 12:47:29.888396
6561 12:47:29.891090 RX Delay -327 -> 252, step: 8
6562 12:47:29.899382 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6563 12:47:29.902943 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6564 12:47:29.905929 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6565 12:47:29.912558 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6566 12:47:29.916122 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6567 12:47:29.919213 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6568 12:47:29.923016 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6569 12:47:29.925908 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6570 12:47:29.932475 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6571 12:47:29.935886 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6572 12:47:29.939550 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6573 12:47:29.942562 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6574 12:47:29.949249 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6575 12:47:29.952676 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6576 12:47:29.955776 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6577 12:47:29.962786 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6578 12:47:29.962858 ==
6579 12:47:29.965729 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 12:47:29.968993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 12:47:29.969112 ==
6582 12:47:29.969248 DQS Delay:
6583 12:47:29.972799 DQS0 = 28, DQS1 = 40
6584 12:47:29.972889 DQM Delay:
6585 12:47:29.975966 DQM0 = 10, DQM1 = 12
6586 12:47:29.976033 DQ Delay:
6587 12:47:29.978888 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6588 12:47:29.982477 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6589 12:47:29.985561 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6590 12:47:29.988923 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6591 12:47:29.989007
6592 12:47:29.989068
6593 12:47:29.995849 [DQSOSCAuto] RK1, (LSB)MR18= 0xba6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6594 12:47:29.998953 CH0 RK1: MR19=C0C, MR18=BA6E
6595 12:47:30.005661 CH0_RK1: MR19=0xC0C, MR18=0xBA6E, DQSOSC=386, MR23=63, INC=396, DEC=264
6596 12:47:30.008994 [RxdqsGatingPostProcess] freq 400
6597 12:47:30.015548 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6598 12:47:30.015667 best DQS0 dly(2T, 0.5T) = (0, 10)
6599 12:47:30.019153 best DQS1 dly(2T, 0.5T) = (0, 10)
6600 12:47:30.022518 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6601 12:47:30.025626 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6602 12:47:30.029169 best DQS0 dly(2T, 0.5T) = (0, 10)
6603 12:47:30.032230 best DQS1 dly(2T, 0.5T) = (0, 10)
6604 12:47:30.035569 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6605 12:47:30.039312 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6606 12:47:30.042378 Pre-setting of DQS Precalculation
6607 12:47:30.045571 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6608 12:47:30.049149 ==
6609 12:47:30.049261 Dram Type= 6, Freq= 0, CH_1, rank 0
6610 12:47:30.055693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 12:47:30.055778 ==
6612 12:47:30.058792 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6613 12:47:30.065673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6614 12:47:30.069123 [CA 0] Center 36 (8~64) winsize 57
6615 12:47:30.072315 [CA 1] Center 36 (8~64) winsize 57
6616 12:47:30.075631 [CA 2] Center 36 (8~64) winsize 57
6617 12:47:30.078911 [CA 3] Center 36 (8~64) winsize 57
6618 12:47:30.082025 [CA 4] Center 36 (8~64) winsize 57
6619 12:47:30.085390 [CA 5] Center 36 (8~64) winsize 57
6620 12:47:30.085464
6621 12:47:30.088796 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6622 12:47:30.088897
6623 12:47:30.091916 [CATrainingPosCal] consider 1 rank data
6624 12:47:30.095427 u2DelayCellTimex100 = 270/100 ps
6625 12:47:30.098530 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 12:47:30.102315 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 12:47:30.105271 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 12:47:30.109379 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 12:47:30.115092 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 12:47:30.118541 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 12:47:30.118628
6632 12:47:30.121878 CA PerBit enable=1, Macro0, CA PI delay=36
6633 12:47:30.121976
6634 12:47:30.125443 [CBTSetCACLKResult] CA Dly = 36
6635 12:47:30.125526 CS Dly: 1 (0~32)
6636 12:47:30.125603 ==
6637 12:47:30.128785 Dram Type= 6, Freq= 0, CH_1, rank 1
6638 12:47:30.135066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 12:47:30.135167 ==
6640 12:47:30.138413 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6641 12:47:30.145232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6642 12:47:30.148357 [CA 0] Center 36 (8~64) winsize 57
6643 12:47:30.151993 [CA 1] Center 36 (8~64) winsize 57
6644 12:47:30.155353 [CA 2] Center 36 (8~64) winsize 57
6645 12:47:30.158221 [CA 3] Center 36 (8~64) winsize 57
6646 12:47:30.161804 [CA 4] Center 36 (8~64) winsize 57
6647 12:47:30.164956 [CA 5] Center 36 (8~64) winsize 57
6648 12:47:30.165078
6649 12:47:30.168504 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6650 12:47:30.168607
6651 12:47:30.171641 [CATrainingPosCal] consider 2 rank data
6652 12:47:30.175259 u2DelayCellTimex100 = 270/100 ps
6653 12:47:30.178419 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 12:47:30.181609 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 12:47:30.185200 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 12:47:30.188399 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 12:47:30.191502 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 12:47:30.195077 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 12:47:30.195172
6660 12:47:30.201776 CA PerBit enable=1, Macro0, CA PI delay=36
6661 12:47:30.201972
6662 12:47:30.202088 [CBTSetCACLKResult] CA Dly = 36
6663 12:47:30.204951 CS Dly: 1 (0~32)
6664 12:47:30.205071
6665 12:47:30.208122 ----->DramcWriteLeveling(PI) begin...
6666 12:47:30.208236 ==
6667 12:47:30.212049 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 12:47:30.214993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 12:47:30.215108 ==
6670 12:47:30.218042 Write leveling (Byte 0): 40 => 8
6671 12:47:30.221660 Write leveling (Byte 1): 32 => 0
6672 12:47:30.225218 DramcWriteLeveling(PI) end<-----
6673 12:47:30.225331
6674 12:47:30.225426 ==
6675 12:47:30.228255 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 12:47:30.231662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 12:47:30.231774 ==
6678 12:47:30.234744 [Gating] SW mode calibration
6679 12:47:30.241244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6680 12:47:30.248131 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6681 12:47:30.251520 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6682 12:47:30.257965 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 12:47:30.261682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 12:47:30.264777 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 12:47:30.271642 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 12:47:30.274796 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 12:47:30.278499 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 12:47:30.284849 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 12:47:30.288314 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 12:47:30.291224 Total UI for P1: 0, mck2ui 16
6691 12:47:30.294627 best dqsien dly found for B0: ( 0, 14, 24)
6692 12:47:30.298234 Total UI for P1: 0, mck2ui 16
6693 12:47:30.301420 best dqsien dly found for B1: ( 0, 14, 24)
6694 12:47:30.304638 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6695 12:47:30.308292 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6696 12:47:30.308378
6697 12:47:30.311400 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6698 12:47:30.314748 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 12:47:30.317834 [Gating] SW calibration Done
6700 12:47:30.317935 ==
6701 12:47:30.321272 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 12:47:30.324503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 12:47:30.324612 ==
6704 12:47:30.328330 RX Vref Scan: 0
6705 12:47:30.328434
6706 12:47:30.331176 RX Vref 0 -> 0, step: 1
6707 12:47:30.331289
6708 12:47:30.331410 RX Delay -410 -> 252, step: 16
6709 12:47:30.338217 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6710 12:47:30.341303 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6711 12:47:30.344835 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6712 12:47:30.347887 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6713 12:47:30.354738 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6714 12:47:30.357792 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6715 12:47:30.361378 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6716 12:47:30.364642 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6717 12:47:30.370896 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6718 12:47:30.374730 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6719 12:47:30.377837 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6720 12:47:30.384393 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6721 12:47:30.387914 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6722 12:47:30.391389 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6723 12:47:30.394382 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6724 12:47:30.401188 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6725 12:47:30.401327 ==
6726 12:47:30.404448 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 12:47:30.407516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 12:47:30.407638 ==
6729 12:47:30.407781 DQS Delay:
6730 12:47:30.411252 DQS0 = 27, DQS1 = 43
6731 12:47:30.411369 DQM Delay:
6732 12:47:30.414311 DQM0 = 5, DQM1 = 15
6733 12:47:30.414428 DQ Delay:
6734 12:47:30.417960 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6735 12:47:30.421232 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6736 12:47:30.424287 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6737 12:47:30.427560 DQ12 =32, DQ13 =16, DQ14 =16, DQ15 =24
6738 12:47:30.427685
6739 12:47:30.427798
6740 12:47:30.427908 ==
6741 12:47:30.430686 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 12:47:30.434339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 12:47:30.434443 ==
6744 12:47:30.434535
6745 12:47:30.434624
6746 12:47:30.437606 TX Vref Scan disable
6747 12:47:30.437703 == TX Byte 0 ==
6748 12:47:30.444590 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6749 12:47:30.447478 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6750 12:47:30.447563 == TX Byte 1 ==
6751 12:47:30.454263 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6752 12:47:30.457940 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6753 12:47:30.458019 ==
6754 12:47:30.460914 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 12:47:30.464460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 12:47:30.464561 ==
6757 12:47:30.464652
6758 12:47:30.464748
6759 12:47:30.467577 TX Vref Scan disable
6760 12:47:30.470856 == TX Byte 0 ==
6761 12:47:30.474097 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 12:47:30.477450 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 12:47:30.477554 == TX Byte 1 ==
6764 12:47:30.484279 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6765 12:47:30.487416 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6766 12:47:30.487526
6767 12:47:30.487618 [DATLAT]
6768 12:47:30.490791 Freq=400, CH1 RK0
6769 12:47:30.490889
6770 12:47:30.490979 DATLAT Default: 0xf
6771 12:47:30.494531 0, 0xFFFF, sum = 0
6772 12:47:30.494618 1, 0xFFFF, sum = 0
6773 12:47:30.497510 2, 0xFFFF, sum = 0
6774 12:47:30.497610 3, 0xFFFF, sum = 0
6775 12:47:30.500833 4, 0xFFFF, sum = 0
6776 12:47:30.500919 5, 0xFFFF, sum = 0
6777 12:47:30.504349 6, 0xFFFF, sum = 0
6778 12:47:30.507678 7, 0xFFFF, sum = 0
6779 12:47:30.507790 8, 0xFFFF, sum = 0
6780 12:47:30.510782 9, 0xFFFF, sum = 0
6781 12:47:30.510896 10, 0xFFFF, sum = 0
6782 12:47:30.514578 11, 0xFFFF, sum = 0
6783 12:47:30.514655 12, 0xFFFF, sum = 0
6784 12:47:30.517568 13, 0x0, sum = 1
6785 12:47:30.517642 14, 0x0, sum = 2
6786 12:47:30.521023 15, 0x0, sum = 3
6787 12:47:30.521096 16, 0x0, sum = 4
6788 12:47:30.524070 best_step = 14
6789 12:47:30.524227
6790 12:47:30.524369 ==
6791 12:47:30.527792 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 12:47:30.530982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 12:47:30.531107 ==
6794 12:47:30.531253 RX Vref Scan: 1
6795 12:47:30.531375
6796 12:47:30.534306 RX Vref 0 -> 0, step: 1
6797 12:47:30.534393
6798 12:47:30.537684 RX Delay -327 -> 252, step: 8
6799 12:47:30.537809
6800 12:47:30.540823 Set Vref, RX VrefLevel [Byte0]: 53
6801 12:47:30.543804 [Byte1]: 53
6802 12:47:30.547819
6803 12:47:30.547936 Final RX Vref Byte 0 = 53 to rank0
6804 12:47:30.551307 Final RX Vref Byte 1 = 53 to rank0
6805 12:47:30.554486 Final RX Vref Byte 0 = 53 to rank1
6806 12:47:30.557830 Final RX Vref Byte 1 = 53 to rank1==
6807 12:47:30.561365 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 12:47:30.567867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 12:47:30.567953 ==
6810 12:47:30.568084 DQS Delay:
6811 12:47:30.571012 DQS0 = 28, DQS1 = 40
6812 12:47:30.571113 DQM Delay:
6813 12:47:30.571216 DQM0 = 8, DQM1 = 12
6814 12:47:30.574296 DQ Delay:
6815 12:47:30.577545 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6816 12:47:30.577631 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6817 12:47:30.580939 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6818 12:47:30.584543 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6819 12:47:30.584644
6820 12:47:30.584747
6821 12:47:30.594275 [DQSOSCAuto] RK0, (LSB)MR18= 0x90cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6822 12:47:30.597396 CH1 RK0: MR19=C0C, MR18=90CB
6823 12:47:30.604038 CH1_RK0: MR19=0xC0C, MR18=0x90CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6824 12:47:30.604152 ==
6825 12:47:30.607290 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 12:47:30.610764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 12:47:30.610864 ==
6828 12:47:30.614478 [Gating] SW mode calibration
6829 12:47:30.620958 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6830 12:47:30.981072 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6831 12:47:30.981543 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6832 12:47:30.981729 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6833 12:47:30.981879 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6834 12:47:30.981971 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 12:47:30.982088 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 12:47:30.982186 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 12:47:30.982291 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 12:47:30.982399 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 12:47:30.982511 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 12:47:30.982623 Total UI for P1: 0, mck2ui 16
6841 12:47:30.982735 best dqsien dly found for B0: ( 0, 14, 24)
6842 12:47:30.982848 Total UI for P1: 0, mck2ui 16
6843 12:47:30.982962 best dqsien dly found for B1: ( 0, 14, 24)
6844 12:47:30.983073 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6845 12:47:30.983183 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6846 12:47:30.983293
6847 12:47:30.983403 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6848 12:47:30.983513 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 12:47:30.983621 [Gating] SW calibration Done
6850 12:47:30.983729 ==
6851 12:47:30.983839 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 12:47:30.983947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 12:47:30.984060 ==
6854 12:47:30.984175 RX Vref Scan: 0
6855 12:47:30.984278
6856 12:47:30.984378 RX Vref 0 -> 0, step: 1
6857 12:47:30.984490
6858 12:47:30.984591 RX Delay -410 -> 252, step: 16
6859 12:47:30.984700 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6860 12:47:30.984811 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6861 12:47:30.984921 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6862 12:47:30.985030 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6863 12:47:30.985139 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6864 12:47:30.985253 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6865 12:47:30.985363 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6866 12:47:30.985473 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6867 12:47:30.985611 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6868 12:47:30.985747 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6869 12:47:30.985900 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6870 12:47:30.986028 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6871 12:47:30.986152 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6872 12:47:30.986286 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6873 12:47:30.986376 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6874 12:47:30.986478 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6875 12:47:30.986580 ==
6876 12:47:30.986685 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 12:47:30.986791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 12:47:30.986884 ==
6879 12:47:30.986985 DQS Delay:
6880 12:47:30.987078 DQS0 = 35, DQS1 = 43
6881 12:47:30.987182 DQM Delay:
6882 12:47:30.987251 DQM0 = 16, DQM1 = 18
6883 12:47:30.987322 DQ Delay:
6884 12:47:30.987379 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6885 12:47:30.987436 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6886 12:47:30.987496 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6887 12:47:30.987560 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6888 12:47:30.987616
6889 12:47:30.987671
6890 12:47:30.987726 ==
6891 12:47:30.987798 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 12:47:30.987855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 12:47:30.987911 ==
6894 12:47:30.987967
6895 12:47:30.988039
6896 12:47:30.988096 TX Vref Scan disable
6897 12:47:30.988151 == TX Byte 0 ==
6898 12:47:30.988205 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6899 12:47:30.988272 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6900 12:47:30.988330 == TX Byte 1 ==
6901 12:47:30.988385 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6902 12:47:30.988440 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6903 12:47:30.988503 ==
6904 12:47:30.988564 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 12:47:30.988620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 12:47:30.988675 ==
6907 12:47:30.988730
6908 12:47:30.988809
6909 12:47:30.988865 TX Vref Scan disable
6910 12:47:30.988934 == TX Byte 0 ==
6911 12:47:30.988993 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6912 12:47:30.989055 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6913 12:47:30.989109 == TX Byte 1 ==
6914 12:47:30.989179 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6915 12:47:30.989259 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6916 12:47:30.989344
6917 12:47:30.989426 [DATLAT]
6918 12:47:30.989516 Freq=400, CH1 RK1
6919 12:47:30.989600
6920 12:47:30.989682 DATLAT Default: 0xe
6921 12:47:30.989772 0, 0xFFFF, sum = 0
6922 12:47:30.989858 1, 0xFFFF, sum = 0
6923 12:47:30.989996 2, 0xFFFF, sum = 0
6924 12:47:30.990090 3, 0xFFFF, sum = 0
6925 12:47:30.990146 4, 0xFFFF, sum = 0
6926 12:47:30.990215 5, 0xFFFF, sum = 0
6927 12:47:30.990285 6, 0xFFFF, sum = 0
6928 12:47:30.990341 7, 0xFFFF, sum = 0
6929 12:47:30.990395 8, 0xFFFF, sum = 0
6930 12:47:30.990449 9, 0xFFFF, sum = 0
6931 12:47:30.990519 10, 0xFFFF, sum = 0
6932 12:47:30.990575 11, 0xFFFF, sum = 0
6933 12:47:30.990630 12, 0xFFFF, sum = 0
6934 12:47:30.990684 13, 0x0, sum = 1
6935 12:47:30.990754 14, 0x0, sum = 2
6936 12:47:30.990810 15, 0x0, sum = 3
6937 12:47:30.990865 16, 0x0, sum = 4
6938 12:47:30.990919 best_step = 14
6939 12:47:30.990983
6940 12:47:30.991038 ==
6941 12:47:30.991091 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 12:47:30.991145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 12:47:30.991204 ==
6944 12:47:30.991265 RX Vref Scan: 0
6945 12:47:30.991318
6946 12:47:30.991371 RX Vref 0 -> 0, step: 1
6947 12:47:30.991424
6948 12:47:30.991510 RX Delay -327 -> 252, step: 8
6949 12:47:30.991595 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6950 12:47:30.991679 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6951 12:47:30.991770 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6952 12:47:30.991854 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6953 12:47:30.991945 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6954 12:47:30.992031 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6955 12:47:30.992114 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6956 12:47:30.992204 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6957 12:47:30.992289 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6958 12:47:30.992372 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6959 12:47:30.992462 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6960 12:47:30.992547 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6961 12:47:30.992630 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6962 12:47:30.992739 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6963 12:47:30.992835 iDelay=217, Bit 14, Center -24 (-255 ~ 208) 464
6964 12:47:30.993116 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6965 12:47:30.993210 ==
6966 12:47:30.993294 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 12:47:30.993367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 12:47:30.993438 ==
6969 12:47:30.993493 DQS Delay:
6970 12:47:30.995965 DQS0 = 32, DQS1 = 36
6971 12:47:30.996079 DQM Delay:
6972 12:47:30.999146 DQM0 = 11, DQM1 = 10
6973 12:47:30.999254 DQ Delay:
6974 12:47:31.002458 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
6975 12:47:31.005932 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
6976 12:47:31.009090 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6977 12:47:31.012705 DQ12 =16, DQ13 =16, DQ14 =12, DQ15 =20
6978 12:47:31.012859
6979 12:47:31.012970
6980 12:47:31.019171 [DQSOSCAuto] RK1, (LSB)MR18= 0xa850, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6981 12:47:31.022895 CH1 RK1: MR19=C0C, MR18=A850
6982 12:47:31.029291 CH1_RK1: MR19=0xC0C, MR18=0xA850, DQSOSC=388, MR23=63, INC=392, DEC=261
6983 12:47:31.033020 [RxdqsGatingPostProcess] freq 400
6984 12:47:31.036045 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6985 12:47:31.039314 best DQS0 dly(2T, 0.5T) = (0, 10)
6986 12:47:31.042426 best DQS1 dly(2T, 0.5T) = (0, 10)
6987 12:47:31.045691 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6988 12:47:31.048990 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6989 12:47:31.052720 best DQS0 dly(2T, 0.5T) = (0, 10)
6990 12:47:31.055859 best DQS1 dly(2T, 0.5T) = (0, 10)
6991 12:47:31.059260 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6992 12:47:31.062590 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6993 12:47:31.065767 Pre-setting of DQS Precalculation
6994 12:47:31.069236 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6995 12:47:31.079420 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6996 12:47:31.086098 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6997 12:47:31.086182
6998 12:47:31.086246
6999 12:47:31.089290 [Calibration Summary] 800 Mbps
7000 12:47:31.089400 CH 0, Rank 0
7001 12:47:31.092928 SW Impedance : PASS
7002 12:47:31.093019 DUTY Scan : NO K
7003 12:47:31.096142 ZQ Calibration : PASS
7004 12:47:31.099165 Jitter Meter : NO K
7005 12:47:31.099274 CBT Training : PASS
7006 12:47:31.102526 Write leveling : PASS
7007 12:47:31.102638 RX DQS gating : PASS
7008 12:47:31.105897 RX DQ/DQS(RDDQC) : PASS
7009 12:47:31.109002 TX DQ/DQS : PASS
7010 12:47:31.109086 RX DATLAT : PASS
7011 12:47:31.112644 RX DQ/DQS(Engine): PASS
7012 12:47:31.115885 TX OE : NO K
7013 12:47:31.116010 All Pass.
7014 12:47:31.116123
7015 12:47:31.116285 CH 0, Rank 1
7016 12:47:31.118930 SW Impedance : PASS
7017 12:47:31.122477 DUTY Scan : NO K
7018 12:47:31.122620 ZQ Calibration : PASS
7019 12:47:31.125901 Jitter Meter : NO K
7020 12:47:31.128995 CBT Training : PASS
7021 12:47:31.129078 Write leveling : NO K
7022 12:47:31.132233 RX DQS gating : PASS
7023 12:47:31.135555 RX DQ/DQS(RDDQC) : PASS
7024 12:47:31.135637 TX DQ/DQS : PASS
7025 12:47:31.139002 RX DATLAT : PASS
7026 12:47:31.142198 RX DQ/DQS(Engine): PASS
7027 12:47:31.142280 TX OE : NO K
7028 12:47:31.142346 All Pass.
7029 12:47:31.145690
7030 12:47:31.145773 CH 1, Rank 0
7031 12:47:31.149053 SW Impedance : PASS
7032 12:47:31.149179 DUTY Scan : NO K
7033 12:47:31.152228 ZQ Calibration : PASS
7034 12:47:31.152350 Jitter Meter : NO K
7035 12:47:31.155403 CBT Training : PASS
7036 12:47:31.159135 Write leveling : PASS
7037 12:47:31.159255 RX DQS gating : PASS
7038 12:47:31.162338 RX DQ/DQS(RDDQC) : PASS
7039 12:47:31.165419 TX DQ/DQS : PASS
7040 12:47:31.165538 RX DATLAT : PASS
7041 12:47:31.168652 RX DQ/DQS(Engine): PASS
7042 12:47:31.172061 TX OE : NO K
7043 12:47:31.172179 All Pass.
7044 12:47:31.172318
7045 12:47:31.172425 CH 1, Rank 1
7046 12:47:31.175521 SW Impedance : PASS
7047 12:47:31.178912 DUTY Scan : NO K
7048 12:47:31.179033 ZQ Calibration : PASS
7049 12:47:31.182448 Jitter Meter : NO K
7050 12:47:31.185326 CBT Training : PASS
7051 12:47:31.185445 Write leveling : NO K
7052 12:47:31.188767 RX DQS gating : PASS
7053 12:47:31.192345 RX DQ/DQS(RDDQC) : PASS
7054 12:47:31.192465 TX DQ/DQS : PASS
7055 12:47:31.195647 RX DATLAT : PASS
7056 12:47:31.195765 RX DQ/DQS(Engine): PASS
7057 12:47:31.199008 TX OE : NO K
7058 12:47:31.199130 All Pass.
7059 12:47:31.199245
7060 12:47:31.202057 DramC Write-DBI off
7061 12:47:31.205562 PER_BANK_REFRESH: Hybrid Mode
7062 12:47:31.205685 TX_TRACKING: ON
7063 12:47:31.215773 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7064 12:47:31.218901 [FAST_K] Save calibration result to emmc
7065 12:47:31.222416 dramc_set_vcore_voltage set vcore to 725000
7066 12:47:31.225675 Read voltage for 1600, 0
7067 12:47:31.225777 Vio18 = 0
7068 12:47:31.228913 Vcore = 725000
7069 12:47:31.228996 Vdram = 0
7070 12:47:31.229061 Vddq = 0
7071 12:47:31.229122 Vmddr = 0
7072 12:47:31.235683 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7073 12:47:31.239080 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7074 12:47:31.242132 MEM_TYPE=3, freq_sel=13
7075 12:47:31.245273 sv_algorithm_assistance_LP4_3733
7076 12:47:31.248936 ============ PULL DRAM RESETB DOWN ============
7077 12:47:31.255488 ========== PULL DRAM RESETB DOWN end =========
7078 12:47:31.258615 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7079 12:47:31.262221 ===================================
7080 12:47:31.265603 LPDDR4 DRAM CONFIGURATION
7081 12:47:31.268858 ===================================
7082 12:47:31.268972 EX_ROW_EN[0] = 0x0
7083 12:47:31.271949 EX_ROW_EN[1] = 0x0
7084 12:47:31.272067 LP4Y_EN = 0x0
7085 12:47:31.275266 WORK_FSP = 0x1
7086 12:47:31.275463 WL = 0x5
7087 12:47:31.278624 RL = 0x5
7088 12:47:31.278744 BL = 0x2
7089 12:47:31.281983 RPST = 0x0
7090 12:47:31.282106 RD_PRE = 0x0
7091 12:47:31.285408 WR_PRE = 0x1
7092 12:47:31.288676 WR_PST = 0x1
7093 12:47:31.288814 DBI_WR = 0x0
7094 12:47:31.291856 DBI_RD = 0x0
7095 12:47:31.291979 OTF = 0x1
7096 12:47:31.295355 ===================================
7097 12:47:31.298495 ===================================
7098 12:47:31.298615 ANA top config
7099 12:47:31.301916 ===================================
7100 12:47:31.305535 DLL_ASYNC_EN = 0
7101 12:47:31.309061 ALL_SLAVE_EN = 0
7102 12:47:31.311777 NEW_RANK_MODE = 1
7103 12:47:31.315408 DLL_IDLE_MODE = 1
7104 12:47:31.315548 LP45_APHY_COMB_EN = 1
7105 12:47:31.318578 TX_ODT_DIS = 0
7106 12:47:31.322287 NEW_8X_MODE = 1
7107 12:47:31.325109 ===================================
7108 12:47:31.328539 ===================================
7109 12:47:31.331958 data_rate = 3200
7110 12:47:31.335054 CKR = 1
7111 12:47:31.335217 DQ_P2S_RATIO = 8
7112 12:47:31.338410 ===================================
7113 12:47:31.341611 CA_P2S_RATIO = 8
7114 12:47:31.345354 DQ_CA_OPEN = 0
7115 12:47:31.348367 DQ_SEMI_OPEN = 0
7116 12:47:31.351773 CA_SEMI_OPEN = 0
7117 12:47:31.355329 CA_FULL_RATE = 0
7118 12:47:31.355454 DQ_CKDIV4_EN = 0
7119 12:47:31.358444 CA_CKDIV4_EN = 0
7120 12:47:31.361778 CA_PREDIV_EN = 0
7121 12:47:31.365092 PH8_DLY = 12
7122 12:47:31.368420 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7123 12:47:31.371566 DQ_AAMCK_DIV = 4
7124 12:47:31.371694 CA_AAMCK_DIV = 4
7125 12:47:31.375144 CA_ADMCK_DIV = 4
7126 12:47:31.378523 DQ_TRACK_CA_EN = 0
7127 12:47:31.381946 CA_PICK = 1600
7128 12:47:31.385335 CA_MCKIO = 1600
7129 12:47:31.388502 MCKIO_SEMI = 0
7130 12:47:31.392242 PLL_FREQ = 3068
7131 12:47:31.392374 DQ_UI_PI_RATIO = 32
7132 12:47:31.395374 CA_UI_PI_RATIO = 0
7133 12:47:31.398359 ===================================
7134 12:47:31.401934 ===================================
7135 12:47:31.405649 memory_type:LPDDR4
7136 12:47:31.408443 GP_NUM : 10
7137 12:47:31.408576 SRAM_EN : 1
7138 12:47:31.493392 MD32_EN : 0
7139 12:47:31.493551 ===================================
7140 12:47:31.493651 [ANA_INIT] >>>>>>>>>>>>>>
7141 12:47:31.493732 <<<<<< [CONFIGURE PHASE]: ANA_TX
7142 12:47:31.493817 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7143 12:47:31.493895 ===================================
7144 12:47:31.493971 data_rate = 3200,PCW = 0X7600
7145 12:47:31.494075 ===================================
7146 12:47:31.494173 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7147 12:47:31.494277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7148 12:47:31.494374 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 12:47:31.494470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7150 12:47:31.494574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7151 12:47:31.494669 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7152 12:47:31.494770 [ANA_INIT] flow start
7153 12:47:31.494864 [ANA_INIT] PLL >>>>>>>>
7154 12:47:31.494967 [ANA_INIT] PLL <<<<<<<<
7155 12:47:31.495067 [ANA_INIT] MIDPI >>>>>>>>
7156 12:47:31.495154 [ANA_INIT] MIDPI <<<<<<<<
7157 12:47:31.495245 [ANA_INIT] DLL >>>>>>>>
7158 12:47:31.495330 [ANA_INIT] DLL <<<<<<<<
7159 12:47:31.495414 [ANA_INIT] flow end
7160 12:47:31.495506 ============ LP4 DIFF to SE enter ============
7161 12:47:31.495592 ============ LP4 DIFF to SE exit ============
7162 12:47:31.495677 [ANA_INIT] <<<<<<<<<<<<<
7163 12:47:31.495768 [Flow] Enable top DCM control >>>>>
7164 12:47:31.495853 [Flow] Enable top DCM control <<<<<
7165 12:47:31.496131 Enable DLL master slave shuffle
7166 12:47:31.501480 ==============================================================
7167 12:47:31.504830 Gating Mode config
7168 12:47:31.508579 ==============================================================
7169 12:47:31.511559 Config description:
7170 12:47:31.521722 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7171 12:47:31.527970 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7172 12:47:31.531423 SELPH_MODE 0: By rank 1: By Phase
7173 12:47:31.537992 ==============================================================
7174 12:47:31.541448 GAT_TRACK_EN = 1
7175 12:47:31.544903 RX_GATING_MODE = 2
7176 12:47:31.544998 RX_GATING_TRACK_MODE = 2
7177 12:47:31.548041 SELPH_MODE = 1
7178 12:47:31.551793 PICG_EARLY_EN = 1
7179 12:47:31.555035 VALID_LAT_VALUE = 1
7180 12:47:31.561469 ==============================================================
7181 12:47:31.564664 Enter into Gating configuration >>>>
7182 12:47:31.567940 Exit from Gating configuration <<<<
7183 12:47:31.571649 Enter into DVFS_PRE_config >>>>>
7184 12:47:31.581270 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7185 12:47:31.584839 Exit from DVFS_PRE_config <<<<<
7186 12:47:31.588151 Enter into PICG configuration >>>>
7187 12:47:31.591244 Exit from PICG configuration <<<<
7188 12:47:31.594568 [RX_INPUT] configuration >>>>>
7189 12:47:31.598269 [RX_INPUT] configuration <<<<<
7190 12:47:31.601410 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7191 12:47:31.607924 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7192 12:47:31.614505 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 12:47:31.621416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 12:47:31.624696 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7195 12:47:31.631660 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7196 12:47:31.634807 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7197 12:47:31.641138 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7198 12:47:31.644693 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7199 12:47:31.647825 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7200 12:47:31.651391 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7201 12:47:31.657799 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 12:47:31.661306 ===================================
7203 12:47:31.661411 LPDDR4 DRAM CONFIGURATION
7204 12:47:31.664315 ===================================
7205 12:47:31.667991 EX_ROW_EN[0] = 0x0
7206 12:47:31.671273 EX_ROW_EN[1] = 0x0
7207 12:47:31.671378 LP4Y_EN = 0x0
7208 12:47:31.674362 WORK_FSP = 0x1
7209 12:47:31.674455 WL = 0x5
7210 12:47:31.677679 RL = 0x5
7211 12:47:31.677773 BL = 0x2
7212 12:47:31.681067 RPST = 0x0
7213 12:47:31.681162 RD_PRE = 0x0
7214 12:47:31.684395 WR_PRE = 0x1
7215 12:47:31.684528 WR_PST = 0x1
7216 12:47:31.687710 DBI_WR = 0x0
7217 12:47:31.687830 DBI_RD = 0x0
7218 12:47:31.691058 OTF = 0x1
7219 12:47:31.694322 ===================================
7220 12:47:31.697826 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7221 12:47:31.701039 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7222 12:47:31.707570 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7223 12:47:31.710953 ===================================
7224 12:47:31.711087 LPDDR4 DRAM CONFIGURATION
7225 12:47:31.713963 ===================================
7226 12:47:31.717624 EX_ROW_EN[0] = 0x10
7227 12:47:31.720738 EX_ROW_EN[1] = 0x0
7228 12:47:31.720864 LP4Y_EN = 0x0
7229 12:47:31.724346 WORK_FSP = 0x1
7230 12:47:31.724486 WL = 0x5
7231 12:47:31.727400 RL = 0x5
7232 12:47:31.727491 BL = 0x2
7233 12:47:31.730975 RPST = 0x0
7234 12:47:31.731073 RD_PRE = 0x0
7235 12:47:31.734125 WR_PRE = 0x1
7236 12:47:31.734218 WR_PST = 0x1
7237 12:47:31.737393 DBI_WR = 0x0
7238 12:47:31.737491 DBI_RD = 0x0
7239 12:47:31.740933 OTF = 0x1
7240 12:47:31.744211 ===================================
7241 12:47:31.750949 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7242 12:47:31.751117 ==
7243 12:47:31.754018 Dram Type= 6, Freq= 0, CH_0, rank 0
7244 12:47:31.757147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7245 12:47:31.757287 ==
7246 12:47:31.760515 [Duty_Offset_Calibration]
7247 12:47:31.760632 B0:2 B1:0 CA:1
7248 12:47:31.760727
7249 12:47:31.764232 [DutyScan_Calibration_Flow] k_type=0
7250 12:47:31.773705
7251 12:47:31.773876 ==CLK 0==
7252 12:47:31.776868 Final CLK duty delay cell = -4
7253 12:47:31.780638 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7254 12:47:31.783727 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7255 12:47:31.786927 [-4] AVG Duty = 4937%(X100)
7256 12:47:31.787056
7257 12:47:31.790611 CH0 CLK Duty spec in!! Max-Min= 187%
7258 12:47:31.793420 [DutyScan_Calibration_Flow] ====Done====
7259 12:47:31.793543
7260 12:47:31.796648 [DutyScan_Calibration_Flow] k_type=1
7261 12:47:31.813185
7262 12:47:31.813338 ==DQS 0 ==
7263 12:47:31.816581 Final DQS duty delay cell = 0
7264 12:47:31.819652 [0] MAX Duty = 5249%(X100), DQS PI = 32
7265 12:47:31.823049 [0] MIN Duty = 4969%(X100), DQS PI = 0
7266 12:47:31.823202 [0] AVG Duty = 5109%(X100)
7267 12:47:31.826368
7268 12:47:31.826509 ==DQS 1 ==
7269 12:47:31.829494 Final DQS duty delay cell = -4
7270 12:47:31.832907 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7271 12:47:31.836428 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7272 12:47:31.839411 [-4] AVG Duty = 5000%(X100)
7273 12:47:31.839540
7274 12:47:31.843212 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7275 12:47:31.843357
7276 12:47:31.846396 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7277 12:47:31.849747 [DutyScan_Calibration_Flow] ====Done====
7278 12:47:31.849908
7279 12:47:31.852649 [DutyScan_Calibration_Flow] k_type=3
7280 12:47:31.869610
7281 12:47:31.869763 ==DQM 0 ==
7282 12:47:31.873328 Final DQM duty delay cell = 0
7283 12:47:31.876372 [0] MAX Duty = 5093%(X100), DQS PI = 26
7284 12:47:31.879742 [0] MIN Duty = 4844%(X100), DQS PI = 2
7285 12:47:31.879882 [0] AVG Duty = 4968%(X100)
7286 12:47:31.882871
7287 12:47:31.882998 ==DQM 1 ==
7288 12:47:31.886144 Final DQM duty delay cell = -4
7289 12:47:31.889789 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7290 12:47:31.893042 [-4] MIN Duty = 4751%(X100), DQS PI = 10
7291 12:47:31.896217 [-4] AVG Duty = 4891%(X100)
7292 12:47:31.896337
7293 12:47:31.899851 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7294 12:47:31.899987
7295 12:47:31.903160 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7296 12:47:31.906475 [DutyScan_Calibration_Flow] ====Done====
7297 12:47:31.906575
7298 12:47:31.909751 [DutyScan_Calibration_Flow] k_type=2
7299 12:47:31.928097
7300 12:47:31.928246 ==DQ 0 ==
7301 12:47:31.931485 Final DQ duty delay cell = 0
7302 12:47:31.934615 [0] MAX Duty = 5124%(X100), DQS PI = 34
7303 12:47:31.938235 [0] MIN Duty = 5000%(X100), DQS PI = 0
7304 12:47:31.938393 [0] AVG Duty = 5062%(X100)
7305 12:47:31.938492
7306 12:47:31.941361 ==DQ 1 ==
7307 12:47:31.941451 Final DQ duty delay cell = 4
7308 12:47:31.947928 [4] MAX Duty = 5125%(X100), DQS PI = 2
7309 12:47:31.951206 [4] MIN Duty = 5062%(X100), DQS PI = 0
7310 12:47:31.951344 [4] AVG Duty = 5093%(X100)
7311 12:47:31.951445
7312 12:47:31.954597 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7313 12:47:31.954723
7314 12:47:31.957983 CH0 DQ 1 Duty spec in!! Max-Min= 63%
7315 12:47:31.961466 [DutyScan_Calibration_Flow] ====Done====
7316 12:47:31.965049 ==
7317 12:47:31.968267 Dram Type= 6, Freq= 0, CH_1, rank 0
7318 12:47:31.971566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7319 12:47:31.971714 ==
7320 12:47:31.974696 [Duty_Offset_Calibration]
7321 12:47:31.974844 B0:0 B1:-1 CA:2
7322 12:47:31.974955
7323 12:47:31.977771 [DutyScan_Calibration_Flow] k_type=0
7324 12:47:31.987981
7325 12:47:31.988164 ==CLK 0==
7326 12:47:31.991214 Final CLK duty delay cell = 0
7327 12:47:31.994498 [0] MAX Duty = 5156%(X100), DQS PI = 10
7328 12:47:31.998129 [0] MIN Duty = 4938%(X100), DQS PI = 44
7329 12:47:32.001267 [0] AVG Duty = 5047%(X100)
7330 12:47:32.001387
7331 12:47:32.004587 CH1 CLK Duty spec in!! Max-Min= 218%
7332 12:47:32.007752 [DutyScan_Calibration_Flow] ====Done====
7333 12:47:32.007889
7334 12:47:32.010868 [DutyScan_Calibration_Flow] k_type=1
7335 12:47:32.027803
7336 12:47:32.027989 ==DQS 0 ==
7337 12:47:32.031279 Final DQS duty delay cell = 0
7338 12:47:32.034389 [0] MAX Duty = 5124%(X100), DQS PI = 26
7339 12:47:32.037561 [0] MIN Duty = 4969%(X100), DQS PI = 2
7340 12:47:32.037660 [0] AVG Duty = 5046%(X100)
7341 12:47:32.040831
7342 12:47:32.040912 ==DQS 1 ==
7343 12:47:32.044315 Final DQS duty delay cell = 0
7344 12:47:32.047448 [0] MAX Duty = 5187%(X100), DQS PI = 0
7345 12:47:32.051011 [0] MIN Duty = 4844%(X100), DQS PI = 32
7346 12:47:32.051110 [0] AVG Duty = 5015%(X100)
7347 12:47:32.054065
7348 12:47:32.057725 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7349 12:47:32.057820
7350 12:47:32.060609 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7351 12:47:32.064038 [DutyScan_Calibration_Flow] ====Done====
7352 12:47:32.064164
7353 12:47:32.067503 [DutyScan_Calibration_Flow] k_type=3
7354 12:47:32.085462
7355 12:47:32.085652 ==DQM 0 ==
7356 12:47:32.088552 Final DQM duty delay cell = 4
7357 12:47:32.092138 [4] MAX Duty = 5156%(X100), DQS PI = 24
7358 12:47:32.095372 [4] MIN Duty = 5000%(X100), DQS PI = 30
7359 12:47:32.098580 [4] AVG Duty = 5078%(X100)
7360 12:47:32.098696
7361 12:47:32.098796 ==DQM 1 ==
7362 12:47:32.101963 Final DQM duty delay cell = 0
7363 12:47:32.105248 [0] MAX Duty = 5281%(X100), DQS PI = 58
7364 12:47:32.108654 [0] MIN Duty = 4907%(X100), DQS PI = 34
7365 12:47:32.111827 [0] AVG Duty = 5094%(X100)
7366 12:47:32.111959
7367 12:47:32.115352 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7368 12:47:32.115479
7369 12:47:32.118549 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7370 12:47:32.122214 [DutyScan_Calibration_Flow] ====Done====
7371 12:47:32.122317
7372 12:47:32.125318 [DutyScan_Calibration_Flow] k_type=2
7373 12:47:32.142390
7374 12:47:32.142544 ==DQ 0 ==
7375 12:47:32.145609 Final DQ duty delay cell = 0
7376 12:47:32.148933 [0] MAX Duty = 5093%(X100), DQS PI = 18
7377 12:47:32.152499 [0] MIN Duty = 4969%(X100), DQS PI = 46
7378 12:47:32.152608 [0] AVG Duty = 5031%(X100)
7379 12:47:32.155374
7380 12:47:32.155495 ==DQ 1 ==
7381 12:47:32.159173 Final DQ duty delay cell = 0
7382 12:47:32.162130 [0] MAX Duty = 5062%(X100), DQS PI = 2
7383 12:47:32.165611 [0] MIN Duty = 4813%(X100), DQS PI = 34
7384 12:47:32.165752 [0] AVG Duty = 4937%(X100)
7385 12:47:32.165853
7386 12:47:32.168937 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7387 12:47:32.171910
7388 12:47:32.175577 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7389 12:47:32.178518 [DutyScan_Calibration_Flow] ====Done====
7390 12:47:32.182174 nWR fixed to 30
7391 12:47:32.182320 [ModeRegInit_LP4] CH0 RK0
7392 12:47:32.185269 [ModeRegInit_LP4] CH0 RK1
7393 12:47:32.188774 [ModeRegInit_LP4] CH1 RK0
7394 12:47:32.191834 [ModeRegInit_LP4] CH1 RK1
7395 12:47:32.191972 match AC timing 5
7396 12:47:32.195176 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7397 12:47:32.201865 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7398 12:47:32.205123 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7399 12:47:32.212243 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7400 12:47:32.215315 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7401 12:47:32.215471 [MiockJmeterHQA]
7402 12:47:32.215589
7403 12:47:32.218545 [DramcMiockJmeter] u1RxGatingPI = 0
7404 12:47:32.222018 0 : 4255, 4029
7405 12:47:32.222132 4 : 4363, 4137
7406 12:47:32.222201 8 : 4252, 4027
7407 12:47:32.225168 12 : 4368, 4140
7408 12:47:32.225289 16 : 4257, 4030
7409 12:47:32.228339 20 : 4253, 4027
7410 12:47:32.228433 24 : 4252, 4026
7411 12:47:32.231590 28 : 4363, 4138
7412 12:47:32.231727 32 : 4363, 4137
7413 12:47:32.235138 36 : 4252, 4027
7414 12:47:32.235275 40 : 4253, 4026
7415 12:47:32.235395 44 : 4253, 4026
7416 12:47:32.238382 48 : 4252, 4027
7417 12:47:32.238522 52 : 4255, 4029
7418 12:47:32.241641 56 : 4363, 4137
7419 12:47:32.241754 60 : 4250, 4026
7420 12:47:32.245235 64 : 4250, 4027
7421 12:47:32.245327 68 : 4252, 4027
7422 12:47:32.248731 72 : 4253, 4029
7423 12:47:32.248873 76 : 4250, 4027
7424 12:47:32.248943 80 : 4363, 4137
7425 12:47:32.251560 84 : 4363, 4140
7426 12:47:32.251672 88 : 4250, 3771
7427 12:47:32.254890 92 : 4250, 0
7428 12:47:32.254983 96 : 4360, 0
7429 12:47:32.255055 100 : 4252, 0
7430 12:47:32.258243 104 : 4250, 0
7431 12:47:32.258332 108 : 4253, 0
7432 12:47:32.261949 112 : 4250, 0
7433 12:47:32.262034 116 : 4250, 0
7434 12:47:32.262098 120 : 4252, 0
7435 12:47:32.264898 124 : 4360, 0
7436 12:47:32.265004 128 : 4253, 0
7437 12:47:32.268461 132 : 4361, 0
7438 12:47:32.268583 136 : 4250, 0
7439 12:47:32.268678 140 : 4360, 0
7440 12:47:32.271829 144 : 4250, 0
7441 12:47:32.271965 148 : 4250, 0
7442 12:47:32.272088 152 : 4250, 0
7443 12:47:32.275297 156 : 4250, 0
7444 12:47:32.275405 160 : 4250, 0
7445 12:47:32.278279 164 : 4250, 0
7446 12:47:32.278386 168 : 4250, 0
7447 12:47:32.278483 172 : 4252, 0
7448 12:47:32.281486 176 : 4360, 0
7449 12:47:32.281602 180 : 4361, 0
7450 12:47:32.285165 184 : 4247, 0
7451 12:47:32.285262 188 : 4250, 0
7452 12:47:32.285350 192 : 4250, 0
7453 12:47:32.288518 196 : 4250, 0
7454 12:47:32.288663 200 : 4250, 0
7455 12:47:32.291648 204 : 4250, 1969
7456 12:47:32.291794 208 : 4250, 4026
7457 12:47:32.294814 212 : 4250, 4027
7458 12:47:32.295000 216 : 4250, 4027
7459 12:47:32.295120 220 : 4250, 4027
7460 12:47:32.298543 224 : 4360, 4138
7461 12:47:32.298760 228 : 4250, 4027
7462 12:47:32.301798 232 : 4250, 4026
7463 12:47:32.301941 236 : 4360, 4137
7464 12:47:32.304994 240 : 4250, 4027
7465 12:47:32.305174 244 : 4250, 4026
7466 12:47:32.308263 248 : 4364, 4140
7467 12:47:32.308408 252 : 4250, 4027
7468 12:47:32.311834 256 : 4250, 4027
7469 12:47:32.311989 260 : 4250, 4026
7470 12:47:32.314999 264 : 4253, 4029
7471 12:47:32.315138 268 : 4250, 4027
7472 12:47:32.318315 272 : 4250, 4027
7473 12:47:32.318458 276 : 4360, 4137
7474 12:47:32.318561 280 : 4250, 4027
7475 12:47:32.321543 284 : 4250, 4027
7476 12:47:32.321669 288 : 4363, 4140
7477 12:47:32.325032 292 : 4250, 4027
7478 12:47:32.325152 296 : 4250, 4026
7479 12:47:32.328510 300 : 4363, 4140
7480 12:47:32.328639 304 : 4250, 4027
7481 12:47:32.331522 308 : 4250, 4027
7482 12:47:32.331635 312 : 4250, 3982
7483 12:47:32.335373 316 : 4252, 2282
7484 12:47:32.335495 320 : 4250, 44
7485 12:47:32.335607
7486 12:47:32.338417 MIOCK jitter meter ch=0
7487 12:47:32.338518
7488 12:47:32.341654 1T = (320-92) = 228 dly cells
7489 12:47:32.344845 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7490 12:47:32.344954 ==
7491 12:47:32.348243 Dram Type= 6, Freq= 0, CH_0, rank 0
7492 12:47:32.355003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7493 12:47:32.355156 ==
7494 12:47:32.358173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7495 12:47:32.364920 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7496 12:47:32.368304 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7497 12:47:32.374930 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7498 12:47:32.382386 [CA 0] Center 42 (12~73) winsize 62
7499 12:47:32.385866 [CA 1] Center 43 (13~73) winsize 61
7500 12:47:32.389132 [CA 2] Center 38 (8~68) winsize 61
7501 12:47:32.392294 [CA 3] Center 37 (8~67) winsize 60
7502 12:47:32.395997 [CA 4] Center 36 (6~66) winsize 61
7503 12:47:32.399256 [CA 5] Center 35 (5~65) winsize 61
7504 12:47:32.399429
7505 12:47:32.402489 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7506 12:47:32.402651
7507 12:47:32.405677 [CATrainingPosCal] consider 1 rank data
7508 12:47:32.409154 u2DelayCellTimex100 = 285/100 ps
7509 12:47:32.412185 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7510 12:47:32.419256 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7511 12:47:32.422368 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7512 12:47:32.426045 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7513 12:47:32.428966 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7514 12:47:32.432562 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7515 12:47:32.432710
7516 12:47:32.435792 CA PerBit enable=1, Macro0, CA PI delay=35
7517 12:47:32.435907
7518 12:47:32.438900 [CBTSetCACLKResult] CA Dly = 35
7519 12:47:32.442426 CS Dly: 10 (0~41)
7520 12:47:32.445630 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7521 12:47:32.448996 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7522 12:47:32.449115 ==
7523 12:47:32.452199 Dram Type= 6, Freq= 0, CH_0, rank 1
7524 12:47:32.455788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 12:47:32.458952 ==
7526 12:47:32.462142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7527 12:47:32.465684 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7528 12:47:32.472080 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7529 12:47:32.475498 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7530 12:47:32.486048 [CA 0] Center 43 (13~74) winsize 62
7531 12:47:32.489166 [CA 1] Center 43 (13~73) winsize 61
7532 12:47:32.492409 [CA 2] Center 38 (9~68) winsize 60
7533 12:47:32.495833 [CA 3] Center 38 (9~68) winsize 60
7534 12:47:32.499242 [CA 4] Center 37 (7~67) winsize 61
7535 12:47:32.502387 [CA 5] Center 36 (6~66) winsize 61
7536 12:47:32.502493
7537 12:47:32.505999 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7538 12:47:32.506120
7539 12:47:32.509301 [CATrainingPosCal] consider 2 rank data
7540 12:47:32.512613 u2DelayCellTimex100 = 285/100 ps
7541 12:47:32.515576 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7542 12:47:32.522335 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7543 12:47:32.525927 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7544 12:47:32.529128 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7545 12:47:32.532249 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7546 12:47:32.536102 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7547 12:47:32.536219
7548 12:47:32.539383 CA PerBit enable=1, Macro0, CA PI delay=35
7549 12:47:32.539483
7550 12:47:32.542334 [CBTSetCACLKResult] CA Dly = 35
7551 12:47:32.545707 CS Dly: 11 (0~43)
7552 12:47:32.549214 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7553 12:47:32.552399 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7554 12:47:32.552501
7555 12:47:32.555847 ----->DramcWriteLeveling(PI) begin...
7556 12:47:32.555943 ==
7557 12:47:32.558890 Dram Type= 6, Freq= 0, CH_0, rank 0
7558 12:47:32.565676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 12:47:32.565806 ==
7560 12:47:32.568780 Write leveling (Byte 0): 38 => 38
7561 12:47:32.568889 Write leveling (Byte 1): 28 => 28
7562 12:47:32.572291 DramcWriteLeveling(PI) end<-----
7563 12:47:32.572428
7564 12:47:32.572530 ==
7565 12:47:32.575714 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 12:47:32.582458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 12:47:32.582587 ==
7568 12:47:32.585951 [Gating] SW mode calibration
7569 12:47:32.592529 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7570 12:47:32.595841 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7571 12:47:32.602260 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 12:47:32.605942 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 12:47:32.609184 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7574 12:47:32.615566 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7575 12:47:32.618785 1 4 16 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
7576 12:47:32.621895 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7577 12:47:32.628484 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7578 12:47:32.631995 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7579 12:47:32.635207 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 12:47:32.641915 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 12:47:32.645186 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7582 12:47:32.648740 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7583 12:47:32.651965 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7584 12:47:32.658419 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7585 12:47:32.661660 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 12:47:32.665231 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 12:47:32.672009 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 12:47:32.675057 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7589 12:47:32.678518 1 6 8 | B1->B0 | 2323 3a39 | 0 1 | (0 0) (0 0)
7590 12:47:32.685364 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7591 12:47:32.688486 1 6 16 | B1->B0 | 2727 4646 | 1 0 | (0 0) (0 0)
7592 12:47:32.691893 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7593 12:47:32.698283 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 12:47:32.702047 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 12:47:32.705024 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 12:47:32.712013 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 12:47:32.715042 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7598 12:47:32.718449 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7599 12:47:32.724989 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7600 12:47:32.728220 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7601 12:47:32.731675 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 12:47:32.738065 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 12:47:32.741747 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 12:47:32.744869 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 12:47:32.751551 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 12:47:32.754868 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 12:47:32.758507 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 12:47:32.764805 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 12:47:32.767908 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 12:47:32.771354 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 12:47:32.778168 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 12:47:32.781312 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 12:47:32.784973 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7614 12:47:32.791156 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7615 12:47:32.794624 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7616 12:47:32.797942 Total UI for P1: 0, mck2ui 16
7617 12:47:32.801180 best dqsien dly found for B0: ( 1, 9, 10)
7618 12:47:32.804624 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7619 12:47:32.807797 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7620 12:47:32.814878 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 12:47:32.818059 Total UI for P1: 0, mck2ui 16
7622 12:47:32.821374 best dqsien dly found for B1: ( 1, 9, 20)
7623 12:47:32.824432 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7624 12:47:32.827714 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7625 12:47:32.827846
7626 12:47:32.831467 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7627 12:47:32.834626 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7628 12:47:32.837743 [Gating] SW calibration Done
7629 12:47:32.837879 ==
7630 12:47:32.841444 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 12:47:32.844398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 12:47:32.844533 ==
7633 12:47:32.847677 RX Vref Scan: 0
7634 12:47:32.847823
7635 12:47:32.850894 RX Vref 0 -> 0, step: 1
7636 12:47:32.851037
7637 12:47:32.851165 RX Delay 0 -> 252, step: 8
7638 12:47:32.857747 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7639 12:47:32.861009 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7640 12:47:32.864270 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7641 12:47:32.867877 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7642 12:47:32.871514 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7643 12:47:32.874701 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7644 12:47:32.881500 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7645 12:47:32.884670 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7646 12:47:32.888040 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7647 12:47:32.891381 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7648 12:47:32.894540 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7649 12:47:32.901234 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7650 12:47:32.904164 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7651 12:47:32.907947 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7652 12:47:32.910922 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7653 12:47:32.914230 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7654 12:47:32.917739 ==
7655 12:47:32.921115 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 12:47:32.924314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 12:47:32.924457 ==
7658 12:47:32.924564 DQS Delay:
7659 12:47:32.927686 DQS0 = 0, DQS1 = 0
7660 12:47:32.927785 DQM Delay:
7661 12:47:32.931461 DQM0 = 138, DQM1 = 127
7662 12:47:32.931561 DQ Delay:
7663 12:47:32.934501 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7664 12:47:32.937778 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7665 12:47:32.941447 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7666 12:47:32.944787 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7667 12:47:32.944945
7668 12:47:32.945072
7669 12:47:32.945186 ==
7670 12:47:32.947827 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 12:47:32.954481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 12:47:32.954663 ==
7673 12:47:32.954794
7674 12:47:32.954909
7675 12:47:32.955030 TX Vref Scan disable
7676 12:47:32.958192 == TX Byte 0 ==
7677 12:47:32.961284 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7678 12:47:32.967794 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7679 12:47:32.967945 == TX Byte 1 ==
7680 12:47:32.971066 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7681 12:47:32.977705 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7682 12:47:32.977882 ==
7683 12:47:32.981333 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 12:47:32.984489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 12:47:32.984637 ==
7686 12:47:32.998018
7687 12:47:33.000865 TX Vref early break, caculate TX vref
7688 12:47:33.004137 TX Vref=16, minBit 0, minWin=23, winSum=378
7689 12:47:33.007755 TX Vref=18, minBit 7, minWin=23, winSum=389
7690 12:47:33.011003 TX Vref=20, minBit 1, minWin=24, winSum=397
7691 12:47:33.014232 TX Vref=22, minBit 7, minWin=24, winSum=405
7692 12:47:33.017628 TX Vref=24, minBit 0, minWin=25, winSum=416
7693 12:47:33.024620 TX Vref=26, minBit 2, minWin=25, winSum=427
7694 12:47:33.027658 TX Vref=28, minBit 0, minWin=26, winSum=433
7695 12:47:33.030959 TX Vref=30, minBit 0, minWin=26, winSum=431
7696 12:47:33.034475 TX Vref=32, minBit 0, minWin=25, winSum=422
7697 12:47:33.037702 TX Vref=34, minBit 4, minWin=24, winSum=408
7698 12:47:33.044564 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
7699 12:47:33.044718
7700 12:47:33.047680 Final TX Range 0 Vref 28
7701 12:47:33.047804
7702 12:47:33.047894 ==
7703 12:47:33.050765 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 12:47:33.054488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 12:47:33.054623 ==
7706 12:47:33.054720
7707 12:47:33.054803
7708 12:47:33.057628 TX Vref Scan disable
7709 12:47:33.064338 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7710 12:47:33.064511 == TX Byte 0 ==
7711 12:47:33.067769 u2DelayCellOfst[0]=17 cells (5 PI)
7712 12:47:33.070793 u2DelayCellOfst[1]=20 cells (6 PI)
7713 12:47:33.073907 u2DelayCellOfst[2]=13 cells (4 PI)
7714 12:47:33.077290 u2DelayCellOfst[3]=17 cells (5 PI)
7715 12:47:33.080730 u2DelayCellOfst[4]=10 cells (3 PI)
7716 12:47:33.084002 u2DelayCellOfst[5]=0 cells (0 PI)
7717 12:47:33.087170 u2DelayCellOfst[6]=20 cells (6 PI)
7718 12:47:33.090705 u2DelayCellOfst[7]=17 cells (5 PI)
7719 12:47:33.093879 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7720 12:47:33.097224 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7721 12:47:33.100866 == TX Byte 1 ==
7722 12:47:33.101015 u2DelayCellOfst[8]=0 cells (0 PI)
7723 12:47:33.104087 u2DelayCellOfst[9]=0 cells (0 PI)
7724 12:47:33.107560 u2DelayCellOfst[10]=6 cells (2 PI)
7725 12:47:33.110425 u2DelayCellOfst[11]=0 cells (0 PI)
7726 12:47:33.114185 u2DelayCellOfst[12]=10 cells (3 PI)
7727 12:47:33.117482 u2DelayCellOfst[13]=10 cells (3 PI)
7728 12:47:33.120780 u2DelayCellOfst[14]=13 cells (4 PI)
7729 12:47:33.124082 u2DelayCellOfst[15]=10 cells (3 PI)
7730 12:47:33.127133 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7731 12:47:33.133756 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7732 12:47:33.133882 DramC Write-DBI on
7733 12:47:33.133985 ==
7734 12:47:33.137361 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 12:47:33.140637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 12:47:33.143825 ==
7737 12:47:33.143920
7738 12:47:33.144005
7739 12:47:33.144092 TX Vref Scan disable
7740 12:47:33.147636 == TX Byte 0 ==
7741 12:47:33.150741 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7742 12:47:33.153776 == TX Byte 1 ==
7743 12:47:33.157410 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7744 12:47:33.160449 DramC Write-DBI off
7745 12:47:33.160566
7746 12:47:33.160664 [DATLAT]
7747 12:47:33.160778 Freq=1600, CH0 RK0
7748 12:47:33.160844
7749 12:47:33.163793 DATLAT Default: 0xf
7750 12:47:33.163893 0, 0xFFFF, sum = 0
7751 12:47:33.167048 1, 0xFFFF, sum = 0
7752 12:47:33.170886 2, 0xFFFF, sum = 0
7753 12:47:33.171040 3, 0xFFFF, sum = 0
7754 12:47:33.173671 4, 0xFFFF, sum = 0
7755 12:47:33.173771 5, 0xFFFF, sum = 0
7756 12:47:33.177378 6, 0xFFFF, sum = 0
7757 12:47:33.177482 7, 0xFFFF, sum = 0
7758 12:47:33.180358 8, 0xFFFF, sum = 0
7759 12:47:33.180482 9, 0xFFFF, sum = 0
7760 12:47:33.183585 10, 0xFFFF, sum = 0
7761 12:47:33.183714 11, 0xFFFF, sum = 0
7762 12:47:33.187343 12, 0xFFFF, sum = 0
7763 12:47:33.187472 13, 0xFFFF, sum = 0
7764 12:47:33.190411 14, 0x0, sum = 1
7765 12:47:33.190551 15, 0x0, sum = 2
7766 12:47:33.193537 16, 0x0, sum = 3
7767 12:47:33.193668 17, 0x0, sum = 4
7768 12:47:33.197345 best_step = 15
7769 12:47:33.197478
7770 12:47:33.197596 ==
7771 12:47:33.200572 Dram Type= 6, Freq= 0, CH_0, rank 0
7772 12:47:33.203513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7773 12:47:33.203648 ==
7774 12:47:33.207091 RX Vref Scan: 1
7775 12:47:33.207217
7776 12:47:33.207319 Set Vref Range= 24 -> 127
7777 12:47:33.207411
7778 12:47:33.210199 RX Vref 24 -> 127, step: 1
7779 12:47:33.210318
7780 12:47:33.213766 RX Delay 19 -> 252, step: 4
7781 12:47:33.213912
7782 12:47:33.216882 Set Vref, RX VrefLevel [Byte0]: 24
7783 12:47:33.220206 [Byte1]: 24
7784 12:47:33.220323
7785 12:47:33.223550 Set Vref, RX VrefLevel [Byte0]: 25
7786 12:47:33.227024 [Byte1]: 25
7787 12:47:33.227159
7788 12:47:33.230429 Set Vref, RX VrefLevel [Byte0]: 26
7789 12:47:33.233633 [Byte1]: 26
7790 12:47:33.237430
7791 12:47:33.237565 Set Vref, RX VrefLevel [Byte0]: 27
7792 12:47:33.240671 [Byte1]: 27
7793 12:47:33.245277
7794 12:47:33.245407 Set Vref, RX VrefLevel [Byte0]: 28
7795 12:47:33.248645 [Byte1]: 28
7796 12:47:33.252563
7797 12:47:33.252677 Set Vref, RX VrefLevel [Byte0]: 29
7798 12:47:33.256140 [Byte1]: 29
7799 12:47:33.260221
7800 12:47:33.260366 Set Vref, RX VrefLevel [Byte0]: 30
7801 12:47:33.263930 [Byte1]: 30
7802 12:47:33.267644
7803 12:47:33.267743 Set Vref, RX VrefLevel [Byte0]: 31
7804 12:47:33.271074 [Byte1]: 31
7805 12:47:33.275344
7806 12:47:33.275452 Set Vref, RX VrefLevel [Byte0]: 32
7807 12:47:33.279035 [Byte1]: 32
7808 12:47:33.283281
7809 12:47:33.283385 Set Vref, RX VrefLevel [Byte0]: 33
7810 12:47:33.286266 [Byte1]: 33
7811 12:47:33.290675
7812 12:47:33.290826 Set Vref, RX VrefLevel [Byte0]: 34
7813 12:47:33.293751 [Byte1]: 34
7814 12:47:33.298169
7815 12:47:33.298317 Set Vref, RX VrefLevel [Byte0]: 35
7816 12:47:33.301376 [Byte1]: 35
7817 12:47:33.305663
7818 12:47:33.305813 Set Vref, RX VrefLevel [Byte0]: 36
7819 12:47:33.309028 [Byte1]: 36
7820 12:47:33.313582
7821 12:47:33.313717 Set Vref, RX VrefLevel [Byte0]: 37
7822 12:47:33.316701 [Byte1]: 37
7823 12:47:33.320736
7824 12:47:33.320876 Set Vref, RX VrefLevel [Byte0]: 38
7825 12:47:33.324222 [Byte1]: 38
7826 12:47:33.328621
7827 12:47:33.328740 Set Vref, RX VrefLevel [Byte0]: 39
7828 12:47:33.331724 [Byte1]: 39
7829 12:47:33.336035
7830 12:47:33.336149 Set Vref, RX VrefLevel [Byte0]: 40
7831 12:47:33.339231 [Byte1]: 40
7832 12:47:33.343785
7833 12:47:33.343896 Set Vref, RX VrefLevel [Byte0]: 41
7834 12:47:33.346744 [Byte1]: 41
7835 12:47:33.351168
7836 12:47:33.351275 Set Vref, RX VrefLevel [Byte0]: 42
7837 12:47:33.354396 [Byte1]: 42
7838 12:47:33.359036
7839 12:47:33.359191 Set Vref, RX VrefLevel [Byte0]: 43
7840 12:47:33.361959 [Byte1]: 43
7841 12:47:33.366224
7842 12:47:33.366375 Set Vref, RX VrefLevel [Byte0]: 44
7843 12:47:33.369705 [Byte1]: 44
7844 12:47:33.373957
7845 12:47:33.374097 Set Vref, RX VrefLevel [Byte0]: 45
7846 12:47:33.377182 [Byte1]: 45
7847 12:47:33.381290
7848 12:47:33.381426 Set Vref, RX VrefLevel [Byte0]: 46
7849 12:47:33.384577 [Byte1]: 46
7850 12:47:33.388940
7851 12:47:33.389101 Set Vref, RX VrefLevel [Byte0]: 47
7852 12:47:33.392299 [Byte1]: 47
7853 12:47:33.396672
7854 12:47:33.396836 Set Vref, RX VrefLevel [Byte0]: 48
7855 12:47:33.399883 [Byte1]: 48
7856 12:47:33.404168
7857 12:47:33.404318 Set Vref, RX VrefLevel [Byte0]: 49
7858 12:47:33.407444 [Byte1]: 49
7859 12:47:33.412192
7860 12:47:33.412340 Set Vref, RX VrefLevel [Byte0]: 50
7861 12:47:33.415343 [Byte1]: 50
7862 12:47:33.419202
7863 12:47:33.419326 Set Vref, RX VrefLevel [Byte0]: 51
7864 12:47:33.422815 [Byte1]: 51
7865 12:47:33.426747
7866 12:47:33.426892 Set Vref, RX VrefLevel [Byte0]: 52
7867 12:47:33.430159 [Byte1]: 52
7868 12:47:33.434506
7869 12:47:33.434651 Set Vref, RX VrefLevel [Byte0]: 53
7870 12:47:33.437986 [Byte1]: 53
7871 12:47:33.442349
7872 12:47:33.442490 Set Vref, RX VrefLevel [Byte0]: 54
7873 12:47:33.445135 [Byte1]: 54
7874 12:47:33.449421
7875 12:47:33.449596 Set Vref, RX VrefLevel [Byte0]: 55
7876 12:47:33.453314 [Byte1]: 55
7877 12:47:33.457353
7878 12:47:33.457533 Set Vref, RX VrefLevel [Byte0]: 56
7879 12:47:33.460326 [Byte1]: 56
7880 12:47:33.464927
7881 12:47:33.465052 Set Vref, RX VrefLevel [Byte0]: 57
7882 12:47:33.468178 [Byte1]: 57
7883 12:47:33.472413
7884 12:47:33.472545 Set Vref, RX VrefLevel [Byte0]: 58
7885 12:47:33.475504 [Byte1]: 58
7886 12:47:33.479985
7887 12:47:33.480114 Set Vref, RX VrefLevel [Byte0]: 59
7888 12:47:33.483038 [Byte1]: 59
7889 12:47:33.487579
7890 12:47:33.487693 Set Vref, RX VrefLevel [Byte0]: 60
7891 12:47:33.490923 [Byte1]: 60
7892 12:47:33.495099
7893 12:47:33.495210 Set Vref, RX VrefLevel [Byte0]: 61
7894 12:47:33.498708 [Byte1]: 61
7895 12:47:33.502622
7896 12:47:33.502723 Set Vref, RX VrefLevel [Byte0]: 62
7897 12:47:33.506044 [Byte1]: 62
7898 12:47:33.510287
7899 12:47:33.510390 Set Vref, RX VrefLevel [Byte0]: 63
7900 12:47:33.513544 [Byte1]: 63
7901 12:47:33.517657
7902 12:47:33.517753 Set Vref, RX VrefLevel [Byte0]: 64
7903 12:47:33.521265 [Byte1]: 64
7904 12:47:33.525238
7905 12:47:33.525338 Set Vref, RX VrefLevel [Byte0]: 65
7906 12:47:33.528537 [Byte1]: 65
7907 12:47:33.533100
7908 12:47:33.533230 Set Vref, RX VrefLevel [Byte0]: 66
7909 12:47:33.536399 [Byte1]: 66
7910 12:47:33.540463
7911 12:47:33.540609 Set Vref, RX VrefLevel [Byte0]: 67
7912 12:47:33.543944 [Byte1]: 67
7913 12:47:33.548088
7914 12:47:33.548222 Set Vref, RX VrefLevel [Byte0]: 68
7915 12:47:33.551524 [Byte1]: 68
7916 12:47:33.555473
7917 12:47:33.555608 Set Vref, RX VrefLevel [Byte0]: 69
7918 12:47:33.558822 [Byte1]: 69
7919 12:47:33.563178
7920 12:47:33.563324 Set Vref, RX VrefLevel [Byte0]: 70
7921 12:47:33.566635 [Byte1]: 70
7922 12:47:33.570769
7923 12:47:33.570918 Set Vref, RX VrefLevel [Byte0]: 71
7924 12:47:33.574106 [Byte1]: 71
7925 12:47:33.578203
7926 12:47:33.578339 Set Vref, RX VrefLevel [Byte0]: 72
7927 12:47:33.581593 [Byte1]: 72
7928 12:47:33.585982
7929 12:47:33.586113 Set Vref, RX VrefLevel [Byte0]: 73
7930 12:47:33.589405 [Byte1]: 73
7931 12:47:33.593526
7932 12:47:33.593657 Set Vref, RX VrefLevel [Byte0]: 74
7933 12:47:33.596668 [Byte1]: 74
7934 12:47:33.601221
7935 12:47:33.601360 Set Vref, RX VrefLevel [Byte0]: 75
7936 12:47:33.604352 [Byte1]: 75
7937 12:47:33.608691
7938 12:47:33.608842 Set Vref, RX VrefLevel [Byte0]: 76
7939 12:47:33.611918 [Byte1]: 76
7940 12:47:33.616032
7941 12:47:33.616175 Set Vref, RX VrefLevel [Byte0]: 77
7942 12:47:33.619685 [Byte1]: 77
7943 12:47:33.623775
7944 12:47:33.623913 Set Vref, RX VrefLevel [Byte0]: 78
7945 12:47:33.627267 [Byte1]: 78
7946 12:47:33.631536
7947 12:47:33.634367 Set Vref, RX VrefLevel [Byte0]: 79
7948 12:47:33.637621 [Byte1]: 79
7949 12:47:33.637711
7950 12:47:33.641068 Set Vref, RX VrefLevel [Byte0]: 80
7951 12:47:33.644313 [Byte1]: 80
7952 12:47:33.644440
7953 12:47:33.648203 Final RX Vref Byte 0 = 64 to rank0
7954 12:47:33.651207 Final RX Vref Byte 1 = 62 to rank0
7955 12:47:33.654506 Final RX Vref Byte 0 = 64 to rank1
7956 12:47:33.657602 Final RX Vref Byte 1 = 62 to rank1==
7957 12:47:33.661112 Dram Type= 6, Freq= 0, CH_0, rank 0
7958 12:47:33.664596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 12:47:33.664688 ==
7960 12:47:33.667900 DQS Delay:
7961 12:47:33.667991 DQS0 = 0, DQS1 = 0
7962 12:47:33.668058 DQM Delay:
7963 12:47:33.671537 DQM0 = 136, DQM1 = 123
7964 12:47:33.671650 DQ Delay:
7965 12:47:33.674396 DQ0 =136, DQ1 =136, DQ2 =134, DQ3 =134
7966 12:47:33.678148 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =142
7967 12:47:33.681173 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7968 12:47:33.687677 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
7969 12:47:33.687848
7970 12:47:33.687975
7971 12:47:33.688090
7972 12:47:33.691390 [DramC_TX_OE_Calibration] TA2
7973 12:47:33.691523 Original DQ_B0 (3 6) =30, OEN = 27
7974 12:47:33.694733 Original DQ_B1 (3 6) =30, OEN = 27
7975 12:47:33.697860 24, 0x0, End_B0=24 End_B1=24
7976 12:47:33.700997 25, 0x0, End_B0=25 End_B1=25
7977 12:47:33.704345 26, 0x0, End_B0=26 End_B1=26
7978 12:47:33.704477 27, 0x0, End_B0=27 End_B1=27
7979 12:47:33.707606 28, 0x0, End_B0=28 End_B1=28
7980 12:47:33.711022 29, 0x0, End_B0=29 End_B1=29
7981 12:47:33.714519 30, 0x0, End_B0=30 End_B1=30
7982 12:47:33.717672 31, 0x4141, End_B0=30 End_B1=30
7983 12:47:33.721029 Byte0 end_step=30 best_step=27
7984 12:47:33.721172 Byte1 end_step=30 best_step=27
7985 12:47:33.724287 Byte0 TX OE(2T, 0.5T) = (3, 3)
7986 12:47:33.727829 Byte1 TX OE(2T, 0.5T) = (3, 3)
7987 12:47:33.727963
7988 12:47:33.728072
7989 12:47:33.737675 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7990 12:47:33.737869 CH0 RK0: MR19=303, MR18=1E1D
7991 12:47:33.744206 CH0_RK0: MR19=0x303, MR18=0x1E1D, DQSOSC=394, MR23=63, INC=23, DEC=15
7992 12:47:33.744349
7993 12:47:33.747511 ----->DramcWriteLeveling(PI) begin...
7994 12:47:33.747643 ==
7995 12:47:33.751155 Dram Type= 6, Freq= 0, CH_0, rank 1
7996 12:47:33.757603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 12:47:33.757792 ==
7998 12:47:33.760931 Write leveling (Byte 0): 37 => 37
7999 12:47:33.761070 Write leveling (Byte 1): 30 => 30
8000 12:47:33.764442 DramcWriteLeveling(PI) end<-----
8001 12:47:33.764573
8002 12:47:33.764699 ==
8003 12:47:33.767744 Dram Type= 6, Freq= 0, CH_0, rank 1
8004 12:47:33.774463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8005 12:47:33.774615 ==
8006 12:47:33.778157 [Gating] SW mode calibration
8007 12:47:33.784506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8008 12:47:33.787658 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8009 12:47:33.794192 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 12:47:33.797699 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 12:47:33.800803 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 12:47:33.807661 1 4 12 | B1->B0 | 2929 3030 | 0 1 | (0 0) (0 0)
8013 12:47:33.810817 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 12:47:33.814054 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 12:47:33.820802 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 12:47:33.824320 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 12:47:33.827561 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 12:47:33.830826 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 12:47:33.837796 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8020 12:47:33.840980 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8021 12:47:33.844206 1 5 16 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8022 12:47:33.850950 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 12:47:33.854225 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 12:47:33.857669 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 12:47:33.864444 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 12:47:33.867790 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 12:47:33.871188 1 6 8 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
8028 12:47:33.877712 1 6 12 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
8029 12:47:33.881215 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8030 12:47:33.884229 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 12:47:33.890979 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 12:47:33.894706 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 12:47:33.897397 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 12:47:33.904204 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 12:47:33.907658 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 12:47:33.911281 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8037 12:47:33.917486 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8038 12:47:33.921067 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 12:47:33.924225 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 12:47:33.930712 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 12:47:33.934000 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 12:47:33.937269 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 12:47:33.944115 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 12:47:33.947363 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 12:47:33.950940 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 12:47:33.954000 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 12:47:33.960696 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 12:47:33.963951 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 12:47:33.967363 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 12:47:33.973964 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:47:33.977145 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8052 12:47:33.980385 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8053 12:47:33.987196 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8054 12:47:33.990202 Total UI for P1: 0, mck2ui 16
8055 12:47:33.993637 best dqsien dly found for B0: ( 1, 9, 10)
8056 12:47:33.997468 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 12:47:34.000440 Total UI for P1: 0, mck2ui 16
8058 12:47:34.003522 best dqsien dly found for B1: ( 1, 9, 14)
8059 12:47:34.006933 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8060 12:47:34.010338 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8061 12:47:34.010465
8062 12:47:34.013714 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8063 12:47:34.020400 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8064 12:47:34.020520 [Gating] SW calibration Done
8065 12:47:34.020605 ==
8066 12:47:34.023696 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 12:47:34.030312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 12:47:34.030464 ==
8069 12:47:34.030562 RX Vref Scan: 0
8070 12:47:34.030662
8071 12:47:34.033342 RX Vref 0 -> 0, step: 1
8072 12:47:34.033481
8073 12:47:34.036776 RX Delay 0 -> 252, step: 8
8074 12:47:34.040605 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8075 12:47:34.043332 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8076 12:47:34.046890 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8077 12:47:34.049933 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8078 12:47:34.057035 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8079 12:47:34.060210 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8080 12:47:34.063520 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8081 12:47:34.066710 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8082 12:47:34.070345 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8083 12:47:34.076676 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8084 12:47:34.080054 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8085 12:47:34.083259 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8086 12:47:34.086851 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8087 12:47:34.089760 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8088 12:47:34.096627 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8089 12:47:34.100312 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8090 12:47:34.100415 ==
8091 12:47:34.103263 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 12:47:34.106605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 12:47:34.106753 ==
8094 12:47:34.109779 DQS Delay:
8095 12:47:34.109915 DQS0 = 0, DQS1 = 0
8096 12:47:34.110048 DQM Delay:
8097 12:47:34.113330 DQM0 = 136, DQM1 = 125
8098 12:47:34.113439 DQ Delay:
8099 12:47:34.116535 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8100 12:47:34.119843 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8101 12:47:34.126509 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8102 12:47:34.130183 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8103 12:47:34.130334
8104 12:47:34.130458
8105 12:47:34.130565 ==
8106 12:47:34.133296 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 12:47:34.136663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 12:47:34.136811 ==
8109 12:47:34.136930
8110 12:47:34.137047
8111 12:47:34.139908 TX Vref Scan disable
8112 12:47:34.140039 == TX Byte 0 ==
8113 12:47:34.146315 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8114 12:47:34.150008 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8115 12:47:34.150156 == TX Byte 1 ==
8116 12:47:34.156574 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8117 12:47:34.159794 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8118 12:47:34.159942 ==
8119 12:47:34.163444 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 12:47:34.166461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 12:47:34.166594 ==
8122 12:47:34.182586
8123 12:47:34.185677 TX Vref early break, caculate TX vref
8124 12:47:34.189162 TX Vref=16, minBit 0, minWin=23, winSum=391
8125 12:47:34.192489 TX Vref=18, minBit 8, minWin=24, winSum=404
8126 12:47:34.196063 TX Vref=20, minBit 0, minWin=24, winSum=406
8127 12:47:34.198993 TX Vref=22, minBit 0, minWin=25, winSum=417
8128 12:47:34.202408 TX Vref=24, minBit 8, minWin=25, winSum=424
8129 12:47:34.209363 TX Vref=26, minBit 2, minWin=25, winSum=426
8130 12:47:34.213055 TX Vref=28, minBit 0, minWin=25, winSum=433
8131 12:47:34.215779 TX Vref=30, minBit 7, minWin=25, winSum=428
8132 12:47:34.219386 TX Vref=32, minBit 2, minWin=25, winSum=421
8133 12:47:34.222423 TX Vref=34, minBit 0, minWin=25, winSum=411
8134 12:47:34.225819 TX Vref=36, minBit 0, minWin=23, winSum=402
8135 12:47:34.232524 [TxChooseVref] Worse bit 0, Min win 25, Win sum 433, Final Vref 28
8136 12:47:34.232685
8137 12:47:34.235679 Final TX Range 0 Vref 28
8138 12:47:34.235802
8139 12:47:34.235901 ==
8140 12:47:34.238996 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 12:47:34.242201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 12:47:34.242340 ==
8143 12:47:34.242455
8144 12:47:34.242568
8145 12:47:34.245791 TX Vref Scan disable
8146 12:47:34.252263 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8147 12:47:34.252378 == TX Byte 0 ==
8148 12:47:34.255564 u2DelayCellOfst[0]=13 cells (4 PI)
8149 12:47:34.258736 u2DelayCellOfst[1]=17 cells (5 PI)
8150 12:47:34.262567 u2DelayCellOfst[2]=10 cells (3 PI)
8151 12:47:34.265568 u2DelayCellOfst[3]=10 cells (3 PI)
8152 12:47:34.268709 u2DelayCellOfst[4]=6 cells (2 PI)
8153 12:47:34.272168 u2DelayCellOfst[5]=0 cells (0 PI)
8154 12:47:34.275368 u2DelayCellOfst[6]=17 cells (5 PI)
8155 12:47:34.278777 u2DelayCellOfst[7]=17 cells (5 PI)
8156 12:47:34.281950 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8157 12:47:34.285545 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8158 12:47:34.288690 == TX Byte 1 ==
8159 12:47:34.291751 u2DelayCellOfst[8]=0 cells (0 PI)
8160 12:47:34.295424 u2DelayCellOfst[9]=0 cells (0 PI)
8161 12:47:34.298601 u2DelayCellOfst[10]=6 cells (2 PI)
8162 12:47:34.298702 u2DelayCellOfst[11]=3 cells (1 PI)
8163 12:47:34.301791 u2DelayCellOfst[12]=13 cells (4 PI)
8164 12:47:34.305045 u2DelayCellOfst[13]=10 cells (3 PI)
8165 12:47:34.308320 u2DelayCellOfst[14]=13 cells (4 PI)
8166 12:47:34.311603 u2DelayCellOfst[15]=10 cells (3 PI)
8167 12:47:34.318531 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8168 12:47:34.322009 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8169 12:47:34.322120 DramC Write-DBI on
8170 12:47:34.322210 ==
8171 12:47:34.324879 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 12:47:34.331534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 12:47:34.331656 ==
8174 12:47:34.331751
8175 12:47:34.331835
8176 12:47:34.331915 TX Vref Scan disable
8177 12:47:34.335663 == TX Byte 0 ==
8178 12:47:34.339277 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8179 12:47:34.342731 == TX Byte 1 ==
8180 12:47:34.346003 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8181 12:47:34.349268 DramC Write-DBI off
8182 12:47:34.349373
8183 12:47:34.349462 [DATLAT]
8184 12:47:34.349544 Freq=1600, CH0 RK1
8185 12:47:34.349624
8186 12:47:34.352579 DATLAT Default: 0xf
8187 12:47:34.352698 0, 0xFFFF, sum = 0
8188 12:47:34.355736 1, 0xFFFF, sum = 0
8189 12:47:34.355860 2, 0xFFFF, sum = 0
8190 12:47:34.359190 3, 0xFFFF, sum = 0
8191 12:47:34.362403 4, 0xFFFF, sum = 0
8192 12:47:34.362503 5, 0xFFFF, sum = 0
8193 12:47:34.366212 6, 0xFFFF, sum = 0
8194 12:47:34.366310 7, 0xFFFF, sum = 0
8195 12:47:34.369355 8, 0xFFFF, sum = 0
8196 12:47:34.369449 9, 0xFFFF, sum = 0
8197 12:47:34.372412 10, 0xFFFF, sum = 0
8198 12:47:34.372503 11, 0xFFFF, sum = 0
8199 12:47:34.375781 12, 0xFFFF, sum = 0
8200 12:47:34.375877 13, 0xFFFF, sum = 0
8201 12:47:34.379264 14, 0x0, sum = 1
8202 12:47:34.379387 15, 0x0, sum = 2
8203 12:47:34.382793 16, 0x0, sum = 3
8204 12:47:34.382914 17, 0x0, sum = 4
8205 12:47:34.385980 best_step = 15
8206 12:47:34.386098
8207 12:47:34.386200 ==
8208 12:47:34.389109 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 12:47:34.392335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 12:47:34.392460 ==
8211 12:47:34.392563 RX Vref Scan: 0
8212 12:47:34.395472
8213 12:47:34.395590 RX Vref 0 -> 0, step: 1
8214 12:47:34.395692
8215 12:47:34.399077 RX Delay 11 -> 252, step: 4
8216 12:47:34.402206 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8217 12:47:34.409155 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8218 12:47:34.412285 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8219 12:47:34.415506 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8220 12:47:34.419195 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8221 12:47:34.422416 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8222 12:47:34.429260 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8223 12:47:34.432357 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8224 12:47:34.435630 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8225 12:47:34.438931 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8226 12:47:34.442047 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8227 12:47:34.448939 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8228 12:47:34.452251 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8229 12:47:34.455437 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8230 12:47:34.458561 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8231 12:47:34.462028 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8232 12:47:34.465195 ==
8233 12:47:34.468732 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 12:47:34.471986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 12:47:34.472091 ==
8236 12:47:34.472182 DQS Delay:
8237 12:47:34.475291 DQS0 = 0, DQS1 = 0
8238 12:47:34.475385 DQM Delay:
8239 12:47:34.478629 DQM0 = 133, DQM1 = 123
8240 12:47:34.478773 DQ Delay:
8241 12:47:34.481743 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =128
8242 12:47:34.485587 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8243 12:47:34.488404 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8244 12:47:34.492151 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8245 12:47:34.492291
8246 12:47:34.492412
8247 12:47:34.492515
8248 12:47:34.495091 [DramC_TX_OE_Calibration] TA2
8249 12:47:34.498662 Original DQ_B0 (3 6) =30, OEN = 27
8250 12:47:34.502064 Original DQ_B1 (3 6) =30, OEN = 27
8251 12:47:34.505428 24, 0x0, End_B0=24 End_B1=24
8252 12:47:34.508525 25, 0x0, End_B0=25 End_B1=25
8253 12:47:34.508671 26, 0x0, End_B0=26 End_B1=26
8254 12:47:34.511802 27, 0x0, End_B0=27 End_B1=27
8255 12:47:34.515267 28, 0x0, End_B0=28 End_B1=28
8256 12:47:34.518472 29, 0x0, End_B0=29 End_B1=29
8257 12:47:34.521785 30, 0x0, End_B0=30 End_B1=30
8258 12:47:34.521914 31, 0x4141, End_B0=30 End_B1=30
8259 12:47:34.525240 Byte0 end_step=30 best_step=27
8260 12:47:34.528172 Byte1 end_step=30 best_step=27
8261 12:47:34.531709 Byte0 TX OE(2T, 0.5T) = (3, 3)
8262 12:47:34.534952 Byte1 TX OE(2T, 0.5T) = (3, 3)
8263 12:47:34.535117
8264 12:47:34.535222
8265 12:47:34.541593 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8266 12:47:34.545056 CH0 RK1: MR19=303, MR18=1F0C
8267 12:47:34.551692 CH0_RK1: MR19=0x303, MR18=0x1F0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8268 12:47:34.555013 [RxdqsGatingPostProcess] freq 1600
8269 12:47:34.561735 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8270 12:47:34.561914 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 12:47:34.564896 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 12:47:34.568365 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 12:47:34.571372 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 12:47:34.574821 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 12:47:34.578294 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 12:47:34.581668 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 12:47:34.584787 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 12:47:34.588336 Pre-setting of DQS Precalculation
8279 12:47:34.591519 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8280 12:47:34.591616 ==
8281 12:47:34.594852 Dram Type= 6, Freq= 0, CH_1, rank 0
8282 12:47:34.601442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 12:47:34.601564 ==
8284 12:47:34.604767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8285 12:47:34.611632 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8286 12:47:34.614876 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8287 12:47:34.621165 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8288 12:47:34.628954 [CA 0] Center 42 (12~72) winsize 61
8289 12:47:34.632354 [CA 1] Center 42 (13~72) winsize 60
8290 12:47:34.635512 [CA 2] Center 38 (9~68) winsize 60
8291 12:47:34.638939 [CA 3] Center 37 (8~67) winsize 60
8292 12:47:34.642638 [CA 4] Center 37 (8~67) winsize 60
8293 12:47:34.645759 [CA 5] Center 37 (7~67) winsize 61
8294 12:47:34.645885
8295 12:47:34.648691 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8296 12:47:34.648812
8297 12:47:34.652020 [CATrainingPosCal] consider 1 rank data
8298 12:47:34.655350 u2DelayCellTimex100 = 285/100 ps
8299 12:47:34.661971 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8300 12:47:34.665251 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8301 12:47:34.668976 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8302 12:47:34.672027 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8303 12:47:34.675406 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8304 12:47:34.678716 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8305 12:47:34.678818
8306 12:47:34.681921 CA PerBit enable=1, Macro0, CA PI delay=37
8307 12:47:34.682017
8308 12:47:34.685407 [CBTSetCACLKResult] CA Dly = 37
8309 12:47:34.688538 CS Dly: 8 (0~39)
8310 12:47:34.691766 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8311 12:47:34.695041 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8312 12:47:34.695135 ==
8313 12:47:34.698534 Dram Type= 6, Freq= 0, CH_1, rank 1
8314 12:47:34.701864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 12:47:34.704990 ==
8316 12:47:34.708211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8317 12:47:34.711808 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8318 12:47:34.718348 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8319 12:47:34.724848 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8320 12:47:34.732035 [CA 0] Center 42 (13~72) winsize 60
8321 12:47:34.735220 [CA 1] Center 42 (12~72) winsize 61
8322 12:47:34.738870 [CA 2] Center 38 (9~68) winsize 60
8323 12:47:34.742172 [CA 3] Center 37 (8~67) winsize 60
8324 12:47:34.745259 [CA 4] Center 39 (10~68) winsize 59
8325 12:47:34.748527 [CA 5] Center 37 (8~67) winsize 60
8326 12:47:34.748659
8327 12:47:34.752082 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8328 12:47:34.752232
8329 12:47:34.755296 [CATrainingPosCal] consider 2 rank data
8330 12:47:34.758815 u2DelayCellTimex100 = 285/100 ps
8331 12:47:34.762072 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8332 12:47:34.768784 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8333 12:47:34.771944 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8334 12:47:34.775368 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8335 12:47:34.778781 CA4 delay=38 (10~67),Diff = 1 PI (3 cell)
8336 12:47:34.781998 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8337 12:47:34.782155
8338 12:47:34.785097 CA PerBit enable=1, Macro0, CA PI delay=37
8339 12:47:34.785230
8340 12:47:34.788317 [CBTSetCACLKResult] CA Dly = 37
8341 12:47:34.791880 CS Dly: 9 (0~42)
8342 12:47:34.795266 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8343 12:47:34.798577 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8344 12:47:34.798720
8345 12:47:34.801719 ----->DramcWriteLeveling(PI) begin...
8346 12:47:34.801858 ==
8347 12:47:34.805076 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 12:47:34.808781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 12:47:34.811902 ==
8350 12:47:34.812035 Write leveling (Byte 0): 24 => 24
8351 12:47:34.815398 Write leveling (Byte 1): 29 => 29
8352 12:47:34.818595 DramcWriteLeveling(PI) end<-----
8353 12:47:34.818707
8354 12:47:34.818805 ==
8355 12:47:34.821983 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 12:47:34.828818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 12:47:34.828930 ==
8358 12:47:34.829006 [Gating] SW mode calibration
8359 12:47:34.838485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8360 12:47:34.841730 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8361 12:47:34.848515 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 12:47:34.851603 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 12:47:34.855320 1 4 8 | B1->B0 | 2727 3232 | 1 1 | (1 1) (0 0)
8364 12:47:34.861901 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8365 12:47:34.865032 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 12:47:34.868393 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 12:47:34.871581 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 12:47:34.878307 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 12:47:34.881746 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 12:47:34.885216 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 12:47:34.891441 1 5 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 1)
8372 12:47:34.895025 1 5 12 | B1->B0 | 2424 2323 | 1 0 | (1 0) (1 0)
8373 12:47:34.898102 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 12:47:34.904727 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 12:47:34.908378 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 12:47:34.911946 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 12:47:34.918663 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 12:47:34.921739 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8379 12:47:34.924883 1 6 8 | B1->B0 | 2f2f 4141 | 0 0 | (0 0) (0 0)
8380 12:47:34.931707 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8381 12:47:34.934973 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 12:47:34.938327 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 12:47:34.944823 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 12:47:34.948061 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 12:47:34.951693 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 12:47:34.958239 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8387 12:47:34.961593 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8388 12:47:34.964704 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8389 12:47:34.971384 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8390 12:47:34.974633 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 12:47:34.977991 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 12:47:34.984730 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 12:47:34.988053 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 12:47:34.991424 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 12:47:34.994702 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 12:47:35.001565 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 12:47:35.004683 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 12:47:35.008323 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 12:47:35.014763 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 12:47:35.017858 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 12:47:35.021542 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:47:35.027706 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8403 12:47:35.031422 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8404 12:47:35.034621 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8405 12:47:35.037806 Total UI for P1: 0, mck2ui 16
8406 12:47:35.041371 best dqsien dly found for B0: ( 1, 9, 6)
8407 12:47:35.047900 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8408 12:47:35.051110 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 12:47:35.054458 Total UI for P1: 0, mck2ui 16
8410 12:47:35.058208 best dqsien dly found for B1: ( 1, 9, 12)
8411 12:47:35.061383 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8412 12:47:35.064664 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8413 12:47:35.064762
8414 12:47:35.068262 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8415 12:47:35.071252 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8416 12:47:35.074502 [Gating] SW calibration Done
8417 12:47:35.074593 ==
8418 12:47:35.078019 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 12:47:35.081161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 12:47:35.084653 ==
8421 12:47:35.084789 RX Vref Scan: 0
8422 12:47:35.084863
8423 12:47:35.087946 RX Vref 0 -> 0, step: 1
8424 12:47:35.088079
8425 12:47:35.088149 RX Delay 0 -> 252, step: 8
8426 12:47:35.094995 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8427 12:47:35.098075 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8428 12:47:35.101510 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8429 12:47:35.105084 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8430 12:47:35.108386 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8431 12:47:35.111509 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8432 12:47:35.117900 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8433 12:47:35.121500 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8434 12:47:35.124650 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8435 12:47:35.127976 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8436 12:47:35.131553 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8437 12:47:35.138016 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8438 12:47:35.141237 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8439 12:47:35.144552 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8440 12:47:35.148191 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8441 12:47:35.151358 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8442 12:47:35.154468 ==
8443 12:47:35.158299 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 12:47:35.161365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 12:47:35.161464 ==
8446 12:47:35.161537 DQS Delay:
8447 12:47:35.164742 DQS0 = 0, DQS1 = 0
8448 12:47:35.164842 DQM Delay:
8449 12:47:35.167854 DQM0 = 139, DQM1 = 130
8450 12:47:35.167967 DQ Delay:
8451 12:47:35.171140 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8452 12:47:35.174617 DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =135
8453 12:47:35.178013 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8454 12:47:35.181500 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8455 12:47:35.181642
8456 12:47:35.181759
8457 12:47:35.181864 ==
8458 12:47:35.184794 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 12:47:35.191191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 12:47:35.191369 ==
8461 12:47:35.191468
8462 12:47:35.191564
8463 12:47:35.191650 TX Vref Scan disable
8464 12:47:35.195019 == TX Byte 0 ==
8465 12:47:35.198101 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8466 12:47:35.204692 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8467 12:47:35.204908 == TX Byte 1 ==
8468 12:47:35.208201 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8469 12:47:35.214940 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8470 12:47:35.215144 ==
8471 12:47:35.218270 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 12:47:35.221290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 12:47:35.221487 ==
8474 12:47:35.233562
8475 12:47:35.237050 TX Vref early break, caculate TX vref
8476 12:47:35.240144 TX Vref=16, minBit 8, minWin=22, winSum=368
8477 12:47:35.243889 TX Vref=18, minBit 15, minWin=22, winSum=384
8478 12:47:35.247320 TX Vref=20, minBit 9, minWin=23, winSum=388
8479 12:47:35.249949 TX Vref=22, minBit 15, minWin=23, winSum=403
8480 12:47:35.253387 TX Vref=24, minBit 15, minWin=23, winSum=407
8481 12:47:35.260278 TX Vref=26, minBit 15, minWin=24, winSum=419
8482 12:47:35.263543 TX Vref=28, minBit 10, minWin=25, winSum=425
8483 12:47:35.266814 TX Vref=30, minBit 10, minWin=24, winSum=420
8484 12:47:35.270072 TX Vref=32, minBit 10, minWin=23, winSum=410
8485 12:47:35.273367 TX Vref=34, minBit 10, minWin=23, winSum=398
8486 12:47:35.280341 [TxChooseVref] Worse bit 10, Min win 25, Win sum 425, Final Vref 28
8487 12:47:35.280479
8488 12:47:35.283251 Final TX Range 0 Vref 28
8489 12:47:35.283371
8490 12:47:35.283469 ==
8491 12:47:35.286648 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 12:47:35.289706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 12:47:35.293104 ==
8494 12:47:35.293219
8495 12:47:35.293290
8496 12:47:35.293354 TX Vref Scan disable
8497 12:47:35.300129 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8498 12:47:35.300257 == TX Byte 0 ==
8499 12:47:35.303327 u2DelayCellOfst[0]=17 cells (5 PI)
8500 12:47:35.306523 u2DelayCellOfst[1]=10 cells (3 PI)
8501 12:47:35.310053 u2DelayCellOfst[2]=0 cells (0 PI)
8502 12:47:35.313256 u2DelayCellOfst[3]=3 cells (1 PI)
8503 12:47:35.316696 u2DelayCellOfst[4]=6 cells (2 PI)
8504 12:47:35.320000 u2DelayCellOfst[5]=20 cells (6 PI)
8505 12:47:35.323348 u2DelayCellOfst[6]=17 cells (5 PI)
8506 12:47:35.326251 u2DelayCellOfst[7]=6 cells (2 PI)
8507 12:47:35.329551 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8508 12:47:35.332982 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8509 12:47:35.336588 == TX Byte 1 ==
8510 12:47:35.339745 u2DelayCellOfst[8]=0 cells (0 PI)
8511 12:47:35.342901 u2DelayCellOfst[9]=3 cells (1 PI)
8512 12:47:35.346299 u2DelayCellOfst[10]=10 cells (3 PI)
8513 12:47:35.346437 u2DelayCellOfst[11]=6 cells (2 PI)
8514 12:47:35.349829 u2DelayCellOfst[12]=17 cells (5 PI)
8515 12:47:35.352800 u2DelayCellOfst[13]=17 cells (5 PI)
8516 12:47:35.356445 u2DelayCellOfst[14]=17 cells (5 PI)
8517 12:47:35.359622 u2DelayCellOfst[15]=17 cells (5 PI)
8518 12:47:35.366170 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8519 12:47:35.369484 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8520 12:47:35.369622 DramC Write-DBI on
8521 12:47:35.369693 ==
8522 12:47:35.373052 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 12:47:35.379865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 12:47:35.379989 ==
8525 12:47:35.380060
8526 12:47:35.380122
8527 12:47:35.382729 TX Vref Scan disable
8528 12:47:35.382823 == TX Byte 0 ==
8529 12:47:35.389470 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8530 12:47:35.389617 == TX Byte 1 ==
8531 12:47:35.392627 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8532 12:47:35.396044 DramC Write-DBI off
8533 12:47:35.396177
8534 12:47:35.396276 [DATLAT]
8535 12:47:35.399151 Freq=1600, CH1 RK0
8536 12:47:35.399263
8537 12:47:35.399359 DATLAT Default: 0xf
8538 12:47:35.402768 0, 0xFFFF, sum = 0
8539 12:47:35.402870 1, 0xFFFF, sum = 0
8540 12:47:35.405924 2, 0xFFFF, sum = 0
8541 12:47:35.406065 3, 0xFFFF, sum = 0
8542 12:47:35.409237 4, 0xFFFF, sum = 0
8543 12:47:35.409390 5, 0xFFFF, sum = 0
8544 12:47:35.412587 6, 0xFFFF, sum = 0
8545 12:47:35.412737 7, 0xFFFF, sum = 0
8546 12:47:35.415709 8, 0xFFFF, sum = 0
8547 12:47:35.415854 9, 0xFFFF, sum = 0
8548 12:47:35.419100 10, 0xFFFF, sum = 0
8549 12:47:35.422424 11, 0xFFFF, sum = 0
8550 12:47:35.422570 12, 0xFFFF, sum = 0
8551 12:47:35.425862 13, 0xFFFF, sum = 0
8552 12:47:35.425988 14, 0x0, sum = 1
8553 12:47:35.429388 15, 0x0, sum = 2
8554 12:47:35.429541 16, 0x0, sum = 3
8555 12:47:35.429651 17, 0x0, sum = 4
8556 12:47:35.432696 best_step = 15
8557 12:47:35.432832
8558 12:47:35.432956 ==
8559 12:47:35.435913 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 12:47:35.439185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 12:47:35.439322 ==
8562 12:47:35.442469 RX Vref Scan: 1
8563 12:47:35.442600
8564 12:47:35.445882 Set Vref Range= 24 -> 127
8565 12:47:35.446016
8566 12:47:35.446135 RX Vref 24 -> 127, step: 1
8567 12:47:35.446257
8568 12:47:35.449398 RX Delay 19 -> 252, step: 4
8569 12:47:35.449525
8570 12:47:35.452418 Set Vref, RX VrefLevel [Byte0]: 24
8571 12:47:35.455916 [Byte1]: 24
8572 12:47:35.456054
8573 12:47:35.459186 Set Vref, RX VrefLevel [Byte0]: 25
8574 12:47:35.462463 [Byte1]: 25
8575 12:47:35.466691
8576 12:47:35.466801 Set Vref, RX VrefLevel [Byte0]: 26
8577 12:47:35.469761 [Byte1]: 26
8578 12:47:35.474004
8579 12:47:35.474094 Set Vref, RX VrefLevel [Byte0]: 27
8580 12:47:35.477168 [Byte1]: 27
8581 12:47:35.481350
8582 12:47:35.485121 Set Vref, RX VrefLevel [Byte0]: 28
8583 12:47:35.488429 [Byte1]: 28
8584 12:47:35.488534
8585 12:47:35.491432 Set Vref, RX VrefLevel [Byte0]: 29
8586 12:47:35.494595 [Byte1]: 29
8587 12:47:35.494745
8588 12:47:35.498293 Set Vref, RX VrefLevel [Byte0]: 30
8589 12:47:35.501562 [Byte1]: 30
8590 12:47:35.501717
8591 12:47:35.504872 Set Vref, RX VrefLevel [Byte0]: 31
8592 12:47:35.508286 [Byte1]: 31
8593 12:47:35.512041
8594 12:47:35.512186 Set Vref, RX VrefLevel [Byte0]: 32
8595 12:47:35.515351 [Byte1]: 32
8596 12:47:35.519541
8597 12:47:35.519661 Set Vref, RX VrefLevel [Byte0]: 33
8598 12:47:35.522509 [Byte1]: 33
8599 12:47:35.526880
8600 12:47:35.527011 Set Vref, RX VrefLevel [Byte0]: 34
8601 12:47:35.530456 [Byte1]: 34
8602 12:47:35.534559
8603 12:47:35.534666 Set Vref, RX VrefLevel [Byte0]: 35
8604 12:47:35.537902 [Byte1]: 35
8605 12:47:35.541967
8606 12:47:35.542072 Set Vref, RX VrefLevel [Byte0]: 36
8607 12:47:35.545553 [Byte1]: 36
8608 12:47:35.549769
8609 12:47:35.549882 Set Vref, RX VrefLevel [Byte0]: 37
8610 12:47:35.552719 [Byte1]: 37
8611 12:47:35.557389
8612 12:47:35.557525 Set Vref, RX VrefLevel [Byte0]: 38
8613 12:47:35.560741 [Byte1]: 38
8614 12:47:35.564690
8615 12:47:35.564809 Set Vref, RX VrefLevel [Byte0]: 39
8616 12:47:35.567962 [Byte1]: 39
8617 12:47:35.572306
8618 12:47:35.572402 Set Vref, RX VrefLevel [Byte0]: 40
8619 12:47:35.575858 [Byte1]: 40
8620 12:47:35.579911
8621 12:47:35.580024 Set Vref, RX VrefLevel [Byte0]: 41
8622 12:47:35.583148 [Byte1]: 41
8623 12:47:35.587869
8624 12:47:35.587975 Set Vref, RX VrefLevel [Byte0]: 42
8625 12:47:35.590933 [Byte1]: 42
8626 12:47:35.595014
8627 12:47:35.595120 Set Vref, RX VrefLevel [Byte0]: 43
8628 12:47:35.598558 [Byte1]: 43
8629 12:47:35.602734
8630 12:47:35.602868 Set Vref, RX VrefLevel [Byte0]: 44
8631 12:47:35.606206 [Byte1]: 44
8632 12:47:35.610140
8633 12:47:35.610304 Set Vref, RX VrefLevel [Byte0]: 45
8634 12:47:35.613571 [Byte1]: 45
8635 12:47:35.617729
8636 12:47:35.617857 Set Vref, RX VrefLevel [Byte0]: 46
8637 12:47:35.621158 [Byte1]: 46
8638 12:47:35.625483
8639 12:47:35.625594 Set Vref, RX VrefLevel [Byte0]: 47
8640 12:47:35.628775 [Byte1]: 47
8641 12:47:35.633331
8642 12:47:35.633487 Set Vref, RX VrefLevel [Byte0]: 48
8643 12:47:35.636317 [Byte1]: 48
8644 12:47:35.640377
8645 12:47:35.640514 Set Vref, RX VrefLevel [Byte0]: 49
8646 12:47:35.643949 [Byte1]: 49
8647 12:47:35.648145
8648 12:47:35.648282 Set Vref, RX VrefLevel [Byte0]: 50
8649 12:47:35.651420 [Byte1]: 50
8650 12:47:35.655676
8651 12:47:35.655805 Set Vref, RX VrefLevel [Byte0]: 51
8652 12:47:35.658988 [Byte1]: 51
8653 12:47:35.663191
8654 12:47:35.663284 Set Vref, RX VrefLevel [Byte0]: 52
8655 12:47:35.666638 [Byte1]: 52
8656 12:47:35.671003
8657 12:47:35.671106 Set Vref, RX VrefLevel [Byte0]: 53
8658 12:47:35.674300 [Byte1]: 53
8659 12:47:35.678510
8660 12:47:35.678634 Set Vref, RX VrefLevel [Byte0]: 54
8661 12:47:35.681587 [Byte1]: 54
8662 12:47:35.686386
8663 12:47:35.686578 Set Vref, RX VrefLevel [Byte0]: 55
8664 12:47:35.689519 [Byte1]: 55
8665 12:47:35.693864
8666 12:47:35.693978 Set Vref, RX VrefLevel [Byte0]: 56
8667 12:47:35.697201 [Byte1]: 56
8668 12:47:35.701275
8669 12:47:35.701404 Set Vref, RX VrefLevel [Byte0]: 57
8670 12:47:35.704368 [Byte1]: 57
8671 12:47:35.708561
8672 12:47:35.708700 Set Vref, RX VrefLevel [Byte0]: 58
8673 12:47:35.711978 [Byte1]: 58
8674 12:47:35.716380
8675 12:47:35.716516 Set Vref, RX VrefLevel [Byte0]: 59
8676 12:47:35.719495 [Byte1]: 59
8677 12:47:35.723853
8678 12:47:35.723953 Set Vref, RX VrefLevel [Byte0]: 60
8679 12:47:35.726921 [Byte1]: 60
8680 12:47:35.731321
8681 12:47:35.731477 Set Vref, RX VrefLevel [Byte0]: 61
8682 12:47:35.734846 [Byte1]: 61
8683 12:47:35.739068
8684 12:47:35.739233 Set Vref, RX VrefLevel [Byte0]: 62
8685 12:47:35.742347 [Byte1]: 62
8686 12:47:35.746484
8687 12:47:35.746653 Set Vref, RX VrefLevel [Byte0]: 63
8688 12:47:35.750103 [Byte1]: 63
8689 12:47:35.754188
8690 12:47:35.754359 Set Vref, RX VrefLevel [Byte0]: 64
8691 12:47:35.757449 [Byte1]: 64
8692 12:47:35.761835
8693 12:47:35.762019 Set Vref, RX VrefLevel [Byte0]: 65
8694 12:47:35.764995 [Byte1]: 65
8695 12:47:35.769143
8696 12:47:35.769304 Set Vref, RX VrefLevel [Byte0]: 66
8697 12:47:35.772708 [Byte1]: 66
8698 12:47:35.776920
8699 12:47:35.777081 Set Vref, RX VrefLevel [Byte0]: 67
8700 12:47:35.780437 [Byte1]: 67
8701 12:47:35.784662
8702 12:47:35.784817 Set Vref, RX VrefLevel [Byte0]: 68
8703 12:47:35.787833 [Byte1]: 68
8704 12:47:35.791958
8705 12:47:35.792084 Set Vref, RX VrefLevel [Byte0]: 69
8706 12:47:35.795248 [Byte1]: 69
8707 12:47:35.799736
8708 12:47:35.799880 Set Vref, RX VrefLevel [Byte0]: 70
8709 12:47:35.803313 [Byte1]: 70
8710 12:47:35.807294
8711 12:47:35.807399 Set Vref, RX VrefLevel [Byte0]: 71
8712 12:47:35.810296 [Byte1]: 71
8713 12:47:35.814761
8714 12:47:35.814880 Set Vref, RX VrefLevel [Byte0]: 72
8715 12:47:35.818167 [Byte1]: 72
8716 12:47:35.822392
8717 12:47:35.822498 Set Vref, RX VrefLevel [Byte0]: 73
8718 12:47:35.825471 [Byte1]: 73
8719 12:47:35.829951
8720 12:47:35.830095 Set Vref, RX VrefLevel [Byte0]: 74
8721 12:47:35.833188 [Byte1]: 74
8722 12:47:35.837478
8723 12:47:35.837626 Set Vref, RX VrefLevel [Byte0]: 75
8724 12:47:35.841092 [Byte1]: 75
8725 12:47:35.845082
8726 12:47:35.848223 Final RX Vref Byte 0 = 60 to rank0
8727 12:47:35.848329 Final RX Vref Byte 1 = 66 to rank0
8728 12:47:35.851525 Final RX Vref Byte 0 = 60 to rank1
8729 12:47:35.855327 Final RX Vref Byte 1 = 66 to rank1==
8730 12:47:35.858406 Dram Type= 6, Freq= 0, CH_1, rank 0
8731 12:47:35.864805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 12:47:35.864976 ==
8733 12:47:35.865094 DQS Delay:
8734 12:47:35.868043 DQS0 = 0, DQS1 = 0
8735 12:47:35.868173 DQM Delay:
8736 12:47:35.868289 DQM0 = 135, DQM1 = 128
8737 12:47:35.871376 DQ Delay:
8738 12:47:35.874784 DQ0 =136, DQ1 =130, DQ2 =124, DQ3 =132
8739 12:47:35.878403 DQ4 =134, DQ5 =146, DQ6 =148, DQ7 =132
8740 12:47:35.881299 DQ8 =114, DQ9 =118, DQ10 =134, DQ11 =120
8741 12:47:35.885060 DQ12 =140, DQ13 =134, DQ14 =134, DQ15 =134
8742 12:47:35.885170
8743 12:47:35.885244
8744 12:47:35.885309
8745 12:47:35.888341 [DramC_TX_OE_Calibration] TA2
8746 12:47:35.891419 Original DQ_B0 (3 6) =30, OEN = 27
8747 12:47:35.894639 Original DQ_B1 (3 6) =30, OEN = 27
8748 12:47:35.897808 24, 0x0, End_B0=24 End_B1=24
8749 12:47:35.897905 25, 0x0, End_B0=25 End_B1=25
8750 12:47:35.901409 26, 0x0, End_B0=26 End_B1=26
8751 12:47:35.904549 27, 0x0, End_B0=27 End_B1=27
8752 12:47:35.907981 28, 0x0, End_B0=28 End_B1=28
8753 12:47:35.911342 29, 0x0, End_B0=29 End_B1=29
8754 12:47:35.911461 30, 0x0, End_B0=30 End_B1=30
8755 12:47:35.914757 31, 0x5151, End_B0=30 End_B1=30
8756 12:47:35.917826 Byte0 end_step=30 best_step=27
8757 12:47:35.921234 Byte1 end_step=30 best_step=27
8758 12:47:35.924612 Byte0 TX OE(2T, 0.5T) = (3, 3)
8759 12:47:35.927848 Byte1 TX OE(2T, 0.5T) = (3, 3)
8760 12:47:35.927988
8761 12:47:35.928089
8762 12:47:35.934303 [DQSOSCAuto] RK0, (LSB)MR18= 0x1827, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8763 12:47:35.937740 CH1 RK0: MR19=303, MR18=1827
8764 12:47:35.944136 CH1_RK0: MR19=0x303, MR18=0x1827, DQSOSC=390, MR23=63, INC=24, DEC=16
8765 12:47:35.944262
8766 12:47:35.947704 ----->DramcWriteLeveling(PI) begin...
8767 12:47:35.947807 ==
8768 12:47:35.950872 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 12:47:35.954324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 12:47:35.954430 ==
8771 12:47:35.957586 Write leveling (Byte 0): 24 => 24
8772 12:47:35.960780 Write leveling (Byte 1): 29 => 29
8773 12:47:35.964205 DramcWriteLeveling(PI) end<-----
8774 12:47:35.964301
8775 12:47:35.964368 ==
8776 12:47:35.967857 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 12:47:35.971184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 12:47:35.971282 ==
8779 12:47:35.974457 [Gating] SW mode calibration
8780 12:47:35.981094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8781 12:47:35.987668 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8782 12:47:35.990864 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 12:47:35.997892 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 12:47:36.000870 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8785 12:47:36.004042 1 4 12 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 1)
8786 12:47:36.010992 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 12:47:36.014197 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 12:47:36.017414 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 12:47:36.020794 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 12:47:36.027572 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 12:47:36.030806 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 12:47:36.034080 1 5 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 0)
8793 12:47:36.040736 1 5 12 | B1->B0 | 2424 3131 | 0 0 | (1 0) (0 0)
8794 12:47:36.044066 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 12:47:36.047517 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 12:47:36.053906 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 12:47:36.057327 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 12:47:36.060509 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 12:47:36.067057 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 12:47:36.070632 1 6 8 | B1->B0 | 3f3f 2424 | 0 0 | (0 0) (0 0)
8801 12:47:36.073873 1 6 12 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
8802 12:47:36.080573 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 12:47:36.084340 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 12:47:36.087046 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 12:47:36.093936 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 12:47:36.097112 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 12:47:36.100381 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 12:47:36.107204 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8809 12:47:36.110407 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8810 12:47:36.113665 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 12:47:36.120076 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 12:47:36.123649 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 12:47:36.126946 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 12:47:36.133388 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 12:47:36.136906 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:47:36.140197 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:47:36.147011 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:47:36.150075 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:47:36.153452 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 12:47:36.160246 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 12:47:36.163198 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 12:47:36.166951 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 12:47:36.170141 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 12:47:36.176889 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8825 12:47:36.180140 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8826 12:47:36.183222 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 12:47:36.186474 Total UI for P1: 0, mck2ui 16
8828 12:47:36.190274 best dqsien dly found for B0: ( 1, 9, 10)
8829 12:47:36.193358 Total UI for P1: 0, mck2ui 16
8830 12:47:36.196692 best dqsien dly found for B1: ( 1, 9, 10)
8831 12:47:36.199902 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8832 12:47:36.203712 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8833 12:47:36.203830
8834 12:47:36.209933 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8835 12:47:36.213604 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8836 12:47:36.216865 [Gating] SW calibration Done
8837 12:47:36.216998 ==
8838 12:47:36.219943 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 12:47:36.223186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 12:47:36.223320 ==
8841 12:47:36.223422 RX Vref Scan: 0
8842 12:47:36.226603
8843 12:47:36.226720 RX Vref 0 -> 0, step: 1
8844 12:47:36.226825
8845 12:47:36.229880 RX Delay 0 -> 252, step: 8
8846 12:47:36.233369 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8847 12:47:36.236695 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8848 12:47:36.240352 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8849 12:47:36.246823 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8850 12:47:36.250061 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8851 12:47:36.253288 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8852 12:47:36.256672 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8853 12:47:36.259736 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8854 12:47:36.266436 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8855 12:47:36.269543 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8856 12:47:36.273093 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8857 12:47:36.276189 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8858 12:47:36.283048 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8859 12:47:36.286245 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8860 12:47:36.289638 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8861 12:47:36.293371 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8862 12:47:36.293505 ==
8863 12:47:36.296485 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 12:47:36.303189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 12:47:36.303326 ==
8866 12:47:36.303454 DQS Delay:
8867 12:47:36.303547 DQS0 = 0, DQS1 = 0
8868 12:47:36.306203 DQM Delay:
8869 12:47:36.306352 DQM0 = 139, DQM1 = 132
8870 12:47:36.309793 DQ Delay:
8871 12:47:36.313150 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8872 12:47:36.316255 DQ4 =139, DQ5 =151, DQ6 =147, DQ7 =139
8873 12:47:36.319327 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8874 12:47:36.322715 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8875 12:47:36.322838
8876 12:47:36.322947
8877 12:47:36.323046 ==
8878 12:47:36.326250 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 12:47:36.329589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 12:47:36.329711 ==
8881 12:47:36.332739
8882 12:47:36.332915
8883 12:47:36.333046 TX Vref Scan disable
8884 12:47:36.336292 == TX Byte 0 ==
8885 12:47:36.339538 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8886 12:47:36.343231 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8887 12:47:36.346294 == TX Byte 1 ==
8888 12:47:36.349526 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8889 12:47:36.353312 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8890 12:47:36.353479 ==
8891 12:47:36.356283 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 12:47:36.363013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 12:47:36.363156 ==
8894 12:47:36.375586
8895 12:47:36.378981 TX Vref early break, caculate TX vref
8896 12:47:36.382259 TX Vref=16, minBit 9, minWin=22, winSum=382
8897 12:47:36.385475 TX Vref=18, minBit 13, minWin=22, winSum=392
8898 12:47:36.389222 TX Vref=20, minBit 13, minWin=23, winSum=401
8899 12:47:36.392384 TX Vref=22, minBit 9, minWin=23, winSum=409
8900 12:47:36.395601 TX Vref=24, minBit 9, minWin=25, winSum=417
8901 12:47:36.402120 TX Vref=26, minBit 13, minWin=24, winSum=422
8902 12:47:36.405888 TX Vref=28, minBit 10, minWin=25, winSum=421
8903 12:47:36.409080 TX Vref=30, minBit 9, minWin=25, winSum=416
8904 12:47:36.412161 TX Vref=32, minBit 6, minWin=25, winSum=409
8905 12:47:36.415802 TX Vref=34, minBit 10, minWin=24, winSum=402
8906 12:47:36.422379 TX Vref=36, minBit 10, minWin=23, winSum=393
8907 12:47:36.426023 [TxChooseVref] Worse bit 10, Min win 25, Win sum 421, Final Vref 28
8908 12:47:36.426126
8909 12:47:36.429329 Final TX Range 0 Vref 28
8910 12:47:36.429424
8911 12:47:36.429492 ==
8912 12:47:36.432368 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 12:47:36.435830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 12:47:36.435925 ==
8915 12:47:36.439049
8916 12:47:36.439138
8917 12:47:36.439204 TX Vref Scan disable
8918 12:47:36.445756 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8919 12:47:36.445904 == TX Byte 0 ==
8920 12:47:36.449001 u2DelayCellOfst[0]=13 cells (4 PI)
8921 12:47:36.452288 u2DelayCellOfst[1]=10 cells (3 PI)
8922 12:47:36.455641 u2DelayCellOfst[2]=0 cells (0 PI)
8923 12:47:36.459056 u2DelayCellOfst[3]=3 cells (1 PI)
8924 12:47:36.462317 u2DelayCellOfst[4]=6 cells (2 PI)
8925 12:47:36.465570 u2DelayCellOfst[5]=17 cells (5 PI)
8926 12:47:36.468905 u2DelayCellOfst[6]=17 cells (5 PI)
8927 12:47:36.472026 u2DelayCellOfst[7]=3 cells (1 PI)
8928 12:47:36.475490 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8929 12:47:36.478965 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8930 12:47:36.482051 == TX Byte 1 ==
8931 12:47:36.485661 u2DelayCellOfst[8]=0 cells (0 PI)
8932 12:47:36.488897 u2DelayCellOfst[9]=3 cells (1 PI)
8933 12:47:36.489035 u2DelayCellOfst[10]=10 cells (3 PI)
8934 12:47:36.491999 u2DelayCellOfst[11]=3 cells (1 PI)
8935 12:47:36.495703 u2DelayCellOfst[12]=13 cells (4 PI)
8936 12:47:36.498984 u2DelayCellOfst[13]=13 cells (4 PI)
8937 12:47:36.502236 u2DelayCellOfst[14]=17 cells (5 PI)
8938 12:47:36.505498 u2DelayCellOfst[15]=13 cells (4 PI)
8939 12:47:36.511910 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8940 12:47:36.515622 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8941 12:47:36.515749 DramC Write-DBI on
8942 12:47:36.515846 ==
8943 12:47:36.518806 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 12:47:36.525246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 12:47:36.525375 ==
8946 12:47:36.525443
8947 12:47:36.525504
8948 12:47:36.525564 TX Vref Scan disable
8949 12:47:36.529748 == TX Byte 0 ==
8950 12:47:36.532860 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8951 12:47:36.536241 == TX Byte 1 ==
8952 12:47:36.539274 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8953 12:47:36.542985 DramC Write-DBI off
8954 12:47:36.543108
8955 12:47:36.543205 [DATLAT]
8956 12:47:36.543322 Freq=1600, CH1 RK1
8957 12:47:36.543421
8958 12:47:36.545884 DATLAT Default: 0xf
8959 12:47:36.545996 0, 0xFFFF, sum = 0
8960 12:47:36.549476 1, 0xFFFF, sum = 0
8961 12:47:36.552665 2, 0xFFFF, sum = 0
8962 12:47:36.552772 3, 0xFFFF, sum = 0
8963 12:47:36.556440 4, 0xFFFF, sum = 0
8964 12:47:36.556604 5, 0xFFFF, sum = 0
8965 12:47:36.559504 6, 0xFFFF, sum = 0
8966 12:47:36.559634 7, 0xFFFF, sum = 0
8967 12:47:36.562895 8, 0xFFFF, sum = 0
8968 12:47:36.563077 9, 0xFFFF, sum = 0
8969 12:47:36.565966 10, 0xFFFF, sum = 0
8970 12:47:36.566101 11, 0xFFFF, sum = 0
8971 12:47:36.569356 12, 0xFFFF, sum = 0
8972 12:47:36.569506 13, 0xFFFF, sum = 0
8973 12:47:36.572593 14, 0x0, sum = 1
8974 12:47:36.572732 15, 0x0, sum = 2
8975 12:47:36.575840 16, 0x0, sum = 3
8976 12:47:36.575987 17, 0x0, sum = 4
8977 12:47:36.579209 best_step = 15
8978 12:47:36.579338
8979 12:47:36.579457 ==
8980 12:47:36.582371 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 12:47:36.585784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 12:47:36.585906 ==
8983 12:47:36.589206 RX Vref Scan: 0
8984 12:47:36.589313
8985 12:47:36.589411 RX Vref 0 -> 0, step: 1
8986 12:47:36.589488
8987 12:47:36.592427 RX Delay 19 -> 252, step: 4
8988 12:47:36.595631 iDelay=191, Bit 0, Center 138 (95 ~ 182) 88
8989 12:47:36.602602 iDelay=191, Bit 1, Center 130 (83 ~ 178) 96
8990 12:47:36.605913 iDelay=191, Bit 2, Center 122 (75 ~ 170) 96
8991 12:47:36.609103 iDelay=191, Bit 3, Center 132 (83 ~ 182) 100
8992 12:47:36.612423 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8993 12:47:36.615641 iDelay=191, Bit 5, Center 146 (103 ~ 190) 88
8994 12:47:36.618978 iDelay=191, Bit 6, Center 144 (99 ~ 190) 92
8995 12:47:36.625876 iDelay=191, Bit 7, Center 132 (83 ~ 182) 100
8996 12:47:36.628969 iDelay=191, Bit 8, Center 112 (63 ~ 162) 100
8997 12:47:36.632468 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8998 12:47:36.635741 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8999 12:47:36.638919 iDelay=191, Bit 11, Center 124 (71 ~ 178) 108
9000 12:47:36.645964 iDelay=191, Bit 12, Center 138 (87 ~ 190) 104
9001 12:47:36.649248 iDelay=191, Bit 13, Center 138 (87 ~ 190) 104
9002 12:47:36.652665 iDelay=191, Bit 14, Center 138 (91 ~ 186) 96
9003 12:47:36.655833 iDelay=191, Bit 15, Center 138 (87 ~ 190) 104
9004 12:47:36.655962 ==
9005 12:47:36.659035 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 12:47:36.665745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 12:47:36.665889 ==
9008 12:47:36.665990 DQS Delay:
9009 12:47:36.669161 DQS0 = 0, DQS1 = 0
9010 12:47:36.669289 DQM Delay:
9011 12:47:36.669386 DQM0 = 134, DQM1 = 129
9012 12:47:36.672222 DQ Delay:
9013 12:47:36.675883 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
9014 12:47:36.679180 DQ4 =134, DQ5 =146, DQ6 =144, DQ7 =132
9015 12:47:36.682336 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9016 12:47:36.685628 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
9017 12:47:36.685755
9018 12:47:36.685883
9019 12:47:36.685976
9020 12:47:36.688989 [DramC_TX_OE_Calibration] TA2
9021 12:47:36.692212 Original DQ_B0 (3 6) =30, OEN = 27
9022 12:47:36.696090 Original DQ_B1 (3 6) =30, OEN = 27
9023 12:47:36.699154 24, 0x0, End_B0=24 End_B1=24
9024 12:47:36.699282 25, 0x0, End_B0=25 End_B1=25
9025 12:47:36.702322 26, 0x0, End_B0=26 End_B1=26
9026 12:47:36.705683 27, 0x0, End_B0=27 End_B1=27
9027 12:47:36.708758 28, 0x0, End_B0=28 End_B1=28
9028 12:47:36.712056 29, 0x0, End_B0=29 End_B1=29
9029 12:47:36.712176 30, 0x0, End_B0=30 End_B1=30
9030 12:47:36.715820 31, 0x4141, End_B0=30 End_B1=30
9031 12:47:36.718788 Byte0 end_step=30 best_step=27
9032 12:47:36.722476 Byte1 end_step=30 best_step=27
9033 12:47:36.725641 Byte0 TX OE(2T, 0.5T) = (3, 3)
9034 12:47:36.728645 Byte1 TX OE(2T, 0.5T) = (3, 3)
9035 12:47:36.728787
9036 12:47:36.728859
9037 12:47:36.735620 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9038 12:47:36.738761 CH1 RK1: MR19=303, MR18=1C07
9039 12:47:36.745424 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9040 12:47:36.748917 [RxdqsGatingPostProcess] freq 1600
9041 12:47:36.752321 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9042 12:47:36.755364 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 12:47:36.758669 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 12:47:36.762153 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 12:47:36.765516 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 12:47:36.768876 best DQS0 dly(2T, 0.5T) = (1, 1)
9047 12:47:36.772225 best DQS1 dly(2T, 0.5T) = (1, 1)
9048 12:47:36.775584 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9049 12:47:36.778988 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9050 12:47:36.781998 Pre-setting of DQS Precalculation
9051 12:47:36.785274 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9052 12:47:36.791851 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9053 12:47:36.798525 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9054 12:47:36.801889
9055 12:47:36.801995
9056 12:47:36.802062 [Calibration Summary] 3200 Mbps
9057 12:47:36.805550 CH 0, Rank 0
9058 12:47:36.805641 SW Impedance : PASS
9059 12:47:36.808771 DUTY Scan : NO K
9060 12:47:36.811966 ZQ Calibration : PASS
9061 12:47:36.812120 Jitter Meter : NO K
9062 12:47:36.815185 CBT Training : PASS
9063 12:47:36.818535 Write leveling : PASS
9064 12:47:36.818660 RX DQS gating : PASS
9065 12:47:36.822141 RX DQ/DQS(RDDQC) : PASS
9066 12:47:36.825179 TX DQ/DQS : PASS
9067 12:47:36.825323 RX DATLAT : PASS
9068 12:47:36.828607 RX DQ/DQS(Engine): PASS
9069 12:47:36.831708 TX OE : PASS
9070 12:47:36.831853 All Pass.
9071 12:47:36.832029
9072 12:47:36.832144 CH 0, Rank 1
9073 12:47:36.835301 SW Impedance : PASS
9074 12:47:36.838902 DUTY Scan : NO K
9075 12:47:36.839040 ZQ Calibration : PASS
9076 12:47:36.841820 Jitter Meter : NO K
9077 12:47:36.841953 CBT Training : PASS
9078 12:47:36.845217 Write leveling : PASS
9079 12:47:36.848555 RX DQS gating : PASS
9080 12:47:36.848692 RX DQ/DQS(RDDQC) : PASS
9081 12:47:36.852208 TX DQ/DQS : PASS
9082 12:47:36.855423 RX DATLAT : PASS
9083 12:47:36.855530 RX DQ/DQS(Engine): PASS
9084 12:47:36.858518 TX OE : PASS
9085 12:47:36.858606 All Pass.
9086 12:47:36.858671
9087 12:47:36.861757 CH 1, Rank 0
9088 12:47:36.861845 SW Impedance : PASS
9089 12:47:36.865291 DUTY Scan : NO K
9090 12:47:36.868567 ZQ Calibration : PASS
9091 12:47:36.868661 Jitter Meter : NO K
9092 12:47:36.872019 CBT Training : PASS
9093 12:47:36.875665 Write leveling : PASS
9094 12:47:36.875763 RX DQS gating : PASS
9095 12:47:36.878647 RX DQ/DQS(RDDQC) : PASS
9096 12:47:36.882087 TX DQ/DQS : PASS
9097 12:47:36.882183 RX DATLAT : PASS
9098 12:47:36.885459 RX DQ/DQS(Engine): PASS
9099 12:47:36.885553 TX OE : PASS
9100 12:47:36.888521 All Pass.
9101 12:47:36.888609
9102 12:47:36.888675 CH 1, Rank 1
9103 12:47:36.891932 SW Impedance : PASS
9104 12:47:36.892069 DUTY Scan : NO K
9105 12:47:36.894988 ZQ Calibration : PASS
9106 12:47:36.898668 Jitter Meter : NO K
9107 12:47:36.898799 CBT Training : PASS
9108 12:47:36.901965 Write leveling : PASS
9109 12:47:36.905153 RX DQS gating : PASS
9110 12:47:36.905319 RX DQ/DQS(RDDQC) : PASS
9111 12:47:36.908358 TX DQ/DQS : PASS
9112 12:47:36.911786 RX DATLAT : PASS
9113 12:47:36.911990 RX DQ/DQS(Engine): PASS
9114 12:47:36.915070 TX OE : PASS
9115 12:47:36.915167 All Pass.
9116 12:47:36.915284
9117 12:47:36.918438 DramC Write-DBI on
9118 12:47:36.921926 PER_BANK_REFRESH: Hybrid Mode
9119 12:47:36.922024 TX_TRACKING: ON
9120 12:47:36.931686 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9121 12:47:36.938494 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9122 12:47:36.945364 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9123 12:47:36.948508 [FAST_K] Save calibration result to emmc
9124 12:47:36.951673 sync common calibartion params.
9125 12:47:36.955332 sync cbt_mode0:1, 1:1
9126 12:47:36.958264 dram_init: ddr_geometry: 2
9127 12:47:36.958360 dram_init: ddr_geometry: 2
9128 12:47:36.961569 dram_init: ddr_geometry: 2
9129 12:47:36.965351 0:dram_rank_size:100000000
9130 12:47:36.965446 1:dram_rank_size:100000000
9131 12:47:36.971789 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9132 12:47:36.974889 DFS_SHUFFLE_HW_MODE: ON
9133 12:47:36.978543 dramc_set_vcore_voltage set vcore to 725000
9134 12:47:36.981717 Read voltage for 1600, 0
9135 12:47:36.981812 Vio18 = 0
9136 12:47:36.981899 Vcore = 725000
9137 12:47:36.985416 Vdram = 0
9138 12:47:36.985507 Vddq = 0
9139 12:47:36.985595 Vmddr = 0
9140 12:47:36.988322 switch to 3200 Mbps bootup
9141 12:47:36.988411 [DramcRunTimeConfig]
9142 12:47:36.991798 PHYPLL
9143 12:47:36.991887 DPM_CONTROL_AFTERK: ON
9144 12:47:36.994883 PER_BANK_REFRESH: ON
9145 12:47:36.998562 REFRESH_OVERHEAD_REDUCTION: ON
9146 12:47:36.998657 CMD_PICG_NEW_MODE: OFF
9147 12:47:37.001607 XRTWTW_NEW_MODE: ON
9148 12:47:37.001697 XRTRTR_NEW_MODE: ON
9149 12:47:37.004884 TX_TRACKING: ON
9150 12:47:37.004975 RDSEL_TRACKING: OFF
9151 12:47:37.008127 DQS Precalculation for DVFS: ON
9152 12:47:37.011340 RX_TRACKING: OFF
9153 12:47:37.011457 HW_GATING DBG: ON
9154 12:47:37.015071 ZQCS_ENABLE_LP4: ON
9155 12:47:37.015165 RX_PICG_NEW_MODE: ON
9156 12:47:37.018375 TX_PICG_NEW_MODE: ON
9157 12:47:37.021453 ENABLE_RX_DCM_DPHY: ON
9158 12:47:37.021544 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9159 12:47:37.024985 DUMMY_READ_FOR_TRACKING: OFF
9160 12:47:37.028101 !!! SPM_CONTROL_AFTERK: OFF
9161 12:47:37.031441 !!! SPM could not control APHY
9162 12:47:37.031536 IMPEDANCE_TRACKING: ON
9163 12:47:37.034525 TEMP_SENSOR: ON
9164 12:47:37.034616 HW_SAVE_FOR_SR: OFF
9165 12:47:37.038369 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9166 12:47:37.041432 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9167 12:47:37.044708 Read ODT Tracking: ON
9168 12:47:37.047920 Refresh Rate DeBounce: ON
9169 12:47:37.048018 DFS_NO_QUEUE_FLUSH: ON
9170 12:47:37.051255 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9171 12:47:37.054611 ENABLE_DFS_RUNTIME_MRW: OFF
9172 12:47:37.058449 DDR_RESERVE_NEW_MODE: ON
9173 12:47:37.058549 MR_CBT_SWITCH_FREQ: ON
9174 12:47:37.061417 =========================
9175 12:47:37.080553 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9176 12:47:37.083655 dram_init: ddr_geometry: 2
9177 12:47:37.102015 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9178 12:47:37.105444 dram_init: dram init end (result: 0)
9179 12:47:37.111884 DRAM-K: Full calibration passed in 24537 msecs
9180 12:47:37.115229 MRC: failed to locate region type 0.
9181 12:47:37.115332 DRAM rank0 size:0x100000000,
9182 12:47:37.118471 DRAM rank1 size=0x100000000
9183 12:47:37.128476 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9184 12:47:37.135024 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9185 12:47:37.141848 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9186 12:47:37.148675 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9187 12:47:37.151813 DRAM rank0 size:0x100000000,
9188 12:47:37.155572 DRAM rank1 size=0x100000000
9189 12:47:37.155666 CBMEM:
9190 12:47:37.158677 IMD: root @ 0xfffff000 254 entries.
9191 12:47:37.162013 IMD: root @ 0xffffec00 62 entries.
9192 12:47:37.165695 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9193 12:47:37.168757 WARNING: RO_VPD is uninitialized or empty.
9194 12:47:37.175429 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9195 12:47:37.181898 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9196 12:47:37.194851 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9197 12:47:37.206082 BS: romstage times (exec / console): total (unknown) / 24032 ms
9198 12:47:37.206208
9199 12:47:37.206277
9200 12:47:37.216066 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9201 12:47:37.219579 ARM64: Exception handlers installed.
9202 12:47:37.222900 ARM64: Testing exception
9203 12:47:37.226198 ARM64: Done test exception
9204 12:47:37.226286 Enumerating buses...
9205 12:47:37.229373 Show all devs... Before device enumeration.
9206 12:47:37.232730 Root Device: enabled 1
9207 12:47:37.236184 CPU_CLUSTER: 0: enabled 1
9208 12:47:37.236284 CPU: 00: enabled 1
9209 12:47:37.239456 Compare with tree...
9210 12:47:37.239545 Root Device: enabled 1
9211 12:47:37.242593 CPU_CLUSTER: 0: enabled 1
9212 12:47:37.246334 CPU: 00: enabled 1
9213 12:47:37.246425 Root Device scanning...
9214 12:47:37.249348 scan_static_bus for Root Device
9215 12:47:37.252648 CPU_CLUSTER: 0 enabled
9216 12:47:37.255916 scan_static_bus for Root Device done
9217 12:47:37.259747 scan_bus: bus Root Device finished in 8 msecs
9218 12:47:37.259855 done
9219 12:47:37.266286 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9220 12:47:37.269274 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9221 12:47:37.276188 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9222 12:47:37.279379 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9223 12:47:37.282534 Allocating resources...
9224 12:47:37.282665 Reading resources...
9225 12:47:37.289357 Root Device read_resources bus 0 link: 0
9226 12:47:37.289508 DRAM rank0 size:0x100000000,
9227 12:47:37.292675 DRAM rank1 size=0x100000000
9228 12:47:37.296168 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9229 12:47:37.299314 CPU: 00 missing read_resources
9230 12:47:37.302477 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9231 12:47:37.309266 Root Device read_resources bus 0 link: 0 done
9232 12:47:37.309401 Done reading resources.
9233 12:47:37.315996 Show resources in subtree (Root Device)...After reading.
9234 12:47:37.318910 Root Device child on link 0 CPU_CLUSTER: 0
9235 12:47:37.322541 CPU_CLUSTER: 0 child on link 0 CPU: 00
9236 12:47:37.332404 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9237 12:47:37.332568 CPU: 00
9238 12:47:37.335644 Root Device assign_resources, bus 0 link: 0
9239 12:47:37.338982 CPU_CLUSTER: 0 missing set_resources
9240 12:47:37.342676 Root Device assign_resources, bus 0 link: 0 done
9241 12:47:37.345777 Done setting resources.
9242 12:47:37.352450 Show resources in subtree (Root Device)...After assigning values.
9243 12:47:37.356037 Root Device child on link 0 CPU_CLUSTER: 0
9244 12:47:37.359373 CPU_CLUSTER: 0 child on link 0 CPU: 00
9245 12:47:37.368957 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9246 12:47:37.369143 CPU: 00
9247 12:47:37.372171 Done allocating resources.
9248 12:47:37.375437 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9249 12:47:37.379061 Enabling resources...
9250 12:47:37.379211 done.
9251 12:47:37.385698 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9252 12:47:37.385871 Initializing devices...
9253 12:47:37.388690 Root Device init
9254 12:47:37.388862 init hardware done!
9255 12:47:37.392329 0x00000018: ctrlr->caps
9256 12:47:37.395557 52.000 MHz: ctrlr->f_max
9257 12:47:37.395707 0.400 MHz: ctrlr->f_min
9258 12:47:37.398689 0x40ff8080: ctrlr->voltages
9259 12:47:37.398841 sclk: 390625
9260 12:47:37.402011 Bus Width = 1
9261 12:47:37.402152 sclk: 390625
9262 12:47:37.405313 Bus Width = 1
9263 12:47:37.405453 Early init status = 3
9264 12:47:37.411851 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9265 12:47:37.415338 in-header: 03 fc 00 00 01 00 00 00
9266 12:47:37.415476 in-data: 00
9267 12:47:37.421683 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9268 12:47:37.425242 in-header: 03 fd 00 00 00 00 00 00
9269 12:47:37.428293 in-data:
9270 12:47:37.431725 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9271 12:47:37.435165 in-header: 03 fc 00 00 01 00 00 00
9272 12:47:37.438546 in-data: 00
9273 12:47:37.442131 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9274 12:47:37.445957 in-header: 03 fd 00 00 00 00 00 00
9275 12:47:37.449866 in-data:
9276 12:47:37.452870 [SSUSB] Setting up USB HOST controller...
9277 12:47:37.456066 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9278 12:47:37.459281 [SSUSB] phy power-on done.
9279 12:47:37.462956 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9280 12:47:37.469363 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9281 12:47:37.472983 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9282 12:47:37.479367 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9283 12:47:37.486280 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9284 12:47:37.493020 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9285 12:47:37.499581 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9286 12:47:37.506428 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9287 12:47:37.506587 SPM: binary array size = 0x9dc
9288 12:47:37.512882 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9289 12:47:37.519425 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9290 12:47:37.526139 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9291 12:47:37.529580 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9292 12:47:37.532664 configure_display: Starting display init
9293 12:47:37.569367 anx7625_power_on_init: Init interface.
9294 12:47:37.572587 anx7625_disable_pd_protocol: Disabled PD feature.
9295 12:47:37.576107 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9296 12:47:37.603647 anx7625_start_dp_work: Secure OCM version=00
9297 12:47:37.606903 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9298 12:47:37.621834 sp_tx_get_edid_block: EDID Block = 1
9299 12:47:37.724448 Extracted contents:
9300 12:47:37.727644 header: 00 ff ff ff ff ff ff 00
9301 12:47:37.731222 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9302 12:47:37.734374 version: 01 04
9303 12:47:37.737723 basic params: 95 1f 11 78 0a
9304 12:47:37.740706 chroma info: 76 90 94 55 54 90 27 21 50 54
9305 12:47:37.744381 established: 00 00 00
9306 12:47:37.750929 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9307 12:47:37.754242 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9308 12:47:37.760853 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9309 12:47:37.767518 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9310 12:47:37.774194 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9311 12:47:37.777356 extensions: 00
9312 12:47:37.777478 checksum: fb
9313 12:47:37.777588
9314 12:47:37.780544 Manufacturer: IVO Model 57d Serial Number 0
9315 12:47:37.784432 Made week 0 of 2020
9316 12:47:37.784552 EDID version: 1.4
9317 12:47:37.787221 Digital display
9318 12:47:37.790582 6 bits per primary color channel
9319 12:47:37.790717 DisplayPort interface
9320 12:47:37.794262 Maximum image size: 31 cm x 17 cm
9321 12:47:37.797509 Gamma: 220%
9322 12:47:37.797626 Check DPMS levels
9323 12:47:37.800376 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9324 12:47:37.807406 First detailed timing is preferred timing
9325 12:47:37.807528 Established timings supported:
9326 12:47:37.810609 Standard timings supported:
9327 12:47:37.814109 Detailed timings
9328 12:47:37.817324 Hex of detail: 383680a07038204018303c0035ae10000019
9329 12:47:37.820538 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9330 12:47:37.827079 0780 0798 07c8 0820 hborder 0
9331 12:47:37.830728 0438 043b 0447 0458 vborder 0
9332 12:47:37.833743 -hsync -vsync
9333 12:47:37.833823 Did detailed timing
9334 12:47:37.840554 Hex of detail: 000000000000000000000000000000000000
9335 12:47:37.840634 Manufacturer-specified data, tag 0
9336 12:47:37.847125 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9337 12:47:37.850476 ASCII string: InfoVision
9338 12:47:37.853686 Hex of detail: 000000fe00523134304e574635205248200a
9339 12:47:37.856914 ASCII string: R140NWF5 RH
9340 12:47:37.856996 Checksum
9341 12:47:37.860370 Checksum: 0xfb (valid)
9342 12:47:37.863907 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9343 12:47:37.867198 DSI data_rate: 832800000 bps
9344 12:47:37.873483 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9345 12:47:37.877070 anx7625_parse_edid: pixelclock(138800).
9346 12:47:37.879961 hactive(1920), hsync(48), hfp(24), hbp(88)
9347 12:47:37.883522 vactive(1080), vsync(12), vfp(3), vbp(17)
9348 12:47:37.886877 anx7625_dsi_config: config dsi.
9349 12:47:37.893455 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9350 12:47:37.906169 anx7625_dsi_config: success to config DSI
9351 12:47:37.910041 anx7625_dp_start: MIPI phy setup OK.
9352 12:47:37.913206 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9353 12:47:37.916448 mtk_ddp_mode_set invalid vrefresh 60
9354 12:47:37.919766 main_disp_path_setup
9355 12:47:37.919886 ovl_layer_smi_id_en
9356 12:47:37.923378 ovl_layer_smi_id_en
9357 12:47:37.923485 ccorr_config
9358 12:47:37.923576 aal_config
9359 12:47:37.926309 gamma_config
9360 12:47:37.926389 postmask_config
9361 12:47:37.929767 dither_config
9362 12:47:37.932960 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9363 12:47:37.939566 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9364 12:47:37.942825 Root Device init finished in 551 msecs
9365 12:47:37.942943 CPU_CLUSTER: 0 init
9366 12:47:37.952885 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9367 12:47:37.956143 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9368 12:47:37.959501 APU_MBOX 0x190000b0 = 0x10001
9369 12:47:37.962801 APU_MBOX 0x190001b0 = 0x10001
9370 12:47:37.966376 APU_MBOX 0x190005b0 = 0x10001
9371 12:47:37.969559 APU_MBOX 0x190006b0 = 0x10001
9372 12:47:37.972820 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9373 12:47:37.985516 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9374 12:47:37.997818 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9375 12:47:38.004262 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9376 12:47:38.016134 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9377 12:47:38.025270 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9378 12:47:38.028461 CPU_CLUSTER: 0 init finished in 81 msecs
9379 12:47:38.031754 Devices initialized
9380 12:47:38.035210 Show all devs... After init.
9381 12:47:38.035337 Root Device: enabled 1
9382 12:47:38.038511 CPU_CLUSTER: 0: enabled 1
9383 12:47:38.041873 CPU: 00: enabled 1
9384 12:47:38.045080 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9385 12:47:38.048261 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9386 12:47:38.051803 ELOG: NV offset 0x57f000 size 0x1000
9387 12:47:38.058420 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9388 12:47:38.064944 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9389 12:47:38.068068 ELOG: Event(17) added with size 13 at 2023-07-20 12:47:32 UTC
9390 12:47:38.071575 out: cmd=0x121: 03 db 21 01 00 00 00 00
9391 12:47:38.076526 in-header: 03 12 00 00 2c 00 00 00
9392 12:47:38.089634 in-data: 4d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9393 12:47:38.096643 ELOG: Event(A1) added with size 10 at 2023-07-20 12:47:32 UTC
9394 12:47:38.103071 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9395 12:47:38.106147 ELOG: Event(A0) added with size 9 at 2023-07-20 12:47:32 UTC
9396 12:47:38.113088 elog_add_boot_reason: Logged dev mode boot
9397 12:47:38.116843 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9398 12:47:38.119957 Finalize devices...
9399 12:47:38.120044 Devices finalized
9400 12:47:38.126212 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9401 12:47:38.129593 Writing coreboot table at 0xffe64000
9402 12:47:38.133433 0. 000000000010a000-0000000000113fff: RAMSTAGE
9403 12:47:38.136597 1. 0000000040000000-00000000400fffff: RAM
9404 12:47:38.139707 2. 0000000040100000-000000004032afff: RAMSTAGE
9405 12:47:38.146148 3. 000000004032b000-00000000545fffff: RAM
9406 12:47:38.149433 4. 0000000054600000-000000005465ffff: BL31
9407 12:47:38.153263 5. 0000000054660000-00000000ffe63fff: RAM
9408 12:47:38.156073 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9409 12:47:38.162675 7. 0000000100000000-000000023fffffff: RAM
9410 12:47:38.162802 Passing 5 GPIOs to payload:
9411 12:47:38.169318 NAME | PORT | POLARITY | VALUE
9412 12:47:38.173021 EC in RW | 0x000000aa | low | undefined
9413 12:47:38.179358 EC interrupt | 0x00000005 | low | undefined
9414 12:47:38.182650 TPM interrupt | 0x000000ab | high | undefined
9415 12:47:38.186335 SD card detect | 0x00000011 | high | undefined
9416 12:47:38.192697 speaker enable | 0x00000093 | high | undefined
9417 12:47:38.195747 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9418 12:47:38.199203 in-header: 03 f9 00 00 02 00 00 00
9419 12:47:38.199292 in-data: 02 00
9420 12:47:38.202634 ADC[4]: Raw value=901770 ID=7
9421 12:47:38.205942 ADC[3]: Raw value=213179 ID=1
9422 12:47:38.206030 RAM Code: 0x71
9423 12:47:38.209112 ADC[6]: Raw value=74502 ID=0
9424 12:47:38.212697 ADC[5]: Raw value=212810 ID=1
9425 12:47:38.212783 SKU Code: 0x1
9426 12:47:38.219425 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5bc8
9427 12:47:38.222439 coreboot table: 964 bytes.
9428 12:47:38.225818 IMD ROOT 0. 0xfffff000 0x00001000
9429 12:47:38.229168 IMD SMALL 1. 0xffffe000 0x00001000
9430 12:47:38.232345 RO MCACHE 2. 0xffffc000 0x00001104
9431 12:47:38.235577 CONSOLE 3. 0xfff7c000 0x00080000
9432 12:47:38.239011 FMAP 4. 0xfff7b000 0x00000452
9433 12:47:38.242222 TIME STAMP 5. 0xfff7a000 0x00000910
9434 12:47:38.245773 VBOOT WORK 6. 0xfff66000 0x00014000
9435 12:47:38.249236 RAMOOPS 7. 0xffe66000 0x00100000
9436 12:47:38.252329 COREBOOT 8. 0xffe64000 0x00002000
9437 12:47:38.252414 IMD small region:
9438 12:47:38.255375 IMD ROOT 0. 0xffffec00 0x00000400
9439 12:47:38.258680 VPD 1. 0xffffeba0 0x0000004c
9440 12:47:38.262390 MMC STATUS 2. 0xffffeb80 0x00000004
9441 12:47:38.269177 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9442 12:47:38.269305 Probing TPM: done!
9443 12:47:38.276011 Connected to device vid:did:rid of 1ae0:0028:00
9444 12:47:38.285848 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9445 12:47:38.289662 Initialized TPM device CR50 revision 0
9446 12:47:38.289795 Checking cr50 for pending updates
9447 12:47:38.295623 Reading cr50 TPM mode
9448 12:47:38.304176 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9449 12:47:38.310936 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9450 12:47:38.351138 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9451 12:47:38.354346 Checking segment from ROM address 0x40100000
9452 12:47:38.360604 Checking segment from ROM address 0x4010001c
9453 12:47:38.364028 Loading segment from ROM address 0x40100000
9454 12:47:38.364112 code (compression=0)
9455 12:47:38.374337 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9456 12:47:38.380698 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9457 12:47:38.380807 it's not compressed!
9458 12:47:38.387229 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9459 12:47:38.394061 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9460 12:47:38.411607 Loading segment from ROM address 0x4010001c
9461 12:47:38.411746 Entry Point 0x80000000
9462 12:47:38.414835 Loaded segments
9463 12:47:38.417927 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9464 12:47:38.424701 Jumping to boot code at 0x80000000(0xffe64000)
9465 12:47:38.431679 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9466 12:47:38.438115 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9467 12:47:38.446029 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9468 12:47:38.449224 Checking segment from ROM address 0x40100000
9469 12:47:38.452507 Checking segment from ROM address 0x4010001c
9470 12:47:38.459153 Loading segment from ROM address 0x40100000
9471 12:47:38.459267 code (compression=1)
9472 12:47:38.465748 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9473 12:47:38.475902 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9474 12:47:38.475990 using LZMA
9475 12:47:38.484488 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9476 12:47:38.490880 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9477 12:47:38.494301 Loading segment from ROM address 0x4010001c
9478 12:47:38.494389 Entry Point 0x54601000
9479 12:47:38.497643 Loaded segments
9480 12:47:38.501224 NOTICE: MT8192 bl31_setup
9481 12:47:38.507809 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9482 12:47:38.511179 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9483 12:47:38.514558 WARNING: region 0:
9484 12:47:38.518120 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 12:47:38.518239 WARNING: region 1:
9486 12:47:38.524656 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9487 12:47:38.527811 WARNING: region 2:
9488 12:47:38.531289 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9489 12:47:38.534310 WARNING: region 3:
9490 12:47:38.538260 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 12:47:38.541426 WARNING: region 4:
9492 12:47:38.544657 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9493 12:47:38.548179 WARNING: region 5:
9494 12:47:38.551289 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 12:47:38.554699 WARNING: region 6:
9496 12:47:38.557778 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 12:47:38.557909 WARNING: region 7:
9498 12:47:38.564936 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 12:47:38.571802 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9500 12:47:38.574861 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9501 12:47:38.577863 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9502 12:47:38.584827 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9503 12:47:38.588130 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9504 12:47:38.591159 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9505 12:47:38.597953 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9506 12:47:38.601283 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9507 12:47:38.604627 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9508 12:47:38.611226 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9509 12:47:38.614692 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9510 12:47:38.621302 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9511 12:47:38.624678 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9512 12:47:38.628123 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9513 12:47:38.634626 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9514 12:47:38.638043 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9515 12:47:38.641637 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9516 12:47:38.648297 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9517 12:47:38.651430 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9518 12:47:38.658021 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9519 12:47:38.661205 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9520 12:47:38.664473 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9521 12:47:38.671209 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9522 12:47:38.674747 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9523 12:47:38.677974 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9524 12:47:38.684832 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9525 12:47:38.688381 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9526 12:47:38.695045 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9527 12:47:38.698204 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9528 12:47:38.701282 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9529 12:47:38.708153 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9530 12:47:38.711250 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9531 12:47:38.714537 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9532 12:47:38.721483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9533 12:47:38.724570 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9534 12:47:38.728087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9535 12:47:38.731616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9536 12:47:38.738286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9537 12:47:38.741580 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9538 12:47:38.744912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9539 12:47:38.748402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9540 12:47:38.755197 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9541 12:47:38.758056 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9542 12:47:38.761803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9543 12:47:38.764909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9544 12:47:38.771498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9545 12:47:38.774857 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9546 12:47:38.778399 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9547 12:47:38.785019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9548 12:47:38.788233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9549 12:47:38.791394 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9550 12:47:38.798384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9551 12:47:38.801731 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9552 12:47:38.807993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9553 12:47:38.811586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9554 12:47:38.817993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9555 12:47:38.821410 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9556 12:47:38.825033 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9557 12:47:38.831400 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9558 12:47:38.835006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9559 12:47:38.841241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9560 12:47:38.845096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9561 12:47:38.851243 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9562 12:47:38.855273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9563 12:47:38.861621 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9564 12:47:38.864709 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9565 12:47:38.868090 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9566 12:47:38.874729 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9567 12:47:38.878145 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9568 12:47:38.884766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9569 12:47:38.887936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9570 12:47:38.891305 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9571 12:47:38.898142 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9572 12:47:38.901431 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9573 12:47:38.908199 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9574 12:47:38.911439 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9575 12:47:38.918273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9576 12:47:38.921290 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9577 12:47:38.928177 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9578 12:47:38.931605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9579 12:47:38.934736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9580 12:47:38.941253 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9581 12:47:38.944906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9582 12:47:38.951364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9583 12:47:38.955217 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9584 12:47:38.961328 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9585 12:47:38.964806 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9586 12:47:38.968203 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9587 12:47:38.974747 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9588 12:47:38.978129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9589 12:47:38.984672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9590 12:47:38.987952 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9591 12:47:38.995107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9592 12:47:38.998382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9593 12:47:39.001245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9594 12:47:39.008374 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9595 12:47:39.011758 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9596 12:47:39.014567 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9597 12:47:39.021461 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9598 12:47:39.024676 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9599 12:47:39.028332 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9600 12:47:39.034571 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9601 12:47:39.038290 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9602 12:47:39.041339 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9603 12:47:39.048068 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9604 12:47:39.051154 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9605 12:47:39.057591 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9606 12:47:39.061495 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9607 12:47:39.064656 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9608 12:47:39.071290 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9609 12:47:39.074472 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9610 12:47:39.080930 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9611 12:47:39.084705 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9612 12:47:39.087798 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9613 12:47:39.094771 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9614 12:47:39.098007 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9615 12:47:39.101180 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9616 12:47:39.107847 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9617 12:47:39.111135 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9618 12:47:39.114684 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9619 12:47:39.118001 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9620 12:47:39.124786 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9621 12:47:39.127889 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9622 12:47:39.131230 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9623 12:47:39.138306 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9624 12:47:39.141189 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9625 12:47:39.144584 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9626 12:47:39.151237 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9627 12:47:39.154581 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9628 12:47:39.161379 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9629 12:47:39.164490 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9630 12:47:39.167906 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9631 12:47:39.174887 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9632 12:47:39.178163 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9633 12:47:39.181316 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9634 12:47:39.188318 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9635 12:47:39.191340 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9636 12:47:39.198138 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9637 12:47:39.201501 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9638 12:47:39.204766 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9639 12:47:39.211379 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9640 12:47:39.214798 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9641 12:47:39.221506 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9642 12:47:39.224732 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9643 12:47:39.227958 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9644 12:47:39.234873 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9645 12:47:39.238019 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9646 12:47:39.241382 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9647 12:47:39.247980 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9648 12:47:39.251393 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9649 12:47:39.258038 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9650 12:47:39.261322 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9651 12:47:39.264961 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9652 12:47:39.271817 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9653 12:47:39.274876 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9654 12:47:39.281716 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9655 12:47:39.284892 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9656 12:47:39.288014 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9657 12:47:39.294780 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9658 12:47:39.298320 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9659 12:47:39.301614 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9660 12:47:39.308277 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9661 12:47:39.311398 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9662 12:47:39.318295 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9663 12:47:39.321712 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9664 12:47:39.325044 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9665 12:47:39.331988 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9666 12:47:39.335241 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9667 12:47:39.338564 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9668 12:47:39.344790 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9669 12:47:39.348196 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9670 12:47:39.355277 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9671 12:47:39.358384 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9672 12:47:39.361433 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9673 12:47:39.368273 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9674 12:47:39.371783 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9675 12:47:39.378161 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9676 12:47:39.381262 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9677 12:47:39.384734 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9678 12:47:39.391845 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9679 12:47:39.394784 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9680 12:47:39.398337 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9681 12:47:39.404698 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9682 12:47:39.408155 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9683 12:47:39.414518 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9684 12:47:39.417717 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9685 12:47:39.421193 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9686 12:47:39.427736 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9687 12:47:39.431103 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9688 12:47:39.437848 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9689 12:47:39.441449 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9690 12:47:39.448028 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9691 12:47:39.451156 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9692 12:47:39.454494 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9693 12:47:39.461047 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9694 12:47:39.464440 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9695 12:47:39.471082 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9696 12:47:39.474270 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9697 12:47:39.481355 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9698 12:47:39.484563 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9699 12:47:39.487931 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9700 12:47:39.494405 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9701 12:47:39.497678 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9702 12:47:39.504106 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9703 12:47:39.507409 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9704 12:47:39.510635 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9705 12:47:39.517667 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9706 12:47:39.521181 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9707 12:47:39.527625 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9708 12:47:39.530843 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9709 12:47:39.534246 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9710 12:47:39.540631 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9711 12:47:39.543971 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9712 12:47:39.550696 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9713 12:47:39.553988 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9714 12:47:39.557801 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9715 12:47:39.564430 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9716 12:47:39.567337 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9717 12:47:39.574175 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9718 12:47:39.577144 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9719 12:47:39.584205 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9720 12:47:39.587462 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9721 12:47:39.590626 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9722 12:47:39.597227 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9723 12:47:39.601026 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9724 12:47:39.607172 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9725 12:47:39.610805 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9726 12:47:39.617349 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9727 12:47:39.620522 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9728 12:47:39.623825 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9729 12:47:39.626850 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9730 12:47:39.633904 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9731 12:47:39.636853 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9732 12:47:39.640452 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9733 12:47:39.643563 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9734 12:47:39.650448 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9735 12:47:39.653510 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9736 12:47:39.660501 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9737 12:47:39.663628 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9738 12:47:39.667220 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9739 12:47:39.673737 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9740 12:47:39.677095 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9741 12:47:39.680447 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9742 12:47:39.687136 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9743 12:47:39.690227 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9744 12:47:39.693440 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9745 12:47:39.700126 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9746 12:47:39.703424 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9747 12:47:39.710383 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9748 12:47:39.713458 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9749 12:47:39.716605 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9750 12:47:39.723439 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9751 12:47:39.726907 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9752 12:47:39.730177 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9753 12:47:39.736882 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9754 12:47:39.739804 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9755 12:47:39.746632 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9756 12:47:39.750204 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9757 12:47:39.753475 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9758 12:47:39.759903 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9759 12:47:39.763176 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9760 12:47:39.766719 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9761 12:47:39.773347 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9762 12:47:39.776364 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9763 12:47:39.780046 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9764 12:47:39.786881 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9765 12:47:39.790217 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9766 12:47:39.796674 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9767 12:47:39.799696 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9768 12:47:39.803507 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9769 12:47:39.806609 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9770 12:47:39.809790 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9771 12:47:39.816190 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9772 12:47:39.819671 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9773 12:47:39.823282 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9774 12:47:39.826793 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9775 12:47:39.833137 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9776 12:47:39.836185 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9777 12:47:39.839893 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9778 12:47:39.842779 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9779 12:47:39.849573 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9780 12:47:39.852702 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9781 12:47:39.856177 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9782 12:47:39.862963 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9783 12:47:39.866410 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9784 12:47:39.872596 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9785 12:47:39.876161 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9786 12:47:39.882810 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9787 12:47:39.885975 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9788 12:47:39.889302 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9789 12:47:39.896145 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9790 12:47:39.899177 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9791 12:47:39.905943 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9792 12:47:39.909250 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9793 12:47:39.912487 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9794 12:47:39.919202 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9795 12:47:39.922442 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9796 12:47:39.929560 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9797 12:47:39.932716 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9798 12:47:39.935930 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9799 12:47:39.942721 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9800 12:47:39.945726 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9801 12:47:39.952242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9802 12:47:39.955703 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9803 12:47:39.962340 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9804 12:47:39.965695 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9805 12:47:39.969273 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9806 12:47:39.975629 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9807 12:47:39.979043 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9808 12:47:39.985538 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9809 12:47:39.988657 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9810 12:47:39.992158 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9811 12:47:39.999128 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9812 12:47:40.002141 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9813 12:47:40.009014 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9814 12:47:40.011921 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9815 12:47:40.015455 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9816 12:47:40.022071 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9817 12:47:40.025400 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9818 12:47:40.031975 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9819 12:47:40.035271 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9820 12:47:40.038336 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9821 12:47:40.045267 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9822 12:47:40.048438 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9823 12:47:40.054919 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9824 12:47:40.058361 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9825 12:47:40.064984 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9826 12:47:40.068437 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9827 12:47:40.071578 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9828 12:47:40.078297 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9829 12:47:40.081467 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9830 12:47:40.088200 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9831 12:47:40.091586 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9832 12:47:40.094931 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9833 12:47:40.101639 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9834 12:47:40.104643 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9835 12:47:40.111289 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9836 12:47:40.114818 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9837 12:47:40.118026 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9838 12:47:40.124861 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9839 12:47:40.127987 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9840 12:47:40.134817 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9841 12:47:40.137993 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9842 12:47:40.144509 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9843 12:47:40.148066 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9844 12:47:40.151302 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9845 12:47:40.157861 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9846 12:47:40.160906 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9847 12:47:40.167863 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9848 12:47:40.170979 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9849 12:47:40.174129 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9850 12:47:40.181402 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9851 12:47:40.184292 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9852 12:47:40.190858 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9853 12:47:40.194232 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9854 12:47:40.197342 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9855 12:47:40.204364 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9856 12:47:40.207534 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9857 12:47:40.214281 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9858 12:47:40.217560 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9859 12:47:40.224228 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9860 12:47:40.227405 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9861 12:47:40.230783 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9862 12:47:40.237575 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9863 12:47:40.241125 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9864 12:47:40.247454 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9865 12:47:40.250742 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9866 12:47:40.257505 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9867 12:47:40.260431 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9868 12:47:40.264099 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9869 12:47:40.270895 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9870 12:47:40.273735 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9871 12:47:40.280570 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9872 12:47:40.283818 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9873 12:47:40.290791 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9874 12:47:40.293979 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9875 12:47:40.300601 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9876 12:47:40.304036 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9877 12:47:40.307117 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9878 12:47:40.313693 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9879 12:47:40.316952 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9880 12:47:40.323808 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9881 12:47:40.326978 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9882 12:47:40.333938 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9883 12:47:40.337134 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9884 12:47:40.340232 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9885 12:47:40.347138 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9886 12:47:40.350243 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9887 12:47:40.357254 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9888 12:47:40.360137 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9889 12:47:40.367377 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9890 12:47:40.370516 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9891 12:47:40.376861 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9892 12:47:40.380259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9893 12:47:40.383879 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9894 12:47:40.390418 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9895 12:47:40.393764 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9896 12:47:40.400209 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9897 12:47:40.403816 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9898 12:47:40.410206 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9899 12:47:40.413585 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9900 12:47:40.416613 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9901 12:47:40.423348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9902 12:47:40.426535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9903 12:47:40.433460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9904 12:47:40.436709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9905 12:47:40.443400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9906 12:47:40.446356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9907 12:47:40.453205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9908 12:47:40.456493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9909 12:47:40.463289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9910 12:47:40.466628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9911 12:47:40.469679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9912 12:47:40.476574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9913 12:47:40.479664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9914 12:47:40.486276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9915 12:47:40.490169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9916 12:47:40.496561 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9917 12:47:40.500147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9918 12:47:40.506275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9919 12:47:40.509515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9920 12:47:40.516312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9921 12:47:40.519522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9922 12:47:40.526623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9923 12:47:40.529859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9924 12:47:40.536456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9925 12:47:40.539853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9926 12:47:40.546326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9927 12:47:40.549741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9928 12:47:40.556482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9929 12:47:40.559666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9930 12:47:40.566552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9931 12:47:40.570002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9932 12:47:40.576374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9933 12:47:40.579724 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9934 12:47:40.582868 INFO: [APUAPC] vio 0
9935 12:47:40.586301 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9936 12:47:40.592787 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9937 12:47:40.596170 INFO: [APUAPC] D0_APC_0: 0x400510
9938 12:47:40.596257 INFO: [APUAPC] D0_APC_1: 0x0
9939 12:47:40.599242 INFO: [APUAPC] D0_APC_2: 0x1540
9940 12:47:40.602395 INFO: [APUAPC] D0_APC_3: 0x0
9941 12:47:40.605939 INFO: [APUAPC] D1_APC_0: 0xffffffff
9942 12:47:40.609072 INFO: [APUAPC] D1_APC_1: 0xffffffff
9943 12:47:40.612504 INFO: [APUAPC] D1_APC_2: 0x3fffff
9944 12:47:40.615624 INFO: [APUAPC] D1_APC_3: 0x0
9945 12:47:40.619243 INFO: [APUAPC] D2_APC_0: 0xffffffff
9946 12:47:40.622761 INFO: [APUAPC] D2_APC_1: 0xffffffff
9947 12:47:40.625897 INFO: [APUAPC] D2_APC_2: 0x3fffff
9948 12:47:40.629123 INFO: [APUAPC] D2_APC_3: 0x0
9949 12:47:40.632171 INFO: [APUAPC] D3_APC_0: 0xffffffff
9950 12:47:40.635742 INFO: [APUAPC] D3_APC_1: 0xffffffff
9951 12:47:40.639069 INFO: [APUAPC] D3_APC_2: 0x3fffff
9952 12:47:40.642326 INFO: [APUAPC] D3_APC_3: 0x0
9953 12:47:40.645604 INFO: [APUAPC] D4_APC_0: 0xffffffff
9954 12:47:40.648806 INFO: [APUAPC] D4_APC_1: 0xffffffff
9955 12:47:40.652480 INFO: [APUAPC] D4_APC_2: 0x3fffff
9956 12:47:40.655596 INFO: [APUAPC] D4_APC_3: 0x0
9957 12:47:40.659184 INFO: [APUAPC] D5_APC_0: 0xffffffff
9958 12:47:40.662439 INFO: [APUAPC] D5_APC_1: 0xffffffff
9959 12:47:40.665594 INFO: [APUAPC] D5_APC_2: 0x3fffff
9960 12:47:40.668865 INFO: [APUAPC] D5_APC_3: 0x0
9961 12:47:40.672199 INFO: [APUAPC] D6_APC_0: 0xffffffff
9962 12:47:40.675882 INFO: [APUAPC] D6_APC_1: 0xffffffff
9963 12:47:40.679175 INFO: [APUAPC] D6_APC_2: 0x3fffff
9964 12:47:40.682247 INFO: [APUAPC] D6_APC_3: 0x0
9965 12:47:40.685455 INFO: [APUAPC] D7_APC_0: 0xffffffff
9966 12:47:40.689069 INFO: [APUAPC] D7_APC_1: 0xffffffff
9967 12:47:40.692239 INFO: [APUAPC] D7_APC_2: 0x3fffff
9968 12:47:40.695566 INFO: [APUAPC] D7_APC_3: 0x0
9969 12:47:40.699225 INFO: [APUAPC] D8_APC_0: 0xffffffff
9970 12:47:40.702360 INFO: [APUAPC] D8_APC_1: 0xffffffff
9971 12:47:40.705770 INFO: [APUAPC] D8_APC_2: 0x3fffff
9972 12:47:40.708701 INFO: [APUAPC] D8_APC_3: 0x0
9973 12:47:40.712478 INFO: [APUAPC] D9_APC_0: 0xffffffff
9974 12:47:40.715303 INFO: [APUAPC] D9_APC_1: 0xffffffff
9975 12:47:40.718903 INFO: [APUAPC] D9_APC_2: 0x3fffff
9976 12:47:40.721925 INFO: [APUAPC] D9_APC_3: 0x0
9977 12:47:40.725710 INFO: [APUAPC] D10_APC_0: 0xffffffff
9978 12:47:40.728717 INFO: [APUAPC] D10_APC_1: 0xffffffff
9979 12:47:40.731963 INFO: [APUAPC] D10_APC_2: 0x3fffff
9980 12:47:40.735310 INFO: [APUAPC] D10_APC_3: 0x0
9981 12:47:40.738725 INFO: [APUAPC] D11_APC_0: 0xffffffff
9982 12:47:40.742019 INFO: [APUAPC] D11_APC_1: 0xffffffff
9983 12:47:40.745230 INFO: [APUAPC] D11_APC_2: 0x3fffff
9984 12:47:40.749032 INFO: [APUAPC] D11_APC_3: 0x0
9985 12:47:40.752146 INFO: [APUAPC] D12_APC_0: 0xffffffff
9986 12:47:40.755200 INFO: [APUAPC] D12_APC_1: 0xffffffff
9987 12:47:40.758857 INFO: [APUAPC] D12_APC_2: 0x3fffff
9988 12:47:40.762094 INFO: [APUAPC] D12_APC_3: 0x0
9989 12:47:40.765254 INFO: [APUAPC] D13_APC_0: 0xffffffff
9990 12:47:40.768386 INFO: [APUAPC] D13_APC_1: 0xffffffff
9991 12:47:40.772156 INFO: [APUAPC] D13_APC_2: 0x3fffff
9992 12:47:40.775265 INFO: [APUAPC] D13_APC_3: 0x0
9993 12:47:40.778650 INFO: [APUAPC] D14_APC_0: 0xffffffff
9994 12:47:40.782010 INFO: [APUAPC] D14_APC_1: 0xffffffff
9995 12:47:40.785096 INFO: [APUAPC] D14_APC_2: 0x3fffff
9996 12:47:40.788359 INFO: [APUAPC] D14_APC_3: 0x0
9997 12:47:40.791785 INFO: [APUAPC] D15_APC_0: 0xffffffff
9998 12:47:40.795300 INFO: [APUAPC] D15_APC_1: 0xffffffff
9999 12:47:40.798723 INFO: [APUAPC] D15_APC_2: 0x3fffff
10000 12:47:40.801781 INFO: [APUAPC] D15_APC_3: 0x0
10001 12:47:40.801901 INFO: [APUAPC] APC_CON: 0x4
10002 12:47:40.805677 INFO: [NOCDAPC] D0_APC_0: 0x0
10003 12:47:40.808723 INFO: [NOCDAPC] D0_APC_1: 0x0
10004 12:47:40.811882 INFO: [NOCDAPC] D1_APC_0: 0x0
10005 12:47:40.814995 INFO: [NOCDAPC] D1_APC_1: 0xfff
10006 12:47:40.818611 INFO: [NOCDAPC] D2_APC_0: 0x0
10007 12:47:40.821963 INFO: [NOCDAPC] D2_APC_1: 0xfff
10008 12:47:40.825367 INFO: [NOCDAPC] D3_APC_0: 0x0
10009 12:47:40.828282 INFO: [NOCDAPC] D3_APC_1: 0xfff
10010 12:47:40.831792 INFO: [NOCDAPC] D4_APC_0: 0x0
10011 12:47:40.831889 INFO: [NOCDAPC] D4_APC_1: 0xfff
10012 12:47:40.834992 INFO: [NOCDAPC] D5_APC_0: 0x0
10013 12:47:40.838178 INFO: [NOCDAPC] D5_APC_1: 0xfff
10014 12:47:40.841970 INFO: [NOCDAPC] D6_APC_0: 0x0
10015 12:47:40.845107 INFO: [NOCDAPC] D6_APC_1: 0xfff
10016 12:47:40.848295 INFO: [NOCDAPC] D7_APC_0: 0x0
10017 12:47:40.852093 INFO: [NOCDAPC] D7_APC_1: 0xfff
10018 12:47:40.855347 INFO: [NOCDAPC] D8_APC_0: 0x0
10019 12:47:40.858457 INFO: [NOCDAPC] D8_APC_1: 0xfff
10020 12:47:40.861564 INFO: [NOCDAPC] D9_APC_0: 0x0
10021 12:47:40.865215 INFO: [NOCDAPC] D9_APC_1: 0xfff
10022 12:47:40.865298 INFO: [NOCDAPC] D10_APC_0: 0x0
10023 12:47:40.868338 INFO: [NOCDAPC] D10_APC_1: 0xfff
10024 12:47:40.871450 INFO: [NOCDAPC] D11_APC_0: 0x0
10025 12:47:40.875018 INFO: [NOCDAPC] D11_APC_1: 0xfff
10026 12:47:40.878225 INFO: [NOCDAPC] D12_APC_0: 0x0
10027 12:47:40.881382 INFO: [NOCDAPC] D12_APC_1: 0xfff
10028 12:47:40.884702 INFO: [NOCDAPC] D13_APC_0: 0x0
10029 12:47:40.888097 INFO: [NOCDAPC] D13_APC_1: 0xfff
10030 12:47:40.891237 INFO: [NOCDAPC] D14_APC_0: 0x0
10031 12:47:40.894654 INFO: [NOCDAPC] D14_APC_1: 0xfff
10032 12:47:40.897880 INFO: [NOCDAPC] D15_APC_0: 0x0
10033 12:47:40.901529 INFO: [NOCDAPC] D15_APC_1: 0xfff
10034 12:47:40.904676 INFO: [NOCDAPC] APC_CON: 0x4
10035 12:47:40.908144 INFO: [APUAPC] set_apusys_apc done
10036 12:47:40.911711 INFO: [DEVAPC] devapc_init done
10037 12:47:40.914517 INFO: GICv3 without legacy support detected.
10038 12:47:40.918211 INFO: ARM GICv3 driver initialized in EL3
10039 12:47:40.921474 INFO: Maximum SPI INTID supported: 639
10040 12:47:40.924439 INFO: BL31: Initializing runtime services
10041 12:47:40.931374 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10042 12:47:40.934941 INFO: SPM: enable CPC mode
10043 12:47:40.941016 INFO: mcdi ready for mcusys-off-idle and system suspend
10044 12:47:40.944430 INFO: BL31: Preparing for EL3 exit to normal world
10045 12:47:40.947629 INFO: Entry point address = 0x80000000
10046 12:47:40.951486 INFO: SPSR = 0x8
10047 12:47:40.956035
10048 12:47:40.956135
10049 12:47:40.956232
10050 12:47:40.959149 Starting depthcharge on Spherion...
10051 12:47:40.959252
10052 12:47:40.959351 Wipe memory regions:
10053 12:47:40.959443
10054 12:47:40.960113 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10055 12:47:40.960228 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10056 12:47:40.960311 Setting prompt string to ['asurada:']
10057 12:47:40.960393 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10058 12:47:40.962241 [0x00000040000000, 0x00000054600000)
10059 12:47:41.084661
10060 12:47:41.084800 [0x00000054660000, 0x00000080000000)
10061 12:47:41.731368
10062 12:47:41.731539 [0x000000821a7280, 0x000000ffe64000)
10063 12:47:42.089350
10064 12:47:42.089486 [0x00000100000000, 0x00000240000000)
10065 12:47:43.978777
10066 12:47:43.981920 Initializing XHCI USB controller at 0x11200000.
10067 12:47:45.020315
10068 12:47:45.023396 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10069 12:47:45.023551
10070 12:47:45.023719
10071 12:47:45.023863
10072 12:47:45.024252 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 12:47:45.124772 asurada: tftpboot 192.168.201.1 11118917/tftp-deploy-8e110p6p/kernel/image.itb 11118917/tftp-deploy-8e110p6p/kernel/cmdline
10075 12:47:45.125051 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 12:47:45.125239 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10077 12:47:45.129155 tftpboot 192.168.201.1 11118917/tftp-deploy-8e110p6p/kernel/image.itp-deploy-8e110p6p/kernel/cmdline
10078 12:47:45.129290
10079 12:47:45.129405 Waiting for link
10080 12:47:45.290020
10081 12:47:45.290230 R8152: Initializing
10082 12:47:45.290359
10083 12:47:45.293108 Version 9 (ocp_data = 6010)
10084 12:47:45.293259
10085 12:47:45.296426 R8152: Done initializing
10086 12:47:45.296580
10087 12:47:45.296698 Adding net device
10088 12:47:47.367448
10089 12:47:47.367607 done.
10090 12:47:47.367703
10091 12:47:47.367792 MAC: 00:e0:4c:72:2d:d6
10092 12:47:47.367873
10093 12:47:47.370411 Sending DHCP discover... done.
10094 12:47:47.370503
10095 12:47:47.374091 Waiting for reply... done.
10096 12:47:47.374179
10097 12:47:47.377246 Sending DHCP request... done.
10098 12:47:47.377332
10099 12:47:48.504855 Waiting for reply... done.
10100 12:47:48.505110
10101 12:47:48.505269 My ip is 192.168.201.21
10102 12:47:48.505421
10103 12:47:48.508363 The DHCP server ip is 192.168.201.1
10104 12:47:48.508514
10105 12:47:48.514690 TFTP server IP predefined by user: 192.168.201.1
10106 12:47:48.514784
10107 12:47:48.521613 Bootfile predefined by user: 11118917/tftp-deploy-8e110p6p/kernel/image.itb
10108 12:47:48.521705
10109 12:47:48.521774 Sending tftp read request... done.
10110 12:47:48.524808
10111 12:47:48.524889 Waiting for the transfer...
10112 12:47:48.524971
10113 12:47:48.776466 00000000 ################################################################
10114 12:47:48.776618
10115 12:47:49.023226 00080000 ################################################################
10116 12:47:49.023390
10117 12:47:49.268715 00100000 ################################################################
10118 12:47:49.268873
10119 12:47:49.510512 00180000 ################################################################
10120 12:47:49.510675
10121 12:47:49.750429 00200000 ################################################################
10122 12:47:49.750690
10123 12:47:49.998541 00280000 ################################################################
10124 12:47:49.998688
10125 12:47:50.246453 00300000 ################################################################
10126 12:47:50.246620
10127 12:47:50.490961 00380000 ################################################################
10128 12:47:50.491139
10129 12:47:50.731815 00400000 ################################################################
10130 12:47:50.732021
10131 12:47:50.972925 00480000 ################################################################
10132 12:47:50.973178
10133 12:47:51.217869 00500000 ################################################################
10134 12:47:51.218013
10135 12:47:51.461260 00580000 ################################################################
10136 12:47:51.461477
10137 12:47:51.705098 00600000 ################################################################
10138 12:47:51.705273
10139 12:47:51.947226 00680000 ################################################################
10140 12:47:51.947376
10141 12:47:52.189835 00700000 ################################################################
10142 12:47:52.189979
10143 12:47:52.430872 00780000 ################################################################
10144 12:47:52.431056
10145 12:47:52.675689 00800000 ################################################################
10146 12:47:52.675838
10147 12:47:52.926693 00880000 ################################################################
10148 12:47:52.926860
10149 12:47:53.173250 00900000 ################################################################
10150 12:47:53.173461
10151 12:47:53.412845 00980000 ################################################################
10152 12:47:53.413048
10153 12:47:53.658059 00a00000 ################################################################
10154 12:47:53.658253
10155 12:47:53.910116 00a80000 ################################################################
10156 12:47:53.910268
10157 12:47:54.151396 00b00000 ################################################################
10158 12:47:54.151534
10159 12:47:54.394660 00b80000 ################################################################
10160 12:47:54.394810
10161 12:47:54.639423 00c00000 ################################################################
10162 12:47:54.639563
10163 12:47:54.883242 00c80000 ################################################################
10164 12:47:54.883437
10165 12:47:55.126301 00d00000 ################################################################
10166 12:47:55.126476
10167 12:47:55.371690 00d80000 ################################################################
10168 12:47:55.371827
10169 12:47:55.616549 00e00000 ################################################################
10170 12:47:55.616748
10171 12:47:55.869488 00e80000 ################################################################
10172 12:47:55.869645
10173 12:47:56.116757 00f00000 ################################################################
10174 12:47:56.116964
10175 12:47:56.375345 00f80000 ################################################################
10176 12:47:56.375548
10177 12:47:56.629124 01000000 ################################################################
10178 12:47:56.629262
10179 12:47:56.885841 01080000 ################################################################
10180 12:47:56.885997
10181 12:47:57.148259 01100000 ################################################################
10182 12:47:57.148505
10183 12:47:57.404365 01180000 ################################################################
10184 12:47:57.404511
10185 12:47:57.925378 01200000 ################################################################
10186 12:47:57.925630
10187 12:47:57.925775 01280000 ################################################################
10188 12:47:57.925886
10189 12:47:58.165315 01300000 ################################################################
10190 12:47:58.165450
10191 12:47:58.414206 01380000 ################################################################
10192 12:47:58.414345
10193 12:47:58.754838 01400000 ################################################################
10194 12:47:58.754996
10195 12:47:58.908830 01480000 ################################################################
10196 12:47:58.909022
10197 12:47:59.150730 01500000 ################################################################
10198 12:47:59.150871
10199 12:47:59.397211 01580000 ################################################################
10200 12:47:59.397403
10201 12:47:59.640946 01600000 ################################################################
10202 12:47:59.641095
10203 12:47:59.890323 01680000 ################################################################
10204 12:47:59.890486
10205 12:48:00.146573 01700000 ################################################################
10206 12:48:00.146703
10207 12:48:00.403821 01780000 ################################################################
10208 12:48:00.403953
10209 12:48:00.656407 01800000 ################################################################
10210 12:48:00.656547
10211 12:48:00.919630 01880000 ################################################################
10212 12:48:00.919766
10213 12:48:01.174241 01900000 ################################################################
10214 12:48:01.174372
10215 12:48:01.433621 01980000 ################################################################
10216 12:48:01.433780
10217 12:48:01.695050 01a00000 ################################################################
10218 12:48:01.695240
10219 12:48:01.951718 01a80000 ################################################################
10220 12:48:01.951879
10221 12:48:02.208164 01b00000 ################################################################
10222 12:48:02.208305
10223 12:48:02.461854 01b80000 ################################################################
10224 12:48:02.461992
10225 12:48:02.721242 01c00000 ################################################################
10226 12:48:02.721382
10227 12:48:02.977015 01c80000 ################################################################
10228 12:48:02.977173
10229 12:48:03.235717 01d00000 ################################################################
10230 12:48:03.235908
10231 12:48:03.963982 01d80000 ################################################################
10232 12:48:03.964179
10233 12:48:03.964382 01e00000 ################################################################
10234 12:48:03.964514
10235 12:48:03.964626 01e80000 ############## done.
10236 12:48:03.964746
10237 12:48:03.964900 The bootfile was 32095918 bytes long.
10238 12:48:03.965047
10239 12:48:03.965163 Sending tftp read request... done.
10240 12:48:03.965276
10241 12:48:03.965388 Waiting for the transfer...
10242 12:48:03.965575
10243 12:48:03.965755 00000000 # done.
10244 12:48:03.965924
10245 12:48:03.966037 Command line loaded dynamically from TFTP file: 11118917/tftp-deploy-8e110p6p/kernel/cmdline
10246 12:48:03.966150
10247 12:48:03.980090 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10248 12:48:03.980278
10249 12:48:03.980407 Loading FIT.
10250 12:48:03.980523
10251 12:48:03.983213 Image ramdisk-1 has 21238782 bytes.
10252 12:48:03.983343
10253 12:48:03.986608 Image fdt-1 has 46924 bytes.
10254 12:48:03.986737
10255 12:48:03.989915 Image kernel-1 has 10808178 bytes.
10256 12:48:03.990038
10257 12:48:03.996709 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10258 12:48:03.996855
10259 12:48:04.016560 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10260 12:48:04.016686
10261 12:48:04.019765 Choosing best match conf-1 for compat google,spherion-rev2.
10262 12:48:04.024614
10263 12:48:04.029157 Connected to device vid:did:rid of 1ae0:0028:00
10264 12:48:04.036119
10265 12:48:04.039560 tpm_get_response: command 0x17b, return code 0x0
10266 12:48:04.039694
10267 12:48:04.042460 ec_init: CrosEC protocol v3 supported (256, 248)
10268 12:48:04.046759
10269 12:48:04.050238 tpm_cleanup: add release locality here.
10270 12:48:04.050348
10271 12:48:04.050444 Shutting down all USB controllers.
10272 12:48:04.053139
10273 12:48:04.053250 Removing current net device
10274 12:48:04.053346
10275 12:48:04.060087 Exiting depthcharge with code 4 at timestamp: 52434411
10276 12:48:04.060183
10277 12:48:04.063194 LZMA decompressing kernel-1 to 0x821a6718
10278 12:48:04.063282
10279 12:48:04.066677 LZMA decompressing kernel-1 to 0x40000000
10280 12:48:05.417943
10281 12:48:05.418098 jumping to kernel
10282 12:48:05.418501 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10283 12:48:05.418600 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10284 12:48:05.418676 Setting prompt string to ['Linux version [0-9]']
10285 12:48:05.418745 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10286 12:48:05.418812 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10287 12:48:05.499615
10288 12:48:05.502955 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10289 12:48:05.506677 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10290 12:48:05.506774 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10291 12:48:05.506867 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10292 12:48:05.506945 Using line separator: #'\n'#
10293 12:48:05.507008 No login prompt set.
10294 12:48:05.507071 Parsing kernel messages
10295 12:48:05.507128 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10296 12:48:05.507232 [login-action] Waiting for messages, (timeout 00:04:01)
10297 12:48:05.526444 [ 0.000000] Linux version 6.1.38-cip1 (KernelCI@build-j6766-arm64-gcc-10-defconfig-arm64-chromebook-9w8v6) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jul 20 12:35:57 UTC 2023
10298 12:48:05.529867 [ 0.000000] random: crng init done
10299 12:48:05.532792 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10300 12:48:05.536434 [ 0.000000] efi: UEFI not found.
10301 12:48:05.546299 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10302 12:48:05.552906 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10303 12:48:05.562749 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10304 12:48:05.572463 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10305 12:48:05.579038 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10306 12:48:05.585466 [ 0.000000] printk: bootconsole [mtk8250] enabled
10307 12:48:05.592427 [ 0.000000] NUMA: No NUMA configuration found
10308 12:48:05.599039 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10309 12:48:05.602192 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10310 12:48:05.605351 [ 0.000000] Zone ranges:
10311 12:48:05.612068 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10312 12:48:05.615786 [ 0.000000] DMA32 empty
10313 12:48:05.622194 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10314 12:48:05.625322 [ 0.000000] Movable zone start for each node
10315 12:48:05.628697 [ 0.000000] Early memory node ranges
10316 12:48:05.635402 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10317 12:48:05.641792 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10318 12:48:05.648999 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10319 12:48:05.655281 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10320 12:48:05.658454 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10321 12:48:05.668785 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10322 12:48:05.723732 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10323 12:48:05.730574 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10324 12:48:05.737364 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10325 12:48:05.740349 [ 0.000000] psci: probing for conduit method from DT.
10326 12:48:05.747050 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10327 12:48:05.750300 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10328 12:48:05.756888 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10329 12:48:05.760138 [ 0.000000] psci: SMC Calling Convention v1.2
10330 12:48:05.766862 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10331 12:48:05.770187 [ 0.000000] Detected VIPT I-cache on CPU0
10332 12:48:05.776882 [ 0.000000] CPU features: detected: GIC system register CPU interface
10333 12:48:05.783627 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10334 12:48:05.790200 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10335 12:48:05.796678 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10336 12:48:09.145942 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10337 12:48:09.146566 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10338 12:48:09.146740 [ 0.000000] alternatives: applying boot alternatives
10339 12:48:09.146872 [ 0.000000] Fallback order for Node 0: 0
10340 12:48:09.146989 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10341 12:48:09.147110 [ 0.000000] Policy zone: Normal
10342 12:48:09.147279 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10343 12:48:09.147410 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10344 12:48:09.147532 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10345 12:48:09.147649 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10346 12:48:09.147773 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10347 12:48:09.147917 <6>[ 0.000000] software IO TLB: area num 8.
10348 12:48:09.148034 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10349 12:48:09.148148 <6>[ 0.000000] Memory: 7949452K/8385536K available (17984K kernel code, 4098K rwdata, 16796K rodata, 8384K init, 615K bss, 403316K reserved, 32768K cma-reserved)
10350 12:48:09.148260 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10351 12:48:09.148374 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10352 12:48:09.148487 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10353 12:48:09.148600 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10354 12:48:09.148713 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10355 12:48:09.148850 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10356 12:48:09.148960 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10357 12:48:09.149072 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10358 12:48:09.149181 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10359 12:48:09.149290 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10360 12:48:09.149394 <6>[ 0.000000] GICv3: 608 SPIs implemented
10361 12:48:09.149502 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10362 12:48:09.149611 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10363 12:48:09.149721 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10364 12:48:09.149829 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10365 12:48:09.149945 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10366 12:48:09.150075 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10367 12:48:09.150204 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10368 12:48:09.150342 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10369 12:48:09.150455 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10370 12:48:09.150592 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10371 12:48:09.150712 <6>[ 0.009182] Console: colour dummy device 80x25
10372 12:48:09.150839 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10373 12:48:09.150978 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10374 12:48:09.151088 <6>[ 0.029223] LSM: Security Framework initializing
10375 12:48:09.151216 <6>[ 0.034160] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10376 12:48:09.151331 <6>[ 0.042020] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10377 12:48:09.151443 <6>[ 0.051442] cblist_init_generic: Setting adjustable number of callback queues.
10378 12:48:09.151570 <6>[ 0.058894] cblist_init_generic: Setting shift to 3 and lim to 1.
10379 12:48:09.151679 <6>[ 0.065233] cblist_init_generic: Setting shift to 3 and lim to 1.
10380 12:48:09.151819 <6>[ 0.071677] rcu: Hierarchical SRCU implementation.
10381 12:48:09.151937 <6>[ 0.076690] rcu: Max phase no-delay instances is 1000.
10382 12:48:09.152058 <6>[ 0.083708] EFI services will not be available.
10383 12:48:09.152183 <6>[ 0.088709] smp: Bringing up secondary CPUs ...
10384 12:48:09.152307 <6>[ 0.093760] Detected VIPT I-cache on CPU1
10385 12:48:09.152447 <6>[ 0.093830] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10386 12:48:09.152573 <6>[ 0.093859] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10387 12:48:09.152685 <6>[ 0.094196] Detected VIPT I-cache on CPU2
10388 12:48:09.152817 <6>[ 0.094250] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10389 12:48:09.153342 <6>[ 0.094267] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10390 12:48:09.153469 <6>[ 0.094523] Detected VIPT I-cache on CPU3
10391 12:48:09.153598 <6>[ 0.094570] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10392 12:48:09.153742 <6>[ 0.094584] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10393 12:48:09.153854 <6>[ 0.094890] CPU features: detected: Spectre-v4
10394 12:48:09.154010 <6>[ 0.094896] CPU features: detected: Spectre-BHB
10395 12:48:09.154167 <6>[ 0.094902] Detected PIPT I-cache on CPU4
10396 12:48:09.154290 <6>[ 0.094960] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10397 12:48:09.154399 <6>[ 0.094977] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10398 12:48:09.154512 <6>[ 0.095271] Detected PIPT I-cache on CPU5
10399 12:48:09.154627 <6>[ 0.095336] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10400 12:48:09.154739 <6>[ 0.095353] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10401 12:48:09.154852 <6>[ 0.095636] Detected PIPT I-cache on CPU6
10402 12:48:09.154969 <6>[ 0.095703] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10403 12:48:09.155083 <6>[ 0.095720] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10404 12:48:09.155197 <6>[ 0.096020] Detected PIPT I-cache on CPU7
10405 12:48:09.155305 <6>[ 0.096087] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10406 12:48:09.155412 <6>[ 0.096104] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10407 12:48:09.155526 <6>[ 0.096153] smp: Brought up 1 node, 8 CPUs
10408 12:48:09.155633 <6>[ 0.237434] SMP: Total of 8 processors activated.
10409 12:48:09.155694 <6>[ 0.242355] CPU features: detected: 32-bit EL0 Support
10410 12:48:09.155751 <6>[ 0.247717] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10411 12:48:09.155820 <6>[ 0.256517] CPU features: detected: Common not Private translations
10412 12:48:09.155891 <6>[ 0.262993] CPU features: detected: CRC32 instructions
10413 12:48:09.155974 <6>[ 0.268377] CPU features: detected: RCpc load-acquire (LDAPR)
10414 12:48:09.156057 <6>[ 0.274337] CPU features: detected: LSE atomic instructions
10415 12:48:09.156112 <6>[ 0.280118] CPU features: detected: Privileged Access Never
10416 12:48:09.156166 <6>[ 0.285898] CPU features: detected: RAS Extension Support
10417 12:48:09.156220 <6>[ 0.291507] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10418 12:48:09.156275 <6>[ 0.298726] CPU: All CPU(s) started at EL2
10419 12:48:09.156329 <6>[ 0.303042] alternatives: applying system-wide alternatives
10420 12:48:09.156383 <6>[ 0.313720] devtmpfs: initialized
10421 12:48:09.156437 <6>[ 0.322662] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10422 12:48:09.156492 <6>[ 0.332625] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10423 12:48:09.156546 <6>[ 0.340695] pinctrl core: initialized pinctrl subsystem
10424 12:48:09.156600 <6>[ 0.347363] DMI not present or invalid.
10425 12:48:09.156654 <6>[ 0.351772] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10426 12:48:09.156708 <6>[ 0.358640] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10427 12:48:09.156771 <6>[ 0.366221] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10428 12:48:09.156828 <6>[ 0.374443] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10429 12:48:09.156882 <6>[ 0.382685] audit: initializing netlink subsys (disabled)
10430 12:48:09.156937 <5>[ 0.388384] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10431 12:48:09.156992 <6>[ 0.389088] thermal_sys: Registered thermal governor 'step_wise'
10432 12:48:09.157047 <6>[ 0.396352] thermal_sys: Registered thermal governor 'power_allocator'
10433 12:48:09.157101 <6>[ 0.402608] cpuidle: using governor menu
10434 12:48:09.157155 <6>[ 0.413572] NET: Registered PF_QIPCRTR protocol family
10435 12:48:09.157209 <6>[ 0.419054] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10436 12:48:09.157264 <6>[ 0.426162] ASID allocator initialised with 32768 entries
10437 12:48:09.157318 <6>[ 0.432733] Serial: AMBA PL011 UART driver
10438 12:48:09.157372 <4>[ 0.441415] Trying to register duplicate clock ID: 134
10439 12:48:09.157425 <6>[ 0.498786] KASLR enabled
10440 12:48:09.157479 <6>[ 0.506541] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10441 12:48:09.157534 <6>[ 0.513558] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10442 12:48:09.157588 <6>[ 0.520048] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10443 12:48:09.157642 <6>[ 0.527053] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10444 12:48:09.157696 <6>[ 0.533542] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10445 12:48:09.157750 <6>[ 0.540546] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10446 12:48:09.157803 <6>[ 0.547034] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10447 12:48:09.158083 <6>[ 0.554041] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10448 12:48:09.158171 <6>[ 0.561506] ACPI: Interpreter disabled.
10449 12:48:09.158239 <6>[ 0.567967] iommu: Default domain type: Translated
10450 12:48:09.158302 <6>[ 0.573082] iommu: DMA domain TLB invalidation policy: strict mode
10451 12:48:09.158364 <5>[ 0.579751] SCSI subsystem initialized
10452 12:48:09.158424 <6>[ 0.584002] usbcore: registered new interface driver usbfs
10453 12:48:09.158482 <6>[ 0.589735] usbcore: registered new interface driver hub
10454 12:48:09.158540 <6>[ 0.595291] usbcore: registered new device driver usb
10455 12:48:09.158597 <6>[ 0.601394] pps_core: LinuxPPS API ver. 1 registered
10456 12:48:09.158654 <6>[ 0.606590] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10457 12:48:09.158711 <6>[ 0.615936] PTP clock support registered
10458 12:48:09.158766 <6>[ 0.620179] EDAC MC: Ver: 3.0.0
10459 12:48:09.158822 <6>[ 0.625332] FPGA manager framework
10460 12:48:09.158877 <6>[ 0.629009] Advanced Linux Sound Architecture Driver Initialized.
10461 12:48:09.158933 <6>[ 0.635775] vgaarb: loaded
10462 12:48:09.158988 <6>[ 0.638958] clocksource: Switched to clocksource arch_sys_counter
10463 12:48:09.159080 <5>[ 0.645414] VFS: Disk quotas dquot_6.6.0
10464 12:48:09.159168 <6>[ 0.649602] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10465 12:48:09.159255 <6>[ 0.656793] pnp: PnP ACPI: disabled
10466 12:48:09.159341 <6>[ 0.663513] NET: Registered PF_INET protocol family
10467 12:48:09.159428 <6>[ 0.669117] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10468 12:48:09.159516 <6>[ 0.681436] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10469 12:48:09.159604 <6>[ 0.690253] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10470 12:48:09.159691 <6>[ 0.698222] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10471 12:48:09.159779 <6>[ 0.706922] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10472 12:48:09.159866 <6>[ 0.716666] TCP: Hash tables configured (established 65536 bind 65536)
10473 12:48:09.159955 <6>[ 0.723527] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10474 12:48:09.160042 <6>[ 0.730728] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10475 12:48:09.160129 <6>[ 0.738431] NET: Registered PF_UNIX/PF_LOCAL protocol family
10476 12:48:09.160216 <6>[ 0.744593] RPC: Registered named UNIX socket transport module.
10477 12:48:09.160302 <6>[ 0.750750] RPC: Registered udp transport module.
10478 12:48:09.160389 <6>[ 0.755684] RPC: Registered tcp transport module.
10479 12:48:09.160475 <6>[ 0.760616] RPC: Registered tcp NFSv4.1 backchannel transport module.
10480 12:48:09.160561 <6>[ 0.767285] PCI: CLS 0 bytes, default 64
10481 12:48:09.160647 <6>[ 0.771689] Unpacking initramfs...
10482 12:48:09.160733 <6>[ 0.791066] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10483 12:48:09.160826 <6>[ 0.799746] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10484 12:48:09.160882 <6>[ 0.808508] kvm [1]: IPA Size Limit: 40 bits
10485 12:48:09.160937 <6>[ 0.813036] kvm [1]: GICv3: no GICV resource entry
10486 12:48:09.160992 <6>[ 0.818059] kvm [1]: disabling GICv2 emulation
10487 12:48:09.161046 <6>[ 0.822744] kvm [1]: GIC system register CPU interface enabled
10488 12:48:09.161100 <6>[ 0.828921] kvm [1]: vgic interrupt IRQ18
10489 12:48:09.161153 <6>[ 0.833289] kvm [1]: VHE mode initialized successfully
10490 12:48:09.161207 <5>[ 0.839727] Initialise system trusted keyrings
10491 12:48:09.161261 <6>[ 0.844547] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10492 12:48:09.161315 <6>[ 0.854757] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10493 12:48:09.161368 <5>[ 0.861182] NFS: Registering the id_resolver key type
10494 12:48:09.161422 <5>[ 0.866495] Key type id_resolver registered
10495 12:48:09.161476 <5>[ 0.870913] Key type id_legacy registered
10496 12:48:09.161530 <6>[ 0.875197] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10497 12:48:09.161584 <6>[ 0.882121] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10498 12:48:09.161638 <6>[ 0.889850] 9p: Installing v9fs 9p2000 file system support
10499 12:48:09.161693 <5>[ 0.928212] Key type asymmetric registered
10500 12:48:09.161747 <5>[ 0.932546] Asymmetric key parser 'x509' registered
10501 12:48:09.161801 <6>[ 0.937706] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10502 12:48:09.161855 <6>[ 0.945326] io scheduler mq-deadline registered
10503 12:48:09.161909 <6>[ 0.950090] io scheduler kyber registered
10504 12:48:09.161993 <6>[ 0.966916] EINJ: ACPI disabled.
10505 12:48:09.162074 <4>[ 0.991957] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10506 12:48:09.162132 <4>[ 1.002583] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10507 12:48:09.162187 <6>[ 1.023286] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10508 12:48:09.162541 <6>[ 1.031355] printk: console [ttyS0] disabled
10509 12:48:09.162656 <6>[ 1.056000] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10510 12:48:09.162755 <6>[ 1.065476] printk: console [ttyS0] enabled
10511 12:48:09.162845 <6>[ 1.065476] printk: console [ttyS0] enabled
10512 12:48:09.162932 <6>[ 1.074369] printk: bootconsole [mtk8250] disabled
10513 12:48:09.163020 <6>[ 1.074369] printk: bootconsole [mtk8250] disabled
10514 12:48:09.163107 <6>[ 1.085678] SuperH (H)SCI(F) driver initialized
10515 12:48:09.163200 <6>[ 1.090956] msm_serial: driver initialized
10516 12:48:09.163289 <6>[ 1.099925] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10517 12:48:09.163377 <6>[ 1.108489] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10518 12:48:09.163465 <6>[ 1.117033] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10519 12:48:09.163552 <6>[ 1.125661] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10520 12:48:09.163650 <6>[ 1.134367] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10521 12:48:09.163777 <6>[ 1.143089] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10522 12:48:09.163866 <6>[ 1.151631] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10523 12:48:09.163967 <6>[ 1.160423] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10524 12:48:09.164069 <6>[ 1.168967] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10525 12:48:09.164156 <6>[ 1.184667] loop: module loaded
10526 12:48:09.164243 <6>[ 1.190780] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10527 12:48:09.164329 <4>[ 1.214173] mtk-pmic-keys: Failed to locate of_node [id: -1]
10528 12:48:09.164415 <6>[ 1.220970] megasas: 07.719.03.00-rc1
10529 12:48:09.164501 <6>[ 1.230675] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10530 12:48:09.164588 <6>[ 1.238347] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10531 12:48:09.164675 <6>[ 1.255163] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10532 12:48:09.164771 <6>[ 1.305672] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10533 12:48:09.164899 <6>[ 1.661857] Freeing initrd memory: 20736K
10534 12:48:09.165045 <6>[ 1.677454] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10535 12:48:09.165158 <6>[ 1.688304] tun: Universal TUN/TAP device driver, 1.6
10536 12:48:09.165241 <6>[ 1.694350] thunder_xcv, ver 1.0
10537 12:48:09.165325 <6>[ 1.697851] thunder_bgx, ver 1.0
10538 12:48:09.165469 <6>[ 1.701346] nicpf, ver 1.0
10539 12:48:09.165555 <6>[ 1.705371] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10540 12:48:09.165610 <6>[ 1.712848] hns3: Copyright (c) 2017 Huawei Corporation.
10541 12:48:09.165664 <6>[ 1.718435] hclge is initializing
10542 12:48:09.165718 <6>[ 1.722015] e1000: Intel(R) PRO/1000 Network Driver
10543 12:48:09.165772 <6>[ 1.727144] e1000: Copyright (c) 1999-2006 Intel Corporation.
10544 12:48:09.165827 <6>[ 1.733159] e1000e: Intel(R) PRO/1000 Network Driver
10545 12:48:09.165880 <6>[ 1.738374] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10546 12:48:09.165981 <6>[ 1.744559] igb: Intel(R) Gigabit Ethernet Network Driver
10547 12:48:09.166049 <6>[ 1.750209] igb: Copyright (c) 2007-2014 Intel Corporation.
10548 12:48:09.166103 <6>[ 1.756044] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10549 12:48:09.166156 <6>[ 1.762562] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10550 12:48:09.166210 <6>[ 1.769022] sky2: driver version 1.30
10551 12:48:09.166264 <6>[ 1.774008] VFIO - User Level meta-driver version: 0.3
10552 12:48:09.166318 <6>[ 1.782192] usbcore: registered new interface driver usb-storage
10553 12:48:09.166402 <6>[ 1.788637] usbcore: registered new device driver onboard-usb-hub
10554 12:48:09.166487 <6>[ 1.797657] mt6397-rtc mt6359-rtc: registered as rtc0
10555 12:48:09.166540 <6>[ 1.803114] mt6397-rtc mt6359-rtc: setting system clock to 2023-07-20T12:48:02 UTC (1689857282)
10556 12:48:09.166595 <6>[ 1.812670] i2c_dev: i2c /dev entries driver
10557 12:48:09.166649 <6>[ 1.824269] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10558 12:48:09.166703 <6>[ 1.834477] sdhci: Secure Digital Host Controller Interface driver
10559 12:48:09.166757 <6>[ 1.840915] sdhci: Copyright(c) Pierre Ossman
10560 12:48:09.166812 <6>[ 1.846299] Synopsys Designware Multimedia Card Interface Driver
10561 12:48:09.166866 <6>[ 1.852937] mmc0: CQHCI version 5.10
10562 12:48:09.166964 <6>[ 1.853456] sdhci-pltfm: SDHCI platform and OF driver helper
10563 12:48:09.167034 <6>[ 1.864875] ledtrig-cpu: registered to indicate activity on CPUs
10564 12:48:09.167088 <6>[ 1.872171] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10565 12:48:09.167142 <6>[ 1.879556] usbcore: registered new interface driver usbhid
10566 12:48:09.167196 <6>[ 1.885384] usbhid: USB HID core driver
10567 12:48:09.167461 <6>[ 1.889614] spi_master spi0: will run message pump with realtime priority
10568 12:48:09.167527 <6>[ 1.930457] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10569 12:48:09.167587 <6>[ 1.945916] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10570 12:48:09.167646 <6>[ 1.959475] mmc0: Command Queue Engine enabled
10571 12:48:09.167702 <6>[ 1.964248] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10572 12:48:09.167759 <6>[ 1.971405] cros-ec-spi spi0.0: Chrome EC device registered
10573 12:48:09.167815 <6>[ 1.971732] mmcblk0: mmc0:0001 DA4128 116 GiB
10574 12:48:09.167871 <6>[ 1.988396] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10575 12:48:09.167927 <6>[ 1.995658] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10576 12:48:09.167983 <6>[ 2.001656] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10577 12:48:09.168038 <6>[ 2.007758] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10578 12:48:09.168094 <6>[ 2.015526] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10579 12:48:09.168149 <6>[ 2.026996] NET: Registered PF_PACKET protocol family
10580 12:48:09.168205 <6>[ 2.032453] 9pnet: Installing 9P2000 support
10581 12:48:09.168260 <5>[ 2.037035] Key type dns_resolver registered
10582 12:48:09.168315 <6>[ 2.042208] registered taskstats version 1
10583 12:48:09.168369 <5>[ 2.046638] Loading compiled-in X.509 certificates
10584 12:48:09.168425 <4>[ 2.073663] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 12:48:09.168480 <4>[ 2.084422] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 12:48:09.168536 <3>[ 2.097044] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10587 12:48:09.168592 <6>[ 2.112462] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10588 12:48:09.168647 <6>[ 2.119235] xhci-mtk 11200000.usb: xHCI Host Controller
10589 12:48:09.168702 <6>[ 2.124735] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10590 12:48:09.168765 <6>[ 2.132577] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10591 12:48:09.168836 <6>[ 2.142021] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10592 12:48:09.168890 <6>[ 2.148235] xhci-mtk 11200000.usb: xHCI Host Controller
10593 12:48:09.168944 <6>[ 2.153730] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10594 12:48:09.168998 <6>[ 2.161391] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10595 12:48:09.169052 <6>[ 2.169304] hub 1-0:1.0: USB hub found
10596 12:48:09.169104 <6>[ 2.173339] hub 1-0:1.0: 1 port detected
10597 12:48:09.169158 <6>[ 2.177685] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10598 12:48:09.169229 <6>[ 2.186494] hub 2-0:1.0: USB hub found
10599 12:48:09.169296 <6>[ 2.190530] hub 2-0:1.0: 1 port detected
10600 12:48:09.169350 <6>[ 2.197685] mtk-msdc 11f70000.mmc: Got CD GPIO
10601 12:48:09.169404 <6>[ 2.212314] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10602 12:48:09.169458 <6>[ 2.220467] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10603 12:48:09.169512 <4>[ 2.228455] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10604 12:48:09.169567 <6>[ 2.238150] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10605 12:48:09.169652 <6>[ 2.246241] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10606 12:48:09.169737 <6>[ 2.254298] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10607 12:48:09.169791 <6>[ 2.262217] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10608 12:48:09.169845 <6>[ 2.270078] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10609 12:48:09.169900 <6>[ 2.277906] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10610 12:48:09.169955 <6>[ 2.288643] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10611 12:48:09.170009 <6>[ 2.297013] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10612 12:48:09.170063 <6>[ 2.305412] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10613 12:48:09.170116 <6>[ 2.313761] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10614 12:48:09.170186 <6>[ 2.322136] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10615 12:48:09.170273 <6>[ 2.330485] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10616 12:48:09.170549 <6>[ 2.338855] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10617 12:48:09.170611 <6>[ 2.347202] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10618 12:48:09.170711 <6>[ 2.355568] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10619 12:48:09.170825 <6>[ 2.363913] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10620 12:48:09.170910 <6>[ 2.372258] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10621 12:48:09.170966 <6>[ 2.380603] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10622 12:48:09.171043 <6>[ 2.388947] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10623 12:48:09.171131 <6>[ 2.397292] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10624 12:48:09.171218 <6>[ 2.405637] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10625 12:48:09.171305 <6>[ 2.414553] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10626 12:48:09.171391 <6>[ 2.421991] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10627 12:48:09.171478 <6>[ 2.429015] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10628 12:48:09.171564 <6>[ 2.436112] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10629 12:48:09.171651 <6>[ 2.443386] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10630 12:48:09.171738 <6>[ 2.450301] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10631 12:48:09.171826 <6>[ 2.459443] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10632 12:48:09.171926 <6>[ 2.468603] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10633 12:48:09.172041 <6>[ 2.477920] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10634 12:48:09.172126 <6>[ 2.487397] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10635 12:48:09.172212 <6>[ 2.496878] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10636 12:48:09.172297 <6>[ 2.506007] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10637 12:48:09.172397 <6>[ 2.515481] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10638 12:48:09.172484 <6>[ 2.524609] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10639 12:48:09.172571 <6>[ 2.533914] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10640 12:48:09.172659 <6>[ 2.544081] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10641 12:48:09.172746 <6>[ 2.556027] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10642 12:48:09.172831 <6>[ 2.575252] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10643 12:48:09.172887 <6>[ 2.605845] hub 2-1:1.0: USB hub found
10644 12:48:09.172941 <6>[ 2.610248] hub 2-1:1.0: 3 ports detected
10645 12:48:09.172995 <6>[ 2.727230] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10646 12:48:09.173050 <6>[ 2.884976] hub 1-1:1.0: USB hub found
10647 12:48:09.173112 <6>[ 2.889396] hub 1-1:1.0: 4 ports detected
10648 12:48:09.203736 <6>[ 2.963485] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10649 12:48:09.447517 <6>[ 3.207233] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10650 12:48:09.580439 <6>[ 3.343422] hub 1-1.4:1.0: USB hub found
10651 12:48:09.583598 <6>[ 3.348078] hub 1-1.4:1.0: 2 ports detected
10652 12:48:09.879502 <6>[ 3.639237] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10653 12:48:10.071315 <6>[ 3.831233] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10654 12:48:21.092239 <6>[ 14.859828] ALSA device list:
10655 12:48:21.098637 <6>[ 14.863084] No soundcards found.
10656 12:48:21.110817 <6>[ 14.875468] Freeing unused kernel memory: 8384K
10657 12:48:21.114223 <6>[ 14.880344] Run /init as init process
10658 12:48:21.140037 Starting syslogd: OK
10659 12:48:21.144232 Starting klogd: OK
10660 12:48:21.152703 Running sysctl: OK
10661 12:48:21.159643 Populating /dev using udev: <30>[ 14.925505] udevd[184]: starting version 3.2.9
10662 12:48:21.168690 <27>[ 14.933319] udevd[184]: specified user 'tss' unknown
10663 12:48:21.175356 <27>[ 14.938719] udevd[184]: specified group 'tss' unknown
10664 12:48:21.178677 <30>[ 14.945072] udevd[185]: starting eudev-3.2.9
10665 12:48:21.208630 <27>[ 14.973202] udevd[185]: specified user 'tss' unknown
10666 12:48:21.215301 <27>[ 14.978592] udevd[185]: specified group 'tss' unknown
10667 12:48:21.398707 <6>[ 15.159853] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10668 12:48:21.413613 <6>[ 15.178259] remoteproc remoteproc0: scp is available
10669 12:48:21.420596 <6>[ 15.184723] remoteproc remoteproc0: powering up scp
10670 12:48:21.427178 <6>[ 15.185780] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10671 12:48:21.437269 <6>[ 15.189941] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10672 12:48:21.443934 <6>[ 15.198138] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10673 12:48:21.450211 <6>[ 15.206693] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10674 12:48:21.459884 <6>[ 15.214678] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10675 12:48:21.467579 <6>[ 15.231937] mc: Linux media interface: v0.10
10676 12:48:21.474303 <4>[ 15.233063] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10677 12:48:21.480620 <4>[ 15.244209] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10678 12:48:21.488604 <6>[ 15.253004] usbcore: registered new interface driver r8152
10679 12:48:21.498431 <3>[ 15.253119] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 12:48:21.505168 <6>[ 15.259599] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10681 12:48:21.511365 <3>[ 15.266923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 12:48:21.521593 <3>[ 15.282712] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 12:48:21.528205 <3>[ 15.291121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 12:48:21.538418 <3>[ 15.299303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 12:48:21.548269 <4>[ 15.308101] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10686 12:48:21.551083 <4>[ 15.308101] Fallback method does not support PEC.
10687 12:48:21.560968 <3>[ 15.309795] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 12:48:21.567613 <3>[ 15.330377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 12:48:21.574632 <6>[ 15.335327] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10690 12:48:21.584369 <6>[ 15.336336] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10691 12:48:21.587812 <6>[ 15.336343] pci_bus 0000:00: root bus resource [bus 00-ff]
10692 12:48:21.594551 <6>[ 15.336350] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10693 12:48:21.604985 <6>[ 15.336355] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10694 12:48:21.611907 <6>[ 15.336386] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10695 12:48:21.618323 <6>[ 15.336407] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10696 12:48:21.625276 <6>[ 15.336483] pci 0000:00:00.0: supports D1 D2
10697 12:48:21.631729 <6>[ 15.336487] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10698 12:48:21.638112 <6>[ 15.338025] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10699 12:48:21.644748 <6>[ 15.338269] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10700 12:48:21.654635 <6>[ 15.338320] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10701 12:48:21.661306 <6>[ 15.338352] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10702 12:48:21.668125 <6>[ 15.338371] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10703 12:48:21.671457 <6>[ 15.338527] pci 0000:01:00.0: supports D1 D2
10704 12:48:21.681640 <3>[ 15.340953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 12:48:21.688481 <3>[ 15.341008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 12:48:21.698613 <3>[ 15.341058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 12:48:21.705110 <3>[ 15.341066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 12:48:21.715031 <3>[ 15.341075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 12:48:21.722034 <3>[ 15.341137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 12:48:21.728951 <3>[ 15.341144] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 12:48:21.738661 <3>[ 15.341152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 12:48:21.745336 <3>[ 15.341439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 12:48:21.755126 <3>[ 15.341450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 12:48:21.761971 <3>[ 15.341480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 12:48:21.768304 <6>[ 15.346414] videodev: Linux video capture interface: v2.00
10716 12:48:21.775406 <6>[ 15.352674] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10717 12:48:21.785302 <6>[ 15.355151] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10718 12:48:21.792205 <6>[ 15.355162] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10719 12:48:21.795207 <6>[ 15.355163] remoteproc remoteproc0: remote processor scp is now up
10720 12:48:21.805079 <6>[ 15.362635] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10721 12:48:21.811615 <6>[ 15.379066] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10722 12:48:21.822069 <6>[ 15.384215] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10723 12:48:21.831777 <6>[ 15.389274] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10724 12:48:21.841651 <6>[ 15.394453] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10725 12:48:21.848281 <6>[ 15.400661] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10726 12:48:21.854923 <6>[ 15.400677] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10727 12:48:21.864537 <4>[ 15.409541] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10728 12:48:21.874414 <6>[ 15.415215] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10729 12:48:21.881316 <6>[ 15.415240] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10730 12:48:21.887978 <6>[ 15.415259] pci 0000:00:00.0: PCI bridge to [bus 01]
10731 12:48:21.894338 <4>[ 15.422908] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10732 12:48:21.901261 <6>[ 15.430346] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10733 12:48:21.907528 <6>[ 15.431167] usbcore: registered new interface driver cdc_ether
10734 12:48:21.914145 <6>[ 15.438281] usbcore: registered new interface driver r8153_ecm
10735 12:48:21.924157 <6>[ 15.439438] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10736 12:48:21.930634 <6>[ 15.441765] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10737 12:48:21.937796 <6>[ 15.443009] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10738 12:48:21.941015 <6>[ 15.451297] Bluetooth: Core ver 2.22
10739 12:48:21.950565 <3>[ 15.462162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10740 12:48:21.957130 <6>[ 15.462805] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10741 12:48:21.964129 <6>[ 15.463181] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10742 12:48:21.967462 <6>[ 15.467209] NET: Registered PF_BLUETOOTH protocol family
10743 12:48:21.973859 <6>[ 15.469107] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10744 12:48:21.987166 <6>[ 15.470880] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10745 12:48:21.993588 <6>[ 15.471312] usbcore: registered new interface driver uvcvideo
10746 12:48:22.000152 <5>[ 15.486253] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10747 12:48:22.007316 <6>[ 15.491298] Bluetooth: HCI device and connection manager initialized
10748 12:48:22.013676 <6>[ 15.492221] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10749 12:48:22.020140 <6>[ 15.507260] r8152 2-1.3:1.0 eth0: v1.12.13
10750 12:48:22.023555 <6>[ 15.507566] Bluetooth: HCI socket layer initialized
10751 12:48:24.041451 <5>[ 15.521952] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10752 12:48:24.041620 <6>[ 15.523710] Bluetooth: L2CAP socket layer initialized
10753 12:48:24.041715 <4>[ 15.531850] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10754 12:48:24.041790 <6>[ 15.537921] Bluetooth: SCO socket layer initialized
10755 12:48:24.041859 <6>[ 15.544381] cfg80211: failed to load regulatory.db
10756 12:48:24.041919 <3>[ 15.557706] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10757 12:48:24.041978 <6>[ 15.619522] usbcore: registered new interface driver btusb
10758 12:48:24.042035 <4>[ 15.643027] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10759 12:48:24.042125 <6>[ 15.662444] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10760 12:48:24.042210 <3>[ 15.664217] Bluetooth: hci0: Failed to load firmware file (-2)
10761 12:48:24.042283 <6>[ 15.672329] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10762 12:48:24.042362 <3>[ 15.678308] Bluetooth: hci0: Failed to set up firmware (-2)
10763 12:48:24.042433 <6>[ 15.704855] mt7921e 0000:01:00.0: ASIC revision: 79610010
10764 12:48:24.042495 <4>[ 15.707331] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10765 12:48:24.042569 <4>[ 15.806622] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10766 12:48:24.042629 done
10767 12:48:24.042719 Saving random seed: OK
10768 12:48:24.042807 Starting network: OK
10769 12:48:24.042908 Starting dropbear sshd: <6>[ 15.963218] NET: Registered PF_INET6 protocol family
10770 12:48:24.043007 <6>[ 15.970208] Segment Routing with IPv6
10771 12:48:24.043102 <6>[ 15.974164] In-situ OAM (IOAM) with IPv6
10772 12:48:24.043193 OK
10773 12:48:24.043288 /bin/sh: can't access tty; job control turned off
10774 12:48:24.043381 / # <4>[ 16.017522] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 12:48:24.043483 <4>[ 16.137513] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 12:48:24.043584 <4>[ 16.257468] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 12:48:24.043680 <4>[ 16.377485] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 12:48:24.043779 <4>[ 16.497520] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 12:48:24.043871 <4>[ 16.617502] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 12:48:24.043961 <4>[ 16.737488] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 12:48:24.044080 <4>[ 16.857540] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 12:48:24.044169 <4>[ 16.977486] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 12:48:24.044256 <3>[ 17.095426] mt7921e 0000:01:00.0: hardware init failed
10784 12:48:24.044658 Matched prompt #10: / #
10786 12:48:24.044978 Setting prompt string to ['/ #']
10787 12:48:24.045122 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10789 12:48:24.045453 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10790 12:48:24.045570 start: 2.2.6 expect-shell-connection (timeout 00:03:42) [common]
10791 12:48:24.045671 Setting prompt string to ['/ #']
10792 12:48:24.045761 Forcing a shell prompt, looking for ['/ #']
10794 12:48:24.096079
10795 12:48:24.096234 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10796 12:48:24.096347 Waiting using forced prompt support (timeout 00:02:30)
10797 12:48:24.101217
10798 12:48:24.101498 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10799 12:48:24.101623 start: 2.2.7 export-device-env (timeout 00:03:42) [common]
10800 12:48:24.101776 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10801 12:48:24.101894 end: 2.2 depthcharge-retry (duration 00:01:18) [common]
10802 12:48:24.102039 end: 2 depthcharge-action (duration 00:01:18) [common]
10803 12:48:24.102155 start: 3 lava-test-retry (timeout 00:01:00) [common]
10804 12:48:24.102240 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10805 12:48:24.102342 Using namespace: common
10807 12:48:24.202660 / # #
10808 12:48:24.202834 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10809 12:48:24.208227 #
10810 12:48:24.208538 Using /lava-11118917
10812 12:48:24.308911 / # export SHELL=/bin/sh
10813 12:48:24.314158 export SHELL=/bin/sh
10815 12:48:24.414662 / # . /lava-11118917/environment
10816 12:48:24.419677 . /lava-11118917/environment
10818 12:48:24.520249 / # /lava-11118917/bin/lava-test-runner /lava-11118917/0
10819 12:48:24.520407 Test shell timeout: 10s (minimum of the action and connection timeout)
10820 12:48:24.525588 /lava-11118917/bin/lava-test-runner /lava-11118917/0
10821 12:48:24.544004 + export 'TESTRUN_ID=0_dmesg'
10822 12:48:24.550446 +<8>[ 18.313654] <LAVA_SIGNAL_STARTRUN 0_dmesg 11118917_1.5.2.3.1>
10823 12:48:24.550704 Received signal: <STARTRUN> 0_dmesg 11118917_1.5.2.3.1
10824 12:48:24.550778 Starting test lava.0_dmesg (11118917_1.5.2.3.1)
10825 12:48:24.550864 Skipping test definition patterns.
10826 12:48:24.553653 cd /lava-11118917/0/tests/0_dmesg
10827 12:48:24.553760 + cat uuid
10828 12:48:24.557062 + UUID=11118917_1.5.2.3.1
10829 12:48:24.557146 + set +x
10830 12:48:24.563786 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10831 12:48:24.573493 <8>[ 18.333475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10832 12:48:24.573774 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10834 12:48:24.592010 <8>[ 18.353809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10835 12:48:24.592264 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10837 12:48:24.612645 <8>[ 18.374123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10838 12:48:24.612898 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10840 12:48:24.616070 + set +x
10841 12:48:24.619405 <8>[ 18.383648] <LAVA_SIGNAL_ENDRUN 0_dmesg 11118917_1.5.2.3.1>
10842 12:48:24.619716 Received signal: <ENDRUN> 0_dmesg 11118917_1.5.2.3.1
10843 12:48:24.619842 Ending use of test pattern.
10844 12:48:24.619954 Ending test lava.0_dmesg (11118917_1.5.2.3.1), duration 0.07
10846 12:48:24.623048 <LAVA_TEST_RUNNER EXIT>
10847 12:48:24.623353 ok: lava_test_shell seems to have completed
10848 12:48:24.623530 alert: pass
crit: pass
emerg: pass
10849 12:48:24.623682 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10850 12:48:24.623828 end: 3 lava-test-retry (duration 00:00:01) [common]
10851 12:48:24.623974 start: 4 lava-test-retry (timeout 00:01:00) [common]
10852 12:48:24.624121 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10853 12:48:24.624241 Using namespace: common
10855 12:48:24.724619 / # #
10856 12:48:24.724787 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10857 12:48:24.724948 Using /lava-11118917
10859 12:48:24.825316 export SHELL=/bin/sh
10860 12:48:24.825455 #
10862 12:48:24.925957 / # export SHELL=/bin/sh. /lava-11118917/environment
10863 12:48:24.926092
10865 12:48:25.026565 / # . /lava-11118917/environment/lava-11118917/bin/lava-test-runner /lava-11118917/1
10866 12:48:25.026761 Test shell timeout: 10s (minimum of the action and connection timeout)
10867 12:48:25.026970
10868 12:48:25.031869 / # /lava-11118917/bin/lava-test-runner /lava-11118917/1
10869 12:48:25.049447 + export 'TESTRUN_ID=1_bootrr'
10870 12:48:25.055955 + <8>[ 18.819154] <LAVA_SIGNAL_STARTRUN 1_bootrr 11118917_1.5.2.3.5>
10871 12:48:25.056234 Received signal: <STARTRUN> 1_bootrr 11118917_1.5.2.3.5
10872 12:48:25.056352 Starting test lava.1_bootrr (11118917_1.5.2.3.5)
10873 12:48:25.056466 Skipping test definition patterns.
10874 12:48:25.059254 cd /lava-11118917/1/tests/1_bootrr
10875 12:48:25.059356 + cat uuid
10876 12:48:25.062818 + UUID=11118917_1.5.2.3.5
10877 12:48:25.062945 + set +x
10878 12:48:25.078681 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11118917/1/../bin:/sbin:/usr/sbin:/<8>[ 18.841442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10879 12:48:25.078967 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10881 12:48:25.082161 bin:/usr/bin'
10882 12:48:25.082253 + cd /opt/bootrr/libexec/bootrr
10883 12:48:25.085438 + sh helpers/bootrr-auto
10884 12:48:25.088701 /lava-11118917/1/../bin/lava-test-case
10885 12:48:25.098925 /lava-11118917/1/../bin/lava-t<8>[ 18.860797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10886 12:48:25.099209 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10888 12:48:25.102080 est-case
10889 12:48:25.105420 /usr/bin/tpm2_getcap
10890 12:48:25.137924 /lava-11118917/1/../bin/lava-test-case
10891 12:48:25.144653 <8>[ 18.906658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10892 12:48:25.144947 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10894 12:48:25.160432 /lava-11118917/1/../bin/lava-test-case
10895 12:48:25.167085 <8>[ 18.928460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10896 12:48:25.167358 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10898 12:48:25.179275 /lava-11118917/1/../bin/lava-test-case
10899 12:48:25.185847 <8>[ 18.947779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10900 12:48:25.186187 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10902 12:48:25.198013 /lava-11118917/1/../bin/lava-test-case
10903 12:48:25.204908 <8>[ 18.966678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10904 12:48:25.205160 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10906 12:48:25.217187 /lava-11118917/1/../bin/lava-test-case
10907 12:48:25.223452 <8>[ 18.985399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10908 12:48:25.223728 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10910 12:48:25.235203 /lava-11118917/1/../bin/lava-test-case
10911 12:48:25.241788 <8>[ 19.003298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10912 12:48:25.242089 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10914 12:48:25.251843 /lava-11118917/1/../bin/lava-test-case
10915 12:48:25.258256 <8>[ 19.019831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10916 12:48:25.258539 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10918 12:48:25.270438 /lava-11118917/1/../bin/lava-test-case
10919 12:48:25.277076 <8>[ 19.038287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10920 12:48:25.277348 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10922 12:48:25.286404 /lava-11118917/1/../bin/lava-test-case
10923 12:48:25.293034 <8>[ 19.054641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10924 12:48:25.293288 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10926 12:48:25.305681 /lava-11118917/1/../bin/lava-test-case
10927 12:48:25.312103 <8>[ 19.073496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10928 12:48:25.312371 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10930 12:48:25.325130 /lava-11118917/1/../bin/lava-test-case
10931 12:48:25.331935 <8>[ 19.093321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10932 12:48:25.332187 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10934 12:48:25.343501 /lava-11118917/1/../bin/lava-test-case
10935 12:48:25.349946 <8>[ 19.111713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10936 12:48:25.350208 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10938 12:48:25.362944 /lava-11118917/1/../bin/lava-test-case
10939 12:48:25.369545 <8>[ 19.131156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10940 12:48:25.369798 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10942 12:48:25.380297 /lava-11118917/1/../bin/lava-test-case
10943 12:48:25.386694 <8>[ 19.148443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10944 12:48:25.386945 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10946 12:48:25.398803 /lava-11118917/1/../bin/lava-test-case
10947 12:48:25.405183 <8>[ 19.166654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10948 12:48:25.405435 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10950 12:48:25.414893 /lava-11118917/1/../bin/lava-test-case
10951 12:48:25.421225 <8>[ 19.183289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10952 12:48:25.421477 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10954 12:48:25.433031 /lava-11118917/1/../bin/lava-test-case
10955 12:48:25.439308 <8>[ 19.201195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10956 12:48:25.439559 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10958 12:48:25.448653 /lava-11118917/1/../bin/lava-test-case
10959 12:48:25.455085 <8>[ 19.216988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10960 12:48:25.455336 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10962 12:48:25.467118 /lava-11118917/1/../bin/lava-test-case
10963 12:48:25.473715 <8>[ 19.235514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10964 12:48:25.473996 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10966 12:48:25.482626 /lava-11118917/1/../bin/lava-test-case
10967 12:48:25.489190 <8>[ 19.251152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10968 12:48:25.489447 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10970 12:48:25.501049 /lava-11118917/1/../bin/lava-test-case
10971 12:48:25.507548 <8>[ 19.268585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10972 12:48:25.507803 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10974 12:48:25.516628 /lava-11118917/1/../bin/lava-test-case
10975 12:48:25.523164 <8>[ 19.284951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10976 12:48:25.523419 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10978 12:48:25.535388 /lava-11118917/1/../bin/lava-test-case
10979 12:48:25.541767 <8>[ 19.303405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10980 12:48:25.542024 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10982 12:48:25.553883 /lava-11118917/1/../bin/lava-test-case
10983 12:48:25.560491 <8>[ 19.322152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10984 12:48:25.560762 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10986 12:48:25.569488 /lava-11118917/1/../bin/lava-test-case
10987 12:48:25.576090 <8>[ 19.337522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10988 12:48:25.576347 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10990 12:48:25.588142 /lava-11118917/1/../bin/lava-test-case
10991 12:48:25.594748 <8>[ 19.356484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10992 12:48:25.595003 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10994 12:48:25.604529 /lava-11118917/1/../bin/lava-test-case
10995 12:48:25.610932 <8>[ 19.372998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10996 12:48:25.611190 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10998 12:48:25.623515 /lava-11118917/1/../bin/lava-test-case
10999 12:48:25.630630 <8>[ 19.391637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11000 12:48:25.630884 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11002 12:48:25.641506 /lava-11118917/1/../bin/lava-test-case
11003 12:48:25.648084 <8>[ 19.409803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11004 12:48:25.648338 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11006 12:48:25.660637 /lava-11118917/1/../bin/lava-test-case
11007 12:48:25.666815 <8>[ 19.428994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11008 12:48:25.667071 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11010 12:48:25.679731 /lava-11118917/1/../bin/lava-test-case
11011 12:48:25.686440 <8>[ 19.448439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11012 12:48:25.686734 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11014 12:48:25.696593 /lava-11118917/1/../bin/lava-test-case
11015 12:48:25.703209 <8>[ 19.465053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11016 12:48:25.703464 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11018 12:48:25.715772 /lava-11118917/1/../bin/lava-test-case
11019 12:48:25.722290 <8>[ 19.483669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11020 12:48:25.722543 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11022 12:48:25.733654 /lava-11118917/1/../bin/lava-test-case
11023 12:48:25.740404 <8>[ 19.502192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11024 12:48:25.740686 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11026 12:48:25.749377 /lava-11118917/1/../bin/lava-test-case
11027 12:48:25.756066 <8>[ 19.517922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11028 12:48:25.756319 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11030 12:48:25.768327 /lava-11118917/1/../bin/lava-test-case
11031 12:48:25.774701 <8>[ 19.536667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11032 12:48:25.774970 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11034 12:48:25.784470 /lava-11118917/1/../bin/lava-test-case
11035 12:48:25.791178 <8>[ 19.552933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11036 12:48:25.791438 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11038 12:48:25.803580 /lava-11118917/1/../bin/lava-test-case
11039 12:48:25.810153 <8>[ 19.572177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11040 12:48:25.810405 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11042 12:48:25.819962 /lava-11118917/1/../bin/lava-test-case
11043 12:48:25.826526 <8>[ 19.588223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11044 12:48:25.826783 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11046 12:48:25.838774 /lava-11118917/1/../bin/lava-test-case
11047 12:48:25.845512 <8>[ 19.606987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11048 12:48:25.845764 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11050 12:48:25.854945 /lava-11118917/1/../bin/lava-test-case
11051 12:48:25.861863 <8>[ 19.623824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11052 12:48:25.862117 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11054 12:48:25.875035 /lava-11118917/1/../bin/lava-test-case
11055 12:48:25.881635 <8>[ 19.643332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11056 12:48:25.881890 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11058 12:48:25.891524 /lava-11118917/1/../bin/lava-test-case
11059 12:48:25.897987 <8>[ 19.659928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11060 12:48:25.898242 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11062 12:48:25.910177 /lava-11118917/1/../bin/lava-test-case
11063 12:48:25.916409 <8>[ 19.678593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11064 12:48:25.916663 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11066 12:48:25.925658 /lava-11118917/1/../bin/lava-test-case
11067 12:48:25.932251 <8>[ 19.694356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11068 12:48:25.932511 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11070 12:48:25.944148 /lava-11118917/1/../bin/lava-test-case
11071 12:48:25.951033 <8>[ 19.712541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11072 12:48:25.951315 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11074 12:48:25.959960 /lava-11118917/1/../bin/lava-test-case
11075 12:48:25.966437 <8>[ 19.728292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11076 12:48:25.966707 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11078 12:48:25.979151 /lava-11118917/1/../bin/lava-test-case
11079 12:48:25.985628 <8>[ 19.747306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11080 12:48:25.985885 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11082 12:48:25.997000 /lava-11118917/1/../bin/lava-test-case
11083 12:48:26.003951 <8>[ 19.765627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11084 12:48:26.004204 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11086 12:48:26.013172 /lava-11118917/1/../bin/lava-test-case
11087 12:48:26.020075 <8>[ 19.781182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11088 12:48:26.020328 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11090 12:48:26.031799 /lava-11118917/1/../bin/lava-test-case
11091 12:48:26.038346 <8>[ 19.799640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11092 12:48:26.038600 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11094 12:48:26.047589 /lava-11118917/1/../bin/lava-test-case
11095 12:48:26.053785 <8>[ 19.815803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11096 12:48:26.054039 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11098 12:48:26.065942 /lava-11118917/1/../bin/lava-test-case
11099 12:48:26.072199 <8>[ 19.833975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11100 12:48:26.072452 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11102 12:48:26.082962 /lava-11118917/1/../bin/lava-test-case
11103 12:48:26.089471 <8>[ 19.851213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11104 12:48:26.089877 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11106 12:48:26.100784 /lava-11118917/1/../bin/lava-test-case
11107 12:48:26.107517 <8>[ 19.868729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11108 12:48:26.107771 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11110 12:48:26.118260 /lava-11118917/1/../bin/lava-test-case
11111 12:48:26.124895 <8>[ 19.886920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11112 12:48:26.125144 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11114 12:48:26.136364 /lava-11118917/1/../bin/lava-test-case
11115 12:48:26.142689 <8>[ 19.904676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11116 12:48:26.142940 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11118 12:48:26.151614 /lava-11118917/1/../bin/lava-test-case
11119 12:48:26.157938 <8>[ 19.919620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11120 12:48:26.158190 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11122 12:48:26.169379 /lava-11118917/1/../bin/lava-test-case
11123 12:48:26.175965 <8>[ 19.937848] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11124 12:48:26.176266 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11126 12:48:26.186893 /lava-11118917/1/../bin/lava-test-case
11127 12:48:26.193960 <8>[ 19.955232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11128 12:48:26.194212 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11130 12:48:26.201680 /lava-11118917/1/../bin/lava-test-case
11131 12:48:26.208134 <8>[ 19.969901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11132 12:48:26.208412 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11134 12:48:26.219879 /lava-11118917/1/../bin/lava-test-case
11135 12:48:26.226654 <8>[ 19.988147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11136 12:48:26.226904 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11138 12:48:26.235340 /lava-11118917/1/../bin/lava-test-case
11139 12:48:26.241996 <8>[ 20.003886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11140 12:48:26.242247 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11142 12:48:26.253170 /lava-11118917/1/../bin/lava-test-case
11143 12:48:26.259815 <8>[ 20.021651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11144 12:48:26.260176 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11146 12:48:26.268655 /lava-11118917/1/../bin/lava-test-case
11147 12:48:26.275330 <8>[ 20.037493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11148 12:48:26.275641 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11150 12:48:26.288043 /lava-11118917/1/../bin/lava-test-case
11151 12:48:26.294456 <8>[ 20.055921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11152 12:48:26.294710 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11154 12:48:26.305688 /lava-11118917/1/../bin/lava-test-case
11155 12:48:26.312171 <8>[ 20.074156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11156 12:48:26.312421 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11158 12:48:26.322640 /lava-11118917/1/../bin/lava-test-case
11159 12:48:26.329512 <8>[ 20.091556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11160 12:48:26.329764 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11162 12:48:26.341499 /lava-11118917/1/../bin/lava-test-case
11163 12:48:26.347580 <8>[ 20.109338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11164 12:48:26.347830 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11166 12:48:26.359307 /lava-11118917/1/../bin/lava-test-case
11167 12:48:26.365646 <8>[ 20.127764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11168 12:48:26.365896 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11170 12:48:26.376730 /lava-11118917/1/../bin/lava-test-case
11171 12:48:26.383393 <8>[ 20.145075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11172 12:48:26.383643 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11174 12:48:26.393616 /lava-11118917/1/../bin/lava-test-case
11175 12:48:26.400307 <8>[ 20.162515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11176 12:48:26.400566 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11178 12:48:26.412068 /lava-11118917/1/../bin/lava-test-case
11179 12:48:26.418600 <8>[ 20.180520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11180 12:48:26.418852 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11182 12:48:26.430329 /lava-11118917/1/../bin/lava-test-case
11183 12:48:26.437142 <8>[ 20.198408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11184 12:48:26.437393 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11186 12:48:26.447938 /lava-11118917/1/../bin/lava-test-case
11187 12:48:26.454478 <8>[ 20.216509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11188 12:48:26.454728 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11190 12:48:26.466910 /lava-11118917/1/../bin/lava-test-case
11191 12:48:26.473284 <8>[ 20.234987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11192 12:48:26.473534 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11194 12:48:26.485209 /lava-11118917/1/../bin/lava-test-case
11195 12:48:26.491338 <8>[ 20.253129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11196 12:48:26.491628 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11198 12:48:26.502648 /lava-11118917/1/../bin/lava-test-case
11199 12:48:26.509302 <8>[ 20.270804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11200 12:48:26.509555 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11202 12:48:26.520921 /lava-11118917/1/../bin/lava-test-case
11203 12:48:26.527395 <8>[ 20.289023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11204 12:48:26.527650 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11206 12:48:26.539055 /lava-11118917/1/../bin/lava-test-case
11207 12:48:26.545619 <8>[ 20.307733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11208 12:48:26.545872 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11210 12:48:26.555078 /lava-11118917/1/../bin/lava-test-case
11211 12:48:26.561536 <8>[ 20.323939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11212 12:48:26.561789 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11214 12:48:26.573923 /lava-11118917/1/../bin/lava-test-case
11215 12:48:26.580566 <8>[ 20.342768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11216 12:48:26.580831 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11218 12:48:26.589866 /lava-11118917/1/../bin/lava-test-case
11219 12:48:26.596339 <8>[ 20.358139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11220 12:48:26.596593 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11222 12:48:26.608478 /lava-11118917/1/../bin/lava-test-case
11223 12:48:26.614688 <8>[ 20.376826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11224 12:48:26.614943 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11226 12:48:26.624585 /lava-11118917/1/../bin/lava-test-case
11227 12:48:26.630860 <8>[ 20.392845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11228 12:48:26.631115 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11230 12:48:26.643899 /lava-11118917/1/../bin/lava-test-case
11231 12:48:26.649978 <8>[ 20.412357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11232 12:48:26.650231 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11234 12:48:26.659755 /lava-11118917/1/../bin/lava-test-case
11235 12:48:26.666417 <8>[ 20.428386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11236 12:48:26.666672 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11238 12:48:26.679098 /lava-11118917/1/../bin/lava-test-case
11239 12:48:26.685392 <8>[ 20.447220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11240 12:48:26.685645 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11242 12:48:26.695225 /lava-11118917/1/../bin/lava-test-case
11243 12:48:26.701526 <8>[ 20.463163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11244 12:48:26.701783 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11246 12:48:26.713631 /lava-11118917/1/../bin/lava-test-case
11247 12:48:26.719996 <8>[ 20.482205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11248 12:48:26.720251 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11250 12:48:26.729137 /lava-11118917/1/../bin/lava-test-case
11251 12:48:26.735686 <8>[ 20.497635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11252 12:48:26.735942 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11254 12:48:26.747988 /lava-11118917/1/../bin/lava-test-case
11255 12:48:26.754493 <8>[ 20.516143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11256 12:48:26.754748 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11258 12:48:26.766405 /lava-11118917/1/../bin/lava-test-case
11259 12:48:26.772912 <8>[ 20.534761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11260 12:48:26.773165 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11262 12:48:26.782851 /lava-11118917/1/../bin/lava-test-case
11263 12:48:26.789128 <8>[ 20.551405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11264 12:48:26.789383 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11266 12:48:26.801577 /lava-11118917/1/../bin/lava-test-case
11267 12:48:26.808222 <8>[ 20.569657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11268 12:48:26.808476 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11270 12:48:26.817296 /lava-11118917/1/../bin/lava-test-case
11271 12:48:26.823908 <8>[ 20.585762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11272 12:48:26.824162 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11274 12:48:26.835198 /lava-11118917/1/../bin/lava-test-case
11275 12:48:26.841600 <8>[ 20.603891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11276 12:48:26.841853 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11278 12:48:26.850605 /lava-11118917/1/../bin/lava-test-case
11279 12:48:26.856903 <8>[ 20.619283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11280 12:48:26.857157 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11282 12:48:27.871068 /lava-11118917/1/../bin/lava-test-case
11283 12:48:27.877375 <8>[ 21.640269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11284 12:48:27.877670 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11286 12:48:27.887476 /lava-11118917/1/../bin/lava-test-case
11287 12:48:27.893913 <8>[ 21.656266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11288 12:48:27.894189 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11290 12:48:28.907946 /lava-11118917/1/../bin/lava-test-case
11291 12:48:28.914503 <8>[ 22.677158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11292 12:48:28.914828 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11294 12:48:28.924105 /lava-11118917/1/../bin/lava-test-case
11295 12:48:28.930691 <8>[ 22.693033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11296 12:48:28.931029 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11298 12:48:29.945530 /lava-11118917/1/../bin/lava-test-case
11299 12:48:29.951997 <8>[ 23.714772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11300 12:48:29.952271 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11302 12:48:29.962694 /lava-11118917/1/../bin/lava-test-case
11303 12:48:29.968970 <8>[ 23.731617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11304 12:48:29.969276 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11306 12:48:30.982930 /lava-11118917/1/../bin/lava-test-case
11307 12:48:30.989270 <8>[ 24.752280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11308 12:48:30.989565 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11310 12:48:30.998895 /lava-11118917/1/../bin/lava-test-case
11311 12:48:31.005295 <8>[ 24.767630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11312 12:48:31.005742 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11314 12:48:32.019135 /lava-11118917/1/../bin/lava-test-case
11315 12:48:32.025438 <8>[ 25.788949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11316 12:48:32.025704 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11318 12:48:32.035626 /lava-11118917/1/../bin/lava-test-case
11319 12:48:32.042216 <8>[ 25.804741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11320 12:48:32.042470 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11322 12:48:33.057193 /lava-11118917/1/../bin/lava-test-case
11323 12:48:33.063640 <8>[ 26.826988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11324 12:48:33.063955 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11326 12:48:33.074014 /lava-11118917/1/../bin/lava-test-case
11327 12:48:33.081075 <8>[ 26.844096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11328 12:48:33.081335 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11330 12:48:34.095050 /lava-11118917/1/../bin/lava-test-case
11331 12:48:34.101509 <8>[ 27.864672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11332 12:48:34.101782 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11334 12:48:34.111419 /lava-11118917/1/../bin/lava-test-case
11335 12:48:34.117994 <8>[ 27.881250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11336 12:48:34.118252 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11338 12:48:34.127608 /lava-11118917/1/../bin/lava-test-case
11339 12:48:34.134272 <8>[ 27.896961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11340 12:48:34.134530 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11342 12:48:35.148196 /lava-11118917/1/../bin/lava-test-case
11343 12:48:35.154687 <8>[ 28.917923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11344 12:48:35.154949 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11346 12:48:35.164663 /lava-11118917/1/../bin/lava-test-case
11347 12:48:35.171476 <8>[ 28.934441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11348 12:48:35.171729 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11350 12:48:35.182569 /lava-11118917/1/../bin/lava-test-case
11351 12:48:35.189164 <8>[ 28.952346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11352 12:48:35.189416 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11354 12:48:35.198362 /lava-11118917/1/../bin/lava-test-case
11355 12:48:35.205188 <8>[ 28.968034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11356 12:48:35.205441 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11358 12:48:35.218002 /lava-11118917/1/../bin/lava-test-case
11359 12:48:35.224390 <8>[ 28.987000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11360 12:48:35.224643 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11362 12:48:35.235675 /lava-11118917/1/../bin/lava-test-case
11363 12:48:35.241972 <8>[ 29.005052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11364 12:48:35.242224 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11366 12:48:35.254551 /lava-11118917/1/../bin/lava-test-case
11367 12:48:35.260988 <8>[ 29.023974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11368 12:48:35.261240 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11370 12:48:35.271359 /lava-11118917/1/../bin/lava-test-case
11371 12:48:35.277605 <8>[ 29.040415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11372 12:48:35.277862 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11374 12:48:35.290170 /lava-11118917/1/../bin/lava-test-case
11375 12:48:35.296929 <8>[ 29.059516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11376 12:48:35.297235 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11378 12:48:35.309026 /lava-11118917/1/../bin/lava-test-case
11379 12:48:35.315463 <8>[ 29.078164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11380 12:48:35.315770 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11382 12:48:35.324808 /lava-11118917/1/../bin/lava-test-case
11383 12:48:35.331551 <8>[ 29.094709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11384 12:48:35.331856 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11386 12:48:35.344081 /lava-11118917/1/../bin/lava-test-case
11387 12:48:35.350448 <8>[ 29.113341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11388 12:48:35.350752 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11390 12:48:35.360050 /lava-11118917/1/../bin/lava-test-case
11391 12:48:35.366677 <8>[ 29.129610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11392 12:48:35.366980 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11394 12:48:35.379575 /lava-11118917/1/../bin/lava-test-case
11395 12:48:35.386043 <8>[ 29.148976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11396 12:48:35.386320 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11398 12:48:35.396177 /lava-11118917/1/../bin/lava-test-case
11399 12:48:35.402946 <8>[ 29.165429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11400 12:48:35.403204 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11402 12:48:35.415662 /lava-11118917/1/../bin/lava-test-case
11403 12:48:35.422507 <8>[ 29.185311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11404 12:48:35.422760 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11406 12:48:35.431564 /lava-11118917/1/../bin/lava-test-case
11407 12:48:35.438274 <8>[ 29.201104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11408 12:48:35.438527 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11410 12:48:35.450994 /lava-11118917/1/../bin/lava-test-case
11411 12:48:35.457404 <8>[ 29.220078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11412 12:48:35.457659 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11414 12:48:35.466823 /lava-11118917/1/../bin/lava-test-case
11415 12:48:35.473146 <8>[ 29.236424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11416 12:48:35.473400 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11418 12:48:35.485697 /lava-11118917/1/../bin/lava-test-case
11419 12:48:35.492354 <8>[ 29.255290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11420 12:48:35.492628 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11422 12:48:35.501664 /lava-11118917/1/../bin/lava-test-case
11423 12:48:35.508059 <8>[ 29.271122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11424 12:48:35.508368 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11426 12:48:36.522467 /lava-11118917/1/../bin/lava-test-case
11427 12:48:36.528911 <8>[ 30.292846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11428 12:48:36.529230 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11430 12:48:37.543922 /lava-11118917/1/../bin/lava-test-case
11431 12:48:37.550132 <8>[ 31.314472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11432 12:48:37.550450 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11434 12:48:37.559980 /lava-11118917/1/../bin/lava-test-case
11435 12:48:37.566667 <8>[ 31.329581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11436 12:48:37.566942 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11438 12:48:37.577897 /lava-11118917/1/../bin/lava-test-case
11439 12:48:37.583880 <8>[ 31.347515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11440 12:48:37.584133 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11442 12:48:37.593019 /lava-11118917/1/../bin/lava-test-case
11443 12:48:37.599107 <8>[ 31.362465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11444 12:48:37.599360 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11446 12:48:37.610380 /lava-11118917/1/../bin/lava-test-case
11447 12:48:37.616883 <8>[ 31.380656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11448 12:48:37.617135 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11450 12:48:37.626388 /lava-11118917/1/../bin/lava-test-case
11451 12:48:37.633060 <8>[ 31.396157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11452 12:48:37.633313 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11454 12:48:37.643431 /lava-11118917/1/../bin/lava-test-case
11455 12:48:37.650531 <8>[ 31.412952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11456 12:48:37.650783 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11458 12:48:37.658828 /lava-11118917/1/../bin/lava-test-case
11459 12:48:37.665433 <8>[ 31.428406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11460 12:48:37.665685 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11462 12:48:37.677171 /lava-11118917/1/../bin/lava-test-case
11463 12:48:37.683585 <8>[ 31.446512] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11464 12:48:37.683837 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11466 12:48:37.689687 /lava-11118917/1/../bin/lava-test-case
11467 12:48:37.699278 <8>[ 31.462166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11468 12:48:37.699532 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11470 12:48:37.711486 /lava-11118917/1/../bin/lava-test-case
11471 12:48:37.717858 <8>[ 31.481226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11472 12:48:37.718109 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11474 12:48:37.727131 /lava-11118917/1/../bin/lava-test-case
11475 12:48:37.733190 <8>[ 31.496650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11476 12:48:37.733443 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11478 12:48:37.745376 /lava-11118917/1/../bin/lava-test-case
11479 12:48:37.751626 <8>[ 31.514641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11480 12:48:37.751907 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11482 12:48:37.759858 /lava-11118917/1/../bin/lava-test-case
11483 12:48:37.766555 <8>[ 31.530212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11484 12:48:37.766809 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11486 12:48:37.778860 /lava-11118917/1/../bin/lava-test-case
11487 12:48:37.785016 <8>[ 31.548773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11488 12:48:37.785269 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11490 12:48:37.793997 /lava-11118917/1/../bin/lava-test-case
11491 12:48:37.800638 <8>[ 31.563900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11492 12:48:37.800918 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11494 12:48:37.811913 /lava-11118917/1/../bin/lava-test-case
11495 12:48:37.818653 <8>[ 31.581851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11496 12:48:37.818908 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11498 12:48:37.827260 /lava-11118917/1/../bin/lava-test-case
11499 12:48:37.834134 <8>[ 31.597091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11500 12:48:37.834387 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11502 12:48:37.845135 /lava-11118917/1/../bin/lava-test-case
11503 12:48:37.851710 <8>[ 31.614672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11504 12:48:37.851963 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11506 12:48:37.860136 /lava-11118917/1/../bin/lava-test-case
11507 12:48:37.866981 <8>[ 31.630100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11508 12:48:37.867233 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11510 12:48:37.879478 /lava-11118917/1/../bin/lava-test-case
11511 12:48:37.886074 <8>[ 31.648795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11512 12:48:37.886327 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11514 12:48:38.897364 /lava-11118917/1/../bin/lava-test-case
11515 12:48:38.904392 <8>[ 32.668516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11516 12:48:38.904723 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11518 12:48:39.917736 /lava-11118917/1/../bin/lava-test-case
11519 12:48:39.924060 <8>[ 33.687862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11520 12:48:39.924369 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11521 12:48:39.924492 Bad test result: blocked
11522 12:48:39.934158 /lava-11118917/1/../bin/lava-test-case
11523 12:48:39.940792 <8>[ 33.704776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11524 12:48:39.941048 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11526 12:48:40.955435 /lava-11118917/1/../bin/lava-test-case
11527 12:48:40.962182 <8>[ 34.726568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11528 12:48:40.962468 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11530 12:48:40.972008 /lava-11118917/1/../bin/lava-test-case
11531 12:48:40.978686 <8>[ 34.742383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11532 12:48:40.978944 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11534 12:48:40.989896 /lava-11118917/1/../bin/lava-test-case
11535 12:48:40.996401 <8>[ 34.760203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11536 12:48:40.996658 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11538 12:48:41.007129 /lava-11118917/1/../bin/lava-test-case
11539 12:48:41.014023 <8>[ 34.777921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11540 12:48:41.014280 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11542 12:48:41.023497 /lava-11118917/1/../bin/lava-test-case
11543 12:48:41.029924 <8>[ 34.793219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11544 12:48:41.030180 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11546 12:48:41.042127 /lava-11118917/1/../bin/lava-test-case
11547 12:48:41.048745 <8>[ 34.812274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11548 12:48:41.049005 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11550 12:48:41.057645 /lava-11118917/1/../bin/lava-test-case
11551 12:48:41.064303 <8>[ 34.828197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11552 12:48:41.064555 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11554 12:48:42.078386 /lava-11118917/1/../bin/lava-test-case
11555 12:48:42.085304 <8>[ 35.849490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11556 12:48:42.085571 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11558 12:48:42.094945 /lava-11118917/1/../bin/lava-test-case
11559 12:48:42.101331 <8>[ 35.865598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11560 12:48:42.101584 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11562 12:48:43.115808 /lava-11118917/1/../bin/lava-test-case
11563 12:48:43.122255 <8>[ 36.887101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11564 12:48:43.122525 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11566 12:48:43.131759 /lava-11118917/1/../bin/lava-test-case
11567 12:48:43.138248 <8>[ 36.901984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11568 12:48:43.138501 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11570 12:48:44.151752 /lava-11118917/1/../bin/lava-test-case
11571 12:48:44.157980 <8>[ 37.923022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11572 12:48:44.158273 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11574 12:48:44.168269 /lava-11118917/1/../bin/lava-test-case
11575 12:48:44.174656 <8>[ 37.938301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11576 12:48:44.174917 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11578 12:48:45.188760 /lava-11118917/1/../bin/lava-test-case
11579 12:48:45.195429 <8>[ 38.960474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11580 12:48:45.195692 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11582 12:48:45.205504 /lava-11118917/1/../bin/lava-test-case
11583 12:48:45.212080 <8>[ 38.976486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11584 12:48:45.212339 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11586 12:48:45.222764 /lava-11118917/1/../bin/lava-test-case
11587 12:48:45.229067 <8>[ 38.993715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11588 12:48:45.229322 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11590 12:48:45.239384 /lava-11118917/1/../bin/lava-test-case
11591 12:48:45.246364 <8>[ 39.010411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11592 12:48:45.246620 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11594 12:48:45.254308 /lava-11118917/1/../bin/lava-test-case
11595 12:48:45.260781 <8>[ 39.025257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11596 12:48:45.261033 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11598 12:48:45.272981 /lava-11118917/1/../bin/lava-test-case
11599 12:48:45.279414 <8>[ 39.043457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11600 12:48:45.279697 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11602 12:48:45.287695 /lava-11118917/1/../bin/lava-test-case
11603 12:48:45.294404 <8>[ 39.058154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11604 12:48:45.294656 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11606 12:48:45.306855 /lava-11118917/1/../bin/lava-test-case
11607 12:48:45.313422 <8>[ 39.077026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11608 12:48:45.313692 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11610 12:48:45.322451 /lava-11118917/1/../bin/lava-test-case
11611 12:48:45.329244 <8>[ 39.093322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11612 12:48:45.329497 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11614 12:48:46.343656 /lava-11118917/1/../bin/lava-test-case
11615 12:48:46.350512 <8>[ 40.115514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11616 12:48:46.350778 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11618 12:48:46.354895 + set +x
11619 12:48:46.358179 Received signal: <ENDRUN> 1_bootrr 11118917_1.5.2.3.5
11620 12:48:46.358268 Ending use of test pattern.
11621 12:48:46.358335 Ending test lava.1_bootrr (11118917_1.5.2.3.5), duration 21.30
11623 12:48:46.361413 <8>[ 40.125473] <LAVA_SIGNAL_ENDRUN 1_bootrr 11118917_1.5.2.3.5>
11624 12:48:46.361496 <LAVA_TEST_RUNNER EXIT>
11625 12:48:46.361728 ok: lava_test_shell seems to have completed
11626 12:48:46.362705 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11627 12:48:46.362849 end: 4.1 lava-test-shell (duration 00:00:22) [common]
11628 12:48:46.362934 end: 4 lava-test-retry (duration 00:00:22) [common]
11629 12:48:46.363042 start: 5 finalize (timeout 00:07:56) [common]
11630 12:48:46.363142 start: 5.1 power-off (timeout 00:00:30) [common]
11631 12:48:46.363294 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11632 12:48:46.438690 >> Command sent successfully.
11633 12:48:46.441083 Returned 0 in 0 seconds
11634 12:48:46.541440 end: 5.1 power-off (duration 00:00:00) [common]
11636 12:48:46.541765 start: 5.2 read-feedback (timeout 00:07:55) [common]
11637 12:48:46.542021 Listened to connection for namespace 'common' for up to 1s
11638 12:48:46.542301 Listened to connection for namespace 'common' for up to 1s
11639 12:48:47.542980 Finalising connection for namespace 'common'
11640 12:48:47.543181 Disconnecting from shell: Finalise
11641 12:48:47.543288 / #
11642 12:48:47.643601 end: 5.2 read-feedback (duration 00:00:01) [common]
11643 12:48:47.643745 end: 5 finalize (duration 00:00:01) [common]
11644 12:48:47.643852 Cleaning after the job
11645 12:48:47.643952 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/ramdisk
11646 12:48:47.646347 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/kernel
11647 12:48:47.652384 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/dtb
11648 12:48:47.652549 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11118917/tftp-deploy-8e110p6p/modules
11649 12:48:47.657941 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11118917
11650 12:48:47.695092 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11118917
11651 12:48:47.695272 Job finished correctly